1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
31 #include <linux/bitops.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/cpumask.h>
36 #include <linux/aer.h>
37 #include <linux/if_vlan.h>
39 #include "ixgbe_type.h"
40 #include "ixgbe_common.h"
41 #include "ixgbe_dcb.h"
42 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
44 #include "ixgbe_fcoe.h"
45 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
46 #ifdef CONFIG_IXGBE_DCA
47 #include <linux/dca.h>
50 /* common prefix used by pr_<> macros */
52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
54 /* TX/RX descriptor defines */
55 #define IXGBE_DEFAULT_TXD 512
56 #define IXGBE_DEFAULT_TX_WORK 256
57 #define IXGBE_MAX_TXD 4096
58 #define IXGBE_MIN_TXD 64
60 #define IXGBE_DEFAULT_RXD 512
61 #define IXGBE_MAX_RXD 4096
62 #define IXGBE_MIN_RXD 64
65 #define IXGBE_MIN_FCRTL 0x40
66 #define IXGBE_MAX_FCRTL 0x7FF80
67 #define IXGBE_MIN_FCRTH 0x600
68 #define IXGBE_MAX_FCRTH 0x7FFF0
69 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
70 #define IXGBE_MIN_FCPAUSE 0
71 #define IXGBE_MAX_FCPAUSE 0xFFFF
73 /* Supported Rx Buffer Sizes */
74 #define IXGBE_RXBUFFER_512 512 /* Used for packet split */
75 #define IXGBE_RXBUFFER_2K 2048
76 #define IXGBE_RXBUFFER_3K 3072
77 #define IXGBE_RXBUFFER_4K 4096
78 #define IXGBE_RXBUFFER_7K 7168
79 #define IXGBE_RXBUFFER_8K 8192
80 #define IXGBE_RXBUFFER_15K 15360
81 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
84 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
85 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
86 * this adds up to 512 bytes of extra data meaning the smallest allocation
87 * we could have is 1K.
88 * i.e. RXBUFFER_512 --> size-1024 slab
90 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
92 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
94 /* How many Rx Buffers do we bundle into one write to the hardware ? */
95 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
97 #define IXGBE_TX_FLAGS_CSUM (u32)(1)
98 #define IXGBE_TX_FLAGS_HW_VLAN (u32)(1 << 1)
99 #define IXGBE_TX_FLAGS_SW_VLAN (u32)(1 << 2)
100 #define IXGBE_TX_FLAGS_TSO (u32)(1 << 3)
101 #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 4)
102 #define IXGBE_TX_FLAGS_FCOE (u32)(1 << 5)
103 #define IXGBE_TX_FLAGS_FSO (u32)(1 << 6)
104 #define IXGBE_TX_FLAGS_TXSW (u32)(1 << 7)
105 #define IXGBE_TX_FLAGS_MAPPED_AS_PAGE (u32)(1 << 8)
106 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
107 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
108 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
109 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
111 #define IXGBE_MAX_RSC_INT_RATE 162760
113 #define IXGBE_MAX_VF_MC_ENTRIES 30
114 #define IXGBE_MAX_VF_FUNCTIONS 64
115 #define IXGBE_MAX_VFTA_ENTRIES 128
116 #define MAX_EMULATION_MAC_ADDRS 16
117 #define IXGBE_MAX_PF_MACVLANS 15
118 #define VMDQ_P(p) ((p) + adapter->num_vfs)
119 #define IXGBE_82599_VF_DEVICE_ID 0x10ED
120 #define IXGBE_X540_VF_DEVICE_ID 0x1515
122 struct vf_data_storage
{
123 unsigned char vf_mac_addresses
[ETH_ALEN
];
124 u16 vf_mc_hashes
[IXGBE_MAX_VF_MC_ENTRIES
];
125 u16 num_vf_mc_hashes
;
126 u16 default_vf_vlan_id
;
130 u16 pf_vlan
; /* When set, guest VLAN config not allowed. */
133 struct pci_dev
*vfdev
;
142 u8 vf_macvlan
[ETH_ALEN
];
145 #define IXGBE_MAX_TXD_PWR 14
146 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
148 /* Tx Descriptors needed, worst case */
149 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
150 #define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
152 /* wrapper around a pointer to a socket buffer,
153 * so a DMA handle can be stored along with the buffer */
154 struct ixgbe_tx_buffer
{
155 union ixgbe_adv_tx_desc
*next_to_watch
;
156 unsigned long time_stamp
;
165 struct ixgbe_rx_buffer
{
170 unsigned int page_offset
;
173 struct ixgbe_queue_stats
{
178 struct ixgbe_tx_queue_stats
{
185 struct ixgbe_rx_queue_stats
{
189 u64 alloc_rx_page_failed
;
190 u64 alloc_rx_buff_failed
;
193 enum ixbge_ring_state_t
{
194 __IXGBE_TX_FDIR_INIT_DONE
,
195 __IXGBE_TX_DETECT_HANG
,
196 __IXGBE_HANG_CHECK_ARMED
,
197 __IXGBE_RX_PS_ENABLED
,
198 __IXGBE_RX_RSC_ENABLED
,
201 #define ring_is_ps_enabled(ring) \
202 test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
203 #define set_ring_ps_enabled(ring) \
204 set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
205 #define clear_ring_ps_enabled(ring) \
206 clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
207 #define check_for_tx_hang(ring) \
208 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
209 #define set_check_for_tx_hang(ring) \
210 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
211 #define clear_check_for_tx_hang(ring) \
212 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
213 #define ring_is_rsc_enabled(ring) \
214 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
215 #define set_ring_rsc_enabled(ring) \
216 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
217 #define clear_ring_rsc_enabled(ring) \
218 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
220 struct ixgbe_ring
*next
; /* pointer to next ring in q_vector */
221 void *desc
; /* descriptor ring memory */
222 struct device
*dev
; /* device for DMA mapping */
223 struct net_device
*netdev
; /* netdev ring belongs to */
225 struct ixgbe_tx_buffer
*tx_buffer_info
;
226 struct ixgbe_rx_buffer
*rx_buffer_info
;
231 u16 count
; /* amount of descriptors */
234 u8 queue_index
; /* needed for multiqueue queue management */
235 u8 reg_idx
; /* holds the special value that gets
236 * the hardware register offset
237 * associated with this ring, which is
238 * different for DCB and RSS modes
247 struct ixgbe_queue_stats stats
;
248 struct u64_stats_sync syncp
;
250 struct ixgbe_tx_queue_stats tx_stats
;
251 struct ixgbe_rx_queue_stats rx_stats
;
254 unsigned int size
; /* length in bytes */
255 dma_addr_t dma
; /* phys. address of descriptor ring */
257 struct ixgbe_q_vector
*q_vector
; /* back-pointer to host q_vector */
258 } ____cacheline_internodealigned_in_smp
;
260 enum ixgbe_ring_f_enum
{
262 RING_F_VMDQ
, /* SR-IOV uses the same ring feature */
267 #endif /* IXGBE_FCOE */
269 RING_F_ARRAY_SIZE
/* must be last in enum set */
272 #define IXGBE_MAX_RSS_INDICES 16
273 #define IXGBE_MAX_VMDQ_INDICES 64
274 #define IXGBE_MAX_FDIR_INDICES 64
276 #define IXGBE_MAX_FCOE_INDICES 8
277 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
278 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
280 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
281 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
282 #endif /* IXGBE_FCOE */
283 struct ixgbe_ring_feature
{
286 } ____cacheline_internodealigned_in_smp
;
288 struct ixgbe_ring_container
{
289 struct ixgbe_ring
*ring
; /* pointer to linked list of rings */
290 unsigned int total_bytes
; /* total bytes processed this int */
291 unsigned int total_packets
; /* total packets processed this int */
292 u16 work_limit
; /* total work allowed per interrupt */
293 u8 count
; /* total number of rings in vector */
294 u8 itr
; /* current ITR setting for ring */
297 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
299 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
301 /* MAX_MSIX_Q_VECTORS of these are allocated,
302 * but we only use one per queue-specific vector.
304 struct ixgbe_q_vector
{
305 struct ixgbe_adapter
*adapter
;
306 #ifdef CONFIG_IXGBE_DCA
307 int cpu
; /* CPU for DCA */
309 u16 v_idx
; /* index of q_vector within array, also used for
310 * finding the bit in EICR and friends that
311 * represents the vector for this ring */
312 u16 itr
; /* Interrupt throttle rate written to EITR */
313 struct ixgbe_ring_container rx
, tx
;
315 struct napi_struct napi
;
316 cpumask_var_t affinity_mask
;
317 char name
[IFNAMSIZ
+ 9];
321 * microsecond values for various ITR rates shifted by 2 to fit itr register
322 * with the first 3 bits reserved 0
324 #define IXGBE_MIN_RSC_ITR 24
325 #define IXGBE_100K_ITR 40
326 #define IXGBE_20K_ITR 200
327 #define IXGBE_10K_ITR 400
328 #define IXGBE_8K_ITR 500
330 static inline u16
ixgbe_desc_unused(struct ixgbe_ring
*ring
)
332 u16 ntc
= ring
->next_to_clean
;
333 u16 ntu
= ring
->next_to_use
;
335 return ((ntc
> ntu
) ? 0 : ring
->count
) + ntc
- ntu
- 1;
338 #define IXGBE_RX_DESC_ADV(R, i) \
339 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
340 #define IXGBE_TX_DESC_ADV(R, i) \
341 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
342 #define IXGBE_TX_CTXTDESC_ADV(R, i) \
343 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
345 #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
347 /* Use 3K as the baby jumbo frame size for FCoE */
348 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
349 #endif /* IXGBE_FCOE */
351 #define OTHER_VECTOR 1
352 #define NON_Q_VECTORS (OTHER_VECTOR)
354 #define MAX_MSIX_VECTORS_82599 64
355 #define MAX_MSIX_Q_VECTORS_82599 64
356 #define MAX_MSIX_VECTORS_82598 18
357 #define MAX_MSIX_Q_VECTORS_82598 16
359 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
360 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
362 #define MIN_MSIX_Q_VECTORS 2
363 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
365 /* board specific private data structure */
366 struct ixgbe_adapter
{
369 /* Some features need tri-state capability,
370 * thus the additional *_CAPABLE flags.
373 #define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
374 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
375 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
376 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
377 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
378 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
379 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
380 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
381 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
382 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
383 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
384 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
385 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
386 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
387 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
388 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
389 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
390 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
391 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
392 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
393 #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 23)
394 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 24)
395 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 25)
396 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 26)
397 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 27)
398 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 28)
399 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 29)
402 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
403 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
404 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
405 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
406 #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
407 #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
408 #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
409 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
411 unsigned long active_vlans
[BITS_TO_LONGS(VLAN_N_VID
)];
413 struct ixgbe_q_vector
*q_vector
[MAX_MSIX_Q_VECTORS
];
416 struct ieee_pfc
*ixgbe_ieee_pfc
;
417 struct ieee_ets
*ixgbe_ieee_ets
;
418 struct ixgbe_dcb_config dcb_cfg
;
419 struct ixgbe_dcb_config temp_dcb_cfg
;
422 enum ixgbe_fc_mode last_lfc_mode
;
424 /* Interrupt Throttle Rate */
434 struct ixgbe_ring
*tx_ring
[MAX_TX_QUEUES
] ____cacheline_aligned_in_smp
;
436 u32 tx_timeout_count
;
443 struct ixgbe_ring
*rx_ring
[MAX_RX_QUEUES
] ____cacheline_aligned_in_smp
;
445 int num_rx_pools
; /* == num_rx_queues in 82598 */
446 int num_rx_queues_per_pool
; /* 1 if 82598, can be many if 82599 */
447 u64 hw_csum_rx_error
;
448 u64 hw_rx_no_dma_resources
;
450 int num_msix_vectors
;
451 int max_msix_q_vectors
; /* true count of q_vectors for device */
452 struct ixgbe_ring_feature ring_feature
[RING_F_ARRAY_SIZE
];
453 struct msix_entry
*msix_entries
;
455 u32 alloc_rx_page_failed
;
456 u32 alloc_rx_buff_failed
;
458 /* default to trying for four seconds */
459 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
461 /* OS defined structs */
462 struct net_device
*netdev
;
463 struct pci_dev
*pdev
;
466 struct ixgbe_ring test_tx_ring
;
467 struct ixgbe_ring test_rx_ring
;
469 /* structs defined in ixgbe_hw.h */
472 struct ixgbe_hw_stats stats
;
474 /* Interrupt Throttle Rate */
479 unsigned int tx_ring_count
;
480 unsigned int rx_ring_count
;
484 unsigned long link_check_timeout
;
486 struct work_struct service_task
;
487 struct timer_list service_timer
;
490 unsigned long fdir_overflow
; /* number of times ATR was backed off */
491 spinlock_t fdir_perfect_lock
;
493 struct ixgbe_fcoe fcoe
;
494 #endif /* IXGBE_FCOE */
506 DECLARE_BITMAP(active_vfs
, IXGBE_MAX_VF_FUNCTIONS
);
507 unsigned int num_vfs
;
508 struct vf_data_storage
*vfinfo
;
509 int vf_rate_link_speed
;
510 struct vf_macvlans vf_mvs
;
511 struct vf_macvlans
*mv_list
;
512 bool antispoofing_enabled
;
514 struct hlist_head fdir_filter_list
;
515 union ixgbe_atr_input fdir_mask
;
516 int fdir_filter_count
;
517 u32 timer_event_accumulator
;
521 struct ixgbe_fdir_filter
{
522 struct hlist_node fdir_node
;
523 union ixgbe_atr_input filter
;
532 __IXGBE_SERVICE_SCHED
,
536 struct ixgbe_rsc_cb
{
541 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
549 extern struct ixgbe_info ixgbe_82598_info
;
550 extern struct ixgbe_info ixgbe_82599_info
;
551 extern struct ixgbe_info ixgbe_X540_info
;
552 #ifdef CONFIG_IXGBE_DCB
553 extern const struct dcbnl_rtnl_ops dcbnl_ops
;
554 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config
*src_dcb_cfg
,
555 struct ixgbe_dcb_config
*dst_dcb_cfg
,
559 extern char ixgbe_driver_name
[];
560 extern const char ixgbe_driver_version
[];
562 extern void ixgbe_up(struct ixgbe_adapter
*adapter
);
563 extern void ixgbe_down(struct ixgbe_adapter
*adapter
);
564 extern void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
);
565 extern void ixgbe_reset(struct ixgbe_adapter
*adapter
);
566 extern void ixgbe_set_ethtool_ops(struct net_device
*netdev
);
567 extern int ixgbe_setup_rx_resources(struct ixgbe_ring
*);
568 extern int ixgbe_setup_tx_resources(struct ixgbe_ring
*);
569 extern void ixgbe_free_rx_resources(struct ixgbe_ring
*);
570 extern void ixgbe_free_tx_resources(struct ixgbe_ring
*);
571 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter
*,struct ixgbe_ring
*);
572 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter
*,struct ixgbe_ring
*);
573 extern void ixgbe_disable_rx_queue(struct ixgbe_adapter
*adapter
,
574 struct ixgbe_ring
*);
575 extern void ixgbe_update_stats(struct ixgbe_adapter
*adapter
);
576 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
);
577 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
);
578 extern netdev_tx_t
ixgbe_xmit_frame_ring(struct sk_buff
*,
579 struct ixgbe_adapter
*,
580 struct ixgbe_ring
*);
581 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring
*,
582 struct ixgbe_tx_buffer
*);
583 extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring
*, u16
);
584 extern void ixgbe_write_eitr(struct ixgbe_q_vector
*);
585 extern int ethtool_ioctl(struct ifreq
*ifr
);
586 extern s32
ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw
*hw
);
587 extern s32
ixgbe_init_fdir_signature_82599(struct ixgbe_hw
*hw
, u32 fdirctrl
);
588 extern s32
ixgbe_init_fdir_perfect_82599(struct ixgbe_hw
*hw
, u32 fdirctrl
);
589 extern s32
ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw
*hw
,
590 union ixgbe_atr_hash_dword input
,
591 union ixgbe_atr_hash_dword common
,
593 extern s32
ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw
*hw
,
594 union ixgbe_atr_input
*input_mask
);
595 extern s32
ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw
*hw
,
596 union ixgbe_atr_input
*input
,
597 u16 soft_id
, u8 queue
);
598 extern s32
ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw
*hw
,
599 union ixgbe_atr_input
*input
,
601 extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input
*input
,
602 union ixgbe_atr_input
*mask
);
603 extern void ixgbe_set_rx_mode(struct net_device
*netdev
);
604 extern int ixgbe_setup_tc(struct net_device
*dev
, u8 tc
);
605 extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring
*, u32
, u32
, u32
, u32
);
606 extern void ixgbe_do_reset(struct net_device
*netdev
);
608 extern void ixgbe_configure_fcoe(struct ixgbe_adapter
*adapter
);
609 extern int ixgbe_fso(struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
610 u32 tx_flags
, u8
*hdr_len
);
611 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter
*adapter
);
612 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter
*adapter
,
613 union ixgbe_adv_rx_desc
*rx_desc
,
616 extern int ixgbe_fcoe_ddp_get(struct net_device
*netdev
, u16 xid
,
617 struct scatterlist
*sgl
, unsigned int sgc
);
618 extern int ixgbe_fcoe_ddp_target(struct net_device
*netdev
, u16 xid
,
619 struct scatterlist
*sgl
, unsigned int sgc
);
620 extern int ixgbe_fcoe_ddp_put(struct net_device
*netdev
, u16 xid
);
621 extern int ixgbe_fcoe_enable(struct net_device
*netdev
);
622 extern int ixgbe_fcoe_disable(struct net_device
*netdev
);
623 #ifdef CONFIG_IXGBE_DCB
624 extern u8
ixgbe_fcoe_getapp(struct ixgbe_adapter
*adapter
);
625 extern u8
ixgbe_fcoe_setapp(struct ixgbe_adapter
*adapter
, u8 up
);
626 #endif /* CONFIG_IXGBE_DCB */
627 extern int ixgbe_fcoe_get_wwn(struct net_device
*netdev
, u64
*wwn
, int type
);
628 #endif /* IXGBE_FCOE */
630 #endif /* _IXGBE_H_ */