drivers/net/ethernet/intel/ixgbe/ixgbe.h

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _IXGBE_H_
  29 #define _IXGBE_H_
  30
  31 #include <linux/bitops.h>
  32 #include <linux/types.h>
  33 #include <linux/pci.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/cpumask.h>
  36 #include <linux/aer.h>
  37 #include <linux/if_vlan.h>
  38
  39 #include "ixgbe_type.h"
  40 #include "ixgbe_common.h"
  41 #include "ixgbe_dcb.h"
  42 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
  43 #define IXGBE_FCOE
  44 #include "ixgbe_fcoe.h"
  45 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
  46 #ifdef CONFIG_IXGBE_DCA
  47 #include <linux/dca.h>
  48 #endif
  49
  50 /* common prefix used by pr_<> macros */
  51 #undef pr_fmt
  52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  53
  54 /* TX/RX descriptor defines */
  55 #define IXGBE_DEFAULT_TXD                   512
  56 #define IXGBE_DEFAULT_TX_WORK               256
  57 #define IXGBE_MAX_TXD                      4096
  58 #define IXGBE_MIN_TXD                        64
  59
  60 #define IXGBE_DEFAULT_RXD                   512
  61 #define IXGBE_MAX_RXD                      4096
  62 #define IXGBE_MIN_RXD                        64
  63
  64 /* flow control */
  65 #define IXGBE_MIN_FCRTL                    0x40
  66 #define IXGBE_MAX_FCRTL                 0x7FF80
  67 #define IXGBE_MIN_FCRTH                   0x600
  68 #define IXGBE_MAX_FCRTH                 0x7FFF0
  69 #define IXGBE_DEFAULT_FCPAUSE            0xFFFF
  70 #define IXGBE_MIN_FCPAUSE                     0
  71 #define IXGBE_MAX_FCPAUSE                0xFFFF
  72
  73 /* Supported Rx Buffer Sizes */
  74 #define IXGBE_RXBUFFER_512   512    /* Used for packet split */
  75 #define IXGBE_RXBUFFER_2K   2048
  76 #define IXGBE_RXBUFFER_3K   3072
  77 #define IXGBE_RXBUFFER_4K   4096
  78 #define IXGBE_RXBUFFER_7K   7168
  79 #define IXGBE_RXBUFFER_8K   8192
  80 #define IXGBE_RXBUFFER_15K  15360
  81 #define IXGBE_MAX_RXBUFFER  16384  /* largest size for a single descriptor */
  82
  83 /*
  84  * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
  85  * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
  86  * this adds up to 512 bytes of extra data meaning the smallest allocation
  87  * we could have is 1K.
  88  * i.e. RXBUFFER_512 --> size-1024 slab
  89  */
  90 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
  91
  92 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
  93
  94 /* How many Rx Buffers do we bundle into one write to the hardware ? */
  95 #define IXGBE_RX_BUFFER_WRITE   16      /* Must be power of 2 */
  96
  97 #define IXGBE_TX_FLAGS_CSUM             (u32)(1)
  98 #define IXGBE_TX_FLAGS_HW_VLAN          (u32)(1 << 1)
  99 #define IXGBE_TX_FLAGS_SW_VLAN          (u32)(1 << 2)
 100 #define IXGBE_TX_FLAGS_TSO              (u32)(1 << 3)
 101 #define IXGBE_TX_FLAGS_IPV4             (u32)(1 << 4)
 102 #define IXGBE_TX_FLAGS_FCOE             (u32)(1 << 5)
 103 #define IXGBE_TX_FLAGS_FSO              (u32)(1 << 6)
 104 #define IXGBE_TX_FLAGS_TXSW             (u32)(1 << 7)
 105 #define IXGBE_TX_FLAGS_MAPPED_AS_PAGE   (u32)(1 << 8)
 106 #define IXGBE_TX_FLAGS_VLAN_MASK        0xffff0000
 107 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK   0xe0000000
 108 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT  29
 109 #define IXGBE_TX_FLAGS_VLAN_SHIFT       16
 110
 111 #define IXGBE_MAX_RSC_INT_RATE          162760
 112
 113 #define IXGBE_MAX_VF_MC_ENTRIES         30
 114 #define IXGBE_MAX_VF_FUNCTIONS          64
 115 #define IXGBE_MAX_VFTA_ENTRIES          128
 116 #define MAX_EMULATION_MAC_ADDRS         16
 117 #define IXGBE_MAX_PF_MACVLANS           15
 118 #define VMDQ_P(p)   ((p) + adapter->num_vfs)
 119 #define IXGBE_82599_VF_DEVICE_ID        0x10ED
 120 #define IXGBE_X540_VF_DEVICE_ID         0x1515
 121
 122 struct vf_data_storage {
 123         unsigned char vf_mac_addresses[ETH_ALEN];
 124         u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
 125         u16 num_vf_mc_hashes;
 126         u16 default_vf_vlan_id;
 127         u16 vlans_enabled;
 128         bool clear_to_send;
 129         bool pf_set_mac;
 130         u16 pf_vlan; /* When set, guest VLAN config not allowed. */
 131         u16 pf_qos;
 132         u16 tx_rate;
 133         u16 vlan_count;
 134         u8 spoofchk_enabled;
 135         struct pci_dev *vfdev;
 136 };
 137
 138 struct vf_macvlans {
 139         struct list_head l;
 140         int vf;
 141         int rar_entry;
 142         bool free;
 143         bool is_macvlan;
 144         u8 vf_macvlan[ETH_ALEN];
 145 };
 146
 147 #define IXGBE_MAX_TXD_PWR       14
 148 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 149
 150 /* Tx Descriptors needed, worst case */
 151 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
 152 #define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
 153
 154 /* wrapper around a pointer to a socket buffer,
 155  * so a DMA handle can be stored along with the buffer */
 156 struct ixgbe_tx_buffer {
 157         union ixgbe_adv_tx_desc *next_to_watch;
 158         unsigned long time_stamp;
 159         dma_addr_t dma;
 160         u32 length;
 161         u32 tx_flags;
 162         struct sk_buff *skb;
 163         u32 bytecount;
 164         u16 gso_segs;
 165 };
 166
 167 struct ixgbe_rx_buffer {
 168         struct sk_buff *skb;
 169         dma_addr_t dma;
 170         struct page *page;
 171         dma_addr_t page_dma;
 172         unsigned int page_offset;
 173 };
 174
 175 struct ixgbe_queue_stats {
 176         u64 packets;
 177         u64 bytes;
 178 };
 179
 180 struct ixgbe_tx_queue_stats {
 181         u64 restart_queue;
 182         u64 tx_busy;
 183         u64 completed;
 184         u64 tx_done_old;
 185 };
 186
 187 struct ixgbe_rx_queue_stats {
 188         u64 rsc_count;
 189         u64 rsc_flush;
 190         u64 non_eop_descs;
 191         u64 alloc_rx_page_failed;
 192         u64 alloc_rx_buff_failed;
 193         u64 csum_err;
 194 };
 195
 196 enum ixbge_ring_state_t {
 197         __IXGBE_TX_FDIR_INIT_DONE,
 198         __IXGBE_TX_DETECT_HANG,
 199         __IXGBE_HANG_CHECK_ARMED,
 200         __IXGBE_RX_PS_ENABLED,
 201         __IXGBE_RX_RSC_ENABLED,
 202         __IXGBE_RX_CSUM_UDP_ZERO_ERR,
 203 };
 204
 205 #define ring_is_ps_enabled(ring) \
 206         test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
 207 #define set_ring_ps_enabled(ring) \
 208         set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
 209 #define clear_ring_ps_enabled(ring) \
 210         clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
 211 #define check_for_tx_hang(ring) \
 212         test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 213 #define set_check_for_tx_hang(ring) \
 214         set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 215 #define clear_check_for_tx_hang(ring) \
 216         clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 217 #define ring_is_rsc_enabled(ring) \
 218         test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 219 #define set_ring_rsc_enabled(ring) \
 220         set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 221 #define clear_ring_rsc_enabled(ring) \
 222         clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 223 struct ixgbe_ring {
 224         struct ixgbe_ring *next;        /* pointer to next ring in q_vector */
 225         void *desc;                     /* descriptor ring memory */
 226         struct device *dev;             /* device for DMA mapping */
 227         struct net_device *netdev;      /* netdev ring belongs to */
 228         union {
 229                 struct ixgbe_tx_buffer *tx_buffer_info;
 230                 struct ixgbe_rx_buffer *rx_buffer_info;
 231         };
 232         unsigned long state;
 233         u8 __iomem *tail;
 234
 235         u16 count;                      /* amount of descriptors */
 236         u16 rx_buf_len;
 237
 238         u8 queue_index; /* needed for multiqueue queue management */
 239         u8 reg_idx;                     /* holds the special value that gets
 240                                          * the hardware register offset
 241                                          * associated with this ring, which is
 242                                          * different for DCB and RSS modes
 243                                          */
 244         u8 atr_sample_rate;
 245         u8 atr_count;
 246
 247         u16 next_to_use;
 248         u16 next_to_clean;
 249
 250         u8 dcb_tc;
 251         struct ixgbe_queue_stats stats;
 252         struct u64_stats_sync syncp;
 253         union {
 254                 struct ixgbe_tx_queue_stats tx_stats;
 255                 struct ixgbe_rx_queue_stats rx_stats;
 256         };
 257         unsigned int size;              /* length in bytes */
 258         dma_addr_t dma;                 /* phys. address of descriptor ring */
 259         struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */
 260 } ____cacheline_internodealigned_in_smp;
 261
 262 enum ixgbe_ring_f_enum {
 263         RING_F_NONE = 0,
 264         RING_F_VMDQ,  /* SR-IOV uses the same ring feature */
 265         RING_F_RSS,
 266         RING_F_FDIR,
 267 #ifdef IXGBE_FCOE
 268         RING_F_FCOE,
 269 #endif /* IXGBE_FCOE */
 270
 271         RING_F_ARRAY_SIZE      /* must be last in enum set */
 272 };
 273
 274 #define IXGBE_MAX_RSS_INDICES  16
 275 #define IXGBE_MAX_VMDQ_INDICES 64
 276 #define IXGBE_MAX_FDIR_INDICES 64
 277 #ifdef IXGBE_FCOE
 278 #define IXGBE_MAX_FCOE_INDICES  8
 279 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
 280 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
 281 #else
 282 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
 283 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
 284 #endif /* IXGBE_FCOE */
 285 struct ixgbe_ring_feature {
 286         int indices;
 287         int mask;
 288 } ____cacheline_internodealigned_in_smp;
 289
 290 struct ixgbe_ring_container {
 291         struct ixgbe_ring *ring;        /* pointer to linked list of rings */
 292         unsigned int total_bytes;       /* total bytes processed this int */
 293         unsigned int total_packets;     /* total packets processed this int */
 294         u16 work_limit;                 /* total work allowed per interrupt */
 295         u8 count;                       /* total number of rings in vector */
 296         u8 itr;                         /* current ITR setting for ring */
 297 };
 298
 299 /* iterator for handling rings in ring container */
 300 #define ixgbe_for_each_ring(pos, head) \
 301         for (pos = (head).ring; pos != NULL; pos = pos->next)
 302
 303 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
 304                               ? 8 : 1)
 305 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
 306
 307 /* MAX_MSIX_Q_VECTORS of these are allocated,
 308  * but we only use one per queue-specific vector.
 309  */
 310 struct ixgbe_q_vector {
 311         struct ixgbe_adapter *adapter;
 312 #ifdef CONFIG_IXGBE_DCA
 313         int cpu;            /* CPU for DCA */
 314 #endif
 315         u16 v_idx;              /* index of q_vector within array, also used for
 316                                  * finding the bit in EICR and friends that
 317                                  * represents the vector for this ring */
 318         u16 itr;                /* Interrupt throttle rate written to EITR */
 319         struct ixgbe_ring_container rx, tx;
 320
 321         struct napi_struct napi;
 322         cpumask_t affinity_mask;
 323         int numa_node;
 324         struct rcu_head rcu;    /* to avoid race with update stats on free */
 325         char name[IFNAMSIZ + 9];
 326
 327         /* for dynamic allocation of rings associated with this q_vector */
 328         struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
 329 };
 330
 331 /*
 332  * microsecond values for various ITR rates shifted by 2 to fit itr register
 333  * with the first 3 bits reserved 0
 334  */
 335 #define IXGBE_MIN_RSC_ITR       24
 336 #define IXGBE_100K_ITR          40
 337 #define IXGBE_20K_ITR           200
 338 #define IXGBE_10K_ITR           400
 339 #define IXGBE_8K_ITR            500
 340
 341 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
 342 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
 343                                         const u32 stat_err_bits)
 344 {
 345         return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
 346 }
 347
 348 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
 349 {
 350         u16 ntc = ring->next_to_clean;
 351         u16 ntu = ring->next_to_use;
 352
 353         return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
 354 }
 355
 356 #define IXGBE_RX_DESC(R, i)         \
 357         (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
 358 #define IXGBE_TX_DESC(R, i)         \
 359         (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
 360 #define IXGBE_TX_CTXTDESC(R, i)     \
 361         (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
 362
 363 #define IXGBE_MAX_JUMBO_FRAME_SIZE        16128
 364 #ifdef IXGBE_FCOE
 365 /* Use 3K as the baby jumbo frame size for FCoE */
 366 #define IXGBE_FCOE_JUMBO_FRAME_SIZE       3072
 367 #endif /* IXGBE_FCOE */
 368
 369 #define OTHER_VECTOR 1
 370 #define NON_Q_VECTORS (OTHER_VECTOR)
 371
 372 #define MAX_MSIX_VECTORS_82599 64
 373 #define MAX_MSIX_Q_VECTORS_82599 64
 374 #define MAX_MSIX_VECTORS_82598 18
 375 #define MAX_MSIX_Q_VECTORS_82598 16
 376
 377 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
 378 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
 379
 380 #define MIN_MSIX_Q_VECTORS 1
 381 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
 382
 383 /* default to trying for four seconds */
 384 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
 385
 386 /* board specific private data structure */
 387 struct ixgbe_adapter {
 388         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 389         /* OS defined structs */
 390         struct net_device *netdev;
 391         struct pci_dev *pdev;
 392
 393         unsigned long state;
 394
 395         /* Some features need tri-state capability,
 396          * thus the additional *_CAPABLE flags.
 397          */
 398         u32 flags;
 399 #define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 1)
 400 #define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 2)
 401 #define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 3)
 402 #define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 4)
 403 #define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 6)
 404 #define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 7)
 405 #define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 8)
 406 #define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 9)
 407 #define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 10)
 408 #define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 11)
 409 #define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 12)
 410 #define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 13)
 411 #define IXGBE_FLAG_DCB_ENABLED                  (u32)(1 << 14)
 412 #define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 16)
 413 #define IXGBE_FLAG_RSS_CAPABLE                  (u32)(1 << 17)
 414 #define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 18)
 415 #define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 19)
 416 #define IXGBE_FLAG_FAN_FAIL_CAPABLE             (u32)(1 << 20)
 417 #define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 22)
 418 #define IXGBE_FLAG_NEED_LINK_CONFIG             (u32)(1 << 23)
 419 #define IXGBE_FLAG_FDIR_HASH_CAPABLE            (u32)(1 << 24)
 420 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE         (u32)(1 << 25)
 421 #define IXGBE_FLAG_FCOE_CAPABLE                 (u32)(1 << 26)
 422 #define IXGBE_FLAG_FCOE_ENABLED                 (u32)(1 << 27)
 423 #define IXGBE_FLAG_SRIOV_CAPABLE                (u32)(1 << 28)
 424 #define IXGBE_FLAG_SRIOV_ENABLED                (u32)(1 << 29)
 425
 426         u32 flags2;
 427 #define IXGBE_FLAG2_RSC_CAPABLE                 (u32)(1)
 428 #define IXGBE_FLAG2_RSC_ENABLED                 (u32)(1 << 1)
 429 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE         (u32)(1 << 2)
 430 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT           (u32)(1 << 3)
 431 #define IXGBE_FLAG2_SEARCH_FOR_SFP              (u32)(1 << 4)
 432 #define IXGBE_FLAG2_SFP_NEEDS_RESET             (u32)(1 << 5)
 433 #define IXGBE_FLAG2_RESET_REQUESTED             (u32)(1 << 6)
 434 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT        (u32)(1 << 7)
 435
 436
 437         /* Tx fast path data */
 438         int num_tx_queues;
 439         u16 tx_itr_setting;
 440         u16 tx_work_limit;
 441
 442         /* Rx fast path data */
 443         int num_rx_queues;
 444         u16 rx_itr_setting;
 445
 446         /* TX */
 447         struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
 448
 449         u64 restart_queue;
 450         u64 lsc_int;
 451         u32 tx_timeout_count;
 452
 453         /* RX */
 454         struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
 455         int num_rx_pools;               /* == num_rx_queues in 82598 */
 456         int num_rx_queues_per_pool;     /* 1 if 82598, can be many if 82599 */
 457         u64 hw_csum_rx_error;
 458         u64 hw_rx_no_dma_resources;
 459         u64 rsc_total_count;
 460         u64 rsc_total_flush;
 461         u64 non_eop_descs;
 462         u32 alloc_rx_page_failed;
 463         u32 alloc_rx_buff_failed;
 464
 465         struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
 466
 467         /* DCB parameters */
 468         struct ieee_pfc *ixgbe_ieee_pfc;
 469         struct ieee_ets *ixgbe_ieee_ets;
 470         struct ixgbe_dcb_config dcb_cfg;
 471         struct ixgbe_dcb_config temp_dcb_cfg;
 472         u8 dcb_set_bitmap;
 473         u8 dcbx_cap;
 474         enum ixgbe_fc_mode last_lfc_mode;
 475
 476         int num_msix_vectors;
 477         int max_msix_q_vectors;         /* true count of q_vectors for device */
 478         struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
 479         struct msix_entry *msix_entries;
 480
 481         u32 test_icr;
 482         struct ixgbe_ring test_tx_ring;
 483         struct ixgbe_ring test_rx_ring;
 484
 485         /* structs defined in ixgbe_hw.h */
 486         struct ixgbe_hw hw;
 487         u16 msg_enable;
 488         struct ixgbe_hw_stats stats;
 489
 490         u64 tx_busy;
 491         unsigned int tx_ring_count;
 492         unsigned int rx_ring_count;
 493
 494         u32 link_speed;
 495         bool link_up;
 496         unsigned long link_check_timeout;
 497
 498         struct timer_list service_timer;
 499         struct work_struct service_task;
 500
 501         struct hlist_head fdir_filter_list;
 502         unsigned long fdir_overflow; /* number of times ATR was backed off */
 503         union ixgbe_atr_input fdir_mask;
 504         int fdir_filter_count;
 505         u32 fdir_pballoc;
 506         u32 atr_sample_rate;
 507         spinlock_t fdir_perfect_lock;
 508
 509 #ifdef IXGBE_FCOE
 510         struct ixgbe_fcoe fcoe;
 511 #endif /* IXGBE_FCOE */
 512         u32 wol;
 513
 514         u16 bd_number;
 515
 516         u16 eeprom_verh;
 517         u16 eeprom_verl;
 518         u16 eeprom_cap;
 519
 520         u32 interrupt_event;
 521         u32 led_reg;
 522
 523         /* SR-IOV */
 524         DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
 525         unsigned int num_vfs;
 526         struct vf_data_storage *vfinfo;
 527         int vf_rate_link_speed;
 528         struct vf_macvlans vf_mvs;
 529         struct vf_macvlans *mv_list;
 530
 531         u32 timer_event_accumulator;
 532         u32 vferr_refcount;
 533 };
 534
 535 struct ixgbe_fdir_filter {
 536         struct hlist_node fdir_node;
 537         union ixgbe_atr_input filter;
 538         u16 sw_idx;
 539         u16 action;
 540 };
 541
 542 enum ixbge_state_t {
 543         __IXGBE_TESTING,
 544         __IXGBE_RESETTING,
 545         __IXGBE_DOWN,
 546         __IXGBE_SERVICE_SCHED,
 547         __IXGBE_IN_SFP_INIT,
 548 };
 549
 550 struct ixgbe_cb {
 551         union {                         /* Union defining head/tail partner */
 552                 struct sk_buff *head;
 553                 struct sk_buff *tail;
 554         };
 555         dma_addr_t dma;
 556         u16 append_cnt;
 557         bool delay_unmap;
 558 };
 559 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
 560
 561 enum ixgbe_boards {
 562         board_82598,
 563         board_82599,
 564         board_X540,
 565 };
 566
 567 extern struct ixgbe_info ixgbe_82598_info;
 568 extern struct ixgbe_info ixgbe_82599_info;
 569 extern struct ixgbe_info ixgbe_X540_info;
 570 #ifdef CONFIG_IXGBE_DCB
 571 extern const struct dcbnl_rtnl_ops dcbnl_ops;
 572 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
 573                               struct ixgbe_dcb_config *dst_dcb_cfg,
 574                               int tc_max);
 575 #endif
 576
 577 extern char ixgbe_driver_name[];
 578 extern const char ixgbe_driver_version[];
 579 extern char ixgbe_default_device_descr[];
 580
 581 extern void ixgbe_up(struct ixgbe_adapter *adapter);
 582 extern void ixgbe_down(struct ixgbe_adapter *adapter);
 583 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
 584 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
 585 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
 586 extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
 587 extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
 588 extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
 589 extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
 590 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
 591 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
 592 extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
 593                                    struct ixgbe_ring *);
 594 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
 595 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
 596 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
 597 extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
 598                                          struct ixgbe_adapter *,
 599                                          struct ixgbe_ring *);
 600 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
 601                                              struct ixgbe_tx_buffer *);
 602 extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
 603 extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
 604 extern int ethtool_ioctl(struct ifreq *ifr);
 605 extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
 606 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
 607 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
 608 extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
 609                                                  union ixgbe_atr_hash_dword input,
 610                                                  union ixgbe_atr_hash_dword common,
 611                                                  u8 queue);
 612 extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
 613                                            union ixgbe_atr_input *input_mask);
 614 extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
 615                                                  union ixgbe_atr_input *input,
 616                                                  u16 soft_id, u8 queue);
 617 extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
 618                                                  union ixgbe_atr_input *input,
 619                                                  u16 soft_id);
 620 extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
 621                                                  union ixgbe_atr_input *mask);
 622 extern void ixgbe_set_rx_mode(struct net_device *netdev);
 623 extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
 624 extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
 625 extern void ixgbe_do_reset(struct net_device *netdev);
 626 #ifdef IXGBE_FCOE
 627 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
 628 extern int ixgbe_fso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
 629                      u32 tx_flags, u8 *hdr_len);
 630 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
 631 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
 632                           union ixgbe_adv_rx_desc *rx_desc,
 633                           struct sk_buff *skb);
 634 extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
 635                               struct scatterlist *sgl, unsigned int sgc);
 636 extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
 637                                  struct scatterlist *sgl, unsigned int sgc);
 638 extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
 639 extern int ixgbe_fcoe_enable(struct net_device *netdev);
 640 extern int ixgbe_fcoe_disable(struct net_device *netdev);
 641 #ifdef CONFIG_IXGBE_DCB
 642 extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
 643 extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
 644 #endif /* CONFIG_IXGBE_DCB */
 645 extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
 646 extern int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
 647                                   struct netdev_fcoe_hbainfo *info);
 648 #endif /* IXGBE_FCOE */
 649
 650 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
 651 {
 652         return netdev_get_tx_queue(ring->netdev, ring->queue_index);
 653 }
 654
 655 #endif /* _IXGBE_H_ */