1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
31 #include <linux/bitops.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/cpumask.h>
36 #include <linux/aer.h>
37 #include <linux/if_vlan.h>
39 #include <linux/clocksource.h>
40 #include <linux/net_tstamp.h>
41 #include <linux/ptp_clock_kernel.h>
43 #include "ixgbe_type.h"
44 #include "ixgbe_common.h"
45 #include "ixgbe_dcb.h"
46 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
48 #include "ixgbe_fcoe.h"
49 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
50 #ifdef CONFIG_IXGBE_DCA
51 #include <linux/dca.h>
54 /* common prefix used by pr_<> macros */
56 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
58 /* TX/RX descriptor defines */
59 #define IXGBE_DEFAULT_TXD 512
60 #define IXGBE_DEFAULT_TX_WORK 256
61 #define IXGBE_MAX_TXD 4096
62 #define IXGBE_MIN_TXD 64
64 #define IXGBE_DEFAULT_RXD 512
65 #define IXGBE_MAX_RXD 4096
66 #define IXGBE_MIN_RXD 64
69 #define IXGBE_MIN_FCRTL 0x40
70 #define IXGBE_MAX_FCRTL 0x7FF80
71 #define IXGBE_MIN_FCRTH 0x600
72 #define IXGBE_MAX_FCRTH 0x7FFF0
73 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
74 #define IXGBE_MIN_FCPAUSE 0
75 #define IXGBE_MAX_FCPAUSE 0xFFFF
77 /* Supported Rx Buffer Sizes */
78 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */
79 #define IXGBE_RXBUFFER_2K 2048
80 #define IXGBE_RXBUFFER_3K 3072
81 #define IXGBE_RXBUFFER_4K 4096
82 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
85 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
86 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more,
87 * this adds up to 448 bytes of extra data.
89 * Since netdev_alloc_skb now allocates a page fragment we can use a value
90 * of 256 and the resultant skb will have a truesize of 960 or less.
92 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
94 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
96 /* How many Rx Buffers do we bundle into one write to the hardware ? */
97 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
99 #define IXGBE_TX_FLAGS_CSUM (u32)(1)
100 #define IXGBE_TX_FLAGS_HW_VLAN (u32)(1 << 1)
101 #define IXGBE_TX_FLAGS_SW_VLAN (u32)(1 << 2)
102 #define IXGBE_TX_FLAGS_TSO (u32)(1 << 3)
103 #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 4)
104 #define IXGBE_TX_FLAGS_FCOE (u32)(1 << 5)
105 #define IXGBE_TX_FLAGS_FSO (u32)(1 << 6)
106 #define IXGBE_TX_FLAGS_TXSW (u32)(1 << 7)
107 #define IXGBE_TX_FLAGS_TSTAMP (u32)(1 << 8)
108 #define IXGBE_TX_FLAGS_NO_IFCS (u32)(1 << 9)
109 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
110 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
111 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
112 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
114 #define IXGBE_MAX_VF_MC_ENTRIES 30
115 #define IXGBE_MAX_VF_FUNCTIONS 64
116 #define IXGBE_MAX_VFTA_ENTRIES 128
117 #define MAX_EMULATION_MAC_ADDRS 16
118 #define IXGBE_MAX_PF_MACVLANS 15
119 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset)
120 #define IXGBE_82599_VF_DEVICE_ID 0x10ED
121 #define IXGBE_X540_VF_DEVICE_ID 0x1515
123 struct vf_data_storage
{
124 unsigned char vf_mac_addresses
[ETH_ALEN
];
125 u16 vf_mc_hashes
[IXGBE_MAX_VF_MC_ENTRIES
];
126 u16 num_vf_mc_hashes
;
127 u16 default_vf_vlan_id
;
131 u16 pf_vlan
; /* When set, guest VLAN config not allowed. */
145 u8 vf_macvlan
[ETH_ALEN
];
148 #define IXGBE_MAX_TXD_PWR 14
149 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
151 /* Tx Descriptors needed, worst case */
152 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
153 #define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
155 /* wrapper around a pointer to a socket buffer,
156 * so a DMA handle can be stored along with the buffer */
157 struct ixgbe_tx_buffer
{
158 union ixgbe_adv_tx_desc
*next_to_watch
;
159 unsigned long time_stamp
;
161 unsigned int bytecount
;
162 unsigned short gso_segs
;
164 DEFINE_DMA_UNMAP_ADDR(dma
);
165 DEFINE_DMA_UNMAP_LEN(len
);
169 struct ixgbe_rx_buffer
{
173 unsigned int page_offset
;
176 struct ixgbe_queue_stats
{
181 struct ixgbe_tx_queue_stats
{
187 struct ixgbe_rx_queue_stats
{
191 u64 alloc_rx_page_failed
;
192 u64 alloc_rx_buff_failed
;
196 enum ixgbe_ring_state_t
{
197 __IXGBE_TX_FDIR_INIT_DONE
,
198 __IXGBE_TX_DETECT_HANG
,
199 __IXGBE_HANG_CHECK_ARMED
,
200 __IXGBE_RX_RSC_ENABLED
,
201 __IXGBE_RX_CSUM_UDP_ZERO_ERR
,
205 #define check_for_tx_hang(ring) \
206 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
207 #define set_check_for_tx_hang(ring) \
208 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
209 #define clear_check_for_tx_hang(ring) \
210 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
211 #define ring_is_rsc_enabled(ring) \
212 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
213 #define set_ring_rsc_enabled(ring) \
214 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
215 #define clear_ring_rsc_enabled(ring) \
216 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
218 struct ixgbe_ring
*next
; /* pointer to next ring in q_vector */
219 struct ixgbe_q_vector
*q_vector
; /* backpointer to host q_vector */
220 struct net_device
*netdev
; /* netdev ring belongs to */
221 struct device
*dev
; /* device for DMA mapping */
222 void *desc
; /* descriptor ring memory */
224 struct ixgbe_tx_buffer
*tx_buffer_info
;
225 struct ixgbe_rx_buffer
*rx_buffer_info
;
229 dma_addr_t dma
; /* phys. address of descriptor ring */
230 unsigned int size
; /* length in bytes */
232 u16 count
; /* amount of descriptors */
234 u8 queue_index
; /* needed for multiqueue queue management */
235 u8 reg_idx
; /* holds the special value that gets
236 * the hardware register offset
237 * associated with this ring, which is
238 * different for DCB and RSS modes
252 struct ixgbe_queue_stats stats
;
253 struct u64_stats_sync syncp
;
255 struct ixgbe_tx_queue_stats tx_stats
;
256 struct ixgbe_rx_queue_stats rx_stats
;
258 } ____cacheline_internodealigned_in_smp
;
260 enum ixgbe_ring_f_enum
{
262 RING_F_VMDQ
, /* SR-IOV uses the same ring feature */
267 #endif /* IXGBE_FCOE */
269 RING_F_ARRAY_SIZE
/* must be last in enum set */
272 #define IXGBE_MAX_RSS_INDICES 16
273 #define IXGBE_MAX_VMDQ_INDICES 64
274 #define IXGBE_MAX_FDIR_INDICES 64
276 #define IXGBE_MAX_FCOE_INDICES 8
277 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
278 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
280 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
281 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
282 #endif /* IXGBE_FCOE */
283 struct ixgbe_ring_feature
{
284 u16 limit
; /* upper limit on feature indices */
285 u16 indices
; /* current value of indices */
286 u16 mask
; /* Mask used for feature to ring mapping */
287 u16 offset
; /* offset to start of feature */
288 } ____cacheline_internodealigned_in_smp
;
290 #define IXGBE_82599_VMDQ_8Q_MASK 0x78
291 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C
292 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E
295 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
296 * this is twice the size of a half page we need to double the page order
297 * for FCoE enabled Rx queues.
299 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring
*ring
)
302 if (test_bit(__IXGBE_RX_FCOE
, &ring
->state
))
303 return (PAGE_SIZE
< 8192) ? IXGBE_RXBUFFER_4K
:
306 return IXGBE_RXBUFFER_2K
;
309 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring
*ring
)
312 if (test_bit(__IXGBE_RX_FCOE
, &ring
->state
))
313 return (PAGE_SIZE
< 8192) ? 1 : 0;
317 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
319 struct ixgbe_ring_container
{
320 struct ixgbe_ring
*ring
; /* pointer to linked list of rings */
321 unsigned int total_bytes
; /* total bytes processed this int */
322 unsigned int total_packets
; /* total packets processed this int */
323 u16 work_limit
; /* total work allowed per interrupt */
324 u8 count
; /* total number of rings in vector */
325 u8 itr
; /* current ITR setting for ring */
328 /* iterator for handling rings in ring container */
329 #define ixgbe_for_each_ring(pos, head) \
330 for (pos = (head).ring; pos != NULL; pos = pos->next)
332 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
334 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
336 /* MAX_Q_VECTORS of these are allocated,
337 * but we only use one per queue-specific vector.
339 struct ixgbe_q_vector
{
340 struct ixgbe_adapter
*adapter
;
341 #ifdef CONFIG_IXGBE_DCA
342 int cpu
; /* CPU for DCA */
344 u16 v_idx
; /* index of q_vector within array, also used for
345 * finding the bit in EICR and friends that
346 * represents the vector for this ring */
347 u16 itr
; /* Interrupt throttle rate written to EITR */
348 struct ixgbe_ring_container rx
, tx
;
350 struct napi_struct napi
;
351 cpumask_t affinity_mask
;
353 struct rcu_head rcu
; /* to avoid race with update stats on free */
354 char name
[IFNAMSIZ
+ 9];
356 /* for dynamic allocation of rings associated with this q_vector */
357 struct ixgbe_ring ring
[0] ____cacheline_internodealigned_in_smp
;
359 #ifdef CONFIG_IXGBE_HWMON
361 #define IXGBE_HWMON_TYPE_LOC 0
362 #define IXGBE_HWMON_TYPE_TEMP 1
363 #define IXGBE_HWMON_TYPE_CAUTION 2
364 #define IXGBE_HWMON_TYPE_MAX 3
367 struct device_attribute dev_attr
;
369 struct ixgbe_thermal_diode_data
*sensor
;
374 struct device
*device
;
375 struct hwmon_attr
*hwmon_list
;
376 unsigned int n_hwmon
;
378 #endif /* CONFIG_IXGBE_HWMON */
381 * microsecond values for various ITR rates shifted by 2 to fit itr register
382 * with the first 3 bits reserved 0
384 #define IXGBE_MIN_RSC_ITR 24
385 #define IXGBE_100K_ITR 40
386 #define IXGBE_20K_ITR 200
387 #define IXGBE_10K_ITR 400
388 #define IXGBE_8K_ITR 500
390 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
391 static inline __le32
ixgbe_test_staterr(union ixgbe_adv_rx_desc
*rx_desc
,
392 const u32 stat_err_bits
)
394 return rx_desc
->wb
.upper
.status_error
& cpu_to_le32(stat_err_bits
);
397 static inline u16
ixgbe_desc_unused(struct ixgbe_ring
*ring
)
399 u16 ntc
= ring
->next_to_clean
;
400 u16 ntu
= ring
->next_to_use
;
402 return ((ntc
> ntu
) ? 0 : ring
->count
) + ntc
- ntu
- 1;
405 #define IXGBE_RX_DESC(R, i) \
406 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
407 #define IXGBE_TX_DESC(R, i) \
408 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
409 #define IXGBE_TX_CTXTDESC(R, i) \
410 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
412 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
414 /* Use 3K as the baby jumbo frame size for FCoE */
415 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
416 #endif /* IXGBE_FCOE */
418 #define OTHER_VECTOR 1
419 #define NON_Q_VECTORS (OTHER_VECTOR)
421 #define MAX_MSIX_VECTORS_82599 64
422 #define MAX_Q_VECTORS_82599 64
423 #define MAX_MSIX_VECTORS_82598 18
424 #define MAX_Q_VECTORS_82598 16
426 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599
427 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
429 #define MIN_MSIX_Q_VECTORS 1
430 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
432 /* default to trying for four seconds */
433 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
435 /* board specific private data structure */
436 struct ixgbe_adapter
{
437 unsigned long active_vlans
[BITS_TO_LONGS(VLAN_N_VID
)];
438 /* OS defined structs */
439 struct net_device
*netdev
;
440 struct pci_dev
*pdev
;
444 /* Some features need tri-state capability,
445 * thus the additional *_CAPABLE flags.
448 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 0)
449 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1)
450 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 2)
451 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3)
452 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4)
453 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5)
454 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6)
455 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 7)
456 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8)
457 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9)
458 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10)
459 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11)
460 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12)
461 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13)
462 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14)
463 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15)
464 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16)
465 #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17)
466 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18)
467 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19)
468 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20)
469 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21)
470 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22)
471 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23)
474 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0)
475 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
476 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
477 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
478 #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
479 #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
480 #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
481 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
482 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8)
483 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9)
484 #define IXGBE_FLAG2_PTP_ENABLED (u32)(1 << 10)
485 #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 11)
486 #define IXGBE_FLAG2_BRIDGE_MODE_VEB (u32)(1 << 12)
488 /* Tx fast path data */
493 /* Rx fast path data */
498 struct ixgbe_ring
*tx_ring
[MAX_TX_QUEUES
] ____cacheline_aligned_in_smp
;
502 u32 tx_timeout_count
;
505 struct ixgbe_ring
*rx_ring
[MAX_RX_QUEUES
];
506 int num_rx_pools
; /* == num_rx_queues in 82598 */
507 int num_rx_queues_per_pool
; /* 1 if 82598, can be many if 82599 */
508 u64 hw_csum_rx_error
;
509 u64 hw_rx_no_dma_resources
;
513 u32 alloc_rx_page_failed
;
514 u32 alloc_rx_buff_failed
;
516 struct ixgbe_q_vector
*q_vector
[MAX_Q_VECTORS
];
519 struct ieee_pfc
*ixgbe_ieee_pfc
;
520 struct ieee_ets
*ixgbe_ieee_ets
;
521 struct ixgbe_dcb_config dcb_cfg
;
522 struct ixgbe_dcb_config temp_dcb_cfg
;
525 enum ixgbe_fc_mode last_lfc_mode
;
527 int num_q_vectors
; /* current number of q_vectors for device */
528 int max_q_vectors
; /* true count of q_vectors for device */
529 struct ixgbe_ring_feature ring_feature
[RING_F_ARRAY_SIZE
];
530 struct msix_entry
*msix_entries
;
533 struct ixgbe_ring test_tx_ring
;
534 struct ixgbe_ring test_rx_ring
;
536 /* structs defined in ixgbe_hw.h */
539 struct ixgbe_hw_stats stats
;
542 unsigned int tx_ring_count
;
543 unsigned int rx_ring_count
;
547 unsigned long link_check_timeout
;
549 struct timer_list service_timer
;
550 struct work_struct service_task
;
552 struct hlist_head fdir_filter_list
;
553 unsigned long fdir_overflow
; /* number of times ATR was backed off */
554 union ixgbe_atr_input fdir_mask
;
555 int fdir_filter_count
;
558 spinlock_t fdir_perfect_lock
;
561 struct ixgbe_fcoe fcoe
;
562 #endif /* IXGBE_FCOE */
574 struct ptp_clock
*ptp_clock
;
575 struct ptp_clock_info ptp_caps
;
576 unsigned long last_overflow_check
;
577 spinlock_t tmreg_lock
;
578 struct cyclecounter cc
;
579 struct timecounter tc
;
580 int rx_hwtstamp_filter
;
584 DECLARE_BITMAP(active_vfs
, IXGBE_MAX_VF_FUNCTIONS
);
585 unsigned int num_vfs
;
586 struct vf_data_storage
*vfinfo
;
587 int vf_rate_link_speed
;
588 struct vf_macvlans vf_mvs
;
589 struct vf_macvlans
*mv_list
;
591 u32 timer_event_accumulator
;
593 struct kobject
*info_kobj
;
594 #ifdef CONFIG_IXGBE_HWMON
595 struct hwmon_buff ixgbe_hwmon_buff
;
596 #endif /* CONFIG_IXGBE_HWMON */
597 #ifdef CONFIG_DEBUG_FS
598 struct dentry
*ixgbe_dbg_adapter
;
599 #endif /*CONFIG_DEBUG_FS*/
604 struct ixgbe_fdir_filter
{
605 struct hlist_node fdir_node
;
606 union ixgbe_atr_input filter
;
615 __IXGBE_SERVICE_SCHED
,
620 union { /* Union defining head/tail partner */
621 struct sk_buff
*head
;
622 struct sk_buff
*tail
;
628 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
636 extern struct ixgbe_info ixgbe_82598_info
;
637 extern struct ixgbe_info ixgbe_82599_info
;
638 extern struct ixgbe_info ixgbe_X540_info
;
639 #ifdef CONFIG_IXGBE_DCB
640 extern const struct dcbnl_rtnl_ops dcbnl_ops
;
643 extern char ixgbe_driver_name
[];
644 extern const char ixgbe_driver_version
[];
646 extern char ixgbe_default_device_descr
[];
647 #endif /* IXGBE_FCOE */
649 extern void ixgbe_up(struct ixgbe_adapter
*adapter
);
650 extern void ixgbe_down(struct ixgbe_adapter
*adapter
);
651 extern void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
);
652 extern void ixgbe_reset(struct ixgbe_adapter
*adapter
);
653 extern void ixgbe_set_ethtool_ops(struct net_device
*netdev
);
654 extern int ixgbe_setup_rx_resources(struct ixgbe_ring
*);
655 extern int ixgbe_setup_tx_resources(struct ixgbe_ring
*);
656 extern void ixgbe_free_rx_resources(struct ixgbe_ring
*);
657 extern void ixgbe_free_tx_resources(struct ixgbe_ring
*);
658 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter
*,struct ixgbe_ring
*);
659 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter
*,struct ixgbe_ring
*);
660 extern void ixgbe_disable_rx_queue(struct ixgbe_adapter
*adapter
,
661 struct ixgbe_ring
*);
662 extern void ixgbe_update_stats(struct ixgbe_adapter
*adapter
);
663 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
);
664 extern int ixgbe_wol_supported(struct ixgbe_adapter
*adapter
, u16 device_id
,
666 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
);
667 extern netdev_tx_t
ixgbe_xmit_frame_ring(struct sk_buff
*,
668 struct ixgbe_adapter
*,
669 struct ixgbe_ring
*);
670 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring
*,
671 struct ixgbe_tx_buffer
*);
672 extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring
*, u16
);
673 extern void ixgbe_write_eitr(struct ixgbe_q_vector
*);
674 extern int ixgbe_poll(struct napi_struct
*napi
, int budget
);
675 extern int ethtool_ioctl(struct ifreq
*ifr
);
676 extern s32
ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw
*hw
);
677 extern s32
ixgbe_init_fdir_signature_82599(struct ixgbe_hw
*hw
, u32 fdirctrl
);
678 extern s32
ixgbe_init_fdir_perfect_82599(struct ixgbe_hw
*hw
, u32 fdirctrl
);
679 extern s32
ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw
*hw
,
680 union ixgbe_atr_hash_dword input
,
681 union ixgbe_atr_hash_dword common
,
683 extern s32
ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw
*hw
,
684 union ixgbe_atr_input
*input_mask
);
685 extern s32
ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw
*hw
,
686 union ixgbe_atr_input
*input
,
687 u16 soft_id
, u8 queue
);
688 extern s32
ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw
*hw
,
689 union ixgbe_atr_input
*input
,
691 extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input
*input
,
692 union ixgbe_atr_input
*mask
);
693 extern bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw
*hw
);
694 extern void ixgbe_set_rx_mode(struct net_device
*netdev
);
695 #ifdef CONFIG_IXGBE_DCB
696 extern void ixgbe_set_rx_drop_en(struct ixgbe_adapter
*adapter
);
697 extern int ixgbe_setup_tc(struct net_device
*dev
, u8 tc
);
699 extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring
*, u32
, u32
, u32
, u32
);
700 extern void ixgbe_do_reset(struct net_device
*netdev
);
701 #ifdef CONFIG_IXGBE_HWMON
702 extern void ixgbe_sysfs_exit(struct ixgbe_adapter
*adapter
);
703 extern int ixgbe_sysfs_init(struct ixgbe_adapter
*adapter
);
704 #endif /* CONFIG_IXGBE_HWMON */
706 extern void ixgbe_configure_fcoe(struct ixgbe_adapter
*adapter
);
707 extern int ixgbe_fso(struct ixgbe_ring
*tx_ring
,
708 struct ixgbe_tx_buffer
*first
,
710 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter
*adapter
,
711 union ixgbe_adv_rx_desc
*rx_desc
,
712 struct sk_buff
*skb
);
713 extern int ixgbe_fcoe_ddp_get(struct net_device
*netdev
, u16 xid
,
714 struct scatterlist
*sgl
, unsigned int sgc
);
715 extern int ixgbe_fcoe_ddp_target(struct net_device
*netdev
, u16 xid
,
716 struct scatterlist
*sgl
, unsigned int sgc
);
717 extern int ixgbe_fcoe_ddp_put(struct net_device
*netdev
, u16 xid
);
718 extern int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter
*adapter
);
719 extern void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter
*adapter
);
720 extern int ixgbe_fcoe_enable(struct net_device
*netdev
);
721 extern int ixgbe_fcoe_disable(struct net_device
*netdev
);
722 #ifdef CONFIG_IXGBE_DCB
723 extern u8
ixgbe_fcoe_getapp(struct ixgbe_adapter
*adapter
);
724 extern u8
ixgbe_fcoe_setapp(struct ixgbe_adapter
*adapter
, u8 up
);
725 #endif /* CONFIG_IXGBE_DCB */
726 extern int ixgbe_fcoe_get_wwn(struct net_device
*netdev
, u64
*wwn
, int type
);
727 extern int ixgbe_fcoe_get_hbainfo(struct net_device
*netdev
,
728 struct netdev_fcoe_hbainfo
*info
);
729 extern u8
ixgbe_fcoe_get_tc(struct ixgbe_adapter
*adapter
);
730 #endif /* IXGBE_FCOE */
731 #ifdef CONFIG_DEBUG_FS
732 extern void ixgbe_dbg_adapter_init(struct ixgbe_adapter
*adapter
);
733 extern void ixgbe_dbg_adapter_exit(struct ixgbe_adapter
*adapter
);
734 extern void ixgbe_dbg_init(void);
735 extern void ixgbe_dbg_exit(void);
736 #endif /* CONFIG_DEBUG_FS */
737 static inline struct netdev_queue
*txring_txq(const struct ixgbe_ring
*ring
)
739 return netdev_get_tx_queue(ring
->netdev
, ring
->queue_index
);
742 extern void ixgbe_ptp_init(struct ixgbe_adapter
*adapter
);
743 extern void ixgbe_ptp_stop(struct ixgbe_adapter
*adapter
);
744 extern void ixgbe_ptp_overflow_check(struct ixgbe_adapter
*adapter
);
745 extern void ixgbe_ptp_tx_hwtstamp(struct ixgbe_q_vector
*q_vector
,
746 struct sk_buff
*skb
);
747 extern void ixgbe_ptp_rx_hwtstamp(struct ixgbe_q_vector
*q_vector
,
748 union ixgbe_adv_rx_desc
*rx_desc
,
749 struct sk_buff
*skb
);
750 extern int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter
*adapter
,
751 struct ifreq
*ifr
, int cmd
);
752 extern void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter
*adapter
);
753 extern void ixgbe_ptp_reset(struct ixgbe_adapter
*adapter
);
754 extern void ixgbe_ptp_check_pps_event(struct ixgbe_adapter
*adapter
, u32 eicr
);
756 #endif /* _IXGBE_H_ */