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Merge tag 'powerpc-4.4-5' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_82598.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2014 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/pci.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
32
33 #include "ixgbe.h"
34 #include "ixgbe_phy.h"
35
36 #define IXGBE_82598_MAX_TX_QUEUES 32
37 #define IXGBE_82598_MAX_RX_QUEUES 64
38 #define IXGBE_82598_RAR_ENTRIES 16
39 #define IXGBE_82598_MC_TBL_SIZE 128
40 #define IXGBE_82598_VFT_TBL_SIZE 128
41 #define IXGBE_82598_RX_PB_SIZE 512
42
43 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
44 ixgbe_link_speed speed,
45 bool autoneg_wait_to_complete);
46 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
47 u8 *eeprom_data);
48
49 /**
50 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
51 * @hw: pointer to the HW structure
52 *
53 * The defaults for 82598 should be in the range of 50us to 50ms,
54 * however the hardware default for these parts is 500us to 1ms which is less
55 * than the 10ms recommended by the pci-e spec. To address this we need to
56 * increase the value to either 10ms to 250ms for capability version 1 config,
57 * or 16ms to 55ms for version 2.
58 **/
59 static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
60 {
61 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
62 u16 pcie_devctl2;
63
64 if (ixgbe_removed(hw->hw_addr))
65 return;
66
67 /* only take action if timeout value is defaulted to 0 */
68 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
69 goto out;
70
71 /*
72 * if capababilities version is type 1 we can write the
73 * timeout of 10ms to 250ms through the GCR register
74 */
75 if (!(gcr & IXGBE_GCR_CAP_VER2)) {
76 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
77 goto out;
78 }
79
80 /*
81 * for version 2 capabilities we need to write the config space
82 * directly in order to set the completion timeout value for
83 * 16ms to 55ms
84 */
85 pcie_devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2);
86 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
87 ixgbe_write_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
88 out:
89 /* disable completion timeout resend */
90 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
91 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
92 }
93
94 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
95 {
96 struct ixgbe_mac_info *mac = &hw->mac;
97
98 /* Call PHY identify routine to get the phy type */
99 ixgbe_identify_phy_generic(hw);
100
101 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
102 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
103 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
104 mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE;
105 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
106 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
107 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
108
109 return 0;
110 }
111
112 /**
113 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
114 * @hw: pointer to hardware structure
115 *
116 * Initialize any function pointers that were not able to be
117 * set during get_invariants because the PHY/SFP type was
118 * not known. Perform the SFP init if necessary.
119 *
120 **/
121 static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
122 {
123 struct ixgbe_mac_info *mac = &hw->mac;
124 struct ixgbe_phy_info *phy = &hw->phy;
125 s32 ret_val;
126 u16 list_offset, data_offset;
127
128 /* Identify the PHY */
129 phy->ops.identify(hw);
130
131 /* Overwrite the link function pointers if copper PHY */
132 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
133 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
134 mac->ops.get_link_capabilities =
135 &ixgbe_get_copper_link_capabilities_generic;
136 }
137
138 switch (hw->phy.type) {
139 case ixgbe_phy_tn:
140 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
141 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
142 phy->ops.get_firmware_version =
143 &ixgbe_get_phy_firmware_version_tnx;
144 break;
145 case ixgbe_phy_nl:
146 phy->ops.reset = &ixgbe_reset_phy_nl;
147
148 /* Call SFP+ identify routine to get the SFP+ module type */
149 ret_val = phy->ops.identify_sfp(hw);
150 if (ret_val)
151 return ret_val;
152 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
153 return IXGBE_ERR_SFP_NOT_SUPPORTED;
154
155 /* Check to see if SFP+ module is supported */
156 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
157 &list_offset,
158 &data_offset);
159 if (ret_val)
160 return IXGBE_ERR_SFP_NOT_SUPPORTED;
161 break;
162 default:
163 break;
164 }
165
166 return 0;
167 }
168
169 /**
170 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
171 * @hw: pointer to hardware structure
172 *
173 * Starts the hardware using the generic start_hw function.
174 * Disables relaxed ordering for archs other than SPARC
175 * Then set pcie completion timeout
176 *
177 **/
178 static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
179 {
180 #ifndef CONFIG_SPARC
181 u32 regval;
182 u32 i;
183 #endif
184 s32 ret_val;
185
186 ret_val = ixgbe_start_hw_generic(hw);
187
188 #ifndef CONFIG_SPARC
189 /* Disable relaxed ordering */
190 for (i = 0; ((i < hw->mac.max_tx_queues) &&
191 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
192 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
193 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
194 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
195 }
196
197 for (i = 0; ((i < hw->mac.max_rx_queues) &&
198 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
199 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
200 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
201 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
202 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
203 }
204 #endif
205 if (ret_val)
206 return ret_val;
207
208 /* set the completion timeout for interface */
209 ixgbe_set_pcie_completion_timeout(hw);
210
211 return 0;
212 }
213
214 /**
215 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
216 * @hw: pointer to hardware structure
217 * @speed: pointer to link speed
218 * @autoneg: boolean auto-negotiation value
219 *
220 * Determines the link capabilities by reading the AUTOC register.
221 **/
222 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
223 ixgbe_link_speed *speed,
224 bool *autoneg)
225 {
226 u32 autoc = 0;
227
228 /*
229 * Determine link capabilities based on the stored value of AUTOC,
230 * which represents EEPROM defaults. If AUTOC value has not been
231 * stored, use the current register value.
232 */
233 if (hw->mac.orig_link_settings_stored)
234 autoc = hw->mac.orig_autoc;
235 else
236 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
237
238 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
239 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
240 *speed = IXGBE_LINK_SPEED_1GB_FULL;
241 *autoneg = false;
242 break;
243
244 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
245 *speed = IXGBE_LINK_SPEED_10GB_FULL;
246 *autoneg = false;
247 break;
248
249 case IXGBE_AUTOC_LMS_1G_AN:
250 *speed = IXGBE_LINK_SPEED_1GB_FULL;
251 *autoneg = true;
252 break;
253
254 case IXGBE_AUTOC_LMS_KX4_AN:
255 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
256 *speed = IXGBE_LINK_SPEED_UNKNOWN;
257 if (autoc & IXGBE_AUTOC_KX4_SUPP)
258 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
259 if (autoc & IXGBE_AUTOC_KX_SUPP)
260 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
261 *autoneg = true;
262 break;
263
264 default:
265 return IXGBE_ERR_LINK_SETUP;
266 }
267
268 return 0;
269 }
270
271 /**
272 * ixgbe_get_media_type_82598 - Determines media type
273 * @hw: pointer to hardware structure
274 *
275 * Returns the media type (fiber, copper, backplane)
276 **/
277 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
278 {
279 /* Detect if there is a copper PHY attached. */
280 switch (hw->phy.type) {
281 case ixgbe_phy_cu_unknown:
282 case ixgbe_phy_tn:
283 return ixgbe_media_type_copper;
284
285 default:
286 break;
287 }
288
289 /* Media type for I82598 is based on device ID */
290 switch (hw->device_id) {
291 case IXGBE_DEV_ID_82598:
292 case IXGBE_DEV_ID_82598_BX:
293 /* Default device ID is mezzanine card KX/KX4 */
294 return ixgbe_media_type_backplane;
295
296 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
297 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
298 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
299 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
300 case IXGBE_DEV_ID_82598EB_XF_LR:
301 case IXGBE_DEV_ID_82598EB_SFP_LOM:
302 return ixgbe_media_type_fiber;
303
304 case IXGBE_DEV_ID_82598EB_CX4:
305 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
306 return ixgbe_media_type_cx4;
307
308 case IXGBE_DEV_ID_82598AT:
309 case IXGBE_DEV_ID_82598AT2:
310 return ixgbe_media_type_copper;
311
312 default:
313 return ixgbe_media_type_unknown;
314 }
315 }
316
317 /**
318 * ixgbe_fc_enable_82598 - Enable flow control
319 * @hw: pointer to hardware structure
320 *
321 * Enable flow control according to the current settings.
322 **/
323 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)
324 {
325 u32 fctrl_reg;
326 u32 rmcs_reg;
327 u32 reg;
328 u32 fcrtl, fcrth;
329 u32 link_speed = 0;
330 int i;
331 bool link_up;
332
333 /* Validate the water mark configuration */
334 if (!hw->fc.pause_time)
335 return IXGBE_ERR_INVALID_LINK_SETTINGS;
336
337 /* Low water mark of zero causes XOFF floods */
338 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
339 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
340 hw->fc.high_water[i]) {
341 if (!hw->fc.low_water[i] ||
342 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
343 hw_dbg(hw, "Invalid water mark configuration\n");
344 return IXGBE_ERR_INVALID_LINK_SETTINGS;
345 }
346 }
347 }
348
349 /*
350 * On 82598 having Rx FC on causes resets while doing 1G
351 * so if it's on turn it off once we know link_speed. For
352 * more details see 82598 Specification update.
353 */
354 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
355 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
356 switch (hw->fc.requested_mode) {
357 case ixgbe_fc_full:
358 hw->fc.requested_mode = ixgbe_fc_tx_pause;
359 break;
360 case ixgbe_fc_rx_pause:
361 hw->fc.requested_mode = ixgbe_fc_none;
362 break;
363 default:
364 /* no change */
365 break;
366 }
367 }
368
369 /* Negotiate the fc mode to use */
370 ixgbe_fc_autoneg(hw);
371
372 /* Disable any previous flow control settings */
373 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
374 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
375
376 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
377 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
378
379 /*
380 * The possible values of fc.current_mode are:
381 * 0: Flow control is completely disabled
382 * 1: Rx flow control is enabled (we can receive pause frames,
383 * but not send pause frames).
384 * 2: Tx flow control is enabled (we can send pause frames but
385 * we do not support receiving pause frames).
386 * 3: Both Rx and Tx flow control (symmetric) are enabled.
387 * other: Invalid.
388 */
389 switch (hw->fc.current_mode) {
390 case ixgbe_fc_none:
391 /*
392 * Flow control is disabled by software override or autoneg.
393 * The code below will actually disable it in the HW.
394 */
395 break;
396 case ixgbe_fc_rx_pause:
397 /*
398 * Rx Flow control is enabled and Tx Flow control is
399 * disabled by software override. Since there really
400 * isn't a way to advertise that we are capable of RX
401 * Pause ONLY, we will advertise that we support both
402 * symmetric and asymmetric Rx PAUSE. Later, we will
403 * disable the adapter's ability to send PAUSE frames.
404 */
405 fctrl_reg |= IXGBE_FCTRL_RFCE;
406 break;
407 case ixgbe_fc_tx_pause:
408 /*
409 * Tx Flow control is enabled, and Rx Flow control is
410 * disabled by software override.
411 */
412 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
413 break;
414 case ixgbe_fc_full:
415 /* Flow control (both Rx and Tx) is enabled by SW override. */
416 fctrl_reg |= IXGBE_FCTRL_RFCE;
417 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
418 break;
419 default:
420 hw_dbg(hw, "Flow control param set incorrectly\n");
421 return IXGBE_ERR_CONFIG;
422 }
423
424 /* Set 802.3x based flow control settings. */
425 fctrl_reg |= IXGBE_FCTRL_DPF;
426 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
427 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
428
429 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
430 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
431 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
432 hw->fc.high_water[i]) {
433 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
434 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
435 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
436 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);
437 } else {
438 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
439 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
440 }
441
442 }
443
444 /* Configure pause time (2 TCs per register) */
445 reg = hw->fc.pause_time * 0x00010001;
446 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
447 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
448
449 /* Configure flow control refresh threshold value */
450 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
451
452 return 0;
453 }
454
455 /**
456 * ixgbe_start_mac_link_82598 - Configures MAC link settings
457 * @hw: pointer to hardware structure
458 *
459 * Configures link settings based on values in the ixgbe_hw struct.
460 * Restarts the link. Performs autonegotiation if needed.
461 **/
462 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
463 bool autoneg_wait_to_complete)
464 {
465 u32 autoc_reg;
466 u32 links_reg;
467 u32 i;
468 s32 status = 0;
469
470 /* Restart link */
471 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
472 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
473 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
474
475 /* Only poll for autoneg to complete if specified to do so */
476 if (autoneg_wait_to_complete) {
477 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
478 IXGBE_AUTOC_LMS_KX4_AN ||
479 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
480 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
481 links_reg = 0; /* Just in case Autoneg time = 0 */
482 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
483 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
484 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
485 break;
486 msleep(100);
487 }
488 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
489 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
490 hw_dbg(hw, "Autonegotiation did not complete.\n");
491 }
492 }
493 }
494
495 /* Add delay to filter out noises during initial link setup */
496 msleep(50);
497
498 return status;
499 }
500
501 /**
502 * ixgbe_validate_link_ready - Function looks for phy link
503 * @hw: pointer to hardware structure
504 *
505 * Function indicates success when phy link is available. If phy is not ready
506 * within 5 seconds of MAC indicating link, the function returns error.
507 **/
508 static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)
509 {
510 u32 timeout;
511 u16 an_reg;
512
513 if (hw->device_id != IXGBE_DEV_ID_82598AT2)
514 return 0;
515
516 for (timeout = 0;
517 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
518 hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg);
519
520 if ((an_reg & MDIO_AN_STAT1_COMPLETE) &&
521 (an_reg & MDIO_STAT1_LSTATUS))
522 break;
523
524 msleep(100);
525 }
526
527 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {
528 hw_dbg(hw, "Link was indicated but link is down\n");
529 return IXGBE_ERR_LINK_SETUP;
530 }
531
532 return 0;
533 }
534
535 /**
536 * ixgbe_check_mac_link_82598 - Get link/speed status
537 * @hw: pointer to hardware structure
538 * @speed: pointer to link speed
539 * @link_up: true is link is up, false otherwise
540 * @link_up_wait_to_complete: bool used to wait for link up or not
541 *
542 * Reads the links register to determine if link is up and the current speed
543 **/
544 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
545 ixgbe_link_speed *speed, bool *link_up,
546 bool link_up_wait_to_complete)
547 {
548 u32 links_reg;
549 u32 i;
550 u16 link_reg, adapt_comp_reg;
551
552 /*
553 * SERDES PHY requires us to read link status from register 0xC79F.
554 * Bit 0 set indicates link is up/ready; clear indicates link down.
555 * 0xC00C is read to check that the XAUI lanes are active. Bit 0
556 * clear indicates active; set indicates inactive.
557 */
558 if (hw->phy.type == ixgbe_phy_nl) {
559 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
560 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
561 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD,
562 &adapt_comp_reg);
563 if (link_up_wait_to_complete) {
564 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
565 if ((link_reg & 1) &&
566 ((adapt_comp_reg & 1) == 0)) {
567 *link_up = true;
568 break;
569 } else {
570 *link_up = false;
571 }
572 msleep(100);
573 hw->phy.ops.read_reg(hw, 0xC79F,
574 MDIO_MMD_PMAPMD,
575 &link_reg);
576 hw->phy.ops.read_reg(hw, 0xC00C,
577 MDIO_MMD_PMAPMD,
578 &adapt_comp_reg);
579 }
580 } else {
581 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
582 *link_up = true;
583 else
584 *link_up = false;
585 }
586
587 if (!*link_up)
588 return 0;
589 }
590
591 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
592 if (link_up_wait_to_complete) {
593 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
594 if (links_reg & IXGBE_LINKS_UP) {
595 *link_up = true;
596 break;
597 } else {
598 *link_up = false;
599 }
600 msleep(100);
601 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
602 }
603 } else {
604 if (links_reg & IXGBE_LINKS_UP)
605 *link_up = true;
606 else
607 *link_up = false;
608 }
609
610 if (links_reg & IXGBE_LINKS_SPEED)
611 *speed = IXGBE_LINK_SPEED_10GB_FULL;
612 else
613 *speed = IXGBE_LINK_SPEED_1GB_FULL;
614
615 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && *link_up &&
616 (ixgbe_validate_link_ready(hw) != 0))
617 *link_up = false;
618
619 return 0;
620 }
621
622 /**
623 * ixgbe_setup_mac_link_82598 - Set MAC link speed
624 * @hw: pointer to hardware structure
625 * @speed: new link speed
626 * @autoneg_wait_to_complete: true when waiting for completion is needed
627 *
628 * Set the link speed in the AUTOC register and restarts link.
629 **/
630 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
631 ixgbe_link_speed speed,
632 bool autoneg_wait_to_complete)
633 {
634 bool autoneg = false;
635 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
636 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
637 u32 autoc = curr_autoc;
638 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
639
640 /* Check to see if speed passed in is supported. */
641 ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
642 speed &= link_capabilities;
643
644 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
645 return IXGBE_ERR_LINK_SETUP;
646
647 /* Set KX4/KX support according to speed requested */
648 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
649 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
650 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
651 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
652 autoc |= IXGBE_AUTOC_KX4_SUPP;
653 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
654 autoc |= IXGBE_AUTOC_KX_SUPP;
655 if (autoc != curr_autoc)
656 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
657 }
658
659 /* Setup and restart the link based on the new values in
660 * ixgbe_hw This will write the AUTOC register based on the new
661 * stored values
662 */
663 return ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
664 }
665
666
667 /**
668 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
669 * @hw: pointer to hardware structure
670 * @speed: new link speed
671 * @autoneg_wait_to_complete: true if waiting is needed to complete
672 *
673 * Sets the link speed in the AUTOC register in the MAC and restarts link.
674 **/
675 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
676 ixgbe_link_speed speed,
677 bool autoneg_wait_to_complete)
678 {
679 s32 status;
680
681 /* Setup the PHY according to input speed */
682 status = hw->phy.ops.setup_link_speed(hw, speed,
683 autoneg_wait_to_complete);
684 /* Set up MAC */
685 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
686
687 return status;
688 }
689
690 /**
691 * ixgbe_reset_hw_82598 - Performs hardware reset
692 * @hw: pointer to hardware structure
693 *
694 * Resets the hardware by resetting the transmit and receive units, masks and
695 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
696 * reset.
697 **/
698 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
699 {
700 s32 status;
701 s32 phy_status = 0;
702 u32 ctrl;
703 u32 gheccr;
704 u32 i;
705 u32 autoc;
706 u8 analog_val;
707
708 /* Call adapter stop to disable tx/rx and clear interrupts */
709 status = hw->mac.ops.stop_adapter(hw);
710 if (status)
711 return status;
712
713 /*
714 * Power up the Atlas Tx lanes if they are currently powered down.
715 * Atlas Tx lanes are powered down for MAC loopback tests, but
716 * they are not automatically restored on reset.
717 */
718 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
719 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
720 /* Enable Tx Atlas so packets can be transmitted again */
721 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
722 &analog_val);
723 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
724 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
725 analog_val);
726
727 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
728 &analog_val);
729 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
730 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
731 analog_val);
732
733 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
734 &analog_val);
735 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
736 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
737 analog_val);
738
739 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
740 &analog_val);
741 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
742 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
743 analog_val);
744 }
745
746 /* Reset PHY */
747 if (hw->phy.reset_disable == false) {
748 /* PHY ops must be identified and initialized prior to reset */
749
750 /* Init PHY and function pointers, perform SFP setup */
751 phy_status = hw->phy.ops.init(hw);
752 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
753 return phy_status;
754 if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
755 goto mac_reset_top;
756
757 hw->phy.ops.reset(hw);
758 }
759
760 mac_reset_top:
761 /*
762 * Issue global reset to the MAC. This needs to be a SW reset.
763 * If link reset is used, it might reset the MAC when mng is using it
764 */
765 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;
766 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
767 IXGBE_WRITE_FLUSH(hw);
768
769 /* Poll for reset bit to self-clear indicating reset is complete */
770 for (i = 0; i < 10; i++) {
771 udelay(1);
772 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
773 if (!(ctrl & IXGBE_CTRL_RST))
774 break;
775 }
776 if (ctrl & IXGBE_CTRL_RST) {
777 status = IXGBE_ERR_RESET_FAILED;
778 hw_dbg(hw, "Reset polling failed to complete.\n");
779 }
780
781 msleep(50);
782
783 /*
784 * Double resets are required for recovery from certain error
785 * conditions. Between resets, it is necessary to stall to allow time
786 * for any pending HW events to complete.
787 */
788 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
789 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
790 goto mac_reset_top;
791 }
792
793 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
794 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
795 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
796
797 /*
798 * Store the original AUTOC value if it has not been
799 * stored off yet. Otherwise restore the stored original
800 * AUTOC value since the reset operation sets back to deaults.
801 */
802 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
803 if (hw->mac.orig_link_settings_stored == false) {
804 hw->mac.orig_autoc = autoc;
805 hw->mac.orig_link_settings_stored = true;
806 } else if (autoc != hw->mac.orig_autoc) {
807 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
808 }
809
810 /* Store the permanent mac address */
811 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
812
813 /*
814 * Store MAC address from RAR0, clear receive address registers, and
815 * clear the multicast table
816 */
817 hw->mac.ops.init_rx_addrs(hw);
818
819 if (phy_status)
820 status = phy_status;
821
822 return status;
823 }
824
825 /**
826 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
827 * @hw: pointer to hardware struct
828 * @rar: receive address register index to associate with a VMDq index
829 * @vmdq: VMDq set index
830 **/
831 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
832 {
833 u32 rar_high;
834 u32 rar_entries = hw->mac.num_rar_entries;
835
836 /* Make sure we are using a valid rar index range */
837 if (rar >= rar_entries) {
838 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
839 return IXGBE_ERR_INVALID_ARGUMENT;
840 }
841
842 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
843 rar_high &= ~IXGBE_RAH_VIND_MASK;
844 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
845 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
846 return 0;
847 }
848
849 /**
850 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
851 * @hw: pointer to hardware struct
852 * @rar: receive address register index to associate with a VMDq index
853 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
854 **/
855 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
856 {
857 u32 rar_high;
858 u32 rar_entries = hw->mac.num_rar_entries;
859
860
861 /* Make sure we are using a valid rar index range */
862 if (rar >= rar_entries) {
863 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
864 return IXGBE_ERR_INVALID_ARGUMENT;
865 }
866
867 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
868 if (rar_high & IXGBE_RAH_VIND_MASK) {
869 rar_high &= ~IXGBE_RAH_VIND_MASK;
870 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
871 }
872
873 return 0;
874 }
875
876 /**
877 * ixgbe_set_vfta_82598 - Set VLAN filter table
878 * @hw: pointer to hardware structure
879 * @vlan: VLAN id to write to VLAN filter
880 * @vind: VMDq output index that maps queue to VLAN id in VFTA
881 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
882 *
883 * Turn on/off specified VLAN in the VLAN filter table.
884 **/
885 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
886 bool vlan_on)
887 {
888 u32 regindex;
889 u32 bitindex;
890 u32 bits;
891 u32 vftabyte;
892
893 if (vlan > 4095)
894 return IXGBE_ERR_PARAM;
895
896 /* Determine 32-bit word position in array */
897 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
898
899 /* Determine the location of the (VMD) queue index */
900 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
901 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
902
903 /* Set the nibble for VMD queue index */
904 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
905 bits &= (~(0x0F << bitindex));
906 bits |= (vind << bitindex);
907 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
908
909 /* Determine the location of the bit for this VLAN id */
910 bitindex = vlan & 0x1F; /* lower five bits */
911
912 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
913 if (vlan_on)
914 /* Turn on this VLAN id */
915 bits |= (1 << bitindex);
916 else
917 /* Turn off this VLAN id */
918 bits &= ~(1 << bitindex);
919 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
920
921 return 0;
922 }
923
924 /**
925 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
926 * @hw: pointer to hardware structure
927 *
928 * Clears the VLAN filer table, and the VMDq index associated with the filter
929 **/
930 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
931 {
932 u32 offset;
933 u32 vlanbyte;
934
935 for (offset = 0; offset < hw->mac.vft_size; offset++)
936 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
937
938 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
939 for (offset = 0; offset < hw->mac.vft_size; offset++)
940 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
941 0);
942
943 return 0;
944 }
945
946 /**
947 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
948 * @hw: pointer to hardware structure
949 * @reg: analog register to read
950 * @val: read value
951 *
952 * Performs read operation to Atlas analog register specified.
953 **/
954 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
955 {
956 u32 atlas_ctl;
957
958 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
959 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
960 IXGBE_WRITE_FLUSH(hw);
961 udelay(10);
962 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
963 *val = (u8)atlas_ctl;
964
965 return 0;
966 }
967
968 /**
969 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
970 * @hw: pointer to hardware structure
971 * @reg: atlas register to write
972 * @val: value to write
973 *
974 * Performs write operation to Atlas analog register specified.
975 **/
976 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
977 {
978 u32 atlas_ctl;
979
980 atlas_ctl = (reg << 8) | val;
981 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
982 IXGBE_WRITE_FLUSH(hw);
983 udelay(10);
984
985 return 0;
986 }
987
988 /**
989 * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface.
990 * @hw: pointer to hardware structure
991 * @dev_addr: address to read from
992 * @byte_offset: byte offset to read from dev_addr
993 * @eeprom_data: value read
994 *
995 * Performs 8 byte read operation to SFP module's data over I2C interface.
996 **/
997 static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,
998 u8 byte_offset, u8 *eeprom_data)
999 {
1000 s32 status = 0;
1001 u16 sfp_addr = 0;
1002 u16 sfp_data = 0;
1003 u16 sfp_stat = 0;
1004 u16 gssr;
1005 u32 i;
1006
1007 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1008 gssr = IXGBE_GSSR_PHY1_SM;
1009 else
1010 gssr = IXGBE_GSSR_PHY0_SM;
1011
1012 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
1013 return IXGBE_ERR_SWFW_SYNC;
1014
1015 if (hw->phy.type == ixgbe_phy_nl) {
1016 /*
1017 * phy SDA/SCL registers are at addresses 0xC30A to
1018 * 0xC30D. These registers are used to talk to the SFP+
1019 * module's EEPROM through the SDA/SCL (I2C) interface.
1020 */
1021 sfp_addr = (dev_addr << 8) + byte_offset;
1022 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1023 hw->phy.ops.write_reg_mdi(hw,
1024 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1025 MDIO_MMD_PMAPMD,
1026 sfp_addr);
1027
1028 /* Poll status */
1029 for (i = 0; i < 100; i++) {
1030 hw->phy.ops.read_reg_mdi(hw,
1031 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1032 MDIO_MMD_PMAPMD,
1033 &sfp_stat);
1034 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1035 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1036 break;
1037 usleep_range(10000, 20000);
1038 }
1039
1040 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1041 hw_dbg(hw, "EEPROM read did not pass.\n");
1042 status = IXGBE_ERR_SFP_NOT_PRESENT;
1043 goto out;
1044 }
1045
1046 /* Read data */
1047 hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1048 MDIO_MMD_PMAPMD, &sfp_data);
1049
1050 *eeprom_data = (u8)(sfp_data >> 8);
1051 } else {
1052 status = IXGBE_ERR_PHY;
1053 }
1054
1055 out:
1056 hw->mac.ops.release_swfw_sync(hw, gssr);
1057 return status;
1058 }
1059
1060 /**
1061 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1062 * @hw: pointer to hardware structure
1063 * @byte_offset: EEPROM byte offset to read
1064 * @eeprom_data: value read
1065 *
1066 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1067 **/
1068 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1069 u8 *eeprom_data)
1070 {
1071 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR,
1072 byte_offset, eeprom_data);
1073 }
1074
1075 /**
1076 * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface.
1077 * @hw: pointer to hardware structure
1078 * @byte_offset: byte offset at address 0xA2
1079 * @eeprom_data: value read
1080 *
1081 * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C
1082 **/
1083 static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,
1084 u8 *sff8472_data)
1085 {
1086 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2,
1087 byte_offset, sff8472_data);
1088 }
1089
1090 /**
1091 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
1092 * port devices.
1093 * @hw: pointer to the HW structure
1094 *
1095 * Calls common function and corrects issue with some single port devices
1096 * that enable LAN1 but not LAN0.
1097 **/
1098 static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
1099 {
1100 struct ixgbe_bus_info *bus = &hw->bus;
1101 u16 pci_gen = 0;
1102 u16 pci_ctrl2 = 0;
1103
1104 ixgbe_set_lan_id_multi_port_pcie(hw);
1105
1106 /* check if LAN0 is disabled */
1107 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
1108 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
1109
1110 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
1111
1112 /* if LAN0 is completely disabled force function to 0 */
1113 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&
1114 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&
1115 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {
1116
1117 bus->func = 0;
1118 }
1119 }
1120 }
1121
1122 /**
1123 * ixgbe_set_rxpba_82598 - Initialize RX packet buffer
1124 * @hw: pointer to hardware structure
1125 * @num_pb: number of packet buffers to allocate
1126 * @headroom: reserve n KB of headroom
1127 * @strategy: packet buffer allocation strategy
1128 **/
1129 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
1130 u32 headroom, int strategy)
1131 {
1132 u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
1133 u8 i = 0;
1134
1135 if (!num_pb)
1136 return;
1137
1138 /* Setup Rx packet buffer sizes */
1139 switch (strategy) {
1140 case PBA_STRATEGY_WEIGHTED:
1141 /* Setup the first four at 80KB */
1142 rxpktsize = IXGBE_RXPBSIZE_80KB;
1143 for (; i < 4; i++)
1144 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1145 /* Setup the last four at 48KB...don't re-init i */
1146 rxpktsize = IXGBE_RXPBSIZE_48KB;
1147 /* Fall Through */
1148 case PBA_STRATEGY_EQUAL:
1149 default:
1150 /* Divide the remaining Rx packet buffer evenly among the TCs */
1151 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1152 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1153 break;
1154 }
1155
1156 /* Setup Tx packet buffer sizes */
1157 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1158 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
1159 }
1160
1161 static struct ixgbe_mac_operations mac_ops_82598 = {
1162 .init_hw = &ixgbe_init_hw_generic,
1163 .reset_hw = &ixgbe_reset_hw_82598,
1164 .start_hw = &ixgbe_start_hw_82598,
1165 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1166 .get_media_type = &ixgbe_get_media_type_82598,
1167 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
1168 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1169 .stop_adapter = &ixgbe_stop_adapter_generic,
1170 .get_bus_info = &ixgbe_get_bus_info_generic,
1171 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598,
1172 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
1173 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
1174 .setup_link = &ixgbe_setup_mac_link_82598,
1175 .set_rxpba = &ixgbe_set_rxpba_82598,
1176 .check_link = &ixgbe_check_mac_link_82598,
1177 .get_link_capabilities = &ixgbe_get_link_capabilities_82598,
1178 .led_on = &ixgbe_led_on_generic,
1179 .led_off = &ixgbe_led_off_generic,
1180 .blink_led_start = &ixgbe_blink_led_start_generic,
1181 .blink_led_stop = &ixgbe_blink_led_stop_generic,
1182 .set_rar = &ixgbe_set_rar_generic,
1183 .clear_rar = &ixgbe_clear_rar_generic,
1184 .set_vmdq = &ixgbe_set_vmdq_82598,
1185 .clear_vmdq = &ixgbe_clear_vmdq_82598,
1186 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1187 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1188 .enable_mc = &ixgbe_enable_mc_generic,
1189 .disable_mc = &ixgbe_disable_mc_generic,
1190 .clear_vfta = &ixgbe_clear_vfta_82598,
1191 .set_vfta = &ixgbe_set_vfta_82598,
1192 .fc_enable = &ixgbe_fc_enable_82598,
1193 .set_fw_drv_ver = NULL,
1194 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
1195 .release_swfw_sync = &ixgbe_release_swfw_sync,
1196 .get_thermal_sensor_data = NULL,
1197 .init_thermal_sensor_thresh = NULL,
1198 .prot_autoc_read = &prot_autoc_read_generic,
1199 .prot_autoc_write = &prot_autoc_write_generic,
1200 .enable_rx = &ixgbe_enable_rx_generic,
1201 .disable_rx = &ixgbe_disable_rx_generic,
1202 };
1203
1204 static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1205 .init_params = &ixgbe_init_eeprom_params_generic,
1206 .read = &ixgbe_read_eerd_generic,
1207 .write = &ixgbe_write_eeprom_generic,
1208 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
1209 .read_buffer = &ixgbe_read_eerd_buffer_generic,
1210 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
1211 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1212 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1213 };
1214
1215 static struct ixgbe_phy_operations phy_ops_82598 = {
1216 .identify = &ixgbe_identify_phy_generic,
1217 .identify_sfp = &ixgbe_identify_module_generic,
1218 .init = &ixgbe_init_phy_ops_82598,
1219 .reset = &ixgbe_reset_phy_generic,
1220 .read_reg = &ixgbe_read_phy_reg_generic,
1221 .write_reg = &ixgbe_write_phy_reg_generic,
1222 .read_reg_mdi = &ixgbe_read_phy_reg_mdi,
1223 .write_reg_mdi = &ixgbe_write_phy_reg_mdi,
1224 .setup_link = &ixgbe_setup_phy_link_generic,
1225 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1226 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_82598,
1227 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598,
1228 .check_overtemp = &ixgbe_tn_check_overtemp,
1229 };
1230
1231 struct ixgbe_info ixgbe_82598_info = {
1232 .mac = ixgbe_mac_82598EB,
1233 .get_invariants = &ixgbe_get_invariants_82598,
1234 .mac_ops = &mac_ops_82598,
1235 .eeprom_ops = &eeprom_ops_82598,
1236 .phy_ops = &phy_ops_82598,
1237 .mvals = ixgbe_mvals_8259X,
1238 };
Linux kernel - Deliverables
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