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ixgbe: add SFP+ LX module support
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_82599.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
35
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41 #define IXGBE_82599_RX_PB_SIZE 512
42
43 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed,
48 bool autoneg_wait_to_complete);
49 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
51 bool autoneg_wait_to_complete);
52 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
53 bool autoneg_wait_to_complete);
54 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
55 ixgbe_link_speed speed,
56 bool autoneg_wait_to_complete);
57 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
58 ixgbe_link_speed speed,
59 bool autoneg_wait_to_complete);
60 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
61
62 static bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
63 {
64 u32 fwsm, manc, factps;
65
66 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
67 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
68 return false;
69
70 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
71 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
72 return false;
73
74 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
75 if (factps & IXGBE_FACTPS_MNGCG)
76 return false;
77
78 return true;
79 }
80
81 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
82 {
83 struct ixgbe_mac_info *mac = &hw->mac;
84
85 /* enable the laser control functions for SFP+ fiber
86 * and MNG not enabled
87 */
88 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
89 !hw->mng_fw_enabled) {
90 mac->ops.disable_tx_laser =
91 &ixgbe_disable_tx_laser_multispeed_fiber;
92 mac->ops.enable_tx_laser =
93 &ixgbe_enable_tx_laser_multispeed_fiber;
94 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
95 } else {
96 mac->ops.disable_tx_laser = NULL;
97 mac->ops.enable_tx_laser = NULL;
98 mac->ops.flap_tx_laser = NULL;
99 }
100
101 if (hw->phy.multispeed_fiber) {
102 /* Set up dual speed SFP+ support */
103 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
104 } else {
105 if ((mac->ops.get_media_type(hw) ==
106 ixgbe_media_type_backplane) &&
107 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
108 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
109 !ixgbe_verify_lesm_fw_enabled_82599(hw))
110 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
111 else
112 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
113 }
114 }
115
116 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
117 {
118 s32 ret_val = 0;
119 u16 list_offset, data_offset, data_value;
120 bool got_lock = false;
121
122 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
123 ixgbe_init_mac_link_ops_82599(hw);
124
125 hw->phy.ops.reset = NULL;
126
127 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
128 &data_offset);
129 if (ret_val != 0)
130 goto setup_sfp_out;
131
132 /* PHY config will finish before releasing the semaphore */
133 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
134 IXGBE_GSSR_MAC_CSR_SM);
135 if (ret_val != 0) {
136 ret_val = IXGBE_ERR_SWFW_SYNC;
137 goto setup_sfp_out;
138 }
139
140 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
141 while (data_value != 0xffff) {
142 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
143 IXGBE_WRITE_FLUSH(hw);
144 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
145 }
146
147 /* Release the semaphore */
148 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
149 /*
150 * Delay obtaining semaphore again to allow FW access,
151 * semaphore_delay is in ms usleep_range needs us.
152 */
153 usleep_range(hw->eeprom.semaphore_delay * 1000,
154 hw->eeprom.semaphore_delay * 2000);
155
156 /* Need SW/FW semaphore around AUTOC writes if LESM on,
157 * likewise reset_pipeline requires lock as it also writes
158 * AUTOC.
159 */
160 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
161 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
162 IXGBE_GSSR_MAC_CSR_SM);
163 if (ret_val)
164 goto setup_sfp_out;
165
166 got_lock = true;
167 }
168
169 /* Restart DSP and set SFI mode */
170 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
171 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL));
172
173 ret_val = ixgbe_reset_pipeline_82599(hw);
174
175 if (got_lock) {
176 hw->mac.ops.release_swfw_sync(hw,
177 IXGBE_GSSR_MAC_CSR_SM);
178 got_lock = false;
179 }
180
181 if (ret_val) {
182 hw_dbg(hw, " sfp module setup not complete\n");
183 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
184 goto setup_sfp_out;
185 }
186 }
187
188 setup_sfp_out:
189 return ret_val;
190 }
191
192 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
193 {
194 struct ixgbe_mac_info *mac = &hw->mac;
195
196 ixgbe_init_mac_link_ops_82599(hw);
197
198 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
199 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
200 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
201 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
202 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
203 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
204
205 return 0;
206 }
207
208 /**
209 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
210 * @hw: pointer to hardware structure
211 *
212 * Initialize any function pointers that were not able to be
213 * set during get_invariants because the PHY/SFP type was
214 * not known. Perform the SFP init if necessary.
215 *
216 **/
217 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
218 {
219 struct ixgbe_mac_info *mac = &hw->mac;
220 struct ixgbe_phy_info *phy = &hw->phy;
221 s32 ret_val = 0;
222
223 /* Identify the PHY or SFP module */
224 ret_val = phy->ops.identify(hw);
225
226 /* Setup function pointers based on detected SFP module and speeds */
227 ixgbe_init_mac_link_ops_82599(hw);
228
229 /* If copper media, overwrite with copper function pointers */
230 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
231 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
232 mac->ops.get_link_capabilities =
233 &ixgbe_get_copper_link_capabilities_generic;
234 }
235
236 /* Set necessary function pointers based on phy type */
237 switch (hw->phy.type) {
238 case ixgbe_phy_tn:
239 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
240 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
241 phy->ops.get_firmware_version =
242 &ixgbe_get_phy_firmware_version_tnx;
243 break;
244 default:
245 break;
246 }
247
248 return ret_val;
249 }
250
251 /**
252 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
253 * @hw: pointer to hardware structure
254 * @speed: pointer to link speed
255 * @autoneg: true when autoneg or autotry is enabled
256 *
257 * Determines the link capabilities by reading the AUTOC register.
258 **/
259 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
260 ixgbe_link_speed *speed,
261 bool *autoneg)
262 {
263 s32 status = 0;
264 u32 autoc = 0;
265
266 /* Determine 1G link capabilities off of SFP+ type */
267 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
268 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
269 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
270 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
271 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
272 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
273 *speed = IXGBE_LINK_SPEED_1GB_FULL;
274 *autoneg = true;
275 goto out;
276 }
277
278 /*
279 * Determine link capabilities based on the stored value of AUTOC,
280 * which represents EEPROM defaults. If AUTOC value has not been
281 * stored, use the current register value.
282 */
283 if (hw->mac.orig_link_settings_stored)
284 autoc = hw->mac.orig_autoc;
285 else
286 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
287
288 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
289 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
290 *speed = IXGBE_LINK_SPEED_1GB_FULL;
291 *autoneg = false;
292 break;
293
294 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
295 *speed = IXGBE_LINK_SPEED_10GB_FULL;
296 *autoneg = false;
297 break;
298
299 case IXGBE_AUTOC_LMS_1G_AN:
300 *speed = IXGBE_LINK_SPEED_1GB_FULL;
301 *autoneg = true;
302 break;
303
304 case IXGBE_AUTOC_LMS_10G_SERIAL:
305 *speed = IXGBE_LINK_SPEED_10GB_FULL;
306 *autoneg = false;
307 break;
308
309 case IXGBE_AUTOC_LMS_KX4_KX_KR:
310 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
311 *speed = IXGBE_LINK_SPEED_UNKNOWN;
312 if (autoc & IXGBE_AUTOC_KR_SUPP)
313 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
314 if (autoc & IXGBE_AUTOC_KX4_SUPP)
315 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
316 if (autoc & IXGBE_AUTOC_KX_SUPP)
317 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
318 *autoneg = true;
319 break;
320
321 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
322 *speed = IXGBE_LINK_SPEED_100_FULL;
323 if (autoc & IXGBE_AUTOC_KR_SUPP)
324 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
325 if (autoc & IXGBE_AUTOC_KX4_SUPP)
326 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
327 if (autoc & IXGBE_AUTOC_KX_SUPP)
328 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
329 *autoneg = true;
330 break;
331
332 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
333 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
334 *autoneg = false;
335 break;
336
337 default:
338 status = IXGBE_ERR_LINK_SETUP;
339 goto out;
340 break;
341 }
342
343 if (hw->phy.multispeed_fiber) {
344 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
345 IXGBE_LINK_SPEED_1GB_FULL;
346 *autoneg = true;
347 }
348
349 out:
350 return status;
351 }
352
353 /**
354 * ixgbe_get_media_type_82599 - Get media type
355 * @hw: pointer to hardware structure
356 *
357 * Returns the media type (fiber, copper, backplane)
358 **/
359 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
360 {
361 enum ixgbe_media_type media_type;
362
363 /* Detect if there is a copper PHY attached. */
364 switch (hw->phy.type) {
365 case ixgbe_phy_cu_unknown:
366 case ixgbe_phy_tn:
367 media_type = ixgbe_media_type_copper;
368 goto out;
369 default:
370 break;
371 }
372
373 switch (hw->device_id) {
374 case IXGBE_DEV_ID_82599_KX4:
375 case IXGBE_DEV_ID_82599_KX4_MEZZ:
376 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
377 case IXGBE_DEV_ID_82599_KR:
378 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
379 case IXGBE_DEV_ID_82599_XAUI_LOM:
380 /* Default device ID is mezzanine card KX/KX4 */
381 media_type = ixgbe_media_type_backplane;
382 break;
383 case IXGBE_DEV_ID_82599_SFP:
384 case IXGBE_DEV_ID_82599_SFP_FCOE:
385 case IXGBE_DEV_ID_82599_SFP_EM:
386 case IXGBE_DEV_ID_82599_SFP_SF2:
387 case IXGBE_DEV_ID_82599_SFP_SF_QP:
388 case IXGBE_DEV_ID_82599EN_SFP:
389 media_type = ixgbe_media_type_fiber;
390 break;
391 case IXGBE_DEV_ID_82599_CX4:
392 media_type = ixgbe_media_type_cx4;
393 break;
394 case IXGBE_DEV_ID_82599_T3_LOM:
395 media_type = ixgbe_media_type_copper;
396 break;
397 case IXGBE_DEV_ID_82599_LS:
398 media_type = ixgbe_media_type_fiber_lco;
399 break;
400 default:
401 media_type = ixgbe_media_type_unknown;
402 break;
403 }
404 out:
405 return media_type;
406 }
407
408 /**
409 * ixgbe_start_mac_link_82599 - Setup MAC link settings
410 * @hw: pointer to hardware structure
411 * @autoneg_wait_to_complete: true when waiting for completion is needed
412 *
413 * Configures link settings based on values in the ixgbe_hw struct.
414 * Restarts the link. Performs autonegotiation if needed.
415 **/
416 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
417 bool autoneg_wait_to_complete)
418 {
419 u32 autoc_reg;
420 u32 links_reg;
421 u32 i;
422 s32 status = 0;
423 bool got_lock = false;
424
425 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
426 status = hw->mac.ops.acquire_swfw_sync(hw,
427 IXGBE_GSSR_MAC_CSR_SM);
428 if (status)
429 goto out;
430
431 got_lock = true;
432 }
433
434 /* Restart link */
435 ixgbe_reset_pipeline_82599(hw);
436
437 if (got_lock)
438 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
439
440 /* Only poll for autoneg to complete if specified to do so */
441 if (autoneg_wait_to_complete) {
442 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
443 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
444 IXGBE_AUTOC_LMS_KX4_KX_KR ||
445 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
446 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
447 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
448 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
449 links_reg = 0; /* Just in case Autoneg time = 0 */
450 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
451 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
452 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
453 break;
454 msleep(100);
455 }
456 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
457 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
458 hw_dbg(hw, "Autoneg did not complete.\n");
459 }
460 }
461 }
462
463 /* Add delay to filter out noises during initial link setup */
464 msleep(50);
465
466 out:
467 return status;
468 }
469
470 /**
471 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
472 * @hw: pointer to hardware structure
473 *
474 * The base drivers may require better control over SFP+ module
475 * PHY states. This includes selectively shutting down the Tx
476 * laser on the PHY, effectively halting physical link.
477 **/
478 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
479 {
480 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
481
482 /* Disable tx laser; allow 100us to go dark per spec */
483 esdp_reg |= IXGBE_ESDP_SDP3;
484 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
485 IXGBE_WRITE_FLUSH(hw);
486 udelay(100);
487 }
488
489 /**
490 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
491 * @hw: pointer to hardware structure
492 *
493 * The base drivers may require better control over SFP+ module
494 * PHY states. This includes selectively turning on the Tx
495 * laser on the PHY, effectively starting physical link.
496 **/
497 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
498 {
499 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
500
501 /* Enable tx laser; allow 100ms to light up */
502 esdp_reg &= ~IXGBE_ESDP_SDP3;
503 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
504 IXGBE_WRITE_FLUSH(hw);
505 msleep(100);
506 }
507
508 /**
509 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
510 * @hw: pointer to hardware structure
511 *
512 * When the driver changes the link speeds that it can support,
513 * it sets autotry_restart to true to indicate that we need to
514 * initiate a new autotry session with the link partner. To do
515 * so, we set the speed then disable and re-enable the tx laser, to
516 * alert the link partner that it also needs to restart autotry on its
517 * end. This is consistent with true clause 37 autoneg, which also
518 * involves a loss of signal.
519 **/
520 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
521 {
522 if (hw->mac.autotry_restart) {
523 ixgbe_disable_tx_laser_multispeed_fiber(hw);
524 ixgbe_enable_tx_laser_multispeed_fiber(hw);
525 hw->mac.autotry_restart = false;
526 }
527 }
528
529 /**
530 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
531 * @hw: pointer to hardware structure
532 * @speed: new link speed
533 * @autoneg_wait_to_complete: true when waiting for completion is needed
534 *
535 * Set the link speed in the AUTOC register and restarts link.
536 **/
537 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
538 ixgbe_link_speed speed,
539 bool autoneg_wait_to_complete)
540 {
541 s32 status = 0;
542 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
543 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
544 u32 speedcnt = 0;
545 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
546 u32 i = 0;
547 bool link_up = false;
548 bool autoneg = false;
549
550 /* Mask off requested but non-supported speeds */
551 status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
552 &autoneg);
553 if (status != 0)
554 return status;
555
556 speed &= link_speed;
557
558 /*
559 * Try each speed one by one, highest priority first. We do this in
560 * software because 10gb fiber doesn't support speed autonegotiation.
561 */
562 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
563 speedcnt++;
564 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
565
566 /* If we already have link at this speed, just jump out */
567 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
568 false);
569 if (status != 0)
570 return status;
571
572 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
573 goto out;
574
575 /* Set the module link speed */
576 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
577 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
578 IXGBE_WRITE_FLUSH(hw);
579
580 /* Allow module to change analog characteristics (1G->10G) */
581 msleep(40);
582
583 status = ixgbe_setup_mac_link_82599(hw,
584 IXGBE_LINK_SPEED_10GB_FULL,
585 autoneg_wait_to_complete);
586 if (status != 0)
587 return status;
588
589 /* Flap the tx laser if it has not already been done */
590 if (hw->mac.ops.flap_tx_laser)
591 hw->mac.ops.flap_tx_laser(hw);
592
593 /*
594 * Wait for the controller to acquire link. Per IEEE 802.3ap,
595 * Section 73.10.2, we may have to wait up to 500ms if KR is
596 * attempted. 82599 uses the same timing for 10g SFI.
597 */
598 for (i = 0; i < 5; i++) {
599 /* Wait for the link partner to also set speed */
600 msleep(100);
601
602 /* If we have link, just jump out */
603 status = hw->mac.ops.check_link(hw, &link_speed,
604 &link_up, false);
605 if (status != 0)
606 return status;
607
608 if (link_up)
609 goto out;
610 }
611 }
612
613 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
614 speedcnt++;
615 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
616 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
617
618 /* If we already have link at this speed, just jump out */
619 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
620 false);
621 if (status != 0)
622 return status;
623
624 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
625 goto out;
626
627 /* Set the module link speed */
628 esdp_reg &= ~IXGBE_ESDP_SDP5;
629 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
630 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
631 IXGBE_WRITE_FLUSH(hw);
632
633 /* Allow module to change analog characteristics (10G->1G) */
634 msleep(40);
635
636 status = ixgbe_setup_mac_link_82599(hw,
637 IXGBE_LINK_SPEED_1GB_FULL,
638 autoneg_wait_to_complete);
639 if (status != 0)
640 return status;
641
642 /* Flap the tx laser if it has not already been done */
643 if (hw->mac.ops.flap_tx_laser)
644 hw->mac.ops.flap_tx_laser(hw);
645
646 /* Wait for the link partner to also set speed */
647 msleep(100);
648
649 /* If we have link, just jump out */
650 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
651 false);
652 if (status != 0)
653 return status;
654
655 if (link_up)
656 goto out;
657 }
658
659 /*
660 * We didn't get link. Configure back to the highest speed we tried,
661 * (if there was more than one). We call ourselves back with just the
662 * single highest speed that the user requested.
663 */
664 if (speedcnt > 1)
665 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
666 highest_link_speed,
667 autoneg_wait_to_complete);
668
669 out:
670 /* Set autoneg_advertised value based on input link speed */
671 hw->phy.autoneg_advertised = 0;
672
673 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
674 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
675
676 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
677 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
678
679 return status;
680 }
681
682 /**
683 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
684 * @hw: pointer to hardware structure
685 * @speed: new link speed
686 * @autoneg_wait_to_complete: true when waiting for completion is needed
687 *
688 * Implements the Intel SmartSpeed algorithm.
689 **/
690 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
691 ixgbe_link_speed speed,
692 bool autoneg_wait_to_complete)
693 {
694 s32 status = 0;
695 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
696 s32 i, j;
697 bool link_up = false;
698 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
699
700 /* Set autoneg_advertised value based on input link speed */
701 hw->phy.autoneg_advertised = 0;
702
703 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
704 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
705
706 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
707 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
708
709 if (speed & IXGBE_LINK_SPEED_100_FULL)
710 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
711
712 /*
713 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
714 * autoneg advertisement if link is unable to be established at the
715 * highest negotiated rate. This can sometimes happen due to integrity
716 * issues with the physical media connection.
717 */
718
719 /* First, try to get link with full advertisement */
720 hw->phy.smart_speed_active = false;
721 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
722 status = ixgbe_setup_mac_link_82599(hw, speed,
723 autoneg_wait_to_complete);
724 if (status != 0)
725 goto out;
726
727 /*
728 * Wait for the controller to acquire link. Per IEEE 802.3ap,
729 * Section 73.10.2, we may have to wait up to 500ms if KR is
730 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
731 * Table 9 in the AN MAS.
732 */
733 for (i = 0; i < 5; i++) {
734 mdelay(100);
735
736 /* If we have link, just jump out */
737 status = hw->mac.ops.check_link(hw, &link_speed,
738 &link_up, false);
739 if (status != 0)
740 goto out;
741
742 if (link_up)
743 goto out;
744 }
745 }
746
747 /*
748 * We didn't get link. If we advertised KR plus one of KX4/KX
749 * (or BX4/BX), then disable KR and try again.
750 */
751 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
752 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
753 goto out;
754
755 /* Turn SmartSpeed on to disable KR support */
756 hw->phy.smart_speed_active = true;
757 status = ixgbe_setup_mac_link_82599(hw, speed,
758 autoneg_wait_to_complete);
759 if (status != 0)
760 goto out;
761
762 /*
763 * Wait for the controller to acquire link. 600ms will allow for
764 * the AN link_fail_inhibit_timer as well for multiple cycles of
765 * parallel detect, both 10g and 1g. This allows for the maximum
766 * connect attempts as defined in the AN MAS table 73-7.
767 */
768 for (i = 0; i < 6; i++) {
769 mdelay(100);
770
771 /* If we have link, just jump out */
772 status = hw->mac.ops.check_link(hw, &link_speed,
773 &link_up, false);
774 if (status != 0)
775 goto out;
776
777 if (link_up)
778 goto out;
779 }
780
781 /* We didn't get link. Turn SmartSpeed back off. */
782 hw->phy.smart_speed_active = false;
783 status = ixgbe_setup_mac_link_82599(hw, speed,
784 autoneg_wait_to_complete);
785
786 out:
787 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
788 hw_dbg(hw, "Smartspeed has downgraded the link speed from "
789 "the maximum advertised\n");
790 return status;
791 }
792
793 /**
794 * ixgbe_setup_mac_link_82599 - Set MAC link speed
795 * @hw: pointer to hardware structure
796 * @speed: new link speed
797 * @autoneg_wait_to_complete: true when waiting for completion is needed
798 *
799 * Set the link speed in the AUTOC register and restarts link.
800 **/
801 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
802 ixgbe_link_speed speed,
803 bool autoneg_wait_to_complete)
804 {
805 s32 status = 0;
806 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
807 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
808 u32 start_autoc = autoc;
809 u32 orig_autoc = 0;
810 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
811 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
812 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
813 u32 links_reg;
814 u32 i;
815 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
816 bool got_lock = false;
817 bool autoneg = false;
818
819 /* Check to see if speed passed in is supported. */
820 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities,
821 &autoneg);
822 if (status != 0)
823 goto out;
824
825 speed &= link_capabilities;
826
827 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
828 status = IXGBE_ERR_LINK_SETUP;
829 goto out;
830 }
831
832 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
833 if (hw->mac.orig_link_settings_stored)
834 orig_autoc = hw->mac.orig_autoc;
835 else
836 orig_autoc = autoc;
837
838 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
839 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
840 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
841 /* Set KX4/KX/KR support according to speed requested */
842 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
843 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
844 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
845 autoc |= IXGBE_AUTOC_KX4_SUPP;
846 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
847 (hw->phy.smart_speed_active == false))
848 autoc |= IXGBE_AUTOC_KR_SUPP;
849 }
850 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
851 autoc |= IXGBE_AUTOC_KX_SUPP;
852 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
853 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
854 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
855 /* Switch from 1G SFI to 10G SFI if requested */
856 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
857 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
858 autoc &= ~IXGBE_AUTOC_LMS_MASK;
859 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
860 }
861 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
862 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
863 /* Switch from 10G SFI to 1G SFI if requested */
864 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
865 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
866 autoc &= ~IXGBE_AUTOC_LMS_MASK;
867 if (autoneg)
868 autoc |= IXGBE_AUTOC_LMS_1G_AN;
869 else
870 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
871 }
872 }
873
874 if (autoc != start_autoc) {
875 /* Need SW/FW semaphore around AUTOC writes if LESM is on,
876 * likewise reset_pipeline requires us to hold this lock as
877 * it also writes to AUTOC.
878 */
879 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
880 status = hw->mac.ops.acquire_swfw_sync(hw,
881 IXGBE_GSSR_MAC_CSR_SM);
882 if (status != 0)
883 goto out;
884
885 got_lock = true;
886 }
887
888 /* Restart link */
889 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
890 ixgbe_reset_pipeline_82599(hw);
891
892 if (got_lock)
893 hw->mac.ops.release_swfw_sync(hw,
894 IXGBE_GSSR_MAC_CSR_SM);
895
896 /* Only poll for autoneg to complete if specified to do so */
897 if (autoneg_wait_to_complete) {
898 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
899 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
900 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
901 links_reg = 0; /*Just in case Autoneg time=0*/
902 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
903 links_reg =
904 IXGBE_READ_REG(hw, IXGBE_LINKS);
905 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
906 break;
907 msleep(100);
908 }
909 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
910 status =
911 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
912 hw_dbg(hw, "Autoneg did not "
913 "complete.\n");
914 }
915 }
916 }
917
918 /* Add delay to filter out noises during initial link setup */
919 msleep(50);
920 }
921
922 out:
923 return status;
924 }
925
926 /**
927 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
928 * @hw: pointer to hardware structure
929 * @speed: new link speed
930 * @autoneg_wait_to_complete: true if waiting is needed to complete
931 *
932 * Restarts link on PHY and MAC based on settings passed in.
933 **/
934 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
935 ixgbe_link_speed speed,
936 bool autoneg_wait_to_complete)
937 {
938 s32 status;
939
940 /* Setup the PHY according to input speed */
941 status = hw->phy.ops.setup_link_speed(hw, speed,
942 autoneg_wait_to_complete);
943 /* Set up MAC */
944 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
945
946 return status;
947 }
948
949 /**
950 * ixgbe_reset_hw_82599 - Perform hardware reset
951 * @hw: pointer to hardware structure
952 *
953 * Resets the hardware by resetting the transmit and receive units, masks
954 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
955 * reset.
956 **/
957 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
958 {
959 ixgbe_link_speed link_speed;
960 s32 status;
961 u32 ctrl, i, autoc, autoc2;
962 u32 curr_lms;
963 bool link_up = false;
964
965 /* Call adapter stop to disable tx/rx and clear interrupts */
966 status = hw->mac.ops.stop_adapter(hw);
967 if (status != 0)
968 goto reset_hw_out;
969
970 /* flush pending Tx transactions */
971 ixgbe_clear_tx_pending(hw);
972
973 /* PHY ops must be identified and initialized prior to reset */
974
975 /* Identify PHY and related function pointers */
976 status = hw->phy.ops.init(hw);
977
978 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
979 goto reset_hw_out;
980
981 /* Setup SFP module if there is one present. */
982 if (hw->phy.sfp_setup_needed) {
983 status = hw->mac.ops.setup_sfp(hw);
984 hw->phy.sfp_setup_needed = false;
985 }
986
987 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
988 goto reset_hw_out;
989
990 /* Reset PHY */
991 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
992 hw->phy.ops.reset(hw);
993
994 /* remember AUTOC LMS from before we reset */
995 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
996
997 mac_reset_top:
998 /*
999 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1000 * If link reset is used when link is up, it might reset the PHY when
1001 * mng is using it. If link is down or the flag to force full link
1002 * reset is set, then perform link reset.
1003 */
1004 ctrl = IXGBE_CTRL_LNK_RST;
1005 if (!hw->force_full_reset) {
1006 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1007 if (link_up)
1008 ctrl = IXGBE_CTRL_RST;
1009 }
1010
1011 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1012 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1013 IXGBE_WRITE_FLUSH(hw);
1014
1015 /* Poll for reset bit to self-clear indicating reset is complete */
1016 for (i = 0; i < 10; i++) {
1017 udelay(1);
1018 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1019 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1020 break;
1021 }
1022
1023 if (ctrl & IXGBE_CTRL_RST_MASK) {
1024 status = IXGBE_ERR_RESET_FAILED;
1025 hw_dbg(hw, "Reset polling failed to complete.\n");
1026 }
1027
1028 msleep(50);
1029
1030 /*
1031 * Double resets are required for recovery from certain error
1032 * conditions. Between resets, it is necessary to stall to allow time
1033 * for any pending HW events to complete.
1034 */
1035 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1036 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1037 goto mac_reset_top;
1038 }
1039
1040 /*
1041 * Store the original AUTOC/AUTOC2 values if they have not been
1042 * stored off yet. Otherwise restore the stored original
1043 * values since the reset operation sets back to defaults.
1044 */
1045 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1046 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1047 if (hw->mac.orig_link_settings_stored == false) {
1048 hw->mac.orig_autoc = autoc;
1049 hw->mac.orig_autoc2 = autoc2;
1050 hw->mac.orig_link_settings_stored = true;
1051 } else {
1052
1053 /* If MNG FW is running on a multi-speed device that
1054 * doesn't autoneg with out driver support we need to
1055 * leave LMS in the state it was before we MAC reset.
1056 * Likewise if we support WoL we don't want change the
1057 * LMS state either.
1058 */
1059 if ((hw->phy.multispeed_fiber && hw->mng_fw_enabled) ||
1060 hw->wol_enabled)
1061 hw->mac.orig_autoc =
1062 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1063 curr_lms;
1064
1065 if (autoc != hw->mac.orig_autoc) {
1066 /* Need SW/FW semaphore around AUTOC writes if LESM is
1067 * on, likewise reset_pipeline requires us to hold
1068 * this lock as it also writes to AUTOC.
1069 */
1070 bool got_lock = false;
1071 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
1072 status = hw->mac.ops.acquire_swfw_sync(hw,
1073 IXGBE_GSSR_MAC_CSR_SM);
1074 if (status)
1075 goto reset_hw_out;
1076
1077 got_lock = true;
1078 }
1079
1080 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
1081 ixgbe_reset_pipeline_82599(hw);
1082
1083 if (got_lock)
1084 hw->mac.ops.release_swfw_sync(hw,
1085 IXGBE_GSSR_MAC_CSR_SM);
1086 }
1087
1088 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1089 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1090 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1091 autoc2 |= (hw->mac.orig_autoc2 &
1092 IXGBE_AUTOC2_UPPER_MASK);
1093 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1094 }
1095 }
1096
1097 /* Store the permanent mac address */
1098 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1099
1100 /*
1101 * Store MAC address from RAR0, clear receive address registers, and
1102 * clear the multicast table. Also reset num_rar_entries to 128,
1103 * since we modify this value when programming the SAN MAC address.
1104 */
1105 hw->mac.num_rar_entries = 128;
1106 hw->mac.ops.init_rx_addrs(hw);
1107
1108 /* Store the permanent SAN mac address */
1109 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1110
1111 /* Add the SAN MAC address to the RAR only if it's a valid address */
1112 if (is_valid_ether_addr(hw->mac.san_addr)) {
1113 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1114 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1115
1116 /* Save the SAN MAC RAR index */
1117 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1118
1119 /* Reserve the last RAR for the SAN MAC address */
1120 hw->mac.num_rar_entries--;
1121 }
1122
1123 /* Store the alternative WWNN/WWPN prefix */
1124 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1125 &hw->mac.wwpn_prefix);
1126
1127 reset_hw_out:
1128 return status;
1129 }
1130
1131 /**
1132 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1133 * @hw: pointer to hardware structure
1134 **/
1135 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1136 {
1137 int i;
1138 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1139 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1140
1141 /*
1142 * Before starting reinitialization process,
1143 * FDIRCMD.CMD must be zero.
1144 */
1145 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1146 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1147 IXGBE_FDIRCMD_CMD_MASK))
1148 break;
1149 udelay(10);
1150 }
1151 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1152 hw_dbg(hw, "Flow Director previous command isn't complete, "
1153 "aborting table re-initialization.\n");
1154 return IXGBE_ERR_FDIR_REINIT_FAILED;
1155 }
1156
1157 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1158 IXGBE_WRITE_FLUSH(hw);
1159 /*
1160 * 82599 adapters flow director init flow cannot be restarted,
1161 * Workaround 82599 silicon errata by performing the following steps
1162 * before re-writing the FDIRCTRL control register with the same value.
1163 * - write 1 to bit 8 of FDIRCMD register &
1164 * - write 0 to bit 8 of FDIRCMD register
1165 */
1166 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1167 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1168 IXGBE_FDIRCMD_CLEARHT));
1169 IXGBE_WRITE_FLUSH(hw);
1170 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1171 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1172 ~IXGBE_FDIRCMD_CLEARHT));
1173 IXGBE_WRITE_FLUSH(hw);
1174 /*
1175 * Clear FDIR Hash register to clear any leftover hashes
1176 * waiting to be programmed.
1177 */
1178 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1179 IXGBE_WRITE_FLUSH(hw);
1180
1181 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1182 IXGBE_WRITE_FLUSH(hw);
1183
1184 /* Poll init-done after we write FDIRCTRL register */
1185 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1186 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1187 IXGBE_FDIRCTRL_INIT_DONE)
1188 break;
1189 usleep_range(1000, 2000);
1190 }
1191 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1192 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1193 return IXGBE_ERR_FDIR_REINIT_FAILED;
1194 }
1195
1196 /* Clear FDIR statistics registers (read to clear) */
1197 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1198 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1199 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1200 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1201 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1202
1203 return 0;
1204 }
1205
1206 /**
1207 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1208 * @hw: pointer to hardware structure
1209 * @fdirctrl: value to write to flow director control register
1210 **/
1211 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1212 {
1213 int i;
1214
1215 /* Prime the keys for hashing */
1216 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1217 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1218
1219 /*
1220 * Poll init-done after we write the register. Estimated times:
1221 * 10G: PBALLOC = 11b, timing is 60us
1222 * 1G: PBALLOC = 11b, timing is 600us
1223 * 100M: PBALLOC = 11b, timing is 6ms
1224 *
1225 * Multiple these timings by 4 if under full Rx load
1226 *
1227 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1228 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1229 * this might not finish in our poll time, but we can live with that
1230 * for now.
1231 */
1232 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1233 IXGBE_WRITE_FLUSH(hw);
1234 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1235 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1236 IXGBE_FDIRCTRL_INIT_DONE)
1237 break;
1238 usleep_range(1000, 2000);
1239 }
1240
1241 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1242 hw_dbg(hw, "Flow Director poll time exceeded!\n");
1243 }
1244
1245 /**
1246 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1247 * @hw: pointer to hardware structure
1248 * @fdirctrl: value to write to flow director control register, initially
1249 * contains just the value of the Rx packet buffer allocation
1250 **/
1251 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1252 {
1253 /*
1254 * Continue setup of fdirctrl register bits:
1255 * Move the flexible bytes to use the ethertype - shift 6 words
1256 * Set the maximum length per hash bucket to 0xA filters
1257 * Send interrupt when 64 filters are left
1258 */
1259 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1260 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1261 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1262
1263 /* write hashes and fdirctrl register, poll for completion */
1264 ixgbe_fdir_enable_82599(hw, fdirctrl);
1265
1266 return 0;
1267 }
1268
1269 /**
1270 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1271 * @hw: pointer to hardware structure
1272 * @fdirctrl: value to write to flow director control register, initially
1273 * contains just the value of the Rx packet buffer allocation
1274 **/
1275 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1276 {
1277 /*
1278 * Continue setup of fdirctrl register bits:
1279 * Turn perfect match filtering on
1280 * Report hash in RSS field of Rx wb descriptor
1281 * Initialize the drop queue
1282 * Move the flexible bytes to use the ethertype - shift 6 words
1283 * Set the maximum length per hash bucket to 0xA filters
1284 * Send interrupt when 64 (0x4 * 16) filters are left
1285 */
1286 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1287 IXGBE_FDIRCTRL_REPORT_STATUS |
1288 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1289 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1290 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1291 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1292
1293 /* write hashes and fdirctrl register, poll for completion */
1294 ixgbe_fdir_enable_82599(hw, fdirctrl);
1295
1296 return 0;
1297 }
1298
1299 /*
1300 * These defines allow us to quickly generate all of the necessary instructions
1301 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1302 * for values 0 through 15
1303 */
1304 #define IXGBE_ATR_COMMON_HASH_KEY \
1305 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1306 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1307 do { \
1308 u32 n = (_n); \
1309 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1310 common_hash ^= lo_hash_dword >> n; \
1311 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1312 bucket_hash ^= lo_hash_dword >> n; \
1313 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1314 sig_hash ^= lo_hash_dword << (16 - n); \
1315 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1316 common_hash ^= hi_hash_dword >> n; \
1317 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1318 bucket_hash ^= hi_hash_dword >> n; \
1319 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1320 sig_hash ^= hi_hash_dword << (16 - n); \
1321 } while (0);
1322
1323 /**
1324 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1325 * @stream: input bitstream to compute the hash on
1326 *
1327 * This function is almost identical to the function above but contains
1328 * several optomizations such as unwinding all of the loops, letting the
1329 * compiler work out all of the conditional ifs since the keys are static
1330 * defines, and computing two keys at once since the hashed dword stream
1331 * will be the same for both keys.
1332 **/
1333 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1334 union ixgbe_atr_hash_dword common)
1335 {
1336 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1337 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1338
1339 /* record the flow_vm_vlan bits as they are a key part to the hash */
1340 flow_vm_vlan = ntohl(input.dword);
1341
1342 /* generate common hash dword */
1343 hi_hash_dword = ntohl(common.dword);
1344
1345 /* low dword is word swapped version of common */
1346 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1347
1348 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1349 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1350
1351 /* Process bits 0 and 16 */
1352 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1353
1354 /*
1355 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1356 * delay this because bit 0 of the stream should not be processed
1357 * so we do not add the vlan until after bit 0 was processed
1358 */
1359 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1360
1361 /* Process remaining 30 bit of the key */
1362 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1363 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1364 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1365 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1366 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1367 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1368 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1369 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1370 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1371 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1372 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1373 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1374 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1375 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1376 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1377
1378 /* combine common_hash result with signature and bucket hashes */
1379 bucket_hash ^= common_hash;
1380 bucket_hash &= IXGBE_ATR_HASH_MASK;
1381
1382 sig_hash ^= common_hash << 16;
1383 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1384
1385 /* return completed signature hash */
1386 return sig_hash ^ bucket_hash;
1387 }
1388
1389 /**
1390 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1391 * @hw: pointer to hardware structure
1392 * @input: unique input dword
1393 * @common: compressed common input dword
1394 * @queue: queue index to direct traffic to
1395 **/
1396 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1397 union ixgbe_atr_hash_dword input,
1398 union ixgbe_atr_hash_dword common,
1399 u8 queue)
1400 {
1401 u64 fdirhashcmd;
1402 u32 fdircmd;
1403
1404 /*
1405 * Get the flow_type in order to program FDIRCMD properly
1406 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1407 */
1408 switch (input.formatted.flow_type) {
1409 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1410 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1411 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1412 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1413 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1414 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1415 break;
1416 default:
1417 hw_dbg(hw, " Error on flow type input\n");
1418 return IXGBE_ERR_CONFIG;
1419 }
1420
1421 /* configure FDIRCMD register */
1422 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1423 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1424 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1425 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1426
1427 /*
1428 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1429 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1430 */
1431 fdirhashcmd = (u64)fdircmd << 32;
1432 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1433 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1434
1435 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1436
1437 return 0;
1438 }
1439
1440 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1441 do { \
1442 u32 n = (_n); \
1443 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1444 bucket_hash ^= lo_hash_dword >> n; \
1445 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1446 bucket_hash ^= hi_hash_dword >> n; \
1447 } while (0);
1448
1449 /**
1450 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1451 * @atr_input: input bitstream to compute the hash on
1452 * @input_mask: mask for the input bitstream
1453 *
1454 * This function serves two main purposes. First it applys the input_mask
1455 * to the atr_input resulting in a cleaned up atr_input data stream.
1456 * Secondly it computes the hash and stores it in the bkt_hash field at
1457 * the end of the input byte stream. This way it will be available for
1458 * future use without needing to recompute the hash.
1459 **/
1460 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1461 union ixgbe_atr_input *input_mask)
1462 {
1463
1464 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1465 u32 bucket_hash = 0;
1466
1467 /* Apply masks to input data */
1468 input->dword_stream[0] &= input_mask->dword_stream[0];
1469 input->dword_stream[1] &= input_mask->dword_stream[1];
1470 input->dword_stream[2] &= input_mask->dword_stream[2];
1471 input->dword_stream[3] &= input_mask->dword_stream[3];
1472 input->dword_stream[4] &= input_mask->dword_stream[4];
1473 input->dword_stream[5] &= input_mask->dword_stream[5];
1474 input->dword_stream[6] &= input_mask->dword_stream[6];
1475 input->dword_stream[7] &= input_mask->dword_stream[7];
1476 input->dword_stream[8] &= input_mask->dword_stream[8];
1477 input->dword_stream[9] &= input_mask->dword_stream[9];
1478 input->dword_stream[10] &= input_mask->dword_stream[10];
1479
1480 /* record the flow_vm_vlan bits as they are a key part to the hash */
1481 flow_vm_vlan = ntohl(input->dword_stream[0]);
1482
1483 /* generate common hash dword */
1484 hi_hash_dword = ntohl(input->dword_stream[1] ^
1485 input->dword_stream[2] ^
1486 input->dword_stream[3] ^
1487 input->dword_stream[4] ^
1488 input->dword_stream[5] ^
1489 input->dword_stream[6] ^
1490 input->dword_stream[7] ^
1491 input->dword_stream[8] ^
1492 input->dword_stream[9] ^
1493 input->dword_stream[10]);
1494
1495 /* low dword is word swapped version of common */
1496 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1497
1498 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1499 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1500
1501 /* Process bits 0 and 16 */
1502 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1503
1504 /*
1505 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1506 * delay this because bit 0 of the stream should not be processed
1507 * so we do not add the vlan until after bit 0 was processed
1508 */
1509 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1510
1511 /* Process remaining 30 bit of the key */
1512 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1513 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1514 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1515 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1516 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1517 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1518 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1519 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1520 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1521 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1522 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1523 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1524 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1525 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1526 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1527
1528 /*
1529 * Limit hash to 13 bits since max bucket count is 8K.
1530 * Store result at the end of the input stream.
1531 */
1532 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1533 }
1534
1535 /**
1536 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1537 * @input_mask: mask to be bit swapped
1538 *
1539 * The source and destination port masks for flow director are bit swapped
1540 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1541 * generate a correctly swapped value we need to bit swap the mask and that
1542 * is what is accomplished by this function.
1543 **/
1544 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1545 {
1546 u32 mask = ntohs(input_mask->formatted.dst_port);
1547 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1548 mask |= ntohs(input_mask->formatted.src_port);
1549 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1550 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1551 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1552 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1553 }
1554
1555 /*
1556 * These two macros are meant to address the fact that we have registers
1557 * that are either all or in part big-endian. As a result on big-endian
1558 * systems we will end up byte swapping the value to little-endian before
1559 * it is byte swapped again and written to the hardware in the original
1560 * big-endian format.
1561 */
1562 #define IXGBE_STORE_AS_BE32(_value) \
1563 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1564 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1565
1566 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1567 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1568
1569 #define IXGBE_STORE_AS_BE16(_value) \
1570 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1571
1572 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1573 union ixgbe_atr_input *input_mask)
1574 {
1575 /* mask IPv6 since it is currently not supported */
1576 u32 fdirm = IXGBE_FDIRM_DIPv6;
1577 u32 fdirtcpm;
1578
1579 /*
1580 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1581 * are zero, then assume a full mask for that field. Also assume that
1582 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1583 * cannot be masked out in this implementation.
1584 *
1585 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1586 * point in time.
1587 */
1588
1589 /* verify bucket hash is cleared on hash generation */
1590 if (input_mask->formatted.bkt_hash)
1591 hw_dbg(hw, " bucket hash should always be 0 in mask\n");
1592
1593 /* Program FDIRM and verify partial masks */
1594 switch (input_mask->formatted.vm_pool & 0x7F) {
1595 case 0x0:
1596 fdirm |= IXGBE_FDIRM_POOL;
1597 case 0x7F:
1598 break;
1599 default:
1600 hw_dbg(hw, " Error on vm pool mask\n");
1601 return IXGBE_ERR_CONFIG;
1602 }
1603
1604 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1605 case 0x0:
1606 fdirm |= IXGBE_FDIRM_L4P;
1607 if (input_mask->formatted.dst_port ||
1608 input_mask->formatted.src_port) {
1609 hw_dbg(hw, " Error on src/dst port mask\n");
1610 return IXGBE_ERR_CONFIG;
1611 }
1612 case IXGBE_ATR_L4TYPE_MASK:
1613 break;
1614 default:
1615 hw_dbg(hw, " Error on flow type mask\n");
1616 return IXGBE_ERR_CONFIG;
1617 }
1618
1619 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) {
1620 case 0x0000:
1621 /* mask VLAN ID, fall through to mask VLAN priority */
1622 fdirm |= IXGBE_FDIRM_VLANID;
1623 case 0x0FFF:
1624 /* mask VLAN priority */
1625 fdirm |= IXGBE_FDIRM_VLANP;
1626 break;
1627 case 0xE000:
1628 /* mask VLAN ID only, fall through */
1629 fdirm |= IXGBE_FDIRM_VLANID;
1630 case 0xEFFF:
1631 /* no VLAN fields masked */
1632 break;
1633 default:
1634 hw_dbg(hw, " Error on VLAN mask\n");
1635 return IXGBE_ERR_CONFIG;
1636 }
1637
1638 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1639 case 0x0000:
1640 /* Mask Flex Bytes, fall through */
1641 fdirm |= IXGBE_FDIRM_FLEX;
1642 case 0xFFFF:
1643 break;
1644 default:
1645 hw_dbg(hw, " Error on flexible byte mask\n");
1646 return IXGBE_ERR_CONFIG;
1647 }
1648
1649 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1650 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1651
1652 /* store the TCP/UDP port masks, bit reversed from port layout */
1653 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1654
1655 /* write both the same so that UDP and TCP use the same mask */
1656 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1657 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1658
1659 /* store source and destination IP masks (big-enian) */
1660 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1661 ~input_mask->formatted.src_ip[0]);
1662 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1663 ~input_mask->formatted.dst_ip[0]);
1664
1665 return 0;
1666 }
1667
1668 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1669 union ixgbe_atr_input *input,
1670 u16 soft_id, u8 queue)
1671 {
1672 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1673
1674 /* currently IPv6 is not supported, must be programmed with 0 */
1675 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1676 input->formatted.src_ip[0]);
1677 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1678 input->formatted.src_ip[1]);
1679 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1680 input->formatted.src_ip[2]);
1681
1682 /* record the source address (big-endian) */
1683 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1684
1685 /* record the first 32 bits of the destination address (big-endian) */
1686 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1687
1688 /* record source and destination port (little-endian)*/
1689 fdirport = ntohs(input->formatted.dst_port);
1690 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1691 fdirport |= ntohs(input->formatted.src_port);
1692 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1693
1694 /* record vlan (little-endian) and flex_bytes(big-endian) */
1695 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1696 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1697 fdirvlan |= ntohs(input->formatted.vlan_id);
1698 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1699
1700 /* configure FDIRHASH register */
1701 fdirhash = input->formatted.bkt_hash;
1702 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1703 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1704
1705 /*
1706 * flush all previous writes to make certain registers are
1707 * programmed prior to issuing the command
1708 */
1709 IXGBE_WRITE_FLUSH(hw);
1710
1711 /* configure FDIRCMD register */
1712 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1713 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1714 if (queue == IXGBE_FDIR_DROP_QUEUE)
1715 fdircmd |= IXGBE_FDIRCMD_DROP;
1716 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1717 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1718 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1719
1720 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1721
1722 return 0;
1723 }
1724
1725 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1726 union ixgbe_atr_input *input,
1727 u16 soft_id)
1728 {
1729 u32 fdirhash;
1730 u32 fdircmd = 0;
1731 u32 retry_count;
1732 s32 err = 0;
1733
1734 /* configure FDIRHASH register */
1735 fdirhash = input->formatted.bkt_hash;
1736 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1737 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1738
1739 /* flush hash to HW */
1740 IXGBE_WRITE_FLUSH(hw);
1741
1742 /* Query if filter is present */
1743 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1744
1745 for (retry_count = 10; retry_count; retry_count--) {
1746 /* allow 10us for query to process */
1747 udelay(10);
1748 /* verify query completed successfully */
1749 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1750 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1751 break;
1752 }
1753
1754 if (!retry_count)
1755 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1756
1757 /* if filter exists in hardware then remove it */
1758 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1759 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1760 IXGBE_WRITE_FLUSH(hw);
1761 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1762 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1763 }
1764
1765 return err;
1766 }
1767
1768 /**
1769 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1770 * @hw: pointer to hardware structure
1771 * @reg: analog register to read
1772 * @val: read value
1773 *
1774 * Performs read operation to Omer analog register specified.
1775 **/
1776 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1777 {
1778 u32 core_ctl;
1779
1780 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1781 (reg << 8));
1782 IXGBE_WRITE_FLUSH(hw);
1783 udelay(10);
1784 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1785 *val = (u8)core_ctl;
1786
1787 return 0;
1788 }
1789
1790 /**
1791 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1792 * @hw: pointer to hardware structure
1793 * @reg: atlas register to write
1794 * @val: value to write
1795 *
1796 * Performs write operation to Omer analog register specified.
1797 **/
1798 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1799 {
1800 u32 core_ctl;
1801
1802 core_ctl = (reg << 8) | val;
1803 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1804 IXGBE_WRITE_FLUSH(hw);
1805 udelay(10);
1806
1807 return 0;
1808 }
1809
1810 /**
1811 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1812 * @hw: pointer to hardware structure
1813 *
1814 * Starts the hardware using the generic start_hw function
1815 * and the generation start_hw function.
1816 * Then performs revision-specific operations, if any.
1817 **/
1818 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1819 {
1820 s32 ret_val = 0;
1821
1822 ret_val = ixgbe_start_hw_generic(hw);
1823 if (ret_val != 0)
1824 goto out;
1825
1826 ret_val = ixgbe_start_hw_gen2(hw);
1827 if (ret_val != 0)
1828 goto out;
1829
1830 /* We need to run link autotry after the driver loads */
1831 hw->mac.autotry_restart = true;
1832 hw->mac.rx_pb_size = IXGBE_82599_RX_PB_SIZE;
1833
1834 if (ret_val == 0)
1835 ret_val = ixgbe_verify_fw_version_82599(hw);
1836 out:
1837 return ret_val;
1838 }
1839
1840 /**
1841 * ixgbe_identify_phy_82599 - Get physical layer module
1842 * @hw: pointer to hardware structure
1843 *
1844 * Determines the physical layer module found on the current adapter.
1845 * If PHY already detected, maintains current PHY type in hw struct,
1846 * otherwise executes the PHY detection routine.
1847 **/
1848 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1849 {
1850 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1851
1852 /* Detect PHY if not unknown - returns success if already detected. */
1853 status = ixgbe_identify_phy_generic(hw);
1854 if (status != 0) {
1855 /* 82599 10GBASE-T requires an external PHY */
1856 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1857 goto out;
1858 else
1859 status = ixgbe_identify_sfp_module_generic(hw);
1860 }
1861
1862 /* Set PHY type none if no PHY detected */
1863 if (hw->phy.type == ixgbe_phy_unknown) {
1864 hw->phy.type = ixgbe_phy_none;
1865 status = 0;
1866 }
1867
1868 /* Return error if SFP module has been detected but is not supported */
1869 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1870 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1871
1872 out:
1873 return status;
1874 }
1875
1876 /**
1877 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1878 * @hw: pointer to hardware structure
1879 *
1880 * Determines physical layer capabilities of the current configuration.
1881 **/
1882 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1883 {
1884 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1885 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1886 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1887 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1888 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1889 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1890 u16 ext_ability = 0;
1891 u8 comp_codes_10g = 0;
1892 u8 comp_codes_1g = 0;
1893
1894 hw->phy.ops.identify(hw);
1895
1896 switch (hw->phy.type) {
1897 case ixgbe_phy_tn:
1898 case ixgbe_phy_cu_unknown:
1899 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1900 &ext_ability);
1901 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1902 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1903 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1904 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1905 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1906 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1907 goto out;
1908 default:
1909 break;
1910 }
1911
1912 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1913 case IXGBE_AUTOC_LMS_1G_AN:
1914 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1915 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1916 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1917 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1918 goto out;
1919 } else
1920 /* SFI mode so read SFP module */
1921 goto sfp_check;
1922 break;
1923 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1924 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1925 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1926 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1927 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1928 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1929 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1930 goto out;
1931 break;
1932 case IXGBE_AUTOC_LMS_10G_SERIAL:
1933 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1934 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1935 goto out;
1936 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1937 goto sfp_check;
1938 break;
1939 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1940 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1941 if (autoc & IXGBE_AUTOC_KX_SUPP)
1942 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1943 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1944 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1945 if (autoc & IXGBE_AUTOC_KR_SUPP)
1946 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1947 goto out;
1948 break;
1949 default:
1950 goto out;
1951 break;
1952 }
1953
1954 sfp_check:
1955 /* SFP check must be done last since DA modules are sometimes used to
1956 * test KR mode - we need to id KR mode correctly before SFP module.
1957 * Call identify_sfp because the pluggable module may have changed */
1958 hw->phy.ops.identify_sfp(hw);
1959 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1960 goto out;
1961
1962 switch (hw->phy.type) {
1963 case ixgbe_phy_sfp_passive_tyco:
1964 case ixgbe_phy_sfp_passive_unknown:
1965 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1966 break;
1967 case ixgbe_phy_sfp_ftl_active:
1968 case ixgbe_phy_sfp_active_unknown:
1969 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1970 break;
1971 case ixgbe_phy_sfp_avago:
1972 case ixgbe_phy_sfp_ftl:
1973 case ixgbe_phy_sfp_intel:
1974 case ixgbe_phy_sfp_unknown:
1975 hw->phy.ops.read_i2c_eeprom(hw,
1976 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1977 hw->phy.ops.read_i2c_eeprom(hw,
1978 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1979 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1980 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1981 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1982 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1983 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1984 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1985 break;
1986 default:
1987 break;
1988 }
1989
1990 out:
1991 return physical_layer;
1992 }
1993
1994 /**
1995 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1996 * @hw: pointer to hardware structure
1997 * @regval: register value to write to RXCTRL
1998 *
1999 * Enables the Rx DMA unit for 82599
2000 **/
2001 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2002 {
2003 /*
2004 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2005 * If traffic is incoming before we enable the Rx unit, it could hang
2006 * the Rx DMA unit. Therefore, make sure the security engine is
2007 * completely disabled prior to enabling the Rx unit.
2008 */
2009 hw->mac.ops.disable_rx_buff(hw);
2010
2011 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2012
2013 hw->mac.ops.enable_rx_buff(hw);
2014
2015 return 0;
2016 }
2017
2018 /**
2019 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2020 * @hw: pointer to hardware structure
2021 *
2022 * Verifies that installed the firmware version is 0.6 or higher
2023 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2024 *
2025 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2026 * if the FW version is not supported.
2027 **/
2028 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2029 {
2030 s32 status = IXGBE_ERR_EEPROM_VERSION;
2031 u16 fw_offset, fw_ptp_cfg_offset;
2032 u16 fw_version = 0;
2033
2034 /* firmware check is only necessary for SFI devices */
2035 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2036 status = 0;
2037 goto fw_version_out;
2038 }
2039
2040 /* get the offset to the Firmware Module block */
2041 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2042
2043 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2044 goto fw_version_out;
2045
2046 /* get the offset to the Pass Through Patch Configuration block */
2047 hw->eeprom.ops.read(hw, (fw_offset +
2048 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2049 &fw_ptp_cfg_offset);
2050
2051 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2052 goto fw_version_out;
2053
2054 /* get the firmware version */
2055 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2056 IXGBE_FW_PATCH_VERSION_4),
2057 &fw_version);
2058
2059 if (fw_version > 0x5)
2060 status = 0;
2061
2062 fw_version_out:
2063 return status;
2064 }
2065
2066 /**
2067 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2068 * @hw: pointer to hardware structure
2069 *
2070 * Returns true if the LESM FW module is present and enabled. Otherwise
2071 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2072 **/
2073 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2074 {
2075 bool lesm_enabled = false;
2076 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2077 s32 status;
2078
2079 /* get the offset to the Firmware Module block */
2080 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2081
2082 if ((status != 0) ||
2083 (fw_offset == 0) || (fw_offset == 0xFFFF))
2084 goto out;
2085
2086 /* get the offset to the LESM Parameters block */
2087 status = hw->eeprom.ops.read(hw, (fw_offset +
2088 IXGBE_FW_LESM_PARAMETERS_PTR),
2089 &fw_lesm_param_offset);
2090
2091 if ((status != 0) ||
2092 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2093 goto out;
2094
2095 /* get the lesm state word */
2096 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2097 IXGBE_FW_LESM_STATE_1),
2098 &fw_lesm_state);
2099
2100 if ((status == 0) &&
2101 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2102 lesm_enabled = true;
2103
2104 out:
2105 return lesm_enabled;
2106 }
2107
2108 /**
2109 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2110 * fastest available method
2111 *
2112 * @hw: pointer to hardware structure
2113 * @offset: offset of word in EEPROM to read
2114 * @words: number of words
2115 * @data: word(s) read from the EEPROM
2116 *
2117 * Retrieves 16 bit word(s) read from EEPROM
2118 **/
2119 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2120 u16 words, u16 *data)
2121 {
2122 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2123 s32 ret_val = IXGBE_ERR_CONFIG;
2124
2125 /*
2126 * If EEPROM is detected and can be addressed using 14 bits,
2127 * use EERD otherwise use bit bang
2128 */
2129 if ((eeprom->type == ixgbe_eeprom_spi) &&
2130 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2131 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2132 data);
2133 else
2134 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2135 words,
2136 data);
2137
2138 return ret_val;
2139 }
2140
2141 /**
2142 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2143 * fastest available method
2144 *
2145 * @hw: pointer to hardware structure
2146 * @offset: offset of word in the EEPROM to read
2147 * @data: word read from the EEPROM
2148 *
2149 * Reads a 16 bit word from the EEPROM
2150 **/
2151 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2152 u16 offset, u16 *data)
2153 {
2154 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2155 s32 ret_val = IXGBE_ERR_CONFIG;
2156
2157 /*
2158 * If EEPROM is detected and can be addressed using 14 bits,
2159 * use EERD otherwise use bit bang
2160 */
2161 if ((eeprom->type == ixgbe_eeprom_spi) &&
2162 (offset <= IXGBE_EERD_MAX_ADDR))
2163 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2164 else
2165 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2166
2167 return ret_val;
2168 }
2169
2170 /**
2171 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2172 *
2173 * @hw: pointer to hardware structure
2174 *
2175 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2176 * full pipeline reset. Note - We must hold the SW/FW semaphore before writing
2177 * to AUTOC, so this function assumes the semaphore is held.
2178 **/
2179 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2180 {
2181 s32 i, autoc_reg, ret_val;
2182 s32 anlp1_reg = 0;
2183
2184 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2185 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2186
2187 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2188 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN);
2189
2190 /* Wait for AN to leave state 0 */
2191 for (i = 0; i < 10; i++) {
2192 usleep_range(4000, 8000);
2193 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2194 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2195 break;
2196 }
2197
2198 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2199 hw_dbg(hw, "auto negotiation not completed\n");
2200 ret_val = IXGBE_ERR_RESET_FAILED;
2201 goto reset_pipeline_out;
2202 }
2203
2204 ret_val = 0;
2205
2206 reset_pipeline_out:
2207 /* Write AUTOC register with original LMS field and Restart_AN */
2208 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2209 IXGBE_WRITE_FLUSH(hw);
2210
2211 return ret_val;
2212 }
2213
2214 static struct ixgbe_mac_operations mac_ops_82599 = {
2215 .init_hw = &ixgbe_init_hw_generic,
2216 .reset_hw = &ixgbe_reset_hw_82599,
2217 .start_hw = &ixgbe_start_hw_82599,
2218 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2219 .get_media_type = &ixgbe_get_media_type_82599,
2220 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2221 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2222 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
2223 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
2224 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2225 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2226 .get_device_caps = &ixgbe_get_device_caps_generic,
2227 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
2228 .stop_adapter = &ixgbe_stop_adapter_generic,
2229 .get_bus_info = &ixgbe_get_bus_info_generic,
2230 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2231 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2232 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2233 .setup_link = &ixgbe_setup_mac_link_82599,
2234 .set_rxpba = &ixgbe_set_rxpba_generic,
2235 .check_link = &ixgbe_check_mac_link_generic,
2236 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2237 .led_on = &ixgbe_led_on_generic,
2238 .led_off = &ixgbe_led_off_generic,
2239 .blink_led_start = &ixgbe_blink_led_start_generic,
2240 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2241 .set_rar = &ixgbe_set_rar_generic,
2242 .clear_rar = &ixgbe_clear_rar_generic,
2243 .set_vmdq = &ixgbe_set_vmdq_generic,
2244 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic,
2245 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2246 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2247 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2248 .enable_mc = &ixgbe_enable_mc_generic,
2249 .disable_mc = &ixgbe_disable_mc_generic,
2250 .clear_vfta = &ixgbe_clear_vfta_generic,
2251 .set_vfta = &ixgbe_set_vfta_generic,
2252 .fc_enable = &ixgbe_fc_enable_generic,
2253 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
2254 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2255 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2256 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2257 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
2258 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2259 .release_swfw_sync = &ixgbe_release_swfw_sync,
2260 .get_thermal_sensor_data = &ixgbe_get_thermal_sensor_data_generic,
2261 .init_thermal_sensor_thresh = &ixgbe_init_thermal_sensor_thresh_generic,
2262 .mng_fw_enabled = &ixgbe_mng_enabled,
2263 };
2264
2265 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2266 .init_params = &ixgbe_init_eeprom_params_generic,
2267 .read = &ixgbe_read_eeprom_82599,
2268 .read_buffer = &ixgbe_read_eeprom_buffer_82599,
2269 .write = &ixgbe_write_eeprom_generic,
2270 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
2271 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2272 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2273 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2274 };
2275
2276 static struct ixgbe_phy_operations phy_ops_82599 = {
2277 .identify = &ixgbe_identify_phy_82599,
2278 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2279 .init = &ixgbe_init_phy_ops_82599,
2280 .reset = &ixgbe_reset_phy_generic,
2281 .read_reg = &ixgbe_read_phy_reg_generic,
2282 .write_reg = &ixgbe_write_phy_reg_generic,
2283 .setup_link = &ixgbe_setup_phy_link_generic,
2284 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2285 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2286 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2287 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
2288 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2289 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2290 .check_overtemp = &ixgbe_tn_check_overtemp,
2291 };
2292
2293 struct ixgbe_info ixgbe_82599_info = {
2294 .mac = ixgbe_mac_82599EB,
2295 .get_invariants = &ixgbe_get_invariants_82599,
2296 .mac_ops = &mac_ops_82599,
2297 .eeprom_ops = &eeprom_ops_82599,
2298 .phy_ops = &phy_ops_82599,
2299 .mbx_ops = &mbx_ops_generic,
2300 };
Linux kernel - Deliverables
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