1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41 #define IXGBE_82599_RX_PB_SIZE 512
43 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
44 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
45 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
46 static s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
47 ixgbe_link_speed speed
,
49 bool autoneg_wait_to_complete
);
50 static s32
ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw
*hw
,
51 ixgbe_link_speed speed
,
53 bool autoneg_wait_to_complete
);
54 static s32
ixgbe_start_mac_link_82599(struct ixgbe_hw
*hw
,
55 bool autoneg_wait_to_complete
);
56 static s32
ixgbe_setup_mac_link_82599(struct ixgbe_hw
*hw
,
57 ixgbe_link_speed speed
,
59 bool autoneg_wait_to_complete
);
60 static s32
ixgbe_setup_copper_link_82599(struct ixgbe_hw
*hw
,
61 ixgbe_link_speed speed
,
63 bool autoneg_wait_to_complete
);
64 static s32
ixgbe_verify_fw_version_82599(struct ixgbe_hw
*hw
);
65 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw
*hw
);
67 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw
*hw
)
69 struct ixgbe_mac_info
*mac
= &hw
->mac
;
71 /* enable the laser control functions for SFP+ fiber */
72 if (mac
->ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) {
73 mac
->ops
.disable_tx_laser
=
74 &ixgbe_disable_tx_laser_multispeed_fiber
;
75 mac
->ops
.enable_tx_laser
=
76 &ixgbe_enable_tx_laser_multispeed_fiber
;
77 mac
->ops
.flap_tx_laser
= &ixgbe_flap_tx_laser_multispeed_fiber
;
79 mac
->ops
.disable_tx_laser
= NULL
;
80 mac
->ops
.enable_tx_laser
= NULL
;
81 mac
->ops
.flap_tx_laser
= NULL
;
84 if (hw
->phy
.multispeed_fiber
) {
85 /* Set up dual speed SFP+ support */
86 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_multispeed_fiber
;
88 if ((mac
->ops
.get_media_type(hw
) ==
89 ixgbe_media_type_backplane
) &&
90 (hw
->phy
.smart_speed
== ixgbe_smart_speed_auto
||
91 hw
->phy
.smart_speed
== ixgbe_smart_speed_on
) &&
92 !ixgbe_verify_lesm_fw_enabled_82599(hw
))
93 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_smartspeed
;
95 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_82599
;
99 static s32
ixgbe_setup_sfp_modules_82599(struct ixgbe_hw
*hw
)
104 u16 list_offset
, data_offset
, data_value
;
106 if (hw
->phy
.sfp_type
!= ixgbe_sfp_type_unknown
) {
107 ixgbe_init_mac_link_ops_82599(hw
);
109 hw
->phy
.ops
.reset
= NULL
;
111 ret_val
= ixgbe_get_sfp_init_sequence_offsets(hw
, &list_offset
,
116 /* PHY config will finish before releasing the semaphore */
117 ret_val
= hw
->mac
.ops
.acquire_swfw_sync(hw
,
118 IXGBE_GSSR_MAC_CSR_SM
);
120 ret_val
= IXGBE_ERR_SWFW_SYNC
;
124 hw
->eeprom
.ops
.read(hw
, ++data_offset
, &data_value
);
125 while (data_value
!= 0xffff) {
126 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, data_value
);
127 IXGBE_WRITE_FLUSH(hw
);
128 hw
->eeprom
.ops
.read(hw
, ++data_offset
, &data_value
);
131 /* Release the semaphore */
132 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_MAC_CSR_SM
);
134 * Delay obtaining semaphore again to allow FW access,
135 * semaphore_delay is in ms usleep_range needs us.
137 usleep_range(hw
->eeprom
.semaphore_delay
* 1000,
138 hw
->eeprom
.semaphore_delay
* 2000);
140 /* Now restart DSP by setting Restart_AN and clearing LMS */
141 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, ((IXGBE_READ_REG(hw
,
142 IXGBE_AUTOC
) & ~IXGBE_AUTOC_LMS_MASK
) |
143 IXGBE_AUTOC_AN_RESTART
));
145 /* Wait for AN to leave state 0 */
146 for (i
= 0; i
< 10; i
++) {
147 usleep_range(4000, 8000);
148 reg_anlp1
= IXGBE_READ_REG(hw
, IXGBE_ANLP1
);
149 if (reg_anlp1
& IXGBE_ANLP1_AN_STATE_MASK
)
152 if (!(reg_anlp1
& IXGBE_ANLP1_AN_STATE_MASK
)) {
153 hw_dbg(hw
, "sfp module setup not complete\n");
154 ret_val
= IXGBE_ERR_SFP_SETUP_NOT_COMPLETE
;
158 /* Restart DSP by setting Restart_AN and return to SFI mode */
159 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, (IXGBE_READ_REG(hw
,
160 IXGBE_AUTOC
) | IXGBE_AUTOC_LMS_10G_SERIAL
|
161 IXGBE_AUTOC_AN_RESTART
));
168 static s32
ixgbe_get_invariants_82599(struct ixgbe_hw
*hw
)
170 struct ixgbe_mac_info
*mac
= &hw
->mac
;
172 ixgbe_init_mac_link_ops_82599(hw
);
174 mac
->mcft_size
= IXGBE_82599_MC_TBL_SIZE
;
175 mac
->vft_size
= IXGBE_82599_VFT_TBL_SIZE
;
176 mac
->num_rar_entries
= IXGBE_82599_RAR_ENTRIES
;
177 mac
->max_rx_queues
= IXGBE_82599_MAX_RX_QUEUES
;
178 mac
->max_tx_queues
= IXGBE_82599_MAX_TX_QUEUES
;
179 mac
->max_msix_vectors
= ixgbe_get_pcie_msix_count_generic(hw
);
185 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
186 * @hw: pointer to hardware structure
188 * Initialize any function pointers that were not able to be
189 * set during get_invariants because the PHY/SFP type was
190 * not known. Perform the SFP init if necessary.
193 static s32
ixgbe_init_phy_ops_82599(struct ixgbe_hw
*hw
)
195 struct ixgbe_mac_info
*mac
= &hw
->mac
;
196 struct ixgbe_phy_info
*phy
= &hw
->phy
;
199 /* Identify the PHY or SFP module */
200 ret_val
= phy
->ops
.identify(hw
);
202 /* Setup function pointers based on detected SFP module and speeds */
203 ixgbe_init_mac_link_ops_82599(hw
);
205 /* If copper media, overwrite with copper function pointers */
206 if (mac
->ops
.get_media_type(hw
) == ixgbe_media_type_copper
) {
207 mac
->ops
.setup_link
= &ixgbe_setup_copper_link_82599
;
208 mac
->ops
.get_link_capabilities
=
209 &ixgbe_get_copper_link_capabilities_generic
;
212 /* Set necessary function pointers based on phy type */
213 switch (hw
->phy
.type
) {
215 phy
->ops
.check_link
= &ixgbe_check_phy_link_tnx
;
216 phy
->ops
.setup_link
= &ixgbe_setup_phy_link_tnx
;
217 phy
->ops
.get_firmware_version
=
218 &ixgbe_get_phy_firmware_version_tnx
;
228 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
229 * @hw: pointer to hardware structure
230 * @speed: pointer to link speed
231 * @negotiation: true when autoneg or autotry is enabled
233 * Determines the link capabilities by reading the AUTOC register.
235 static s32
ixgbe_get_link_capabilities_82599(struct ixgbe_hw
*hw
,
236 ixgbe_link_speed
*speed
,
242 /* Determine 1G link capabilities off of SFP+ type */
243 if (hw
->phy
.sfp_type
== ixgbe_sfp_type_1g_cu_core0
||
244 hw
->phy
.sfp_type
== ixgbe_sfp_type_1g_cu_core1
||
245 hw
->phy
.sfp_type
== ixgbe_sfp_type_1g_sx_core0
||
246 hw
->phy
.sfp_type
== ixgbe_sfp_type_1g_sx_core1
) {
247 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
253 * Determine link capabilities based on the stored value of AUTOC,
254 * which represents EEPROM defaults. If AUTOC value has not been
255 * stored, use the current register value.
257 if (hw
->mac
.orig_link_settings_stored
)
258 autoc
= hw
->mac
.orig_autoc
;
260 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
262 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
263 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
264 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
265 *negotiation
= false;
268 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
269 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
270 *negotiation
= false;
273 case IXGBE_AUTOC_LMS_1G_AN
:
274 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
278 case IXGBE_AUTOC_LMS_10G_SERIAL
:
279 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
280 *negotiation
= false;
283 case IXGBE_AUTOC_LMS_KX4_KX_KR
:
284 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
:
285 *speed
= IXGBE_LINK_SPEED_UNKNOWN
;
286 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
287 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
288 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
289 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
290 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
291 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
295 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
:
296 *speed
= IXGBE_LINK_SPEED_100_FULL
;
297 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
298 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
299 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
300 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
301 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
302 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
306 case IXGBE_AUTOC_LMS_SGMII_1G_100M
:
307 *speed
= IXGBE_LINK_SPEED_1GB_FULL
| IXGBE_LINK_SPEED_100_FULL
;
308 *negotiation
= false;
312 status
= IXGBE_ERR_LINK_SETUP
;
317 if (hw
->phy
.multispeed_fiber
) {
318 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
|
319 IXGBE_LINK_SPEED_1GB_FULL
;
328 * ixgbe_get_media_type_82599 - Get media type
329 * @hw: pointer to hardware structure
331 * Returns the media type (fiber, copper, backplane)
333 static enum ixgbe_media_type
ixgbe_get_media_type_82599(struct ixgbe_hw
*hw
)
335 enum ixgbe_media_type media_type
;
337 /* Detect if there is a copper PHY attached. */
338 switch (hw
->phy
.type
) {
339 case ixgbe_phy_cu_unknown
:
341 media_type
= ixgbe_media_type_copper
;
347 switch (hw
->device_id
) {
348 case IXGBE_DEV_ID_82599_KX4
:
349 case IXGBE_DEV_ID_82599_KX4_MEZZ
:
350 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE
:
351 case IXGBE_DEV_ID_82599_KR
:
352 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE
:
353 case IXGBE_DEV_ID_82599_XAUI_LOM
:
354 /* Default device ID is mezzanine card KX/KX4 */
355 media_type
= ixgbe_media_type_backplane
;
357 case IXGBE_DEV_ID_82599_SFP
:
358 case IXGBE_DEV_ID_82599_SFP_FCOE
:
359 case IXGBE_DEV_ID_82599_SFP_EM
:
360 case IXGBE_DEV_ID_82599_SFP_SF2
:
361 case IXGBE_DEV_ID_82599_SFP_SF_QP
:
362 case IXGBE_DEV_ID_82599EN_SFP
:
363 media_type
= ixgbe_media_type_fiber
;
365 case IXGBE_DEV_ID_82599_CX4
:
366 media_type
= ixgbe_media_type_cx4
;
368 case IXGBE_DEV_ID_82599_T3_LOM
:
369 media_type
= ixgbe_media_type_copper
;
371 case IXGBE_DEV_ID_82599_LS
:
372 media_type
= ixgbe_media_type_fiber_lco
;
375 media_type
= ixgbe_media_type_unknown
;
383 * ixgbe_start_mac_link_82599 - Setup MAC link settings
384 * @hw: pointer to hardware structure
385 * @autoneg_wait_to_complete: true when waiting for completion is needed
387 * Configures link settings based on values in the ixgbe_hw struct.
388 * Restarts the link. Performs autonegotiation if needed.
390 static s32
ixgbe_start_mac_link_82599(struct ixgbe_hw
*hw
,
391 bool autoneg_wait_to_complete
)
399 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
400 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
401 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
403 /* Only poll for autoneg to complete if specified to do so */
404 if (autoneg_wait_to_complete
) {
405 if ((autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
406 IXGBE_AUTOC_LMS_KX4_KX_KR
||
407 (autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
408 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
409 (autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
410 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
411 links_reg
= 0; /* Just in case Autoneg time = 0 */
412 for (i
= 0; i
< IXGBE_AUTO_NEG_TIME
; i
++) {
413 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
414 if (links_reg
& IXGBE_LINKS_KX_AN_COMP
)
418 if (!(links_reg
& IXGBE_LINKS_KX_AN_COMP
)) {
419 status
= IXGBE_ERR_AUTONEG_NOT_COMPLETE
;
420 hw_dbg(hw
, "Autoneg did not complete.\n");
425 /* Add delay to filter out noises during initial link setup */
432 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
433 * @hw: pointer to hardware structure
435 * The base drivers may require better control over SFP+ module
436 * PHY states. This includes selectively shutting down the Tx
437 * laser on the PHY, effectively halting physical link.
439 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
441 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
443 /* Disable tx laser; allow 100us to go dark per spec */
444 esdp_reg
|= IXGBE_ESDP_SDP3
;
445 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
446 IXGBE_WRITE_FLUSH(hw
);
451 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
452 * @hw: pointer to hardware structure
454 * The base drivers may require better control over SFP+ module
455 * PHY states. This includes selectively turning on the Tx
456 * laser on the PHY, effectively starting physical link.
458 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
460 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
462 /* Enable tx laser; allow 100ms to light up */
463 esdp_reg
&= ~IXGBE_ESDP_SDP3
;
464 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
465 IXGBE_WRITE_FLUSH(hw
);
470 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
471 * @hw: pointer to hardware structure
473 * When the driver changes the link speeds that it can support,
474 * it sets autotry_restart to true to indicate that we need to
475 * initiate a new autotry session with the link partner. To do
476 * so, we set the speed then disable and re-enable the tx laser, to
477 * alert the link partner that it also needs to restart autotry on its
478 * end. This is consistent with true clause 37 autoneg, which also
479 * involves a loss of signal.
481 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
483 if (hw
->mac
.autotry_restart
) {
484 ixgbe_disable_tx_laser_multispeed_fiber(hw
);
485 ixgbe_enable_tx_laser_multispeed_fiber(hw
);
486 hw
->mac
.autotry_restart
= false;
491 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
492 * @hw: pointer to hardware structure
493 * @speed: new link speed
494 * @autoneg: true if autonegotiation enabled
495 * @autoneg_wait_to_complete: true when waiting for completion is needed
497 * Set the link speed in the AUTOC register and restarts link.
499 static s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
500 ixgbe_link_speed speed
,
502 bool autoneg_wait_to_complete
)
505 ixgbe_link_speed link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
506 ixgbe_link_speed highest_link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
508 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
510 bool link_up
= false;
513 /* Mask off requested but non-supported speeds */
514 status
= hw
->mac
.ops
.get_link_capabilities(hw
, &link_speed
,
522 * Try each speed one by one, highest priority first. We do this in
523 * software because 10gb fiber doesn't support speed autonegotiation.
525 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
) {
527 highest_link_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
529 /* If we already have link at this speed, just jump out */
530 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
535 if ((link_speed
== IXGBE_LINK_SPEED_10GB_FULL
) && link_up
)
538 /* Set the module link speed */
539 esdp_reg
|= (IXGBE_ESDP_SDP5_DIR
| IXGBE_ESDP_SDP5
);
540 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
541 IXGBE_WRITE_FLUSH(hw
);
543 /* Allow module to change analog characteristics (1G->10G) */
546 status
= ixgbe_setup_mac_link_82599(hw
,
547 IXGBE_LINK_SPEED_10GB_FULL
,
549 autoneg_wait_to_complete
);
553 /* Flap the tx laser if it has not already been done */
554 hw
->mac
.ops
.flap_tx_laser(hw
);
557 * Wait for the controller to acquire link. Per IEEE 802.3ap,
558 * Section 73.10.2, we may have to wait up to 500ms if KR is
559 * attempted. 82599 uses the same timing for 10g SFI.
561 for (i
= 0; i
< 5; i
++) {
562 /* Wait for the link partner to also set speed */
565 /* If we have link, just jump out */
566 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
,
576 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
) {
578 if (highest_link_speed
== IXGBE_LINK_SPEED_UNKNOWN
)
579 highest_link_speed
= IXGBE_LINK_SPEED_1GB_FULL
;
581 /* If we already have link at this speed, just jump out */
582 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
587 if ((link_speed
== IXGBE_LINK_SPEED_1GB_FULL
) && link_up
)
590 /* Set the module link speed */
591 esdp_reg
&= ~IXGBE_ESDP_SDP5
;
592 esdp_reg
|= IXGBE_ESDP_SDP5_DIR
;
593 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
594 IXGBE_WRITE_FLUSH(hw
);
596 /* Allow module to change analog characteristics (10G->1G) */
599 status
= ixgbe_setup_mac_link_82599(hw
,
600 IXGBE_LINK_SPEED_1GB_FULL
,
602 autoneg_wait_to_complete
);
606 /* Flap the tx laser if it has not already been done */
607 hw
->mac
.ops
.flap_tx_laser(hw
);
609 /* Wait for the link partner to also set speed */
612 /* If we have link, just jump out */
613 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
623 * We didn't get link. Configure back to the highest speed we tried,
624 * (if there was more than one). We call ourselves back with just the
625 * single highest speed that the user requested.
628 status
= ixgbe_setup_mac_link_multispeed_fiber(hw
,
631 autoneg_wait_to_complete
);
634 /* Set autoneg_advertised value based on input link speed */
635 hw
->phy
.autoneg_advertised
= 0;
637 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
638 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
640 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
641 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
647 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
648 * @hw: pointer to hardware structure
649 * @speed: new link speed
650 * @autoneg: true if autonegotiation enabled
651 * @autoneg_wait_to_complete: true when waiting for completion is needed
653 * Implements the Intel SmartSpeed algorithm.
655 static s32
ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw
*hw
,
656 ixgbe_link_speed speed
, bool autoneg
,
657 bool autoneg_wait_to_complete
)
660 ixgbe_link_speed link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
662 bool link_up
= false;
663 u32 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
665 /* Set autoneg_advertised value based on input link speed */
666 hw
->phy
.autoneg_advertised
= 0;
668 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
669 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
671 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
672 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
674 if (speed
& IXGBE_LINK_SPEED_100_FULL
)
675 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_100_FULL
;
678 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
679 * autoneg advertisement if link is unable to be established at the
680 * highest negotiated rate. This can sometimes happen due to integrity
681 * issues with the physical media connection.
684 /* First, try to get link with full advertisement */
685 hw
->phy
.smart_speed_active
= false;
686 for (j
= 0; j
< IXGBE_SMARTSPEED_MAX_RETRIES
; j
++) {
687 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
688 autoneg_wait_to_complete
);
693 * Wait for the controller to acquire link. Per IEEE 802.3ap,
694 * Section 73.10.2, we may have to wait up to 500ms if KR is
695 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
696 * Table 9 in the AN MAS.
698 for (i
= 0; i
< 5; i
++) {
701 /* If we have link, just jump out */
702 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
,
713 * We didn't get link. If we advertised KR plus one of KX4/KX
714 * (or BX4/BX), then disable KR and try again.
716 if (((autoc_reg
& IXGBE_AUTOC_KR_SUPP
) == 0) ||
717 ((autoc_reg
& IXGBE_AUTOC_KX4_KX_SUPP_MASK
) == 0))
720 /* Turn SmartSpeed on to disable KR support */
721 hw
->phy
.smart_speed_active
= true;
722 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
723 autoneg_wait_to_complete
);
728 * Wait for the controller to acquire link. 600ms will allow for
729 * the AN link_fail_inhibit_timer as well for multiple cycles of
730 * parallel detect, both 10g and 1g. This allows for the maximum
731 * connect attempts as defined in the AN MAS table 73-7.
733 for (i
= 0; i
< 6; i
++) {
736 /* If we have link, just jump out */
737 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
,
746 /* We didn't get link. Turn SmartSpeed back off. */
747 hw
->phy
.smart_speed_active
= false;
748 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
749 autoneg_wait_to_complete
);
752 if (link_up
&& (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
))
753 hw_dbg(hw
, "Smartspeed has downgraded the link speed from "
754 "the maximum advertised\n");
759 * ixgbe_setup_mac_link_82599 - Set MAC link speed
760 * @hw: pointer to hardware structure
761 * @speed: new link speed
762 * @autoneg: true if autonegotiation enabled
763 * @autoneg_wait_to_complete: true when waiting for completion is needed
765 * Set the link speed in the AUTOC register and restarts link.
767 static s32
ixgbe_setup_mac_link_82599(struct ixgbe_hw
*hw
,
768 ixgbe_link_speed speed
, bool autoneg
,
769 bool autoneg_wait_to_complete
)
772 u32 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
773 u32 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
774 u32 start_autoc
= autoc
;
776 u32 link_mode
= autoc
& IXGBE_AUTOC_LMS_MASK
;
777 u32 pma_pmd_1g
= autoc
& IXGBE_AUTOC_1G_PMA_PMD_MASK
;
778 u32 pma_pmd_10g_serial
= autoc2
& IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK
;
781 ixgbe_link_speed link_capabilities
= IXGBE_LINK_SPEED_UNKNOWN
;
783 /* Check to see if speed passed in is supported. */
784 status
= hw
->mac
.ops
.get_link_capabilities(hw
, &link_capabilities
,
789 speed
&= link_capabilities
;
791 if (speed
== IXGBE_LINK_SPEED_UNKNOWN
) {
792 status
= IXGBE_ERR_LINK_SETUP
;
796 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
797 if (hw
->mac
.orig_link_settings_stored
)
798 orig_autoc
= hw
->mac
.orig_autoc
;
802 if (link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR
||
803 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
804 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
805 /* Set KX4/KX/KR support according to speed requested */
806 autoc
&= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK
| IXGBE_AUTOC_KR_SUPP
);
807 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
808 if (orig_autoc
& IXGBE_AUTOC_KX4_SUPP
)
809 autoc
|= IXGBE_AUTOC_KX4_SUPP
;
810 if ((orig_autoc
& IXGBE_AUTOC_KR_SUPP
) &&
811 (hw
->phy
.smart_speed_active
== false))
812 autoc
|= IXGBE_AUTOC_KR_SUPP
;
813 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
814 autoc
|= IXGBE_AUTOC_KX_SUPP
;
815 } else if ((pma_pmd_1g
== IXGBE_AUTOC_1G_SFI
) &&
816 (link_mode
== IXGBE_AUTOC_LMS_1G_LINK_NO_AN
||
817 link_mode
== IXGBE_AUTOC_LMS_1G_AN
)) {
818 /* Switch from 1G SFI to 10G SFI if requested */
819 if ((speed
== IXGBE_LINK_SPEED_10GB_FULL
) &&
820 (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
)) {
821 autoc
&= ~IXGBE_AUTOC_LMS_MASK
;
822 autoc
|= IXGBE_AUTOC_LMS_10G_SERIAL
;
824 } else if ((pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
) &&
825 (link_mode
== IXGBE_AUTOC_LMS_10G_SERIAL
)) {
826 /* Switch from 10G SFI to 1G SFI if requested */
827 if ((speed
== IXGBE_LINK_SPEED_1GB_FULL
) &&
828 (pma_pmd_1g
== IXGBE_AUTOC_1G_SFI
)) {
829 autoc
&= ~IXGBE_AUTOC_LMS_MASK
;
831 autoc
|= IXGBE_AUTOC_LMS_1G_AN
;
833 autoc
|= IXGBE_AUTOC_LMS_1G_LINK_NO_AN
;
837 if (autoc
!= start_autoc
) {
839 autoc
|= IXGBE_AUTOC_AN_RESTART
;
840 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc
);
842 /* Only poll for autoneg to complete if specified to do so */
843 if (autoneg_wait_to_complete
) {
844 if (link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR
||
845 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
846 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
847 links_reg
= 0; /*Just in case Autoneg time=0*/
848 for (i
= 0; i
< IXGBE_AUTO_NEG_TIME
; i
++) {
850 IXGBE_READ_REG(hw
, IXGBE_LINKS
);
851 if (links_reg
& IXGBE_LINKS_KX_AN_COMP
)
855 if (!(links_reg
& IXGBE_LINKS_KX_AN_COMP
)) {
857 IXGBE_ERR_AUTONEG_NOT_COMPLETE
;
858 hw_dbg(hw
, "Autoneg did not "
864 /* Add delay to filter out noises during initial link setup */
873 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
874 * @hw: pointer to hardware structure
875 * @speed: new link speed
876 * @autoneg: true if autonegotiation enabled
877 * @autoneg_wait_to_complete: true if waiting is needed to complete
879 * Restarts link on PHY and MAC based on settings passed in.
881 static s32
ixgbe_setup_copper_link_82599(struct ixgbe_hw
*hw
,
882 ixgbe_link_speed speed
,
884 bool autoneg_wait_to_complete
)
888 /* Setup the PHY according to input speed */
889 status
= hw
->phy
.ops
.setup_link_speed(hw
, speed
, autoneg
,
890 autoneg_wait_to_complete
);
892 ixgbe_start_mac_link_82599(hw
, autoneg_wait_to_complete
);
898 * ixgbe_reset_hw_82599 - Perform hardware reset
899 * @hw: pointer to hardware structure
901 * Resets the hardware by resetting the transmit and receive units, masks
902 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
905 static s32
ixgbe_reset_hw_82599(struct ixgbe_hw
*hw
)
907 ixgbe_link_speed link_speed
;
909 u32 ctrl
, i
, autoc
, autoc2
;
910 bool link_up
= false;
912 /* Call adapter stop to disable tx/rx and clear interrupts */
913 status
= hw
->mac
.ops
.stop_adapter(hw
);
917 /* flush pending Tx transactions */
918 ixgbe_clear_tx_pending(hw
);
920 /* PHY ops must be identified and initialized prior to reset */
922 /* Identify PHY and related function pointers */
923 status
= hw
->phy
.ops
.init(hw
);
925 if (status
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
928 /* Setup SFP module if there is one present. */
929 if (hw
->phy
.sfp_setup_needed
) {
930 status
= hw
->mac
.ops
.setup_sfp(hw
);
931 hw
->phy
.sfp_setup_needed
= false;
934 if (status
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
938 if (hw
->phy
.reset_disable
== false && hw
->phy
.ops
.reset
!= NULL
)
939 hw
->phy
.ops
.reset(hw
);
943 * Issue global reset to the MAC. Needs to be SW reset if link is up.
944 * If link reset is used when link is up, it might reset the PHY when
945 * mng is using it. If link is down or the flag to force full link
946 * reset is set, then perform link reset.
948 ctrl
= IXGBE_CTRL_LNK_RST
;
949 if (!hw
->force_full_reset
) {
950 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
952 ctrl
= IXGBE_CTRL_RST
;
955 ctrl
|= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
956 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
957 IXGBE_WRITE_FLUSH(hw
);
959 /* Poll for reset bit to self-clear indicating reset is complete */
960 for (i
= 0; i
< 10; i
++) {
962 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
963 if (!(ctrl
& IXGBE_CTRL_RST_MASK
))
967 if (ctrl
& IXGBE_CTRL_RST_MASK
) {
968 status
= IXGBE_ERR_RESET_FAILED
;
969 hw_dbg(hw
, "Reset polling failed to complete.\n");
975 * Double resets are required for recovery from certain error
976 * conditions. Between resets, it is necessary to stall to allow time
977 * for any pending HW events to complete.
979 if (hw
->mac
.flags
& IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
) {
980 hw
->mac
.flags
&= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
;
985 * Store the original AUTOC/AUTOC2 values if they have not been
986 * stored off yet. Otherwise restore the stored original
987 * values since the reset operation sets back to defaults.
989 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
990 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
991 if (hw
->mac
.orig_link_settings_stored
== false) {
992 hw
->mac
.orig_autoc
= autoc
;
993 hw
->mac
.orig_autoc2
= autoc2
;
994 hw
->mac
.orig_link_settings_stored
= true;
996 if (autoc
!= hw
->mac
.orig_autoc
)
997 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, (hw
->mac
.orig_autoc
|
998 IXGBE_AUTOC_AN_RESTART
));
1000 if ((autoc2
& IXGBE_AUTOC2_UPPER_MASK
) !=
1001 (hw
->mac
.orig_autoc2
& IXGBE_AUTOC2_UPPER_MASK
)) {
1002 autoc2
&= ~IXGBE_AUTOC2_UPPER_MASK
;
1003 autoc2
|= (hw
->mac
.orig_autoc2
&
1004 IXGBE_AUTOC2_UPPER_MASK
);
1005 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC2
, autoc2
);
1009 /* Store the permanent mac address */
1010 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.perm_addr
);
1013 * Store MAC address from RAR0, clear receive address registers, and
1014 * clear the multicast table. Also reset num_rar_entries to 128,
1015 * since we modify this value when programming the SAN MAC address.
1017 hw
->mac
.num_rar_entries
= 128;
1018 hw
->mac
.ops
.init_rx_addrs(hw
);
1020 /* Store the permanent SAN mac address */
1021 hw
->mac
.ops
.get_san_mac_addr(hw
, hw
->mac
.san_addr
);
1023 /* Add the SAN MAC address to the RAR only if it's a valid address */
1024 if (ixgbe_validate_mac_addr(hw
->mac
.san_addr
) == 0) {
1025 hw
->mac
.ops
.set_rar(hw
, hw
->mac
.num_rar_entries
- 1,
1026 hw
->mac
.san_addr
, 0, IXGBE_RAH_AV
);
1028 /* Reserve the last RAR for the SAN MAC address */
1029 hw
->mac
.num_rar_entries
--;
1032 /* Store the alternative WWNN/WWPN prefix */
1033 hw
->mac
.ops
.get_wwn_prefix(hw
, &hw
->mac
.wwnn_prefix
,
1034 &hw
->mac
.wwpn_prefix
);
1041 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1042 * @hw: pointer to hardware structure
1044 s32
ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw
*hw
)
1047 u32 fdirctrl
= IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
);
1048 fdirctrl
&= ~IXGBE_FDIRCTRL_INIT_DONE
;
1051 * Before starting reinitialization process,
1052 * FDIRCMD.CMD must be zero.
1054 for (i
= 0; i
< IXGBE_FDIRCMD_CMD_POLL
; i
++) {
1055 if (!(IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) &
1056 IXGBE_FDIRCMD_CMD_MASK
))
1060 if (i
>= IXGBE_FDIRCMD_CMD_POLL
) {
1061 hw_dbg(hw
, "Flow Director previous command isn't complete, "
1062 "aborting table re-initialization.\n");
1063 return IXGBE_ERR_FDIR_REINIT_FAILED
;
1066 IXGBE_WRITE_REG(hw
, IXGBE_FDIRFREE
, 0);
1067 IXGBE_WRITE_FLUSH(hw
);
1069 * 82599 adapters flow director init flow cannot be restarted,
1070 * Workaround 82599 silicon errata by performing the following steps
1071 * before re-writing the FDIRCTRL control register with the same value.
1072 * - write 1 to bit 8 of FDIRCMD register &
1073 * - write 0 to bit 8 of FDIRCMD register
1075 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
,
1076 (IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) |
1077 IXGBE_FDIRCMD_CLEARHT
));
1078 IXGBE_WRITE_FLUSH(hw
);
1079 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
,
1080 (IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) &
1081 ~IXGBE_FDIRCMD_CLEARHT
));
1082 IXGBE_WRITE_FLUSH(hw
);
1084 * Clear FDIR Hash register to clear any leftover hashes
1085 * waiting to be programmed.
1087 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, 0x00);
1088 IXGBE_WRITE_FLUSH(hw
);
1090 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1091 IXGBE_WRITE_FLUSH(hw
);
1093 /* Poll init-done after we write FDIRCTRL register */
1094 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1095 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1096 IXGBE_FDIRCTRL_INIT_DONE
)
1100 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
) {
1101 hw_dbg(hw
, "Flow Director Signature poll time exceeded!\n");
1102 return IXGBE_ERR_FDIR_REINIT_FAILED
;
1105 /* Clear FDIR statistics registers (read to clear) */
1106 IXGBE_READ_REG(hw
, IXGBE_FDIRUSTAT
);
1107 IXGBE_READ_REG(hw
, IXGBE_FDIRFSTAT
);
1108 IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
1109 IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
1110 IXGBE_READ_REG(hw
, IXGBE_FDIRLEN
);
1116 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1117 * @hw: pointer to hardware structure
1118 * @fdirctrl: value to write to flow director control register
1120 static void ixgbe_fdir_enable_82599(struct ixgbe_hw
*hw
, u32 fdirctrl
)
1124 /* Prime the keys for hashing */
1125 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHKEY
, IXGBE_ATR_BUCKET_HASH_KEY
);
1126 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSKEY
, IXGBE_ATR_SIGNATURE_HASH_KEY
);
1129 * Poll init-done after we write the register. Estimated times:
1130 * 10G: PBALLOC = 11b, timing is 60us
1131 * 1G: PBALLOC = 11b, timing is 600us
1132 * 100M: PBALLOC = 11b, timing is 6ms
1134 * Multiple these timings by 4 if under full Rx load
1136 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1137 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1138 * this might not finish in our poll time, but we can live with that
1141 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1142 IXGBE_WRITE_FLUSH(hw
);
1143 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1144 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1145 IXGBE_FDIRCTRL_INIT_DONE
)
1147 usleep_range(1000, 2000);
1150 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
)
1151 hw_dbg(hw
, "Flow Director poll time exceeded!\n");
1155 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1156 * @hw: pointer to hardware structure
1157 * @fdirctrl: value to write to flow director control register, initially
1158 * contains just the value of the Rx packet buffer allocation
1160 s32
ixgbe_init_fdir_signature_82599(struct ixgbe_hw
*hw
, u32 fdirctrl
)
1163 * Continue setup of fdirctrl register bits:
1164 * Move the flexible bytes to use the ethertype - shift 6 words
1165 * Set the maximum length per hash bucket to 0xA filters
1166 * Send interrupt when 64 filters are left
1168 fdirctrl
|= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT
) |
1169 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT
) |
1170 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT
);
1172 /* write hashes and fdirctrl register, poll for completion */
1173 ixgbe_fdir_enable_82599(hw
, fdirctrl
);
1179 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1180 * @hw: pointer to hardware structure
1181 * @fdirctrl: value to write to flow director control register, initially
1182 * contains just the value of the Rx packet buffer allocation
1184 s32
ixgbe_init_fdir_perfect_82599(struct ixgbe_hw
*hw
, u32 fdirctrl
)
1187 * Continue setup of fdirctrl register bits:
1188 * Turn perfect match filtering on
1189 * Report hash in RSS field of Rx wb descriptor
1190 * Initialize the drop queue
1191 * Move the flexible bytes to use the ethertype - shift 6 words
1192 * Set the maximum length per hash bucket to 0xA filters
1193 * Send interrupt when 64 (0x4 * 16) filters are left
1195 fdirctrl
|= IXGBE_FDIRCTRL_PERFECT_MATCH
|
1196 IXGBE_FDIRCTRL_REPORT_STATUS
|
1197 (IXGBE_FDIR_DROP_QUEUE
<< IXGBE_FDIRCTRL_DROP_Q_SHIFT
) |
1198 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT
) |
1199 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT
) |
1200 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT
);
1202 /* write hashes and fdirctrl register, poll for completion */
1203 ixgbe_fdir_enable_82599(hw
, fdirctrl
);
1209 * These defines allow us to quickly generate all of the necessary instructions
1210 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1211 * for values 0 through 15
1213 #define IXGBE_ATR_COMMON_HASH_KEY \
1214 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1215 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1218 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1219 common_hash ^= lo_hash_dword >> n; \
1220 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1221 bucket_hash ^= lo_hash_dword >> n; \
1222 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1223 sig_hash ^= lo_hash_dword << (16 - n); \
1224 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1225 common_hash ^= hi_hash_dword >> n; \
1226 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1227 bucket_hash ^= hi_hash_dword >> n; \
1228 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1229 sig_hash ^= hi_hash_dword << (16 - n); \
1233 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1234 * @stream: input bitstream to compute the hash on
1236 * This function is almost identical to the function above but contains
1237 * several optomizations such as unwinding all of the loops, letting the
1238 * compiler work out all of the conditional ifs since the keys are static
1239 * defines, and computing two keys at once since the hashed dword stream
1240 * will be the same for both keys.
1242 static u32
ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input
,
1243 union ixgbe_atr_hash_dword common
)
1245 u32 hi_hash_dword
, lo_hash_dword
, flow_vm_vlan
;
1246 u32 sig_hash
= 0, bucket_hash
= 0, common_hash
= 0;
1248 /* record the flow_vm_vlan bits as they are a key part to the hash */
1249 flow_vm_vlan
= ntohl(input
.dword
);
1251 /* generate common hash dword */
1252 hi_hash_dword
= ntohl(common
.dword
);
1254 /* low dword is word swapped version of common */
1255 lo_hash_dword
= (hi_hash_dword
>> 16) | (hi_hash_dword
<< 16);
1257 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1258 hi_hash_dword
^= flow_vm_vlan
^ (flow_vm_vlan
>> 16);
1260 /* Process bits 0 and 16 */
1261 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1264 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1265 * delay this because bit 0 of the stream should not be processed
1266 * so we do not add the vlan until after bit 0 was processed
1268 lo_hash_dword
^= flow_vm_vlan
^ (flow_vm_vlan
<< 16);
1270 /* Process remaining 30 bit of the key */
1271 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1272 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1273 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1274 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1275 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1276 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1277 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1278 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1279 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1280 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1281 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1282 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1283 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1284 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1285 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1287 /* combine common_hash result with signature and bucket hashes */
1288 bucket_hash
^= common_hash
;
1289 bucket_hash
&= IXGBE_ATR_HASH_MASK
;
1291 sig_hash
^= common_hash
<< 16;
1292 sig_hash
&= IXGBE_ATR_HASH_MASK
<< 16;
1294 /* return completed signature hash */
1295 return sig_hash
^ bucket_hash
;
1299 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1300 * @hw: pointer to hardware structure
1301 * @input: unique input dword
1302 * @common: compressed common input dword
1303 * @queue: queue index to direct traffic to
1305 s32
ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw
*hw
,
1306 union ixgbe_atr_hash_dword input
,
1307 union ixgbe_atr_hash_dword common
,
1314 * Get the flow_type in order to program FDIRCMD properly
1315 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1317 switch (input
.formatted
.flow_type
) {
1318 case IXGBE_ATR_FLOW_TYPE_TCPV4
:
1319 case IXGBE_ATR_FLOW_TYPE_UDPV4
:
1320 case IXGBE_ATR_FLOW_TYPE_SCTPV4
:
1321 case IXGBE_ATR_FLOW_TYPE_TCPV6
:
1322 case IXGBE_ATR_FLOW_TYPE_UDPV6
:
1323 case IXGBE_ATR_FLOW_TYPE_SCTPV6
:
1326 hw_dbg(hw
, " Error on flow type input\n");
1327 return IXGBE_ERR_CONFIG
;
1330 /* configure FDIRCMD register */
1331 fdircmd
= IXGBE_FDIRCMD_CMD_ADD_FLOW
| IXGBE_FDIRCMD_FILTER_UPDATE
|
1332 IXGBE_FDIRCMD_LAST
| IXGBE_FDIRCMD_QUEUE_EN
;
1333 fdircmd
|= input
.formatted
.flow_type
<< IXGBE_FDIRCMD_FLOW_TYPE_SHIFT
;
1334 fdircmd
|= (u32
)queue
<< IXGBE_FDIRCMD_RX_QUEUE_SHIFT
;
1337 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1338 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1340 fdirhashcmd
= (u64
)fdircmd
<< 32;
1341 fdirhashcmd
|= ixgbe_atr_compute_sig_hash_82599(input
, common
);
1342 IXGBE_WRITE_REG64(hw
, IXGBE_FDIRHASH
, fdirhashcmd
);
1344 hw_dbg(hw
, "Tx Queue=%x hash=%x\n", queue
, (u32
)fdirhashcmd
);
1349 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1352 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1353 bucket_hash ^= lo_hash_dword >> n; \
1354 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1355 bucket_hash ^= hi_hash_dword >> n; \
1359 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1360 * @atr_input: input bitstream to compute the hash on
1361 * @input_mask: mask for the input bitstream
1363 * This function serves two main purposes. First it applys the input_mask
1364 * to the atr_input resulting in a cleaned up atr_input data stream.
1365 * Secondly it computes the hash and stores it in the bkt_hash field at
1366 * the end of the input byte stream. This way it will be available for
1367 * future use without needing to recompute the hash.
1369 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input
*input
,
1370 union ixgbe_atr_input
*input_mask
)
1373 u32 hi_hash_dword
, lo_hash_dword
, flow_vm_vlan
;
1374 u32 bucket_hash
= 0;
1376 /* Apply masks to input data */
1377 input
->dword_stream
[0] &= input_mask
->dword_stream
[0];
1378 input
->dword_stream
[1] &= input_mask
->dword_stream
[1];
1379 input
->dword_stream
[2] &= input_mask
->dword_stream
[2];
1380 input
->dword_stream
[3] &= input_mask
->dword_stream
[3];
1381 input
->dword_stream
[4] &= input_mask
->dword_stream
[4];
1382 input
->dword_stream
[5] &= input_mask
->dword_stream
[5];
1383 input
->dword_stream
[6] &= input_mask
->dword_stream
[6];
1384 input
->dword_stream
[7] &= input_mask
->dword_stream
[7];
1385 input
->dword_stream
[8] &= input_mask
->dword_stream
[8];
1386 input
->dword_stream
[9] &= input_mask
->dword_stream
[9];
1387 input
->dword_stream
[10] &= input_mask
->dword_stream
[10];
1389 /* record the flow_vm_vlan bits as they are a key part to the hash */
1390 flow_vm_vlan
= ntohl(input
->dword_stream
[0]);
1392 /* generate common hash dword */
1393 hi_hash_dword
= ntohl(input
->dword_stream
[1] ^
1394 input
->dword_stream
[2] ^
1395 input
->dword_stream
[3] ^
1396 input
->dword_stream
[4] ^
1397 input
->dword_stream
[5] ^
1398 input
->dword_stream
[6] ^
1399 input
->dword_stream
[7] ^
1400 input
->dword_stream
[8] ^
1401 input
->dword_stream
[9] ^
1402 input
->dword_stream
[10]);
1404 /* low dword is word swapped version of common */
1405 lo_hash_dword
= (hi_hash_dword
>> 16) | (hi_hash_dword
<< 16);
1407 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1408 hi_hash_dword
^= flow_vm_vlan
^ (flow_vm_vlan
>> 16);
1410 /* Process bits 0 and 16 */
1411 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1414 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1415 * delay this because bit 0 of the stream should not be processed
1416 * so we do not add the vlan until after bit 0 was processed
1418 lo_hash_dword
^= flow_vm_vlan
^ (flow_vm_vlan
<< 16);
1420 /* Process remaining 30 bit of the key */
1421 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1422 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1423 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1424 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1425 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1426 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1427 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1428 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1429 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1430 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1431 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1432 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1433 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1434 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1435 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1438 * Limit hash to 13 bits since max bucket count is 8K.
1439 * Store result at the end of the input stream.
1441 input
->formatted
.bkt_hash
= bucket_hash
& 0x1FFF;
1445 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1446 * @input_mask: mask to be bit swapped
1448 * The source and destination port masks for flow director are bit swapped
1449 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1450 * generate a correctly swapped value we need to bit swap the mask and that
1451 * is what is accomplished by this function.
1453 static u32
ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input
*input_mask
)
1455 u32 mask
= ntohs(input_mask
->formatted
.dst_port
);
1456 mask
<<= IXGBE_FDIRTCPM_DPORTM_SHIFT
;
1457 mask
|= ntohs(input_mask
->formatted
.src_port
);
1458 mask
= ((mask
& 0x55555555) << 1) | ((mask
& 0xAAAAAAAA) >> 1);
1459 mask
= ((mask
& 0x33333333) << 2) | ((mask
& 0xCCCCCCCC) >> 2);
1460 mask
= ((mask
& 0x0F0F0F0F) << 4) | ((mask
& 0xF0F0F0F0) >> 4);
1461 return ((mask
& 0x00FF00FF) << 8) | ((mask
& 0xFF00FF00) >> 8);
1465 * These two macros are meant to address the fact that we have registers
1466 * that are either all or in part big-endian. As a result on big-endian
1467 * systems we will end up byte swapping the value to little-endian before
1468 * it is byte swapped again and written to the hardware in the original
1469 * big-endian format.
1471 #define IXGBE_STORE_AS_BE32(_value) \
1472 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1473 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1475 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1476 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1478 #define IXGBE_STORE_AS_BE16(_value) \
1479 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1481 s32
ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw
*hw
,
1482 union ixgbe_atr_input
*input_mask
)
1484 /* mask IPv6 since it is currently not supported */
1485 u32 fdirm
= IXGBE_FDIRM_DIPv6
;
1489 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1490 * are zero, then assume a full mask for that field. Also assume that
1491 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1492 * cannot be masked out in this implementation.
1494 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1498 /* verify bucket hash is cleared on hash generation */
1499 if (input_mask
->formatted
.bkt_hash
)
1500 hw_dbg(hw
, " bucket hash should always be 0 in mask\n");
1502 /* Program FDIRM and verify partial masks */
1503 switch (input_mask
->formatted
.vm_pool
& 0x7F) {
1505 fdirm
|= IXGBE_FDIRM_POOL
;
1509 hw_dbg(hw
, " Error on vm pool mask\n");
1510 return IXGBE_ERR_CONFIG
;
1513 switch (input_mask
->formatted
.flow_type
& IXGBE_ATR_L4TYPE_MASK
) {
1515 fdirm
|= IXGBE_FDIRM_L4P
;
1516 if (input_mask
->formatted
.dst_port
||
1517 input_mask
->formatted
.src_port
) {
1518 hw_dbg(hw
, " Error on src/dst port mask\n");
1519 return IXGBE_ERR_CONFIG
;
1521 case IXGBE_ATR_L4TYPE_MASK
:
1524 hw_dbg(hw
, " Error on flow type mask\n");
1525 return IXGBE_ERR_CONFIG
;
1528 switch (ntohs(input_mask
->formatted
.vlan_id
) & 0xEFFF) {
1530 /* mask VLAN ID, fall through to mask VLAN priority */
1531 fdirm
|= IXGBE_FDIRM_VLANID
;
1533 /* mask VLAN priority */
1534 fdirm
|= IXGBE_FDIRM_VLANP
;
1537 /* mask VLAN ID only, fall through */
1538 fdirm
|= IXGBE_FDIRM_VLANID
;
1540 /* no VLAN fields masked */
1543 hw_dbg(hw
, " Error on VLAN mask\n");
1544 return IXGBE_ERR_CONFIG
;
1547 switch (input_mask
->formatted
.flex_bytes
& 0xFFFF) {
1549 /* Mask Flex Bytes, fall through */
1550 fdirm
|= IXGBE_FDIRM_FLEX
;
1554 hw_dbg(hw
, " Error on flexible byte mask\n");
1555 return IXGBE_ERR_CONFIG
;
1558 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1559 IXGBE_WRITE_REG(hw
, IXGBE_FDIRM
, fdirm
);
1561 /* store the TCP/UDP port masks, bit reversed from port layout */
1562 fdirtcpm
= ixgbe_get_fdirtcpm_82599(input_mask
);
1564 /* write both the same so that UDP and TCP use the same mask */
1565 IXGBE_WRITE_REG(hw
, IXGBE_FDIRTCPM
, ~fdirtcpm
);
1566 IXGBE_WRITE_REG(hw
, IXGBE_FDIRUDPM
, ~fdirtcpm
);
1568 /* store source and destination IP masks (big-enian) */
1569 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRSIP4M
,
1570 ~input_mask
->formatted
.src_ip
[0]);
1571 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRDIP4M
,
1572 ~input_mask
->formatted
.dst_ip
[0]);
1577 s32
ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw
*hw
,
1578 union ixgbe_atr_input
*input
,
1579 u16 soft_id
, u8 queue
)
1581 u32 fdirport
, fdirvlan
, fdirhash
, fdircmd
;
1583 /* currently IPv6 is not supported, must be programmed with 0 */
1584 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRSIPv6(0),
1585 input
->formatted
.src_ip
[0]);
1586 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRSIPv6(1),
1587 input
->formatted
.src_ip
[1]);
1588 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRSIPv6(2),
1589 input
->formatted
.src_ip
[2]);
1591 /* record the source address (big-endian) */
1592 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRIPSA
, input
->formatted
.src_ip
[0]);
1594 /* record the first 32 bits of the destination address (big-endian) */
1595 IXGBE_WRITE_REG_BE32(hw
, IXGBE_FDIRIPDA
, input
->formatted
.dst_ip
[0]);
1597 /* record source and destination port (little-endian)*/
1598 fdirport
= ntohs(input
->formatted
.dst_port
);
1599 fdirport
<<= IXGBE_FDIRPORT_DESTINATION_SHIFT
;
1600 fdirport
|= ntohs(input
->formatted
.src_port
);
1601 IXGBE_WRITE_REG(hw
, IXGBE_FDIRPORT
, fdirport
);
1603 /* record vlan (little-endian) and flex_bytes(big-endian) */
1604 fdirvlan
= IXGBE_STORE_AS_BE16(input
->formatted
.flex_bytes
);
1605 fdirvlan
<<= IXGBE_FDIRVLAN_FLEX_SHIFT
;
1606 fdirvlan
|= ntohs(input
->formatted
.vlan_id
);
1607 IXGBE_WRITE_REG(hw
, IXGBE_FDIRVLAN
, fdirvlan
);
1609 /* configure FDIRHASH register */
1610 fdirhash
= input
->formatted
.bkt_hash
;
1611 fdirhash
|= soft_id
<< IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT
;
1612 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, fdirhash
);
1615 * flush all previous writes to make certain registers are
1616 * programmed prior to issuing the command
1618 IXGBE_WRITE_FLUSH(hw
);
1620 /* configure FDIRCMD register */
1621 fdircmd
= IXGBE_FDIRCMD_CMD_ADD_FLOW
| IXGBE_FDIRCMD_FILTER_UPDATE
|
1622 IXGBE_FDIRCMD_LAST
| IXGBE_FDIRCMD_QUEUE_EN
;
1623 if (queue
== IXGBE_FDIR_DROP_QUEUE
)
1624 fdircmd
|= IXGBE_FDIRCMD_DROP
;
1625 fdircmd
|= input
->formatted
.flow_type
<< IXGBE_FDIRCMD_FLOW_TYPE_SHIFT
;
1626 fdircmd
|= (u32
)queue
<< IXGBE_FDIRCMD_RX_QUEUE_SHIFT
;
1627 fdircmd
|= (u32
)input
->formatted
.vm_pool
<< IXGBE_FDIRCMD_VT_POOL_SHIFT
;
1629 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
, fdircmd
);
1634 s32
ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw
*hw
,
1635 union ixgbe_atr_input
*input
,
1643 /* configure FDIRHASH register */
1644 fdirhash
= input
->formatted
.bkt_hash
;
1645 fdirhash
|= soft_id
<< IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT
;
1646 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, fdirhash
);
1648 /* flush hash to HW */
1649 IXGBE_WRITE_FLUSH(hw
);
1651 /* Query if filter is present */
1652 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT
);
1654 for (retry_count
= 10; retry_count
; retry_count
--) {
1655 /* allow 10us for query to process */
1657 /* verify query completed successfully */
1658 fdircmd
= IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
);
1659 if (!(fdircmd
& IXGBE_FDIRCMD_CMD_MASK
))
1664 err
= IXGBE_ERR_FDIR_REINIT_FAILED
;
1666 /* if filter exists in hardware then remove it */
1667 if (fdircmd
& IXGBE_FDIRCMD_FILTER_VALID
) {
1668 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, fdirhash
);
1669 IXGBE_WRITE_FLUSH(hw
);
1670 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
,
1671 IXGBE_FDIRCMD_CMD_REMOVE_FLOW
);
1678 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1679 * @hw: pointer to hardware structure
1680 * @reg: analog register to read
1683 * Performs read operation to Omer analog register specified.
1685 static s32
ixgbe_read_analog_reg8_82599(struct ixgbe_hw
*hw
, u32 reg
, u8
*val
)
1689 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, IXGBE_CORECTL_WRITE_CMD
|
1691 IXGBE_WRITE_FLUSH(hw
);
1693 core_ctl
= IXGBE_READ_REG(hw
, IXGBE_CORECTL
);
1694 *val
= (u8
)core_ctl
;
1700 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1701 * @hw: pointer to hardware structure
1702 * @reg: atlas register to write
1703 * @val: value to write
1705 * Performs write operation to Omer analog register specified.
1707 static s32
ixgbe_write_analog_reg8_82599(struct ixgbe_hw
*hw
, u32 reg
, u8 val
)
1711 core_ctl
= (reg
<< 8) | val
;
1712 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, core_ctl
);
1713 IXGBE_WRITE_FLUSH(hw
);
1720 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1721 * @hw: pointer to hardware structure
1723 * Starts the hardware using the generic start_hw function
1724 * and the generation start_hw function.
1725 * Then performs revision-specific operations, if any.
1727 static s32
ixgbe_start_hw_82599(struct ixgbe_hw
*hw
)
1731 ret_val
= ixgbe_start_hw_generic(hw
);
1735 ret_val
= ixgbe_start_hw_gen2(hw
);
1739 /* We need to run link autotry after the driver loads */
1740 hw
->mac
.autotry_restart
= true;
1741 hw
->mac
.rx_pb_size
= IXGBE_82599_RX_PB_SIZE
;
1744 ret_val
= ixgbe_verify_fw_version_82599(hw
);
1750 * ixgbe_identify_phy_82599 - Get physical layer module
1751 * @hw: pointer to hardware structure
1753 * Determines the physical layer module found on the current adapter.
1754 * If PHY already detected, maintains current PHY type in hw struct,
1755 * otherwise executes the PHY detection routine.
1757 static s32
ixgbe_identify_phy_82599(struct ixgbe_hw
*hw
)
1759 s32 status
= IXGBE_ERR_PHY_ADDR_INVALID
;
1761 /* Detect PHY if not unknown - returns success if already detected. */
1762 status
= ixgbe_identify_phy_generic(hw
);
1764 /* 82599 10GBASE-T requires an external PHY */
1765 if (hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_copper
)
1768 status
= ixgbe_identify_sfp_module_generic(hw
);
1771 /* Set PHY type none if no PHY detected */
1772 if (hw
->phy
.type
== ixgbe_phy_unknown
) {
1773 hw
->phy
.type
= ixgbe_phy_none
;
1777 /* Return error if SFP module has been detected but is not supported */
1778 if (hw
->phy
.type
== ixgbe_phy_sfp_unsupported
)
1779 status
= IXGBE_ERR_SFP_NOT_SUPPORTED
;
1786 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1787 * @hw: pointer to hardware structure
1789 * Determines physical layer capabilities of the current configuration.
1791 static u32
ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw
*hw
)
1793 u32 physical_layer
= IXGBE_PHYSICAL_LAYER_UNKNOWN
;
1794 u32 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
1795 u32 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
1796 u32 pma_pmd_10g_serial
= autoc2
& IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK
;
1797 u32 pma_pmd_10g_parallel
= autoc
& IXGBE_AUTOC_10G_PMA_PMD_MASK
;
1798 u32 pma_pmd_1g
= autoc
& IXGBE_AUTOC_1G_PMA_PMD_MASK
;
1799 u16 ext_ability
= 0;
1800 u8 comp_codes_10g
= 0;
1801 u8 comp_codes_1g
= 0;
1803 hw
->phy
.ops
.identify(hw
);
1805 switch (hw
->phy
.type
) {
1807 case ixgbe_phy_cu_unknown
:
1808 hw
->phy
.ops
.read_reg(hw
, MDIO_PMA_EXTABLE
, MDIO_MMD_PMAPMD
,
1810 if (ext_ability
& MDIO_PMA_EXTABLE_10GBT
)
1811 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_T
;
1812 if (ext_ability
& MDIO_PMA_EXTABLE_1000BT
)
1813 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_T
;
1814 if (ext_ability
& MDIO_PMA_EXTABLE_100BTX
)
1815 physical_layer
|= IXGBE_PHYSICAL_LAYER_100BASE_TX
;
1821 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
1822 case IXGBE_AUTOC_LMS_1G_AN
:
1823 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
1824 if (pma_pmd_1g
== IXGBE_AUTOC_1G_KX_BX
) {
1825 physical_layer
= IXGBE_PHYSICAL_LAYER_1000BASE_KX
|
1826 IXGBE_PHYSICAL_LAYER_1000BASE_BX
;
1829 /* SFI mode so read SFP module */
1832 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
1833 if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_CX4
)
1834 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_CX4
;
1835 else if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_KX4
)
1836 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
1837 else if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_XAUI
)
1838 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_XAUI
;
1841 case IXGBE_AUTOC_LMS_10G_SERIAL
:
1842 if (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_KR
) {
1843 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_KR
;
1845 } else if (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
)
1848 case IXGBE_AUTOC_LMS_KX4_KX_KR
:
1849 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
:
1850 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
1851 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_KX
;
1852 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
1853 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
1854 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
1855 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_KR
;
1864 /* SFP check must be done last since DA modules are sometimes used to
1865 * test KR mode - we need to id KR mode correctly before SFP module.
1866 * Call identify_sfp because the pluggable module may have changed */
1867 hw
->phy
.ops
.identify_sfp(hw
);
1868 if (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)
1871 switch (hw
->phy
.type
) {
1872 case ixgbe_phy_sfp_passive_tyco
:
1873 case ixgbe_phy_sfp_passive_unknown
:
1874 physical_layer
= IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU
;
1876 case ixgbe_phy_sfp_ftl_active
:
1877 case ixgbe_phy_sfp_active_unknown
:
1878 physical_layer
= IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA
;
1880 case ixgbe_phy_sfp_avago
:
1881 case ixgbe_phy_sfp_ftl
:
1882 case ixgbe_phy_sfp_intel
:
1883 case ixgbe_phy_sfp_unknown
:
1884 hw
->phy
.ops
.read_i2c_eeprom(hw
,
1885 IXGBE_SFF_1GBE_COMP_CODES
, &comp_codes_1g
);
1886 hw
->phy
.ops
.read_i2c_eeprom(hw
,
1887 IXGBE_SFF_10GBE_COMP_CODES
, &comp_codes_10g
);
1888 if (comp_codes_10g
& IXGBE_SFF_10GBASESR_CAPABLE
)
1889 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_SR
;
1890 else if (comp_codes_10g
& IXGBE_SFF_10GBASELR_CAPABLE
)
1891 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_LR
;
1892 else if (comp_codes_1g
& IXGBE_SFF_1GBASET_CAPABLE
)
1893 physical_layer
= IXGBE_PHYSICAL_LAYER_1000BASE_T
;
1900 return physical_layer
;
1904 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1905 * @hw: pointer to hardware structure
1906 * @regval: register value to write to RXCTRL
1908 * Enables the Rx DMA unit for 82599
1910 static s32
ixgbe_enable_rx_dma_82599(struct ixgbe_hw
*hw
, u32 regval
)
1913 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1914 * If traffic is incoming before we enable the Rx unit, it could hang
1915 * the Rx DMA unit. Therefore, make sure the security engine is
1916 * completely disabled prior to enabling the Rx unit.
1918 hw
->mac
.ops
.disable_rx_buff(hw
);
1920 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, regval
);
1922 hw
->mac
.ops
.enable_rx_buff(hw
);
1928 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
1929 * @hw: pointer to hardware structure
1931 * Verifies that installed the firmware version is 0.6 or higher
1932 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
1934 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
1935 * if the FW version is not supported.
1937 static s32
ixgbe_verify_fw_version_82599(struct ixgbe_hw
*hw
)
1939 s32 status
= IXGBE_ERR_EEPROM_VERSION
;
1940 u16 fw_offset
, fw_ptp_cfg_offset
;
1943 /* firmware check is only necessary for SFI devices */
1944 if (hw
->phy
.media_type
!= ixgbe_media_type_fiber
) {
1946 goto fw_version_out
;
1949 /* get the offset to the Firmware Module block */
1950 hw
->eeprom
.ops
.read(hw
, IXGBE_FW_PTR
, &fw_offset
);
1952 if ((fw_offset
== 0) || (fw_offset
== 0xFFFF))
1953 goto fw_version_out
;
1955 /* get the offset to the Pass Through Patch Configuration block */
1956 hw
->eeprom
.ops
.read(hw
, (fw_offset
+
1957 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR
),
1958 &fw_ptp_cfg_offset
);
1960 if ((fw_ptp_cfg_offset
== 0) || (fw_ptp_cfg_offset
== 0xFFFF))
1961 goto fw_version_out
;
1963 /* get the firmware version */
1964 hw
->eeprom
.ops
.read(hw
, (fw_ptp_cfg_offset
+
1965 IXGBE_FW_PATCH_VERSION_4
),
1968 if (fw_version
> 0x5)
1976 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
1977 * @hw: pointer to hardware structure
1979 * Returns true if the LESM FW module is present and enabled. Otherwise
1980 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
1982 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw
*hw
)
1984 bool lesm_enabled
= false;
1985 u16 fw_offset
, fw_lesm_param_offset
, fw_lesm_state
;
1988 /* get the offset to the Firmware Module block */
1989 status
= hw
->eeprom
.ops
.read(hw
, IXGBE_FW_PTR
, &fw_offset
);
1991 if ((status
!= 0) ||
1992 (fw_offset
== 0) || (fw_offset
== 0xFFFF))
1995 /* get the offset to the LESM Parameters block */
1996 status
= hw
->eeprom
.ops
.read(hw
, (fw_offset
+
1997 IXGBE_FW_LESM_PARAMETERS_PTR
),
1998 &fw_lesm_param_offset
);
2000 if ((status
!= 0) ||
2001 (fw_lesm_param_offset
== 0) || (fw_lesm_param_offset
== 0xFFFF))
2004 /* get the lesm state word */
2005 status
= hw
->eeprom
.ops
.read(hw
, (fw_lesm_param_offset
+
2006 IXGBE_FW_LESM_STATE_1
),
2009 if ((status
== 0) &&
2010 (fw_lesm_state
& IXGBE_FW_LESM_STATE_ENABLED
))
2011 lesm_enabled
= true;
2014 return lesm_enabled
;
2018 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2019 * fastest available method
2021 * @hw: pointer to hardware structure
2022 * @offset: offset of word in EEPROM to read
2023 * @words: number of words
2024 * @data: word(s) read from the EEPROM
2026 * Retrieves 16 bit word(s) read from EEPROM
2028 static s32
ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw
*hw
, u16 offset
,
2029 u16 words
, u16
*data
)
2031 struct ixgbe_eeprom_info
*eeprom
= &hw
->eeprom
;
2032 s32 ret_val
= IXGBE_ERR_CONFIG
;
2035 * If EEPROM is detected and can be addressed using 14 bits,
2036 * use EERD otherwise use bit bang
2038 if ((eeprom
->type
== ixgbe_eeprom_spi
) &&
2039 (offset
+ (words
- 1) <= IXGBE_EERD_MAX_ADDR
))
2040 ret_val
= ixgbe_read_eerd_buffer_generic(hw
, offset
, words
,
2043 ret_val
= ixgbe_read_eeprom_buffer_bit_bang_generic(hw
, offset
,
2051 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2052 * fastest available method
2054 * @hw: pointer to hardware structure
2055 * @offset: offset of word in the EEPROM to read
2056 * @data: word read from the EEPROM
2058 * Reads a 16 bit word from the EEPROM
2060 static s32
ixgbe_read_eeprom_82599(struct ixgbe_hw
*hw
,
2061 u16 offset
, u16
*data
)
2063 struct ixgbe_eeprom_info
*eeprom
= &hw
->eeprom
;
2064 s32 ret_val
= IXGBE_ERR_CONFIG
;
2067 * If EEPROM is detected and can be addressed using 14 bits,
2068 * use EERD otherwise use bit bang
2070 if ((eeprom
->type
== ixgbe_eeprom_spi
) &&
2071 (offset
<= IXGBE_EERD_MAX_ADDR
))
2072 ret_val
= ixgbe_read_eerd_generic(hw
, offset
, data
);
2074 ret_val
= ixgbe_read_eeprom_bit_bang_generic(hw
, offset
, data
);
2079 static struct ixgbe_mac_operations mac_ops_82599
= {
2080 .init_hw
= &ixgbe_init_hw_generic
,
2081 .reset_hw
= &ixgbe_reset_hw_82599
,
2082 .start_hw
= &ixgbe_start_hw_82599
,
2083 .clear_hw_cntrs
= &ixgbe_clear_hw_cntrs_generic
,
2084 .get_media_type
= &ixgbe_get_media_type_82599
,
2085 .get_supported_physical_layer
= &ixgbe_get_supported_physical_layer_82599
,
2086 .enable_rx_dma
= &ixgbe_enable_rx_dma_82599
,
2087 .disable_rx_buff
= &ixgbe_disable_rx_buff_generic
,
2088 .enable_rx_buff
= &ixgbe_enable_rx_buff_generic
,
2089 .get_mac_addr
= &ixgbe_get_mac_addr_generic
,
2090 .get_san_mac_addr
= &ixgbe_get_san_mac_addr_generic
,
2091 .get_device_caps
= &ixgbe_get_device_caps_generic
,
2092 .get_wwn_prefix
= &ixgbe_get_wwn_prefix_generic
,
2093 .stop_adapter
= &ixgbe_stop_adapter_generic
,
2094 .get_bus_info
= &ixgbe_get_bus_info_generic
,
2095 .set_lan_id
= &ixgbe_set_lan_id_multi_port_pcie
,
2096 .read_analog_reg8
= &ixgbe_read_analog_reg8_82599
,
2097 .write_analog_reg8
= &ixgbe_write_analog_reg8_82599
,
2098 .setup_link
= &ixgbe_setup_mac_link_82599
,
2099 .set_rxpba
= &ixgbe_set_rxpba_generic
,
2100 .check_link
= &ixgbe_check_mac_link_generic
,
2101 .get_link_capabilities
= &ixgbe_get_link_capabilities_82599
,
2102 .led_on
= &ixgbe_led_on_generic
,
2103 .led_off
= &ixgbe_led_off_generic
,
2104 .blink_led_start
= &ixgbe_blink_led_start_generic
,
2105 .blink_led_stop
= &ixgbe_blink_led_stop_generic
,
2106 .set_rar
= &ixgbe_set_rar_generic
,
2107 .clear_rar
= &ixgbe_clear_rar_generic
,
2108 .set_vmdq
= &ixgbe_set_vmdq_generic
,
2109 .clear_vmdq
= &ixgbe_clear_vmdq_generic
,
2110 .init_rx_addrs
= &ixgbe_init_rx_addrs_generic
,
2111 .update_mc_addr_list
= &ixgbe_update_mc_addr_list_generic
,
2112 .enable_mc
= &ixgbe_enable_mc_generic
,
2113 .disable_mc
= &ixgbe_disable_mc_generic
,
2114 .clear_vfta
= &ixgbe_clear_vfta_generic
,
2115 .set_vfta
= &ixgbe_set_vfta_generic
,
2116 .fc_enable
= &ixgbe_fc_enable_generic
,
2117 .set_fw_drv_ver
= &ixgbe_set_fw_drv_ver_generic
,
2118 .init_uta_tables
= &ixgbe_init_uta_tables_generic
,
2119 .setup_sfp
= &ixgbe_setup_sfp_modules_82599
,
2120 .set_mac_anti_spoofing
= &ixgbe_set_mac_anti_spoofing
,
2121 .set_vlan_anti_spoofing
= &ixgbe_set_vlan_anti_spoofing
,
2122 .acquire_swfw_sync
= &ixgbe_acquire_swfw_sync
,
2123 .release_swfw_sync
= &ixgbe_release_swfw_sync
,
2124 .get_thermal_sensor_data
= &ixgbe_get_thermal_sensor_data_generic
,
2125 .init_thermal_sensor_thresh
= &ixgbe_init_thermal_sensor_thresh_generic
,
2129 static struct ixgbe_eeprom_operations eeprom_ops_82599
= {
2130 .init_params
= &ixgbe_init_eeprom_params_generic
,
2131 .read
= &ixgbe_read_eeprom_82599
,
2132 .read_buffer
= &ixgbe_read_eeprom_buffer_82599
,
2133 .write
= &ixgbe_write_eeprom_generic
,
2134 .write_buffer
= &ixgbe_write_eeprom_buffer_bit_bang_generic
,
2135 .calc_checksum
= &ixgbe_calc_eeprom_checksum_generic
,
2136 .validate_checksum
= &ixgbe_validate_eeprom_checksum_generic
,
2137 .update_checksum
= &ixgbe_update_eeprom_checksum_generic
,
2140 static struct ixgbe_phy_operations phy_ops_82599
= {
2141 .identify
= &ixgbe_identify_phy_82599
,
2142 .identify_sfp
= &ixgbe_identify_sfp_module_generic
,
2143 .init
= &ixgbe_init_phy_ops_82599
,
2144 .reset
= &ixgbe_reset_phy_generic
,
2145 .read_reg
= &ixgbe_read_phy_reg_generic
,
2146 .write_reg
= &ixgbe_write_phy_reg_generic
,
2147 .setup_link
= &ixgbe_setup_phy_link_generic
,
2148 .setup_link_speed
= &ixgbe_setup_phy_link_speed_generic
,
2149 .read_i2c_byte
= &ixgbe_read_i2c_byte_generic
,
2150 .write_i2c_byte
= &ixgbe_write_i2c_byte_generic
,
2151 .read_i2c_eeprom
= &ixgbe_read_i2c_eeprom_generic
,
2152 .write_i2c_eeprom
= &ixgbe_write_i2c_eeprom_generic
,
2153 .check_overtemp
= &ixgbe_tn_check_overtemp
,
2156 struct ixgbe_info ixgbe_82599_info
= {
2157 .mac
= ixgbe_mac_82599EB
,
2158 .get_invariants
= &ixgbe_get_invariants_82599
,
2159 .mac_ops
= &mac_ops_82599
,
2160 .eeprom_ops
= &eeprom_ops_82599
,
2161 .phy_ops
= &phy_ops_82599
,
2162 .mbx_ops
= &mbx_ops_generic
,