1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2016 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/pci.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
32 #include <linux/netdevice.h>
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
38 static s32
ixgbe_acquire_eeprom(struct ixgbe_hw
*hw
);
39 static s32
ixgbe_get_eeprom_semaphore(struct ixgbe_hw
*hw
);
40 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw
*hw
);
41 static s32
ixgbe_ready_eeprom(struct ixgbe_hw
*hw
);
42 static void ixgbe_standby_eeprom(struct ixgbe_hw
*hw
);
43 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw
*hw
, u16 data
,
45 static u16
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw
*hw
, u16 count
);
46 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
);
47 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
);
48 static void ixgbe_release_eeprom(struct ixgbe_hw
*hw
);
50 static s32
ixgbe_mta_vector(struct ixgbe_hw
*hw
, u8
*mc_addr
);
51 static s32
ixgbe_poll_eerd_eewr_done(struct ixgbe_hw
*hw
, u32 ee_reg
);
52 static s32
ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw
*hw
, u16 offset
,
53 u16 words
, u16
*data
);
54 static s32
ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw
*hw
, u16 offset
,
55 u16 words
, u16
*data
);
56 static s32
ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw
*hw
,
58 static s32
ixgbe_disable_pcie_master(struct ixgbe_hw
*hw
);
60 /* Base table for registers values that change by MAC */
61 const u32 ixgbe_mvals_8259X
[IXGBE_MVALS_IDX_LIMIT
] = {
62 IXGBE_MVALS_INIT(8259X
)
66 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
68 * @hw: pointer to hardware structure
70 * There are several phys that do not support autoneg flow control. This
71 * function check the device id to see if the associated phy supports
72 * autoneg flow control.
74 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw
*hw
)
76 bool supported
= false;
77 ixgbe_link_speed speed
;
80 switch (hw
->phy
.media_type
) {
81 case ixgbe_media_type_fiber
:
82 hw
->mac
.ops
.check_link(hw
, &speed
, &link_up
, false);
83 /* if link is down, assume supported */
85 supported
= speed
== IXGBE_LINK_SPEED_1GB_FULL
?
90 case ixgbe_media_type_backplane
:
93 case ixgbe_media_type_copper
:
94 /* only some copper devices support flow control autoneg */
95 switch (hw
->device_id
) {
96 case IXGBE_DEV_ID_82599_T3_LOM
:
97 case IXGBE_DEV_ID_X540T
:
98 case IXGBE_DEV_ID_X540T1
:
99 case IXGBE_DEV_ID_X550T
:
100 case IXGBE_DEV_ID_X550T1
:
101 case IXGBE_DEV_ID_X550EM_X_10G_T
:
115 * ixgbe_setup_fc_generic - Set up flow control
116 * @hw: pointer to hardware structure
118 * Called at init time to set up flow control.
120 s32
ixgbe_setup_fc_generic(struct ixgbe_hw
*hw
)
123 u32 reg
= 0, reg_bp
= 0;
128 * Validate the requested mode. Strict IEEE mode does not allow
129 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
131 if (hw
->fc
.strict_ieee
&& hw
->fc
.requested_mode
== ixgbe_fc_rx_pause
) {
132 hw_dbg(hw
, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
133 return IXGBE_ERR_INVALID_LINK_SETTINGS
;
137 * 10gig parts do not have a word in the EEPROM to determine the
138 * default flow control setting, so we explicitly set it to full.
140 if (hw
->fc
.requested_mode
== ixgbe_fc_default
)
141 hw
->fc
.requested_mode
= ixgbe_fc_full
;
144 * Set up the 1G and 10G flow control advertisement registers so the
145 * HW will be able to do fc autoneg once the cable is plugged in. If
146 * we link at 10G, the 1G advertisement is harmless and vice versa.
148 switch (hw
->phy
.media_type
) {
149 case ixgbe_media_type_backplane
:
150 /* some MAC's need RMW protection on AUTOC */
151 ret_val
= hw
->mac
.ops
.prot_autoc_read(hw
, &locked
, ®_bp
);
155 /* only backplane uses autoc so fall though */
156 case ixgbe_media_type_fiber
:
157 reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANA
);
160 case ixgbe_media_type_copper
:
161 hw
->phy
.ops
.read_reg(hw
, MDIO_AN_ADVERTISE
,
162 MDIO_MMD_AN
, ®_cu
);
169 * The possible values of fc.requested_mode are:
170 * 0: Flow control is completely disabled
171 * 1: Rx flow control is enabled (we can receive pause frames,
172 * but not send pause frames).
173 * 2: Tx flow control is enabled (we can send pause frames but
174 * we do not support receiving pause frames).
175 * 3: Both Rx and Tx flow control (symmetric) are enabled.
178 switch (hw
->fc
.requested_mode
) {
180 /* Flow control completely disabled by software override. */
181 reg
&= ~(IXGBE_PCS1GANA_SYM_PAUSE
| IXGBE_PCS1GANA_ASM_PAUSE
);
182 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
)
183 reg_bp
&= ~(IXGBE_AUTOC_SYM_PAUSE
|
184 IXGBE_AUTOC_ASM_PAUSE
);
185 else if (hw
->phy
.media_type
== ixgbe_media_type_copper
)
186 reg_cu
&= ~(IXGBE_TAF_SYM_PAUSE
| IXGBE_TAF_ASM_PAUSE
);
188 case ixgbe_fc_tx_pause
:
190 * Tx Flow control is enabled, and Rx Flow control is
191 * disabled by software override.
193 reg
|= IXGBE_PCS1GANA_ASM_PAUSE
;
194 reg
&= ~IXGBE_PCS1GANA_SYM_PAUSE
;
195 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
) {
196 reg_bp
|= IXGBE_AUTOC_ASM_PAUSE
;
197 reg_bp
&= ~IXGBE_AUTOC_SYM_PAUSE
;
198 } else if (hw
->phy
.media_type
== ixgbe_media_type_copper
) {
199 reg_cu
|= IXGBE_TAF_ASM_PAUSE
;
200 reg_cu
&= ~IXGBE_TAF_SYM_PAUSE
;
203 case ixgbe_fc_rx_pause
:
205 * Rx Flow control is enabled and Tx Flow control is
206 * disabled by software override. Since there really
207 * isn't a way to advertise that we are capable of RX
208 * Pause ONLY, we will advertise that we support both
209 * symmetric and asymmetric Rx PAUSE, as such we fall
210 * through to the fc_full statement. Later, we will
211 * disable the adapter's ability to send PAUSE frames.
214 /* Flow control (both Rx and Tx) is enabled by SW override. */
215 reg
|= IXGBE_PCS1GANA_SYM_PAUSE
| IXGBE_PCS1GANA_ASM_PAUSE
;
216 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
)
217 reg_bp
|= IXGBE_AUTOC_SYM_PAUSE
|
218 IXGBE_AUTOC_ASM_PAUSE
;
219 else if (hw
->phy
.media_type
== ixgbe_media_type_copper
)
220 reg_cu
|= IXGBE_TAF_SYM_PAUSE
| IXGBE_TAF_ASM_PAUSE
;
223 hw_dbg(hw
, "Flow control param set incorrectly\n");
224 return IXGBE_ERR_CONFIG
;
227 if (hw
->mac
.type
!= ixgbe_mac_X540
) {
229 * Enable auto-negotiation between the MAC & PHY;
230 * the MAC will advertise clause 37 flow control.
232 IXGBE_WRITE_REG(hw
, IXGBE_PCS1GANA
, reg
);
233 reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GLCTL
);
235 /* Disable AN timeout */
236 if (hw
->fc
.strict_ieee
)
237 reg
&= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN
;
239 IXGBE_WRITE_REG(hw
, IXGBE_PCS1GLCTL
, reg
);
240 hw_dbg(hw
, "Set up FC; PCS1GLCTL = 0x%08X\n", reg
);
244 * AUTOC restart handles negotiation of 1G and 10G on backplane
245 * and copper. There is no need to set the PCS1GCTL register.
248 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
) {
249 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
250 * LESM is on, likewise reset_pipeline requries the lock as
251 * it also writes AUTOC.
253 ret_val
= hw
->mac
.ops
.prot_autoc_write(hw
, reg_bp
, locked
);
257 } else if ((hw
->phy
.media_type
== ixgbe_media_type_copper
) &&
258 ixgbe_device_supports_autoneg_fc(hw
)) {
259 hw
->phy
.ops
.write_reg(hw
, MDIO_AN_ADVERTISE
,
260 MDIO_MMD_AN
, reg_cu
);
263 hw_dbg(hw
, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg
);
268 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
269 * @hw: pointer to hardware structure
271 * Starts the hardware by filling the bus info structure and media type, clears
272 * all on chip counters, initializes receive address registers, multicast
273 * table, VLAN filter table, calls routine to set up link and flow control
274 * settings, and leaves transmit and receive units disabled and uninitialized
276 s32
ixgbe_start_hw_generic(struct ixgbe_hw
*hw
)
281 /* Set the media type */
282 hw
->phy
.media_type
= hw
->mac
.ops
.get_media_type(hw
);
284 /* Identify the PHY */
285 hw
->phy
.ops
.identify(hw
);
287 /* Clear the VLAN filter table */
288 hw
->mac
.ops
.clear_vfta(hw
);
290 /* Clear statistics registers */
291 hw
->mac
.ops
.clear_hw_cntrs(hw
);
293 /* Set No Snoop Disable */
294 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
295 ctrl_ext
|= IXGBE_CTRL_EXT_NS_DIS
;
296 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
297 IXGBE_WRITE_FLUSH(hw
);
299 /* Setup flow control */
300 ret_val
= hw
->mac
.ops
.setup_fc(hw
);
304 /* Clear adapter stopped flag */
305 hw
->adapter_stopped
= false;
311 * ixgbe_start_hw_gen2 - Init sequence for common device family
312 * @hw: pointer to hw structure
314 * Performs the init sequence common to the second generation
316 * Devices in the second generation:
320 s32
ixgbe_start_hw_gen2(struct ixgbe_hw
*hw
)
324 /* Clear the rate limiters */
325 for (i
= 0; i
< hw
->mac
.max_tx_queues
; i
++) {
326 IXGBE_WRITE_REG(hw
, IXGBE_RTTDQSEL
, i
);
327 IXGBE_WRITE_REG(hw
, IXGBE_RTTBCNRC
, 0);
329 IXGBE_WRITE_FLUSH(hw
);
332 /* Disable relaxed ordering */
333 for (i
= 0; i
< hw
->mac
.max_tx_queues
; i
++) {
336 regval
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(i
));
337 regval
&= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN
;
338 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(i
), regval
);
341 for (i
= 0; i
< hw
->mac
.max_rx_queues
; i
++) {
344 regval
= IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(i
));
345 regval
&= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN
|
346 IXGBE_DCA_RXCTRL_HEAD_WRO_EN
);
347 IXGBE_WRITE_REG(hw
, IXGBE_DCA_RXCTRL(i
), regval
);
354 * ixgbe_init_hw_generic - Generic hardware initialization
355 * @hw: pointer to hardware structure
357 * Initialize the hardware by resetting the hardware, filling the bus info
358 * structure and media type, clears all on chip counters, initializes receive
359 * address registers, multicast table, VLAN filter table, calls routine to set
360 * up link and flow control settings, and leaves transmit and receive units
361 * disabled and uninitialized
363 s32
ixgbe_init_hw_generic(struct ixgbe_hw
*hw
)
367 /* Reset the hardware */
368 status
= hw
->mac
.ops
.reset_hw(hw
);
372 status
= hw
->mac
.ops
.start_hw(hw
);
379 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
380 * @hw: pointer to hardware structure
382 * Clears all hardware statistics counters by reading them from the hardware
383 * Statistics counters are clear on read.
385 s32
ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw
*hw
)
389 IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
390 IXGBE_READ_REG(hw
, IXGBE_ILLERRC
);
391 IXGBE_READ_REG(hw
, IXGBE_ERRBC
);
392 IXGBE_READ_REG(hw
, IXGBE_MSPDC
);
393 for (i
= 0; i
< 8; i
++)
394 IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
396 IXGBE_READ_REG(hw
, IXGBE_MLFC
);
397 IXGBE_READ_REG(hw
, IXGBE_MRFC
);
398 IXGBE_READ_REG(hw
, IXGBE_RLEC
);
399 IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
400 IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
401 if (hw
->mac
.type
>= ixgbe_mac_82599EB
) {
402 IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
403 IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
405 IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
406 IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
409 for (i
= 0; i
< 8; i
++) {
410 IXGBE_READ_REG(hw
, IXGBE_PXONTXC(i
));
411 IXGBE_READ_REG(hw
, IXGBE_PXOFFTXC(i
));
412 if (hw
->mac
.type
>= ixgbe_mac_82599EB
) {
413 IXGBE_READ_REG(hw
, IXGBE_PXONRXCNT(i
));
414 IXGBE_READ_REG(hw
, IXGBE_PXOFFRXCNT(i
));
416 IXGBE_READ_REG(hw
, IXGBE_PXONRXC(i
));
417 IXGBE_READ_REG(hw
, IXGBE_PXOFFRXC(i
));
420 if (hw
->mac
.type
>= ixgbe_mac_82599EB
)
421 for (i
= 0; i
< 8; i
++)
422 IXGBE_READ_REG(hw
, IXGBE_PXON2OFFCNT(i
));
423 IXGBE_READ_REG(hw
, IXGBE_PRC64
);
424 IXGBE_READ_REG(hw
, IXGBE_PRC127
);
425 IXGBE_READ_REG(hw
, IXGBE_PRC255
);
426 IXGBE_READ_REG(hw
, IXGBE_PRC511
);
427 IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
428 IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
429 IXGBE_READ_REG(hw
, IXGBE_GPRC
);
430 IXGBE_READ_REG(hw
, IXGBE_BPRC
);
431 IXGBE_READ_REG(hw
, IXGBE_MPRC
);
432 IXGBE_READ_REG(hw
, IXGBE_GPTC
);
433 IXGBE_READ_REG(hw
, IXGBE_GORCL
);
434 IXGBE_READ_REG(hw
, IXGBE_GORCH
);
435 IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
436 IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
437 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
438 for (i
= 0; i
< 8; i
++)
439 IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
440 IXGBE_READ_REG(hw
, IXGBE_RUC
);
441 IXGBE_READ_REG(hw
, IXGBE_RFC
);
442 IXGBE_READ_REG(hw
, IXGBE_ROC
);
443 IXGBE_READ_REG(hw
, IXGBE_RJC
);
444 IXGBE_READ_REG(hw
, IXGBE_MNGPRC
);
445 IXGBE_READ_REG(hw
, IXGBE_MNGPDC
);
446 IXGBE_READ_REG(hw
, IXGBE_MNGPTC
);
447 IXGBE_READ_REG(hw
, IXGBE_TORL
);
448 IXGBE_READ_REG(hw
, IXGBE_TORH
);
449 IXGBE_READ_REG(hw
, IXGBE_TPR
);
450 IXGBE_READ_REG(hw
, IXGBE_TPT
);
451 IXGBE_READ_REG(hw
, IXGBE_PTC64
);
452 IXGBE_READ_REG(hw
, IXGBE_PTC127
);
453 IXGBE_READ_REG(hw
, IXGBE_PTC255
);
454 IXGBE_READ_REG(hw
, IXGBE_PTC511
);
455 IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
456 IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
457 IXGBE_READ_REG(hw
, IXGBE_MPTC
);
458 IXGBE_READ_REG(hw
, IXGBE_BPTC
);
459 for (i
= 0; i
< 16; i
++) {
460 IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
461 IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
462 if (hw
->mac
.type
>= ixgbe_mac_82599EB
) {
463 IXGBE_READ_REG(hw
, IXGBE_QBRC_L(i
));
464 IXGBE_READ_REG(hw
, IXGBE_QBRC_H(i
));
465 IXGBE_READ_REG(hw
, IXGBE_QBTC_L(i
));
466 IXGBE_READ_REG(hw
, IXGBE_QBTC_H(i
));
467 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
469 IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
470 IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
474 if (hw
->mac
.type
== ixgbe_mac_X550
|| hw
->mac
.type
== ixgbe_mac_X540
) {
476 hw
->phy
.ops
.identify(hw
);
477 hw
->phy
.ops
.read_reg(hw
, IXGBE_PCRC8ECL
, MDIO_MMD_PCS
, &i
);
478 hw
->phy
.ops
.read_reg(hw
, IXGBE_PCRC8ECH
, MDIO_MMD_PCS
, &i
);
479 hw
->phy
.ops
.read_reg(hw
, IXGBE_LDPCECL
, MDIO_MMD_PCS
, &i
);
480 hw
->phy
.ops
.read_reg(hw
, IXGBE_LDPCECH
, MDIO_MMD_PCS
, &i
);
487 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
488 * @hw: pointer to hardware structure
489 * @pba_num: stores the part number string from the EEPROM
490 * @pba_num_size: part number string buffer length
492 * Reads the part number string from the EEPROM.
494 s32
ixgbe_read_pba_string_generic(struct ixgbe_hw
*hw
, u8
*pba_num
,
503 if (pba_num
== NULL
) {
504 hw_dbg(hw
, "PBA string buffer was null\n");
505 return IXGBE_ERR_INVALID_ARGUMENT
;
508 ret_val
= hw
->eeprom
.ops
.read(hw
, IXGBE_PBANUM0_PTR
, &data
);
510 hw_dbg(hw
, "NVM Read Error\n");
514 ret_val
= hw
->eeprom
.ops
.read(hw
, IXGBE_PBANUM1_PTR
, &pba_ptr
);
516 hw_dbg(hw
, "NVM Read Error\n");
521 * if data is not ptr guard the PBA must be in legacy format which
522 * means pba_ptr is actually our second data word for the PBA number
523 * and we can decode it into an ascii string
525 if (data
!= IXGBE_PBANUM_PTR_GUARD
) {
526 hw_dbg(hw
, "NVM PBA number is not stored as string\n");
528 /* we will need 11 characters to store the PBA */
529 if (pba_num_size
< 11) {
530 hw_dbg(hw
, "PBA string buffer too small\n");
531 return IXGBE_ERR_NO_SPACE
;
534 /* extract hex string from data and pba_ptr */
535 pba_num
[0] = (data
>> 12) & 0xF;
536 pba_num
[1] = (data
>> 8) & 0xF;
537 pba_num
[2] = (data
>> 4) & 0xF;
538 pba_num
[3] = data
& 0xF;
539 pba_num
[4] = (pba_ptr
>> 12) & 0xF;
540 pba_num
[5] = (pba_ptr
>> 8) & 0xF;
543 pba_num
[8] = (pba_ptr
>> 4) & 0xF;
544 pba_num
[9] = pba_ptr
& 0xF;
546 /* put a null character on the end of our string */
549 /* switch all the data but the '-' to hex char */
550 for (offset
= 0; offset
< 10; offset
++) {
551 if (pba_num
[offset
] < 0xA)
552 pba_num
[offset
] += '0';
553 else if (pba_num
[offset
] < 0x10)
554 pba_num
[offset
] += 'A' - 0xA;
560 ret_val
= hw
->eeprom
.ops
.read(hw
, pba_ptr
, &length
);
562 hw_dbg(hw
, "NVM Read Error\n");
566 if (length
== 0xFFFF || length
== 0) {
567 hw_dbg(hw
, "NVM PBA number section invalid length\n");
568 return IXGBE_ERR_PBA_SECTION
;
571 /* check if pba_num buffer is big enough */
572 if (pba_num_size
< (((u32
)length
* 2) - 1)) {
573 hw_dbg(hw
, "PBA string buffer too small\n");
574 return IXGBE_ERR_NO_SPACE
;
577 /* trim pba length from start of string */
581 for (offset
= 0; offset
< length
; offset
++) {
582 ret_val
= hw
->eeprom
.ops
.read(hw
, pba_ptr
+ offset
, &data
);
584 hw_dbg(hw
, "NVM Read Error\n");
587 pba_num
[offset
* 2] = (u8
)(data
>> 8);
588 pba_num
[(offset
* 2) + 1] = (u8
)(data
& 0xFF);
590 pba_num
[offset
* 2] = '\0';
596 * ixgbe_get_mac_addr_generic - Generic get MAC address
597 * @hw: pointer to hardware structure
598 * @mac_addr: Adapter MAC address
600 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
601 * A reset of the adapter must be performed prior to calling this function
602 * in order for the MAC address to have been loaded from the EEPROM into RAR0
604 s32
ixgbe_get_mac_addr_generic(struct ixgbe_hw
*hw
, u8
*mac_addr
)
610 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(0));
611 rar_low
= IXGBE_READ_REG(hw
, IXGBE_RAL(0));
613 for (i
= 0; i
< 4; i
++)
614 mac_addr
[i
] = (u8
)(rar_low
>> (i
*8));
616 for (i
= 0; i
< 2; i
++)
617 mac_addr
[i
+4] = (u8
)(rar_high
>> (i
*8));
622 enum ixgbe_bus_width
ixgbe_convert_bus_width(u16 link_status
)
624 switch (link_status
& IXGBE_PCI_LINK_WIDTH
) {
625 case IXGBE_PCI_LINK_WIDTH_1
:
626 return ixgbe_bus_width_pcie_x1
;
627 case IXGBE_PCI_LINK_WIDTH_2
:
628 return ixgbe_bus_width_pcie_x2
;
629 case IXGBE_PCI_LINK_WIDTH_4
:
630 return ixgbe_bus_width_pcie_x4
;
631 case IXGBE_PCI_LINK_WIDTH_8
:
632 return ixgbe_bus_width_pcie_x8
;
634 return ixgbe_bus_width_unknown
;
638 enum ixgbe_bus_speed
ixgbe_convert_bus_speed(u16 link_status
)
640 switch (link_status
& IXGBE_PCI_LINK_SPEED
) {
641 case IXGBE_PCI_LINK_SPEED_2500
:
642 return ixgbe_bus_speed_2500
;
643 case IXGBE_PCI_LINK_SPEED_5000
:
644 return ixgbe_bus_speed_5000
;
645 case IXGBE_PCI_LINK_SPEED_8000
:
646 return ixgbe_bus_speed_8000
;
648 return ixgbe_bus_speed_unknown
;
653 * ixgbe_get_bus_info_generic - Generic set PCI bus info
654 * @hw: pointer to hardware structure
656 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
658 s32
ixgbe_get_bus_info_generic(struct ixgbe_hw
*hw
)
662 hw
->bus
.type
= ixgbe_bus_type_pci_express
;
664 /* Get the negotiated link width and speed from PCI config space */
665 link_status
= ixgbe_read_pci_cfg_word(hw
, IXGBE_PCI_LINK_STATUS
);
667 hw
->bus
.width
= ixgbe_convert_bus_width(link_status
);
668 hw
->bus
.speed
= ixgbe_convert_bus_speed(link_status
);
670 hw
->mac
.ops
.set_lan_id(hw
);
676 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
677 * @hw: pointer to the HW structure
679 * Determines the LAN function id by reading memory-mapped registers
680 * and swaps the port value if requested.
682 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw
*hw
)
684 struct ixgbe_bus_info
*bus
= &hw
->bus
;
688 reg
= IXGBE_READ_REG(hw
, IXGBE_STATUS
);
689 bus
->func
= (reg
& IXGBE_STATUS_LAN_ID
) >> IXGBE_STATUS_LAN_ID_SHIFT
;
690 bus
->lan_id
= bus
->func
;
692 /* check for a port swap */
693 reg
= IXGBE_READ_REG(hw
, IXGBE_FACTPS(hw
));
694 if (reg
& IXGBE_FACTPS_LFS
)
697 /* Get MAC instance from EEPROM for configuring CS4227 */
698 if (hw
->device_id
== IXGBE_DEV_ID_X550EM_A_SFP
) {
699 hw
->eeprom
.ops
.read(hw
, IXGBE_EEPROM_CTRL_4
, &ee_ctrl_4
);
700 bus
->instance_id
= (ee_ctrl_4
& IXGBE_EE_CTRL_4_INST_ID
) >>
701 IXGBE_EE_CTRL_4_INST_ID_SHIFT
;
706 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
707 * @hw: pointer to hardware structure
709 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
710 * disables transmit and receive units. The adapter_stopped flag is used by
711 * the shared code and drivers to determine if the adapter is in a stopped
712 * state and should not touch the hardware.
714 s32
ixgbe_stop_adapter_generic(struct ixgbe_hw
*hw
)
720 * Set the adapter_stopped flag so other driver functions stop touching
723 hw
->adapter_stopped
= true;
725 /* Disable the receive unit */
726 hw
->mac
.ops
.disable_rx(hw
);
728 /* Clear interrupt mask to stop interrupts from being generated */
729 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
731 /* Clear any pending interrupts, flush previous writes */
732 IXGBE_READ_REG(hw
, IXGBE_EICR
);
734 /* Disable the transmit unit. Each queue must be disabled. */
735 for (i
= 0; i
< hw
->mac
.max_tx_queues
; i
++)
736 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(i
), IXGBE_TXDCTL_SWFLSH
);
738 /* Disable the receive unit by stopping each queue */
739 for (i
= 0; i
< hw
->mac
.max_rx_queues
; i
++) {
740 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
741 reg_val
&= ~IXGBE_RXDCTL_ENABLE
;
742 reg_val
|= IXGBE_RXDCTL_SWFLSH
;
743 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(i
), reg_val
);
746 /* flush all queues disables */
747 IXGBE_WRITE_FLUSH(hw
);
748 usleep_range(1000, 2000);
751 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
752 * access and verify no pending requests
754 return ixgbe_disable_pcie_master(hw
);
758 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
759 * @hw: pointer to hardware structure
760 * @index: led number to turn on
762 s32
ixgbe_led_on_generic(struct ixgbe_hw
*hw
, u32 index
)
764 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
767 return IXGBE_ERR_PARAM
;
769 /* To turn on the LED, set mode to ON. */
770 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
771 led_reg
|= IXGBE_LED_ON
<< IXGBE_LED_MODE_SHIFT(index
);
772 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
773 IXGBE_WRITE_FLUSH(hw
);
779 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
780 * @hw: pointer to hardware structure
781 * @index: led number to turn off
783 s32
ixgbe_led_off_generic(struct ixgbe_hw
*hw
, u32 index
)
785 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
788 return IXGBE_ERR_PARAM
;
790 /* To turn off the LED, set mode to OFF. */
791 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
792 led_reg
|= IXGBE_LED_OFF
<< IXGBE_LED_MODE_SHIFT(index
);
793 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
794 IXGBE_WRITE_FLUSH(hw
);
800 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
801 * @hw: pointer to hardware structure
803 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
804 * ixgbe_hw struct in order to set up EEPROM access.
806 s32
ixgbe_init_eeprom_params_generic(struct ixgbe_hw
*hw
)
808 struct ixgbe_eeprom_info
*eeprom
= &hw
->eeprom
;
812 if (eeprom
->type
== ixgbe_eeprom_uninitialized
) {
813 eeprom
->type
= ixgbe_eeprom_none
;
814 /* Set default semaphore delay to 10ms which is a well
816 eeprom
->semaphore_delay
= 10;
817 /* Clear EEPROM page size, it will be initialized as needed */
818 eeprom
->word_page_size
= 0;
821 * Check for EEPROM present first.
822 * If not present leave as none
824 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC(hw
));
825 if (eec
& IXGBE_EEC_PRES
) {
826 eeprom
->type
= ixgbe_eeprom_spi
;
829 * SPI EEPROM is assumed here. This code would need to
830 * change if a future EEPROM is not SPI.
832 eeprom_size
= (u16
)((eec
& IXGBE_EEC_SIZE
) >>
833 IXGBE_EEC_SIZE_SHIFT
);
834 eeprom
->word_size
= BIT(eeprom_size
+
835 IXGBE_EEPROM_WORD_SIZE_SHIFT
);
838 if (eec
& IXGBE_EEC_ADDR_SIZE
)
839 eeprom
->address_bits
= 16;
841 eeprom
->address_bits
= 8;
842 hw_dbg(hw
, "Eeprom params: type = %d, size = %d, address bits: %d\n",
843 eeprom
->type
, eeprom
->word_size
, eeprom
->address_bits
);
850 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
851 * @hw: pointer to hardware structure
852 * @offset: offset within the EEPROM to write
853 * @words: number of words
854 * @data: 16 bit word(s) to write to EEPROM
856 * Reads 16 bit word(s) from EEPROM through bit-bang method
858 s32
ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw
*hw
, u16 offset
,
859 u16 words
, u16
*data
)
864 hw
->eeprom
.ops
.init_params(hw
);
867 return IXGBE_ERR_INVALID_ARGUMENT
;
869 if (offset
+ words
> hw
->eeprom
.word_size
)
870 return IXGBE_ERR_EEPROM
;
873 * The EEPROM page size cannot be queried from the chip. We do lazy
874 * initialization. It is worth to do that when we write large buffer.
876 if ((hw
->eeprom
.word_page_size
== 0) &&
877 (words
> IXGBE_EEPROM_PAGE_SIZE_MAX
))
878 ixgbe_detect_eeprom_page_size_generic(hw
, offset
);
881 * We cannot hold synchronization semaphores for too long
882 * to avoid other entity starvation. However it is more efficient
883 * to read in bursts than synchronizing access for each word.
885 for (i
= 0; i
< words
; i
+= IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
) {
886 count
= (words
- i
) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
> 0 ?
887 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
: (words
- i
);
888 status
= ixgbe_write_eeprom_buffer_bit_bang(hw
, offset
+ i
,
899 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
900 * @hw: pointer to hardware structure
901 * @offset: offset within the EEPROM to be written to
902 * @words: number of word(s)
903 * @data: 16 bit word(s) to be written to the EEPROM
905 * If ixgbe_eeprom_update_checksum is not called after this function, the
906 * EEPROM will most likely contain an invalid checksum.
908 static s32
ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw
*hw
, u16 offset
,
909 u16 words
, u16
*data
)
915 u8 write_opcode
= IXGBE_EEPROM_WRITE_OPCODE_SPI
;
917 /* Prepare the EEPROM for writing */
918 status
= ixgbe_acquire_eeprom(hw
);
922 if (ixgbe_ready_eeprom(hw
) != 0) {
923 ixgbe_release_eeprom(hw
);
924 return IXGBE_ERR_EEPROM
;
927 for (i
= 0; i
< words
; i
++) {
928 ixgbe_standby_eeprom(hw
);
930 /* Send the WRITE ENABLE command (8 bit opcode) */
931 ixgbe_shift_out_eeprom_bits(hw
,
932 IXGBE_EEPROM_WREN_OPCODE_SPI
,
933 IXGBE_EEPROM_OPCODE_BITS
);
935 ixgbe_standby_eeprom(hw
);
937 /* Some SPI eeproms use the 8th address bit embedded
940 if ((hw
->eeprom
.address_bits
== 8) &&
941 ((offset
+ i
) >= 128))
942 write_opcode
|= IXGBE_EEPROM_A8_OPCODE_SPI
;
944 /* Send the Write command (8-bit opcode + addr) */
945 ixgbe_shift_out_eeprom_bits(hw
, write_opcode
,
946 IXGBE_EEPROM_OPCODE_BITS
);
947 ixgbe_shift_out_eeprom_bits(hw
, (u16
)((offset
+ i
) * 2),
948 hw
->eeprom
.address_bits
);
950 page_size
= hw
->eeprom
.word_page_size
;
952 /* Send the data in burst via SPI */
955 word
= (word
>> 8) | (word
<< 8);
956 ixgbe_shift_out_eeprom_bits(hw
, word
, 16);
961 /* do not wrap around page */
962 if (((offset
+ i
) & (page_size
- 1)) ==
965 } while (++i
< words
);
967 ixgbe_standby_eeprom(hw
);
968 usleep_range(10000, 20000);
970 /* Done with writing - release the EEPROM */
971 ixgbe_release_eeprom(hw
);
977 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
978 * @hw: pointer to hardware structure
979 * @offset: offset within the EEPROM to be written to
980 * @data: 16 bit word to be written to the EEPROM
982 * If ixgbe_eeprom_update_checksum is not called after this function, the
983 * EEPROM will most likely contain an invalid checksum.
985 s32
ixgbe_write_eeprom_generic(struct ixgbe_hw
*hw
, u16 offset
, u16 data
)
987 hw
->eeprom
.ops
.init_params(hw
);
989 if (offset
>= hw
->eeprom
.word_size
)
990 return IXGBE_ERR_EEPROM
;
992 return ixgbe_write_eeprom_buffer_bit_bang(hw
, offset
, 1, &data
);
996 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
997 * @hw: pointer to hardware structure
998 * @offset: offset within the EEPROM to be read
999 * @words: number of word(s)
1000 * @data: read 16 bit words(s) from EEPROM
1002 * Reads 16 bit word(s) from EEPROM through bit-bang method
1004 s32
ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw
*hw
, u16 offset
,
1005 u16 words
, u16
*data
)
1010 hw
->eeprom
.ops
.init_params(hw
);
1013 return IXGBE_ERR_INVALID_ARGUMENT
;
1015 if (offset
+ words
> hw
->eeprom
.word_size
)
1016 return IXGBE_ERR_EEPROM
;
1019 * We cannot hold synchronization semaphores for too long
1020 * to avoid other entity starvation. However it is more efficient
1021 * to read in bursts than synchronizing access for each word.
1023 for (i
= 0; i
< words
; i
+= IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
) {
1024 count
= (words
- i
) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
> 0 ?
1025 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
: (words
- i
);
1027 status
= ixgbe_read_eeprom_buffer_bit_bang(hw
, offset
+ i
,
1038 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1039 * @hw: pointer to hardware structure
1040 * @offset: offset within the EEPROM to be read
1041 * @words: number of word(s)
1042 * @data: read 16 bit word(s) from EEPROM
1044 * Reads 16 bit word(s) from EEPROM through bit-bang method
1046 static s32
ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw
*hw
, u16 offset
,
1047 u16 words
, u16
*data
)
1051 u8 read_opcode
= IXGBE_EEPROM_READ_OPCODE_SPI
;
1054 /* Prepare the EEPROM for reading */
1055 status
= ixgbe_acquire_eeprom(hw
);
1059 if (ixgbe_ready_eeprom(hw
) != 0) {
1060 ixgbe_release_eeprom(hw
);
1061 return IXGBE_ERR_EEPROM
;
1064 for (i
= 0; i
< words
; i
++) {
1065 ixgbe_standby_eeprom(hw
);
1066 /* Some SPI eeproms use the 8th address bit embedded
1069 if ((hw
->eeprom
.address_bits
== 8) &&
1070 ((offset
+ i
) >= 128))
1071 read_opcode
|= IXGBE_EEPROM_A8_OPCODE_SPI
;
1073 /* Send the READ command (opcode + addr) */
1074 ixgbe_shift_out_eeprom_bits(hw
, read_opcode
,
1075 IXGBE_EEPROM_OPCODE_BITS
);
1076 ixgbe_shift_out_eeprom_bits(hw
, (u16
)((offset
+ i
) * 2),
1077 hw
->eeprom
.address_bits
);
1079 /* Read the data. */
1080 word_in
= ixgbe_shift_in_eeprom_bits(hw
, 16);
1081 data
[i
] = (word_in
>> 8) | (word_in
<< 8);
1084 /* End this read operation */
1085 ixgbe_release_eeprom(hw
);
1091 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1092 * @hw: pointer to hardware structure
1093 * @offset: offset within the EEPROM to be read
1094 * @data: read 16 bit value from EEPROM
1096 * Reads 16 bit value from EEPROM through bit-bang method
1098 s32
ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw
*hw
, u16 offset
,
1101 hw
->eeprom
.ops
.init_params(hw
);
1103 if (offset
>= hw
->eeprom
.word_size
)
1104 return IXGBE_ERR_EEPROM
;
1106 return ixgbe_read_eeprom_buffer_bit_bang(hw
, offset
, 1, data
);
1110 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1111 * @hw: pointer to hardware structure
1112 * @offset: offset of word in the EEPROM to read
1113 * @words: number of word(s)
1114 * @data: 16 bit word(s) from the EEPROM
1116 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1118 s32
ixgbe_read_eerd_buffer_generic(struct ixgbe_hw
*hw
, u16 offset
,
1119 u16 words
, u16
*data
)
1125 hw
->eeprom
.ops
.init_params(hw
);
1128 return IXGBE_ERR_INVALID_ARGUMENT
;
1130 if (offset
>= hw
->eeprom
.word_size
)
1131 return IXGBE_ERR_EEPROM
;
1133 for (i
= 0; i
< words
; i
++) {
1134 eerd
= ((offset
+ i
) << IXGBE_EEPROM_RW_ADDR_SHIFT
) |
1135 IXGBE_EEPROM_RW_REG_START
;
1137 IXGBE_WRITE_REG(hw
, IXGBE_EERD
, eerd
);
1138 status
= ixgbe_poll_eerd_eewr_done(hw
, IXGBE_NVM_POLL_READ
);
1141 data
[i
] = (IXGBE_READ_REG(hw
, IXGBE_EERD
) >>
1142 IXGBE_EEPROM_RW_REG_DATA
);
1144 hw_dbg(hw
, "Eeprom read timed out\n");
1153 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1154 * @hw: pointer to hardware structure
1155 * @offset: offset within the EEPROM to be used as a scratch pad
1157 * Discover EEPROM page size by writing marching data at given offset.
1158 * This function is called only when we are writing a new large buffer
1159 * at given offset so the data would be overwritten anyway.
1161 static s32
ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw
*hw
,
1164 u16 data
[IXGBE_EEPROM_PAGE_SIZE_MAX
];
1168 for (i
= 0; i
< IXGBE_EEPROM_PAGE_SIZE_MAX
; i
++)
1171 hw
->eeprom
.word_page_size
= IXGBE_EEPROM_PAGE_SIZE_MAX
;
1172 status
= ixgbe_write_eeprom_buffer_bit_bang(hw
, offset
,
1173 IXGBE_EEPROM_PAGE_SIZE_MAX
, data
);
1174 hw
->eeprom
.word_page_size
= 0;
1178 status
= ixgbe_read_eeprom_buffer_bit_bang(hw
, offset
, 1, data
);
1183 * When writing in burst more than the actual page size
1184 * EEPROM address wraps around current page.
1186 hw
->eeprom
.word_page_size
= IXGBE_EEPROM_PAGE_SIZE_MAX
- data
[0];
1188 hw_dbg(hw
, "Detected EEPROM page size = %d words.\n",
1189 hw
->eeprom
.word_page_size
);
1194 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1195 * @hw: pointer to hardware structure
1196 * @offset: offset of word in the EEPROM to read
1197 * @data: word read from the EEPROM
1199 * Reads a 16 bit word from the EEPROM using the EERD register.
1201 s32
ixgbe_read_eerd_generic(struct ixgbe_hw
*hw
, u16 offset
, u16
*data
)
1203 return ixgbe_read_eerd_buffer_generic(hw
, offset
, 1, data
);
1207 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1208 * @hw: pointer to hardware structure
1209 * @offset: offset of word in the EEPROM to write
1210 * @words: number of words
1211 * @data: word(s) write to the EEPROM
1213 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1215 s32
ixgbe_write_eewr_buffer_generic(struct ixgbe_hw
*hw
, u16 offset
,
1216 u16 words
, u16
*data
)
1222 hw
->eeprom
.ops
.init_params(hw
);
1225 return IXGBE_ERR_INVALID_ARGUMENT
;
1227 if (offset
>= hw
->eeprom
.word_size
)
1228 return IXGBE_ERR_EEPROM
;
1230 for (i
= 0; i
< words
; i
++) {
1231 eewr
= ((offset
+ i
) << IXGBE_EEPROM_RW_ADDR_SHIFT
) |
1232 (data
[i
] << IXGBE_EEPROM_RW_REG_DATA
) |
1233 IXGBE_EEPROM_RW_REG_START
;
1235 status
= ixgbe_poll_eerd_eewr_done(hw
, IXGBE_NVM_POLL_WRITE
);
1237 hw_dbg(hw
, "Eeprom write EEWR timed out\n");
1241 IXGBE_WRITE_REG(hw
, IXGBE_EEWR
, eewr
);
1243 status
= ixgbe_poll_eerd_eewr_done(hw
, IXGBE_NVM_POLL_WRITE
);
1245 hw_dbg(hw
, "Eeprom write EEWR timed out\n");
1254 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1255 * @hw: pointer to hardware structure
1256 * @offset: offset of word in the EEPROM to write
1257 * @data: word write to the EEPROM
1259 * Write a 16 bit word to the EEPROM using the EEWR register.
1261 s32
ixgbe_write_eewr_generic(struct ixgbe_hw
*hw
, u16 offset
, u16 data
)
1263 return ixgbe_write_eewr_buffer_generic(hw
, offset
, 1, &data
);
1267 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1268 * @hw: pointer to hardware structure
1269 * @ee_reg: EEPROM flag for polling
1271 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1272 * read or write is done respectively.
1274 static s32
ixgbe_poll_eerd_eewr_done(struct ixgbe_hw
*hw
, u32 ee_reg
)
1279 for (i
= 0; i
< IXGBE_EERD_EEWR_ATTEMPTS
; i
++) {
1280 if (ee_reg
== IXGBE_NVM_POLL_READ
)
1281 reg
= IXGBE_READ_REG(hw
, IXGBE_EERD
);
1283 reg
= IXGBE_READ_REG(hw
, IXGBE_EEWR
);
1285 if (reg
& IXGBE_EEPROM_RW_REG_DONE
) {
1290 return IXGBE_ERR_EEPROM
;
1294 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1295 * @hw: pointer to hardware structure
1297 * Prepares EEPROM for access using bit-bang method. This function should
1298 * be called before issuing a command to the EEPROM.
1300 static s32
ixgbe_acquire_eeprom(struct ixgbe_hw
*hw
)
1305 if (hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
) != 0)
1306 return IXGBE_ERR_SWFW_SYNC
;
1308 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC(hw
));
1310 /* Request EEPROM Access */
1311 eec
|= IXGBE_EEC_REQ
;
1312 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), eec
);
1314 for (i
= 0; i
< IXGBE_EEPROM_GRANT_ATTEMPTS
; i
++) {
1315 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC(hw
));
1316 if (eec
& IXGBE_EEC_GNT
)
1321 /* Release if grant not acquired */
1322 if (!(eec
& IXGBE_EEC_GNT
)) {
1323 eec
&= ~IXGBE_EEC_REQ
;
1324 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), eec
);
1325 hw_dbg(hw
, "Could not acquire EEPROM grant\n");
1327 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
1328 return IXGBE_ERR_EEPROM
;
1331 /* Setup EEPROM for Read/Write */
1332 /* Clear CS and SK */
1333 eec
&= ~(IXGBE_EEC_CS
| IXGBE_EEC_SK
);
1334 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), eec
);
1335 IXGBE_WRITE_FLUSH(hw
);
1341 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1342 * @hw: pointer to hardware structure
1344 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1346 static s32
ixgbe_get_eeprom_semaphore(struct ixgbe_hw
*hw
)
1352 /* Get SMBI software semaphore between device drivers first */
1353 for (i
= 0; i
< timeout
; i
++) {
1355 * If the SMBI bit is 0 when we read it, then the bit will be
1356 * set and we have the semaphore
1358 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM(hw
));
1359 if (!(swsm
& IXGBE_SWSM_SMBI
))
1361 usleep_range(50, 100);
1365 hw_dbg(hw
, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n");
1366 /* this release is particularly important because our attempts
1367 * above to get the semaphore may have succeeded, and if there
1368 * was a timeout, we should unconditionally clear the semaphore
1369 * bits to free the driver to make progress
1371 ixgbe_release_eeprom_semaphore(hw
);
1373 usleep_range(50, 100);
1375 * If the SMBI bit is 0 when we read it, then the bit will be
1376 * set and we have the semaphore
1378 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM(hw
));
1379 if (swsm
& IXGBE_SWSM_SMBI
) {
1380 hw_dbg(hw
, "Software semaphore SMBI between device drivers not granted.\n");
1381 return IXGBE_ERR_EEPROM
;
1385 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1386 for (i
= 0; i
< timeout
; i
++) {
1387 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM(hw
));
1389 /* Set the SW EEPROM semaphore bit to request access */
1390 swsm
|= IXGBE_SWSM_SWESMBI
;
1391 IXGBE_WRITE_REG(hw
, IXGBE_SWSM(hw
), swsm
);
1393 /* If we set the bit successfully then we got the
1396 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM(hw
));
1397 if (swsm
& IXGBE_SWSM_SWESMBI
)
1400 usleep_range(50, 100);
1403 /* Release semaphores and return error if SW EEPROM semaphore
1404 * was not granted because we don't have access to the EEPROM
1407 hw_dbg(hw
, "SWESMBI Software EEPROM semaphore not granted.\n");
1408 ixgbe_release_eeprom_semaphore(hw
);
1409 return IXGBE_ERR_EEPROM
;
1416 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1417 * @hw: pointer to hardware structure
1419 * This function clears hardware semaphore bits.
1421 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw
*hw
)
1425 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM(hw
));
1427 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1428 swsm
&= ~(IXGBE_SWSM_SWESMBI
| IXGBE_SWSM_SMBI
);
1429 IXGBE_WRITE_REG(hw
, IXGBE_SWSM(hw
), swsm
);
1430 IXGBE_WRITE_FLUSH(hw
);
1434 * ixgbe_ready_eeprom - Polls for EEPROM ready
1435 * @hw: pointer to hardware structure
1437 static s32
ixgbe_ready_eeprom(struct ixgbe_hw
*hw
)
1443 * Read "Status Register" repeatedly until the LSB is cleared. The
1444 * EEPROM will signal that the command has been completed by clearing
1445 * bit 0 of the internal status register. If it's not cleared within
1446 * 5 milliseconds, then error out.
1448 for (i
= 0; i
< IXGBE_EEPROM_MAX_RETRY_SPI
; i
+= 5) {
1449 ixgbe_shift_out_eeprom_bits(hw
, IXGBE_EEPROM_RDSR_OPCODE_SPI
,
1450 IXGBE_EEPROM_OPCODE_BITS
);
1451 spi_stat_reg
= (u8
)ixgbe_shift_in_eeprom_bits(hw
, 8);
1452 if (!(spi_stat_reg
& IXGBE_EEPROM_STATUS_RDY_SPI
))
1456 ixgbe_standby_eeprom(hw
);
1460 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1461 * devices (and only 0-5mSec on 5V devices)
1463 if (i
>= IXGBE_EEPROM_MAX_RETRY_SPI
) {
1464 hw_dbg(hw
, "SPI EEPROM Status error\n");
1465 return IXGBE_ERR_EEPROM
;
1472 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1473 * @hw: pointer to hardware structure
1475 static void ixgbe_standby_eeprom(struct ixgbe_hw
*hw
)
1479 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC(hw
));
1481 /* Toggle CS to flush commands */
1482 eec
|= IXGBE_EEC_CS
;
1483 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), eec
);
1484 IXGBE_WRITE_FLUSH(hw
);
1486 eec
&= ~IXGBE_EEC_CS
;
1487 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), eec
);
1488 IXGBE_WRITE_FLUSH(hw
);
1493 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1494 * @hw: pointer to hardware structure
1495 * @data: data to send to the EEPROM
1496 * @count: number of bits to shift out
1498 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw
*hw
, u16 data
,
1505 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC(hw
));
1508 * Mask is used to shift "count" bits of "data" out to the EEPROM
1509 * one bit at a time. Determine the starting bit based on count
1511 mask
= BIT(count
- 1);
1513 for (i
= 0; i
< count
; i
++) {
1515 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1516 * "1", and then raising and then lowering the clock (the SK
1517 * bit controls the clock input to the EEPROM). A "0" is
1518 * shifted out to the EEPROM by setting "DI" to "0" and then
1519 * raising and then lowering the clock.
1522 eec
|= IXGBE_EEC_DI
;
1524 eec
&= ~IXGBE_EEC_DI
;
1526 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), eec
);
1527 IXGBE_WRITE_FLUSH(hw
);
1531 ixgbe_raise_eeprom_clk(hw
, &eec
);
1532 ixgbe_lower_eeprom_clk(hw
, &eec
);
1535 * Shift mask to signify next bit of data to shift in to the
1541 /* We leave the "DI" bit set to "0" when we leave this routine. */
1542 eec
&= ~IXGBE_EEC_DI
;
1543 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), eec
);
1544 IXGBE_WRITE_FLUSH(hw
);
1548 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1549 * @hw: pointer to hardware structure
1551 static u16
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw
*hw
, u16 count
)
1558 * In order to read a register from the EEPROM, we need to shift
1559 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1560 * the clock input to the EEPROM (setting the SK bit), and then reading
1561 * the value of the "DO" bit. During this "shifting in" process the
1562 * "DI" bit should always be clear.
1564 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC(hw
));
1566 eec
&= ~(IXGBE_EEC_DO
| IXGBE_EEC_DI
);
1568 for (i
= 0; i
< count
; i
++) {
1570 ixgbe_raise_eeprom_clk(hw
, &eec
);
1572 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC(hw
));
1574 eec
&= ~(IXGBE_EEC_DI
);
1575 if (eec
& IXGBE_EEC_DO
)
1578 ixgbe_lower_eeprom_clk(hw
, &eec
);
1585 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1586 * @hw: pointer to hardware structure
1587 * @eec: EEC register's current value
1589 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
)
1592 * Raise the clock input to the EEPROM
1593 * (setting the SK bit), then delay
1595 *eec
= *eec
| IXGBE_EEC_SK
;
1596 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), *eec
);
1597 IXGBE_WRITE_FLUSH(hw
);
1602 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1603 * @hw: pointer to hardware structure
1604 * @eecd: EECD's current value
1606 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
)
1609 * Lower the clock input to the EEPROM (clearing the SK bit), then
1612 *eec
= *eec
& ~IXGBE_EEC_SK
;
1613 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), *eec
);
1614 IXGBE_WRITE_FLUSH(hw
);
1619 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1620 * @hw: pointer to hardware structure
1622 static void ixgbe_release_eeprom(struct ixgbe_hw
*hw
)
1626 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC(hw
));
1628 eec
|= IXGBE_EEC_CS
; /* Pull CS high */
1629 eec
&= ~IXGBE_EEC_SK
; /* Lower SCK */
1631 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), eec
);
1632 IXGBE_WRITE_FLUSH(hw
);
1636 /* Stop requesting EEPROM access */
1637 eec
&= ~IXGBE_EEC_REQ
;
1638 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), eec
);
1640 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
1643 * Delay before attempt to obtain semaphore again to allow FW
1644 * access. semaphore_delay is in ms we need us for usleep_range
1646 usleep_range(hw
->eeprom
.semaphore_delay
* 1000,
1647 hw
->eeprom
.semaphore_delay
* 2000);
1651 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1652 * @hw: pointer to hardware structure
1654 s32
ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw
*hw
)
1663 /* Include 0x0-0x3F in the checksum */
1664 for (i
= 0; i
< IXGBE_EEPROM_CHECKSUM
; i
++) {
1665 if (hw
->eeprom
.ops
.read(hw
, i
, &word
)) {
1666 hw_dbg(hw
, "EEPROM read failed\n");
1672 /* Include all data from pointers except for the fw pointer */
1673 for (i
= IXGBE_PCIE_ANALOG_PTR
; i
< IXGBE_FW_PTR
; i
++) {
1674 if (hw
->eeprom
.ops
.read(hw
, i
, &pointer
)) {
1675 hw_dbg(hw
, "EEPROM read failed\n");
1676 return IXGBE_ERR_EEPROM
;
1679 /* If the pointer seems invalid */
1680 if (pointer
== 0xFFFF || pointer
== 0)
1683 if (hw
->eeprom
.ops
.read(hw
, pointer
, &length
)) {
1684 hw_dbg(hw
, "EEPROM read failed\n");
1685 return IXGBE_ERR_EEPROM
;
1688 if (length
== 0xFFFF || length
== 0)
1691 for (j
= pointer
+ 1; j
<= pointer
+ length
; j
++) {
1692 if (hw
->eeprom
.ops
.read(hw
, j
, &word
)) {
1693 hw_dbg(hw
, "EEPROM read failed\n");
1694 return IXGBE_ERR_EEPROM
;
1700 checksum
= (u16
)IXGBE_EEPROM_SUM
- checksum
;
1702 return (s32
)checksum
;
1706 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1707 * @hw: pointer to hardware structure
1708 * @checksum_val: calculated checksum
1710 * Performs checksum calculation and validates the EEPROM checksum. If the
1711 * caller does not need checksum_val, the value can be NULL.
1713 s32
ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw
*hw
,
1718 u16 read_checksum
= 0;
1721 * Read the first word from the EEPROM. If this times out or fails, do
1722 * not continue or we could be in for a very long wait while every
1725 status
= hw
->eeprom
.ops
.read(hw
, 0, &checksum
);
1727 hw_dbg(hw
, "EEPROM read failed\n");
1731 status
= hw
->eeprom
.ops
.calc_checksum(hw
);
1735 checksum
= (u16
)(status
& 0xffff);
1737 status
= hw
->eeprom
.ops
.read(hw
, IXGBE_EEPROM_CHECKSUM
, &read_checksum
);
1739 hw_dbg(hw
, "EEPROM read failed\n");
1743 /* Verify read checksum from EEPROM is the same as
1744 * calculated checksum
1746 if (read_checksum
!= checksum
)
1747 status
= IXGBE_ERR_EEPROM_CHECKSUM
;
1749 /* If the user cares, return the calculated checksum */
1751 *checksum_val
= checksum
;
1757 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1758 * @hw: pointer to hardware structure
1760 s32
ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw
*hw
)
1766 * Read the first word from the EEPROM. If this times out or fails, do
1767 * not continue or we could be in for a very long wait while every
1770 status
= hw
->eeprom
.ops
.read(hw
, 0, &checksum
);
1772 hw_dbg(hw
, "EEPROM read failed\n");
1776 status
= hw
->eeprom
.ops
.calc_checksum(hw
);
1780 checksum
= (u16
)(status
& 0xffff);
1782 status
= hw
->eeprom
.ops
.write(hw
, IXGBE_EEPROM_CHECKSUM
, checksum
);
1788 * ixgbe_set_rar_generic - Set Rx address register
1789 * @hw: pointer to hardware structure
1790 * @index: Receive address register to write
1791 * @addr: Address to put into receive address register
1792 * @vmdq: VMDq "set" or "pool" index
1793 * @enable_addr: set flag that address is active
1795 * Puts an ethernet address into a receive address register.
1797 s32
ixgbe_set_rar_generic(struct ixgbe_hw
*hw
, u32 index
, u8
*addr
, u32 vmdq
,
1800 u32 rar_low
, rar_high
;
1801 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1803 /* Make sure we are using a valid rar index range */
1804 if (index
>= rar_entries
) {
1805 hw_dbg(hw
, "RAR index %d is out of range.\n", index
);
1806 return IXGBE_ERR_INVALID_ARGUMENT
;
1809 /* setup VMDq pool selection before this RAR gets enabled */
1810 hw
->mac
.ops
.set_vmdq(hw
, index
, vmdq
);
1813 * HW expects these in little endian so we reverse the byte
1814 * order from network order (big endian) to little endian
1816 rar_low
= ((u32
)addr
[0] |
1817 ((u32
)addr
[1] << 8) |
1818 ((u32
)addr
[2] << 16) |
1819 ((u32
)addr
[3] << 24));
1821 * Some parts put the VMDq setting in the extra RAH bits,
1822 * so save everything except the lower 16 bits that hold part
1823 * of the address and the address valid bit.
1825 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1826 rar_high
&= ~(0x0000FFFF | IXGBE_RAH_AV
);
1827 rar_high
|= ((u32
)addr
[4] | ((u32
)addr
[5] << 8));
1829 if (enable_addr
!= 0)
1830 rar_high
|= IXGBE_RAH_AV
;
1832 IXGBE_WRITE_REG(hw
, IXGBE_RAL(index
), rar_low
);
1833 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1839 * ixgbe_clear_rar_generic - Remove Rx address register
1840 * @hw: pointer to hardware structure
1841 * @index: Receive address register to write
1843 * Clears an ethernet address from a receive address register.
1845 s32
ixgbe_clear_rar_generic(struct ixgbe_hw
*hw
, u32 index
)
1848 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1850 /* Make sure we are using a valid rar index range */
1851 if (index
>= rar_entries
) {
1852 hw_dbg(hw
, "RAR index %d is out of range.\n", index
);
1853 return IXGBE_ERR_INVALID_ARGUMENT
;
1857 * Some parts put the VMDq setting in the extra RAH bits,
1858 * so save everything except the lower 16 bits that hold part
1859 * of the address and the address valid bit.
1861 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1862 rar_high
&= ~(0x0000FFFF | IXGBE_RAH_AV
);
1864 IXGBE_WRITE_REG(hw
, IXGBE_RAL(index
), 0);
1865 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1867 /* clear VMDq pool/queue selection for this RAR */
1868 hw
->mac
.ops
.clear_vmdq(hw
, index
, IXGBE_CLEAR_VMDQ_ALL
);
1874 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1875 * @hw: pointer to hardware structure
1877 * Places the MAC address in receive address register 0 and clears the rest
1878 * of the receive address registers. Clears the multicast table. Assumes
1879 * the receiver is in reset when the routine is called.
1881 s32
ixgbe_init_rx_addrs_generic(struct ixgbe_hw
*hw
)
1884 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1887 * If the current mac address is valid, assume it is a software override
1888 * to the permanent address.
1889 * Otherwise, use the permanent address from the eeprom.
1891 if (!is_valid_ether_addr(hw
->mac
.addr
)) {
1892 /* Get the MAC address from the RAR0 for later reference */
1893 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.addr
);
1895 hw_dbg(hw
, " Keeping Current RAR0 Addr =%pM\n", hw
->mac
.addr
);
1897 /* Setup the receive address. */
1898 hw_dbg(hw
, "Overriding MAC Address in RAR[0]\n");
1899 hw_dbg(hw
, " New MAC Addr =%pM\n", hw
->mac
.addr
);
1901 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, 0, IXGBE_RAH_AV
);
1904 /* clear VMDq pool/queue selection for RAR 0 */
1905 hw
->mac
.ops
.clear_vmdq(hw
, 0, IXGBE_CLEAR_VMDQ_ALL
);
1907 hw
->addr_ctrl
.overflow_promisc
= 0;
1909 hw
->addr_ctrl
.rar_used_count
= 1;
1911 /* Zero out the other receive addresses. */
1912 hw_dbg(hw
, "Clearing RAR[1-%d]\n", rar_entries
- 1);
1913 for (i
= 1; i
< rar_entries
; i
++) {
1914 IXGBE_WRITE_REG(hw
, IXGBE_RAL(i
), 0);
1915 IXGBE_WRITE_REG(hw
, IXGBE_RAH(i
), 0);
1919 hw
->addr_ctrl
.mta_in_use
= 0;
1920 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, hw
->mac
.mc_filter_type
);
1922 hw_dbg(hw
, " Clearing MTA\n");
1923 for (i
= 0; i
< hw
->mac
.mcft_size
; i
++)
1924 IXGBE_WRITE_REG(hw
, IXGBE_MTA(i
), 0);
1926 if (hw
->mac
.ops
.init_uta_tables
)
1927 hw
->mac
.ops
.init_uta_tables(hw
);
1933 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1934 * @hw: pointer to hardware structure
1935 * @mc_addr: the multicast address
1937 * Extracts the 12 bits, from a multicast address, to determine which
1938 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1939 * incoming rx multicast addresses, to determine the bit-vector to check in
1940 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1941 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1942 * to mc_filter_type.
1944 static s32
ixgbe_mta_vector(struct ixgbe_hw
*hw
, u8
*mc_addr
)
1948 switch (hw
->mac
.mc_filter_type
) {
1949 case 0: /* use bits [47:36] of the address */
1950 vector
= ((mc_addr
[4] >> 4) | (((u16
)mc_addr
[5]) << 4));
1952 case 1: /* use bits [46:35] of the address */
1953 vector
= ((mc_addr
[4] >> 3) | (((u16
)mc_addr
[5]) << 5));
1955 case 2: /* use bits [45:34] of the address */
1956 vector
= ((mc_addr
[4] >> 2) | (((u16
)mc_addr
[5]) << 6));
1958 case 3: /* use bits [43:32] of the address */
1959 vector
= ((mc_addr
[4]) | (((u16
)mc_addr
[5]) << 8));
1961 default: /* Invalid mc_filter_type */
1962 hw_dbg(hw
, "MC filter type param set incorrectly\n");
1966 /* vector can only be 12-bits or boundary will be exceeded */
1972 * ixgbe_set_mta - Set bit-vector in multicast table
1973 * @hw: pointer to hardware structure
1974 * @hash_value: Multicast address hash value
1976 * Sets the bit-vector in the multicast table.
1978 static void ixgbe_set_mta(struct ixgbe_hw
*hw
, u8
*mc_addr
)
1984 hw
->addr_ctrl
.mta_in_use
++;
1986 vector
= ixgbe_mta_vector(hw
, mc_addr
);
1987 hw_dbg(hw
, " bit-vector = 0x%03X\n", vector
);
1990 * The MTA is a register array of 128 32-bit registers. It is treated
1991 * like an array of 4096 bits. We want to set bit
1992 * BitArray[vector_value]. So we figure out what register the bit is
1993 * in, read it, OR in the new bit, then write back the new value. The
1994 * register is determined by the upper 7 bits of the vector value and
1995 * the bit within that register are determined by the lower 5 bits of
1998 vector_reg
= (vector
>> 5) & 0x7F;
1999 vector_bit
= vector
& 0x1F;
2000 hw
->mac
.mta_shadow
[vector_reg
] |= BIT(vector_bit
);
2004 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2005 * @hw: pointer to hardware structure
2006 * @netdev: pointer to net device structure
2008 * The given list replaces any existing list. Clears the MC addrs from receive
2009 * address registers and the multicast table. Uses unused receive address
2010 * registers for the first multicast addresses, and hashes the rest into the
2013 s32
ixgbe_update_mc_addr_list_generic(struct ixgbe_hw
*hw
,
2014 struct net_device
*netdev
)
2016 struct netdev_hw_addr
*ha
;
2020 * Set the new number of MC addresses that we are being requested to
2023 hw
->addr_ctrl
.num_mc_addrs
= netdev_mc_count(netdev
);
2024 hw
->addr_ctrl
.mta_in_use
= 0;
2026 /* Clear mta_shadow */
2027 hw_dbg(hw
, " Clearing MTA\n");
2028 memset(&hw
->mac
.mta_shadow
, 0, sizeof(hw
->mac
.mta_shadow
));
2030 /* Update mta shadow */
2031 netdev_for_each_mc_addr(ha
, netdev
) {
2032 hw_dbg(hw
, " Adding the multicast addresses:\n");
2033 ixgbe_set_mta(hw
, ha
->addr
);
2037 for (i
= 0; i
< hw
->mac
.mcft_size
; i
++)
2038 IXGBE_WRITE_REG_ARRAY(hw
, IXGBE_MTA(0), i
,
2039 hw
->mac
.mta_shadow
[i
]);
2041 if (hw
->addr_ctrl
.mta_in_use
> 0)
2042 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
,
2043 IXGBE_MCSTCTRL_MFE
| hw
->mac
.mc_filter_type
);
2045 hw_dbg(hw
, "ixgbe_update_mc_addr_list_generic Complete\n");
2050 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2051 * @hw: pointer to hardware structure
2053 * Enables multicast address in RAR and the use of the multicast hash table.
2055 s32
ixgbe_enable_mc_generic(struct ixgbe_hw
*hw
)
2057 struct ixgbe_addr_filter_info
*a
= &hw
->addr_ctrl
;
2059 if (a
->mta_in_use
> 0)
2060 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, IXGBE_MCSTCTRL_MFE
|
2061 hw
->mac
.mc_filter_type
);
2067 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2068 * @hw: pointer to hardware structure
2070 * Disables multicast address in RAR and the use of the multicast hash table.
2072 s32
ixgbe_disable_mc_generic(struct ixgbe_hw
*hw
)
2074 struct ixgbe_addr_filter_info
*a
= &hw
->addr_ctrl
;
2076 if (a
->mta_in_use
> 0)
2077 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, hw
->mac
.mc_filter_type
);
2083 * ixgbe_fc_enable_generic - Enable flow control
2084 * @hw: pointer to hardware structure
2086 * Enable flow control according to the current settings.
2088 s32
ixgbe_fc_enable_generic(struct ixgbe_hw
*hw
)
2090 u32 mflcn_reg
, fccfg_reg
;
2095 /* Validate the water mark configuration. */
2096 if (!hw
->fc
.pause_time
)
2097 return IXGBE_ERR_INVALID_LINK_SETTINGS
;
2099 /* Low water mark of zero causes XOFF floods */
2100 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++) {
2101 if ((hw
->fc
.current_mode
& ixgbe_fc_tx_pause
) &&
2102 hw
->fc
.high_water
[i
]) {
2103 if (!hw
->fc
.low_water
[i
] ||
2104 hw
->fc
.low_water
[i
] >= hw
->fc
.high_water
[i
]) {
2105 hw_dbg(hw
, "Invalid water mark configuration\n");
2106 return IXGBE_ERR_INVALID_LINK_SETTINGS
;
2111 /* Negotiate the fc mode to use */
2112 ixgbe_fc_autoneg(hw
);
2114 /* Disable any previous flow control settings */
2115 mflcn_reg
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
2116 mflcn_reg
&= ~(IXGBE_MFLCN_RPFCE_MASK
| IXGBE_MFLCN_RFCE
);
2118 fccfg_reg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
2119 fccfg_reg
&= ~(IXGBE_FCCFG_TFCE_802_3X
| IXGBE_FCCFG_TFCE_PRIORITY
);
2122 * The possible values of fc.current_mode are:
2123 * 0: Flow control is completely disabled
2124 * 1: Rx flow control is enabled (we can receive pause frames,
2125 * but not send pause frames).
2126 * 2: Tx flow control is enabled (we can send pause frames but
2127 * we do not support receiving pause frames).
2128 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2131 switch (hw
->fc
.current_mode
) {
2134 * Flow control is disabled by software override or autoneg.
2135 * The code below will actually disable it in the HW.
2138 case ixgbe_fc_rx_pause
:
2140 * Rx Flow control is enabled and Tx Flow control is
2141 * disabled by software override. Since there really
2142 * isn't a way to advertise that we are capable of RX
2143 * Pause ONLY, we will advertise that we support both
2144 * symmetric and asymmetric Rx PAUSE. Later, we will
2145 * disable the adapter's ability to send PAUSE frames.
2147 mflcn_reg
|= IXGBE_MFLCN_RFCE
;
2149 case ixgbe_fc_tx_pause
:
2151 * Tx Flow control is enabled, and Rx Flow control is
2152 * disabled by software override.
2154 fccfg_reg
|= IXGBE_FCCFG_TFCE_802_3X
;
2157 /* Flow control (both Rx and Tx) is enabled by SW override. */
2158 mflcn_reg
|= IXGBE_MFLCN_RFCE
;
2159 fccfg_reg
|= IXGBE_FCCFG_TFCE_802_3X
;
2162 hw_dbg(hw
, "Flow control param set incorrectly\n");
2163 return IXGBE_ERR_CONFIG
;
2166 /* Set 802.3x based flow control settings. */
2167 mflcn_reg
|= IXGBE_MFLCN_DPF
;
2168 IXGBE_WRITE_REG(hw
, IXGBE_MFLCN
, mflcn_reg
);
2169 IXGBE_WRITE_REG(hw
, IXGBE_FCCFG
, fccfg_reg
);
2171 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2172 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++) {
2173 if ((hw
->fc
.current_mode
& ixgbe_fc_tx_pause
) &&
2174 hw
->fc
.high_water
[i
]) {
2175 fcrtl
= (hw
->fc
.low_water
[i
] << 10) | IXGBE_FCRTL_XONE
;
2176 IXGBE_WRITE_REG(hw
, IXGBE_FCRTL_82599(i
), fcrtl
);
2177 fcrth
= (hw
->fc
.high_water
[i
] << 10) | IXGBE_FCRTH_FCEN
;
2179 IXGBE_WRITE_REG(hw
, IXGBE_FCRTL_82599(i
), 0);
2181 * In order to prevent Tx hangs when the internal Tx
2182 * switch is enabled we must set the high water mark
2183 * to the Rx packet buffer size - 24KB. This allows
2184 * the Tx switch to function even under heavy Rx
2187 fcrth
= IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(i
)) - 24576;
2190 IXGBE_WRITE_REG(hw
, IXGBE_FCRTH_82599(i
), fcrth
);
2193 /* Configure pause time (2 TCs per register) */
2194 reg
= hw
->fc
.pause_time
* 0x00010001;
2195 for (i
= 0; i
< (MAX_TRAFFIC_CLASS
/ 2); i
++)
2196 IXGBE_WRITE_REG(hw
, IXGBE_FCTTV(i
), reg
);
2198 IXGBE_WRITE_REG(hw
, IXGBE_FCRTV
, hw
->fc
.pause_time
/ 2);
2204 * ixgbe_negotiate_fc - Negotiate flow control
2205 * @hw: pointer to hardware structure
2206 * @adv_reg: flow control advertised settings
2207 * @lp_reg: link partner's flow control settings
2208 * @adv_sym: symmetric pause bit in advertisement
2209 * @adv_asm: asymmetric pause bit in advertisement
2210 * @lp_sym: symmetric pause bit in link partner advertisement
2211 * @lp_asm: asymmetric pause bit in link partner advertisement
2213 * Find the intersection between advertised settings and link partner's
2214 * advertised settings
2216 static s32
ixgbe_negotiate_fc(struct ixgbe_hw
*hw
, u32 adv_reg
, u32 lp_reg
,
2217 u32 adv_sym
, u32 adv_asm
, u32 lp_sym
, u32 lp_asm
)
2219 if ((!(adv_reg
)) || (!(lp_reg
)))
2220 return IXGBE_ERR_FC_NOT_NEGOTIATED
;
2222 if ((adv_reg
& adv_sym
) && (lp_reg
& lp_sym
)) {
2224 * Now we need to check if the user selected Rx ONLY
2225 * of pause frames. In this case, we had to advertise
2226 * FULL flow control because we could not advertise RX
2227 * ONLY. Hence, we must now check to see if we need to
2228 * turn OFF the TRANSMISSION of PAUSE frames.
2230 if (hw
->fc
.requested_mode
== ixgbe_fc_full
) {
2231 hw
->fc
.current_mode
= ixgbe_fc_full
;
2232 hw_dbg(hw
, "Flow Control = FULL.\n");
2234 hw
->fc
.current_mode
= ixgbe_fc_rx_pause
;
2235 hw_dbg(hw
, "Flow Control=RX PAUSE frames only\n");
2237 } else if (!(adv_reg
& adv_sym
) && (adv_reg
& adv_asm
) &&
2238 (lp_reg
& lp_sym
) && (lp_reg
& lp_asm
)) {
2239 hw
->fc
.current_mode
= ixgbe_fc_tx_pause
;
2240 hw_dbg(hw
, "Flow Control = TX PAUSE frames only.\n");
2241 } else if ((adv_reg
& adv_sym
) && (adv_reg
& adv_asm
) &&
2242 !(lp_reg
& lp_sym
) && (lp_reg
& lp_asm
)) {
2243 hw
->fc
.current_mode
= ixgbe_fc_rx_pause
;
2244 hw_dbg(hw
, "Flow Control = RX PAUSE frames only.\n");
2246 hw
->fc
.current_mode
= ixgbe_fc_none
;
2247 hw_dbg(hw
, "Flow Control = NONE.\n");
2253 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2254 * @hw: pointer to hardware structure
2256 * Enable flow control according on 1 gig fiber.
2258 static s32
ixgbe_fc_autoneg_fiber(struct ixgbe_hw
*hw
)
2260 u32 pcs_anadv_reg
, pcs_lpab_reg
, linkstat
;
2264 * On multispeed fiber at 1g, bail out if
2265 * - link is up but AN did not complete, or if
2266 * - link is up and AN completed but timed out
2269 linkstat
= IXGBE_READ_REG(hw
, IXGBE_PCS1GLSTA
);
2270 if ((!!(linkstat
& IXGBE_PCS1GLSTA_AN_COMPLETE
) == 0) ||
2271 (!!(linkstat
& IXGBE_PCS1GLSTA_AN_TIMED_OUT
) == 1))
2272 return IXGBE_ERR_FC_NOT_NEGOTIATED
;
2274 pcs_anadv_reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANA
);
2275 pcs_lpab_reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANLP
);
2277 ret_val
= ixgbe_negotiate_fc(hw
, pcs_anadv_reg
,
2278 pcs_lpab_reg
, IXGBE_PCS1GANA_SYM_PAUSE
,
2279 IXGBE_PCS1GANA_ASM_PAUSE
,
2280 IXGBE_PCS1GANA_SYM_PAUSE
,
2281 IXGBE_PCS1GANA_ASM_PAUSE
);
2287 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2288 * @hw: pointer to hardware structure
2290 * Enable flow control according to IEEE clause 37.
2292 static s32
ixgbe_fc_autoneg_backplane(struct ixgbe_hw
*hw
)
2294 u32 links2
, anlp1_reg
, autoc_reg
, links
;
2298 * On backplane, bail out if
2299 * - backplane autoneg was not completed, or if
2300 * - we are 82599 and link partner is not AN enabled
2302 links
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
2303 if ((links
& IXGBE_LINKS_KX_AN_COMP
) == 0)
2304 return IXGBE_ERR_FC_NOT_NEGOTIATED
;
2306 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2307 links2
= IXGBE_READ_REG(hw
, IXGBE_LINKS2
);
2308 if ((links2
& IXGBE_LINKS2_AN_SUPPORTED
) == 0)
2309 return IXGBE_ERR_FC_NOT_NEGOTIATED
;
2312 * Read the 10g AN autoc and LP ability registers and resolve
2313 * local flow control settings accordingly
2315 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2316 anlp1_reg
= IXGBE_READ_REG(hw
, IXGBE_ANLP1
);
2318 ret_val
= ixgbe_negotiate_fc(hw
, autoc_reg
,
2319 anlp1_reg
, IXGBE_AUTOC_SYM_PAUSE
, IXGBE_AUTOC_ASM_PAUSE
,
2320 IXGBE_ANLP1_SYM_PAUSE
, IXGBE_ANLP1_ASM_PAUSE
);
2326 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2327 * @hw: pointer to hardware structure
2329 * Enable flow control according to IEEE clause 37.
2331 static s32
ixgbe_fc_autoneg_copper(struct ixgbe_hw
*hw
)
2333 u16 technology_ability_reg
= 0;
2334 u16 lp_technology_ability_reg
= 0;
2336 hw
->phy
.ops
.read_reg(hw
, MDIO_AN_ADVERTISE
,
2338 &technology_ability_reg
);
2339 hw
->phy
.ops
.read_reg(hw
, MDIO_AN_LPA
,
2341 &lp_technology_ability_reg
);
2343 return ixgbe_negotiate_fc(hw
, (u32
)technology_ability_reg
,
2344 (u32
)lp_technology_ability_reg
,
2345 IXGBE_TAF_SYM_PAUSE
, IXGBE_TAF_ASM_PAUSE
,
2346 IXGBE_TAF_SYM_PAUSE
, IXGBE_TAF_ASM_PAUSE
);
2350 * ixgbe_fc_autoneg - Configure flow control
2351 * @hw: pointer to hardware structure
2353 * Compares our advertised flow control capabilities to those advertised by
2354 * our link partner, and determines the proper flow control mode to use.
2356 void ixgbe_fc_autoneg(struct ixgbe_hw
*hw
)
2358 s32 ret_val
= IXGBE_ERR_FC_NOT_NEGOTIATED
;
2359 ixgbe_link_speed speed
;
2363 * AN should have completed when the cable was plugged in.
2364 * Look for reasons to bail out. Bail out if:
2365 * - FC autoneg is disabled, or if
2368 * Since we're being called from an LSC, link is already known to be up.
2369 * So use link_up_wait_to_complete=false.
2371 if (hw
->fc
.disable_fc_autoneg
)
2374 hw
->mac
.ops
.check_link(hw
, &speed
, &link_up
, false);
2378 switch (hw
->phy
.media_type
) {
2379 /* Autoneg flow control on fiber adapters */
2380 case ixgbe_media_type_fiber
:
2381 if (speed
== IXGBE_LINK_SPEED_1GB_FULL
)
2382 ret_val
= ixgbe_fc_autoneg_fiber(hw
);
2385 /* Autoneg flow control on backplane adapters */
2386 case ixgbe_media_type_backplane
:
2387 ret_val
= ixgbe_fc_autoneg_backplane(hw
);
2390 /* Autoneg flow control on copper adapters */
2391 case ixgbe_media_type_copper
:
2392 if (ixgbe_device_supports_autoneg_fc(hw
))
2393 ret_val
= ixgbe_fc_autoneg_copper(hw
);
2402 hw
->fc
.fc_was_autonegged
= true;
2404 hw
->fc
.fc_was_autonegged
= false;
2405 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
2410 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
2411 * @hw: pointer to hardware structure
2413 * System-wide timeout range is encoded in PCIe Device Control2 register.
2415 * Add 10% to specified maximum and return the number of times to poll for
2416 * completion timeout, in units of 100 microsec. Never return less than
2417 * 800 = 80 millisec.
2419 static u32
ixgbe_pcie_timeout_poll(struct ixgbe_hw
*hw
)
2424 devctl2
= ixgbe_read_pci_cfg_word(hw
, IXGBE_PCI_DEVICE_CONTROL2
);
2425 devctl2
&= IXGBE_PCIDEVCTRL2_TIMEO_MASK
;
2428 case IXGBE_PCIDEVCTRL2_65_130ms
:
2429 pollcnt
= 1300; /* 130 millisec */
2431 case IXGBE_PCIDEVCTRL2_260_520ms
:
2432 pollcnt
= 5200; /* 520 millisec */
2434 case IXGBE_PCIDEVCTRL2_1_2s
:
2435 pollcnt
= 20000; /* 2 sec */
2437 case IXGBE_PCIDEVCTRL2_4_8s
:
2438 pollcnt
= 80000; /* 8 sec */
2440 case IXGBE_PCIDEVCTRL2_17_34s
:
2441 pollcnt
= 34000; /* 34 sec */
2443 case IXGBE_PCIDEVCTRL2_50_100us
: /* 100 microsecs */
2444 case IXGBE_PCIDEVCTRL2_1_2ms
: /* 2 millisecs */
2445 case IXGBE_PCIDEVCTRL2_16_32ms
: /* 32 millisec */
2446 case IXGBE_PCIDEVCTRL2_16_32ms_def
: /* 32 millisec default */
2448 pollcnt
= 800; /* 80 millisec minimum */
2452 /* add 10% to spec maximum */
2453 return (pollcnt
* 11) / 10;
2457 * ixgbe_disable_pcie_master - Disable PCI-express master access
2458 * @hw: pointer to hardware structure
2460 * Disables PCI-Express master access and verifies there are no pending
2461 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2462 * bit hasn't caused the master requests to be disabled, else 0
2463 * is returned signifying master requests disabled.
2465 static s32
ixgbe_disable_pcie_master(struct ixgbe_hw
*hw
)
2470 /* Always set this bit to ensure any future transactions are blocked */
2471 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, IXGBE_CTRL_GIO_DIS
);
2473 /* Poll for bit to read as set */
2474 for (i
= 0; i
< IXGBE_PCI_MASTER_DISABLE_TIMEOUT
; i
++) {
2475 if (IXGBE_READ_REG(hw
, IXGBE_CTRL
) & IXGBE_CTRL_GIO_DIS
)
2477 usleep_range(100, 120);
2479 if (i
>= IXGBE_PCI_MASTER_DISABLE_TIMEOUT
) {
2480 hw_dbg(hw
, "GIO disable did not set - requesting resets\n");
2481 goto gio_disable_fail
;
2484 /* Exit if master requests are blocked */
2485 if (!(IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_GIO
) ||
2486 ixgbe_removed(hw
->hw_addr
))
2489 /* Poll for master request bit to clear */
2490 for (i
= 0; i
< IXGBE_PCI_MASTER_DISABLE_TIMEOUT
; i
++) {
2492 if (!(IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_GIO
))
2497 * Two consecutive resets are required via CTRL.RST per datasheet
2498 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2499 * of this need. The first reset prevents new master requests from
2500 * being issued by our device. We then must wait 1usec or more for any
2501 * remaining completions from the PCIe bus to trickle in, and then reset
2502 * again to clear out any effects they may have had on our device.
2504 hw_dbg(hw
, "GIO Master Disable bit didn't clear - requesting resets\n");
2506 hw
->mac
.flags
|= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
;
2508 if (hw
->mac
.type
>= ixgbe_mac_X550
)
2512 * Before proceeding, make sure that the PCIe block does not have
2513 * transactions pending.
2515 poll
= ixgbe_pcie_timeout_poll(hw
);
2516 for (i
= 0; i
< poll
; i
++) {
2518 value
= ixgbe_read_pci_cfg_word(hw
, IXGBE_PCI_DEVICE_STATUS
);
2519 if (ixgbe_removed(hw
->hw_addr
))
2521 if (!(value
& IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING
))
2525 hw_dbg(hw
, "PCIe transaction pending bit also did not clear.\n");
2526 return IXGBE_ERR_MASTER_REQUESTS_PENDING
;
2530 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2531 * @hw: pointer to hardware structure
2532 * @mask: Mask to specify which semaphore to acquire
2534 * Acquires the SWFW semaphore through the GSSR register for the specified
2535 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2537 s32
ixgbe_acquire_swfw_sync(struct ixgbe_hw
*hw
, u32 mask
)
2541 u32 fwmask
= mask
<< 5;
2545 for (i
= 0; i
< timeout
; i
++) {
2547 * SW NVM semaphore bit is used for access to all
2548 * SW_FW_SYNC bits (not just NVM)
2550 if (ixgbe_get_eeprom_semaphore(hw
))
2551 return IXGBE_ERR_SWFW_SYNC
;
2553 gssr
= IXGBE_READ_REG(hw
, IXGBE_GSSR
);
2554 if (!(gssr
& (fwmask
| swmask
))) {
2556 IXGBE_WRITE_REG(hw
, IXGBE_GSSR
, gssr
);
2557 ixgbe_release_eeprom_semaphore(hw
);
2560 /* Resource is currently in use by FW or SW */
2561 ixgbe_release_eeprom_semaphore(hw
);
2562 usleep_range(5000, 10000);
2566 /* If time expired clear the bits holding the lock and retry */
2567 if (gssr
& (fwmask
| swmask
))
2568 ixgbe_release_swfw_sync(hw
, gssr
& (fwmask
| swmask
));
2570 usleep_range(5000, 10000);
2571 return IXGBE_ERR_SWFW_SYNC
;
2575 * ixgbe_release_swfw_sync - Release SWFW semaphore
2576 * @hw: pointer to hardware structure
2577 * @mask: Mask to specify which semaphore to release
2579 * Releases the SWFW semaphore through the GSSR register for the specified
2580 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2582 void ixgbe_release_swfw_sync(struct ixgbe_hw
*hw
, u32 mask
)
2587 ixgbe_get_eeprom_semaphore(hw
);
2589 gssr
= IXGBE_READ_REG(hw
, IXGBE_GSSR
);
2591 IXGBE_WRITE_REG(hw
, IXGBE_GSSR
, gssr
);
2593 ixgbe_release_eeprom_semaphore(hw
);
2597 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
2598 * @hw: pointer to hardware structure
2599 * @reg_val: Value we read from AUTOC
2600 * @locked: bool to indicate whether the SW/FW lock should be taken. Never
2601 * true in this the generic case.
2603 * The default case requires no protection so just to the register read.
2605 s32
prot_autoc_read_generic(struct ixgbe_hw
*hw
, bool *locked
, u32
*reg_val
)
2608 *reg_val
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2613 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
2614 * @hw: pointer to hardware structure
2615 * @reg_val: value to write to AUTOC
2616 * @locked: bool to indicate whether the SW/FW lock was already taken by
2619 s32
prot_autoc_write_generic(struct ixgbe_hw
*hw
, u32 reg_val
, bool locked
)
2621 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, reg_val
);
2626 * ixgbe_disable_rx_buff_generic - Stops the receive data path
2627 * @hw: pointer to hardware structure
2629 * Stops the receive data path and waits for the HW to internally
2630 * empty the Rx security block.
2632 s32
ixgbe_disable_rx_buff_generic(struct ixgbe_hw
*hw
)
2634 #define IXGBE_MAX_SECRX_POLL 40
2638 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
2639 secrxreg
|= IXGBE_SECRXCTRL_RX_DIS
;
2640 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
2641 for (i
= 0; i
< IXGBE_MAX_SECRX_POLL
; i
++) {
2642 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXSTAT
);
2643 if (secrxreg
& IXGBE_SECRXSTAT_SECRX_RDY
)
2646 /* Use interrupt-safe sleep just in case */
2650 /* For informational purposes only */
2651 if (i
>= IXGBE_MAX_SECRX_POLL
)
2652 hw_dbg(hw
, "Rx unit being enabled before security path fully disabled. Continuing with init.\n");
2659 * ixgbe_enable_rx_buff - Enables the receive data path
2660 * @hw: pointer to hardware structure
2662 * Enables the receive data path
2664 s32
ixgbe_enable_rx_buff_generic(struct ixgbe_hw
*hw
)
2668 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
2669 secrxreg
&= ~IXGBE_SECRXCTRL_RX_DIS
;
2670 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
2671 IXGBE_WRITE_FLUSH(hw
);
2677 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2678 * @hw: pointer to hardware structure
2679 * @regval: register value to write to RXCTRL
2681 * Enables the Rx DMA unit
2683 s32
ixgbe_enable_rx_dma_generic(struct ixgbe_hw
*hw
, u32 regval
)
2685 if (regval
& IXGBE_RXCTRL_RXEN
)
2686 hw
->mac
.ops
.enable_rx(hw
);
2688 hw
->mac
.ops
.disable_rx(hw
);
2694 * ixgbe_blink_led_start_generic - Blink LED based on index.
2695 * @hw: pointer to hardware structure
2696 * @index: led number to blink
2698 s32
ixgbe_blink_led_start_generic(struct ixgbe_hw
*hw
, u32 index
)
2700 ixgbe_link_speed speed
= 0;
2701 bool link_up
= false;
2702 u32 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2703 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
2704 bool locked
= false;
2708 return IXGBE_ERR_PARAM
;
2711 * Link must be up to auto-blink the LEDs;
2712 * Force it if link is down.
2714 hw
->mac
.ops
.check_link(hw
, &speed
, &link_up
, false);
2717 ret_val
= hw
->mac
.ops
.prot_autoc_read(hw
, &locked
, &autoc_reg
);
2721 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
2722 autoc_reg
|= IXGBE_AUTOC_FLU
;
2724 ret_val
= hw
->mac
.ops
.prot_autoc_write(hw
, autoc_reg
, locked
);
2728 IXGBE_WRITE_FLUSH(hw
);
2730 usleep_range(10000, 20000);
2733 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
2734 led_reg
|= IXGBE_LED_BLINK(index
);
2735 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
2736 IXGBE_WRITE_FLUSH(hw
);
2742 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2743 * @hw: pointer to hardware structure
2744 * @index: led number to stop blinking
2746 s32
ixgbe_blink_led_stop_generic(struct ixgbe_hw
*hw
, u32 index
)
2749 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
2750 bool locked
= false;
2754 return IXGBE_ERR_PARAM
;
2756 ret_val
= hw
->mac
.ops
.prot_autoc_read(hw
, &locked
, &autoc_reg
);
2760 autoc_reg
&= ~IXGBE_AUTOC_FLU
;
2761 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
2763 ret_val
= hw
->mac
.ops
.prot_autoc_write(hw
, autoc_reg
, locked
);
2767 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
2768 led_reg
&= ~IXGBE_LED_BLINK(index
);
2769 led_reg
|= IXGBE_LED_LINK_ACTIVE
<< IXGBE_LED_MODE_SHIFT(index
);
2770 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
2771 IXGBE_WRITE_FLUSH(hw
);
2777 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2778 * @hw: pointer to hardware structure
2779 * @san_mac_offset: SAN MAC address offset
2781 * This function will read the EEPROM location for the SAN MAC address
2782 * pointer, and returns the value at that location. This is used in both
2783 * get and set mac_addr routines.
2785 static s32
ixgbe_get_san_mac_addr_offset(struct ixgbe_hw
*hw
,
2786 u16
*san_mac_offset
)
2791 * First read the EEPROM pointer to see if the MAC addresses are
2794 ret_val
= hw
->eeprom
.ops
.read(hw
, IXGBE_SAN_MAC_ADDR_PTR
,
2797 hw_err(hw
, "eeprom read at offset %d failed\n",
2798 IXGBE_SAN_MAC_ADDR_PTR
);
2804 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2805 * @hw: pointer to hardware structure
2806 * @san_mac_addr: SAN MAC address
2808 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2809 * per-port, so set_lan_id() must be called before reading the addresses.
2810 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2811 * upon for non-SFP connections, so we must call it here.
2813 s32
ixgbe_get_san_mac_addr_generic(struct ixgbe_hw
*hw
, u8
*san_mac_addr
)
2815 u16 san_mac_data
, san_mac_offset
;
2820 * First read the EEPROM pointer to see if the MAC addresses are
2821 * available. If they're not, no point in calling set_lan_id() here.
2823 ret_val
= ixgbe_get_san_mac_addr_offset(hw
, &san_mac_offset
);
2824 if (ret_val
|| san_mac_offset
== 0 || san_mac_offset
== 0xFFFF)
2826 goto san_mac_addr_clr
;
2828 /* make sure we know which port we need to program */
2829 hw
->mac
.ops
.set_lan_id(hw
);
2830 /* apply the port offset to the address offset */
2831 (hw
->bus
.func
) ? (san_mac_offset
+= IXGBE_SAN_MAC_ADDR_PORT1_OFFSET
) :
2832 (san_mac_offset
+= IXGBE_SAN_MAC_ADDR_PORT0_OFFSET
);
2833 for (i
= 0; i
< 3; i
++) {
2834 ret_val
= hw
->eeprom
.ops
.read(hw
, san_mac_offset
,
2837 hw_err(hw
, "eeprom read at offset %d failed\n",
2839 goto san_mac_addr_clr
;
2841 san_mac_addr
[i
* 2] = (u8
)(san_mac_data
);
2842 san_mac_addr
[i
* 2 + 1] = (u8
)(san_mac_data
>> 8);
2848 /* No addresses available in this EEPROM. It's not necessarily an
2849 * error though, so just wipe the local address and return.
2851 for (i
= 0; i
< 6; i
++)
2852 san_mac_addr
[i
] = 0xFF;
2857 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2858 * @hw: pointer to hardware structure
2860 * Read PCIe configuration space, and get the MSI-X vector count from
2861 * the capabilities table.
2863 u16
ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw
*hw
)
2869 switch (hw
->mac
.type
) {
2870 case ixgbe_mac_82598EB
:
2871 pcie_offset
= IXGBE_PCIE_MSIX_82598_CAPS
;
2872 max_msix_count
= IXGBE_MAX_MSIX_VECTORS_82598
;
2874 case ixgbe_mac_82599EB
:
2875 case ixgbe_mac_X540
:
2876 case ixgbe_mac_X550
:
2877 case ixgbe_mac_X550EM_x
:
2878 case ixgbe_mac_x550em_a
:
2879 pcie_offset
= IXGBE_PCIE_MSIX_82599_CAPS
;
2880 max_msix_count
= IXGBE_MAX_MSIX_VECTORS_82599
;
2886 msix_count
= ixgbe_read_pci_cfg_word(hw
, pcie_offset
);
2887 if (ixgbe_removed(hw
->hw_addr
))
2889 msix_count
&= IXGBE_PCIE_MSIX_TBL_SZ_MASK
;
2891 /* MSI-X count is zero-based in HW */
2894 if (msix_count
> max_msix_count
)
2895 msix_count
= max_msix_count
;
2901 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2902 * @hw: pointer to hardware struct
2903 * @rar: receive address register index to disassociate
2904 * @vmdq: VMDq pool index to remove from the rar
2906 s32
ixgbe_clear_vmdq_generic(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
2908 u32 mpsar_lo
, mpsar_hi
;
2909 u32 rar_entries
= hw
->mac
.num_rar_entries
;
2911 /* Make sure we are using a valid rar index range */
2912 if (rar
>= rar_entries
) {
2913 hw_dbg(hw
, "RAR index %d is out of range.\n", rar
);
2914 return IXGBE_ERR_INVALID_ARGUMENT
;
2917 mpsar_lo
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_LO(rar
));
2918 mpsar_hi
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_HI(rar
));
2920 if (ixgbe_removed(hw
->hw_addr
))
2923 if (!mpsar_lo
&& !mpsar_hi
)
2926 if (vmdq
== IXGBE_CLEAR_VMDQ_ALL
) {
2928 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), 0);
2932 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), 0);
2935 } else if (vmdq
< 32) {
2936 mpsar_lo
&= ~BIT(vmdq
);
2937 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), mpsar_lo
);
2939 mpsar_hi
&= ~BIT(vmdq
- 32);
2940 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), mpsar_hi
);
2943 /* was that the last pool using this rar? */
2944 if (mpsar_lo
== 0 && mpsar_hi
== 0 && rar
!= 0)
2945 hw
->mac
.ops
.clear_rar(hw
, rar
);
2950 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2951 * @hw: pointer to hardware struct
2952 * @rar: receive address register index to associate with a VMDq index
2953 * @vmdq: VMDq pool index
2955 s32
ixgbe_set_vmdq_generic(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
2958 u32 rar_entries
= hw
->mac
.num_rar_entries
;
2960 /* Make sure we are using a valid rar index range */
2961 if (rar
>= rar_entries
) {
2962 hw_dbg(hw
, "RAR index %d is out of range.\n", rar
);
2963 return IXGBE_ERR_INVALID_ARGUMENT
;
2967 mpsar
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_LO(rar
));
2969 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), mpsar
);
2971 mpsar
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_HI(rar
));
2972 mpsar
|= BIT(vmdq
- 32);
2973 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), mpsar
);
2979 * This function should only be involved in the IOV mode.
2980 * In IOV mode, Default pool is next pool after the number of
2981 * VFs advertized and not 0.
2982 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
2984 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
2985 * @hw: pointer to hardware struct
2986 * @vmdq: VMDq pool index
2988 s32
ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw
*hw
, u32 vmdq
)
2990 u32 rar
= hw
->mac
.san_mac_rar_index
;
2993 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), BIT(vmdq
));
2994 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), 0);
2996 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), 0);
2997 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), BIT(vmdq
- 32));
3004 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3005 * @hw: pointer to hardware structure
3007 s32
ixgbe_init_uta_tables_generic(struct ixgbe_hw
*hw
)
3011 for (i
= 0; i
< 128; i
++)
3012 IXGBE_WRITE_REG(hw
, IXGBE_UTA(i
), 0);
3018 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3019 * @hw: pointer to hardware structure
3020 * @vlan: VLAN id to write to VLAN filter
3022 * return the VLVF index where this VLAN id should be placed
3025 static s32
ixgbe_find_vlvf_slot(struct ixgbe_hw
*hw
, u32 vlan
, bool vlvf_bypass
)
3027 s32 regindex
, first_empty_slot
;
3030 /* short cut the special case */
3034 /* if vlvf_bypass is set we don't want to use an empty slot, we
3035 * will simply bypass the VLVF if there are no entries present in the
3036 * VLVF that contain our VLAN
3038 first_empty_slot
= vlvf_bypass
? IXGBE_ERR_NO_SPACE
: 0;
3040 /* add VLAN enable bit for comparison */
3041 vlan
|= IXGBE_VLVF_VIEN
;
3043 /* Search for the vlan id in the VLVF entries. Save off the first empty
3044 * slot found along the way.
3046 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
3048 for (regindex
= IXGBE_VLVF_ENTRIES
; --regindex
;) {
3049 bits
= IXGBE_READ_REG(hw
, IXGBE_VLVF(regindex
));
3052 if (!first_empty_slot
&& !bits
)
3053 first_empty_slot
= regindex
;
3056 /* If we are here then we didn't find the VLAN. Return first empty
3057 * slot we found during our search, else error.
3059 if (!first_empty_slot
)
3060 hw_dbg(hw
, "No space in VLVF.\n");
3062 return first_empty_slot
? : IXGBE_ERR_NO_SPACE
;
3066 * ixgbe_set_vfta_generic - Set VLAN filter table
3067 * @hw: pointer to hardware structure
3068 * @vlan: VLAN id to write to VLAN filter
3069 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3070 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3071 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3073 * Turn on/off specified VLAN in the VLAN filter table.
3075 s32
ixgbe_set_vfta_generic(struct ixgbe_hw
*hw
, u32 vlan
, u32 vind
,
3076 bool vlan_on
, bool vlvf_bypass
)
3078 u32 regidx
, vfta_delta
, vfta
, bits
;
3081 if ((vlan
> 4095) || (vind
> 63))
3082 return IXGBE_ERR_PARAM
;
3085 * this is a 2 part operation - first the VFTA, then the
3086 * VLVF and VLVFB if VT Mode is set
3087 * We don't write the VFTA until we know the VLVF part succeeded.
3091 * The VFTA is a bitstring made up of 128 32-bit registers
3092 * that enable the particular VLAN id, much like the MTA:
3093 * bits[11-5]: which register
3094 * bits[4-0]: which bit in the register
3097 vfta_delta
= BIT(vlan
% 32);
3098 vfta
= IXGBE_READ_REG(hw
, IXGBE_VFTA(regidx
));
3100 /* vfta_delta represents the difference between the current value
3101 * of vfta and the value we want in the register. Since the diff
3102 * is an XOR mask we can just update vfta using an XOR.
3104 vfta_delta
&= vlan_on
? ~vfta
: vfta
;
3110 * make sure the vlan is in VLVF
3111 * set the vind bit in the matching VLVFB
3113 * clear the pool bit and possibly the vind
3115 if (!(IXGBE_READ_REG(hw
, IXGBE_VT_CTL
) & IXGBE_VT_CTL_VT_ENABLE
))
3118 vlvf_index
= ixgbe_find_vlvf_slot(hw
, vlan
, vlvf_bypass
);
3119 if (vlvf_index
< 0) {
3125 bits
= IXGBE_READ_REG(hw
, IXGBE_VLVFB(vlvf_index
* 2 + vind
/ 32));
3127 /* set the pool bit */
3128 bits
|= BIT(vind
% 32);
3132 /* clear the pool bit */
3133 bits
^= BIT(vind
% 32);
3136 !IXGBE_READ_REG(hw
, IXGBE_VLVFB(vlvf_index
* 2 + 1 - vind
/ 32))) {
3137 /* Clear VFTA first, then disable VLVF. Otherwise
3138 * we run the risk of stray packets leaking into
3139 * the PF via the default pool
3142 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(regidx
), vfta
);
3144 /* disable VLVF and clear remaining bit from pool */
3145 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(vlvf_index
), 0);
3146 IXGBE_WRITE_REG(hw
, IXGBE_VLVFB(vlvf_index
* 2 + vind
/ 32), 0);
3151 /* If there are still bits set in the VLVFB registers
3152 * for the VLAN ID indicated we need to see if the
3153 * caller is requesting that we clear the VFTA entry bit.
3154 * If the caller has requested that we clear the VFTA
3155 * entry bit but there are still pools/VFs using this VLAN
3156 * ID entry then ignore the request. We're not worried
3157 * about the case where we're turning the VFTA VLAN ID
3158 * entry bit on, only when requested to turn it off as
3159 * there may be multiple pools and/or VFs using the
3160 * VLAN ID entry. In that case we cannot clear the
3161 * VFTA bit until all pools/VFs using that VLAN ID have also
3162 * been cleared. This will be indicated by "bits" being
3168 /* record pool change and enable VLAN ID if not already enabled */
3169 IXGBE_WRITE_REG(hw
, IXGBE_VLVFB(vlvf_index
* 2 + vind
/ 32), bits
);
3170 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(vlvf_index
), IXGBE_VLVF_VIEN
| vlan
);
3173 /* Update VFTA now that we are ready for traffic */
3175 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(regidx
), vfta
);
3181 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3182 * @hw: pointer to hardware structure
3184 * Clears the VLAN filer table, and the VMDq index associated with the filter
3186 s32
ixgbe_clear_vfta_generic(struct ixgbe_hw
*hw
)
3190 for (offset
= 0; offset
< hw
->mac
.vft_size
; offset
++)
3191 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(offset
), 0);
3193 for (offset
= 0; offset
< IXGBE_VLVF_ENTRIES
; offset
++) {
3194 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(offset
), 0);
3195 IXGBE_WRITE_REG(hw
, IXGBE_VLVFB(offset
* 2), 0);
3196 IXGBE_WRITE_REG(hw
, IXGBE_VLVFB(offset
* 2 + 1), 0);
3203 * ixgbe_check_mac_link_generic - Determine link and speed status
3204 * @hw: pointer to hardware structure
3205 * @speed: pointer to link speed
3206 * @link_up: true when link is up
3207 * @link_up_wait_to_complete: bool used to wait for link up or not
3209 * Reads the links register to determine if link is up and the current speed
3211 s32
ixgbe_check_mac_link_generic(struct ixgbe_hw
*hw
, ixgbe_link_speed
*speed
,
3212 bool *link_up
, bool link_up_wait_to_complete
)
3214 u32 links_reg
, links_orig
;
3217 /* clear the old state */
3218 links_orig
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
3220 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
3222 if (links_orig
!= links_reg
) {
3223 hw_dbg(hw
, "LINKS changed from %08X to %08X\n",
3224 links_orig
, links_reg
);
3227 if (link_up_wait_to_complete
) {
3228 for (i
= 0; i
< IXGBE_LINK_UP_TIME
; i
++) {
3229 if (links_reg
& IXGBE_LINKS_UP
) {
3236 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
3239 if (links_reg
& IXGBE_LINKS_UP
)
3245 switch (links_reg
& IXGBE_LINKS_SPEED_82599
) {
3246 case IXGBE_LINKS_SPEED_10G_82599
:
3247 if ((hw
->mac
.type
>= ixgbe_mac_X550
) &&
3248 (links_reg
& IXGBE_LINKS_SPEED_NON_STD
))
3249 *speed
= IXGBE_LINK_SPEED_2_5GB_FULL
;
3251 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
3253 case IXGBE_LINKS_SPEED_1G_82599
:
3254 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
3256 case IXGBE_LINKS_SPEED_100_82599
:
3257 if ((hw
->mac
.type
>= ixgbe_mac_X550
) &&
3258 (links_reg
& IXGBE_LINKS_SPEED_NON_STD
))
3259 *speed
= IXGBE_LINK_SPEED_5GB_FULL
;
3261 *speed
= IXGBE_LINK_SPEED_100_FULL
;
3264 *speed
= IXGBE_LINK_SPEED_UNKNOWN
;
3271 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
3273 * @hw: pointer to hardware structure
3274 * @wwnn_prefix: the alternative WWNN prefix
3275 * @wwpn_prefix: the alternative WWPN prefix
3277 * This function will read the EEPROM from the alternative SAN MAC address
3278 * block to check the support for the alternative WWNN/WWPN prefix support.
3280 s32
ixgbe_get_wwn_prefix_generic(struct ixgbe_hw
*hw
, u16
*wwnn_prefix
,
3284 u16 alt_san_mac_blk_offset
;
3286 /* clear output first */
3287 *wwnn_prefix
= 0xFFFF;
3288 *wwpn_prefix
= 0xFFFF;
3290 /* check if alternative SAN MAC is supported */
3291 offset
= IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR
;
3292 if (hw
->eeprom
.ops
.read(hw
, offset
, &alt_san_mac_blk_offset
))
3293 goto wwn_prefix_err
;
3295 if ((alt_san_mac_blk_offset
== 0) ||
3296 (alt_san_mac_blk_offset
== 0xFFFF))
3299 /* check capability in alternative san mac address block */
3300 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET
;
3301 if (hw
->eeprom
.ops
.read(hw
, offset
, &caps
))
3302 goto wwn_prefix_err
;
3303 if (!(caps
& IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN
))
3306 /* get the corresponding prefix for WWNN/WWPN */
3307 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET
;
3308 if (hw
->eeprom
.ops
.read(hw
, offset
, wwnn_prefix
))
3309 hw_err(hw
, "eeprom read at offset %d failed\n", offset
);
3311 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET
;
3312 if (hw
->eeprom
.ops
.read(hw
, offset
, wwpn_prefix
))
3313 goto wwn_prefix_err
;
3318 hw_err(hw
, "eeprom read at offset %d failed\n", offset
);
3323 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3324 * @hw: pointer to hardware structure
3325 * @enable: enable or disable switch for MAC anti-spoofing
3326 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
3329 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw
*hw
, bool enable
, int vf
)
3331 int vf_target_reg
= vf
>> 3;
3332 int vf_target_shift
= vf
% 8;
3335 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3338 pfvfspoof
= IXGBE_READ_REG(hw
, IXGBE_PFVFSPOOF(vf_target_reg
));
3340 pfvfspoof
|= BIT(vf_target_shift
);
3342 pfvfspoof
&= ~BIT(vf_target_shift
);
3343 IXGBE_WRITE_REG(hw
, IXGBE_PFVFSPOOF(vf_target_reg
), pfvfspoof
);
3347 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3348 * @hw: pointer to hardware structure
3349 * @enable: enable or disable switch for VLAN anti-spoofing
3350 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3353 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw
*hw
, bool enable
, int vf
)
3355 int vf_target_reg
= vf
>> 3;
3356 int vf_target_shift
= vf
% 8 + IXGBE_SPOOF_VLANAS_SHIFT
;
3359 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3362 pfvfspoof
= IXGBE_READ_REG(hw
, IXGBE_PFVFSPOOF(vf_target_reg
));
3364 pfvfspoof
|= BIT(vf_target_shift
);
3366 pfvfspoof
&= ~BIT(vf_target_shift
);
3367 IXGBE_WRITE_REG(hw
, IXGBE_PFVFSPOOF(vf_target_reg
), pfvfspoof
);
3371 * ixgbe_get_device_caps_generic - Get additional device capabilities
3372 * @hw: pointer to hardware structure
3373 * @device_caps: the EEPROM word with the extra device capabilities
3375 * This function will read the EEPROM location for the device capabilities,
3376 * and return the word through device_caps.
3378 s32
ixgbe_get_device_caps_generic(struct ixgbe_hw
*hw
, u16
*device_caps
)
3380 hw
->eeprom
.ops
.read(hw
, IXGBE_DEVICE_CAPS
, device_caps
);
3386 * ixgbe_set_rxpba_generic - Initialize RX packet buffer
3387 * @hw: pointer to hardware structure
3388 * @num_pb: number of packet buffers to allocate
3389 * @headroom: reserve n KB of headroom
3390 * @strategy: packet buffer allocation strategy
3392 void ixgbe_set_rxpba_generic(struct ixgbe_hw
*hw
,
3397 u32 pbsize
= hw
->mac
.rx_pb_size
;
3399 u32 rxpktsize
, txpktsize
, txpbthresh
;
3401 /* Reserve headroom */
3407 /* Divide remaining packet buffer space amongst the number
3408 * of packet buffers requested using supplied strategy.
3411 case (PBA_STRATEGY_WEIGHTED
):
3412 /* pba_80_48 strategy weight first half of packet buffer with
3413 * 5/8 of the packet buffer space.
3415 rxpktsize
= ((pbsize
* 5 * 2) / (num_pb
* 8));
3416 pbsize
-= rxpktsize
* (num_pb
/ 2);
3417 rxpktsize
<<= IXGBE_RXPBSIZE_SHIFT
;
3418 for (; i
< (num_pb
/ 2); i
++)
3419 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), rxpktsize
);
3420 /* Fall through to configure remaining packet buffers */
3421 case (PBA_STRATEGY_EQUAL
):
3422 /* Divide the remaining Rx packet buffer evenly among the TCs */
3423 rxpktsize
= (pbsize
/ (num_pb
- i
)) << IXGBE_RXPBSIZE_SHIFT
;
3424 for (; i
< num_pb
; i
++)
3425 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), rxpktsize
);
3432 * Setup Tx packet buffer and threshold equally for all TCs
3433 * TXPBTHRESH register is set in K so divide by 1024 and subtract
3434 * 10 since the largest packet we support is just over 9K.
3436 txpktsize
= IXGBE_TXPBSIZE_MAX
/ num_pb
;
3437 txpbthresh
= (txpktsize
/ 1024) - IXGBE_TXPKT_SIZE_MAX
;
3438 for (i
= 0; i
< num_pb
; i
++) {
3439 IXGBE_WRITE_REG(hw
, IXGBE_TXPBSIZE(i
), txpktsize
);
3440 IXGBE_WRITE_REG(hw
, IXGBE_TXPBTHRESH(i
), txpbthresh
);
3443 /* Clear unused TCs, if any, to zero buffer size*/
3444 for (; i
< IXGBE_MAX_PB
; i
++) {
3445 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), 0);
3446 IXGBE_WRITE_REG(hw
, IXGBE_TXPBSIZE(i
), 0);
3447 IXGBE_WRITE_REG(hw
, IXGBE_TXPBTHRESH(i
), 0);
3452 * ixgbe_calculate_checksum - Calculate checksum for buffer
3453 * @buffer: pointer to EEPROM
3454 * @length: size of EEPROM to calculate a checksum for
3456 * Calculates the checksum for some buffer on a specified length. The
3457 * checksum calculated is returned.
3459 static u8
ixgbe_calculate_checksum(u8
*buffer
, u32 length
)
3467 for (i
= 0; i
< length
; i
++)
3470 return (u8
) (0 - sum
);
3474 * ixgbe_host_interface_command - Issue command to manageability block
3475 * @hw: pointer to the HW structure
3476 * @buffer: contains the command to write and where the return status will
3478 * @length: length of buffer, must be multiple of 4 bytes
3479 * @timeout: time in ms to wait for command completion
3480 * @return_data: read and return data from the buffer (true) or not (false)
3481 * Needed because FW structures are big endian and decoding of
3482 * these fields can be 8 bit or 16 bit based on command. Decoding
3483 * is not easily understood without making a table of commands.
3484 * So we will leave this up to the caller to read back the data
3487 * Communicates with the manageability block. On success return 0
3488 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3490 s32
ixgbe_host_interface_command(struct ixgbe_hw
*hw
, void *buffer
,
3491 u32 length
, u32 timeout
,
3494 u32 hdr_size
= sizeof(struct ixgbe_hic_hdr
);
3495 u32 hicr
, i
, bi
, fwsts
;
3496 u16 buf_len
, dword_len
;
3498 struct ixgbe_hic_hdr hdr
;
3503 if (!length
|| length
> IXGBE_HI_MAX_BLOCK_BYTE_LENGTH
) {
3504 hw_dbg(hw
, "Buffer length failure buffersize-%d.\n", length
);
3505 return IXGBE_ERR_HOST_INTERFACE_COMMAND
;
3507 /* Take management host interface semaphore */
3508 status
= hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_SW_MNG_SM
);
3512 /* Set bit 9 of FWSTS clearing FW reset indication */
3513 fwsts
= IXGBE_READ_REG(hw
, IXGBE_FWSTS
);
3514 IXGBE_WRITE_REG(hw
, IXGBE_FWSTS
, fwsts
| IXGBE_FWSTS_FWRI
);
3516 /* Check that the host interface is enabled. */
3517 hicr
= IXGBE_READ_REG(hw
, IXGBE_HICR
);
3518 if (!(hicr
& IXGBE_HICR_EN
)) {
3519 hw_dbg(hw
, "IXGBE_HOST_EN bit disabled.\n");
3520 status
= IXGBE_ERR_HOST_INTERFACE_COMMAND
;
3524 /* Calculate length in DWORDs. We must be DWORD aligned */
3525 if (length
% sizeof(u32
)) {
3526 hw_dbg(hw
, "Buffer length failure, not aligned to dword");
3527 status
= IXGBE_ERR_INVALID_ARGUMENT
;
3531 dword_len
= length
>> 2;
3533 /* The device driver writes the relevant command block
3534 * into the ram area.
3536 for (i
= 0; i
< dword_len
; i
++)
3537 IXGBE_WRITE_REG_ARRAY(hw
, IXGBE_FLEX_MNG
,
3538 i
, cpu_to_le32(bp
->u32arr
[i
]));
3540 /* Setting this bit tells the ARC that a new command is pending. */
3541 IXGBE_WRITE_REG(hw
, IXGBE_HICR
, hicr
| IXGBE_HICR_C
);
3543 for (i
= 0; i
< timeout
; i
++) {
3544 hicr
= IXGBE_READ_REG(hw
, IXGBE_HICR
);
3545 if (!(hicr
& IXGBE_HICR_C
))
3547 usleep_range(1000, 2000);
3550 /* Check command successful completion. */
3551 if ((timeout
&& i
== timeout
) ||
3552 !(IXGBE_READ_REG(hw
, IXGBE_HICR
) & IXGBE_HICR_SV
)) {
3553 hw_dbg(hw
, "Command has failed with no status valid.\n");
3554 status
= IXGBE_ERR_HOST_INTERFACE_COMMAND
;
3561 /* Calculate length in DWORDs */
3562 dword_len
= hdr_size
>> 2;
3564 /* first pull in the header so we know the buffer length */
3565 for (bi
= 0; bi
< dword_len
; bi
++) {
3566 bp
->u32arr
[bi
] = IXGBE_READ_REG_ARRAY(hw
, IXGBE_FLEX_MNG
, bi
);
3567 le32_to_cpus(&bp
->u32arr
[bi
]);
3570 /* If there is any thing in data position pull it in */
3571 buf_len
= bp
->hdr
.buf_len
;
3575 if (length
< round_up(buf_len
, 4) + hdr_size
) {
3576 hw_dbg(hw
, "Buffer not large enough for reply message.\n");
3577 status
= IXGBE_ERR_HOST_INTERFACE_COMMAND
;
3581 /* Calculate length in DWORDs, add 3 for odd lengths */
3582 dword_len
= (buf_len
+ 3) >> 2;
3584 /* Pull in the rest of the buffer (bi is where we left off) */
3585 for (; bi
<= dword_len
; bi
++) {
3586 bp
->u32arr
[bi
] = IXGBE_READ_REG_ARRAY(hw
, IXGBE_FLEX_MNG
, bi
);
3587 le32_to_cpus(&bp
->u32arr
[bi
]);
3591 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_SW_MNG_SM
);
3597 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3598 * @hw: pointer to the HW structure
3599 * @maj: driver version major number
3600 * @min: driver version minor number
3601 * @build: driver version build number
3602 * @sub: driver version sub build number
3604 * Sends driver version number to firmware through the manageability
3605 * block. On success return 0
3606 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3607 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3609 s32
ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw
*hw
, u8 maj
, u8 min
,
3612 struct ixgbe_hic_drv_info fw_cmd
;
3616 fw_cmd
.hdr
.cmd
= FW_CEM_CMD_DRIVER_INFO
;
3617 fw_cmd
.hdr
.buf_len
= FW_CEM_CMD_DRIVER_INFO_LEN
;
3618 fw_cmd
.hdr
.cmd_or_resp
.cmd_resv
= FW_CEM_CMD_RESERVED
;
3619 fw_cmd
.port_num
= hw
->bus
.func
;
3620 fw_cmd
.ver_maj
= maj
;
3621 fw_cmd
.ver_min
= min
;
3622 fw_cmd
.ver_build
= build
;
3623 fw_cmd
.ver_sub
= sub
;
3624 fw_cmd
.hdr
.checksum
= 0;
3625 fw_cmd
.hdr
.checksum
= ixgbe_calculate_checksum((u8
*)&fw_cmd
,
3626 (FW_CEM_HDR_LEN
+ fw_cmd
.hdr
.buf_len
));
3630 for (i
= 0; i
<= FW_CEM_MAX_RETRIES
; i
++) {
3631 ret_val
= ixgbe_host_interface_command(hw
, &fw_cmd
,
3633 IXGBE_HI_COMMAND_TIMEOUT
,
3638 if (fw_cmd
.hdr
.cmd_or_resp
.ret_status
==
3639 FW_CEM_RESP_STATUS_SUCCESS
)
3642 ret_val
= IXGBE_ERR_HOST_INTERFACE_COMMAND
;
3651 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3652 * @hw: pointer to the hardware structure
3654 * The 82599 and x540 MACs can experience issues if TX work is still pending
3655 * when a reset occurs. This function prevents this by flushing the PCIe
3656 * buffers on the system.
3658 void ixgbe_clear_tx_pending(struct ixgbe_hw
*hw
)
3660 u32 gcr_ext
, hlreg0
, i
, poll
;
3664 * If double reset is not requested then all transactions should
3665 * already be clear and as such there is no work to do
3667 if (!(hw
->mac
.flags
& IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
))
3671 * Set loopback enable to prevent any transmits from being sent
3672 * should the link come up. This assumes that the RXCTRL.RXEN bit
3673 * has already been cleared.
3675 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
3676 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
| IXGBE_HLREG0_LPBK
);
3678 /* wait for a last completion before clearing buffers */
3679 IXGBE_WRITE_FLUSH(hw
);
3680 usleep_range(3000, 6000);
3682 /* Before proceeding, make sure that the PCIe block does not have
3683 * transactions pending.
3685 poll
= ixgbe_pcie_timeout_poll(hw
);
3686 for (i
= 0; i
< poll
; i
++) {
3687 usleep_range(100, 200);
3688 value
= ixgbe_read_pci_cfg_word(hw
, IXGBE_PCI_DEVICE_STATUS
);
3689 if (ixgbe_removed(hw
->hw_addr
))
3691 if (!(value
& IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING
))
3695 /* initiate cleaning flow for buffers in the PCIe transaction layer */
3696 gcr_ext
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
3697 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
,
3698 gcr_ext
| IXGBE_GCR_EXT_BUFFERS_CLEAR
);
3700 /* Flush all writes and allow 20usec for all transactions to clear */
3701 IXGBE_WRITE_FLUSH(hw
);
3704 /* restore previous register values */
3705 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr_ext
);
3706 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
3709 static const u8 ixgbe_emc_temp_data
[4] = {
3710 IXGBE_EMC_INTERNAL_DATA
,
3711 IXGBE_EMC_DIODE1_DATA
,
3712 IXGBE_EMC_DIODE2_DATA
,
3713 IXGBE_EMC_DIODE3_DATA
3715 static const u8 ixgbe_emc_therm_limit
[4] = {
3716 IXGBE_EMC_INTERNAL_THERM_LIMIT
,
3717 IXGBE_EMC_DIODE1_THERM_LIMIT
,
3718 IXGBE_EMC_DIODE2_THERM_LIMIT
,
3719 IXGBE_EMC_DIODE3_THERM_LIMIT
3723 * ixgbe_get_ets_data - Extracts the ETS bit data
3724 * @hw: pointer to hardware structure
3725 * @ets_cfg: extected ETS data
3726 * @ets_offset: offset of ETS data
3728 * Returns error code.
3730 static s32
ixgbe_get_ets_data(struct ixgbe_hw
*hw
, u16
*ets_cfg
,
3735 status
= hw
->eeprom
.ops
.read(hw
, IXGBE_ETS_CFG
, ets_offset
);
3739 if ((*ets_offset
== 0x0000) || (*ets_offset
== 0xFFFF))
3740 return IXGBE_NOT_IMPLEMENTED
;
3742 status
= hw
->eeprom
.ops
.read(hw
, *ets_offset
, ets_cfg
);
3746 if ((*ets_cfg
& IXGBE_ETS_TYPE_MASK
) != IXGBE_ETS_TYPE_EMC_SHIFTED
)
3747 return IXGBE_NOT_IMPLEMENTED
;
3753 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
3754 * @hw: pointer to hardware structure
3756 * Returns the thermal sensor data structure
3758 s32
ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw
*hw
)
3766 struct ixgbe_thermal_sensor_data
*data
= &hw
->mac
.thermal_sensor_data
;
3768 /* Only support thermal sensors attached to physical port 0 */
3769 if ((IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_LAN_ID_1
))
3770 return IXGBE_NOT_IMPLEMENTED
;
3772 status
= ixgbe_get_ets_data(hw
, &ets_cfg
, &ets_offset
);
3776 num_sensors
= (ets_cfg
& IXGBE_ETS_NUM_SENSORS_MASK
);
3777 if (num_sensors
> IXGBE_MAX_SENSORS
)
3778 num_sensors
= IXGBE_MAX_SENSORS
;
3780 for (i
= 0; i
< num_sensors
; i
++) {
3784 status
= hw
->eeprom
.ops
.read(hw
, (ets_offset
+ 1 + i
),
3789 sensor_index
= ((ets_sensor
& IXGBE_ETS_DATA_INDEX_MASK
) >>
3790 IXGBE_ETS_DATA_INDEX_SHIFT
);
3791 sensor_location
= ((ets_sensor
& IXGBE_ETS_DATA_LOC_MASK
) >>
3792 IXGBE_ETS_DATA_LOC_SHIFT
);
3794 if (sensor_location
!= 0) {
3795 status
= hw
->phy
.ops
.read_i2c_byte(hw
,
3796 ixgbe_emc_temp_data
[sensor_index
],
3797 IXGBE_I2C_THERMAL_SENSOR_ADDR
,
3798 &data
->sensor
[i
].temp
);
3808 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
3809 * @hw: pointer to hardware structure
3811 * Inits the thermal sensor thresholds according to the NVM map
3812 * and save off the threshold and location values into mac.thermal_sensor_data
3814 s32
ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw
*hw
)
3820 u8 low_thresh_delta
;
3824 struct ixgbe_thermal_sensor_data
*data
= &hw
->mac
.thermal_sensor_data
;
3826 memset(data
, 0, sizeof(struct ixgbe_thermal_sensor_data
));
3828 /* Only support thermal sensors attached to physical port 0 */
3829 if ((IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_LAN_ID_1
))
3830 return IXGBE_NOT_IMPLEMENTED
;
3832 status
= ixgbe_get_ets_data(hw
, &ets_cfg
, &ets_offset
);
3836 low_thresh_delta
= ((ets_cfg
& IXGBE_ETS_LTHRES_DELTA_MASK
) >>
3837 IXGBE_ETS_LTHRES_DELTA_SHIFT
);
3838 num_sensors
= (ets_cfg
& IXGBE_ETS_NUM_SENSORS_MASK
);
3839 if (num_sensors
> IXGBE_MAX_SENSORS
)
3840 num_sensors
= IXGBE_MAX_SENSORS
;
3842 for (i
= 0; i
< num_sensors
; i
++) {
3846 if (hw
->eeprom
.ops
.read(hw
, ets_offset
+ 1 + i
, &ets_sensor
)) {
3847 hw_err(hw
, "eeprom read at offset %d failed\n",
3848 ets_offset
+ 1 + i
);
3851 sensor_index
= ((ets_sensor
& IXGBE_ETS_DATA_INDEX_MASK
) >>
3852 IXGBE_ETS_DATA_INDEX_SHIFT
);
3853 sensor_location
= ((ets_sensor
& IXGBE_ETS_DATA_LOC_MASK
) >>
3854 IXGBE_ETS_DATA_LOC_SHIFT
);
3855 therm_limit
= ets_sensor
& IXGBE_ETS_DATA_HTHRESH_MASK
;
3857 hw
->phy
.ops
.write_i2c_byte(hw
,
3858 ixgbe_emc_therm_limit
[sensor_index
],
3859 IXGBE_I2C_THERMAL_SENSOR_ADDR
, therm_limit
);
3861 if (sensor_location
== 0)
3864 data
->sensor
[i
].location
= sensor_location
;
3865 data
->sensor
[i
].caution_thresh
= therm_limit
;
3866 data
->sensor
[i
].max_op_thresh
= therm_limit
- low_thresh_delta
;
3872 void ixgbe_disable_rx_generic(struct ixgbe_hw
*hw
)
3876 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3877 if (rxctrl
& IXGBE_RXCTRL_RXEN
) {
3878 if (hw
->mac
.type
!= ixgbe_mac_82598EB
) {
3881 pfdtxgswc
= IXGBE_READ_REG(hw
, IXGBE_PFDTXGSWC
);
3882 if (pfdtxgswc
& IXGBE_PFDTXGSWC_VT_LBEN
) {
3883 pfdtxgswc
&= ~IXGBE_PFDTXGSWC_VT_LBEN
;
3884 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, pfdtxgswc
);
3885 hw
->mac
.set_lben
= true;
3887 hw
->mac
.set_lben
= false;
3890 rxctrl
&= ~IXGBE_RXCTRL_RXEN
;
3891 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
);
3895 void ixgbe_enable_rx_generic(struct ixgbe_hw
*hw
)
3899 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3900 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, (rxctrl
| IXGBE_RXCTRL_RXEN
));
3902 if (hw
->mac
.type
!= ixgbe_mac_82598EB
) {
3903 if (hw
->mac
.set_lben
) {
3906 pfdtxgswc
= IXGBE_READ_REG(hw
, IXGBE_PFDTXGSWC
);
3907 pfdtxgswc
|= IXGBE_PFDTXGSWC_VT_LBEN
;
3908 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, pfdtxgswc
);
3909 hw
->mac
.set_lben
= false;
3914 /** ixgbe_mng_present - returns true when management capability is present
3915 * @hw: pointer to hardware structure
3917 bool ixgbe_mng_present(struct ixgbe_hw
*hw
)
3921 if (hw
->mac
.type
< ixgbe_mac_82599EB
)
3924 fwsm
= IXGBE_READ_REG(hw
, IXGBE_FWSM(hw
));
3925 fwsm
&= IXGBE_FWSM_MODE_MASK
;
3926 return fwsm
== IXGBE_FWSM_FW_MODE_PT
;
3930 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
3931 * @hw: pointer to hardware structure
3932 * @speed: new link speed
3933 * @autoneg_wait_to_complete: true when waiting for completion is needed
3935 * Set the link speed in the MAC and/or PHY register and restarts link.
3937 s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
3938 ixgbe_link_speed speed
,
3939 bool autoneg_wait_to_complete
)
3941 ixgbe_link_speed link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
3942 ixgbe_link_speed highest_link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
3946 bool autoneg
, link_up
= false;
3948 /* Mask off requested but non-supported speeds */
3949 status
= hw
->mac
.ops
.get_link_capabilities(hw
, &link_speed
, &autoneg
);
3953 speed
&= link_speed
;
3955 /* Try each speed one by one, highest priority first. We do this in
3956 * software because 10Gb fiber doesn't support speed autonegotiation.
3958 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
) {
3960 highest_link_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
3962 /* If we already have link at this speed, just jump out */
3963 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
3968 if (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
&& link_up
)
3971 /* Set the module link speed */
3972 switch (hw
->phy
.media_type
) {
3973 case ixgbe_media_type_fiber
:
3974 hw
->mac
.ops
.set_rate_select_speed(hw
,
3975 IXGBE_LINK_SPEED_10GB_FULL
);
3977 case ixgbe_media_type_fiber_qsfp
:
3978 /* QSFP module automatically detects MAC link speed */
3981 hw_dbg(hw
, "Unexpected media type\n");
3985 /* Allow module to change analog characteristics (1G->10G) */
3988 status
= hw
->mac
.ops
.setup_mac_link(hw
,
3989 IXGBE_LINK_SPEED_10GB_FULL
,
3990 autoneg_wait_to_complete
);
3994 /* Flap the Tx laser if it has not already been done */
3995 if (hw
->mac
.ops
.flap_tx_laser
)
3996 hw
->mac
.ops
.flap_tx_laser(hw
);
3998 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
3999 * Section 73.10.2, we may have to wait up to 500ms if KR is
4000 * attempted. 82599 uses the same timing for 10g SFI.
4002 for (i
= 0; i
< 5; i
++) {
4003 /* Wait for the link partner to also set speed */
4006 /* If we have link, just jump out */
4007 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
,
4017 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
) {
4019 if (highest_link_speed
== IXGBE_LINK_SPEED_UNKNOWN
)
4020 highest_link_speed
= IXGBE_LINK_SPEED_1GB_FULL
;
4022 /* If we already have link at this speed, just jump out */
4023 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
4028 if (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
&& link_up
)
4031 /* Set the module link speed */
4032 switch (hw
->phy
.media_type
) {
4033 case ixgbe_media_type_fiber
:
4034 hw
->mac
.ops
.set_rate_select_speed(hw
,
4035 IXGBE_LINK_SPEED_1GB_FULL
);
4037 case ixgbe_media_type_fiber_qsfp
:
4038 /* QSFP module automatically detects link speed */
4041 hw_dbg(hw
, "Unexpected media type\n");
4045 /* Allow module to change analog characteristics (10G->1G) */
4048 status
= hw
->mac
.ops
.setup_mac_link(hw
,
4049 IXGBE_LINK_SPEED_1GB_FULL
,
4050 autoneg_wait_to_complete
);
4054 /* Flap the Tx laser if it has not already been done */
4055 if (hw
->mac
.ops
.flap_tx_laser
)
4056 hw
->mac
.ops
.flap_tx_laser(hw
);
4058 /* Wait for the link partner to also set speed */
4061 /* If we have link, just jump out */
4062 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
4071 /* We didn't get link. Configure back to the highest speed we tried,
4072 * (if there was more than one). We call ourselves back with just the
4073 * single highest speed that the user requested.
4076 status
= ixgbe_setup_mac_link_multispeed_fiber(hw
,
4078 autoneg_wait_to_complete
);
4081 /* Set autoneg_advertised value based on input link speed */
4082 hw
->phy
.autoneg_advertised
= 0;
4084 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
4085 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
4087 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
4088 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
4094 * ixgbe_set_soft_rate_select_speed - Set module link speed
4095 * @hw: pointer to hardware structure
4096 * @speed: link speed to set
4098 * Set module link speed via the soft rate select.
4100 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw
*hw
,
4101 ixgbe_link_speed speed
)
4107 case IXGBE_LINK_SPEED_10GB_FULL
:
4108 /* one bit mask same as setting on */
4109 rs
= IXGBE_SFF_SOFT_RS_SELECT_10G
;
4111 case IXGBE_LINK_SPEED_1GB_FULL
:
4112 rs
= IXGBE_SFF_SOFT_RS_SELECT_1G
;
4115 hw_dbg(hw
, "Invalid fixed module speed\n");
4120 status
= hw
->phy
.ops
.read_i2c_byte(hw
, IXGBE_SFF_SFF_8472_OSCB
,
4121 IXGBE_I2C_EEPROM_DEV_ADDR2
,
4124 hw_dbg(hw
, "Failed to read Rx Rate Select RS0\n");
4128 eeprom_data
= (eeprom_data
& ~IXGBE_SFF_SOFT_RS_SELECT_MASK
) | rs
;
4130 status
= hw
->phy
.ops
.write_i2c_byte(hw
, IXGBE_SFF_SFF_8472_OSCB
,
4131 IXGBE_I2C_EEPROM_DEV_ADDR2
,
4134 hw_dbg(hw
, "Failed to write Rx Rate Select RS0\n");