1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2014 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/pci.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
32 #include <linux/netdevice.h>
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
38 static s32
ixgbe_acquire_eeprom(struct ixgbe_hw
*hw
);
39 static s32
ixgbe_get_eeprom_semaphore(struct ixgbe_hw
*hw
);
40 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw
*hw
);
41 static s32
ixgbe_ready_eeprom(struct ixgbe_hw
*hw
);
42 static void ixgbe_standby_eeprom(struct ixgbe_hw
*hw
);
43 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw
*hw
, u16 data
,
45 static u16
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw
*hw
, u16 count
);
46 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
);
47 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
);
48 static void ixgbe_release_eeprom(struct ixgbe_hw
*hw
);
50 static s32
ixgbe_mta_vector(struct ixgbe_hw
*hw
, u8
*mc_addr
);
51 static s32
ixgbe_poll_eerd_eewr_done(struct ixgbe_hw
*hw
, u32 ee_reg
);
52 static s32
ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw
*hw
, u16 offset
,
53 u16 words
, u16
*data
);
54 static s32
ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw
*hw
, u16 offset
,
55 u16 words
, u16
*data
);
56 static s32
ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw
*hw
,
58 static s32
ixgbe_disable_pcie_master(struct ixgbe_hw
*hw
);
60 /* Base table for registers values that change by MAC */
61 const u32 ixgbe_mvals_8259X
[IXGBE_MVALS_IDX_LIMIT
] = {
62 IXGBE_MVALS_INIT(8259X
)
66 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
68 * @hw: pointer to hardware structure
70 * There are several phys that do not support autoneg flow control. This
71 * function check the device id to see if the associated phy supports
72 * autoneg flow control.
74 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw
*hw
)
76 bool supported
= false;
77 ixgbe_link_speed speed
;
80 switch (hw
->phy
.media_type
) {
81 case ixgbe_media_type_fiber
:
82 hw
->mac
.ops
.check_link(hw
, &speed
, &link_up
, false);
83 /* if link is down, assume supported */
85 supported
= speed
== IXGBE_LINK_SPEED_1GB_FULL
?
90 case ixgbe_media_type_backplane
:
93 case ixgbe_media_type_copper
:
94 /* only some copper devices support flow control autoneg */
95 switch (hw
->device_id
) {
96 case IXGBE_DEV_ID_82599_T3_LOM
:
97 case IXGBE_DEV_ID_X540T
:
98 case IXGBE_DEV_ID_X540T1
:
99 case IXGBE_DEV_ID_X550T
:
100 case IXGBE_DEV_ID_X550EM_X_10G_T
:
114 * ixgbe_setup_fc - Set up flow control
115 * @hw: pointer to hardware structure
117 * Called at init time to set up flow control.
119 static s32
ixgbe_setup_fc(struct ixgbe_hw
*hw
)
122 u32 reg
= 0, reg_bp
= 0;
127 * Validate the requested mode. Strict IEEE mode does not allow
128 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
130 if (hw
->fc
.strict_ieee
&& hw
->fc
.requested_mode
== ixgbe_fc_rx_pause
) {
131 hw_dbg(hw
, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
132 return IXGBE_ERR_INVALID_LINK_SETTINGS
;
136 * 10gig parts do not have a word in the EEPROM to determine the
137 * default flow control setting, so we explicitly set it to full.
139 if (hw
->fc
.requested_mode
== ixgbe_fc_default
)
140 hw
->fc
.requested_mode
= ixgbe_fc_full
;
143 * Set up the 1G and 10G flow control advertisement registers so the
144 * HW will be able to do fc autoneg once the cable is plugged in. If
145 * we link at 10G, the 1G advertisement is harmless and vice versa.
147 switch (hw
->phy
.media_type
) {
148 case ixgbe_media_type_backplane
:
149 /* some MAC's need RMW protection on AUTOC */
150 ret_val
= hw
->mac
.ops
.prot_autoc_read(hw
, &locked
, ®_bp
);
154 /* only backplane uses autoc so fall though */
155 case ixgbe_media_type_fiber
:
156 reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANA
);
159 case ixgbe_media_type_copper
:
160 hw
->phy
.ops
.read_reg(hw
, MDIO_AN_ADVERTISE
,
161 MDIO_MMD_AN
, ®_cu
);
168 * The possible values of fc.requested_mode are:
169 * 0: Flow control is completely disabled
170 * 1: Rx flow control is enabled (we can receive pause frames,
171 * but not send pause frames).
172 * 2: Tx flow control is enabled (we can send pause frames but
173 * we do not support receiving pause frames).
174 * 3: Both Rx and Tx flow control (symmetric) are enabled.
177 switch (hw
->fc
.requested_mode
) {
179 /* Flow control completely disabled by software override. */
180 reg
&= ~(IXGBE_PCS1GANA_SYM_PAUSE
| IXGBE_PCS1GANA_ASM_PAUSE
);
181 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
)
182 reg_bp
&= ~(IXGBE_AUTOC_SYM_PAUSE
|
183 IXGBE_AUTOC_ASM_PAUSE
);
184 else if (hw
->phy
.media_type
== ixgbe_media_type_copper
)
185 reg_cu
&= ~(IXGBE_TAF_SYM_PAUSE
| IXGBE_TAF_ASM_PAUSE
);
187 case ixgbe_fc_tx_pause
:
189 * Tx Flow control is enabled, and Rx Flow control is
190 * disabled by software override.
192 reg
|= IXGBE_PCS1GANA_ASM_PAUSE
;
193 reg
&= ~IXGBE_PCS1GANA_SYM_PAUSE
;
194 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
) {
195 reg_bp
|= IXGBE_AUTOC_ASM_PAUSE
;
196 reg_bp
&= ~IXGBE_AUTOC_SYM_PAUSE
;
197 } else if (hw
->phy
.media_type
== ixgbe_media_type_copper
) {
198 reg_cu
|= IXGBE_TAF_ASM_PAUSE
;
199 reg_cu
&= ~IXGBE_TAF_SYM_PAUSE
;
202 case ixgbe_fc_rx_pause
:
204 * Rx Flow control is enabled and Tx Flow control is
205 * disabled by software override. Since there really
206 * isn't a way to advertise that we are capable of RX
207 * Pause ONLY, we will advertise that we support both
208 * symmetric and asymmetric Rx PAUSE, as such we fall
209 * through to the fc_full statement. Later, we will
210 * disable the adapter's ability to send PAUSE frames.
213 /* Flow control (both Rx and Tx) is enabled by SW override. */
214 reg
|= IXGBE_PCS1GANA_SYM_PAUSE
| IXGBE_PCS1GANA_ASM_PAUSE
;
215 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
)
216 reg_bp
|= IXGBE_AUTOC_SYM_PAUSE
|
217 IXGBE_AUTOC_ASM_PAUSE
;
218 else if (hw
->phy
.media_type
== ixgbe_media_type_copper
)
219 reg_cu
|= IXGBE_TAF_SYM_PAUSE
| IXGBE_TAF_ASM_PAUSE
;
222 hw_dbg(hw
, "Flow control param set incorrectly\n");
223 return IXGBE_ERR_CONFIG
;
226 if (hw
->mac
.type
!= ixgbe_mac_X540
) {
228 * Enable auto-negotiation between the MAC & PHY;
229 * the MAC will advertise clause 37 flow control.
231 IXGBE_WRITE_REG(hw
, IXGBE_PCS1GANA
, reg
);
232 reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GLCTL
);
234 /* Disable AN timeout */
235 if (hw
->fc
.strict_ieee
)
236 reg
&= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN
;
238 IXGBE_WRITE_REG(hw
, IXGBE_PCS1GLCTL
, reg
);
239 hw_dbg(hw
, "Set up FC; PCS1GLCTL = 0x%08X\n", reg
);
243 * AUTOC restart handles negotiation of 1G and 10G on backplane
244 * and copper. There is no need to set the PCS1GCTL register.
247 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
) {
248 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
249 * LESM is on, likewise reset_pipeline requries the lock as
250 * it also writes AUTOC.
252 ret_val
= hw
->mac
.ops
.prot_autoc_write(hw
, reg_bp
, locked
);
256 } else if ((hw
->phy
.media_type
== ixgbe_media_type_copper
) &&
257 ixgbe_device_supports_autoneg_fc(hw
)) {
258 hw
->phy
.ops
.write_reg(hw
, MDIO_AN_ADVERTISE
,
259 MDIO_MMD_AN
, reg_cu
);
262 hw_dbg(hw
, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg
);
267 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
268 * @hw: pointer to hardware structure
270 * Starts the hardware by filling the bus info structure and media type, clears
271 * all on chip counters, initializes receive address registers, multicast
272 * table, VLAN filter table, calls routine to set up link and flow control
273 * settings, and leaves transmit and receive units disabled and uninitialized
275 s32
ixgbe_start_hw_generic(struct ixgbe_hw
*hw
)
280 /* Set the media type */
281 hw
->phy
.media_type
= hw
->mac
.ops
.get_media_type(hw
);
283 /* Identify the PHY */
284 hw
->phy
.ops
.identify(hw
);
286 /* Clear the VLAN filter table */
287 hw
->mac
.ops
.clear_vfta(hw
);
289 /* Clear statistics registers */
290 hw
->mac
.ops
.clear_hw_cntrs(hw
);
292 /* Set No Snoop Disable */
293 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
294 ctrl_ext
|= IXGBE_CTRL_EXT_NS_DIS
;
295 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
296 IXGBE_WRITE_FLUSH(hw
);
298 /* Setup flow control */
299 ret_val
= ixgbe_setup_fc(hw
);
303 /* Clear adapter stopped flag */
304 hw
->adapter_stopped
= false;
310 * ixgbe_start_hw_gen2 - Init sequence for common device family
311 * @hw: pointer to hw structure
313 * Performs the init sequence common to the second generation
315 * Devices in the second generation:
319 s32
ixgbe_start_hw_gen2(struct ixgbe_hw
*hw
)
323 /* Clear the rate limiters */
324 for (i
= 0; i
< hw
->mac
.max_tx_queues
; i
++) {
325 IXGBE_WRITE_REG(hw
, IXGBE_RTTDQSEL
, i
);
326 IXGBE_WRITE_REG(hw
, IXGBE_RTTBCNRC
, 0);
328 IXGBE_WRITE_FLUSH(hw
);
331 /* Disable relaxed ordering */
332 for (i
= 0; i
< hw
->mac
.max_tx_queues
; i
++) {
335 regval
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(i
));
336 regval
&= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN
;
337 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(i
), regval
);
340 for (i
= 0; i
< hw
->mac
.max_rx_queues
; i
++) {
343 regval
= IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(i
));
344 regval
&= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN
|
345 IXGBE_DCA_RXCTRL_HEAD_WRO_EN
);
346 IXGBE_WRITE_REG(hw
, IXGBE_DCA_RXCTRL(i
), regval
);
353 * ixgbe_init_hw_generic - Generic hardware initialization
354 * @hw: pointer to hardware structure
356 * Initialize the hardware by resetting the hardware, filling the bus info
357 * structure and media type, clears all on chip counters, initializes receive
358 * address registers, multicast table, VLAN filter table, calls routine to set
359 * up link and flow control settings, and leaves transmit and receive units
360 * disabled and uninitialized
362 s32
ixgbe_init_hw_generic(struct ixgbe_hw
*hw
)
366 /* Reset the hardware */
367 status
= hw
->mac
.ops
.reset_hw(hw
);
371 status
= hw
->mac
.ops
.start_hw(hw
);
378 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
379 * @hw: pointer to hardware structure
381 * Clears all hardware statistics counters by reading them from the hardware
382 * Statistics counters are clear on read.
384 s32
ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw
*hw
)
388 IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
389 IXGBE_READ_REG(hw
, IXGBE_ILLERRC
);
390 IXGBE_READ_REG(hw
, IXGBE_ERRBC
);
391 IXGBE_READ_REG(hw
, IXGBE_MSPDC
);
392 for (i
= 0; i
< 8; i
++)
393 IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
395 IXGBE_READ_REG(hw
, IXGBE_MLFC
);
396 IXGBE_READ_REG(hw
, IXGBE_MRFC
);
397 IXGBE_READ_REG(hw
, IXGBE_RLEC
);
398 IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
399 IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
400 if (hw
->mac
.type
>= ixgbe_mac_82599EB
) {
401 IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
402 IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
404 IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
405 IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
408 for (i
= 0; i
< 8; i
++) {
409 IXGBE_READ_REG(hw
, IXGBE_PXONTXC(i
));
410 IXGBE_READ_REG(hw
, IXGBE_PXOFFTXC(i
));
411 if (hw
->mac
.type
>= ixgbe_mac_82599EB
) {
412 IXGBE_READ_REG(hw
, IXGBE_PXONRXCNT(i
));
413 IXGBE_READ_REG(hw
, IXGBE_PXOFFRXCNT(i
));
415 IXGBE_READ_REG(hw
, IXGBE_PXONRXC(i
));
416 IXGBE_READ_REG(hw
, IXGBE_PXOFFRXC(i
));
419 if (hw
->mac
.type
>= ixgbe_mac_82599EB
)
420 for (i
= 0; i
< 8; i
++)
421 IXGBE_READ_REG(hw
, IXGBE_PXON2OFFCNT(i
));
422 IXGBE_READ_REG(hw
, IXGBE_PRC64
);
423 IXGBE_READ_REG(hw
, IXGBE_PRC127
);
424 IXGBE_READ_REG(hw
, IXGBE_PRC255
);
425 IXGBE_READ_REG(hw
, IXGBE_PRC511
);
426 IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
427 IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
428 IXGBE_READ_REG(hw
, IXGBE_GPRC
);
429 IXGBE_READ_REG(hw
, IXGBE_BPRC
);
430 IXGBE_READ_REG(hw
, IXGBE_MPRC
);
431 IXGBE_READ_REG(hw
, IXGBE_GPTC
);
432 IXGBE_READ_REG(hw
, IXGBE_GORCL
);
433 IXGBE_READ_REG(hw
, IXGBE_GORCH
);
434 IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
435 IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
436 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
437 for (i
= 0; i
< 8; i
++)
438 IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
439 IXGBE_READ_REG(hw
, IXGBE_RUC
);
440 IXGBE_READ_REG(hw
, IXGBE_RFC
);
441 IXGBE_READ_REG(hw
, IXGBE_ROC
);
442 IXGBE_READ_REG(hw
, IXGBE_RJC
);
443 IXGBE_READ_REG(hw
, IXGBE_MNGPRC
);
444 IXGBE_READ_REG(hw
, IXGBE_MNGPDC
);
445 IXGBE_READ_REG(hw
, IXGBE_MNGPTC
);
446 IXGBE_READ_REG(hw
, IXGBE_TORL
);
447 IXGBE_READ_REG(hw
, IXGBE_TORH
);
448 IXGBE_READ_REG(hw
, IXGBE_TPR
);
449 IXGBE_READ_REG(hw
, IXGBE_TPT
);
450 IXGBE_READ_REG(hw
, IXGBE_PTC64
);
451 IXGBE_READ_REG(hw
, IXGBE_PTC127
);
452 IXGBE_READ_REG(hw
, IXGBE_PTC255
);
453 IXGBE_READ_REG(hw
, IXGBE_PTC511
);
454 IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
455 IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
456 IXGBE_READ_REG(hw
, IXGBE_MPTC
);
457 IXGBE_READ_REG(hw
, IXGBE_BPTC
);
458 for (i
= 0; i
< 16; i
++) {
459 IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
460 IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
461 if (hw
->mac
.type
>= ixgbe_mac_82599EB
) {
462 IXGBE_READ_REG(hw
, IXGBE_QBRC_L(i
));
463 IXGBE_READ_REG(hw
, IXGBE_QBRC_H(i
));
464 IXGBE_READ_REG(hw
, IXGBE_QBTC_L(i
));
465 IXGBE_READ_REG(hw
, IXGBE_QBTC_H(i
));
466 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
468 IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
469 IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
473 if (hw
->mac
.type
== ixgbe_mac_X550
|| hw
->mac
.type
== ixgbe_mac_X540
) {
475 hw
->phy
.ops
.identify(hw
);
476 hw
->phy
.ops
.read_reg(hw
, IXGBE_PCRC8ECL
, MDIO_MMD_PCS
, &i
);
477 hw
->phy
.ops
.read_reg(hw
, IXGBE_PCRC8ECH
, MDIO_MMD_PCS
, &i
);
478 hw
->phy
.ops
.read_reg(hw
, IXGBE_LDPCECL
, MDIO_MMD_PCS
, &i
);
479 hw
->phy
.ops
.read_reg(hw
, IXGBE_LDPCECH
, MDIO_MMD_PCS
, &i
);
486 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
487 * @hw: pointer to hardware structure
488 * @pba_num: stores the part number string from the EEPROM
489 * @pba_num_size: part number string buffer length
491 * Reads the part number string from the EEPROM.
493 s32
ixgbe_read_pba_string_generic(struct ixgbe_hw
*hw
, u8
*pba_num
,
502 if (pba_num
== NULL
) {
503 hw_dbg(hw
, "PBA string buffer was null\n");
504 return IXGBE_ERR_INVALID_ARGUMENT
;
507 ret_val
= hw
->eeprom
.ops
.read(hw
, IXGBE_PBANUM0_PTR
, &data
);
509 hw_dbg(hw
, "NVM Read Error\n");
513 ret_val
= hw
->eeprom
.ops
.read(hw
, IXGBE_PBANUM1_PTR
, &pba_ptr
);
515 hw_dbg(hw
, "NVM Read Error\n");
520 * if data is not ptr guard the PBA must be in legacy format which
521 * means pba_ptr is actually our second data word for the PBA number
522 * and we can decode it into an ascii string
524 if (data
!= IXGBE_PBANUM_PTR_GUARD
) {
525 hw_dbg(hw
, "NVM PBA number is not stored as string\n");
527 /* we will need 11 characters to store the PBA */
528 if (pba_num_size
< 11) {
529 hw_dbg(hw
, "PBA string buffer too small\n");
530 return IXGBE_ERR_NO_SPACE
;
533 /* extract hex string from data and pba_ptr */
534 pba_num
[0] = (data
>> 12) & 0xF;
535 pba_num
[1] = (data
>> 8) & 0xF;
536 pba_num
[2] = (data
>> 4) & 0xF;
537 pba_num
[3] = data
& 0xF;
538 pba_num
[4] = (pba_ptr
>> 12) & 0xF;
539 pba_num
[5] = (pba_ptr
>> 8) & 0xF;
542 pba_num
[8] = (pba_ptr
>> 4) & 0xF;
543 pba_num
[9] = pba_ptr
& 0xF;
545 /* put a null character on the end of our string */
548 /* switch all the data but the '-' to hex char */
549 for (offset
= 0; offset
< 10; offset
++) {
550 if (pba_num
[offset
] < 0xA)
551 pba_num
[offset
] += '0';
552 else if (pba_num
[offset
] < 0x10)
553 pba_num
[offset
] += 'A' - 0xA;
559 ret_val
= hw
->eeprom
.ops
.read(hw
, pba_ptr
, &length
);
561 hw_dbg(hw
, "NVM Read Error\n");
565 if (length
== 0xFFFF || length
== 0) {
566 hw_dbg(hw
, "NVM PBA number section invalid length\n");
567 return IXGBE_ERR_PBA_SECTION
;
570 /* check if pba_num buffer is big enough */
571 if (pba_num_size
< (((u32
)length
* 2) - 1)) {
572 hw_dbg(hw
, "PBA string buffer too small\n");
573 return IXGBE_ERR_NO_SPACE
;
576 /* trim pba length from start of string */
580 for (offset
= 0; offset
< length
; offset
++) {
581 ret_val
= hw
->eeprom
.ops
.read(hw
, pba_ptr
+ offset
, &data
);
583 hw_dbg(hw
, "NVM Read Error\n");
586 pba_num
[offset
* 2] = (u8
)(data
>> 8);
587 pba_num
[(offset
* 2) + 1] = (u8
)(data
& 0xFF);
589 pba_num
[offset
* 2] = '\0';
595 * ixgbe_get_mac_addr_generic - Generic get MAC address
596 * @hw: pointer to hardware structure
597 * @mac_addr: Adapter MAC address
599 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
600 * A reset of the adapter must be performed prior to calling this function
601 * in order for the MAC address to have been loaded from the EEPROM into RAR0
603 s32
ixgbe_get_mac_addr_generic(struct ixgbe_hw
*hw
, u8
*mac_addr
)
609 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(0));
610 rar_low
= IXGBE_READ_REG(hw
, IXGBE_RAL(0));
612 for (i
= 0; i
< 4; i
++)
613 mac_addr
[i
] = (u8
)(rar_low
>> (i
*8));
615 for (i
= 0; i
< 2; i
++)
616 mac_addr
[i
+4] = (u8
)(rar_high
>> (i
*8));
621 enum ixgbe_bus_width
ixgbe_convert_bus_width(u16 link_status
)
623 switch (link_status
& IXGBE_PCI_LINK_WIDTH
) {
624 case IXGBE_PCI_LINK_WIDTH_1
:
625 return ixgbe_bus_width_pcie_x1
;
626 case IXGBE_PCI_LINK_WIDTH_2
:
627 return ixgbe_bus_width_pcie_x2
;
628 case IXGBE_PCI_LINK_WIDTH_4
:
629 return ixgbe_bus_width_pcie_x4
;
630 case IXGBE_PCI_LINK_WIDTH_8
:
631 return ixgbe_bus_width_pcie_x8
;
633 return ixgbe_bus_width_unknown
;
637 enum ixgbe_bus_speed
ixgbe_convert_bus_speed(u16 link_status
)
639 switch (link_status
& IXGBE_PCI_LINK_SPEED
) {
640 case IXGBE_PCI_LINK_SPEED_2500
:
641 return ixgbe_bus_speed_2500
;
642 case IXGBE_PCI_LINK_SPEED_5000
:
643 return ixgbe_bus_speed_5000
;
644 case IXGBE_PCI_LINK_SPEED_8000
:
645 return ixgbe_bus_speed_8000
;
647 return ixgbe_bus_speed_unknown
;
652 * ixgbe_get_bus_info_generic - Generic set PCI bus info
653 * @hw: pointer to hardware structure
655 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
657 s32
ixgbe_get_bus_info_generic(struct ixgbe_hw
*hw
)
661 hw
->bus
.type
= ixgbe_bus_type_pci_express
;
663 /* Get the negotiated link width and speed from PCI config space */
664 link_status
= ixgbe_read_pci_cfg_word(hw
, IXGBE_PCI_LINK_STATUS
);
666 hw
->bus
.width
= ixgbe_convert_bus_width(link_status
);
667 hw
->bus
.speed
= ixgbe_convert_bus_speed(link_status
);
669 hw
->mac
.ops
.set_lan_id(hw
);
675 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
676 * @hw: pointer to the HW structure
678 * Determines the LAN function id by reading memory-mapped registers
679 * and swaps the port value if requested.
681 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw
*hw
)
683 struct ixgbe_bus_info
*bus
= &hw
->bus
;
686 reg
= IXGBE_READ_REG(hw
, IXGBE_STATUS
);
687 bus
->func
= (reg
& IXGBE_STATUS_LAN_ID
) >> IXGBE_STATUS_LAN_ID_SHIFT
;
688 bus
->lan_id
= bus
->func
;
690 /* check for a port swap */
691 reg
= IXGBE_READ_REG(hw
, IXGBE_FACTPS(hw
));
692 if (reg
& IXGBE_FACTPS_LFS
)
697 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
698 * @hw: pointer to hardware structure
700 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
701 * disables transmit and receive units. The adapter_stopped flag is used by
702 * the shared code and drivers to determine if the adapter is in a stopped
703 * state and should not touch the hardware.
705 s32
ixgbe_stop_adapter_generic(struct ixgbe_hw
*hw
)
711 * Set the adapter_stopped flag so other driver functions stop touching
714 hw
->adapter_stopped
= true;
716 /* Disable the receive unit */
717 hw
->mac
.ops
.disable_rx(hw
);
719 /* Clear interrupt mask to stop interrupts from being generated */
720 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
722 /* Clear any pending interrupts, flush previous writes */
723 IXGBE_READ_REG(hw
, IXGBE_EICR
);
725 /* Disable the transmit unit. Each queue must be disabled. */
726 for (i
= 0; i
< hw
->mac
.max_tx_queues
; i
++)
727 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(i
), IXGBE_TXDCTL_SWFLSH
);
729 /* Disable the receive unit by stopping each queue */
730 for (i
= 0; i
< hw
->mac
.max_rx_queues
; i
++) {
731 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
732 reg_val
&= ~IXGBE_RXDCTL_ENABLE
;
733 reg_val
|= IXGBE_RXDCTL_SWFLSH
;
734 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(i
), reg_val
);
737 /* flush all queues disables */
738 IXGBE_WRITE_FLUSH(hw
);
739 usleep_range(1000, 2000);
742 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
743 * access and verify no pending requests
745 return ixgbe_disable_pcie_master(hw
);
749 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
750 * @hw: pointer to hardware structure
751 * @index: led number to turn on
753 s32
ixgbe_led_on_generic(struct ixgbe_hw
*hw
, u32 index
)
755 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
757 /* To turn on the LED, set mode to ON. */
758 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
759 led_reg
|= IXGBE_LED_ON
<< IXGBE_LED_MODE_SHIFT(index
);
760 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
761 IXGBE_WRITE_FLUSH(hw
);
767 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
768 * @hw: pointer to hardware structure
769 * @index: led number to turn off
771 s32
ixgbe_led_off_generic(struct ixgbe_hw
*hw
, u32 index
)
773 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
775 /* To turn off the LED, set mode to OFF. */
776 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
777 led_reg
|= IXGBE_LED_OFF
<< IXGBE_LED_MODE_SHIFT(index
);
778 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
779 IXGBE_WRITE_FLUSH(hw
);
785 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
786 * @hw: pointer to hardware structure
788 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
789 * ixgbe_hw struct in order to set up EEPROM access.
791 s32
ixgbe_init_eeprom_params_generic(struct ixgbe_hw
*hw
)
793 struct ixgbe_eeprom_info
*eeprom
= &hw
->eeprom
;
797 if (eeprom
->type
== ixgbe_eeprom_uninitialized
) {
798 eeprom
->type
= ixgbe_eeprom_none
;
799 /* Set default semaphore delay to 10ms which is a well
801 eeprom
->semaphore_delay
= 10;
802 /* Clear EEPROM page size, it will be initialized as needed */
803 eeprom
->word_page_size
= 0;
806 * Check for EEPROM present first.
807 * If not present leave as none
809 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC(hw
));
810 if (eec
& IXGBE_EEC_PRES
) {
811 eeprom
->type
= ixgbe_eeprom_spi
;
814 * SPI EEPROM is assumed here. This code would need to
815 * change if a future EEPROM is not SPI.
817 eeprom_size
= (u16
)((eec
& IXGBE_EEC_SIZE
) >>
818 IXGBE_EEC_SIZE_SHIFT
);
819 eeprom
->word_size
= 1 << (eeprom_size
+
820 IXGBE_EEPROM_WORD_SIZE_SHIFT
);
823 if (eec
& IXGBE_EEC_ADDR_SIZE
)
824 eeprom
->address_bits
= 16;
826 eeprom
->address_bits
= 8;
827 hw_dbg(hw
, "Eeprom params: type = %d, size = %d, address bits: %d\n",
828 eeprom
->type
, eeprom
->word_size
, eeprom
->address_bits
);
835 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
836 * @hw: pointer to hardware structure
837 * @offset: offset within the EEPROM to write
838 * @words: number of words
839 * @data: 16 bit word(s) to write to EEPROM
841 * Reads 16 bit word(s) from EEPROM through bit-bang method
843 s32
ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw
*hw
, u16 offset
,
844 u16 words
, u16
*data
)
849 hw
->eeprom
.ops
.init_params(hw
);
852 return IXGBE_ERR_INVALID_ARGUMENT
;
854 if (offset
+ words
> hw
->eeprom
.word_size
)
855 return IXGBE_ERR_EEPROM
;
858 * The EEPROM page size cannot be queried from the chip. We do lazy
859 * initialization. It is worth to do that when we write large buffer.
861 if ((hw
->eeprom
.word_page_size
== 0) &&
862 (words
> IXGBE_EEPROM_PAGE_SIZE_MAX
))
863 ixgbe_detect_eeprom_page_size_generic(hw
, offset
);
866 * We cannot hold synchronization semaphores for too long
867 * to avoid other entity starvation. However it is more efficient
868 * to read in bursts than synchronizing access for each word.
870 for (i
= 0; i
< words
; i
+= IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
) {
871 count
= (words
- i
) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
> 0 ?
872 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
: (words
- i
);
873 status
= ixgbe_write_eeprom_buffer_bit_bang(hw
, offset
+ i
,
884 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
885 * @hw: pointer to hardware structure
886 * @offset: offset within the EEPROM to be written to
887 * @words: number of word(s)
888 * @data: 16 bit word(s) to be written to the EEPROM
890 * If ixgbe_eeprom_update_checksum is not called after this function, the
891 * EEPROM will most likely contain an invalid checksum.
893 static s32
ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw
*hw
, u16 offset
,
894 u16 words
, u16
*data
)
900 u8 write_opcode
= IXGBE_EEPROM_WRITE_OPCODE_SPI
;
902 /* Prepare the EEPROM for writing */
903 status
= ixgbe_acquire_eeprom(hw
);
907 if (ixgbe_ready_eeprom(hw
) != 0) {
908 ixgbe_release_eeprom(hw
);
909 return IXGBE_ERR_EEPROM
;
912 for (i
= 0; i
< words
; i
++) {
913 ixgbe_standby_eeprom(hw
);
915 /* Send the WRITE ENABLE command (8 bit opcode) */
916 ixgbe_shift_out_eeprom_bits(hw
,
917 IXGBE_EEPROM_WREN_OPCODE_SPI
,
918 IXGBE_EEPROM_OPCODE_BITS
);
920 ixgbe_standby_eeprom(hw
);
922 /* Some SPI eeproms use the 8th address bit embedded
925 if ((hw
->eeprom
.address_bits
== 8) &&
926 ((offset
+ i
) >= 128))
927 write_opcode
|= IXGBE_EEPROM_A8_OPCODE_SPI
;
929 /* Send the Write command (8-bit opcode + addr) */
930 ixgbe_shift_out_eeprom_bits(hw
, write_opcode
,
931 IXGBE_EEPROM_OPCODE_BITS
);
932 ixgbe_shift_out_eeprom_bits(hw
, (u16
)((offset
+ i
) * 2),
933 hw
->eeprom
.address_bits
);
935 page_size
= hw
->eeprom
.word_page_size
;
937 /* Send the data in burst via SPI */
940 word
= (word
>> 8) | (word
<< 8);
941 ixgbe_shift_out_eeprom_bits(hw
, word
, 16);
946 /* do not wrap around page */
947 if (((offset
+ i
) & (page_size
- 1)) ==
950 } while (++i
< words
);
952 ixgbe_standby_eeprom(hw
);
953 usleep_range(10000, 20000);
955 /* Done with writing - release the EEPROM */
956 ixgbe_release_eeprom(hw
);
962 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
963 * @hw: pointer to hardware structure
964 * @offset: offset within the EEPROM to be written to
965 * @data: 16 bit word to be written to the EEPROM
967 * If ixgbe_eeprom_update_checksum is not called after this function, the
968 * EEPROM will most likely contain an invalid checksum.
970 s32
ixgbe_write_eeprom_generic(struct ixgbe_hw
*hw
, u16 offset
, u16 data
)
972 hw
->eeprom
.ops
.init_params(hw
);
974 if (offset
>= hw
->eeprom
.word_size
)
975 return IXGBE_ERR_EEPROM
;
977 return ixgbe_write_eeprom_buffer_bit_bang(hw
, offset
, 1, &data
);
981 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
982 * @hw: pointer to hardware structure
983 * @offset: offset within the EEPROM to be read
984 * @words: number of word(s)
985 * @data: read 16 bit words(s) from EEPROM
987 * Reads 16 bit word(s) from EEPROM through bit-bang method
989 s32
ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw
*hw
, u16 offset
,
990 u16 words
, u16
*data
)
995 hw
->eeprom
.ops
.init_params(hw
);
998 return IXGBE_ERR_INVALID_ARGUMENT
;
1000 if (offset
+ words
> hw
->eeprom
.word_size
)
1001 return IXGBE_ERR_EEPROM
;
1004 * We cannot hold synchronization semaphores for too long
1005 * to avoid other entity starvation. However it is more efficient
1006 * to read in bursts than synchronizing access for each word.
1008 for (i
= 0; i
< words
; i
+= IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
) {
1009 count
= (words
- i
) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
> 0 ?
1010 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
: (words
- i
);
1012 status
= ixgbe_read_eeprom_buffer_bit_bang(hw
, offset
+ i
,
1023 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1024 * @hw: pointer to hardware structure
1025 * @offset: offset within the EEPROM to be read
1026 * @words: number of word(s)
1027 * @data: read 16 bit word(s) from EEPROM
1029 * Reads 16 bit word(s) from EEPROM through bit-bang method
1031 static s32
ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw
*hw
, u16 offset
,
1032 u16 words
, u16
*data
)
1036 u8 read_opcode
= IXGBE_EEPROM_READ_OPCODE_SPI
;
1039 /* Prepare the EEPROM for reading */
1040 status
= ixgbe_acquire_eeprom(hw
);
1044 if (ixgbe_ready_eeprom(hw
) != 0) {
1045 ixgbe_release_eeprom(hw
);
1046 return IXGBE_ERR_EEPROM
;
1049 for (i
= 0; i
< words
; i
++) {
1050 ixgbe_standby_eeprom(hw
);
1051 /* Some SPI eeproms use the 8th address bit embedded
1054 if ((hw
->eeprom
.address_bits
== 8) &&
1055 ((offset
+ i
) >= 128))
1056 read_opcode
|= IXGBE_EEPROM_A8_OPCODE_SPI
;
1058 /* Send the READ command (opcode + addr) */
1059 ixgbe_shift_out_eeprom_bits(hw
, read_opcode
,
1060 IXGBE_EEPROM_OPCODE_BITS
);
1061 ixgbe_shift_out_eeprom_bits(hw
, (u16
)((offset
+ i
) * 2),
1062 hw
->eeprom
.address_bits
);
1064 /* Read the data. */
1065 word_in
= ixgbe_shift_in_eeprom_bits(hw
, 16);
1066 data
[i
] = (word_in
>> 8) | (word_in
<< 8);
1069 /* End this read operation */
1070 ixgbe_release_eeprom(hw
);
1076 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1077 * @hw: pointer to hardware structure
1078 * @offset: offset within the EEPROM to be read
1079 * @data: read 16 bit value from EEPROM
1081 * Reads 16 bit value from EEPROM through bit-bang method
1083 s32
ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw
*hw
, u16 offset
,
1086 hw
->eeprom
.ops
.init_params(hw
);
1088 if (offset
>= hw
->eeprom
.word_size
)
1089 return IXGBE_ERR_EEPROM
;
1091 return ixgbe_read_eeprom_buffer_bit_bang(hw
, offset
, 1, data
);
1095 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1096 * @hw: pointer to hardware structure
1097 * @offset: offset of word in the EEPROM to read
1098 * @words: number of word(s)
1099 * @data: 16 bit word(s) from the EEPROM
1101 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1103 s32
ixgbe_read_eerd_buffer_generic(struct ixgbe_hw
*hw
, u16 offset
,
1104 u16 words
, u16
*data
)
1110 hw
->eeprom
.ops
.init_params(hw
);
1113 return IXGBE_ERR_INVALID_ARGUMENT
;
1115 if (offset
>= hw
->eeprom
.word_size
)
1116 return IXGBE_ERR_EEPROM
;
1118 for (i
= 0; i
< words
; i
++) {
1119 eerd
= ((offset
+ i
) << IXGBE_EEPROM_RW_ADDR_SHIFT
) |
1120 IXGBE_EEPROM_RW_REG_START
;
1122 IXGBE_WRITE_REG(hw
, IXGBE_EERD
, eerd
);
1123 status
= ixgbe_poll_eerd_eewr_done(hw
, IXGBE_NVM_POLL_READ
);
1126 data
[i
] = (IXGBE_READ_REG(hw
, IXGBE_EERD
) >>
1127 IXGBE_EEPROM_RW_REG_DATA
);
1129 hw_dbg(hw
, "Eeprom read timed out\n");
1138 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1139 * @hw: pointer to hardware structure
1140 * @offset: offset within the EEPROM to be used as a scratch pad
1142 * Discover EEPROM page size by writing marching data at given offset.
1143 * This function is called only when we are writing a new large buffer
1144 * at given offset so the data would be overwritten anyway.
1146 static s32
ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw
*hw
,
1149 u16 data
[IXGBE_EEPROM_PAGE_SIZE_MAX
];
1153 for (i
= 0; i
< IXGBE_EEPROM_PAGE_SIZE_MAX
; i
++)
1156 hw
->eeprom
.word_page_size
= IXGBE_EEPROM_PAGE_SIZE_MAX
;
1157 status
= ixgbe_write_eeprom_buffer_bit_bang(hw
, offset
,
1158 IXGBE_EEPROM_PAGE_SIZE_MAX
, data
);
1159 hw
->eeprom
.word_page_size
= 0;
1163 status
= ixgbe_read_eeprom_buffer_bit_bang(hw
, offset
, 1, data
);
1168 * When writing in burst more than the actual page size
1169 * EEPROM address wraps around current page.
1171 hw
->eeprom
.word_page_size
= IXGBE_EEPROM_PAGE_SIZE_MAX
- data
[0];
1173 hw_dbg(hw
, "Detected EEPROM page size = %d words.\n",
1174 hw
->eeprom
.word_page_size
);
1179 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1180 * @hw: pointer to hardware structure
1181 * @offset: offset of word in the EEPROM to read
1182 * @data: word read from the EEPROM
1184 * Reads a 16 bit word from the EEPROM using the EERD register.
1186 s32
ixgbe_read_eerd_generic(struct ixgbe_hw
*hw
, u16 offset
, u16
*data
)
1188 return ixgbe_read_eerd_buffer_generic(hw
, offset
, 1, data
);
1192 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1193 * @hw: pointer to hardware structure
1194 * @offset: offset of word in the EEPROM to write
1195 * @words: number of words
1196 * @data: word(s) write to the EEPROM
1198 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1200 s32
ixgbe_write_eewr_buffer_generic(struct ixgbe_hw
*hw
, u16 offset
,
1201 u16 words
, u16
*data
)
1207 hw
->eeprom
.ops
.init_params(hw
);
1210 return IXGBE_ERR_INVALID_ARGUMENT
;
1212 if (offset
>= hw
->eeprom
.word_size
)
1213 return IXGBE_ERR_EEPROM
;
1215 for (i
= 0; i
< words
; i
++) {
1216 eewr
= ((offset
+ i
) << IXGBE_EEPROM_RW_ADDR_SHIFT
) |
1217 (data
[i
] << IXGBE_EEPROM_RW_REG_DATA
) |
1218 IXGBE_EEPROM_RW_REG_START
;
1220 status
= ixgbe_poll_eerd_eewr_done(hw
, IXGBE_NVM_POLL_WRITE
);
1222 hw_dbg(hw
, "Eeprom write EEWR timed out\n");
1226 IXGBE_WRITE_REG(hw
, IXGBE_EEWR
, eewr
);
1228 status
= ixgbe_poll_eerd_eewr_done(hw
, IXGBE_NVM_POLL_WRITE
);
1230 hw_dbg(hw
, "Eeprom write EEWR timed out\n");
1239 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1240 * @hw: pointer to hardware structure
1241 * @offset: offset of word in the EEPROM to write
1242 * @data: word write to the EEPROM
1244 * Write a 16 bit word to the EEPROM using the EEWR register.
1246 s32
ixgbe_write_eewr_generic(struct ixgbe_hw
*hw
, u16 offset
, u16 data
)
1248 return ixgbe_write_eewr_buffer_generic(hw
, offset
, 1, &data
);
1252 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1253 * @hw: pointer to hardware structure
1254 * @ee_reg: EEPROM flag for polling
1256 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1257 * read or write is done respectively.
1259 static s32
ixgbe_poll_eerd_eewr_done(struct ixgbe_hw
*hw
, u32 ee_reg
)
1264 for (i
= 0; i
< IXGBE_EERD_EEWR_ATTEMPTS
; i
++) {
1265 if (ee_reg
== IXGBE_NVM_POLL_READ
)
1266 reg
= IXGBE_READ_REG(hw
, IXGBE_EERD
);
1268 reg
= IXGBE_READ_REG(hw
, IXGBE_EEWR
);
1270 if (reg
& IXGBE_EEPROM_RW_REG_DONE
) {
1275 return IXGBE_ERR_EEPROM
;
1279 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1280 * @hw: pointer to hardware structure
1282 * Prepares EEPROM for access using bit-bang method. This function should
1283 * be called before issuing a command to the EEPROM.
1285 static s32
ixgbe_acquire_eeprom(struct ixgbe_hw
*hw
)
1290 if (hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
) != 0)
1291 return IXGBE_ERR_SWFW_SYNC
;
1293 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC(hw
));
1295 /* Request EEPROM Access */
1296 eec
|= IXGBE_EEC_REQ
;
1297 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), eec
);
1299 for (i
= 0; i
< IXGBE_EEPROM_GRANT_ATTEMPTS
; i
++) {
1300 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC(hw
));
1301 if (eec
& IXGBE_EEC_GNT
)
1306 /* Release if grant not acquired */
1307 if (!(eec
& IXGBE_EEC_GNT
)) {
1308 eec
&= ~IXGBE_EEC_REQ
;
1309 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), eec
);
1310 hw_dbg(hw
, "Could not acquire EEPROM grant\n");
1312 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
1313 return IXGBE_ERR_EEPROM
;
1316 /* Setup EEPROM for Read/Write */
1317 /* Clear CS and SK */
1318 eec
&= ~(IXGBE_EEC_CS
| IXGBE_EEC_SK
);
1319 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), eec
);
1320 IXGBE_WRITE_FLUSH(hw
);
1326 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1327 * @hw: pointer to hardware structure
1329 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1331 static s32
ixgbe_get_eeprom_semaphore(struct ixgbe_hw
*hw
)
1337 /* Get SMBI software semaphore between device drivers first */
1338 for (i
= 0; i
< timeout
; i
++) {
1340 * If the SMBI bit is 0 when we read it, then the bit will be
1341 * set and we have the semaphore
1343 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM(hw
));
1344 if (!(swsm
& IXGBE_SWSM_SMBI
))
1346 usleep_range(50, 100);
1350 hw_dbg(hw
, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n");
1351 /* this release is particularly important because our attempts
1352 * above to get the semaphore may have succeeded, and if there
1353 * was a timeout, we should unconditionally clear the semaphore
1354 * bits to free the driver to make progress
1356 ixgbe_release_eeprom_semaphore(hw
);
1358 usleep_range(50, 100);
1360 * If the SMBI bit is 0 when we read it, then the bit will be
1361 * set and we have the semaphore
1363 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM(hw
));
1364 if (swsm
& IXGBE_SWSM_SMBI
) {
1365 hw_dbg(hw
, "Software semaphore SMBI between device drivers not granted.\n");
1366 return IXGBE_ERR_EEPROM
;
1370 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1371 for (i
= 0; i
< timeout
; i
++) {
1372 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM(hw
));
1374 /* Set the SW EEPROM semaphore bit to request access */
1375 swsm
|= IXGBE_SWSM_SWESMBI
;
1376 IXGBE_WRITE_REG(hw
, IXGBE_SWSM(hw
), swsm
);
1378 /* If we set the bit successfully then we got the
1381 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM(hw
));
1382 if (swsm
& IXGBE_SWSM_SWESMBI
)
1385 usleep_range(50, 100);
1388 /* Release semaphores and return error if SW EEPROM semaphore
1389 * was not granted because we don't have access to the EEPROM
1392 hw_dbg(hw
, "SWESMBI Software EEPROM semaphore not granted.\n");
1393 ixgbe_release_eeprom_semaphore(hw
);
1394 return IXGBE_ERR_EEPROM
;
1401 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1402 * @hw: pointer to hardware structure
1404 * This function clears hardware semaphore bits.
1406 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw
*hw
)
1410 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM(hw
));
1412 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1413 swsm
&= ~(IXGBE_SWSM_SWESMBI
| IXGBE_SWSM_SMBI
);
1414 IXGBE_WRITE_REG(hw
, IXGBE_SWSM(hw
), swsm
);
1415 IXGBE_WRITE_FLUSH(hw
);
1419 * ixgbe_ready_eeprom - Polls for EEPROM ready
1420 * @hw: pointer to hardware structure
1422 static s32
ixgbe_ready_eeprom(struct ixgbe_hw
*hw
)
1428 * Read "Status Register" repeatedly until the LSB is cleared. The
1429 * EEPROM will signal that the command has been completed by clearing
1430 * bit 0 of the internal status register. If it's not cleared within
1431 * 5 milliseconds, then error out.
1433 for (i
= 0; i
< IXGBE_EEPROM_MAX_RETRY_SPI
; i
+= 5) {
1434 ixgbe_shift_out_eeprom_bits(hw
, IXGBE_EEPROM_RDSR_OPCODE_SPI
,
1435 IXGBE_EEPROM_OPCODE_BITS
);
1436 spi_stat_reg
= (u8
)ixgbe_shift_in_eeprom_bits(hw
, 8);
1437 if (!(spi_stat_reg
& IXGBE_EEPROM_STATUS_RDY_SPI
))
1441 ixgbe_standby_eeprom(hw
);
1445 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1446 * devices (and only 0-5mSec on 5V devices)
1448 if (i
>= IXGBE_EEPROM_MAX_RETRY_SPI
) {
1449 hw_dbg(hw
, "SPI EEPROM Status error\n");
1450 return IXGBE_ERR_EEPROM
;
1457 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1458 * @hw: pointer to hardware structure
1460 static void ixgbe_standby_eeprom(struct ixgbe_hw
*hw
)
1464 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC(hw
));
1466 /* Toggle CS to flush commands */
1467 eec
|= IXGBE_EEC_CS
;
1468 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), eec
);
1469 IXGBE_WRITE_FLUSH(hw
);
1471 eec
&= ~IXGBE_EEC_CS
;
1472 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), eec
);
1473 IXGBE_WRITE_FLUSH(hw
);
1478 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1479 * @hw: pointer to hardware structure
1480 * @data: data to send to the EEPROM
1481 * @count: number of bits to shift out
1483 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw
*hw
, u16 data
,
1490 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC(hw
));
1493 * Mask is used to shift "count" bits of "data" out to the EEPROM
1494 * one bit at a time. Determine the starting bit based on count
1496 mask
= 0x01 << (count
- 1);
1498 for (i
= 0; i
< count
; i
++) {
1500 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1501 * "1", and then raising and then lowering the clock (the SK
1502 * bit controls the clock input to the EEPROM). A "0" is
1503 * shifted out to the EEPROM by setting "DI" to "0" and then
1504 * raising and then lowering the clock.
1507 eec
|= IXGBE_EEC_DI
;
1509 eec
&= ~IXGBE_EEC_DI
;
1511 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), eec
);
1512 IXGBE_WRITE_FLUSH(hw
);
1516 ixgbe_raise_eeprom_clk(hw
, &eec
);
1517 ixgbe_lower_eeprom_clk(hw
, &eec
);
1520 * Shift mask to signify next bit of data to shift in to the
1526 /* We leave the "DI" bit set to "0" when we leave this routine. */
1527 eec
&= ~IXGBE_EEC_DI
;
1528 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), eec
);
1529 IXGBE_WRITE_FLUSH(hw
);
1533 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1534 * @hw: pointer to hardware structure
1536 static u16
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw
*hw
, u16 count
)
1543 * In order to read a register from the EEPROM, we need to shift
1544 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1545 * the clock input to the EEPROM (setting the SK bit), and then reading
1546 * the value of the "DO" bit. During this "shifting in" process the
1547 * "DI" bit should always be clear.
1549 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC(hw
));
1551 eec
&= ~(IXGBE_EEC_DO
| IXGBE_EEC_DI
);
1553 for (i
= 0; i
< count
; i
++) {
1555 ixgbe_raise_eeprom_clk(hw
, &eec
);
1557 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC(hw
));
1559 eec
&= ~(IXGBE_EEC_DI
);
1560 if (eec
& IXGBE_EEC_DO
)
1563 ixgbe_lower_eeprom_clk(hw
, &eec
);
1570 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1571 * @hw: pointer to hardware structure
1572 * @eec: EEC register's current value
1574 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
)
1577 * Raise the clock input to the EEPROM
1578 * (setting the SK bit), then delay
1580 *eec
= *eec
| IXGBE_EEC_SK
;
1581 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), *eec
);
1582 IXGBE_WRITE_FLUSH(hw
);
1587 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1588 * @hw: pointer to hardware structure
1589 * @eecd: EECD's current value
1591 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
)
1594 * Lower the clock input to the EEPROM (clearing the SK bit), then
1597 *eec
= *eec
& ~IXGBE_EEC_SK
;
1598 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), *eec
);
1599 IXGBE_WRITE_FLUSH(hw
);
1604 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1605 * @hw: pointer to hardware structure
1607 static void ixgbe_release_eeprom(struct ixgbe_hw
*hw
)
1611 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC(hw
));
1613 eec
|= IXGBE_EEC_CS
; /* Pull CS high */
1614 eec
&= ~IXGBE_EEC_SK
; /* Lower SCK */
1616 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), eec
);
1617 IXGBE_WRITE_FLUSH(hw
);
1621 /* Stop requesting EEPROM access */
1622 eec
&= ~IXGBE_EEC_REQ
;
1623 IXGBE_WRITE_REG(hw
, IXGBE_EEC(hw
), eec
);
1625 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
1628 * Delay before attempt to obtain semaphore again to allow FW
1629 * access. semaphore_delay is in ms we need us for usleep_range
1631 usleep_range(hw
->eeprom
.semaphore_delay
* 1000,
1632 hw
->eeprom
.semaphore_delay
* 2000);
1636 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1637 * @hw: pointer to hardware structure
1639 s32
ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw
*hw
)
1648 /* Include 0x0-0x3F in the checksum */
1649 for (i
= 0; i
< IXGBE_EEPROM_CHECKSUM
; i
++) {
1650 if (hw
->eeprom
.ops
.read(hw
, i
, &word
)) {
1651 hw_dbg(hw
, "EEPROM read failed\n");
1657 /* Include all data from pointers except for the fw pointer */
1658 for (i
= IXGBE_PCIE_ANALOG_PTR
; i
< IXGBE_FW_PTR
; i
++) {
1659 if (hw
->eeprom
.ops
.read(hw
, i
, &pointer
)) {
1660 hw_dbg(hw
, "EEPROM read failed\n");
1661 return IXGBE_ERR_EEPROM
;
1664 /* If the pointer seems invalid */
1665 if (pointer
== 0xFFFF || pointer
== 0)
1668 if (hw
->eeprom
.ops
.read(hw
, pointer
, &length
)) {
1669 hw_dbg(hw
, "EEPROM read failed\n");
1670 return IXGBE_ERR_EEPROM
;
1673 if (length
== 0xFFFF || length
== 0)
1676 for (j
= pointer
+ 1; j
<= pointer
+ length
; j
++) {
1677 if (hw
->eeprom
.ops
.read(hw
, j
, &word
)) {
1678 hw_dbg(hw
, "EEPROM read failed\n");
1679 return IXGBE_ERR_EEPROM
;
1685 checksum
= (u16
)IXGBE_EEPROM_SUM
- checksum
;
1687 return (s32
)checksum
;
1691 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1692 * @hw: pointer to hardware structure
1693 * @checksum_val: calculated checksum
1695 * Performs checksum calculation and validates the EEPROM checksum. If the
1696 * caller does not need checksum_val, the value can be NULL.
1698 s32
ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw
*hw
,
1703 u16 read_checksum
= 0;
1706 * Read the first word from the EEPROM. If this times out or fails, do
1707 * not continue or we could be in for a very long wait while every
1710 status
= hw
->eeprom
.ops
.read(hw
, 0, &checksum
);
1712 hw_dbg(hw
, "EEPROM read failed\n");
1716 status
= hw
->eeprom
.ops
.calc_checksum(hw
);
1720 checksum
= (u16
)(status
& 0xffff);
1722 status
= hw
->eeprom
.ops
.read(hw
, IXGBE_EEPROM_CHECKSUM
, &read_checksum
);
1724 hw_dbg(hw
, "EEPROM read failed\n");
1728 /* Verify read checksum from EEPROM is the same as
1729 * calculated checksum
1731 if (read_checksum
!= checksum
)
1732 status
= IXGBE_ERR_EEPROM_CHECKSUM
;
1734 /* If the user cares, return the calculated checksum */
1736 *checksum_val
= checksum
;
1742 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1743 * @hw: pointer to hardware structure
1745 s32
ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw
*hw
)
1751 * Read the first word from the EEPROM. If this times out or fails, do
1752 * not continue or we could be in for a very long wait while every
1755 status
= hw
->eeprom
.ops
.read(hw
, 0, &checksum
);
1757 hw_dbg(hw
, "EEPROM read failed\n");
1761 status
= hw
->eeprom
.ops
.calc_checksum(hw
);
1765 checksum
= (u16
)(status
& 0xffff);
1767 status
= hw
->eeprom
.ops
.write(hw
, IXGBE_EEPROM_CHECKSUM
, checksum
);
1773 * ixgbe_set_rar_generic - Set Rx address register
1774 * @hw: pointer to hardware structure
1775 * @index: Receive address register to write
1776 * @addr: Address to put into receive address register
1777 * @vmdq: VMDq "set" or "pool" index
1778 * @enable_addr: set flag that address is active
1780 * Puts an ethernet address into a receive address register.
1782 s32
ixgbe_set_rar_generic(struct ixgbe_hw
*hw
, u32 index
, u8
*addr
, u32 vmdq
,
1785 u32 rar_low
, rar_high
;
1786 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1788 /* Make sure we are using a valid rar index range */
1789 if (index
>= rar_entries
) {
1790 hw_dbg(hw
, "RAR index %d is out of range.\n", index
);
1791 return IXGBE_ERR_INVALID_ARGUMENT
;
1794 /* setup VMDq pool selection before this RAR gets enabled */
1795 hw
->mac
.ops
.set_vmdq(hw
, index
, vmdq
);
1798 * HW expects these in little endian so we reverse the byte
1799 * order from network order (big endian) to little endian
1801 rar_low
= ((u32
)addr
[0] |
1802 ((u32
)addr
[1] << 8) |
1803 ((u32
)addr
[2] << 16) |
1804 ((u32
)addr
[3] << 24));
1806 * Some parts put the VMDq setting in the extra RAH bits,
1807 * so save everything except the lower 16 bits that hold part
1808 * of the address and the address valid bit.
1810 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1811 rar_high
&= ~(0x0000FFFF | IXGBE_RAH_AV
);
1812 rar_high
|= ((u32
)addr
[4] | ((u32
)addr
[5] << 8));
1814 if (enable_addr
!= 0)
1815 rar_high
|= IXGBE_RAH_AV
;
1817 IXGBE_WRITE_REG(hw
, IXGBE_RAL(index
), rar_low
);
1818 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1824 * ixgbe_clear_rar_generic - Remove Rx address register
1825 * @hw: pointer to hardware structure
1826 * @index: Receive address register to write
1828 * Clears an ethernet address from a receive address register.
1830 s32
ixgbe_clear_rar_generic(struct ixgbe_hw
*hw
, u32 index
)
1833 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1835 /* Make sure we are using a valid rar index range */
1836 if (index
>= rar_entries
) {
1837 hw_dbg(hw
, "RAR index %d is out of range.\n", index
);
1838 return IXGBE_ERR_INVALID_ARGUMENT
;
1842 * Some parts put the VMDq setting in the extra RAH bits,
1843 * so save everything except the lower 16 bits that hold part
1844 * of the address and the address valid bit.
1846 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1847 rar_high
&= ~(0x0000FFFF | IXGBE_RAH_AV
);
1849 IXGBE_WRITE_REG(hw
, IXGBE_RAL(index
), 0);
1850 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1852 /* clear VMDq pool/queue selection for this RAR */
1853 hw
->mac
.ops
.clear_vmdq(hw
, index
, IXGBE_CLEAR_VMDQ_ALL
);
1859 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1860 * @hw: pointer to hardware structure
1862 * Places the MAC address in receive address register 0 and clears the rest
1863 * of the receive address registers. Clears the multicast table. Assumes
1864 * the receiver is in reset when the routine is called.
1866 s32
ixgbe_init_rx_addrs_generic(struct ixgbe_hw
*hw
)
1869 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1872 * If the current mac address is valid, assume it is a software override
1873 * to the permanent address.
1874 * Otherwise, use the permanent address from the eeprom.
1876 if (!is_valid_ether_addr(hw
->mac
.addr
)) {
1877 /* Get the MAC address from the RAR0 for later reference */
1878 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.addr
);
1880 hw_dbg(hw
, " Keeping Current RAR0 Addr =%pM\n", hw
->mac
.addr
);
1882 /* Setup the receive address. */
1883 hw_dbg(hw
, "Overriding MAC Address in RAR[0]\n");
1884 hw_dbg(hw
, " New MAC Addr =%pM\n", hw
->mac
.addr
);
1886 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, 0, IXGBE_RAH_AV
);
1888 /* clear VMDq pool/queue selection for RAR 0 */
1889 hw
->mac
.ops
.clear_vmdq(hw
, 0, IXGBE_CLEAR_VMDQ_ALL
);
1891 hw
->addr_ctrl
.overflow_promisc
= 0;
1893 hw
->addr_ctrl
.rar_used_count
= 1;
1895 /* Zero out the other receive addresses. */
1896 hw_dbg(hw
, "Clearing RAR[1-%d]\n", rar_entries
- 1);
1897 for (i
= 1; i
< rar_entries
; i
++) {
1898 IXGBE_WRITE_REG(hw
, IXGBE_RAL(i
), 0);
1899 IXGBE_WRITE_REG(hw
, IXGBE_RAH(i
), 0);
1903 hw
->addr_ctrl
.mta_in_use
= 0;
1904 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, hw
->mac
.mc_filter_type
);
1906 hw_dbg(hw
, " Clearing MTA\n");
1907 for (i
= 0; i
< hw
->mac
.mcft_size
; i
++)
1908 IXGBE_WRITE_REG(hw
, IXGBE_MTA(i
), 0);
1910 if (hw
->mac
.ops
.init_uta_tables
)
1911 hw
->mac
.ops
.init_uta_tables(hw
);
1917 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1918 * @hw: pointer to hardware structure
1919 * @mc_addr: the multicast address
1921 * Extracts the 12 bits, from a multicast address, to determine which
1922 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1923 * incoming rx multicast addresses, to determine the bit-vector to check in
1924 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1925 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1926 * to mc_filter_type.
1928 static s32
ixgbe_mta_vector(struct ixgbe_hw
*hw
, u8
*mc_addr
)
1932 switch (hw
->mac
.mc_filter_type
) {
1933 case 0: /* use bits [47:36] of the address */
1934 vector
= ((mc_addr
[4] >> 4) | (((u16
)mc_addr
[5]) << 4));
1936 case 1: /* use bits [46:35] of the address */
1937 vector
= ((mc_addr
[4] >> 3) | (((u16
)mc_addr
[5]) << 5));
1939 case 2: /* use bits [45:34] of the address */
1940 vector
= ((mc_addr
[4] >> 2) | (((u16
)mc_addr
[5]) << 6));
1942 case 3: /* use bits [43:32] of the address */
1943 vector
= ((mc_addr
[4]) | (((u16
)mc_addr
[5]) << 8));
1945 default: /* Invalid mc_filter_type */
1946 hw_dbg(hw
, "MC filter type param set incorrectly\n");
1950 /* vector can only be 12-bits or boundary will be exceeded */
1956 * ixgbe_set_mta - Set bit-vector in multicast table
1957 * @hw: pointer to hardware structure
1958 * @hash_value: Multicast address hash value
1960 * Sets the bit-vector in the multicast table.
1962 static void ixgbe_set_mta(struct ixgbe_hw
*hw
, u8
*mc_addr
)
1968 hw
->addr_ctrl
.mta_in_use
++;
1970 vector
= ixgbe_mta_vector(hw
, mc_addr
);
1971 hw_dbg(hw
, " bit-vector = 0x%03X\n", vector
);
1974 * The MTA is a register array of 128 32-bit registers. It is treated
1975 * like an array of 4096 bits. We want to set bit
1976 * BitArray[vector_value]. So we figure out what register the bit is
1977 * in, read it, OR in the new bit, then write back the new value. The
1978 * register is determined by the upper 7 bits of the vector value and
1979 * the bit within that register are determined by the lower 5 bits of
1982 vector_reg
= (vector
>> 5) & 0x7F;
1983 vector_bit
= vector
& 0x1F;
1984 hw
->mac
.mta_shadow
[vector_reg
] |= (1 << vector_bit
);
1988 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
1989 * @hw: pointer to hardware structure
1990 * @netdev: pointer to net device structure
1992 * The given list replaces any existing list. Clears the MC addrs from receive
1993 * address registers and the multicast table. Uses unused receive address
1994 * registers for the first multicast addresses, and hashes the rest into the
1997 s32
ixgbe_update_mc_addr_list_generic(struct ixgbe_hw
*hw
,
1998 struct net_device
*netdev
)
2000 struct netdev_hw_addr
*ha
;
2004 * Set the new number of MC addresses that we are being requested to
2007 hw
->addr_ctrl
.num_mc_addrs
= netdev_mc_count(netdev
);
2008 hw
->addr_ctrl
.mta_in_use
= 0;
2010 /* Clear mta_shadow */
2011 hw_dbg(hw
, " Clearing MTA\n");
2012 memset(&hw
->mac
.mta_shadow
, 0, sizeof(hw
->mac
.mta_shadow
));
2014 /* Update mta shadow */
2015 netdev_for_each_mc_addr(ha
, netdev
) {
2016 hw_dbg(hw
, " Adding the multicast addresses:\n");
2017 ixgbe_set_mta(hw
, ha
->addr
);
2021 for (i
= 0; i
< hw
->mac
.mcft_size
; i
++)
2022 IXGBE_WRITE_REG_ARRAY(hw
, IXGBE_MTA(0), i
,
2023 hw
->mac
.mta_shadow
[i
]);
2025 if (hw
->addr_ctrl
.mta_in_use
> 0)
2026 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
,
2027 IXGBE_MCSTCTRL_MFE
| hw
->mac
.mc_filter_type
);
2029 hw_dbg(hw
, "ixgbe_update_mc_addr_list_generic Complete\n");
2034 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2035 * @hw: pointer to hardware structure
2037 * Enables multicast address in RAR and the use of the multicast hash table.
2039 s32
ixgbe_enable_mc_generic(struct ixgbe_hw
*hw
)
2041 struct ixgbe_addr_filter_info
*a
= &hw
->addr_ctrl
;
2043 if (a
->mta_in_use
> 0)
2044 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, IXGBE_MCSTCTRL_MFE
|
2045 hw
->mac
.mc_filter_type
);
2051 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2052 * @hw: pointer to hardware structure
2054 * Disables multicast address in RAR and the use of the multicast hash table.
2056 s32
ixgbe_disable_mc_generic(struct ixgbe_hw
*hw
)
2058 struct ixgbe_addr_filter_info
*a
= &hw
->addr_ctrl
;
2060 if (a
->mta_in_use
> 0)
2061 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, hw
->mac
.mc_filter_type
);
2067 * ixgbe_fc_enable_generic - Enable flow control
2068 * @hw: pointer to hardware structure
2070 * Enable flow control according to the current settings.
2072 s32
ixgbe_fc_enable_generic(struct ixgbe_hw
*hw
)
2074 u32 mflcn_reg
, fccfg_reg
;
2079 /* Validate the water mark configuration. */
2080 if (!hw
->fc
.pause_time
)
2081 return IXGBE_ERR_INVALID_LINK_SETTINGS
;
2083 /* Low water mark of zero causes XOFF floods */
2084 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++) {
2085 if ((hw
->fc
.current_mode
& ixgbe_fc_tx_pause
) &&
2086 hw
->fc
.high_water
[i
]) {
2087 if (!hw
->fc
.low_water
[i
] ||
2088 hw
->fc
.low_water
[i
] >= hw
->fc
.high_water
[i
]) {
2089 hw_dbg(hw
, "Invalid water mark configuration\n");
2090 return IXGBE_ERR_INVALID_LINK_SETTINGS
;
2095 /* Negotiate the fc mode to use */
2096 ixgbe_fc_autoneg(hw
);
2098 /* Disable any previous flow control settings */
2099 mflcn_reg
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
2100 mflcn_reg
&= ~(IXGBE_MFLCN_RPFCE_MASK
| IXGBE_MFLCN_RFCE
);
2102 fccfg_reg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
2103 fccfg_reg
&= ~(IXGBE_FCCFG_TFCE_802_3X
| IXGBE_FCCFG_TFCE_PRIORITY
);
2106 * The possible values of fc.current_mode are:
2107 * 0: Flow control is completely disabled
2108 * 1: Rx flow control is enabled (we can receive pause frames,
2109 * but not send pause frames).
2110 * 2: Tx flow control is enabled (we can send pause frames but
2111 * we do not support receiving pause frames).
2112 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2115 switch (hw
->fc
.current_mode
) {
2118 * Flow control is disabled by software override or autoneg.
2119 * The code below will actually disable it in the HW.
2122 case ixgbe_fc_rx_pause
:
2124 * Rx Flow control is enabled and Tx Flow control is
2125 * disabled by software override. Since there really
2126 * isn't a way to advertise that we are capable of RX
2127 * Pause ONLY, we will advertise that we support both
2128 * symmetric and asymmetric Rx PAUSE. Later, we will
2129 * disable the adapter's ability to send PAUSE frames.
2131 mflcn_reg
|= IXGBE_MFLCN_RFCE
;
2133 case ixgbe_fc_tx_pause
:
2135 * Tx Flow control is enabled, and Rx Flow control is
2136 * disabled by software override.
2138 fccfg_reg
|= IXGBE_FCCFG_TFCE_802_3X
;
2141 /* Flow control (both Rx and Tx) is enabled by SW override. */
2142 mflcn_reg
|= IXGBE_MFLCN_RFCE
;
2143 fccfg_reg
|= IXGBE_FCCFG_TFCE_802_3X
;
2146 hw_dbg(hw
, "Flow control param set incorrectly\n");
2147 return IXGBE_ERR_CONFIG
;
2150 /* Set 802.3x based flow control settings. */
2151 mflcn_reg
|= IXGBE_MFLCN_DPF
;
2152 IXGBE_WRITE_REG(hw
, IXGBE_MFLCN
, mflcn_reg
);
2153 IXGBE_WRITE_REG(hw
, IXGBE_FCCFG
, fccfg_reg
);
2155 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2156 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++) {
2157 if ((hw
->fc
.current_mode
& ixgbe_fc_tx_pause
) &&
2158 hw
->fc
.high_water
[i
]) {
2159 fcrtl
= (hw
->fc
.low_water
[i
] << 10) | IXGBE_FCRTL_XONE
;
2160 IXGBE_WRITE_REG(hw
, IXGBE_FCRTL_82599(i
), fcrtl
);
2161 fcrth
= (hw
->fc
.high_water
[i
] << 10) | IXGBE_FCRTH_FCEN
;
2163 IXGBE_WRITE_REG(hw
, IXGBE_FCRTL_82599(i
), 0);
2165 * In order to prevent Tx hangs when the internal Tx
2166 * switch is enabled we must set the high water mark
2167 * to the maximum FCRTH value. This allows the Tx
2168 * switch to function even under heavy Rx workloads.
2170 fcrth
= IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(i
)) - 32;
2173 IXGBE_WRITE_REG(hw
, IXGBE_FCRTH_82599(i
), fcrth
);
2176 /* Configure pause time (2 TCs per register) */
2177 reg
= hw
->fc
.pause_time
* 0x00010001;
2178 for (i
= 0; i
< (MAX_TRAFFIC_CLASS
/ 2); i
++)
2179 IXGBE_WRITE_REG(hw
, IXGBE_FCTTV(i
), reg
);
2181 IXGBE_WRITE_REG(hw
, IXGBE_FCRTV
, hw
->fc
.pause_time
/ 2);
2187 * ixgbe_negotiate_fc - Negotiate flow control
2188 * @hw: pointer to hardware structure
2189 * @adv_reg: flow control advertised settings
2190 * @lp_reg: link partner's flow control settings
2191 * @adv_sym: symmetric pause bit in advertisement
2192 * @adv_asm: asymmetric pause bit in advertisement
2193 * @lp_sym: symmetric pause bit in link partner advertisement
2194 * @lp_asm: asymmetric pause bit in link partner advertisement
2196 * Find the intersection between advertised settings and link partner's
2197 * advertised settings
2199 static s32
ixgbe_negotiate_fc(struct ixgbe_hw
*hw
, u32 adv_reg
, u32 lp_reg
,
2200 u32 adv_sym
, u32 adv_asm
, u32 lp_sym
, u32 lp_asm
)
2202 if ((!(adv_reg
)) || (!(lp_reg
)))
2203 return IXGBE_ERR_FC_NOT_NEGOTIATED
;
2205 if ((adv_reg
& adv_sym
) && (lp_reg
& lp_sym
)) {
2207 * Now we need to check if the user selected Rx ONLY
2208 * of pause frames. In this case, we had to advertise
2209 * FULL flow control because we could not advertise RX
2210 * ONLY. Hence, we must now check to see if we need to
2211 * turn OFF the TRANSMISSION of PAUSE frames.
2213 if (hw
->fc
.requested_mode
== ixgbe_fc_full
) {
2214 hw
->fc
.current_mode
= ixgbe_fc_full
;
2215 hw_dbg(hw
, "Flow Control = FULL.\n");
2217 hw
->fc
.current_mode
= ixgbe_fc_rx_pause
;
2218 hw_dbg(hw
, "Flow Control=RX PAUSE frames only\n");
2220 } else if (!(adv_reg
& adv_sym
) && (adv_reg
& adv_asm
) &&
2221 (lp_reg
& lp_sym
) && (lp_reg
& lp_asm
)) {
2222 hw
->fc
.current_mode
= ixgbe_fc_tx_pause
;
2223 hw_dbg(hw
, "Flow Control = TX PAUSE frames only.\n");
2224 } else if ((adv_reg
& adv_sym
) && (adv_reg
& adv_asm
) &&
2225 !(lp_reg
& lp_sym
) && (lp_reg
& lp_asm
)) {
2226 hw
->fc
.current_mode
= ixgbe_fc_rx_pause
;
2227 hw_dbg(hw
, "Flow Control = RX PAUSE frames only.\n");
2229 hw
->fc
.current_mode
= ixgbe_fc_none
;
2230 hw_dbg(hw
, "Flow Control = NONE.\n");
2236 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2237 * @hw: pointer to hardware structure
2239 * Enable flow control according on 1 gig fiber.
2241 static s32
ixgbe_fc_autoneg_fiber(struct ixgbe_hw
*hw
)
2243 u32 pcs_anadv_reg
, pcs_lpab_reg
, linkstat
;
2247 * On multispeed fiber at 1g, bail out if
2248 * - link is up but AN did not complete, or if
2249 * - link is up and AN completed but timed out
2252 linkstat
= IXGBE_READ_REG(hw
, IXGBE_PCS1GLSTA
);
2253 if ((!!(linkstat
& IXGBE_PCS1GLSTA_AN_COMPLETE
) == 0) ||
2254 (!!(linkstat
& IXGBE_PCS1GLSTA_AN_TIMED_OUT
) == 1))
2255 return IXGBE_ERR_FC_NOT_NEGOTIATED
;
2257 pcs_anadv_reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANA
);
2258 pcs_lpab_reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANLP
);
2260 ret_val
= ixgbe_negotiate_fc(hw
, pcs_anadv_reg
,
2261 pcs_lpab_reg
, IXGBE_PCS1GANA_SYM_PAUSE
,
2262 IXGBE_PCS1GANA_ASM_PAUSE
,
2263 IXGBE_PCS1GANA_SYM_PAUSE
,
2264 IXGBE_PCS1GANA_ASM_PAUSE
);
2270 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2271 * @hw: pointer to hardware structure
2273 * Enable flow control according to IEEE clause 37.
2275 static s32
ixgbe_fc_autoneg_backplane(struct ixgbe_hw
*hw
)
2277 u32 links2
, anlp1_reg
, autoc_reg
, links
;
2281 * On backplane, bail out if
2282 * - backplane autoneg was not completed, or if
2283 * - we are 82599 and link partner is not AN enabled
2285 links
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
2286 if ((links
& IXGBE_LINKS_KX_AN_COMP
) == 0)
2287 return IXGBE_ERR_FC_NOT_NEGOTIATED
;
2289 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2290 links2
= IXGBE_READ_REG(hw
, IXGBE_LINKS2
);
2291 if ((links2
& IXGBE_LINKS2_AN_SUPPORTED
) == 0)
2292 return IXGBE_ERR_FC_NOT_NEGOTIATED
;
2295 * Read the 10g AN autoc and LP ability registers and resolve
2296 * local flow control settings accordingly
2298 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2299 anlp1_reg
= IXGBE_READ_REG(hw
, IXGBE_ANLP1
);
2301 ret_val
= ixgbe_negotiate_fc(hw
, autoc_reg
,
2302 anlp1_reg
, IXGBE_AUTOC_SYM_PAUSE
, IXGBE_AUTOC_ASM_PAUSE
,
2303 IXGBE_ANLP1_SYM_PAUSE
, IXGBE_ANLP1_ASM_PAUSE
);
2309 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2310 * @hw: pointer to hardware structure
2312 * Enable flow control according to IEEE clause 37.
2314 static s32
ixgbe_fc_autoneg_copper(struct ixgbe_hw
*hw
)
2316 u16 technology_ability_reg
= 0;
2317 u16 lp_technology_ability_reg
= 0;
2319 hw
->phy
.ops
.read_reg(hw
, MDIO_AN_ADVERTISE
,
2321 &technology_ability_reg
);
2322 hw
->phy
.ops
.read_reg(hw
, MDIO_AN_LPA
,
2324 &lp_technology_ability_reg
);
2326 return ixgbe_negotiate_fc(hw
, (u32
)technology_ability_reg
,
2327 (u32
)lp_technology_ability_reg
,
2328 IXGBE_TAF_SYM_PAUSE
, IXGBE_TAF_ASM_PAUSE
,
2329 IXGBE_TAF_SYM_PAUSE
, IXGBE_TAF_ASM_PAUSE
);
2333 * ixgbe_fc_autoneg - Configure flow control
2334 * @hw: pointer to hardware structure
2336 * Compares our advertised flow control capabilities to those advertised by
2337 * our link partner, and determines the proper flow control mode to use.
2339 void ixgbe_fc_autoneg(struct ixgbe_hw
*hw
)
2341 s32 ret_val
= IXGBE_ERR_FC_NOT_NEGOTIATED
;
2342 ixgbe_link_speed speed
;
2346 * AN should have completed when the cable was plugged in.
2347 * Look for reasons to bail out. Bail out if:
2348 * - FC autoneg is disabled, or if
2351 * Since we're being called from an LSC, link is already known to be up.
2352 * So use link_up_wait_to_complete=false.
2354 if (hw
->fc
.disable_fc_autoneg
)
2357 hw
->mac
.ops
.check_link(hw
, &speed
, &link_up
, false);
2361 switch (hw
->phy
.media_type
) {
2362 /* Autoneg flow control on fiber adapters */
2363 case ixgbe_media_type_fiber
:
2364 if (speed
== IXGBE_LINK_SPEED_1GB_FULL
)
2365 ret_val
= ixgbe_fc_autoneg_fiber(hw
);
2368 /* Autoneg flow control on backplane adapters */
2369 case ixgbe_media_type_backplane
:
2370 ret_val
= ixgbe_fc_autoneg_backplane(hw
);
2373 /* Autoneg flow control on copper adapters */
2374 case ixgbe_media_type_copper
:
2375 if (ixgbe_device_supports_autoneg_fc(hw
))
2376 ret_val
= ixgbe_fc_autoneg_copper(hw
);
2385 hw
->fc
.fc_was_autonegged
= true;
2387 hw
->fc
.fc_was_autonegged
= false;
2388 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
2393 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
2394 * @hw: pointer to hardware structure
2396 * System-wide timeout range is encoded in PCIe Device Control2 register.
2398 * Add 10% to specified maximum and return the number of times to poll for
2399 * completion timeout, in units of 100 microsec. Never return less than
2400 * 800 = 80 millisec.
2402 static u32
ixgbe_pcie_timeout_poll(struct ixgbe_hw
*hw
)
2407 devctl2
= ixgbe_read_pci_cfg_word(hw
, IXGBE_PCI_DEVICE_CONTROL2
);
2408 devctl2
&= IXGBE_PCIDEVCTRL2_TIMEO_MASK
;
2411 case IXGBE_PCIDEVCTRL2_65_130ms
:
2412 pollcnt
= 1300; /* 130 millisec */
2414 case IXGBE_PCIDEVCTRL2_260_520ms
:
2415 pollcnt
= 5200; /* 520 millisec */
2417 case IXGBE_PCIDEVCTRL2_1_2s
:
2418 pollcnt
= 20000; /* 2 sec */
2420 case IXGBE_PCIDEVCTRL2_4_8s
:
2421 pollcnt
= 80000; /* 8 sec */
2423 case IXGBE_PCIDEVCTRL2_17_34s
:
2424 pollcnt
= 34000; /* 34 sec */
2426 case IXGBE_PCIDEVCTRL2_50_100us
: /* 100 microsecs */
2427 case IXGBE_PCIDEVCTRL2_1_2ms
: /* 2 millisecs */
2428 case IXGBE_PCIDEVCTRL2_16_32ms
: /* 32 millisec */
2429 case IXGBE_PCIDEVCTRL2_16_32ms_def
: /* 32 millisec default */
2431 pollcnt
= 800; /* 80 millisec minimum */
2435 /* add 10% to spec maximum */
2436 return (pollcnt
* 11) / 10;
2440 * ixgbe_disable_pcie_master - Disable PCI-express master access
2441 * @hw: pointer to hardware structure
2443 * Disables PCI-Express master access and verifies there are no pending
2444 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2445 * bit hasn't caused the master requests to be disabled, else 0
2446 * is returned signifying master requests disabled.
2448 static s32
ixgbe_disable_pcie_master(struct ixgbe_hw
*hw
)
2453 /* Always set this bit to ensure any future transactions are blocked */
2454 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, IXGBE_CTRL_GIO_DIS
);
2456 /* Exit if master requests are blocked */
2457 if (!(IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_GIO
) ||
2458 ixgbe_removed(hw
->hw_addr
))
2461 /* Poll for master request bit to clear */
2462 for (i
= 0; i
< IXGBE_PCI_MASTER_DISABLE_TIMEOUT
; i
++) {
2464 if (!(IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_GIO
))
2469 * Two consecutive resets are required via CTRL.RST per datasheet
2470 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2471 * of this need. The first reset prevents new master requests from
2472 * being issued by our device. We then must wait 1usec or more for any
2473 * remaining completions from the PCIe bus to trickle in, and then reset
2474 * again to clear out any effects they may have had on our device.
2476 hw_dbg(hw
, "GIO Master Disable bit didn't clear - requesting resets\n");
2477 hw
->mac
.flags
|= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
;
2480 * Before proceeding, make sure that the PCIe block does not have
2481 * transactions pending.
2483 poll
= ixgbe_pcie_timeout_poll(hw
);
2484 for (i
= 0; i
< poll
; i
++) {
2486 value
= ixgbe_read_pci_cfg_word(hw
, IXGBE_PCI_DEVICE_STATUS
);
2487 if (ixgbe_removed(hw
->hw_addr
))
2489 if (!(value
& IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING
))
2493 hw_dbg(hw
, "PCIe transaction pending bit also did not clear.\n");
2494 return IXGBE_ERR_MASTER_REQUESTS_PENDING
;
2498 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2499 * @hw: pointer to hardware structure
2500 * @mask: Mask to specify which semaphore to acquire
2502 * Acquires the SWFW semaphore through the GSSR register for the specified
2503 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2505 s32
ixgbe_acquire_swfw_sync(struct ixgbe_hw
*hw
, u32 mask
)
2509 u32 fwmask
= mask
<< 5;
2513 for (i
= 0; i
< timeout
; i
++) {
2515 * SW NVM semaphore bit is used for access to all
2516 * SW_FW_SYNC bits (not just NVM)
2518 if (ixgbe_get_eeprom_semaphore(hw
))
2519 return IXGBE_ERR_SWFW_SYNC
;
2521 gssr
= IXGBE_READ_REG(hw
, IXGBE_GSSR
);
2522 if (!(gssr
& (fwmask
| swmask
))) {
2524 IXGBE_WRITE_REG(hw
, IXGBE_GSSR
, gssr
);
2525 ixgbe_release_eeprom_semaphore(hw
);
2528 /* Resource is currently in use by FW or SW */
2529 ixgbe_release_eeprom_semaphore(hw
);
2530 usleep_range(5000, 10000);
2534 /* If time expired clear the bits holding the lock and retry */
2535 if (gssr
& (fwmask
| swmask
))
2536 ixgbe_release_swfw_sync(hw
, gssr
& (fwmask
| swmask
));
2538 usleep_range(5000, 10000);
2539 return IXGBE_ERR_SWFW_SYNC
;
2543 * ixgbe_release_swfw_sync - Release SWFW semaphore
2544 * @hw: pointer to hardware structure
2545 * @mask: Mask to specify which semaphore to release
2547 * Releases the SWFW semaphore through the GSSR register for the specified
2548 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2550 void ixgbe_release_swfw_sync(struct ixgbe_hw
*hw
, u32 mask
)
2555 ixgbe_get_eeprom_semaphore(hw
);
2557 gssr
= IXGBE_READ_REG(hw
, IXGBE_GSSR
);
2559 IXGBE_WRITE_REG(hw
, IXGBE_GSSR
, gssr
);
2561 ixgbe_release_eeprom_semaphore(hw
);
2565 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
2566 * @hw: pointer to hardware structure
2567 * @reg_val: Value we read from AUTOC
2568 * @locked: bool to indicate whether the SW/FW lock should be taken. Never
2569 * true in this the generic case.
2571 * The default case requires no protection so just to the register read.
2573 s32
prot_autoc_read_generic(struct ixgbe_hw
*hw
, bool *locked
, u32
*reg_val
)
2576 *reg_val
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2581 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
2582 * @hw: pointer to hardware structure
2583 * @reg_val: value to write to AUTOC
2584 * @locked: bool to indicate whether the SW/FW lock was already taken by
2587 s32
prot_autoc_write_generic(struct ixgbe_hw
*hw
, u32 reg_val
, bool locked
)
2589 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, reg_val
);
2594 * ixgbe_disable_rx_buff_generic - Stops the receive data path
2595 * @hw: pointer to hardware structure
2597 * Stops the receive data path and waits for the HW to internally
2598 * empty the Rx security block.
2600 s32
ixgbe_disable_rx_buff_generic(struct ixgbe_hw
*hw
)
2602 #define IXGBE_MAX_SECRX_POLL 40
2606 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
2607 secrxreg
|= IXGBE_SECRXCTRL_RX_DIS
;
2608 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
2609 for (i
= 0; i
< IXGBE_MAX_SECRX_POLL
; i
++) {
2610 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXSTAT
);
2611 if (secrxreg
& IXGBE_SECRXSTAT_SECRX_RDY
)
2614 /* Use interrupt-safe sleep just in case */
2618 /* For informational purposes only */
2619 if (i
>= IXGBE_MAX_SECRX_POLL
)
2620 hw_dbg(hw
, "Rx unit being enabled before security path fully disabled. Continuing with init.\n");
2627 * ixgbe_enable_rx_buff - Enables the receive data path
2628 * @hw: pointer to hardware structure
2630 * Enables the receive data path
2632 s32
ixgbe_enable_rx_buff_generic(struct ixgbe_hw
*hw
)
2636 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
2637 secrxreg
&= ~IXGBE_SECRXCTRL_RX_DIS
;
2638 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
2639 IXGBE_WRITE_FLUSH(hw
);
2645 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2646 * @hw: pointer to hardware structure
2647 * @regval: register value to write to RXCTRL
2649 * Enables the Rx DMA unit
2651 s32
ixgbe_enable_rx_dma_generic(struct ixgbe_hw
*hw
, u32 regval
)
2653 if (regval
& IXGBE_RXCTRL_RXEN
)
2654 hw
->mac
.ops
.enable_rx(hw
);
2656 hw
->mac
.ops
.disable_rx(hw
);
2662 * ixgbe_blink_led_start_generic - Blink LED based on index.
2663 * @hw: pointer to hardware structure
2664 * @index: led number to blink
2666 s32
ixgbe_blink_led_start_generic(struct ixgbe_hw
*hw
, u32 index
)
2668 ixgbe_link_speed speed
= 0;
2669 bool link_up
= false;
2670 u32 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2671 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
2672 bool locked
= false;
2676 * Link must be up to auto-blink the LEDs;
2677 * Force it if link is down.
2679 hw
->mac
.ops
.check_link(hw
, &speed
, &link_up
, false);
2682 ret_val
= hw
->mac
.ops
.prot_autoc_read(hw
, &locked
, &autoc_reg
);
2686 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
2687 autoc_reg
|= IXGBE_AUTOC_FLU
;
2689 ret_val
= hw
->mac
.ops
.prot_autoc_write(hw
, autoc_reg
, locked
);
2693 IXGBE_WRITE_FLUSH(hw
);
2695 usleep_range(10000, 20000);
2698 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
2699 led_reg
|= IXGBE_LED_BLINK(index
);
2700 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
2701 IXGBE_WRITE_FLUSH(hw
);
2707 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2708 * @hw: pointer to hardware structure
2709 * @index: led number to stop blinking
2711 s32
ixgbe_blink_led_stop_generic(struct ixgbe_hw
*hw
, u32 index
)
2714 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
2715 bool locked
= false;
2718 ret_val
= hw
->mac
.ops
.prot_autoc_read(hw
, &locked
, &autoc_reg
);
2722 autoc_reg
&= ~IXGBE_AUTOC_FLU
;
2723 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
2725 ret_val
= hw
->mac
.ops
.prot_autoc_write(hw
, autoc_reg
, locked
);
2729 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
2730 led_reg
&= ~IXGBE_LED_BLINK(index
);
2731 led_reg
|= IXGBE_LED_LINK_ACTIVE
<< IXGBE_LED_MODE_SHIFT(index
);
2732 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
2733 IXGBE_WRITE_FLUSH(hw
);
2739 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2740 * @hw: pointer to hardware structure
2741 * @san_mac_offset: SAN MAC address offset
2743 * This function will read the EEPROM location for the SAN MAC address
2744 * pointer, and returns the value at that location. This is used in both
2745 * get and set mac_addr routines.
2747 static s32
ixgbe_get_san_mac_addr_offset(struct ixgbe_hw
*hw
,
2748 u16
*san_mac_offset
)
2753 * First read the EEPROM pointer to see if the MAC addresses are
2756 ret_val
= hw
->eeprom
.ops
.read(hw
, IXGBE_SAN_MAC_ADDR_PTR
,
2759 hw_err(hw
, "eeprom read at offset %d failed\n",
2760 IXGBE_SAN_MAC_ADDR_PTR
);
2766 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2767 * @hw: pointer to hardware structure
2768 * @san_mac_addr: SAN MAC address
2770 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2771 * per-port, so set_lan_id() must be called before reading the addresses.
2772 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2773 * upon for non-SFP connections, so we must call it here.
2775 s32
ixgbe_get_san_mac_addr_generic(struct ixgbe_hw
*hw
, u8
*san_mac_addr
)
2777 u16 san_mac_data
, san_mac_offset
;
2782 * First read the EEPROM pointer to see if the MAC addresses are
2783 * available. If they're not, no point in calling set_lan_id() here.
2785 ret_val
= ixgbe_get_san_mac_addr_offset(hw
, &san_mac_offset
);
2786 if (ret_val
|| san_mac_offset
== 0 || san_mac_offset
== 0xFFFF)
2788 goto san_mac_addr_clr
;
2790 /* make sure we know which port we need to program */
2791 hw
->mac
.ops
.set_lan_id(hw
);
2792 /* apply the port offset to the address offset */
2793 (hw
->bus
.func
) ? (san_mac_offset
+= IXGBE_SAN_MAC_ADDR_PORT1_OFFSET
) :
2794 (san_mac_offset
+= IXGBE_SAN_MAC_ADDR_PORT0_OFFSET
);
2795 for (i
= 0; i
< 3; i
++) {
2796 ret_val
= hw
->eeprom
.ops
.read(hw
, san_mac_offset
,
2799 hw_err(hw
, "eeprom read at offset %d failed\n",
2801 goto san_mac_addr_clr
;
2803 san_mac_addr
[i
* 2] = (u8
)(san_mac_data
);
2804 san_mac_addr
[i
* 2 + 1] = (u8
)(san_mac_data
>> 8);
2810 /* No addresses available in this EEPROM. It's not necessarily an
2811 * error though, so just wipe the local address and return.
2813 for (i
= 0; i
< 6; i
++)
2814 san_mac_addr
[i
] = 0xFF;
2819 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2820 * @hw: pointer to hardware structure
2822 * Read PCIe configuration space, and get the MSI-X vector count from
2823 * the capabilities table.
2825 u16
ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw
*hw
)
2831 switch (hw
->mac
.type
) {
2832 case ixgbe_mac_82598EB
:
2833 pcie_offset
= IXGBE_PCIE_MSIX_82598_CAPS
;
2834 max_msix_count
= IXGBE_MAX_MSIX_VECTORS_82598
;
2836 case ixgbe_mac_82599EB
:
2837 case ixgbe_mac_X540
:
2838 case ixgbe_mac_X550
:
2839 case ixgbe_mac_X550EM_x
:
2840 pcie_offset
= IXGBE_PCIE_MSIX_82599_CAPS
;
2841 max_msix_count
= IXGBE_MAX_MSIX_VECTORS_82599
;
2847 msix_count
= ixgbe_read_pci_cfg_word(hw
, pcie_offset
);
2848 if (ixgbe_removed(hw
->hw_addr
))
2850 msix_count
&= IXGBE_PCIE_MSIX_TBL_SZ_MASK
;
2852 /* MSI-X count is zero-based in HW */
2855 if (msix_count
> max_msix_count
)
2856 msix_count
= max_msix_count
;
2862 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2863 * @hw: pointer to hardware struct
2864 * @rar: receive address register index to disassociate
2865 * @vmdq: VMDq pool index to remove from the rar
2867 s32
ixgbe_clear_vmdq_generic(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
2869 u32 mpsar_lo
, mpsar_hi
;
2870 u32 rar_entries
= hw
->mac
.num_rar_entries
;
2872 /* Make sure we are using a valid rar index range */
2873 if (rar
>= rar_entries
) {
2874 hw_dbg(hw
, "RAR index %d is out of range.\n", rar
);
2875 return IXGBE_ERR_INVALID_ARGUMENT
;
2878 mpsar_lo
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_LO(rar
));
2879 mpsar_hi
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_HI(rar
));
2881 if (ixgbe_removed(hw
->hw_addr
))
2884 if (!mpsar_lo
&& !mpsar_hi
)
2887 if (vmdq
== IXGBE_CLEAR_VMDQ_ALL
) {
2889 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), 0);
2893 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), 0);
2896 } else if (vmdq
< 32) {
2897 mpsar_lo
&= ~(1 << vmdq
);
2898 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), mpsar_lo
);
2900 mpsar_hi
&= ~(1 << (vmdq
- 32));
2901 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), mpsar_hi
);
2904 /* was that the last pool using this rar? */
2905 if (mpsar_lo
== 0 && mpsar_hi
== 0 && rar
!= 0)
2906 hw
->mac
.ops
.clear_rar(hw
, rar
);
2911 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2912 * @hw: pointer to hardware struct
2913 * @rar: receive address register index to associate with a VMDq index
2914 * @vmdq: VMDq pool index
2916 s32
ixgbe_set_vmdq_generic(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
2919 u32 rar_entries
= hw
->mac
.num_rar_entries
;
2921 /* Make sure we are using a valid rar index range */
2922 if (rar
>= rar_entries
) {
2923 hw_dbg(hw
, "RAR index %d is out of range.\n", rar
);
2924 return IXGBE_ERR_INVALID_ARGUMENT
;
2928 mpsar
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_LO(rar
));
2930 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), mpsar
);
2932 mpsar
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_HI(rar
));
2933 mpsar
|= 1 << (vmdq
- 32);
2934 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), mpsar
);
2940 * This function should only be involved in the IOV mode.
2941 * In IOV mode, Default pool is next pool after the number of
2942 * VFs advertized and not 0.
2943 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
2945 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
2946 * @hw: pointer to hardware struct
2947 * @vmdq: VMDq pool index
2949 s32
ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw
*hw
, u32 vmdq
)
2951 u32 rar
= hw
->mac
.san_mac_rar_index
;
2954 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), 1 << vmdq
);
2955 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), 0);
2957 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), 0);
2958 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), 1 << (vmdq
- 32));
2965 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2966 * @hw: pointer to hardware structure
2968 s32
ixgbe_init_uta_tables_generic(struct ixgbe_hw
*hw
)
2972 for (i
= 0; i
< 128; i
++)
2973 IXGBE_WRITE_REG(hw
, IXGBE_UTA(i
), 0);
2979 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2980 * @hw: pointer to hardware structure
2981 * @vlan: VLAN id to write to VLAN filter
2983 * return the VLVF index where this VLAN id should be placed
2986 static s32
ixgbe_find_vlvf_slot(struct ixgbe_hw
*hw
, u32 vlan
)
2989 u32 first_empty_slot
= 0;
2992 /* short cut the special case */
2997 * Search for the vlan id in the VLVF entries. Save off the first empty
2998 * slot found along the way
3000 for (regindex
= 1; regindex
< IXGBE_VLVF_ENTRIES
; regindex
++) {
3001 bits
= IXGBE_READ_REG(hw
, IXGBE_VLVF(regindex
));
3002 if (!bits
&& !(first_empty_slot
))
3003 first_empty_slot
= regindex
;
3004 else if ((bits
& 0x0FFF) == vlan
)
3009 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3010 * in the VLVF. Else use the first empty VLVF register for this
3013 if (regindex
>= IXGBE_VLVF_ENTRIES
) {
3014 if (first_empty_slot
)
3015 regindex
= first_empty_slot
;
3017 hw_dbg(hw
, "No space in VLVF.\n");
3018 regindex
= IXGBE_ERR_NO_SPACE
;
3026 * ixgbe_set_vfta_generic - Set VLAN filter table
3027 * @hw: pointer to hardware structure
3028 * @vlan: VLAN id to write to VLAN filter
3029 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3030 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3032 * Turn on/off specified VLAN in the VLAN filter table.
3034 s32
ixgbe_set_vfta_generic(struct ixgbe_hw
*hw
, u32 vlan
, u32 vind
,
3043 bool vfta_changed
= false;
3046 return IXGBE_ERR_PARAM
;
3049 * this is a 2 part operation - first the VFTA, then the
3050 * VLVF and VLVFB if VT Mode is set
3051 * We don't write the VFTA until we know the VLVF part succeeded.
3055 * The VFTA is a bitstring made up of 128 32-bit registers
3056 * that enable the particular VLAN id, much like the MTA:
3057 * bits[11-5]: which register
3058 * bits[4-0]: which bit in the register
3060 regindex
= (vlan
>> 5) & 0x7F;
3061 bitindex
= vlan
& 0x1F;
3062 targetbit
= (1 << bitindex
);
3063 vfta
= IXGBE_READ_REG(hw
, IXGBE_VFTA(regindex
));
3066 if (!(vfta
& targetbit
)) {
3068 vfta_changed
= true;
3071 if ((vfta
& targetbit
)) {
3073 vfta_changed
= true;
3080 * make sure the vlan is in VLVF
3081 * set the vind bit in the matching VLVFB
3083 * clear the pool bit and possibly the vind
3085 vt
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
3086 if (vt
& IXGBE_VT_CTL_VT_ENABLE
) {
3089 vlvf_index
= ixgbe_find_vlvf_slot(hw
, vlan
);
3094 /* set the pool bit */
3096 bits
= IXGBE_READ_REG(hw
,
3097 IXGBE_VLVFB(vlvf_index
*2));
3098 bits
|= (1 << vind
);
3100 IXGBE_VLVFB(vlvf_index
*2),
3103 bits
= IXGBE_READ_REG(hw
,
3104 IXGBE_VLVFB((vlvf_index
*2)+1));
3105 bits
|= (1 << (vind
-32));
3107 IXGBE_VLVFB((vlvf_index
*2)+1),
3111 /* clear the pool bit */
3113 bits
= IXGBE_READ_REG(hw
,
3114 IXGBE_VLVFB(vlvf_index
*2));
3115 bits
&= ~(1 << vind
);
3117 IXGBE_VLVFB(vlvf_index
*2),
3119 bits
|= IXGBE_READ_REG(hw
,
3120 IXGBE_VLVFB((vlvf_index
*2)+1));
3122 bits
= IXGBE_READ_REG(hw
,
3123 IXGBE_VLVFB((vlvf_index
*2)+1));
3124 bits
&= ~(1 << (vind
-32));
3126 IXGBE_VLVFB((vlvf_index
*2)+1),
3128 bits
|= IXGBE_READ_REG(hw
,
3129 IXGBE_VLVFB(vlvf_index
*2));
3134 * If there are still bits set in the VLVFB registers
3135 * for the VLAN ID indicated we need to see if the
3136 * caller is requesting that we clear the VFTA entry bit.
3137 * If the caller has requested that we clear the VFTA
3138 * entry bit but there are still pools/VFs using this VLAN
3139 * ID entry then ignore the request. We're not worried
3140 * about the case where we're turning the VFTA VLAN ID
3141 * entry bit on, only when requested to turn it off as
3142 * there may be multiple pools and/or VFs using the
3143 * VLAN ID entry. In that case we cannot clear the
3144 * VFTA bit until all pools/VFs using that VLAN ID have also
3145 * been cleared. This will be indicated by "bits" being
3149 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(vlvf_index
),
3150 (IXGBE_VLVF_VIEN
| vlan
));
3152 /* someone wants to clear the vfta entry
3153 * but some pools/VFs are still using it.
3155 vfta_changed
= false;
3158 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(vlvf_index
), 0);
3163 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(regindex
), vfta
);
3169 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3170 * @hw: pointer to hardware structure
3172 * Clears the VLAN filer table, and the VMDq index associated with the filter
3174 s32
ixgbe_clear_vfta_generic(struct ixgbe_hw
*hw
)
3178 for (offset
= 0; offset
< hw
->mac
.vft_size
; offset
++)
3179 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(offset
), 0);
3181 for (offset
= 0; offset
< IXGBE_VLVF_ENTRIES
; offset
++) {
3182 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(offset
), 0);
3183 IXGBE_WRITE_REG(hw
, IXGBE_VLVFB(offset
*2), 0);
3184 IXGBE_WRITE_REG(hw
, IXGBE_VLVFB((offset
*2)+1), 0);
3191 * ixgbe_check_mac_link_generic - Determine link and speed status
3192 * @hw: pointer to hardware structure
3193 * @speed: pointer to link speed
3194 * @link_up: true when link is up
3195 * @link_up_wait_to_complete: bool used to wait for link up or not
3197 * Reads the links register to determine if link is up and the current speed
3199 s32
ixgbe_check_mac_link_generic(struct ixgbe_hw
*hw
, ixgbe_link_speed
*speed
,
3200 bool *link_up
, bool link_up_wait_to_complete
)
3202 u32 links_reg
, links_orig
;
3205 /* clear the old state */
3206 links_orig
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
3208 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
3210 if (links_orig
!= links_reg
) {
3211 hw_dbg(hw
, "LINKS changed from %08X to %08X\n",
3212 links_orig
, links_reg
);
3215 if (link_up_wait_to_complete
) {
3216 for (i
= 0; i
< IXGBE_LINK_UP_TIME
; i
++) {
3217 if (links_reg
& IXGBE_LINKS_UP
) {
3224 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
3227 if (links_reg
& IXGBE_LINKS_UP
)
3233 switch (links_reg
& IXGBE_LINKS_SPEED_82599
) {
3234 case IXGBE_LINKS_SPEED_10G_82599
:
3235 if ((hw
->mac
.type
>= ixgbe_mac_X550
) &&
3236 (links_reg
& IXGBE_LINKS_SPEED_NON_STD
))
3237 *speed
= IXGBE_LINK_SPEED_2_5GB_FULL
;
3239 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
3241 case IXGBE_LINKS_SPEED_1G_82599
:
3242 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
3244 case IXGBE_LINKS_SPEED_100_82599
:
3245 if ((hw
->mac
.type
>= ixgbe_mac_X550
) &&
3246 (links_reg
& IXGBE_LINKS_SPEED_NON_STD
))
3247 *speed
= IXGBE_LINK_SPEED_5GB_FULL
;
3249 *speed
= IXGBE_LINK_SPEED_100_FULL
;
3252 *speed
= IXGBE_LINK_SPEED_UNKNOWN
;
3259 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
3261 * @hw: pointer to hardware structure
3262 * @wwnn_prefix: the alternative WWNN prefix
3263 * @wwpn_prefix: the alternative WWPN prefix
3265 * This function will read the EEPROM from the alternative SAN MAC address
3266 * block to check the support for the alternative WWNN/WWPN prefix support.
3268 s32
ixgbe_get_wwn_prefix_generic(struct ixgbe_hw
*hw
, u16
*wwnn_prefix
,
3272 u16 alt_san_mac_blk_offset
;
3274 /* clear output first */
3275 *wwnn_prefix
= 0xFFFF;
3276 *wwpn_prefix
= 0xFFFF;
3278 /* check if alternative SAN MAC is supported */
3279 offset
= IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR
;
3280 if (hw
->eeprom
.ops
.read(hw
, offset
, &alt_san_mac_blk_offset
))
3281 goto wwn_prefix_err
;
3283 if ((alt_san_mac_blk_offset
== 0) ||
3284 (alt_san_mac_blk_offset
== 0xFFFF))
3287 /* check capability in alternative san mac address block */
3288 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET
;
3289 if (hw
->eeprom
.ops
.read(hw
, offset
, &caps
))
3290 goto wwn_prefix_err
;
3291 if (!(caps
& IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN
))
3294 /* get the corresponding prefix for WWNN/WWPN */
3295 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET
;
3296 if (hw
->eeprom
.ops
.read(hw
, offset
, wwnn_prefix
))
3297 hw_err(hw
, "eeprom read at offset %d failed\n", offset
);
3299 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET
;
3300 if (hw
->eeprom
.ops
.read(hw
, offset
, wwpn_prefix
))
3301 goto wwn_prefix_err
;
3306 hw_err(hw
, "eeprom read at offset %d failed\n", offset
);
3311 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3312 * @hw: pointer to hardware structure
3313 * @enable: enable or disable switch for anti-spoofing
3314 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3317 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw
*hw
, bool enable
, int pf
)
3320 int pf_target_reg
= pf
>> 3;
3321 int pf_target_shift
= pf
% 8;
3324 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3328 pfvfspoof
= IXGBE_SPOOF_MACAS_MASK
;
3331 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3332 * MAC anti-spoof enables in each register array element.
3334 for (j
= 0; j
< pf_target_reg
; j
++)
3335 IXGBE_WRITE_REG(hw
, IXGBE_PFVFSPOOF(j
), pfvfspoof
);
3338 * The PF should be allowed to spoof so that it can support
3339 * emulation mode NICs. Do not set the bits assigned to the PF
3341 pfvfspoof
&= (1 << pf_target_shift
) - 1;
3342 IXGBE_WRITE_REG(hw
, IXGBE_PFVFSPOOF(j
), pfvfspoof
);
3345 * Remaining pools belong to the PF so they do not need to have
3346 * anti-spoofing enabled.
3348 for (j
++; j
< IXGBE_PFVFSPOOF_REG_COUNT
; j
++)
3349 IXGBE_WRITE_REG(hw
, IXGBE_PFVFSPOOF(j
), 0);
3353 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3354 * @hw: pointer to hardware structure
3355 * @enable: enable or disable switch for VLAN anti-spoofing
3356 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3359 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw
*hw
, bool enable
, int vf
)
3361 int vf_target_reg
= vf
>> 3;
3362 int vf_target_shift
= vf
% 8 + IXGBE_SPOOF_VLANAS_SHIFT
;
3365 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3368 pfvfspoof
= IXGBE_READ_REG(hw
, IXGBE_PFVFSPOOF(vf_target_reg
));
3370 pfvfspoof
|= (1 << vf_target_shift
);
3372 pfvfspoof
&= ~(1 << vf_target_shift
);
3373 IXGBE_WRITE_REG(hw
, IXGBE_PFVFSPOOF(vf_target_reg
), pfvfspoof
);
3377 * ixgbe_get_device_caps_generic - Get additional device capabilities
3378 * @hw: pointer to hardware structure
3379 * @device_caps: the EEPROM word with the extra device capabilities
3381 * This function will read the EEPROM location for the device capabilities,
3382 * and return the word through device_caps.
3384 s32
ixgbe_get_device_caps_generic(struct ixgbe_hw
*hw
, u16
*device_caps
)
3386 hw
->eeprom
.ops
.read(hw
, IXGBE_DEVICE_CAPS
, device_caps
);
3392 * ixgbe_set_rxpba_generic - Initialize RX packet buffer
3393 * @hw: pointer to hardware structure
3394 * @num_pb: number of packet buffers to allocate
3395 * @headroom: reserve n KB of headroom
3396 * @strategy: packet buffer allocation strategy
3398 void ixgbe_set_rxpba_generic(struct ixgbe_hw
*hw
,
3403 u32 pbsize
= hw
->mac
.rx_pb_size
;
3405 u32 rxpktsize
, txpktsize
, txpbthresh
;
3407 /* Reserve headroom */
3413 /* Divide remaining packet buffer space amongst the number
3414 * of packet buffers requested using supplied strategy.
3417 case (PBA_STRATEGY_WEIGHTED
):
3418 /* pba_80_48 strategy weight first half of packet buffer with
3419 * 5/8 of the packet buffer space.
3421 rxpktsize
= ((pbsize
* 5 * 2) / (num_pb
* 8));
3422 pbsize
-= rxpktsize
* (num_pb
/ 2);
3423 rxpktsize
<<= IXGBE_RXPBSIZE_SHIFT
;
3424 for (; i
< (num_pb
/ 2); i
++)
3425 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), rxpktsize
);
3426 /* Fall through to configure remaining packet buffers */
3427 case (PBA_STRATEGY_EQUAL
):
3428 /* Divide the remaining Rx packet buffer evenly among the TCs */
3429 rxpktsize
= (pbsize
/ (num_pb
- i
)) << IXGBE_RXPBSIZE_SHIFT
;
3430 for (; i
< num_pb
; i
++)
3431 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), rxpktsize
);
3438 * Setup Tx packet buffer and threshold equally for all TCs
3439 * TXPBTHRESH register is set in K so divide by 1024 and subtract
3440 * 10 since the largest packet we support is just over 9K.
3442 txpktsize
= IXGBE_TXPBSIZE_MAX
/ num_pb
;
3443 txpbthresh
= (txpktsize
/ 1024) - IXGBE_TXPKT_SIZE_MAX
;
3444 for (i
= 0; i
< num_pb
; i
++) {
3445 IXGBE_WRITE_REG(hw
, IXGBE_TXPBSIZE(i
), txpktsize
);
3446 IXGBE_WRITE_REG(hw
, IXGBE_TXPBTHRESH(i
), txpbthresh
);
3449 /* Clear unused TCs, if any, to zero buffer size*/
3450 for (; i
< IXGBE_MAX_PB
; i
++) {
3451 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), 0);
3452 IXGBE_WRITE_REG(hw
, IXGBE_TXPBSIZE(i
), 0);
3453 IXGBE_WRITE_REG(hw
, IXGBE_TXPBTHRESH(i
), 0);
3458 * ixgbe_calculate_checksum - Calculate checksum for buffer
3459 * @buffer: pointer to EEPROM
3460 * @length: size of EEPROM to calculate a checksum for
3462 * Calculates the checksum for some buffer on a specified length. The
3463 * checksum calculated is returned.
3465 static u8
ixgbe_calculate_checksum(u8
*buffer
, u32 length
)
3473 for (i
= 0; i
< length
; i
++)
3476 return (u8
) (0 - sum
);
3480 * ixgbe_host_interface_command - Issue command to manageability block
3481 * @hw: pointer to the HW structure
3482 * @buffer: contains the command to write and where the return status will
3484 * @length: length of buffer, must be multiple of 4 bytes
3485 * @timeout: time in ms to wait for command completion
3486 * @return_data: read and return data from the buffer (true) or not (false)
3487 * Needed because FW structures are big endian and decoding of
3488 * these fields can be 8 bit or 16 bit based on command. Decoding
3489 * is not easily understood without making a table of commands.
3490 * So we will leave this up to the caller to read back the data
3493 * Communicates with the manageability block. On success return 0
3494 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3496 s32
ixgbe_host_interface_command(struct ixgbe_hw
*hw
, u32
*buffer
,
3497 u32 length
, u32 timeout
,
3500 u32 hicr
, i
, bi
, fwsts
;
3501 u32 hdr_size
= sizeof(struct ixgbe_hic_hdr
);
3502 u16 buf_len
, dword_len
;
3504 if (length
== 0 || length
> IXGBE_HI_MAX_BLOCK_BYTE_LENGTH
) {
3505 hw_dbg(hw
, "Buffer length failure buffersize-%d.\n", length
);
3506 return IXGBE_ERR_HOST_INTERFACE_COMMAND
;
3509 /* Set bit 9 of FWSTS clearing FW reset indication */
3510 fwsts
= IXGBE_READ_REG(hw
, IXGBE_FWSTS
);
3511 IXGBE_WRITE_REG(hw
, IXGBE_FWSTS
, fwsts
| IXGBE_FWSTS_FWRI
);
3513 /* Check that the host interface is enabled. */
3514 hicr
= IXGBE_READ_REG(hw
, IXGBE_HICR
);
3515 if ((hicr
& IXGBE_HICR_EN
) == 0) {
3516 hw_dbg(hw
, "IXGBE_HOST_EN bit disabled.\n");
3517 return IXGBE_ERR_HOST_INTERFACE_COMMAND
;
3520 /* Calculate length in DWORDs. We must be DWORD aligned */
3521 if ((length
% (sizeof(u32
))) != 0) {
3522 hw_dbg(hw
, "Buffer length failure, not aligned to dword");
3523 return IXGBE_ERR_INVALID_ARGUMENT
;
3526 dword_len
= length
>> 2;
3529 * The device driver writes the relevant command block
3530 * into the ram area.
3532 for (i
= 0; i
< dword_len
; i
++)
3533 IXGBE_WRITE_REG_ARRAY(hw
, IXGBE_FLEX_MNG
,
3534 i
, cpu_to_le32(buffer
[i
]));
3536 /* Setting this bit tells the ARC that a new command is pending. */
3537 IXGBE_WRITE_REG(hw
, IXGBE_HICR
, hicr
| IXGBE_HICR_C
);
3539 for (i
= 0; i
< timeout
; i
++) {
3540 hicr
= IXGBE_READ_REG(hw
, IXGBE_HICR
);
3541 if (!(hicr
& IXGBE_HICR_C
))
3543 usleep_range(1000, 2000);
3546 /* Check command successful completion. */
3547 if ((timeout
!= 0 && i
== timeout
) ||
3548 (!(IXGBE_READ_REG(hw
, IXGBE_HICR
) & IXGBE_HICR_SV
))) {
3549 hw_dbg(hw
, "Command has failed with no status valid.\n");
3550 return IXGBE_ERR_HOST_INTERFACE_COMMAND
;
3556 /* Calculate length in DWORDs */
3557 dword_len
= hdr_size
>> 2;
3559 /* first pull in the header so we know the buffer length */
3560 for (bi
= 0; bi
< dword_len
; bi
++) {
3561 buffer
[bi
] = IXGBE_READ_REG_ARRAY(hw
, IXGBE_FLEX_MNG
, bi
);
3562 le32_to_cpus(&buffer
[bi
]);
3565 /* If there is any thing in data position pull it in */
3566 buf_len
= ((struct ixgbe_hic_hdr
*)buffer
)->buf_len
;
3570 if (length
< (buf_len
+ hdr_size
)) {
3571 hw_dbg(hw
, "Buffer not large enough for reply message.\n");
3572 return IXGBE_ERR_HOST_INTERFACE_COMMAND
;
3575 /* Calculate length in DWORDs, add 3 for odd lengths */
3576 dword_len
= (buf_len
+ 3) >> 2;
3578 /* Pull in the rest of the buffer (bi is where we left off)*/
3579 for (; bi
<= dword_len
; bi
++) {
3580 buffer
[bi
] = IXGBE_READ_REG_ARRAY(hw
, IXGBE_FLEX_MNG
, bi
);
3581 le32_to_cpus(&buffer
[bi
]);
3588 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3589 * @hw: pointer to the HW structure
3590 * @maj: driver version major number
3591 * @min: driver version minor number
3592 * @build: driver version build number
3593 * @sub: driver version sub build number
3595 * Sends driver version number to firmware through the manageability
3596 * block. On success return 0
3597 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3598 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3600 s32
ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw
*hw
, u8 maj
, u8 min
,
3603 struct ixgbe_hic_drv_info fw_cmd
;
3607 if (hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_SW_MNG_SM
))
3608 return IXGBE_ERR_SWFW_SYNC
;
3610 fw_cmd
.hdr
.cmd
= FW_CEM_CMD_DRIVER_INFO
;
3611 fw_cmd
.hdr
.buf_len
= FW_CEM_CMD_DRIVER_INFO_LEN
;
3612 fw_cmd
.hdr
.cmd_or_resp
.cmd_resv
= FW_CEM_CMD_RESERVED
;
3613 fw_cmd
.port_num
= (u8
)hw
->bus
.func
;
3614 fw_cmd
.ver_maj
= maj
;
3615 fw_cmd
.ver_min
= min
;
3616 fw_cmd
.ver_build
= build
;
3617 fw_cmd
.ver_sub
= sub
;
3618 fw_cmd
.hdr
.checksum
= 0;
3619 fw_cmd
.hdr
.checksum
= ixgbe_calculate_checksum((u8
*)&fw_cmd
,
3620 (FW_CEM_HDR_LEN
+ fw_cmd
.hdr
.buf_len
));
3624 for (i
= 0; i
<= FW_CEM_MAX_RETRIES
; i
++) {
3625 ret_val
= ixgbe_host_interface_command(hw
, (u32
*)&fw_cmd
,
3627 IXGBE_HI_COMMAND_TIMEOUT
,
3632 if (fw_cmd
.hdr
.cmd_or_resp
.ret_status
==
3633 FW_CEM_RESP_STATUS_SUCCESS
)
3636 ret_val
= IXGBE_ERR_HOST_INTERFACE_COMMAND
;
3641 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_SW_MNG_SM
);
3646 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3647 * @hw: pointer to the hardware structure
3649 * The 82599 and x540 MACs can experience issues if TX work is still pending
3650 * when a reset occurs. This function prevents this by flushing the PCIe
3651 * buffers on the system.
3653 void ixgbe_clear_tx_pending(struct ixgbe_hw
*hw
)
3655 u32 gcr_ext
, hlreg0
, i
, poll
;
3659 * If double reset is not requested then all transactions should
3660 * already be clear and as such there is no work to do
3662 if (!(hw
->mac
.flags
& IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
))
3666 * Set loopback enable to prevent any transmits from being sent
3667 * should the link come up. This assumes that the RXCTRL.RXEN bit
3668 * has already been cleared.
3670 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
3671 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
| IXGBE_HLREG0_LPBK
);
3673 /* wait for a last completion before clearing buffers */
3674 IXGBE_WRITE_FLUSH(hw
);
3675 usleep_range(3000, 6000);
3677 /* Before proceeding, make sure that the PCIe block does not have
3678 * transactions pending.
3680 poll
= ixgbe_pcie_timeout_poll(hw
);
3681 for (i
= 0; i
< poll
; i
++) {
3682 usleep_range(100, 200);
3683 value
= ixgbe_read_pci_cfg_word(hw
, IXGBE_PCI_DEVICE_STATUS
);
3684 if (ixgbe_removed(hw
->hw_addr
))
3686 if (!(value
& IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING
))
3690 /* initiate cleaning flow for buffers in the PCIe transaction layer */
3691 gcr_ext
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
3692 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
,
3693 gcr_ext
| IXGBE_GCR_EXT_BUFFERS_CLEAR
);
3695 /* Flush all writes and allow 20usec for all transactions to clear */
3696 IXGBE_WRITE_FLUSH(hw
);
3699 /* restore previous register values */
3700 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr_ext
);
3701 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
3704 static const u8 ixgbe_emc_temp_data
[4] = {
3705 IXGBE_EMC_INTERNAL_DATA
,
3706 IXGBE_EMC_DIODE1_DATA
,
3707 IXGBE_EMC_DIODE2_DATA
,
3708 IXGBE_EMC_DIODE3_DATA
3710 static const u8 ixgbe_emc_therm_limit
[4] = {
3711 IXGBE_EMC_INTERNAL_THERM_LIMIT
,
3712 IXGBE_EMC_DIODE1_THERM_LIMIT
,
3713 IXGBE_EMC_DIODE2_THERM_LIMIT
,
3714 IXGBE_EMC_DIODE3_THERM_LIMIT
3718 * ixgbe_get_ets_data - Extracts the ETS bit data
3719 * @hw: pointer to hardware structure
3720 * @ets_cfg: extected ETS data
3721 * @ets_offset: offset of ETS data
3723 * Returns error code.
3725 static s32
ixgbe_get_ets_data(struct ixgbe_hw
*hw
, u16
*ets_cfg
,
3730 status
= hw
->eeprom
.ops
.read(hw
, IXGBE_ETS_CFG
, ets_offset
);
3734 if ((*ets_offset
== 0x0000) || (*ets_offset
== 0xFFFF))
3735 return IXGBE_NOT_IMPLEMENTED
;
3737 status
= hw
->eeprom
.ops
.read(hw
, *ets_offset
, ets_cfg
);
3741 if ((*ets_cfg
& IXGBE_ETS_TYPE_MASK
) != IXGBE_ETS_TYPE_EMC_SHIFTED
)
3742 return IXGBE_NOT_IMPLEMENTED
;
3748 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
3749 * @hw: pointer to hardware structure
3751 * Returns the thermal sensor data structure
3753 s32
ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw
*hw
)
3761 struct ixgbe_thermal_sensor_data
*data
= &hw
->mac
.thermal_sensor_data
;
3763 /* Only support thermal sensors attached to physical port 0 */
3764 if ((IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_LAN_ID_1
))
3765 return IXGBE_NOT_IMPLEMENTED
;
3767 status
= ixgbe_get_ets_data(hw
, &ets_cfg
, &ets_offset
);
3771 num_sensors
= (ets_cfg
& IXGBE_ETS_NUM_SENSORS_MASK
);
3772 if (num_sensors
> IXGBE_MAX_SENSORS
)
3773 num_sensors
= IXGBE_MAX_SENSORS
;
3775 for (i
= 0; i
< num_sensors
; i
++) {
3779 status
= hw
->eeprom
.ops
.read(hw
, (ets_offset
+ 1 + i
),
3784 sensor_index
= ((ets_sensor
& IXGBE_ETS_DATA_INDEX_MASK
) >>
3785 IXGBE_ETS_DATA_INDEX_SHIFT
);
3786 sensor_location
= ((ets_sensor
& IXGBE_ETS_DATA_LOC_MASK
) >>
3787 IXGBE_ETS_DATA_LOC_SHIFT
);
3789 if (sensor_location
!= 0) {
3790 status
= hw
->phy
.ops
.read_i2c_byte(hw
,
3791 ixgbe_emc_temp_data
[sensor_index
],
3792 IXGBE_I2C_THERMAL_SENSOR_ADDR
,
3793 &data
->sensor
[i
].temp
);
3803 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
3804 * @hw: pointer to hardware structure
3806 * Inits the thermal sensor thresholds according to the NVM map
3807 * and save off the threshold and location values into mac.thermal_sensor_data
3809 s32
ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw
*hw
)
3815 u8 low_thresh_delta
;
3819 struct ixgbe_thermal_sensor_data
*data
= &hw
->mac
.thermal_sensor_data
;
3821 memset(data
, 0, sizeof(struct ixgbe_thermal_sensor_data
));
3823 /* Only support thermal sensors attached to physical port 0 */
3824 if ((IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_LAN_ID_1
))
3825 return IXGBE_NOT_IMPLEMENTED
;
3827 status
= ixgbe_get_ets_data(hw
, &ets_cfg
, &ets_offset
);
3831 low_thresh_delta
= ((ets_cfg
& IXGBE_ETS_LTHRES_DELTA_MASK
) >>
3832 IXGBE_ETS_LTHRES_DELTA_SHIFT
);
3833 num_sensors
= (ets_cfg
& IXGBE_ETS_NUM_SENSORS_MASK
);
3834 if (num_sensors
> IXGBE_MAX_SENSORS
)
3835 num_sensors
= IXGBE_MAX_SENSORS
;
3837 for (i
= 0; i
< num_sensors
; i
++) {
3841 if (hw
->eeprom
.ops
.read(hw
, ets_offset
+ 1 + i
, &ets_sensor
)) {
3842 hw_err(hw
, "eeprom read at offset %d failed\n",
3843 ets_offset
+ 1 + i
);
3846 sensor_index
= ((ets_sensor
& IXGBE_ETS_DATA_INDEX_MASK
) >>
3847 IXGBE_ETS_DATA_INDEX_SHIFT
);
3848 sensor_location
= ((ets_sensor
& IXGBE_ETS_DATA_LOC_MASK
) >>
3849 IXGBE_ETS_DATA_LOC_SHIFT
);
3850 therm_limit
= ets_sensor
& IXGBE_ETS_DATA_HTHRESH_MASK
;
3852 hw
->phy
.ops
.write_i2c_byte(hw
,
3853 ixgbe_emc_therm_limit
[sensor_index
],
3854 IXGBE_I2C_THERMAL_SENSOR_ADDR
, therm_limit
);
3856 if (sensor_location
== 0)
3859 data
->sensor
[i
].location
= sensor_location
;
3860 data
->sensor
[i
].caution_thresh
= therm_limit
;
3861 data
->sensor
[i
].max_op_thresh
= therm_limit
- low_thresh_delta
;
3867 void ixgbe_disable_rx_generic(struct ixgbe_hw
*hw
)
3871 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3872 if (rxctrl
& IXGBE_RXCTRL_RXEN
) {
3873 if (hw
->mac
.type
!= ixgbe_mac_82598EB
) {
3876 pfdtxgswc
= IXGBE_READ_REG(hw
, IXGBE_PFDTXGSWC
);
3877 if (pfdtxgswc
& IXGBE_PFDTXGSWC_VT_LBEN
) {
3878 pfdtxgswc
&= ~IXGBE_PFDTXGSWC_VT_LBEN
;
3879 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, pfdtxgswc
);
3880 hw
->mac
.set_lben
= true;
3882 hw
->mac
.set_lben
= false;
3885 rxctrl
&= ~IXGBE_RXCTRL_RXEN
;
3886 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
);
3890 void ixgbe_enable_rx_generic(struct ixgbe_hw
*hw
)
3894 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3895 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, (rxctrl
| IXGBE_RXCTRL_RXEN
));
3897 if (hw
->mac
.type
!= ixgbe_mac_82598EB
) {
3898 if (hw
->mac
.set_lben
) {
3901 pfdtxgswc
= IXGBE_READ_REG(hw
, IXGBE_PFDTXGSWC
);
3902 pfdtxgswc
|= IXGBE_PFDTXGSWC_VT_LBEN
;
3903 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, pfdtxgswc
);
3904 hw
->mac
.set_lben
= false;
3909 /** ixgbe_mng_present - returns true when management capability is present
3910 * @hw: pointer to hardware structure
3912 bool ixgbe_mng_present(struct ixgbe_hw
*hw
)
3916 if (hw
->mac
.type
< ixgbe_mac_82599EB
)
3919 fwsm
= IXGBE_READ_REG(hw
, IXGBE_FWSM(hw
));
3920 fwsm
&= IXGBE_FWSM_MODE_MASK
;
3921 return fwsm
== IXGBE_FWSM_FW_MODE_PT
;
3925 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
3926 * @hw: pointer to hardware structure
3927 * @speed: new link speed
3928 * @autoneg_wait_to_complete: true when waiting for completion is needed
3930 * Set the link speed in the MAC and/or PHY register and restarts link.
3932 s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
3933 ixgbe_link_speed speed
,
3934 bool autoneg_wait_to_complete
)
3936 ixgbe_link_speed link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
3937 ixgbe_link_speed highest_link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
3941 bool autoneg
, link_up
= false;
3943 /* Mask off requested but non-supported speeds */
3944 status
= hw
->mac
.ops
.get_link_capabilities(hw
, &link_speed
, &autoneg
);
3948 speed
&= link_speed
;
3950 /* Try each speed one by one, highest priority first. We do this in
3951 * software because 10Gb fiber doesn't support speed autonegotiation.
3953 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
) {
3955 highest_link_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
3957 /* If we already have link at this speed, just jump out */
3958 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
3963 if (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
&& link_up
)
3966 /* Set the module link speed */
3967 switch (hw
->phy
.media_type
) {
3968 case ixgbe_media_type_fiber
:
3969 hw
->mac
.ops
.set_rate_select_speed(hw
,
3970 IXGBE_LINK_SPEED_10GB_FULL
);
3972 case ixgbe_media_type_fiber_qsfp
:
3973 /* QSFP module automatically detects MAC link speed */
3976 hw_dbg(hw
, "Unexpected media type\n");
3980 /* Allow module to change analog characteristics (1G->10G) */
3983 status
= hw
->mac
.ops
.setup_mac_link(hw
,
3984 IXGBE_LINK_SPEED_10GB_FULL
,
3985 autoneg_wait_to_complete
);
3989 /* Flap the Tx laser if it has not already been done */
3990 if (hw
->mac
.ops
.flap_tx_laser
)
3991 hw
->mac
.ops
.flap_tx_laser(hw
);
3993 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
3994 * Section 73.10.2, we may have to wait up to 500ms if KR is
3995 * attempted. 82599 uses the same timing for 10g SFI.
3997 for (i
= 0; i
< 5; i
++) {
3998 /* Wait for the link partner to also set speed */
4001 /* If we have link, just jump out */
4002 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
,
4012 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
) {
4014 if (highest_link_speed
== IXGBE_LINK_SPEED_UNKNOWN
)
4015 highest_link_speed
= IXGBE_LINK_SPEED_1GB_FULL
;
4017 /* If we already have link at this speed, just jump out */
4018 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
4023 if (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
&& link_up
)
4026 /* Set the module link speed */
4027 switch (hw
->phy
.media_type
) {
4028 case ixgbe_media_type_fiber
:
4029 hw
->mac
.ops
.set_rate_select_speed(hw
,
4030 IXGBE_LINK_SPEED_1GB_FULL
);
4032 case ixgbe_media_type_fiber_qsfp
:
4033 /* QSFP module automatically detects link speed */
4036 hw_dbg(hw
, "Unexpected media type\n");
4040 /* Allow module to change analog characteristics (10G->1G) */
4043 status
= hw
->mac
.ops
.setup_mac_link(hw
,
4044 IXGBE_LINK_SPEED_1GB_FULL
,
4045 autoneg_wait_to_complete
);
4049 /* Flap the Tx laser if it has not already been done */
4050 if (hw
->mac
.ops
.flap_tx_laser
)
4051 hw
->mac
.ops
.flap_tx_laser(hw
);
4053 /* Wait for the link partner to also set speed */
4056 /* If we have link, just jump out */
4057 status
= hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
,
4066 /* We didn't get link. Configure back to the highest speed we tried,
4067 * (if there was more than one). We call ourselves back with just the
4068 * single highest speed that the user requested.
4071 status
= ixgbe_setup_mac_link_multispeed_fiber(hw
,
4073 autoneg_wait_to_complete
);
4076 /* Set autoneg_advertised value based on input link speed */
4077 hw
->phy
.autoneg_advertised
= 0;
4079 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
4080 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
4082 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
4083 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
4089 * ixgbe_set_soft_rate_select_speed - Set module link speed
4090 * @hw: pointer to hardware structure
4091 * @speed: link speed to set
4093 * Set module link speed via the soft rate select.
4095 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw
*hw
,
4096 ixgbe_link_speed speed
)
4102 case IXGBE_LINK_SPEED_10GB_FULL
:
4103 /* one bit mask same as setting on */
4104 rs
= IXGBE_SFF_SOFT_RS_SELECT_10G
;
4106 case IXGBE_LINK_SPEED_1GB_FULL
:
4107 rs
= IXGBE_SFF_SOFT_RS_SELECT_1G
;
4110 hw_dbg(hw
, "Invalid fixed module speed\n");
4115 status
= hw
->phy
.ops
.read_i2c_byte(hw
, IXGBE_SFF_SFF_8472_OSCB
,
4116 IXGBE_I2C_EEPROM_DEV_ADDR2
,
4119 hw_dbg(hw
, "Failed to read Rx Rate Select RS0\n");
4123 eeprom_data
= (eeprom_data
& ~IXGBE_SFF_SOFT_RS_SELECT_MASK
) | rs
;
4125 status
= hw
->phy
.ops
.write_i2c_byte(hw
, IXGBE_SFF_SFF_8472_OSCB
,
4126 IXGBE_I2C_EEPROM_DEV_ADDR2
,
4129 hw_dbg(hw
, "Failed to write Rx Rate Select RS0\n");