1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31 #include <linux/netdevice.h>
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
37 static s32
ixgbe_acquire_eeprom(struct ixgbe_hw
*hw
);
38 static s32
ixgbe_get_eeprom_semaphore(struct ixgbe_hw
*hw
);
39 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw
*hw
);
40 static s32
ixgbe_ready_eeprom(struct ixgbe_hw
*hw
);
41 static void ixgbe_standby_eeprom(struct ixgbe_hw
*hw
);
42 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw
*hw
, u16 data
,
44 static u16
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw
*hw
, u16 count
);
45 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
);
46 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
);
47 static void ixgbe_release_eeprom(struct ixgbe_hw
*hw
);
49 static s32
ixgbe_mta_vector(struct ixgbe_hw
*hw
, u8
*mc_addr
);
50 static s32
ixgbe_poll_eerd_eewr_done(struct ixgbe_hw
*hw
, u32 ee_reg
);
51 static s32
ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw
*hw
, u16 offset
,
52 u16 words
, u16
*data
);
53 static s32
ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw
*hw
, u16 offset
,
54 u16 words
, u16
*data
);
55 static s32
ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw
*hw
,
57 static s32
ixgbe_disable_pcie_master(struct ixgbe_hw
*hw
);
60 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
62 * @hw: pointer to hardware structure
64 * There are several phys that do not support autoneg flow control. This
65 * function check the device id to see if the associated phy supports
66 * autoneg flow control.
68 static s32
ixgbe_device_supports_autoneg_fc(struct ixgbe_hw
*hw
)
71 switch (hw
->device_id
) {
72 case IXGBE_DEV_ID_X540T
:
74 case IXGBE_DEV_ID_82599_T3_LOM
:
77 return IXGBE_ERR_FC_NOT_SUPPORTED
;
82 * ixgbe_setup_fc - Set up flow control
83 * @hw: pointer to hardware structure
85 * Called at init time to set up flow control.
87 static s32
ixgbe_setup_fc(struct ixgbe_hw
*hw
)
90 u32 reg
= 0, reg_bp
= 0;
94 * Validate the requested mode. Strict IEEE mode does not allow
95 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
97 if (hw
->fc
.strict_ieee
&& hw
->fc
.requested_mode
== ixgbe_fc_rx_pause
) {
98 hw_dbg(hw
, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
99 ret_val
= IXGBE_ERR_INVALID_LINK_SETTINGS
;
104 * 10gig parts do not have a word in the EEPROM to determine the
105 * default flow control setting, so we explicitly set it to full.
107 if (hw
->fc
.requested_mode
== ixgbe_fc_default
)
108 hw
->fc
.requested_mode
= ixgbe_fc_full
;
111 * Set up the 1G and 10G flow control advertisement registers so the
112 * HW will be able to do fc autoneg once the cable is plugged in. If
113 * we link at 10G, the 1G advertisement is harmless and vice versa.
115 switch (hw
->phy
.media_type
) {
116 case ixgbe_media_type_fiber
:
117 case ixgbe_media_type_backplane
:
118 reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANA
);
119 reg_bp
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
121 case ixgbe_media_type_copper
:
122 hw
->phy
.ops
.read_reg(hw
, MDIO_AN_ADVERTISE
,
123 MDIO_MMD_AN
, ®_cu
);
130 * The possible values of fc.requested_mode are:
131 * 0: Flow control is completely disabled
132 * 1: Rx flow control is enabled (we can receive pause frames,
133 * but not send pause frames).
134 * 2: Tx flow control is enabled (we can send pause frames but
135 * we do not support receiving pause frames).
136 * 3: Both Rx and Tx flow control (symmetric) are enabled.
139 switch (hw
->fc
.requested_mode
) {
141 /* Flow control completely disabled by software override. */
142 reg
&= ~(IXGBE_PCS1GANA_SYM_PAUSE
| IXGBE_PCS1GANA_ASM_PAUSE
);
143 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
)
144 reg_bp
&= ~(IXGBE_AUTOC_SYM_PAUSE
|
145 IXGBE_AUTOC_ASM_PAUSE
);
146 else if (hw
->phy
.media_type
== ixgbe_media_type_copper
)
147 reg_cu
&= ~(IXGBE_TAF_SYM_PAUSE
| IXGBE_TAF_ASM_PAUSE
);
149 case ixgbe_fc_tx_pause
:
151 * Tx Flow control is enabled, and Rx Flow control is
152 * disabled by software override.
154 reg
|= IXGBE_PCS1GANA_ASM_PAUSE
;
155 reg
&= ~IXGBE_PCS1GANA_SYM_PAUSE
;
156 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
) {
157 reg_bp
|= IXGBE_AUTOC_ASM_PAUSE
;
158 reg_bp
&= ~IXGBE_AUTOC_SYM_PAUSE
;
159 } else if (hw
->phy
.media_type
== ixgbe_media_type_copper
) {
160 reg_cu
|= IXGBE_TAF_ASM_PAUSE
;
161 reg_cu
&= ~IXGBE_TAF_SYM_PAUSE
;
164 case ixgbe_fc_rx_pause
:
166 * Rx Flow control is enabled and Tx Flow control is
167 * disabled by software override. Since there really
168 * isn't a way to advertise that we are capable of RX
169 * Pause ONLY, we will advertise that we support both
170 * symmetric and asymmetric Rx PAUSE, as such we fall
171 * through to the fc_full statement. Later, we will
172 * disable the adapter's ability to send PAUSE frames.
175 /* Flow control (both Rx and Tx) is enabled by SW override. */
176 reg
|= IXGBE_PCS1GANA_SYM_PAUSE
| IXGBE_PCS1GANA_ASM_PAUSE
;
177 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
)
178 reg_bp
|= IXGBE_AUTOC_SYM_PAUSE
|
179 IXGBE_AUTOC_ASM_PAUSE
;
180 else if (hw
->phy
.media_type
== ixgbe_media_type_copper
)
181 reg_cu
|= IXGBE_TAF_SYM_PAUSE
| IXGBE_TAF_ASM_PAUSE
;
184 hw_dbg(hw
, "Flow control param set incorrectly\n");
185 ret_val
= IXGBE_ERR_CONFIG
;
190 if (hw
->mac
.type
!= ixgbe_mac_X540
) {
192 * Enable auto-negotiation between the MAC & PHY;
193 * the MAC will advertise clause 37 flow control.
195 IXGBE_WRITE_REG(hw
, IXGBE_PCS1GANA
, reg
);
196 reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GLCTL
);
198 /* Disable AN timeout */
199 if (hw
->fc
.strict_ieee
)
200 reg
&= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN
;
202 IXGBE_WRITE_REG(hw
, IXGBE_PCS1GLCTL
, reg
);
203 hw_dbg(hw
, "Set up FC; PCS1GLCTL = 0x%08X\n", reg
);
207 * AUTOC restart handles negotiation of 1G and 10G on backplane
208 * and copper. There is no need to set the PCS1GCTL register.
211 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
) {
212 reg_bp
|= IXGBE_AUTOC_AN_RESTART
;
213 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, reg_bp
);
214 } else if ((hw
->phy
.media_type
== ixgbe_media_type_copper
) &&
215 (ixgbe_device_supports_autoneg_fc(hw
) == 0)) {
216 hw
->phy
.ops
.write_reg(hw
, MDIO_AN_ADVERTISE
,
217 MDIO_MMD_AN
, reg_cu
);
220 hw_dbg(hw
, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg
);
226 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
227 * @hw: pointer to hardware structure
229 * Starts the hardware by filling the bus info structure and media type, clears
230 * all on chip counters, initializes receive address registers, multicast
231 * table, VLAN filter table, calls routine to set up link and flow control
232 * settings, and leaves transmit and receive units disabled and uninitialized
234 s32
ixgbe_start_hw_generic(struct ixgbe_hw
*hw
)
238 /* Set the media type */
239 hw
->phy
.media_type
= hw
->mac
.ops
.get_media_type(hw
);
241 /* Identify the PHY */
242 hw
->phy
.ops
.identify(hw
);
244 /* Clear the VLAN filter table */
245 hw
->mac
.ops
.clear_vfta(hw
);
247 /* Clear statistics registers */
248 hw
->mac
.ops
.clear_hw_cntrs(hw
);
250 /* Set No Snoop Disable */
251 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
252 ctrl_ext
|= IXGBE_CTRL_EXT_NS_DIS
;
253 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
254 IXGBE_WRITE_FLUSH(hw
);
256 /* Setup flow control */
259 /* Clear adapter stopped flag */
260 hw
->adapter_stopped
= false;
266 * ixgbe_start_hw_gen2 - Init sequence for common device family
267 * @hw: pointer to hw structure
269 * Performs the init sequence common to the second generation
271 * Devices in the second generation:
275 s32
ixgbe_start_hw_gen2(struct ixgbe_hw
*hw
)
280 /* Clear the rate limiters */
281 for (i
= 0; i
< hw
->mac
.max_tx_queues
; i
++) {
282 IXGBE_WRITE_REG(hw
, IXGBE_RTTDQSEL
, i
);
283 IXGBE_WRITE_REG(hw
, IXGBE_RTTBCNRC
, 0);
285 IXGBE_WRITE_FLUSH(hw
);
287 /* Disable relaxed ordering */
288 for (i
= 0; i
< hw
->mac
.max_tx_queues
; i
++) {
289 regval
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(i
));
290 regval
&= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN
;
291 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(i
), regval
);
294 for (i
= 0; i
< hw
->mac
.max_rx_queues
; i
++) {
295 regval
= IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(i
));
296 regval
&= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN
|
297 IXGBE_DCA_RXCTRL_HEAD_WRO_EN
);
298 IXGBE_WRITE_REG(hw
, IXGBE_DCA_RXCTRL(i
), regval
);
305 * ixgbe_init_hw_generic - Generic hardware initialization
306 * @hw: pointer to hardware structure
308 * Initialize the hardware by resetting the hardware, filling the bus info
309 * structure and media type, clears all on chip counters, initializes receive
310 * address registers, multicast table, VLAN filter table, calls routine to set
311 * up link and flow control settings, and leaves transmit and receive units
312 * disabled and uninitialized
314 s32
ixgbe_init_hw_generic(struct ixgbe_hw
*hw
)
318 /* Reset the hardware */
319 status
= hw
->mac
.ops
.reset_hw(hw
);
323 status
= hw
->mac
.ops
.start_hw(hw
);
330 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
331 * @hw: pointer to hardware structure
333 * Clears all hardware statistics counters by reading them from the hardware
334 * Statistics counters are clear on read.
336 s32
ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw
*hw
)
340 IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
341 IXGBE_READ_REG(hw
, IXGBE_ILLERRC
);
342 IXGBE_READ_REG(hw
, IXGBE_ERRBC
);
343 IXGBE_READ_REG(hw
, IXGBE_MSPDC
);
344 for (i
= 0; i
< 8; i
++)
345 IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
347 IXGBE_READ_REG(hw
, IXGBE_MLFC
);
348 IXGBE_READ_REG(hw
, IXGBE_MRFC
);
349 IXGBE_READ_REG(hw
, IXGBE_RLEC
);
350 IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
351 IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
352 if (hw
->mac
.type
>= ixgbe_mac_82599EB
) {
353 IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
354 IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
356 IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
357 IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
360 for (i
= 0; i
< 8; i
++) {
361 IXGBE_READ_REG(hw
, IXGBE_PXONTXC(i
));
362 IXGBE_READ_REG(hw
, IXGBE_PXOFFTXC(i
));
363 if (hw
->mac
.type
>= ixgbe_mac_82599EB
) {
364 IXGBE_READ_REG(hw
, IXGBE_PXONRXCNT(i
));
365 IXGBE_READ_REG(hw
, IXGBE_PXOFFRXCNT(i
));
367 IXGBE_READ_REG(hw
, IXGBE_PXONRXC(i
));
368 IXGBE_READ_REG(hw
, IXGBE_PXOFFRXC(i
));
371 if (hw
->mac
.type
>= ixgbe_mac_82599EB
)
372 for (i
= 0; i
< 8; i
++)
373 IXGBE_READ_REG(hw
, IXGBE_PXON2OFFCNT(i
));
374 IXGBE_READ_REG(hw
, IXGBE_PRC64
);
375 IXGBE_READ_REG(hw
, IXGBE_PRC127
);
376 IXGBE_READ_REG(hw
, IXGBE_PRC255
);
377 IXGBE_READ_REG(hw
, IXGBE_PRC511
);
378 IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
379 IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
380 IXGBE_READ_REG(hw
, IXGBE_GPRC
);
381 IXGBE_READ_REG(hw
, IXGBE_BPRC
);
382 IXGBE_READ_REG(hw
, IXGBE_MPRC
);
383 IXGBE_READ_REG(hw
, IXGBE_GPTC
);
384 IXGBE_READ_REG(hw
, IXGBE_GORCL
);
385 IXGBE_READ_REG(hw
, IXGBE_GORCH
);
386 IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
387 IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
388 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
389 for (i
= 0; i
< 8; i
++)
390 IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
391 IXGBE_READ_REG(hw
, IXGBE_RUC
);
392 IXGBE_READ_REG(hw
, IXGBE_RFC
);
393 IXGBE_READ_REG(hw
, IXGBE_ROC
);
394 IXGBE_READ_REG(hw
, IXGBE_RJC
);
395 IXGBE_READ_REG(hw
, IXGBE_MNGPRC
);
396 IXGBE_READ_REG(hw
, IXGBE_MNGPDC
);
397 IXGBE_READ_REG(hw
, IXGBE_MNGPTC
);
398 IXGBE_READ_REG(hw
, IXGBE_TORL
);
399 IXGBE_READ_REG(hw
, IXGBE_TORH
);
400 IXGBE_READ_REG(hw
, IXGBE_TPR
);
401 IXGBE_READ_REG(hw
, IXGBE_TPT
);
402 IXGBE_READ_REG(hw
, IXGBE_PTC64
);
403 IXGBE_READ_REG(hw
, IXGBE_PTC127
);
404 IXGBE_READ_REG(hw
, IXGBE_PTC255
);
405 IXGBE_READ_REG(hw
, IXGBE_PTC511
);
406 IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
407 IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
408 IXGBE_READ_REG(hw
, IXGBE_MPTC
);
409 IXGBE_READ_REG(hw
, IXGBE_BPTC
);
410 for (i
= 0; i
< 16; i
++) {
411 IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
412 IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
413 if (hw
->mac
.type
>= ixgbe_mac_82599EB
) {
414 IXGBE_READ_REG(hw
, IXGBE_QBRC_L(i
));
415 IXGBE_READ_REG(hw
, IXGBE_QBRC_H(i
));
416 IXGBE_READ_REG(hw
, IXGBE_QBTC_L(i
));
417 IXGBE_READ_REG(hw
, IXGBE_QBTC_H(i
));
418 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
420 IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
421 IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
425 if (hw
->mac
.type
== ixgbe_mac_X540
) {
427 hw
->phy
.ops
.identify(hw
);
428 hw
->phy
.ops
.read_reg(hw
, IXGBE_PCRC8ECL
, MDIO_MMD_PCS
, &i
);
429 hw
->phy
.ops
.read_reg(hw
, IXGBE_PCRC8ECH
, MDIO_MMD_PCS
, &i
);
430 hw
->phy
.ops
.read_reg(hw
, IXGBE_LDPCECL
, MDIO_MMD_PCS
, &i
);
431 hw
->phy
.ops
.read_reg(hw
, IXGBE_LDPCECH
, MDIO_MMD_PCS
, &i
);
438 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
439 * @hw: pointer to hardware structure
440 * @pba_num: stores the part number string from the EEPROM
441 * @pba_num_size: part number string buffer length
443 * Reads the part number string from the EEPROM.
445 s32
ixgbe_read_pba_string_generic(struct ixgbe_hw
*hw
, u8
*pba_num
,
454 if (pba_num
== NULL
) {
455 hw_dbg(hw
, "PBA string buffer was null\n");
456 return IXGBE_ERR_INVALID_ARGUMENT
;
459 ret_val
= hw
->eeprom
.ops
.read(hw
, IXGBE_PBANUM0_PTR
, &data
);
461 hw_dbg(hw
, "NVM Read Error\n");
465 ret_val
= hw
->eeprom
.ops
.read(hw
, IXGBE_PBANUM1_PTR
, &pba_ptr
);
467 hw_dbg(hw
, "NVM Read Error\n");
472 * if data is not ptr guard the PBA must be in legacy format which
473 * means pba_ptr is actually our second data word for the PBA number
474 * and we can decode it into an ascii string
476 if (data
!= IXGBE_PBANUM_PTR_GUARD
) {
477 hw_dbg(hw
, "NVM PBA number is not stored as string\n");
479 /* we will need 11 characters to store the PBA */
480 if (pba_num_size
< 11) {
481 hw_dbg(hw
, "PBA string buffer too small\n");
482 return IXGBE_ERR_NO_SPACE
;
485 /* extract hex string from data and pba_ptr */
486 pba_num
[0] = (data
>> 12) & 0xF;
487 pba_num
[1] = (data
>> 8) & 0xF;
488 pba_num
[2] = (data
>> 4) & 0xF;
489 pba_num
[3] = data
& 0xF;
490 pba_num
[4] = (pba_ptr
>> 12) & 0xF;
491 pba_num
[5] = (pba_ptr
>> 8) & 0xF;
494 pba_num
[8] = (pba_ptr
>> 4) & 0xF;
495 pba_num
[9] = pba_ptr
& 0xF;
497 /* put a null character on the end of our string */
500 /* switch all the data but the '-' to hex char */
501 for (offset
= 0; offset
< 10; offset
++) {
502 if (pba_num
[offset
] < 0xA)
503 pba_num
[offset
] += '0';
504 else if (pba_num
[offset
] < 0x10)
505 pba_num
[offset
] += 'A' - 0xA;
511 ret_val
= hw
->eeprom
.ops
.read(hw
, pba_ptr
, &length
);
513 hw_dbg(hw
, "NVM Read Error\n");
517 if (length
== 0xFFFF || length
== 0) {
518 hw_dbg(hw
, "NVM PBA number section invalid length\n");
519 return IXGBE_ERR_PBA_SECTION
;
522 /* check if pba_num buffer is big enough */
523 if (pba_num_size
< (((u32
)length
* 2) - 1)) {
524 hw_dbg(hw
, "PBA string buffer too small\n");
525 return IXGBE_ERR_NO_SPACE
;
528 /* trim pba length from start of string */
532 for (offset
= 0; offset
< length
; offset
++) {
533 ret_val
= hw
->eeprom
.ops
.read(hw
, pba_ptr
+ offset
, &data
);
535 hw_dbg(hw
, "NVM Read Error\n");
538 pba_num
[offset
* 2] = (u8
)(data
>> 8);
539 pba_num
[(offset
* 2) + 1] = (u8
)(data
& 0xFF);
541 pba_num
[offset
* 2] = '\0';
547 * ixgbe_get_mac_addr_generic - Generic get MAC address
548 * @hw: pointer to hardware structure
549 * @mac_addr: Adapter MAC address
551 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
552 * A reset of the adapter must be performed prior to calling this function
553 * in order for the MAC address to have been loaded from the EEPROM into RAR0
555 s32
ixgbe_get_mac_addr_generic(struct ixgbe_hw
*hw
, u8
*mac_addr
)
561 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(0));
562 rar_low
= IXGBE_READ_REG(hw
, IXGBE_RAL(0));
564 for (i
= 0; i
< 4; i
++)
565 mac_addr
[i
] = (u8
)(rar_low
>> (i
*8));
567 for (i
= 0; i
< 2; i
++)
568 mac_addr
[i
+4] = (u8
)(rar_high
>> (i
*8));
574 * ixgbe_get_bus_info_generic - Generic set PCI bus info
575 * @hw: pointer to hardware structure
577 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
579 s32
ixgbe_get_bus_info_generic(struct ixgbe_hw
*hw
)
581 struct ixgbe_adapter
*adapter
= hw
->back
;
582 struct ixgbe_mac_info
*mac
= &hw
->mac
;
585 hw
->bus
.type
= ixgbe_bus_type_pci_express
;
587 /* Get the negotiated link width and speed from PCI config space */
588 pci_read_config_word(adapter
->pdev
, IXGBE_PCI_LINK_STATUS
,
591 switch (link_status
& IXGBE_PCI_LINK_WIDTH
) {
592 case IXGBE_PCI_LINK_WIDTH_1
:
593 hw
->bus
.width
= ixgbe_bus_width_pcie_x1
;
595 case IXGBE_PCI_LINK_WIDTH_2
:
596 hw
->bus
.width
= ixgbe_bus_width_pcie_x2
;
598 case IXGBE_PCI_LINK_WIDTH_4
:
599 hw
->bus
.width
= ixgbe_bus_width_pcie_x4
;
601 case IXGBE_PCI_LINK_WIDTH_8
:
602 hw
->bus
.width
= ixgbe_bus_width_pcie_x8
;
605 hw
->bus
.width
= ixgbe_bus_width_unknown
;
609 switch (link_status
& IXGBE_PCI_LINK_SPEED
) {
610 case IXGBE_PCI_LINK_SPEED_2500
:
611 hw
->bus
.speed
= ixgbe_bus_speed_2500
;
613 case IXGBE_PCI_LINK_SPEED_5000
:
614 hw
->bus
.speed
= ixgbe_bus_speed_5000
;
617 hw
->bus
.speed
= ixgbe_bus_speed_unknown
;
621 mac
->ops
.set_lan_id(hw
);
627 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
628 * @hw: pointer to the HW structure
630 * Determines the LAN function id by reading memory-mapped registers
631 * and swaps the port value if requested.
633 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw
*hw
)
635 struct ixgbe_bus_info
*bus
= &hw
->bus
;
638 reg
= IXGBE_READ_REG(hw
, IXGBE_STATUS
);
639 bus
->func
= (reg
& IXGBE_STATUS_LAN_ID
) >> IXGBE_STATUS_LAN_ID_SHIFT
;
640 bus
->lan_id
= bus
->func
;
642 /* check for a port swap */
643 reg
= IXGBE_READ_REG(hw
, IXGBE_FACTPS
);
644 if (reg
& IXGBE_FACTPS_LFS
)
649 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
650 * @hw: pointer to hardware structure
652 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
653 * disables transmit and receive units. The adapter_stopped flag is used by
654 * the shared code and drivers to determine if the adapter is in a stopped
655 * state and should not touch the hardware.
657 s32
ixgbe_stop_adapter_generic(struct ixgbe_hw
*hw
)
663 * Set the adapter_stopped flag so other driver functions stop touching
666 hw
->adapter_stopped
= true;
668 /* Disable the receive unit */
669 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, 0);
671 /* Clear interrupt mask to stop interrupts from being generated */
672 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
674 /* Clear any pending interrupts, flush previous writes */
675 IXGBE_READ_REG(hw
, IXGBE_EICR
);
677 /* Disable the transmit unit. Each queue must be disabled. */
678 for (i
= 0; i
< hw
->mac
.max_tx_queues
; i
++)
679 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(i
), IXGBE_TXDCTL_SWFLSH
);
681 /* Disable the receive unit by stopping each queue */
682 for (i
= 0; i
< hw
->mac
.max_rx_queues
; i
++) {
683 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
684 reg_val
&= ~IXGBE_RXDCTL_ENABLE
;
685 reg_val
|= IXGBE_RXDCTL_SWFLSH
;
686 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(i
), reg_val
);
689 /* flush all queues disables */
690 IXGBE_WRITE_FLUSH(hw
);
691 usleep_range(1000, 2000);
694 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
695 * access and verify no pending requests
697 return ixgbe_disable_pcie_master(hw
);
701 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
702 * @hw: pointer to hardware structure
703 * @index: led number to turn on
705 s32
ixgbe_led_on_generic(struct ixgbe_hw
*hw
, u32 index
)
707 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
709 /* To turn on the LED, set mode to ON. */
710 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
711 led_reg
|= IXGBE_LED_ON
<< IXGBE_LED_MODE_SHIFT(index
);
712 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
713 IXGBE_WRITE_FLUSH(hw
);
719 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
720 * @hw: pointer to hardware structure
721 * @index: led number to turn off
723 s32
ixgbe_led_off_generic(struct ixgbe_hw
*hw
, u32 index
)
725 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
727 /* To turn off the LED, set mode to OFF. */
728 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
729 led_reg
|= IXGBE_LED_OFF
<< IXGBE_LED_MODE_SHIFT(index
);
730 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
731 IXGBE_WRITE_FLUSH(hw
);
737 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
738 * @hw: pointer to hardware structure
740 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
741 * ixgbe_hw struct in order to set up EEPROM access.
743 s32
ixgbe_init_eeprom_params_generic(struct ixgbe_hw
*hw
)
745 struct ixgbe_eeprom_info
*eeprom
= &hw
->eeprom
;
749 if (eeprom
->type
== ixgbe_eeprom_uninitialized
) {
750 eeprom
->type
= ixgbe_eeprom_none
;
751 /* Set default semaphore delay to 10ms which is a well
753 eeprom
->semaphore_delay
= 10;
754 /* Clear EEPROM page size, it will be initialized as needed */
755 eeprom
->word_page_size
= 0;
758 * Check for EEPROM present first.
759 * If not present leave as none
761 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
762 if (eec
& IXGBE_EEC_PRES
) {
763 eeprom
->type
= ixgbe_eeprom_spi
;
766 * SPI EEPROM is assumed here. This code would need to
767 * change if a future EEPROM is not SPI.
769 eeprom_size
= (u16
)((eec
& IXGBE_EEC_SIZE
) >>
770 IXGBE_EEC_SIZE_SHIFT
);
771 eeprom
->word_size
= 1 << (eeprom_size
+
772 IXGBE_EEPROM_WORD_SIZE_SHIFT
);
775 if (eec
& IXGBE_EEC_ADDR_SIZE
)
776 eeprom
->address_bits
= 16;
778 eeprom
->address_bits
= 8;
779 hw_dbg(hw
, "Eeprom params: type = %d, size = %d, address bits: "
780 "%d\n", eeprom
->type
, eeprom
->word_size
,
781 eeprom
->address_bits
);
788 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
789 * @hw: pointer to hardware structure
790 * @offset: offset within the EEPROM to write
791 * @words: number of words
792 * @data: 16 bit word(s) to write to EEPROM
794 * Reads 16 bit word(s) from EEPROM through bit-bang method
796 s32
ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw
*hw
, u16 offset
,
797 u16 words
, u16
*data
)
802 hw
->eeprom
.ops
.init_params(hw
);
805 status
= IXGBE_ERR_INVALID_ARGUMENT
;
809 if (offset
+ words
> hw
->eeprom
.word_size
) {
810 status
= IXGBE_ERR_EEPROM
;
815 * The EEPROM page size cannot be queried from the chip. We do lazy
816 * initialization. It is worth to do that when we write large buffer.
818 if ((hw
->eeprom
.word_page_size
== 0) &&
819 (words
> IXGBE_EEPROM_PAGE_SIZE_MAX
))
820 ixgbe_detect_eeprom_page_size_generic(hw
, offset
);
823 * We cannot hold synchronization semaphores for too long
824 * to avoid other entity starvation. However it is more efficient
825 * to read in bursts than synchronizing access for each word.
827 for (i
= 0; i
< words
; i
+= IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
) {
828 count
= (words
- i
) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
> 0 ?
829 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
: (words
- i
);
830 status
= ixgbe_write_eeprom_buffer_bit_bang(hw
, offset
+ i
,
842 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
843 * @hw: pointer to hardware structure
844 * @offset: offset within the EEPROM to be written to
845 * @words: number of word(s)
846 * @data: 16 bit word(s) to be written to the EEPROM
848 * If ixgbe_eeprom_update_checksum is not called after this function, the
849 * EEPROM will most likely contain an invalid checksum.
851 static s32
ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw
*hw
, u16 offset
,
852 u16 words
, u16
*data
)
858 u8 write_opcode
= IXGBE_EEPROM_WRITE_OPCODE_SPI
;
860 /* Prepare the EEPROM for writing */
861 status
= ixgbe_acquire_eeprom(hw
);
864 if (ixgbe_ready_eeprom(hw
) != 0) {
865 ixgbe_release_eeprom(hw
);
866 status
= IXGBE_ERR_EEPROM
;
871 for (i
= 0; i
< words
; i
++) {
872 ixgbe_standby_eeprom(hw
);
874 /* Send the WRITE ENABLE command (8 bit opcode ) */
875 ixgbe_shift_out_eeprom_bits(hw
,
876 IXGBE_EEPROM_WREN_OPCODE_SPI
,
877 IXGBE_EEPROM_OPCODE_BITS
);
879 ixgbe_standby_eeprom(hw
);
882 * Some SPI eeproms use the 8th address bit embedded
885 if ((hw
->eeprom
.address_bits
== 8) &&
886 ((offset
+ i
) >= 128))
887 write_opcode
|= IXGBE_EEPROM_A8_OPCODE_SPI
;
889 /* Send the Write command (8-bit opcode + addr) */
890 ixgbe_shift_out_eeprom_bits(hw
, write_opcode
,
891 IXGBE_EEPROM_OPCODE_BITS
);
892 ixgbe_shift_out_eeprom_bits(hw
, (u16
)((offset
+ i
) * 2),
893 hw
->eeprom
.address_bits
);
895 page_size
= hw
->eeprom
.word_page_size
;
897 /* Send the data in burst via SPI*/
900 word
= (word
>> 8) | (word
<< 8);
901 ixgbe_shift_out_eeprom_bits(hw
, word
, 16);
906 /* do not wrap around page */
907 if (((offset
+ i
) & (page_size
- 1)) ==
910 } while (++i
< words
);
912 ixgbe_standby_eeprom(hw
);
913 usleep_range(10000, 20000);
915 /* Done with writing - release the EEPROM */
916 ixgbe_release_eeprom(hw
);
923 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
924 * @hw: pointer to hardware structure
925 * @offset: offset within the EEPROM to be written to
926 * @data: 16 bit word to be written to the EEPROM
928 * If ixgbe_eeprom_update_checksum is not called after this function, the
929 * EEPROM will most likely contain an invalid checksum.
931 s32
ixgbe_write_eeprom_generic(struct ixgbe_hw
*hw
, u16 offset
, u16 data
)
935 hw
->eeprom
.ops
.init_params(hw
);
937 if (offset
>= hw
->eeprom
.word_size
) {
938 status
= IXGBE_ERR_EEPROM
;
942 status
= ixgbe_write_eeprom_buffer_bit_bang(hw
, offset
, 1, &data
);
949 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
950 * @hw: pointer to hardware structure
951 * @offset: offset within the EEPROM to be read
952 * @words: number of word(s)
953 * @data: read 16 bit words(s) from EEPROM
955 * Reads 16 bit word(s) from EEPROM through bit-bang method
957 s32
ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw
*hw
, u16 offset
,
958 u16 words
, u16
*data
)
963 hw
->eeprom
.ops
.init_params(hw
);
966 status
= IXGBE_ERR_INVALID_ARGUMENT
;
970 if (offset
+ words
> hw
->eeprom
.word_size
) {
971 status
= IXGBE_ERR_EEPROM
;
976 * We cannot hold synchronization semaphores for too long
977 * to avoid other entity starvation. However it is more efficient
978 * to read in bursts than synchronizing access for each word.
980 for (i
= 0; i
< words
; i
+= IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
) {
981 count
= (words
- i
) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
> 0 ?
982 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
: (words
- i
);
984 status
= ixgbe_read_eeprom_buffer_bit_bang(hw
, offset
+ i
,
996 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
997 * @hw: pointer to hardware structure
998 * @offset: offset within the EEPROM to be read
999 * @words: number of word(s)
1000 * @data: read 16 bit word(s) from EEPROM
1002 * Reads 16 bit word(s) from EEPROM through bit-bang method
1004 static s32
ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw
*hw
, u16 offset
,
1005 u16 words
, u16
*data
)
1009 u8 read_opcode
= IXGBE_EEPROM_READ_OPCODE_SPI
;
1012 /* Prepare the EEPROM for reading */
1013 status
= ixgbe_acquire_eeprom(hw
);
1016 if (ixgbe_ready_eeprom(hw
) != 0) {
1017 ixgbe_release_eeprom(hw
);
1018 status
= IXGBE_ERR_EEPROM
;
1023 for (i
= 0; i
< words
; i
++) {
1024 ixgbe_standby_eeprom(hw
);
1026 * Some SPI eeproms use the 8th address bit embedded
1029 if ((hw
->eeprom
.address_bits
== 8) &&
1030 ((offset
+ i
) >= 128))
1031 read_opcode
|= IXGBE_EEPROM_A8_OPCODE_SPI
;
1033 /* Send the READ command (opcode + addr) */
1034 ixgbe_shift_out_eeprom_bits(hw
, read_opcode
,
1035 IXGBE_EEPROM_OPCODE_BITS
);
1036 ixgbe_shift_out_eeprom_bits(hw
, (u16
)((offset
+ i
) * 2),
1037 hw
->eeprom
.address_bits
);
1039 /* Read the data. */
1040 word_in
= ixgbe_shift_in_eeprom_bits(hw
, 16);
1041 data
[i
] = (word_in
>> 8) | (word_in
<< 8);
1044 /* End this read operation */
1045 ixgbe_release_eeprom(hw
);
1052 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1053 * @hw: pointer to hardware structure
1054 * @offset: offset within the EEPROM to be read
1055 * @data: read 16 bit value from EEPROM
1057 * Reads 16 bit value from EEPROM through bit-bang method
1059 s32
ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw
*hw
, u16 offset
,
1064 hw
->eeprom
.ops
.init_params(hw
);
1066 if (offset
>= hw
->eeprom
.word_size
) {
1067 status
= IXGBE_ERR_EEPROM
;
1071 status
= ixgbe_read_eeprom_buffer_bit_bang(hw
, offset
, 1, data
);
1078 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1079 * @hw: pointer to hardware structure
1080 * @offset: offset of word in the EEPROM to read
1081 * @words: number of word(s)
1082 * @data: 16 bit word(s) from the EEPROM
1084 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1086 s32
ixgbe_read_eerd_buffer_generic(struct ixgbe_hw
*hw
, u16 offset
,
1087 u16 words
, u16
*data
)
1093 hw
->eeprom
.ops
.init_params(hw
);
1096 status
= IXGBE_ERR_INVALID_ARGUMENT
;
1100 if (offset
>= hw
->eeprom
.word_size
) {
1101 status
= IXGBE_ERR_EEPROM
;
1105 for (i
= 0; i
< words
; i
++) {
1106 eerd
= ((offset
+ i
) << IXGBE_EEPROM_RW_ADDR_SHIFT
) +
1107 IXGBE_EEPROM_RW_REG_START
;
1109 IXGBE_WRITE_REG(hw
, IXGBE_EERD
, eerd
);
1110 status
= ixgbe_poll_eerd_eewr_done(hw
, IXGBE_NVM_POLL_READ
);
1113 data
[i
] = (IXGBE_READ_REG(hw
, IXGBE_EERD
) >>
1114 IXGBE_EEPROM_RW_REG_DATA
);
1116 hw_dbg(hw
, "Eeprom read timed out\n");
1125 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1126 * @hw: pointer to hardware structure
1127 * @offset: offset within the EEPROM to be used as a scratch pad
1129 * Discover EEPROM page size by writing marching data at given offset.
1130 * This function is called only when we are writing a new large buffer
1131 * at given offset so the data would be overwritten anyway.
1133 static s32
ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw
*hw
,
1136 u16 data
[IXGBE_EEPROM_PAGE_SIZE_MAX
];
1140 for (i
= 0; i
< IXGBE_EEPROM_PAGE_SIZE_MAX
; i
++)
1143 hw
->eeprom
.word_page_size
= IXGBE_EEPROM_PAGE_SIZE_MAX
;
1144 status
= ixgbe_write_eeprom_buffer_bit_bang(hw
, offset
,
1145 IXGBE_EEPROM_PAGE_SIZE_MAX
, data
);
1146 hw
->eeprom
.word_page_size
= 0;
1150 status
= ixgbe_read_eeprom_buffer_bit_bang(hw
, offset
, 1, data
);
1155 * When writing in burst more than the actual page size
1156 * EEPROM address wraps around current page.
1158 hw
->eeprom
.word_page_size
= IXGBE_EEPROM_PAGE_SIZE_MAX
- data
[0];
1160 hw_dbg(hw
, "Detected EEPROM page size = %d words.",
1161 hw
->eeprom
.word_page_size
);
1167 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1168 * @hw: pointer to hardware structure
1169 * @offset: offset of word in the EEPROM to read
1170 * @data: word read from the EEPROM
1172 * Reads a 16 bit word from the EEPROM using the EERD register.
1174 s32
ixgbe_read_eerd_generic(struct ixgbe_hw
*hw
, u16 offset
, u16
*data
)
1176 return ixgbe_read_eerd_buffer_generic(hw
, offset
, 1, data
);
1180 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1181 * @hw: pointer to hardware structure
1182 * @offset: offset of word in the EEPROM to write
1183 * @words: number of words
1184 * @data: word(s) write to the EEPROM
1186 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1188 s32
ixgbe_write_eewr_buffer_generic(struct ixgbe_hw
*hw
, u16 offset
,
1189 u16 words
, u16
*data
)
1195 hw
->eeprom
.ops
.init_params(hw
);
1198 status
= IXGBE_ERR_INVALID_ARGUMENT
;
1202 if (offset
>= hw
->eeprom
.word_size
) {
1203 status
= IXGBE_ERR_EEPROM
;
1207 for (i
= 0; i
< words
; i
++) {
1208 eewr
= ((offset
+ i
) << IXGBE_EEPROM_RW_ADDR_SHIFT
) |
1209 (data
[i
] << IXGBE_EEPROM_RW_REG_DATA
) |
1210 IXGBE_EEPROM_RW_REG_START
;
1212 status
= ixgbe_poll_eerd_eewr_done(hw
, IXGBE_NVM_POLL_WRITE
);
1214 hw_dbg(hw
, "Eeprom write EEWR timed out\n");
1218 IXGBE_WRITE_REG(hw
, IXGBE_EEWR
, eewr
);
1220 status
= ixgbe_poll_eerd_eewr_done(hw
, IXGBE_NVM_POLL_WRITE
);
1222 hw_dbg(hw
, "Eeprom write EEWR timed out\n");
1232 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1233 * @hw: pointer to hardware structure
1234 * @offset: offset of word in the EEPROM to write
1235 * @data: word write to the EEPROM
1237 * Write a 16 bit word to the EEPROM using the EEWR register.
1239 s32
ixgbe_write_eewr_generic(struct ixgbe_hw
*hw
, u16 offset
, u16 data
)
1241 return ixgbe_write_eewr_buffer_generic(hw
, offset
, 1, &data
);
1245 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1246 * @hw: pointer to hardware structure
1247 * @ee_reg: EEPROM flag for polling
1249 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1250 * read or write is done respectively.
1252 static s32
ixgbe_poll_eerd_eewr_done(struct ixgbe_hw
*hw
, u32 ee_reg
)
1256 s32 status
= IXGBE_ERR_EEPROM
;
1258 for (i
= 0; i
< IXGBE_EERD_EEWR_ATTEMPTS
; i
++) {
1259 if (ee_reg
== IXGBE_NVM_POLL_READ
)
1260 reg
= IXGBE_READ_REG(hw
, IXGBE_EERD
);
1262 reg
= IXGBE_READ_REG(hw
, IXGBE_EEWR
);
1264 if (reg
& IXGBE_EEPROM_RW_REG_DONE
) {
1274 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1275 * @hw: pointer to hardware structure
1277 * Prepares EEPROM for access using bit-bang method. This function should
1278 * be called before issuing a command to the EEPROM.
1280 static s32
ixgbe_acquire_eeprom(struct ixgbe_hw
*hw
)
1286 if (hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
) != 0)
1287 status
= IXGBE_ERR_SWFW_SYNC
;
1290 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
1292 /* Request EEPROM Access */
1293 eec
|= IXGBE_EEC_REQ
;
1294 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
1296 for (i
= 0; i
< IXGBE_EEPROM_GRANT_ATTEMPTS
; i
++) {
1297 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
1298 if (eec
& IXGBE_EEC_GNT
)
1303 /* Release if grant not acquired */
1304 if (!(eec
& IXGBE_EEC_GNT
)) {
1305 eec
&= ~IXGBE_EEC_REQ
;
1306 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
1307 hw_dbg(hw
, "Could not acquire EEPROM grant\n");
1309 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
1310 status
= IXGBE_ERR_EEPROM
;
1313 /* Setup EEPROM for Read/Write */
1315 /* Clear CS and SK */
1316 eec
&= ~(IXGBE_EEC_CS
| IXGBE_EEC_SK
);
1317 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
1318 IXGBE_WRITE_FLUSH(hw
);
1326 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1327 * @hw: pointer to hardware structure
1329 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1331 static s32
ixgbe_get_eeprom_semaphore(struct ixgbe_hw
*hw
)
1333 s32 status
= IXGBE_ERR_EEPROM
;
1338 /* Get SMBI software semaphore between device drivers first */
1339 for (i
= 0; i
< timeout
; i
++) {
1341 * If the SMBI bit is 0 when we read it, then the bit will be
1342 * set and we have the semaphore
1344 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
1345 if (!(swsm
& IXGBE_SWSM_SMBI
)) {
1353 hw_dbg(hw
, "Driver can't access the Eeprom - SMBI Semaphore "
1356 * this release is particularly important because our attempts
1357 * above to get the semaphore may have succeeded, and if there
1358 * was a timeout, we should unconditionally clear the semaphore
1359 * bits to free the driver to make progress
1361 ixgbe_release_eeprom_semaphore(hw
);
1366 * If the SMBI bit is 0 when we read it, then the bit will be
1367 * set and we have the semaphore
1369 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
1370 if (!(swsm
& IXGBE_SWSM_SMBI
))
1374 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1376 for (i
= 0; i
< timeout
; i
++) {
1377 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
1379 /* Set the SW EEPROM semaphore bit to request access */
1380 swsm
|= IXGBE_SWSM_SWESMBI
;
1381 IXGBE_WRITE_REG(hw
, IXGBE_SWSM
, swsm
);
1384 * If we set the bit successfully then we got the
1387 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
1388 if (swsm
& IXGBE_SWSM_SWESMBI
)
1395 * Release semaphores and return error if SW EEPROM semaphore
1396 * was not granted because we don't have access to the EEPROM
1399 hw_dbg(hw
, "SWESMBI Software EEPROM semaphore "
1401 ixgbe_release_eeprom_semaphore(hw
);
1402 status
= IXGBE_ERR_EEPROM
;
1405 hw_dbg(hw
, "Software semaphore SMBI between device drivers "
1413 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1414 * @hw: pointer to hardware structure
1416 * This function clears hardware semaphore bits.
1418 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw
*hw
)
1422 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
1424 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1425 swsm
&= ~(IXGBE_SWSM_SWESMBI
| IXGBE_SWSM_SMBI
);
1426 IXGBE_WRITE_REG(hw
, IXGBE_SWSM
, swsm
);
1427 IXGBE_WRITE_FLUSH(hw
);
1431 * ixgbe_ready_eeprom - Polls for EEPROM ready
1432 * @hw: pointer to hardware structure
1434 static s32
ixgbe_ready_eeprom(struct ixgbe_hw
*hw
)
1441 * Read "Status Register" repeatedly until the LSB is cleared. The
1442 * EEPROM will signal that the command has been completed by clearing
1443 * bit 0 of the internal status register. If it's not cleared within
1444 * 5 milliseconds, then error out.
1446 for (i
= 0; i
< IXGBE_EEPROM_MAX_RETRY_SPI
; i
+= 5) {
1447 ixgbe_shift_out_eeprom_bits(hw
, IXGBE_EEPROM_RDSR_OPCODE_SPI
,
1448 IXGBE_EEPROM_OPCODE_BITS
);
1449 spi_stat_reg
= (u8
)ixgbe_shift_in_eeprom_bits(hw
, 8);
1450 if (!(spi_stat_reg
& IXGBE_EEPROM_STATUS_RDY_SPI
))
1454 ixgbe_standby_eeprom(hw
);
1458 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1459 * devices (and only 0-5mSec on 5V devices)
1461 if (i
>= IXGBE_EEPROM_MAX_RETRY_SPI
) {
1462 hw_dbg(hw
, "SPI EEPROM Status error\n");
1463 status
= IXGBE_ERR_EEPROM
;
1470 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1471 * @hw: pointer to hardware structure
1473 static void ixgbe_standby_eeprom(struct ixgbe_hw
*hw
)
1477 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
1479 /* Toggle CS to flush commands */
1480 eec
|= IXGBE_EEC_CS
;
1481 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
1482 IXGBE_WRITE_FLUSH(hw
);
1484 eec
&= ~IXGBE_EEC_CS
;
1485 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
1486 IXGBE_WRITE_FLUSH(hw
);
1491 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1492 * @hw: pointer to hardware structure
1493 * @data: data to send to the EEPROM
1494 * @count: number of bits to shift out
1496 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw
*hw
, u16 data
,
1503 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
1506 * Mask is used to shift "count" bits of "data" out to the EEPROM
1507 * one bit at a time. Determine the starting bit based on count
1509 mask
= 0x01 << (count
- 1);
1511 for (i
= 0; i
< count
; i
++) {
1513 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1514 * "1", and then raising and then lowering the clock (the SK
1515 * bit controls the clock input to the EEPROM). A "0" is
1516 * shifted out to the EEPROM by setting "DI" to "0" and then
1517 * raising and then lowering the clock.
1520 eec
|= IXGBE_EEC_DI
;
1522 eec
&= ~IXGBE_EEC_DI
;
1524 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
1525 IXGBE_WRITE_FLUSH(hw
);
1529 ixgbe_raise_eeprom_clk(hw
, &eec
);
1530 ixgbe_lower_eeprom_clk(hw
, &eec
);
1533 * Shift mask to signify next bit of data to shift in to the
1539 /* We leave the "DI" bit set to "0" when we leave this routine. */
1540 eec
&= ~IXGBE_EEC_DI
;
1541 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
1542 IXGBE_WRITE_FLUSH(hw
);
1546 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1547 * @hw: pointer to hardware structure
1549 static u16
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw
*hw
, u16 count
)
1556 * In order to read a register from the EEPROM, we need to shift
1557 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1558 * the clock input to the EEPROM (setting the SK bit), and then reading
1559 * the value of the "DO" bit. During this "shifting in" process the
1560 * "DI" bit should always be clear.
1562 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
1564 eec
&= ~(IXGBE_EEC_DO
| IXGBE_EEC_DI
);
1566 for (i
= 0; i
< count
; i
++) {
1568 ixgbe_raise_eeprom_clk(hw
, &eec
);
1570 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
1572 eec
&= ~(IXGBE_EEC_DI
);
1573 if (eec
& IXGBE_EEC_DO
)
1576 ixgbe_lower_eeprom_clk(hw
, &eec
);
1583 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1584 * @hw: pointer to hardware structure
1585 * @eec: EEC register's current value
1587 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
)
1590 * Raise the clock input to the EEPROM
1591 * (setting the SK bit), then delay
1593 *eec
= *eec
| IXGBE_EEC_SK
;
1594 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, *eec
);
1595 IXGBE_WRITE_FLUSH(hw
);
1600 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1601 * @hw: pointer to hardware structure
1602 * @eecd: EECD's current value
1604 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
)
1607 * Lower the clock input to the EEPROM (clearing the SK bit), then
1610 *eec
= *eec
& ~IXGBE_EEC_SK
;
1611 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, *eec
);
1612 IXGBE_WRITE_FLUSH(hw
);
1617 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1618 * @hw: pointer to hardware structure
1620 static void ixgbe_release_eeprom(struct ixgbe_hw
*hw
)
1624 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
1626 eec
|= IXGBE_EEC_CS
; /* Pull CS high */
1627 eec
&= ~IXGBE_EEC_SK
; /* Lower SCK */
1629 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
1630 IXGBE_WRITE_FLUSH(hw
);
1634 /* Stop requesting EEPROM access */
1635 eec
&= ~IXGBE_EEC_REQ
;
1636 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
1638 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
1641 * Delay before attempt to obtain semaphore again to allow FW
1642 * access. semaphore_delay is in ms we need us for usleep_range
1644 usleep_range(hw
->eeprom
.semaphore_delay
* 1000,
1645 hw
->eeprom
.semaphore_delay
* 2000);
1649 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1650 * @hw: pointer to hardware structure
1652 u16
ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw
*hw
)
1661 /* Include 0x0-0x3F in the checksum */
1662 for (i
= 0; i
< IXGBE_EEPROM_CHECKSUM
; i
++) {
1663 if (hw
->eeprom
.ops
.read(hw
, i
, &word
) != 0) {
1664 hw_dbg(hw
, "EEPROM read failed\n");
1670 /* Include all data from pointers except for the fw pointer */
1671 for (i
= IXGBE_PCIE_ANALOG_PTR
; i
< IXGBE_FW_PTR
; i
++) {
1672 hw
->eeprom
.ops
.read(hw
, i
, &pointer
);
1674 /* Make sure the pointer seems valid */
1675 if (pointer
!= 0xFFFF && pointer
!= 0) {
1676 hw
->eeprom
.ops
.read(hw
, pointer
, &length
);
1678 if (length
!= 0xFFFF && length
!= 0) {
1679 for (j
= pointer
+1; j
<= pointer
+length
; j
++) {
1680 hw
->eeprom
.ops
.read(hw
, j
, &word
);
1687 checksum
= (u16
)IXGBE_EEPROM_SUM
- checksum
;
1693 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1694 * @hw: pointer to hardware structure
1695 * @checksum_val: calculated checksum
1697 * Performs checksum calculation and validates the EEPROM checksum. If the
1698 * caller does not need checksum_val, the value can be NULL.
1700 s32
ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw
*hw
,
1705 u16 read_checksum
= 0;
1708 * Read the first word from the EEPROM. If this times out or fails, do
1709 * not continue or we could be in for a very long wait while every
1712 status
= hw
->eeprom
.ops
.read(hw
, 0, &checksum
);
1715 checksum
= hw
->eeprom
.ops
.calc_checksum(hw
);
1717 hw
->eeprom
.ops
.read(hw
, IXGBE_EEPROM_CHECKSUM
, &read_checksum
);
1720 * Verify read checksum from EEPROM is the same as
1721 * calculated checksum
1723 if (read_checksum
!= checksum
)
1724 status
= IXGBE_ERR_EEPROM_CHECKSUM
;
1726 /* If the user cares, return the calculated checksum */
1728 *checksum_val
= checksum
;
1730 hw_dbg(hw
, "EEPROM read failed\n");
1737 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1738 * @hw: pointer to hardware structure
1740 s32
ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw
*hw
)
1746 * Read the first word from the EEPROM. If this times out or fails, do
1747 * not continue or we could be in for a very long wait while every
1750 status
= hw
->eeprom
.ops
.read(hw
, 0, &checksum
);
1753 checksum
= hw
->eeprom
.ops
.calc_checksum(hw
);
1754 status
= hw
->eeprom
.ops
.write(hw
, IXGBE_EEPROM_CHECKSUM
,
1757 hw_dbg(hw
, "EEPROM read failed\n");
1764 * ixgbe_validate_mac_addr - Validate MAC address
1765 * @mac_addr: pointer to MAC address.
1767 * Tests a MAC address to ensure it is a valid Individual Address
1769 s32
ixgbe_validate_mac_addr(u8
*mac_addr
)
1773 /* Make sure it is not a multicast address */
1774 if (IXGBE_IS_MULTICAST(mac_addr
))
1775 status
= IXGBE_ERR_INVALID_MAC_ADDR
;
1776 /* Not a broadcast address */
1777 else if (IXGBE_IS_BROADCAST(mac_addr
))
1778 status
= IXGBE_ERR_INVALID_MAC_ADDR
;
1779 /* Reject the zero address */
1780 else if (mac_addr
[0] == 0 && mac_addr
[1] == 0 && mac_addr
[2] == 0 &&
1781 mac_addr
[3] == 0 && mac_addr
[4] == 0 && mac_addr
[5] == 0)
1782 status
= IXGBE_ERR_INVALID_MAC_ADDR
;
1788 * ixgbe_set_rar_generic - Set Rx address register
1789 * @hw: pointer to hardware structure
1790 * @index: Receive address register to write
1791 * @addr: Address to put into receive address register
1792 * @vmdq: VMDq "set" or "pool" index
1793 * @enable_addr: set flag that address is active
1795 * Puts an ethernet address into a receive address register.
1797 s32
ixgbe_set_rar_generic(struct ixgbe_hw
*hw
, u32 index
, u8
*addr
, u32 vmdq
,
1800 u32 rar_low
, rar_high
;
1801 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1803 /* Make sure we are using a valid rar index range */
1804 if (index
>= rar_entries
) {
1805 hw_dbg(hw
, "RAR index %d is out of range.\n", index
);
1806 return IXGBE_ERR_INVALID_ARGUMENT
;
1809 /* setup VMDq pool selection before this RAR gets enabled */
1810 hw
->mac
.ops
.set_vmdq(hw
, index
, vmdq
);
1813 * HW expects these in little endian so we reverse the byte
1814 * order from network order (big endian) to little endian
1816 rar_low
= ((u32
)addr
[0] |
1817 ((u32
)addr
[1] << 8) |
1818 ((u32
)addr
[2] << 16) |
1819 ((u32
)addr
[3] << 24));
1821 * Some parts put the VMDq setting in the extra RAH bits,
1822 * so save everything except the lower 16 bits that hold part
1823 * of the address and the address valid bit.
1825 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1826 rar_high
&= ~(0x0000FFFF | IXGBE_RAH_AV
);
1827 rar_high
|= ((u32
)addr
[4] | ((u32
)addr
[5] << 8));
1829 if (enable_addr
!= 0)
1830 rar_high
|= IXGBE_RAH_AV
;
1832 IXGBE_WRITE_REG(hw
, IXGBE_RAL(index
), rar_low
);
1833 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1839 * ixgbe_clear_rar_generic - Remove Rx address register
1840 * @hw: pointer to hardware structure
1841 * @index: Receive address register to write
1843 * Clears an ethernet address from a receive address register.
1845 s32
ixgbe_clear_rar_generic(struct ixgbe_hw
*hw
, u32 index
)
1848 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1850 /* Make sure we are using a valid rar index range */
1851 if (index
>= rar_entries
) {
1852 hw_dbg(hw
, "RAR index %d is out of range.\n", index
);
1853 return IXGBE_ERR_INVALID_ARGUMENT
;
1857 * Some parts put the VMDq setting in the extra RAH bits,
1858 * so save everything except the lower 16 bits that hold part
1859 * of the address and the address valid bit.
1861 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1862 rar_high
&= ~(0x0000FFFF | IXGBE_RAH_AV
);
1864 IXGBE_WRITE_REG(hw
, IXGBE_RAL(index
), 0);
1865 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1867 /* clear VMDq pool/queue selection for this RAR */
1868 hw
->mac
.ops
.clear_vmdq(hw
, index
, IXGBE_CLEAR_VMDQ_ALL
);
1874 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1875 * @hw: pointer to hardware structure
1877 * Places the MAC address in receive address register 0 and clears the rest
1878 * of the receive address registers. Clears the multicast table. Assumes
1879 * the receiver is in reset when the routine is called.
1881 s32
ixgbe_init_rx_addrs_generic(struct ixgbe_hw
*hw
)
1884 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1887 * If the current mac address is valid, assume it is a software override
1888 * to the permanent address.
1889 * Otherwise, use the permanent address from the eeprom.
1891 if (ixgbe_validate_mac_addr(hw
->mac
.addr
) ==
1892 IXGBE_ERR_INVALID_MAC_ADDR
) {
1893 /* Get the MAC address from the RAR0 for later reference */
1894 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.addr
);
1896 hw_dbg(hw
, " Keeping Current RAR0 Addr =%pM\n", hw
->mac
.addr
);
1898 /* Setup the receive address. */
1899 hw_dbg(hw
, "Overriding MAC Address in RAR[0]\n");
1900 hw_dbg(hw
, " New MAC Addr =%pM\n", hw
->mac
.addr
);
1902 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, 0, IXGBE_RAH_AV
);
1904 /* clear VMDq pool/queue selection for RAR 0 */
1905 hw
->mac
.ops
.clear_vmdq(hw
, 0, IXGBE_CLEAR_VMDQ_ALL
);
1907 hw
->addr_ctrl
.overflow_promisc
= 0;
1909 hw
->addr_ctrl
.rar_used_count
= 1;
1911 /* Zero out the other receive addresses. */
1912 hw_dbg(hw
, "Clearing RAR[1-%d]\n", rar_entries
- 1);
1913 for (i
= 1; i
< rar_entries
; i
++) {
1914 IXGBE_WRITE_REG(hw
, IXGBE_RAL(i
), 0);
1915 IXGBE_WRITE_REG(hw
, IXGBE_RAH(i
), 0);
1919 hw
->addr_ctrl
.mta_in_use
= 0;
1920 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, hw
->mac
.mc_filter_type
);
1922 hw_dbg(hw
, " Clearing MTA\n");
1923 for (i
= 0; i
< hw
->mac
.mcft_size
; i
++)
1924 IXGBE_WRITE_REG(hw
, IXGBE_MTA(i
), 0);
1926 if (hw
->mac
.ops
.init_uta_tables
)
1927 hw
->mac
.ops
.init_uta_tables(hw
);
1933 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1934 * @hw: pointer to hardware structure
1935 * @mc_addr: the multicast address
1937 * Extracts the 12 bits, from a multicast address, to determine which
1938 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1939 * incoming rx multicast addresses, to determine the bit-vector to check in
1940 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1941 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1942 * to mc_filter_type.
1944 static s32
ixgbe_mta_vector(struct ixgbe_hw
*hw
, u8
*mc_addr
)
1948 switch (hw
->mac
.mc_filter_type
) {
1949 case 0: /* use bits [47:36] of the address */
1950 vector
= ((mc_addr
[4] >> 4) | (((u16
)mc_addr
[5]) << 4));
1952 case 1: /* use bits [46:35] of the address */
1953 vector
= ((mc_addr
[4] >> 3) | (((u16
)mc_addr
[5]) << 5));
1955 case 2: /* use bits [45:34] of the address */
1956 vector
= ((mc_addr
[4] >> 2) | (((u16
)mc_addr
[5]) << 6));
1958 case 3: /* use bits [43:32] of the address */
1959 vector
= ((mc_addr
[4]) | (((u16
)mc_addr
[5]) << 8));
1961 default: /* Invalid mc_filter_type */
1962 hw_dbg(hw
, "MC filter type param set incorrectly\n");
1966 /* vector can only be 12-bits or boundary will be exceeded */
1972 * ixgbe_set_mta - Set bit-vector in multicast table
1973 * @hw: pointer to hardware structure
1974 * @hash_value: Multicast address hash value
1976 * Sets the bit-vector in the multicast table.
1978 static void ixgbe_set_mta(struct ixgbe_hw
*hw
, u8
*mc_addr
)
1984 hw
->addr_ctrl
.mta_in_use
++;
1986 vector
= ixgbe_mta_vector(hw
, mc_addr
);
1987 hw_dbg(hw
, " bit-vector = 0x%03X\n", vector
);
1990 * The MTA is a register array of 128 32-bit registers. It is treated
1991 * like an array of 4096 bits. We want to set bit
1992 * BitArray[vector_value]. So we figure out what register the bit is
1993 * in, read it, OR in the new bit, then write back the new value. The
1994 * register is determined by the upper 7 bits of the vector value and
1995 * the bit within that register are determined by the lower 5 bits of
1998 vector_reg
= (vector
>> 5) & 0x7F;
1999 vector_bit
= vector
& 0x1F;
2000 hw
->mac
.mta_shadow
[vector_reg
] |= (1 << vector_bit
);
2004 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2005 * @hw: pointer to hardware structure
2006 * @netdev: pointer to net device structure
2008 * The given list replaces any existing list. Clears the MC addrs from receive
2009 * address registers and the multicast table. Uses unused receive address
2010 * registers for the first multicast addresses, and hashes the rest into the
2013 s32
ixgbe_update_mc_addr_list_generic(struct ixgbe_hw
*hw
,
2014 struct net_device
*netdev
)
2016 struct netdev_hw_addr
*ha
;
2020 * Set the new number of MC addresses that we are being requested to
2023 hw
->addr_ctrl
.num_mc_addrs
= netdev_mc_count(netdev
);
2024 hw
->addr_ctrl
.mta_in_use
= 0;
2026 /* Clear mta_shadow */
2027 hw_dbg(hw
, " Clearing MTA\n");
2028 memset(&hw
->mac
.mta_shadow
, 0, sizeof(hw
->mac
.mta_shadow
));
2030 /* Update mta shadow */
2031 netdev_for_each_mc_addr(ha
, netdev
) {
2032 hw_dbg(hw
, " Adding the multicast addresses:\n");
2033 ixgbe_set_mta(hw
, ha
->addr
);
2037 for (i
= 0; i
< hw
->mac
.mcft_size
; i
++)
2038 IXGBE_WRITE_REG_ARRAY(hw
, IXGBE_MTA(0), i
,
2039 hw
->mac
.mta_shadow
[i
]);
2041 if (hw
->addr_ctrl
.mta_in_use
> 0)
2042 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
,
2043 IXGBE_MCSTCTRL_MFE
| hw
->mac
.mc_filter_type
);
2045 hw_dbg(hw
, "ixgbe_update_mc_addr_list_generic Complete\n");
2050 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2051 * @hw: pointer to hardware structure
2053 * Enables multicast address in RAR and the use of the multicast hash table.
2055 s32
ixgbe_enable_mc_generic(struct ixgbe_hw
*hw
)
2057 struct ixgbe_addr_filter_info
*a
= &hw
->addr_ctrl
;
2059 if (a
->mta_in_use
> 0)
2060 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, IXGBE_MCSTCTRL_MFE
|
2061 hw
->mac
.mc_filter_type
);
2067 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2068 * @hw: pointer to hardware structure
2070 * Disables multicast address in RAR and the use of the multicast hash table.
2072 s32
ixgbe_disable_mc_generic(struct ixgbe_hw
*hw
)
2074 struct ixgbe_addr_filter_info
*a
= &hw
->addr_ctrl
;
2076 if (a
->mta_in_use
> 0)
2077 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, hw
->mac
.mc_filter_type
);
2083 * ixgbe_fc_enable_generic - Enable flow control
2084 * @hw: pointer to hardware structure
2086 * Enable flow control according to the current settings.
2088 s32
ixgbe_fc_enable_generic(struct ixgbe_hw
*hw
)
2091 u32 mflcn_reg
, fccfg_reg
;
2097 * Validate the water mark configuration for packet buffer 0. Zero
2098 * water marks indicate that the packet buffer was not configured
2099 * and the watermarks for packet buffer 0 should always be configured.
2101 if (!hw
->fc
.low_water
||
2102 !hw
->fc
.high_water
[0] ||
2103 !hw
->fc
.pause_time
) {
2104 hw_dbg(hw
, "Invalid water mark configuration\n");
2105 ret_val
= IXGBE_ERR_INVALID_LINK_SETTINGS
;
2109 /* Negotiate the fc mode to use */
2110 ixgbe_fc_autoneg(hw
);
2112 /* Disable any previous flow control settings */
2113 mflcn_reg
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
2114 mflcn_reg
&= ~(IXGBE_MFLCN_RPFCE_MASK
| IXGBE_MFLCN_RFCE
);
2116 fccfg_reg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
2117 fccfg_reg
&= ~(IXGBE_FCCFG_TFCE_802_3X
| IXGBE_FCCFG_TFCE_PRIORITY
);
2120 * The possible values of fc.current_mode are:
2121 * 0: Flow control is completely disabled
2122 * 1: Rx flow control is enabled (we can receive pause frames,
2123 * but not send pause frames).
2124 * 2: Tx flow control is enabled (we can send pause frames but
2125 * we do not support receiving pause frames).
2126 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2129 switch (hw
->fc
.current_mode
) {
2132 * Flow control is disabled by software override or autoneg.
2133 * The code below will actually disable it in the HW.
2136 case ixgbe_fc_rx_pause
:
2138 * Rx Flow control is enabled and Tx Flow control is
2139 * disabled by software override. Since there really
2140 * isn't a way to advertise that we are capable of RX
2141 * Pause ONLY, we will advertise that we support both
2142 * symmetric and asymmetric Rx PAUSE. Later, we will
2143 * disable the adapter's ability to send PAUSE frames.
2145 mflcn_reg
|= IXGBE_MFLCN_RFCE
;
2147 case ixgbe_fc_tx_pause
:
2149 * Tx Flow control is enabled, and Rx Flow control is
2150 * disabled by software override.
2152 fccfg_reg
|= IXGBE_FCCFG_TFCE_802_3X
;
2155 /* Flow control (both Rx and Tx) is enabled by SW override. */
2156 mflcn_reg
|= IXGBE_MFLCN_RFCE
;
2157 fccfg_reg
|= IXGBE_FCCFG_TFCE_802_3X
;
2160 hw_dbg(hw
, "Flow control param set incorrectly\n");
2161 ret_val
= IXGBE_ERR_CONFIG
;
2166 /* Set 802.3x based flow control settings. */
2167 mflcn_reg
|= IXGBE_MFLCN_DPF
;
2168 IXGBE_WRITE_REG(hw
, IXGBE_MFLCN
, mflcn_reg
);
2169 IXGBE_WRITE_REG(hw
, IXGBE_FCCFG
, fccfg_reg
);
2171 fcrtl
= (hw
->fc
.low_water
<< 10) | IXGBE_FCRTL_XONE
;
2173 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2174 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++) {
2175 if ((hw
->fc
.current_mode
& ixgbe_fc_tx_pause
) &&
2176 hw
->fc
.high_water
[i
]) {
2177 IXGBE_WRITE_REG(hw
, IXGBE_FCRTL_82599(i
), fcrtl
);
2178 fcrth
= (hw
->fc
.high_water
[i
] << 10) | IXGBE_FCRTH_FCEN
;
2180 IXGBE_WRITE_REG(hw
, IXGBE_FCRTL_82599(i
), 0);
2182 * In order to prevent Tx hangs when the internal Tx
2183 * switch is enabled we must set the high water mark
2184 * to the maximum FCRTH value. This allows the Tx
2185 * switch to function even under heavy Rx workloads.
2187 fcrth
= IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(i
)) - 32;
2190 IXGBE_WRITE_REG(hw
, IXGBE_FCRTH_82599(i
), fcrth
);
2193 /* Configure pause time (2 TCs per register) */
2194 reg
= hw
->fc
.pause_time
* 0x00010001;
2195 for (i
= 0; i
< (MAX_TRAFFIC_CLASS
/ 2); i
++)
2196 IXGBE_WRITE_REG(hw
, IXGBE_FCTTV(i
), reg
);
2198 IXGBE_WRITE_REG(hw
, IXGBE_FCRTV
, hw
->fc
.pause_time
/ 2);
2205 * ixgbe_negotiate_fc - Negotiate flow control
2206 * @hw: pointer to hardware structure
2207 * @adv_reg: flow control advertised settings
2208 * @lp_reg: link partner's flow control settings
2209 * @adv_sym: symmetric pause bit in advertisement
2210 * @adv_asm: asymmetric pause bit in advertisement
2211 * @lp_sym: symmetric pause bit in link partner advertisement
2212 * @lp_asm: asymmetric pause bit in link partner advertisement
2214 * Find the intersection between advertised settings and link partner's
2215 * advertised settings
2217 static s32
ixgbe_negotiate_fc(struct ixgbe_hw
*hw
, u32 adv_reg
, u32 lp_reg
,
2218 u32 adv_sym
, u32 adv_asm
, u32 lp_sym
, u32 lp_asm
)
2220 if ((!(adv_reg
)) || (!(lp_reg
)))
2221 return IXGBE_ERR_FC_NOT_NEGOTIATED
;
2223 if ((adv_reg
& adv_sym
) && (lp_reg
& lp_sym
)) {
2225 * Now we need to check if the user selected Rx ONLY
2226 * of pause frames. In this case, we had to advertise
2227 * FULL flow control because we could not advertise RX
2228 * ONLY. Hence, we must now check to see if we need to
2229 * turn OFF the TRANSMISSION of PAUSE frames.
2231 if (hw
->fc
.requested_mode
== ixgbe_fc_full
) {
2232 hw
->fc
.current_mode
= ixgbe_fc_full
;
2233 hw_dbg(hw
, "Flow Control = FULL.\n");
2235 hw
->fc
.current_mode
= ixgbe_fc_rx_pause
;
2236 hw_dbg(hw
, "Flow Control=RX PAUSE frames only\n");
2238 } else if (!(adv_reg
& adv_sym
) && (adv_reg
& adv_asm
) &&
2239 (lp_reg
& lp_sym
) && (lp_reg
& lp_asm
)) {
2240 hw
->fc
.current_mode
= ixgbe_fc_tx_pause
;
2241 hw_dbg(hw
, "Flow Control = TX PAUSE frames only.\n");
2242 } else if ((adv_reg
& adv_sym
) && (adv_reg
& adv_asm
) &&
2243 !(lp_reg
& lp_sym
) && (lp_reg
& lp_asm
)) {
2244 hw
->fc
.current_mode
= ixgbe_fc_rx_pause
;
2245 hw_dbg(hw
, "Flow Control = RX PAUSE frames only.\n");
2247 hw
->fc
.current_mode
= ixgbe_fc_none
;
2248 hw_dbg(hw
, "Flow Control = NONE.\n");
2254 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2255 * @hw: pointer to hardware structure
2257 * Enable flow control according on 1 gig fiber.
2259 static s32
ixgbe_fc_autoneg_fiber(struct ixgbe_hw
*hw
)
2261 u32 pcs_anadv_reg
, pcs_lpab_reg
, linkstat
;
2262 s32 ret_val
= IXGBE_ERR_FC_NOT_NEGOTIATED
;
2265 * On multispeed fiber at 1g, bail out if
2266 * - link is up but AN did not complete, or if
2267 * - link is up and AN completed but timed out
2270 linkstat
= IXGBE_READ_REG(hw
, IXGBE_PCS1GLSTA
);
2271 if ((!!(linkstat
& IXGBE_PCS1GLSTA_AN_COMPLETE
) == 0) ||
2272 (!!(linkstat
& IXGBE_PCS1GLSTA_AN_TIMED_OUT
) == 1))
2275 pcs_anadv_reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANA
);
2276 pcs_lpab_reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANLP
);
2278 ret_val
= ixgbe_negotiate_fc(hw
, pcs_anadv_reg
,
2279 pcs_lpab_reg
, IXGBE_PCS1GANA_SYM_PAUSE
,
2280 IXGBE_PCS1GANA_ASM_PAUSE
,
2281 IXGBE_PCS1GANA_SYM_PAUSE
,
2282 IXGBE_PCS1GANA_ASM_PAUSE
);
2289 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2290 * @hw: pointer to hardware structure
2292 * Enable flow control according to IEEE clause 37.
2294 static s32
ixgbe_fc_autoneg_backplane(struct ixgbe_hw
*hw
)
2296 u32 links2
, anlp1_reg
, autoc_reg
, links
;
2297 s32 ret_val
= IXGBE_ERR_FC_NOT_NEGOTIATED
;
2300 * On backplane, bail out if
2301 * - backplane autoneg was not completed, or if
2302 * - we are 82599 and link partner is not AN enabled
2304 links
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
2305 if ((links
& IXGBE_LINKS_KX_AN_COMP
) == 0)
2308 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2309 links2
= IXGBE_READ_REG(hw
, IXGBE_LINKS2
);
2310 if ((links2
& IXGBE_LINKS2_AN_SUPPORTED
) == 0)
2314 * Read the 10g AN autoc and LP ability registers and resolve
2315 * local flow control settings accordingly
2317 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2318 anlp1_reg
= IXGBE_READ_REG(hw
, IXGBE_ANLP1
);
2320 ret_val
= ixgbe_negotiate_fc(hw
, autoc_reg
,
2321 anlp1_reg
, IXGBE_AUTOC_SYM_PAUSE
, IXGBE_AUTOC_ASM_PAUSE
,
2322 IXGBE_ANLP1_SYM_PAUSE
, IXGBE_ANLP1_ASM_PAUSE
);
2329 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2330 * @hw: pointer to hardware structure
2332 * Enable flow control according to IEEE clause 37.
2334 static s32
ixgbe_fc_autoneg_copper(struct ixgbe_hw
*hw
)
2336 u16 technology_ability_reg
= 0;
2337 u16 lp_technology_ability_reg
= 0;
2339 hw
->phy
.ops
.read_reg(hw
, MDIO_AN_ADVERTISE
,
2341 &technology_ability_reg
);
2342 hw
->phy
.ops
.read_reg(hw
, MDIO_AN_LPA
,
2344 &lp_technology_ability_reg
);
2346 return ixgbe_negotiate_fc(hw
, (u32
)technology_ability_reg
,
2347 (u32
)lp_technology_ability_reg
,
2348 IXGBE_TAF_SYM_PAUSE
, IXGBE_TAF_ASM_PAUSE
,
2349 IXGBE_TAF_SYM_PAUSE
, IXGBE_TAF_ASM_PAUSE
);
2353 * ixgbe_fc_autoneg - Configure flow control
2354 * @hw: pointer to hardware structure
2356 * Compares our advertised flow control capabilities to those advertised by
2357 * our link partner, and determines the proper flow control mode to use.
2359 void ixgbe_fc_autoneg(struct ixgbe_hw
*hw
)
2361 s32 ret_val
= IXGBE_ERR_FC_NOT_NEGOTIATED
;
2362 ixgbe_link_speed speed
;
2366 * AN should have completed when the cable was plugged in.
2367 * Look for reasons to bail out. Bail out if:
2368 * - FC autoneg is disabled, or if
2371 * Since we're being called from an LSC, link is already known to be up.
2372 * So use link_up_wait_to_complete=false.
2374 if (hw
->fc
.disable_fc_autoneg
)
2377 hw
->mac
.ops
.check_link(hw
, &speed
, &link_up
, false);
2381 switch (hw
->phy
.media_type
) {
2382 /* Autoneg flow control on fiber adapters */
2383 case ixgbe_media_type_fiber
:
2384 if (speed
== IXGBE_LINK_SPEED_1GB_FULL
)
2385 ret_val
= ixgbe_fc_autoneg_fiber(hw
);
2388 /* Autoneg flow control on backplane adapters */
2389 case ixgbe_media_type_backplane
:
2390 ret_val
= ixgbe_fc_autoneg_backplane(hw
);
2393 /* Autoneg flow control on copper adapters */
2394 case ixgbe_media_type_copper
:
2395 if (ixgbe_device_supports_autoneg_fc(hw
) == 0)
2396 ret_val
= ixgbe_fc_autoneg_copper(hw
);
2405 hw
->fc
.fc_was_autonegged
= true;
2407 hw
->fc
.fc_was_autonegged
= false;
2408 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
2413 * ixgbe_disable_pcie_master - Disable PCI-express master access
2414 * @hw: pointer to hardware structure
2416 * Disables PCI-Express master access and verifies there are no pending
2417 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2418 * bit hasn't caused the master requests to be disabled, else 0
2419 * is returned signifying master requests disabled.
2421 static s32
ixgbe_disable_pcie_master(struct ixgbe_hw
*hw
)
2423 struct ixgbe_adapter
*adapter
= hw
->back
;
2428 /* Always set this bit to ensure any future transactions are blocked */
2429 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, IXGBE_CTRL_GIO_DIS
);
2431 /* Exit if master requests are blocked */
2432 if (!(IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_GIO
))
2435 /* Poll for master request bit to clear */
2436 for (i
= 0; i
< IXGBE_PCI_MASTER_DISABLE_TIMEOUT
; i
++) {
2438 if (!(IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_GIO
))
2443 * Two consecutive resets are required via CTRL.RST per datasheet
2444 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2445 * of this need. The first reset prevents new master requests from
2446 * being issued by our device. We then must wait 1usec or more for any
2447 * remaining completions from the PCIe bus to trickle in, and then reset
2448 * again to clear out any effects they may have had on our device.
2450 hw_dbg(hw
, "GIO Master Disable bit didn't clear - requesting resets\n");
2451 hw
->mac
.flags
|= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
;
2454 * Before proceeding, make sure that the PCIe block does not have
2455 * transactions pending.
2457 for (i
= 0; i
< IXGBE_PCI_MASTER_DISABLE_TIMEOUT
; i
++) {
2459 pci_read_config_word(adapter
->pdev
, IXGBE_PCI_DEVICE_STATUS
,
2461 if (!(value
& IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING
))
2465 hw_dbg(hw
, "PCIe transaction pending bit also did not clear.\n");
2466 status
= IXGBE_ERR_MASTER_REQUESTS_PENDING
;
2473 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2474 * @hw: pointer to hardware structure
2475 * @mask: Mask to specify which semaphore to acquire
2477 * Acquires the SWFW semaphore through the GSSR register for the specified
2478 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2480 s32
ixgbe_acquire_swfw_sync(struct ixgbe_hw
*hw
, u16 mask
)
2484 u32 fwmask
= mask
<< 5;
2489 * SW EEPROM semaphore bit is used for access to all
2490 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2492 if (ixgbe_get_eeprom_semaphore(hw
))
2493 return IXGBE_ERR_SWFW_SYNC
;
2495 gssr
= IXGBE_READ_REG(hw
, IXGBE_GSSR
);
2496 if (!(gssr
& (fwmask
| swmask
)))
2500 * Firmware currently using resource (fwmask) or other software
2501 * thread currently using resource (swmask)
2503 ixgbe_release_eeprom_semaphore(hw
);
2504 usleep_range(5000, 10000);
2509 hw_dbg(hw
, "Driver can't access resource, SW_FW_SYNC timeout.\n");
2510 return IXGBE_ERR_SWFW_SYNC
;
2514 IXGBE_WRITE_REG(hw
, IXGBE_GSSR
, gssr
);
2516 ixgbe_release_eeprom_semaphore(hw
);
2521 * ixgbe_release_swfw_sync - Release SWFW semaphore
2522 * @hw: pointer to hardware structure
2523 * @mask: Mask to specify which semaphore to release
2525 * Releases the SWFW semaphore through the GSSR register for the specified
2526 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2528 void ixgbe_release_swfw_sync(struct ixgbe_hw
*hw
, u16 mask
)
2533 ixgbe_get_eeprom_semaphore(hw
);
2535 gssr
= IXGBE_READ_REG(hw
, IXGBE_GSSR
);
2537 IXGBE_WRITE_REG(hw
, IXGBE_GSSR
, gssr
);
2539 ixgbe_release_eeprom_semaphore(hw
);
2543 * ixgbe_disable_rx_buff_generic - Stops the receive data path
2544 * @hw: pointer to hardware structure
2546 * Stops the receive data path and waits for the HW to internally
2547 * empty the Rx security block.
2549 s32
ixgbe_disable_rx_buff_generic(struct ixgbe_hw
*hw
)
2551 #define IXGBE_MAX_SECRX_POLL 40
2555 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
2556 secrxreg
|= IXGBE_SECRXCTRL_RX_DIS
;
2557 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
2558 for (i
= 0; i
< IXGBE_MAX_SECRX_POLL
; i
++) {
2559 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXSTAT
);
2560 if (secrxreg
& IXGBE_SECRXSTAT_SECRX_RDY
)
2563 /* Use interrupt-safe sleep just in case */
2567 /* For informational purposes only */
2568 if (i
>= IXGBE_MAX_SECRX_POLL
)
2569 hw_dbg(hw
, "Rx unit being enabled before security "
2570 "path fully disabled. Continuing with init.\n");
2577 * ixgbe_enable_rx_buff - Enables the receive data path
2578 * @hw: pointer to hardware structure
2580 * Enables the receive data path
2582 s32
ixgbe_enable_rx_buff_generic(struct ixgbe_hw
*hw
)
2586 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
2587 secrxreg
&= ~IXGBE_SECRXCTRL_RX_DIS
;
2588 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
2589 IXGBE_WRITE_FLUSH(hw
);
2595 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2596 * @hw: pointer to hardware structure
2597 * @regval: register value to write to RXCTRL
2599 * Enables the Rx DMA unit
2601 s32
ixgbe_enable_rx_dma_generic(struct ixgbe_hw
*hw
, u32 regval
)
2603 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, regval
);
2609 * ixgbe_blink_led_start_generic - Blink LED based on index.
2610 * @hw: pointer to hardware structure
2611 * @index: led number to blink
2613 s32
ixgbe_blink_led_start_generic(struct ixgbe_hw
*hw
, u32 index
)
2615 ixgbe_link_speed speed
= 0;
2616 bool link_up
= false;
2617 u32 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2618 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
2621 * Link must be up to auto-blink the LEDs;
2622 * Force it if link is down.
2624 hw
->mac
.ops
.check_link(hw
, &speed
, &link_up
, false);
2627 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
2628 autoc_reg
|= IXGBE_AUTOC_FLU
;
2629 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
2630 IXGBE_WRITE_FLUSH(hw
);
2631 usleep_range(10000, 20000);
2634 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
2635 led_reg
|= IXGBE_LED_BLINK(index
);
2636 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
2637 IXGBE_WRITE_FLUSH(hw
);
2643 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2644 * @hw: pointer to hardware structure
2645 * @index: led number to stop blinking
2647 s32
ixgbe_blink_led_stop_generic(struct ixgbe_hw
*hw
, u32 index
)
2649 u32 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2650 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
2652 autoc_reg
&= ~IXGBE_AUTOC_FLU
;
2653 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
2654 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
2656 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
2657 led_reg
&= ~IXGBE_LED_BLINK(index
);
2658 led_reg
|= IXGBE_LED_LINK_ACTIVE
<< IXGBE_LED_MODE_SHIFT(index
);
2659 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
2660 IXGBE_WRITE_FLUSH(hw
);
2666 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2667 * @hw: pointer to hardware structure
2668 * @san_mac_offset: SAN MAC address offset
2670 * This function will read the EEPROM location for the SAN MAC address
2671 * pointer, and returns the value at that location. This is used in both
2672 * get and set mac_addr routines.
2674 static s32
ixgbe_get_san_mac_addr_offset(struct ixgbe_hw
*hw
,
2675 u16
*san_mac_offset
)
2678 * First read the EEPROM pointer to see if the MAC addresses are
2681 hw
->eeprom
.ops
.read(hw
, IXGBE_SAN_MAC_ADDR_PTR
, san_mac_offset
);
2687 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2688 * @hw: pointer to hardware structure
2689 * @san_mac_addr: SAN MAC address
2691 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2692 * per-port, so set_lan_id() must be called before reading the addresses.
2693 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2694 * upon for non-SFP connections, so we must call it here.
2696 s32
ixgbe_get_san_mac_addr_generic(struct ixgbe_hw
*hw
, u8
*san_mac_addr
)
2698 u16 san_mac_data
, san_mac_offset
;
2702 * First read the EEPROM pointer to see if the MAC addresses are
2703 * available. If they're not, no point in calling set_lan_id() here.
2705 ixgbe_get_san_mac_addr_offset(hw
, &san_mac_offset
);
2707 if ((san_mac_offset
== 0) || (san_mac_offset
== 0xFFFF)) {
2709 * No addresses available in this EEPROM. It's not an
2710 * error though, so just wipe the local address and return.
2712 for (i
= 0; i
< 6; i
++)
2713 san_mac_addr
[i
] = 0xFF;
2715 goto san_mac_addr_out
;
2718 /* make sure we know which port we need to program */
2719 hw
->mac
.ops
.set_lan_id(hw
);
2720 /* apply the port offset to the address offset */
2721 (hw
->bus
.func
) ? (san_mac_offset
+= IXGBE_SAN_MAC_ADDR_PORT1_OFFSET
) :
2722 (san_mac_offset
+= IXGBE_SAN_MAC_ADDR_PORT0_OFFSET
);
2723 for (i
= 0; i
< 3; i
++) {
2724 hw
->eeprom
.ops
.read(hw
, san_mac_offset
, &san_mac_data
);
2725 san_mac_addr
[i
* 2] = (u8
)(san_mac_data
);
2726 san_mac_addr
[i
* 2 + 1] = (u8
)(san_mac_data
>> 8);
2735 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2736 * @hw: pointer to hardware structure
2738 * Read PCIe configuration space, and get the MSI-X vector count from
2739 * the capabilities table.
2741 u16
ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw
*hw
)
2743 struct ixgbe_adapter
*adapter
= hw
->back
;
2748 switch (hw
->mac
.type
) {
2749 case ixgbe_mac_82598EB
:
2750 pcie_offset
= IXGBE_PCIE_MSIX_82598_CAPS
;
2751 max_msix_count
= IXGBE_MAX_MSIX_VECTORS_82598
;
2753 case ixgbe_mac_82599EB
:
2754 case ixgbe_mac_X540
:
2755 pcie_offset
= IXGBE_PCIE_MSIX_82599_CAPS
;
2756 max_msix_count
= IXGBE_MAX_MSIX_VECTORS_82599
;
2762 pci_read_config_word(adapter
->pdev
, pcie_offset
, &msix_count
);
2763 msix_count
&= IXGBE_PCIE_MSIX_TBL_SZ_MASK
;
2765 /* MSI-X count is zero-based in HW */
2768 if (msix_count
> max_msix_count
)
2769 msix_count
= max_msix_count
;
2775 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2776 * @hw: pointer to hardware struct
2777 * @rar: receive address register index to disassociate
2778 * @vmdq: VMDq pool index to remove from the rar
2780 s32
ixgbe_clear_vmdq_generic(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
2782 u32 mpsar_lo
, mpsar_hi
;
2783 u32 rar_entries
= hw
->mac
.num_rar_entries
;
2785 /* Make sure we are using a valid rar index range */
2786 if (rar
>= rar_entries
) {
2787 hw_dbg(hw
, "RAR index %d is out of range.\n", rar
);
2788 return IXGBE_ERR_INVALID_ARGUMENT
;
2791 mpsar_lo
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_LO(rar
));
2792 mpsar_hi
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_HI(rar
));
2794 if (!mpsar_lo
&& !mpsar_hi
)
2797 if (vmdq
== IXGBE_CLEAR_VMDQ_ALL
) {
2799 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), 0);
2803 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), 0);
2806 } else if (vmdq
< 32) {
2807 mpsar_lo
&= ~(1 << vmdq
);
2808 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), mpsar_lo
);
2810 mpsar_hi
&= ~(1 << (vmdq
- 32));
2811 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), mpsar_hi
);
2814 /* was that the last pool using this rar? */
2815 if (mpsar_lo
== 0 && mpsar_hi
== 0 && rar
!= 0)
2816 hw
->mac
.ops
.clear_rar(hw
, rar
);
2822 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2823 * @hw: pointer to hardware struct
2824 * @rar: receive address register index to associate with a VMDq index
2825 * @vmdq: VMDq pool index
2827 s32
ixgbe_set_vmdq_generic(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
2830 u32 rar_entries
= hw
->mac
.num_rar_entries
;
2832 /* Make sure we are using a valid rar index range */
2833 if (rar
>= rar_entries
) {
2834 hw_dbg(hw
, "RAR index %d is out of range.\n", rar
);
2835 return IXGBE_ERR_INVALID_ARGUMENT
;
2839 mpsar
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_LO(rar
));
2841 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), mpsar
);
2843 mpsar
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_HI(rar
));
2844 mpsar
|= 1 << (vmdq
- 32);
2845 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), mpsar
);
2851 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2852 * @hw: pointer to hardware structure
2854 s32
ixgbe_init_uta_tables_generic(struct ixgbe_hw
*hw
)
2858 for (i
= 0; i
< 128; i
++)
2859 IXGBE_WRITE_REG(hw
, IXGBE_UTA(i
), 0);
2865 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2866 * @hw: pointer to hardware structure
2867 * @vlan: VLAN id to write to VLAN filter
2869 * return the VLVF index where this VLAN id should be placed
2872 static s32
ixgbe_find_vlvf_slot(struct ixgbe_hw
*hw
, u32 vlan
)
2875 u32 first_empty_slot
= 0;
2878 /* short cut the special case */
2883 * Search for the vlan id in the VLVF entries. Save off the first empty
2884 * slot found along the way
2886 for (regindex
= 1; regindex
< IXGBE_VLVF_ENTRIES
; regindex
++) {
2887 bits
= IXGBE_READ_REG(hw
, IXGBE_VLVF(regindex
));
2888 if (!bits
&& !(first_empty_slot
))
2889 first_empty_slot
= regindex
;
2890 else if ((bits
& 0x0FFF) == vlan
)
2895 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2896 * in the VLVF. Else use the first empty VLVF register for this
2899 if (regindex
>= IXGBE_VLVF_ENTRIES
) {
2900 if (first_empty_slot
)
2901 regindex
= first_empty_slot
;
2903 hw_dbg(hw
, "No space in VLVF.\n");
2904 regindex
= IXGBE_ERR_NO_SPACE
;
2912 * ixgbe_set_vfta_generic - Set VLAN filter table
2913 * @hw: pointer to hardware structure
2914 * @vlan: VLAN id to write to VLAN filter
2915 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2916 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2918 * Turn on/off specified VLAN in the VLAN filter table.
2920 s32
ixgbe_set_vfta_generic(struct ixgbe_hw
*hw
, u32 vlan
, u32 vind
,
2929 bool vfta_changed
= false;
2932 return IXGBE_ERR_PARAM
;
2935 * this is a 2 part operation - first the VFTA, then the
2936 * VLVF and VLVFB if VT Mode is set
2937 * We don't write the VFTA until we know the VLVF part succeeded.
2941 * The VFTA is a bitstring made up of 128 32-bit registers
2942 * that enable the particular VLAN id, much like the MTA:
2943 * bits[11-5]: which register
2944 * bits[4-0]: which bit in the register
2946 regindex
= (vlan
>> 5) & 0x7F;
2947 bitindex
= vlan
& 0x1F;
2948 targetbit
= (1 << bitindex
);
2949 vfta
= IXGBE_READ_REG(hw
, IXGBE_VFTA(regindex
));
2952 if (!(vfta
& targetbit
)) {
2954 vfta_changed
= true;
2957 if ((vfta
& targetbit
)) {
2959 vfta_changed
= true;
2966 * make sure the vlan is in VLVF
2967 * set the vind bit in the matching VLVFB
2969 * clear the pool bit and possibly the vind
2971 vt
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
2972 if (vt
& IXGBE_VT_CTL_VT_ENABLE
) {
2975 vlvf_index
= ixgbe_find_vlvf_slot(hw
, vlan
);
2980 /* set the pool bit */
2982 bits
= IXGBE_READ_REG(hw
,
2983 IXGBE_VLVFB(vlvf_index
*2));
2984 bits
|= (1 << vind
);
2986 IXGBE_VLVFB(vlvf_index
*2),
2989 bits
= IXGBE_READ_REG(hw
,
2990 IXGBE_VLVFB((vlvf_index
*2)+1));
2991 bits
|= (1 << (vind
-32));
2993 IXGBE_VLVFB((vlvf_index
*2)+1),
2997 /* clear the pool bit */
2999 bits
= IXGBE_READ_REG(hw
,
3000 IXGBE_VLVFB(vlvf_index
*2));
3001 bits
&= ~(1 << vind
);
3003 IXGBE_VLVFB(vlvf_index
*2),
3005 bits
|= IXGBE_READ_REG(hw
,
3006 IXGBE_VLVFB((vlvf_index
*2)+1));
3008 bits
= IXGBE_READ_REG(hw
,
3009 IXGBE_VLVFB((vlvf_index
*2)+1));
3010 bits
&= ~(1 << (vind
-32));
3012 IXGBE_VLVFB((vlvf_index
*2)+1),
3014 bits
|= IXGBE_READ_REG(hw
,
3015 IXGBE_VLVFB(vlvf_index
*2));
3020 * If there are still bits set in the VLVFB registers
3021 * for the VLAN ID indicated we need to see if the
3022 * caller is requesting that we clear the VFTA entry bit.
3023 * If the caller has requested that we clear the VFTA
3024 * entry bit but there are still pools/VFs using this VLAN
3025 * ID entry then ignore the request. We're not worried
3026 * about the case where we're turning the VFTA VLAN ID
3027 * entry bit on, only when requested to turn it off as
3028 * there may be multiple pools and/or VFs using the
3029 * VLAN ID entry. In that case we cannot clear the
3030 * VFTA bit until all pools/VFs using that VLAN ID have also
3031 * been cleared. This will be indicated by "bits" being
3035 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(vlvf_index
),
3036 (IXGBE_VLVF_VIEN
| vlan
));
3038 /* someone wants to clear the vfta entry
3039 * but some pools/VFs are still using it.
3041 vfta_changed
= false;
3045 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(vlvf_index
), 0);
3049 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(regindex
), vfta
);
3055 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3056 * @hw: pointer to hardware structure
3058 * Clears the VLAN filer table, and the VMDq index associated with the filter
3060 s32
ixgbe_clear_vfta_generic(struct ixgbe_hw
*hw
)
3064 for (offset
= 0; offset
< hw
->mac
.vft_size
; offset
++)
3065 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(offset
), 0);
3067 for (offset
= 0; offset
< IXGBE_VLVF_ENTRIES
; offset
++) {
3068 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(offset
), 0);
3069 IXGBE_WRITE_REG(hw
, IXGBE_VLVFB(offset
*2), 0);
3070 IXGBE_WRITE_REG(hw
, IXGBE_VLVFB((offset
*2)+1), 0);
3077 * ixgbe_check_mac_link_generic - Determine link and speed status
3078 * @hw: pointer to hardware structure
3079 * @speed: pointer to link speed
3080 * @link_up: true when link is up
3081 * @link_up_wait_to_complete: bool used to wait for link up or not
3083 * Reads the links register to determine if link is up and the current speed
3085 s32
ixgbe_check_mac_link_generic(struct ixgbe_hw
*hw
, ixgbe_link_speed
*speed
,
3086 bool *link_up
, bool link_up_wait_to_complete
)
3088 u32 links_reg
, links_orig
;
3091 /* clear the old state */
3092 links_orig
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
3094 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
3096 if (links_orig
!= links_reg
) {
3097 hw_dbg(hw
, "LINKS changed from %08X to %08X\n",
3098 links_orig
, links_reg
);
3101 if (link_up_wait_to_complete
) {
3102 for (i
= 0; i
< IXGBE_LINK_UP_TIME
; i
++) {
3103 if (links_reg
& IXGBE_LINKS_UP
) {
3110 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
3113 if (links_reg
& IXGBE_LINKS_UP
)
3119 if ((links_reg
& IXGBE_LINKS_SPEED_82599
) ==
3120 IXGBE_LINKS_SPEED_10G_82599
)
3121 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
3122 else if ((links_reg
& IXGBE_LINKS_SPEED_82599
) ==
3123 IXGBE_LINKS_SPEED_1G_82599
)
3124 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
3125 else if ((links_reg
& IXGBE_LINKS_SPEED_82599
) ==
3126 IXGBE_LINKS_SPEED_100_82599
)
3127 *speed
= IXGBE_LINK_SPEED_100_FULL
;
3129 *speed
= IXGBE_LINK_SPEED_UNKNOWN
;
3135 * ixgbe_get_wwn_prefix_generic Get alternative WWNN/WWPN prefix from
3137 * @hw: pointer to hardware structure
3138 * @wwnn_prefix: the alternative WWNN prefix
3139 * @wwpn_prefix: the alternative WWPN prefix
3141 * This function will read the EEPROM from the alternative SAN MAC address
3142 * block to check the support for the alternative WWNN/WWPN prefix support.
3144 s32
ixgbe_get_wwn_prefix_generic(struct ixgbe_hw
*hw
, u16
*wwnn_prefix
,
3148 u16 alt_san_mac_blk_offset
;
3150 /* clear output first */
3151 *wwnn_prefix
= 0xFFFF;
3152 *wwpn_prefix
= 0xFFFF;
3154 /* check if alternative SAN MAC is supported */
3155 hw
->eeprom
.ops
.read(hw
, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR
,
3156 &alt_san_mac_blk_offset
);
3158 if ((alt_san_mac_blk_offset
== 0) ||
3159 (alt_san_mac_blk_offset
== 0xFFFF))
3160 goto wwn_prefix_out
;
3162 /* check capability in alternative san mac address block */
3163 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET
;
3164 hw
->eeprom
.ops
.read(hw
, offset
, &caps
);
3165 if (!(caps
& IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN
))
3166 goto wwn_prefix_out
;
3168 /* get the corresponding prefix for WWNN/WWPN */
3169 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET
;
3170 hw
->eeprom
.ops
.read(hw
, offset
, wwnn_prefix
);
3172 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET
;
3173 hw
->eeprom
.ops
.read(hw
, offset
, wwpn_prefix
);
3180 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3181 * @hw: pointer to hardware structure
3182 * @enable: enable or disable switch for anti-spoofing
3183 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3186 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw
*hw
, bool enable
, int pf
)
3189 int pf_target_reg
= pf
>> 3;
3190 int pf_target_shift
= pf
% 8;
3193 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3197 pfvfspoof
= IXGBE_SPOOF_MACAS_MASK
;
3200 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3201 * MAC anti-spoof enables in each register array element.
3203 for (j
= 0; j
< IXGBE_PFVFSPOOF_REG_COUNT
; j
++)
3204 IXGBE_WRITE_REG(hw
, IXGBE_PFVFSPOOF(j
), pfvfspoof
);
3206 /* If not enabling anti-spoofing then done */
3211 * The PF should be allowed to spoof so that it can support
3212 * emulation mode NICs. Reset the bit assigned to the PF
3214 pfvfspoof
= IXGBE_READ_REG(hw
, IXGBE_PFVFSPOOF(pf_target_reg
));
3215 pfvfspoof
^= (1 << pf_target_shift
);
3216 IXGBE_WRITE_REG(hw
, IXGBE_PFVFSPOOF(pf_target_reg
), pfvfspoof
);
3220 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3221 * @hw: pointer to hardware structure
3222 * @enable: enable or disable switch for VLAN anti-spoofing
3223 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3226 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw
*hw
, bool enable
, int vf
)
3228 int vf_target_reg
= vf
>> 3;
3229 int vf_target_shift
= vf
% 8 + IXGBE_SPOOF_VLANAS_SHIFT
;
3232 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3235 pfvfspoof
= IXGBE_READ_REG(hw
, IXGBE_PFVFSPOOF(vf_target_reg
));
3237 pfvfspoof
|= (1 << vf_target_shift
);
3239 pfvfspoof
&= ~(1 << vf_target_shift
);
3240 IXGBE_WRITE_REG(hw
, IXGBE_PFVFSPOOF(vf_target_reg
), pfvfspoof
);
3244 * ixgbe_get_device_caps_generic - Get additional device capabilities
3245 * @hw: pointer to hardware structure
3246 * @device_caps: the EEPROM word with the extra device capabilities
3248 * This function will read the EEPROM location for the device capabilities,
3249 * and return the word through device_caps.
3251 s32
ixgbe_get_device_caps_generic(struct ixgbe_hw
*hw
, u16
*device_caps
)
3253 hw
->eeprom
.ops
.read(hw
, IXGBE_DEVICE_CAPS
, device_caps
);
3259 * ixgbe_set_rxpba_generic - Initialize RX packet buffer
3260 * @hw: pointer to hardware structure
3261 * @num_pb: number of packet buffers to allocate
3262 * @headroom: reserve n KB of headroom
3263 * @strategy: packet buffer allocation strategy
3265 void ixgbe_set_rxpba_generic(struct ixgbe_hw
*hw
,
3270 u32 pbsize
= hw
->mac
.rx_pb_size
;
3272 u32 rxpktsize
, txpktsize
, txpbthresh
;
3274 /* Reserve headroom */
3280 /* Divide remaining packet buffer space amongst the number
3281 * of packet buffers requested using supplied strategy.
3284 case (PBA_STRATEGY_WEIGHTED
):
3285 /* pba_80_48 strategy weight first half of packet buffer with
3286 * 5/8 of the packet buffer space.
3288 rxpktsize
= ((pbsize
* 5 * 2) / (num_pb
* 8));
3289 pbsize
-= rxpktsize
* (num_pb
/ 2);
3290 rxpktsize
<<= IXGBE_RXPBSIZE_SHIFT
;
3291 for (; i
< (num_pb
/ 2); i
++)
3292 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), rxpktsize
);
3293 /* Fall through to configure remaining packet buffers */
3294 case (PBA_STRATEGY_EQUAL
):
3295 /* Divide the remaining Rx packet buffer evenly among the TCs */
3296 rxpktsize
= (pbsize
/ (num_pb
- i
)) << IXGBE_RXPBSIZE_SHIFT
;
3297 for (; i
< num_pb
; i
++)
3298 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), rxpktsize
);
3305 * Setup Tx packet buffer and threshold equally for all TCs
3306 * TXPBTHRESH register is set in K so divide by 1024 and subtract
3307 * 10 since the largest packet we support is just over 9K.
3309 txpktsize
= IXGBE_TXPBSIZE_MAX
/ num_pb
;
3310 txpbthresh
= (txpktsize
/ 1024) - IXGBE_TXPKT_SIZE_MAX
;
3311 for (i
= 0; i
< num_pb
; i
++) {
3312 IXGBE_WRITE_REG(hw
, IXGBE_TXPBSIZE(i
), txpktsize
);
3313 IXGBE_WRITE_REG(hw
, IXGBE_TXPBTHRESH(i
), txpbthresh
);
3316 /* Clear unused TCs, if any, to zero buffer size*/
3317 for (; i
< IXGBE_MAX_PB
; i
++) {
3318 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), 0);
3319 IXGBE_WRITE_REG(hw
, IXGBE_TXPBSIZE(i
), 0);
3320 IXGBE_WRITE_REG(hw
, IXGBE_TXPBTHRESH(i
), 0);
3325 * ixgbe_calculate_checksum - Calculate checksum for buffer
3326 * @buffer: pointer to EEPROM
3327 * @length: size of EEPROM to calculate a checksum for
3328 * Calculates the checksum for some buffer on a specified length. The
3329 * checksum calculated is returned.
3331 static u8
ixgbe_calculate_checksum(u8
*buffer
, u32 length
)
3339 for (i
= 0; i
< length
; i
++)
3342 return (u8
) (0 - sum
);
3346 * ixgbe_host_interface_command - Issue command to manageability block
3347 * @hw: pointer to the HW structure
3348 * @buffer: contains the command to write and where the return status will
3350 * @length: length of buffer, must be multiple of 4 bytes
3352 * Communicates with the manageability block. On success return 0
3353 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3355 static s32
ixgbe_host_interface_command(struct ixgbe_hw
*hw
, u32
*buffer
,
3359 u32 hdr_size
= sizeof(struct ixgbe_hic_hdr
);
3360 u8 buf_len
, dword_len
;
3364 if (length
== 0 || length
& 0x3 ||
3365 length
> IXGBE_HI_MAX_BLOCK_BYTE_LENGTH
) {
3366 hw_dbg(hw
, "Buffer length failure.\n");
3367 ret_val
= IXGBE_ERR_HOST_INTERFACE_COMMAND
;
3371 /* Check that the host interface is enabled. */
3372 hicr
= IXGBE_READ_REG(hw
, IXGBE_HICR
);
3373 if ((hicr
& IXGBE_HICR_EN
) == 0) {
3374 hw_dbg(hw
, "IXGBE_HOST_EN bit disabled.\n");
3375 ret_val
= IXGBE_ERR_HOST_INTERFACE_COMMAND
;
3379 /* Calculate length in DWORDs */
3380 dword_len
= length
>> 2;
3383 * The device driver writes the relevant command block
3384 * into the ram area.
3386 for (i
= 0; i
< dword_len
; i
++)
3387 IXGBE_WRITE_REG_ARRAY(hw
, IXGBE_FLEX_MNG
,
3388 i
, cpu_to_le32(buffer
[i
]));
3390 /* Setting this bit tells the ARC that a new command is pending. */
3391 IXGBE_WRITE_REG(hw
, IXGBE_HICR
, hicr
| IXGBE_HICR_C
);
3393 for (i
= 0; i
< IXGBE_HI_COMMAND_TIMEOUT
; i
++) {
3394 hicr
= IXGBE_READ_REG(hw
, IXGBE_HICR
);
3395 if (!(hicr
& IXGBE_HICR_C
))
3397 usleep_range(1000, 2000);
3400 /* Check command successful completion. */
3401 if (i
== IXGBE_HI_COMMAND_TIMEOUT
||
3402 (!(IXGBE_READ_REG(hw
, IXGBE_HICR
) & IXGBE_HICR_SV
))) {
3403 hw_dbg(hw
, "Command has failed with no status valid.\n");
3404 ret_val
= IXGBE_ERR_HOST_INTERFACE_COMMAND
;
3408 /* Calculate length in DWORDs */
3409 dword_len
= hdr_size
>> 2;
3411 /* first pull in the header so we know the buffer length */
3412 for (bi
= 0; bi
< dword_len
; bi
++) {
3413 buffer
[bi
] = IXGBE_READ_REG_ARRAY(hw
, IXGBE_FLEX_MNG
, bi
);
3414 le32_to_cpus(&buffer
[bi
]);
3417 /* If there is any thing in data position pull it in */
3418 buf_len
= ((struct ixgbe_hic_hdr
*)buffer
)->buf_len
;
3422 if (length
< (buf_len
+ hdr_size
)) {
3423 hw_dbg(hw
, "Buffer not large enough for reply message.\n");
3424 ret_val
= IXGBE_ERR_HOST_INTERFACE_COMMAND
;
3428 /* Calculate length in DWORDs, add 3 for odd lengths */
3429 dword_len
= (buf_len
+ 3) >> 2;
3431 /* Pull in the rest of the buffer (bi is where we left off)*/
3432 for (; bi
<= dword_len
; bi
++) {
3433 buffer
[bi
] = IXGBE_READ_REG_ARRAY(hw
, IXGBE_FLEX_MNG
, bi
);
3434 le32_to_cpus(&buffer
[bi
]);
3442 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3443 * @hw: pointer to the HW structure
3444 * @maj: driver version major number
3445 * @min: driver version minor number
3446 * @build: driver version build number
3447 * @sub: driver version sub build number
3449 * Sends driver version number to firmware through the manageability
3450 * block. On success return 0
3451 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3452 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3454 s32
ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw
*hw
, u8 maj
, u8 min
,
3457 struct ixgbe_hic_drv_info fw_cmd
;
3461 if (hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_SW_MNG_SM
) != 0) {
3462 ret_val
= IXGBE_ERR_SWFW_SYNC
;
3466 fw_cmd
.hdr
.cmd
= FW_CEM_CMD_DRIVER_INFO
;
3467 fw_cmd
.hdr
.buf_len
= FW_CEM_CMD_DRIVER_INFO_LEN
;
3468 fw_cmd
.hdr
.cmd_or_resp
.cmd_resv
= FW_CEM_CMD_RESERVED
;
3469 fw_cmd
.port_num
= (u8
)hw
->bus
.func
;
3470 fw_cmd
.ver_maj
= maj
;
3471 fw_cmd
.ver_min
= min
;
3472 fw_cmd
.ver_build
= build
;
3473 fw_cmd
.ver_sub
= sub
;
3474 fw_cmd
.hdr
.checksum
= 0;
3475 fw_cmd
.hdr
.checksum
= ixgbe_calculate_checksum((u8
*)&fw_cmd
,
3476 (FW_CEM_HDR_LEN
+ fw_cmd
.hdr
.buf_len
));
3480 for (i
= 0; i
<= FW_CEM_MAX_RETRIES
; i
++) {
3481 ret_val
= ixgbe_host_interface_command(hw
, (u32
*)&fw_cmd
,
3486 if (fw_cmd
.hdr
.cmd_or_resp
.ret_status
==
3487 FW_CEM_RESP_STATUS_SUCCESS
)
3490 ret_val
= IXGBE_ERR_HOST_INTERFACE_COMMAND
;
3495 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_SW_MNG_SM
);
3501 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3502 * @hw: pointer to the hardware structure
3504 * The 82599 and x540 MACs can experience issues if TX work is still pending
3505 * when a reset occurs. This function prevents this by flushing the PCIe
3506 * buffers on the system.
3508 void ixgbe_clear_tx_pending(struct ixgbe_hw
*hw
)
3510 u32 gcr_ext
, hlreg0
;
3513 * If double reset is not requested then all transactions should
3514 * already be clear and as such there is no work to do
3516 if (!(hw
->mac
.flags
& IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
))
3520 * Set loopback enable to prevent any transmits from being sent
3521 * should the link come up. This assumes that the RXCTRL.RXEN bit
3522 * has already been cleared.
3524 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
3525 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
| IXGBE_HLREG0_LPBK
);
3527 /* initiate cleaning flow for buffers in the PCIe transaction layer */
3528 gcr_ext
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
3529 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
,
3530 gcr_ext
| IXGBE_GCR_EXT_BUFFERS_CLEAR
);
3532 /* Flush all writes and allow 20usec for all transactions to clear */
3533 IXGBE_WRITE_FLUSH(hw
);
3536 /* restore previous register values */
3537 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr_ext
);
3538 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
3541 static const u8 ixgbe_emc_temp_data
[4] = {
3542 IXGBE_EMC_INTERNAL_DATA
,
3543 IXGBE_EMC_DIODE1_DATA
,
3544 IXGBE_EMC_DIODE2_DATA
,
3545 IXGBE_EMC_DIODE3_DATA
3547 static const u8 ixgbe_emc_therm_limit
[4] = {
3548 IXGBE_EMC_INTERNAL_THERM_LIMIT
,
3549 IXGBE_EMC_DIODE1_THERM_LIMIT
,
3550 IXGBE_EMC_DIODE2_THERM_LIMIT
,
3551 IXGBE_EMC_DIODE3_THERM_LIMIT
3555 * ixgbe_get_ets_data - Extracts the ETS bit data
3556 * @hw: pointer to hardware structure
3557 * @ets_cfg: extected ETS data
3558 * @ets_offset: offset of ETS data
3560 * Returns error code.
3562 static s32
ixgbe_get_ets_data(struct ixgbe_hw
*hw
, u16
*ets_cfg
,
3567 status
= hw
->eeprom
.ops
.read(hw
, IXGBE_ETS_CFG
, ets_offset
);
3571 if ((*ets_offset
== 0x0000) || (*ets_offset
== 0xFFFF)) {
3572 status
= IXGBE_NOT_IMPLEMENTED
;
3576 status
= hw
->eeprom
.ops
.read(hw
, *ets_offset
, ets_cfg
);
3580 if ((*ets_cfg
& IXGBE_ETS_TYPE_MASK
) != IXGBE_ETS_TYPE_EMC_SHIFTED
) {
3581 status
= IXGBE_NOT_IMPLEMENTED
;
3590 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
3591 * @hw: pointer to hardware structure
3593 * Returns the thermal sensor data structure
3595 s32
ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw
*hw
)
3603 struct ixgbe_thermal_sensor_data
*data
= &hw
->mac
.thermal_sensor_data
;
3605 /* Only support thermal sensors attached to physical port 0 */
3606 if ((IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_LAN_ID_1
)) {
3607 status
= IXGBE_NOT_IMPLEMENTED
;
3611 status
= ixgbe_get_ets_data(hw
, &ets_cfg
, &ets_offset
);
3615 num_sensors
= (ets_cfg
& IXGBE_ETS_NUM_SENSORS_MASK
);
3616 if (num_sensors
> IXGBE_MAX_SENSORS
)
3617 num_sensors
= IXGBE_MAX_SENSORS
;
3619 for (i
= 0; i
< num_sensors
; i
++) {
3623 status
= hw
->eeprom
.ops
.read(hw
, (ets_offset
+ 1 + i
),
3628 sensor_index
= ((ets_sensor
& IXGBE_ETS_DATA_INDEX_MASK
) >>
3629 IXGBE_ETS_DATA_INDEX_SHIFT
);
3630 sensor_location
= ((ets_sensor
& IXGBE_ETS_DATA_LOC_MASK
) >>
3631 IXGBE_ETS_DATA_LOC_SHIFT
);
3633 if (sensor_location
!= 0) {
3634 status
= hw
->phy
.ops
.read_i2c_byte(hw
,
3635 ixgbe_emc_temp_data
[sensor_index
],
3636 IXGBE_I2C_THERMAL_SENSOR_ADDR
,
3637 &data
->sensor
[i
].temp
);
3647 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
3648 * @hw: pointer to hardware structure
3650 * Inits the thermal sensor thresholds according to the NVM map
3651 * and save off the threshold and location values into mac.thermal_sensor_data
3653 s32
ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw
*hw
)
3659 u8 low_thresh_delta
;
3663 struct ixgbe_thermal_sensor_data
*data
= &hw
->mac
.thermal_sensor_data
;
3665 memset(data
, 0, sizeof(struct ixgbe_thermal_sensor_data
));
3667 /* Only support thermal sensors attached to physical port 0 */
3668 if ((IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_LAN_ID_1
)) {
3669 status
= IXGBE_NOT_IMPLEMENTED
;
3673 status
= ixgbe_get_ets_data(hw
, &ets_cfg
, &ets_offset
);
3677 low_thresh_delta
= ((ets_cfg
& IXGBE_ETS_LTHRES_DELTA_MASK
) >>
3678 IXGBE_ETS_LTHRES_DELTA_SHIFT
);
3679 num_sensors
= (ets_cfg
& IXGBE_ETS_NUM_SENSORS_MASK
);
3680 if (num_sensors
> IXGBE_MAX_SENSORS
)
3681 num_sensors
= IXGBE_MAX_SENSORS
;
3683 for (i
= 0; i
< num_sensors
; i
++) {
3687 hw
->eeprom
.ops
.read(hw
, (ets_offset
+ 1 + i
), &ets_sensor
);
3688 sensor_index
= ((ets_sensor
& IXGBE_ETS_DATA_INDEX_MASK
) >>
3689 IXGBE_ETS_DATA_INDEX_SHIFT
);
3690 sensor_location
= ((ets_sensor
& IXGBE_ETS_DATA_LOC_MASK
) >>
3691 IXGBE_ETS_DATA_LOC_SHIFT
);
3692 therm_limit
= ets_sensor
& IXGBE_ETS_DATA_HTHRESH_MASK
;
3694 hw
->phy
.ops
.write_i2c_byte(hw
,
3695 ixgbe_emc_therm_limit
[sensor_index
],
3696 IXGBE_I2C_THERMAL_SENSOR_ADDR
, therm_limit
);
3698 if (sensor_location
== 0)
3701 data
->sensor
[i
].location
= sensor_location
;
3702 data
->sensor
[i
].caution_thresh
= therm_limit
;
3703 data
->sensor
[i
].max_op_thresh
= therm_limit
- low_thresh_delta
;