1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2014 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #ifndef _IXGBE_COMMON_H_
30 #define _IXGBE_COMMON_H_
32 #include "ixgbe_type.h"
35 u16
ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw
*hw
);
36 s32
ixgbe_init_ops_generic(struct ixgbe_hw
*hw
);
37 s32
ixgbe_init_hw_generic(struct ixgbe_hw
*hw
);
38 s32
ixgbe_start_hw_generic(struct ixgbe_hw
*hw
);
39 s32
ixgbe_start_hw_gen2(struct ixgbe_hw
*hw
);
40 s32
ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw
*hw
);
41 s32
ixgbe_read_pba_string_generic(struct ixgbe_hw
*hw
, u8
*pba_num
,
43 s32
ixgbe_get_mac_addr_generic(struct ixgbe_hw
*hw
, u8
*mac_addr
);
44 enum ixgbe_bus_width
ixgbe_convert_bus_width(u16 link_status
);
45 enum ixgbe_bus_speed
ixgbe_convert_bus_speed(u16 link_status
);
46 s32
ixgbe_get_bus_info_generic(struct ixgbe_hw
*hw
);
47 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw
*hw
);
48 s32
ixgbe_stop_adapter_generic(struct ixgbe_hw
*hw
);
50 s32
ixgbe_led_on_generic(struct ixgbe_hw
*hw
, u32 index
);
51 s32
ixgbe_led_off_generic(struct ixgbe_hw
*hw
, u32 index
);
53 s32
ixgbe_init_eeprom_params_generic(struct ixgbe_hw
*hw
);
54 s32
ixgbe_write_eeprom_generic(struct ixgbe_hw
*hw
, u16 offset
, u16 data
);
55 s32
ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw
*hw
, u16 offset
,
56 u16 words
, u16
*data
);
57 s32
ixgbe_read_eerd_generic(struct ixgbe_hw
*hw
, u16 offset
, u16
*data
);
58 s32
ixgbe_read_eerd_buffer_generic(struct ixgbe_hw
*hw
, u16 offset
,
59 u16 words
, u16
*data
);
60 s32
ixgbe_write_eewr_generic(struct ixgbe_hw
*hw
, u16 offset
, u16 data
);
61 s32
ixgbe_write_eewr_buffer_generic(struct ixgbe_hw
*hw
, u16 offset
,
62 u16 words
, u16
*data
);
63 s32
ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw
*hw
, u16 offset
,
65 s32
ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw
*hw
, u16 offset
,
66 u16 words
, u16
*data
);
67 s32
ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw
*hw
);
68 s32
ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw
*hw
,
70 s32
ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw
*hw
);
72 s32
ixgbe_set_rar_generic(struct ixgbe_hw
*hw
, u32 index
, u8
*addr
, u32 vmdq
,
74 s32
ixgbe_clear_rar_generic(struct ixgbe_hw
*hw
, u32 index
);
75 s32
ixgbe_init_rx_addrs_generic(struct ixgbe_hw
*hw
);
76 s32
ixgbe_update_mc_addr_list_generic(struct ixgbe_hw
*hw
,
77 struct net_device
*netdev
);
78 s32
ixgbe_enable_mc_generic(struct ixgbe_hw
*hw
);
79 s32
ixgbe_disable_mc_generic(struct ixgbe_hw
*hw
);
80 s32
ixgbe_disable_rx_buff_generic(struct ixgbe_hw
*hw
);
81 s32
ixgbe_enable_rx_buff_generic(struct ixgbe_hw
*hw
);
82 s32
ixgbe_enable_rx_dma_generic(struct ixgbe_hw
*hw
, u32 regval
);
83 s32
ixgbe_fc_enable_generic(struct ixgbe_hw
*hw
);
84 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw
*hw
);
85 void ixgbe_fc_autoneg(struct ixgbe_hw
*hw
);
87 s32
ixgbe_acquire_swfw_sync(struct ixgbe_hw
*hw
, u32 mask
);
88 void ixgbe_release_swfw_sync(struct ixgbe_hw
*hw
, u32 mask
);
89 s32
ixgbe_get_san_mac_addr_generic(struct ixgbe_hw
*hw
, u8
*san_mac_addr
);
90 s32
ixgbe_set_vmdq_generic(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
);
91 s32
ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw
*hw
, u32 vmdq
);
92 s32
ixgbe_clear_vmdq_generic(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
);
93 s32
ixgbe_init_uta_tables_generic(struct ixgbe_hw
*hw
);
94 s32
ixgbe_set_vfta_generic(struct ixgbe_hw
*hw
, u32 vlan
,
95 u32 vind
, bool vlan_on
);
96 s32
ixgbe_clear_vfta_generic(struct ixgbe_hw
*hw
);
97 s32
ixgbe_check_mac_link_generic(struct ixgbe_hw
*hw
,
98 ixgbe_link_speed
*speed
,
99 bool *link_up
, bool link_up_wait_to_complete
);
100 s32
ixgbe_get_wwn_prefix_generic(struct ixgbe_hw
*hw
, u16
*wwnn_prefix
,
103 s32
prot_autoc_read_generic(struct ixgbe_hw
*hw
, bool *, u32
*reg_val
);
104 s32
prot_autoc_write_generic(struct ixgbe_hw
*hw
, u32 reg_val
, bool locked
);
106 s32
ixgbe_blink_led_start_generic(struct ixgbe_hw
*hw
, u32 index
);
107 s32
ixgbe_blink_led_stop_generic(struct ixgbe_hw
*hw
, u32 index
);
108 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw
*hw
, bool enable
, int pf
);
109 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw
*hw
, bool enable
, int vf
);
110 s32
ixgbe_get_device_caps_generic(struct ixgbe_hw
*hw
, u16
*device_caps
);
111 s32
ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw
*hw
, u8 maj
, u8 min
,
113 s32
ixgbe_host_interface_command(struct ixgbe_hw
*hw
, u32
*buffer
,
114 u32 length
, u32 timeout
, bool return_data
);
115 void ixgbe_clear_tx_pending(struct ixgbe_hw
*hw
);
116 bool ixgbe_mng_present(struct ixgbe_hw
*hw
);
117 bool ixgbe_mng_enabled(struct ixgbe_hw
*hw
);
119 void ixgbe_set_rxpba_generic(struct ixgbe_hw
*hw
, int num_pb
,
120 u32 headroom
, int strategy
);
122 extern const u32 ixgbe_mvals_8259X
[IXGBE_MVALS_IDX_LIMIT
];
124 #define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8
125 #define IXGBE_EMC_INTERNAL_DATA 0x00
126 #define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20
127 #define IXGBE_EMC_DIODE1_DATA 0x01
128 #define IXGBE_EMC_DIODE1_THERM_LIMIT 0x19
129 #define IXGBE_EMC_DIODE2_DATA 0x23
130 #define IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A
131 #define IXGBE_EMC_DIODE3_DATA 0x2A
132 #define IXGBE_EMC_DIODE3_THERM_LIMIT 0x30
134 s32
ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw
*hw
);
135 s32
ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw
*hw
);
136 void ixgbe_disable_rx_generic(struct ixgbe_hw
*hw
);
137 void ixgbe_enable_rx_generic(struct ixgbe_hw
*hw
);
138 s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
139 ixgbe_link_speed speed
,
140 bool autoneg_wait_to_complete
);
141 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw
*hw
,
142 ixgbe_link_speed speed
);
144 #define IXGBE_FAILED_READ_REG 0xffffffffU
145 #define IXGBE_FAILED_READ_CFG_DWORD 0xffffffffU
146 #define IXGBE_FAILED_READ_CFG_WORD 0xffffU
148 u16
ixgbe_read_pci_cfg_word(struct ixgbe_hw
*hw
, u32 reg
);
149 void ixgbe_write_pci_cfg_word(struct ixgbe_hw
*hw
, u32 reg
, u16 value
);
151 static inline bool ixgbe_removed(void __iomem
*addr
)
153 return unlikely(!addr
);
156 static inline void ixgbe_write_reg(struct ixgbe_hw
*hw
, u32 reg
, u32 value
)
158 u8 __iomem
*reg_addr
= ACCESS_ONCE(hw
->hw_addr
);
160 if (ixgbe_removed(reg_addr
))
162 writel(value
, reg_addr
+ reg
);
164 #define IXGBE_WRITE_REG(a, reg, value) ixgbe_write_reg((a), (reg), (value))
167 #define writeq writeq
168 static inline void writeq(u64 val
, void __iomem
*addr
)
170 writel((u32
)val
, addr
);
171 writel((u32
)(val
>> 32), addr
+ 4);
175 static inline void ixgbe_write_reg64(struct ixgbe_hw
*hw
, u32 reg
, u64 value
)
177 u8 __iomem
*reg_addr
= ACCESS_ONCE(hw
->hw_addr
);
179 if (ixgbe_removed(reg_addr
))
181 writeq(value
, reg_addr
+ reg
);
183 #define IXGBE_WRITE_REG64(a, reg, value) ixgbe_write_reg64((a), (reg), (value))
185 u32
ixgbe_read_reg(struct ixgbe_hw
*hw
, u32 reg
);
186 #define IXGBE_READ_REG(a, reg) ixgbe_read_reg((a), (reg))
188 #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) \
189 ixgbe_write_reg((a), (reg) + ((offset) << 2), (value))
191 #define IXGBE_READ_REG_ARRAY(a, reg, offset) \
192 ixgbe_read_reg((a), (reg) + ((offset) << 2))
194 #define IXGBE_WRITE_FLUSH(a) ixgbe_read_reg((a), IXGBE_STATUS)
196 #define ixgbe_hw_to_netdev(hw) (((struct ixgbe_adapter *)(hw)->back)->netdev)
198 #define hw_dbg(hw, format, arg...) \
199 netdev_dbg(ixgbe_hw_to_netdev(hw), format, ## arg)
200 #define hw_err(hw, format, arg...) \
201 netdev_err(ixgbe_hw_to_netdev(hw), format, ## arg)
202 #define e_dev_info(format, arg...) \
203 dev_info(&adapter->pdev->dev, format, ## arg)
204 #define e_dev_warn(format, arg...) \
205 dev_warn(&adapter->pdev->dev, format, ## arg)
206 #define e_dev_err(format, arg...) \
207 dev_err(&adapter->pdev->dev, format, ## arg)
208 #define e_dev_notice(format, arg...) \
209 dev_notice(&adapter->pdev->dev, format, ## arg)
210 #define e_info(msglvl, format, arg...) \
211 netif_info(adapter, msglvl, adapter->netdev, format, ## arg)
212 #define e_err(msglvl, format, arg...) \
213 netif_err(adapter, msglvl, adapter->netdev, format, ## arg)
214 #define e_warn(msglvl, format, arg...) \
215 netif_warn(adapter, msglvl, adapter->netdev, format, ## arg)
216 #define e_crit(msglvl, format, arg...) \
217 netif_crit(adapter, msglvl, adapter->netdev, format, ## arg)
218 #endif /* IXGBE_COMMON */
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