drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #include "ixgbe.h"
  30 #include "ixgbe_type.h"
  31 #include "ixgbe_dcb.h"
  32 #include "ixgbe_dcb_82598.h"
  33
  34 /**
  35  * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
  36  * @hw: pointer to hardware structure
  37  * @dcb_config: pointer to ixgbe_dcb_config structure
  38  *
  39  * Configure Rx Data Arbiter and credits for each traffic class.
  40  */
  41 s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
  42                                         u16 *refill,
  43                                         u16 *max,
  44                                         u8 *prio_type)
  45 {
  46         u32    reg           = 0;
  47         u32    credit_refill = 0;
  48         u32    credit_max    = 0;
  49         u8     i             = 0;
  50
  51         reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
  52         IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
  53
  54         reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
  55         /* Enable Arbiter */
  56         reg &= ~IXGBE_RMCS_ARBDIS;
  57         /* Enable Receive Recycle within the BWG */
  58         reg |= IXGBE_RMCS_RRM;
  59         /* Enable Deficit Fixed Priority arbitration*/
  60         reg |= IXGBE_RMCS_DFP;
  61
  62         IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
  63
  64         /* Configure traffic class credits and priority */
  65         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
  66                 credit_refill = refill[i];
  67                 credit_max    = max[i];
  68
  69                 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
  70
  71                 if (prio_type[i] == prio_link)
  72                         reg |= IXGBE_RT2CR_LSP;
  73
  74                 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
  75         }
  76
  77         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
  78         reg |= IXGBE_RDRXCTL_RDMTS_1_2;
  79         reg |= IXGBE_RDRXCTL_MPBEN;
  80         reg |= IXGBE_RDRXCTL_MCEN;
  81         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
  82
  83         reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
  84         /* Make sure there is enough descriptors before arbitration */
  85         reg &= ~IXGBE_RXCTRL_DMBYPS;
  86         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);
  87
  88         return 0;
  89 }
  90
  91 /**
  92  * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
  93  * @hw: pointer to hardware structure
  94  * @dcb_config: pointer to ixgbe_dcb_config structure
  95  *
  96  * Configure Tx Descriptor Arbiter and credits for each traffic class.
  97  */
  98 s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
  99                                                 u16 *refill,
 100                                                 u16 *max,
 101                                                 u8 *bwg_id,
 102                                                 u8 *prio_type)
 103 {
 104         u32    reg, max_credits;
 105         u8     i;
 106
 107         reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
 108
 109         /* Enable arbiter */
 110         reg &= ~IXGBE_DPMCS_ARBDIS;
 111         reg |= IXGBE_DPMCS_TSOEF;
 112
 113         /* Configure Max TSO packet size 34KB including payload and headers */
 114         reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
 115
 116         IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
 117
 118         /* Configure traffic class credits and priority */
 119         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
 120                 max_credits = max[i];
 121                 reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
 122                 reg |= refill[i];
 123                 reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
 124
 125                 if (prio_type[i] == prio_group)
 126                         reg |= IXGBE_TDTQ2TCCR_GSP;
 127
 128                 if (prio_type[i] == prio_link)
 129                         reg |= IXGBE_TDTQ2TCCR_LSP;
 130
 131                 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
 132         }
 133
 134         return 0;
 135 }
 136
 137 /**
 138  * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
 139  * @hw: pointer to hardware structure
 140  * @dcb_config: pointer to ixgbe_dcb_config structure
 141  *
 142  * Configure Tx Data Arbiter and credits for each traffic class.
 143  */
 144 s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
 145                                                 u16 *refill,
 146                                                 u16 *max,
 147                                                 u8 *bwg_id,
 148                                                 u8 *prio_type)
 149 {
 150         u32 reg;
 151         u8 i;
 152
 153         reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
 154         /* Enable Data Plane Arbiter */
 155         reg &= ~IXGBE_PDPMCS_ARBDIS;
 156         /* Enable DFP and Transmit Recycle Mode */
 157         reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);
 158
 159         IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
 160
 161         /* Configure traffic class credits and priority */
 162         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
 163                 reg = refill[i];
 164                 reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
 165                 reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
 166
 167                 if (prio_type[i] == prio_group)
 168                         reg |= IXGBE_TDPT2TCCR_GSP;
 169
 170                 if (prio_type[i] == prio_link)
 171                         reg |= IXGBE_TDPT2TCCR_LSP;
 172
 173                 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
 174         }
 175
 176         /* Enable Tx packet buffer division */
 177         reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
 178         reg |= IXGBE_DTXCTL_ENDBUBD;
 179         IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
 180
 181         return 0;
 182 }
 183
 184 /**
 185  * ixgbe_dcb_config_pfc_82598 - Config priority flow control
 186  * @hw: pointer to hardware structure
 187  * @dcb_config: pointer to ixgbe_dcb_config structure
 188  *
 189  * Configure Priority Flow Control for each traffic class.
 190  */
 191 s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
 192 {
 193         u32 fcrtl, reg;
 194         u8  i;
 195
 196         /* Enable Transmit Priority Flow Control */
 197         reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
 198         reg &= ~IXGBE_RMCS_TFCE_802_3X;
 199         reg |= IXGBE_RMCS_TFCE_PRIORITY;
 200         IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
 201
 202         /* Enable Receive Priority Flow Control */
 203         reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
 204         reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE);
 205
 206         if (pfc_en)
 207                 reg |= IXGBE_FCTRL_RPFCE;
 208
 209         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
 210
 211         fcrtl = (hw->fc.low_water << 10) | IXGBE_FCRTL_XONE;
 212         /* Configure PFC Tx thresholds per TC */
 213         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
 214                 if (!(pfc_en & (1 << i))) {
 215                         IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
 216                         IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
 217                         continue;
 218                 }
 219
 220                 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
 221                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
 222                 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
 223         }
 224
 225         /* Configure pause time */
 226         reg = hw->fc.pause_time * 0x00010001;
 227         for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
 228                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
 229
 230         /* Configure flow control refresh threshold value */
 231         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
 232
 233
 234         return 0;
 235 }
 236
 237 /**
 238  * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics
 239  * @hw: pointer to hardware structure
 240  *
 241  * Configure queue statistics registers, all queues belonging to same traffic
 242  * class uses a single set of queue statistics counters.
 243  */
 244 static s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
 245 {
 246         u32 reg = 0;
 247         u8  i   = 0;
 248         u8  j   = 0;
 249
 250         /* Receive Queues stats setting -  8 queues per statistics reg */
 251         for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {
 252                 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
 253                 reg |= ((0x1010101) * j);
 254                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
 255                 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
 256                 reg |= ((0x1010101) * j);
 257                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
 258         }
 259         /* Transmit Queues stats setting -  4 queues per statistics reg */
 260         for (i = 0; i < 8; i++) {
 261                 reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
 262                 reg |= ((0x1010101) * i);
 263                 IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);
 264         }
 265
 266         return 0;
 267 }
 268
 269 /**
 270  * ixgbe_dcb_hw_config_82598 - Config and enable DCB
 271  * @hw: pointer to hardware structure
 272  * @dcb_config: pointer to ixgbe_dcb_config structure
 273  *
 274  * Configure dcb settings and enable dcb mode.
 275  */
 276 s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
 277                               u16 *max, u8 *bwg_id, u8 *prio_type)
 278 {
 279         ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, prio_type);
 280         ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
 281                                                bwg_id, prio_type);
 282         ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
 283                                                bwg_id, prio_type);
 284         ixgbe_dcb_config_pfc_82598(hw, pfc_en);
 285         ixgbe_dcb_config_tc_stats_82598(hw);
 286
 287         return 0;
 288 }