drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include "ixgbe.h"
  29 #include "ixgbe_sriov.h"
  30
  31 /**
  32  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
  33  * @adapter: board private structure to initialize
  34  *
  35  * Cache the descriptor ring offsets for RSS to the assigned rings.
  36  *
  37  **/
  38 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
  39 {
  40         int i;
  41
  42         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
  43                 return false;
  44
  45         for (i = 0; i < adapter->num_rx_queues; i++)
  46                 adapter->rx_ring[i]->reg_idx = i;
  47         for (i = 0; i < adapter->num_tx_queues; i++)
  48                 adapter->tx_ring[i]->reg_idx = i;
  49
  50         return true;
  51 }
  52 #ifdef CONFIG_IXGBE_DCB
  53
  54 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
  55 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
  56                                     unsigned int *tx, unsigned int *rx)
  57 {
  58         struct net_device *dev = adapter->netdev;
  59         struct ixgbe_hw *hw = &adapter->hw;
  60         u8 num_tcs = netdev_get_num_tc(dev);
  61
  62         *tx = 0;
  63         *rx = 0;
  64
  65         switch (hw->mac.type) {
  66         case ixgbe_mac_82598EB:
  67                 *tx = tc << 2;
  68                 *rx = tc << 3;
  69                 break;
  70         case ixgbe_mac_82599EB:
  71         case ixgbe_mac_X540:
  72                 if (num_tcs > 4) {
  73                         if (tc < 3) {
  74                                 *tx = tc << 5;
  75                                 *rx = tc << 4;
  76                         } else if (tc <  5) {
  77                                 *tx = ((tc + 2) << 4);
  78                                 *rx = tc << 4;
  79                         } else if (tc < num_tcs) {
  80                                 *tx = ((tc + 8) << 3);
  81                                 *rx = tc << 4;
  82                         }
  83                 } else {
  84                         *rx =  tc << 5;
  85                         switch (tc) {
  86                         case 0:
  87                                 *tx =  0;
  88                                 break;
  89                         case 1:
  90                                 *tx = 64;
  91                                 break;
  92                         case 2:
  93                                 *tx = 96;
  94                                 break;
  95                         case 3:
  96                                 *tx = 112;
  97                                 break;
  98                         default:
  99                                 break;
 100                         }
 101                 }
 102                 break;
 103         default:
 104                 break;
 105         }
 106 }
 107
 108 /**
 109  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
 110  * @adapter: board private structure to initialize
 111  *
 112  * Cache the descriptor ring offsets for DCB to the assigned rings.
 113  *
 114  **/
 115 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
 116 {
 117         struct net_device *dev = adapter->netdev;
 118         int i, j, k;
 119         u8 num_tcs = netdev_get_num_tc(dev);
 120
 121         if (!num_tcs)
 122                 return false;
 123
 124         for (i = 0, k = 0; i < num_tcs; i++) {
 125                 unsigned int tx_s, rx_s;
 126                 u16 count = dev->tc_to_txq[i].count;
 127
 128                 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
 129                 for (j = 0; j < count; j++, k++) {
 130                         adapter->tx_ring[k]->reg_idx = tx_s + j;
 131                         adapter->rx_ring[k]->reg_idx = rx_s + j;
 132                         adapter->tx_ring[k]->dcb_tc = i;
 133                         adapter->rx_ring[k]->dcb_tc = i;
 134                 }
 135         }
 136
 137         return true;
 138 }
 139 #endif
 140
 141 /**
 142  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
 143  * @adapter: board private structure to initialize
 144  *
 145  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
 146  *
 147  **/
 148 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
 149 {
 150         int i;
 151         bool ret = false;
 152
 153         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
 154             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
 155                 for (i = 0; i < adapter->num_rx_queues; i++)
 156                         adapter->rx_ring[i]->reg_idx = i;
 157                 for (i = 0; i < adapter->num_tx_queues; i++)
 158                         adapter->tx_ring[i]->reg_idx = i;
 159                 ret = true;
 160         }
 161
 162         return ret;
 163 }
 164
 165 #ifdef IXGBE_FCOE
 166 /**
 167  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
 168  * @adapter: board private structure to initialize
 169  *
 170  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
 171  *
 172  */
 173 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
 174 {
 175         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
 176         int i;
 177         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
 178
 179         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
 180                 return false;
 181
 182         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
 183                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
 184                         ixgbe_cache_ring_fdir(adapter);
 185                 else
 186                         ixgbe_cache_ring_rss(adapter);
 187
 188                 fcoe_rx_i = f->mask;
 189                 fcoe_tx_i = f->mask;
 190         }
 191         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
 192                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
 193                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
 194         }
 195         return true;
 196 }
 197
 198 #endif /* IXGBE_FCOE */
 199 /**
 200  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
 201  * @adapter: board private structure to initialize
 202  *
 203  * SR-IOV doesn't use any descriptor rings but changes the default if
 204  * no other mapping is used.
 205  *
 206  */
 207 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
 208 {
 209         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
 210         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
 211         if (adapter->num_vfs)
 212                 return true;
 213         else
 214                 return false;
 215 }
 216
 217 /**
 218  * ixgbe_cache_ring_register - Descriptor ring to register mapping
 219  * @adapter: board private structure to initialize
 220  *
 221  * Once we know the feature-set enabled for the device, we'll cache
 222  * the register offset the descriptor ring is assigned to.
 223  *
 224  * Note, the order the various feature calls is important.  It must start with
 225  * the "most" features enabled at the same time, then trickle down to the
 226  * least amount of features turned on at once.
 227  **/
 228 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
 229 {
 230         /* start with default case */
 231         adapter->rx_ring[0]->reg_idx = 0;
 232         adapter->tx_ring[0]->reg_idx = 0;
 233
 234         if (ixgbe_cache_ring_sriov(adapter))
 235                 return;
 236
 237 #ifdef CONFIG_IXGBE_DCB
 238         if (ixgbe_cache_ring_dcb(adapter))
 239                 return;
 240 #endif
 241
 242 #ifdef IXGBE_FCOE
 243         if (ixgbe_cache_ring_fcoe(adapter))
 244                 return;
 245 #endif /* IXGBE_FCOE */
 246
 247         if (ixgbe_cache_ring_fdir(adapter))
 248                 return;
 249
 250         if (ixgbe_cache_ring_rss(adapter))
 251                 return;
 252 }
 253
 254 /**
 255  * ixgbe_set_sriov_queues: Allocate queues for IOV use
 256  * @adapter: board private structure to initialize
 257  *
 258  * IOV doesn't actually use anything, so just NAK the
 259  * request for now and let the other queue routines
 260  * figure out what to do.
 261  */
 262 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
 263 {
 264         return false;
 265 }
 266
 267 /**
 268  * ixgbe_set_rss_queues: Allocate queues for RSS
 269  * @adapter: board private structure to initialize
 270  *
 271  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
 272  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
 273  *
 274  **/
 275 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
 276 {
 277         bool ret = false;
 278         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
 279
 280         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
 281                 f->mask = 0xF;
 282                 adapter->num_rx_queues = f->indices;
 283                 adapter->num_tx_queues = f->indices;
 284                 ret = true;
 285         }
 286
 287         return ret;
 288 }
 289
 290 /**
 291  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
 292  * @adapter: board private structure to initialize
 293  *
 294  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
 295  * to the original CPU that initiated the Tx session.  This runs in addition
 296  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
 297  * Rx load across CPUs using RSS.
 298  *
 299  **/
 300 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
 301 {
 302         bool ret = false;
 303         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
 304
 305         f_fdir->indices = min_t(int, num_online_cpus(), f_fdir->indices);
 306         f_fdir->mask = 0;
 307
 308         /*
 309          * Use RSS in addition to Flow Director to ensure the best
 310          * distribution of flows across cores, even when an FDIR flow
 311          * isn't matched.
 312          */
 313         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
 314             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
 315                 adapter->num_tx_queues = f_fdir->indices;
 316                 adapter->num_rx_queues = f_fdir->indices;
 317                 ret = true;
 318         } else {
 319                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
 320         }
 321         return ret;
 322 }
 323
 324 #ifdef IXGBE_FCOE
 325 /**
 326  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
 327  * @adapter: board private structure to initialize
 328  *
 329  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
 330  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
 331  * rx queues out of the max number of rx queues, instead, it is used as the
 332  * index of the first rx queue used by FCoE.
 333  *
 334  **/
 335 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
 336 {
 337         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
 338
 339         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
 340                 return false;
 341
 342         f->indices = min_t(int, num_online_cpus(), f->indices);
 343
 344         adapter->num_rx_queues = 1;
 345         adapter->num_tx_queues = 1;
 346
 347         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
 348                 e_info(probe, "FCoE enabled with RSS\n");
 349                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
 350                         ixgbe_set_fdir_queues(adapter);
 351                 else
 352                         ixgbe_set_rss_queues(adapter);
 353         }
 354
 355         /* adding FCoE rx rings to the end */
 356         f->mask = adapter->num_rx_queues;
 357         adapter->num_rx_queues += f->indices;
 358         adapter->num_tx_queues += f->indices;
 359
 360         return true;
 361 }
 362 #endif /* IXGBE_FCOE */
 363
 364 /* Artificial max queue cap per traffic class in DCB mode */
 365 #define DCB_QUEUE_CAP 8
 366
 367 #ifdef CONFIG_IXGBE_DCB
 368 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
 369 {
 370         int per_tc_q, q, i, offset = 0;
 371         struct net_device *dev = adapter->netdev;
 372         int tcs = netdev_get_num_tc(dev);
 373
 374         if (!tcs)
 375                 return false;
 376
 377         /* Map queue offset and counts onto allocated tx queues */
 378         per_tc_q = min_t(unsigned int, dev->num_tx_queues / tcs, DCB_QUEUE_CAP);
 379         q = min_t(int, num_online_cpus(), per_tc_q);
 380
 381         for (i = 0; i < tcs; i++) {
 382                 netdev_set_tc_queue(dev, i, q, offset);
 383                 offset += q;
 384         }
 385
 386         adapter->num_tx_queues = q * tcs;
 387         adapter->num_rx_queues = q * tcs;
 388
 389 #ifdef IXGBE_FCOE
 390         /* FCoE enabled queues require special configuration indexed
 391          * by feature specific indices and mask. Here we map FCoE
 392          * indices onto the DCB queue pairs allowing FCoE to own
 393          * configuration later.
 394          */
 395         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 396                 u8 prio_tc[MAX_USER_PRIORITY] = {0};
 397                 int tc;
 398                 struct ixgbe_ring_feature *f =
 399                                         &adapter->ring_feature[RING_F_FCOE];
 400
 401                 ixgbe_dcb_unpack_map(&adapter->dcb_cfg, DCB_TX_CONFIG, prio_tc);
 402                 tc = prio_tc[adapter->fcoe.up];
 403                 f->indices = dev->tc_to_txq[tc].count;
 404                 f->mask = dev->tc_to_txq[tc].offset;
 405         }
 406 #endif
 407
 408         return true;
 409 }
 410 #endif
 411
 412 /**
 413  * ixgbe_set_num_queues: Allocate queues for device, feature dependent
 414  * @adapter: board private structure to initialize
 415  *
 416  * This is the top level queue allocation routine.  The order here is very
 417  * important, starting with the "most" number of features turned on at once,
 418  * and ending with the smallest set of features.  This way large combinations
 419  * can be allocated if they're turned on, and smaller combinations are the
 420  * fallthrough conditions.
 421  *
 422  **/
 423 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
 424 {
 425         /* Start with base case */
 426         adapter->num_rx_queues = 1;
 427         adapter->num_tx_queues = 1;
 428         adapter->num_rx_pools = adapter->num_rx_queues;
 429         adapter->num_rx_queues_per_pool = 1;
 430
 431         if (ixgbe_set_sriov_queues(adapter))
 432                 goto done;
 433
 434 #ifdef CONFIG_IXGBE_DCB
 435         if (ixgbe_set_dcb_queues(adapter))
 436                 goto done;
 437
 438 #endif
 439 #ifdef IXGBE_FCOE
 440         if (ixgbe_set_fcoe_queues(adapter))
 441                 goto done;
 442
 443 #endif /* IXGBE_FCOE */
 444         if (ixgbe_set_fdir_queues(adapter))
 445                 goto done;
 446
 447         if (ixgbe_set_rss_queues(adapter))
 448                 goto done;
 449
 450         /* fallback to base case */
 451         adapter->num_rx_queues = 1;
 452         adapter->num_tx_queues = 1;
 453
 454 done:
 455         if ((adapter->netdev->reg_state == NETREG_UNREGISTERED) ||
 456             (adapter->netdev->reg_state == NETREG_UNREGISTERING))
 457                 return 0;
 458
 459         /* Notify the stack of the (possibly) reduced queue counts. */
 460         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
 461         return netif_set_real_num_rx_queues(adapter->netdev,
 462                                             adapter->num_rx_queues);
 463 }
 464
 465 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
 466                                        int vectors)
 467 {
 468         int err, vector_threshold;
 469
 470         /* We'll want at least 2 (vector_threshold):
 471          * 1) TxQ[0] + RxQ[0] handler
 472          * 2) Other (Link Status Change, etc.)
 473          */
 474         vector_threshold = MIN_MSIX_COUNT;
 475
 476         /*
 477          * The more we get, the more we will assign to Tx/Rx Cleanup
 478          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
 479          * Right now, we simply care about how many we'll get; we'll
 480          * set them up later while requesting irq's.
 481          */
 482         while (vectors >= vector_threshold) {
 483                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
 484                                       vectors);
 485                 if (!err) /* Success in acquiring all requested vectors. */
 486                         break;
 487                 else if (err < 0)
 488                         vectors = 0; /* Nasty failure, quit now */
 489                 else /* err == number of vectors we should try again with */
 490                         vectors = err;
 491         }
 492
 493         if (vectors < vector_threshold) {
 494                 /* Can't allocate enough MSI-X interrupts?  Oh well.
 495                  * This just means we'll go with either a single MSI
 496                  * vector or fall back to legacy interrupts.
 497                  */
 498                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
 499                              "Unable to allocate MSI-X interrupts\n");
 500                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
 501                 kfree(adapter->msix_entries);
 502                 adapter->msix_entries = NULL;
 503         } else {
 504                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
 505                 /*
 506                  * Adjust for only the vectors we'll use, which is minimum
 507                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
 508                  * vectors we were allocated.
 509                  */
 510                 adapter->num_msix_vectors = min(vectors,
 511                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
 512         }
 513 }
 514
 515 static void ixgbe_add_ring(struct ixgbe_ring *ring,
 516                            struct ixgbe_ring_container *head)
 517 {
 518         ring->next = head->ring;
 519         head->ring = ring;
 520         head->count++;
 521 }
 522
 523 /**
 524  * ixgbe_alloc_q_vector - Allocate memory for a single interrupt vector
 525  * @adapter: board private structure to initialize
 526  * @v_idx: index of vector in adapter struct
 527  *
 528  * We allocate one q_vector.  If allocation fails we return -ENOMEM.
 529  **/
 530 static int ixgbe_alloc_q_vector(struct ixgbe_adapter *adapter, int v_idx,
 531                                 int txr_count, int txr_idx,
 532                                 int rxr_count, int rxr_idx)
 533 {
 534         struct ixgbe_q_vector *q_vector;
 535         struct ixgbe_ring *ring;
 536         int node = -1;
 537         int cpu = -1;
 538         int ring_count, size;
 539
 540         ring_count = txr_count + rxr_count;
 541         size = sizeof(struct ixgbe_q_vector) +
 542                (sizeof(struct ixgbe_ring) * ring_count);
 543
 544         /* customize cpu for Flow Director mapping */
 545         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
 546                 if (cpu_online(v_idx)) {
 547                         cpu = v_idx;
 548                         node = cpu_to_node(cpu);
 549                 }
 550         }
 551
 552         /* allocate q_vector and rings */
 553         q_vector = kzalloc_node(size, GFP_KERNEL, node);
 554         if (!q_vector)
 555                 q_vector = kzalloc(size, GFP_KERNEL);
 556         if (!q_vector)
 557                 return -ENOMEM;
 558
 559         /* setup affinity mask and node */
 560         if (cpu != -1)
 561                 cpumask_set_cpu(cpu, &q_vector->affinity_mask);
 562         else
 563                 cpumask_copy(&q_vector->affinity_mask, cpu_online_mask);
 564         q_vector->numa_node = node;
 565
 566         /* initialize NAPI */
 567         netif_napi_add(adapter->netdev, &q_vector->napi,
 568                        ixgbe_poll, 64);
 569
 570         /* tie q_vector and adapter together */
 571         adapter->q_vector[v_idx] = q_vector;
 572         q_vector->adapter = adapter;
 573         q_vector->v_idx = v_idx;
 574
 575         /* initialize work limits */
 576         q_vector->tx.work_limit = adapter->tx_work_limit;
 577
 578         /* initialize pointer to rings */
 579         ring = q_vector->ring;
 580
 581         while (txr_count) {
 582                 /* assign generic ring traits */
 583                 ring->dev = &adapter->pdev->dev;
 584                 ring->netdev = adapter->netdev;
 585
 586                 /* configure backlink on ring */
 587                 ring->q_vector = q_vector;
 588
 589                 /* update q_vector Tx values */
 590                 ixgbe_add_ring(ring, &q_vector->tx);
 591
 592                 /* apply Tx specific ring traits */
 593                 ring->count = adapter->tx_ring_count;
 594                 ring->queue_index = txr_idx;
 595
 596                 /* assign ring to adapter */
 597                 adapter->tx_ring[txr_idx] = ring;
 598
 599                 /* update count and index */
 600                 txr_count--;
 601                 txr_idx++;
 602
 603                 /* push pointer to next ring */
 604                 ring++;
 605         }
 606
 607         while (rxr_count) {
 608                 /* assign generic ring traits */
 609                 ring->dev = &adapter->pdev->dev;
 610                 ring->netdev = adapter->netdev;
 611
 612                 /* configure backlink on ring */
 613                 ring->q_vector = q_vector;
 614
 615                 /* update q_vector Rx values */
 616                 ixgbe_add_ring(ring, &q_vector->rx);
 617
 618                 /*
 619                  * 82599 errata, UDP frames with a 0 checksum
 620                  * can be marked as checksum errors.
 621                  */
 622                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 623                         set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state);
 624
 625 #ifdef IXGBE_FCOE
 626                 if (adapter->netdev->features & NETIF_F_FCOE_MTU) {
 627                         struct ixgbe_ring_feature *f;
 628                         f = &adapter->ring_feature[RING_F_FCOE];
 629                         if ((rxr_idx >= f->mask) &&
 630                             (rxr_idx < f->mask + f->indices))
 631                                 set_bit(__IXGBE_RX_FCOE_BUFSZ, &ring->state);
 632                 }
 633
 634 #endif /* IXGBE_FCOE */
 635                 /* apply Rx specific ring traits */
 636                 ring->count = adapter->rx_ring_count;
 637                 ring->queue_index = rxr_idx;
 638
 639                 /* assign ring to adapter */
 640                 adapter->rx_ring[rxr_idx] = ring;
 641
 642                 /* update count and index */
 643                 rxr_count--;
 644                 rxr_idx++;
 645
 646                 /* push pointer to next ring */
 647                 ring++;
 648         }
 649
 650         return 0;
 651 }
 652
 653 /**
 654  * ixgbe_free_q_vector - Free memory allocated for specific interrupt vector
 655  * @adapter: board private structure to initialize
 656  * @v_idx: Index of vector to be freed
 657  *
 658  * This function frees the memory allocated to the q_vector.  In addition if
 659  * NAPI is enabled it will delete any references to the NAPI struct prior
 660  * to freeing the q_vector.
 661  **/
 662 static void ixgbe_free_q_vector(struct ixgbe_adapter *adapter, int v_idx)
 663 {
 664         struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
 665         struct ixgbe_ring *ring;
 666
 667         ixgbe_for_each_ring(ring, q_vector->tx)
 668                 adapter->tx_ring[ring->queue_index] = NULL;
 669
 670         ixgbe_for_each_ring(ring, q_vector->rx)
 671                 adapter->rx_ring[ring->queue_index] = NULL;
 672
 673         adapter->q_vector[v_idx] = NULL;
 674         netif_napi_del(&q_vector->napi);
 675
 676         /*
 677          * ixgbe_get_stats64() might access the rings on this vector,
 678          * we must wait a grace period before freeing it.
 679          */
 680         kfree_rcu(q_vector, rcu);
 681 }
 682
 683 /**
 684  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
 685  * @adapter: board private structure to initialize
 686  *
 687  * We allocate one q_vector per queue interrupt.  If allocation fails we
 688  * return -ENOMEM.
 689  **/
 690 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
 691 {
 692         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 693         int rxr_remaining = adapter->num_rx_queues;
 694         int txr_remaining = adapter->num_tx_queues;
 695         int rxr_idx = 0, txr_idx = 0, v_idx = 0;
 696         int err;
 697
 698         /* only one q_vector if MSI-X is disabled. */
 699         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
 700                 q_vectors = 1;
 701
 702         if (q_vectors >= (rxr_remaining + txr_remaining)) {
 703                 for (; rxr_remaining; v_idx++, q_vectors--) {
 704                         int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors);
 705                         err = ixgbe_alloc_q_vector(adapter, v_idx,
 706                                                    0, 0, rqpv, rxr_idx);
 707
 708                         if (err)
 709                                 goto err_out;
 710
 711                         /* update counts and index */
 712                         rxr_remaining -= rqpv;
 713                         rxr_idx += rqpv;
 714                 }
 715         }
 716
 717         for (; q_vectors; v_idx++, q_vectors--) {
 718                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors);
 719                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors);
 720                 err = ixgbe_alloc_q_vector(adapter, v_idx,
 721                                            tqpv, txr_idx,
 722                                            rqpv, rxr_idx);
 723
 724                 if (err)
 725                         goto err_out;
 726
 727                 /* update counts and index */
 728                 rxr_remaining -= rqpv;
 729                 rxr_idx += rqpv;
 730                 txr_remaining -= tqpv;
 731                 txr_idx += tqpv;
 732         }
 733
 734         return 0;
 735
 736 err_out:
 737         while (v_idx) {
 738                 v_idx--;
 739                 ixgbe_free_q_vector(adapter, v_idx);
 740         }
 741
 742         return -ENOMEM;
 743 }
 744
 745 /**
 746  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
 747  * @adapter: board private structure to initialize
 748  *
 749  * This function frees the memory allocated to the q_vectors.  In addition if
 750  * NAPI is enabled it will delete any references to the NAPI struct prior
 751  * to freeing the q_vector.
 752  **/
 753 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
 754 {
 755         int v_idx, q_vectors;
 756
 757         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
 758                 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 759         else
 760                 q_vectors = 1;
 761
 762         for (v_idx = 0; v_idx < q_vectors; v_idx++)
 763                 ixgbe_free_q_vector(adapter, v_idx);
 764 }
 765
 766 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
 767 {
 768         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
 769                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
 770                 pci_disable_msix(adapter->pdev);
 771                 kfree(adapter->msix_entries);
 772                 adapter->msix_entries = NULL;
 773         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
 774                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
 775                 pci_disable_msi(adapter->pdev);
 776         }
 777 }
 778
 779 /**
 780  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
 781  * @adapter: board private structure to initialize
 782  *
 783  * Attempt to configure the interrupts using the best available
 784  * capabilities of the hardware and the kernel.
 785  **/
 786 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
 787 {
 788         struct ixgbe_hw *hw = &adapter->hw;
 789         int err = 0;
 790         int vector, v_budget;
 791
 792         /*
 793          * It's easy to be greedy for MSI-X vectors, but it really
 794          * doesn't do us much good if we have a lot more vectors
 795          * than CPU's.  So let's be conservative and only ask for
 796          * (roughly) the same number of vectors as there are CPU's.
 797          * The default is to use pairs of vectors.
 798          */
 799         v_budget = max(adapter->num_rx_queues, adapter->num_tx_queues);
 800         v_budget = min_t(int, v_budget, num_online_cpus());
 801         v_budget += NON_Q_VECTORS;
 802
 803         /*
 804          * At the same time, hardware can only support a maximum of
 805          * hw.mac->max_msix_vectors vectors.  With features
 806          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
 807          * descriptor queues supported by our device.  Thus, we cap it off in
 808          * those rare cases where the cpu count also exceeds our vector limit.
 809          */
 810         v_budget = min_t(int, v_budget, hw->mac.max_msix_vectors);
 811
 812         /* A failure in MSI-X entry allocation isn't fatal, but it does
 813          * mean we disable MSI-X capabilities of the adapter. */
 814         adapter->msix_entries = kcalloc(v_budget,
 815                                         sizeof(struct msix_entry), GFP_KERNEL);
 816         if (adapter->msix_entries) {
 817                 for (vector = 0; vector < v_budget; vector++)
 818                         adapter->msix_entries[vector].entry = vector;
 819
 820                 ixgbe_acquire_msix_vectors(adapter, v_budget);
 821
 822                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
 823                         goto out;
 824         }
 825
 826         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
 827         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
 828         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
 829                 e_err(probe,
 830                       "ATR is not supported while multiple "
 831                       "queues are disabled.  Disabling Flow Director\n");
 832         }
 833         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
 834         adapter->atr_sample_rate = 0;
 835         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
 836                 ixgbe_disable_sriov(adapter);
 837
 838         err = ixgbe_set_num_queues(adapter);
 839         if (err)
 840                 return err;
 841
 842         err = pci_enable_msi(adapter->pdev);
 843         if (!err) {
 844                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
 845         } else {
 846                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
 847                              "Unable to allocate MSI interrupt, "
 848                              "falling back to legacy.  Error: %d\n", err);
 849                 /* reset err */
 850                 err = 0;
 851         }
 852
 853 out:
 854         return err;
 855 }
 856
 857 /**
 858  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
 859  * @adapter: board private structure to initialize
 860  *
 861  * We determine which interrupt scheme to use based on...
 862  * - Kernel support (MSI, MSI-X)
 863  *   - which can be user-defined (via MODULE_PARAM)
 864  * - Hardware queue count (num_*_queues)
 865  *   - defined by miscellaneous hardware support/features (RSS, etc.)
 866  **/
 867 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
 868 {
 869         int err;
 870
 871         /* Number of supported queues */
 872         err = ixgbe_set_num_queues(adapter);
 873         if (err)
 874                 return err;
 875
 876         err = ixgbe_set_interrupt_capability(adapter);
 877         if (err) {
 878                 e_dev_err("Unable to setup interrupt capabilities\n");
 879                 goto err_set_interrupt;
 880         }
 881
 882         err = ixgbe_alloc_q_vectors(adapter);
 883         if (err) {
 884                 e_dev_err("Unable to allocate memory for queue vectors\n");
 885                 goto err_alloc_q_vectors;
 886         }
 887
 888         ixgbe_cache_ring_register(adapter);
 889
 890         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
 891                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
 892                    adapter->num_rx_queues, adapter->num_tx_queues);
 893
 894         set_bit(__IXGBE_DOWN, &adapter->state);
 895
 896         return 0;
 897
 898 err_alloc_q_vectors:
 899         ixgbe_reset_interrupt_capability(adapter);
 900 err_set_interrupt:
 901         return err;
 902 }
 903
 904 /**
 905  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
 906  * @adapter: board private structure to clear interrupt scheme on
 907  *
 908  * We go through and clear interrupt specific resources and reset the structure
 909  * to pre-load conditions
 910  **/
 911 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
 912 {
 913         adapter->num_tx_queues = 0;
 914         adapter->num_rx_queues = 0;
 915
 916         ixgbe_free_q_vectors(adapter);
 917         ixgbe_reset_interrupt_capability(adapter);
 918 }
 919
 920 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
 921                        u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
 922 {
 923         struct ixgbe_adv_tx_context_desc *context_desc;
 924         u16 i = tx_ring->next_to_use;
 925
 926         context_desc = IXGBE_TX_CTXTDESC(tx_ring, i);
 927
 928         i++;
 929         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
 930
 931         /* set bits to identify this as an advanced context descriptor */
 932         type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
 933
 934         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
 935         context_desc->seqnum_seed       = cpu_to_le32(fcoe_sof_eof);
 936         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
 937         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
 938 }
 939