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net: vlan: rename NETIF_F_HW_VLAN_* feature flags to NETIF_F_HW_VLAN_CTAG_*
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/if_bridge.h>
48 #include <linux/prefetch.h>
49 #include <scsi/fc/fc_fcoe.h>
50
51 #include "ixgbe.h"
52 #include "ixgbe_common.h"
53 #include "ixgbe_dcb_82599.h"
54 #include "ixgbe_sriov.h"
55
56 char ixgbe_driver_name[] = "ixgbe";
57 static const char ixgbe_driver_string[] =
58 "Intel(R) 10 Gigabit PCI Express Network Driver";
59 #ifdef IXGBE_FCOE
60 char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
62 #else
63 static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
65 #endif
66 #define DRV_VERSION "3.13.10-k"
67 const char ixgbe_driver_version[] = DRV_VERSION;
68 static const char ixgbe_copyright[] =
69 "Copyright (c) 1999-2013 Intel Corporation.";
70
71 static const struct ixgbe_info *ixgbe_info_tbl[] = {
72 [board_82598] = &ixgbe_82598_info,
73 [board_82599] = &ixgbe_82599_info,
74 [board_X540] = &ixgbe_X540_info,
75 };
76
77 /* ixgbe_pci_tbl - PCI Device ID Table
78 *
79 * Wildcard entries (PCI_ANY_ID) should come last
80 * Last entry must be all 0s
81 *
82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
83 * Class, Class Mask, private data (not used) }
84 */
85 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
115 /* required last entry */
116 {0, }
117 };
118 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
119
120 #ifdef CONFIG_IXGBE_DCA
121 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
122 void *p);
123 static struct notifier_block dca_notifier = {
124 .notifier_call = ixgbe_notify_dca,
125 .next = NULL,
126 .priority = 0
127 };
128 #endif
129
130 #ifdef CONFIG_PCI_IOV
131 static unsigned int max_vfs;
132 module_param(max_vfs, uint, 0);
133 MODULE_PARM_DESC(max_vfs,
134 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
135 #endif /* CONFIG_PCI_IOV */
136
137 static unsigned int allow_unsupported_sfp;
138 module_param(allow_unsupported_sfp, uint, 0);
139 MODULE_PARM_DESC(allow_unsupported_sfp,
140 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
141
142 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
143 static int debug = -1;
144 module_param(debug, int, 0);
145 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
146
147 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
148 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
149 MODULE_LICENSE("GPL");
150 MODULE_VERSION(DRV_VERSION);
151
152 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
153 u32 reg, u16 *value)
154 {
155 int pos = 0;
156 struct pci_dev *parent_dev;
157 struct pci_bus *parent_bus;
158
159 parent_bus = adapter->pdev->bus->parent;
160 if (!parent_bus)
161 return -1;
162
163 parent_dev = parent_bus->self;
164 if (!parent_dev)
165 return -1;
166
167 pos = pci_find_capability(parent_dev, PCI_CAP_ID_EXP);
168 if (!pos)
169 return -1;
170
171 pci_read_config_word(parent_dev, pos + reg, value);
172 return 0;
173 }
174
175 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
176 {
177 struct ixgbe_hw *hw = &adapter->hw;
178 u16 link_status = 0;
179 int err;
180
181 hw->bus.type = ixgbe_bus_type_pci_express;
182
183 /* Get the negotiated link width and speed from PCI config space of the
184 * parent, as this device is behind a switch
185 */
186 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
187
188 /* assume caller will handle error case */
189 if (err)
190 return err;
191
192 hw->bus.width = ixgbe_convert_bus_width(link_status);
193 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
194
195 return 0;
196 }
197
198 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
199 {
200 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
201 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
202 schedule_work(&adapter->service_task);
203 }
204
205 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
206 {
207 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
208
209 /* flush memory to make sure state is correct before next watchdog */
210 smp_mb__before_clear_bit();
211 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
212 }
213
214 struct ixgbe_reg_info {
215 u32 ofs;
216 char *name;
217 };
218
219 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
220
221 /* General Registers */
222 {IXGBE_CTRL, "CTRL"},
223 {IXGBE_STATUS, "STATUS"},
224 {IXGBE_CTRL_EXT, "CTRL_EXT"},
225
226 /* Interrupt Registers */
227 {IXGBE_EICR, "EICR"},
228
229 /* RX Registers */
230 {IXGBE_SRRCTL(0), "SRRCTL"},
231 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
232 {IXGBE_RDLEN(0), "RDLEN"},
233 {IXGBE_RDH(0), "RDH"},
234 {IXGBE_RDT(0), "RDT"},
235 {IXGBE_RXDCTL(0), "RXDCTL"},
236 {IXGBE_RDBAL(0), "RDBAL"},
237 {IXGBE_RDBAH(0), "RDBAH"},
238
239 /* TX Registers */
240 {IXGBE_TDBAL(0), "TDBAL"},
241 {IXGBE_TDBAH(0), "TDBAH"},
242 {IXGBE_TDLEN(0), "TDLEN"},
243 {IXGBE_TDH(0), "TDH"},
244 {IXGBE_TDT(0), "TDT"},
245 {IXGBE_TXDCTL(0), "TXDCTL"},
246
247 /* List Terminator */
248 {}
249 };
250
251
252 /*
253 * ixgbe_regdump - register printout routine
254 */
255 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
256 {
257 int i = 0, j = 0;
258 char rname[16];
259 u32 regs[64];
260
261 switch (reginfo->ofs) {
262 case IXGBE_SRRCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
265 break;
266 case IXGBE_DCA_RXCTRL(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
269 break;
270 case IXGBE_RDLEN(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
273 break;
274 case IXGBE_RDH(0):
275 for (i = 0; i < 64; i++)
276 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
277 break;
278 case IXGBE_RDT(0):
279 for (i = 0; i < 64; i++)
280 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
281 break;
282 case IXGBE_RXDCTL(0):
283 for (i = 0; i < 64; i++)
284 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
285 break;
286 case IXGBE_RDBAL(0):
287 for (i = 0; i < 64; i++)
288 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
289 break;
290 case IXGBE_RDBAH(0):
291 for (i = 0; i < 64; i++)
292 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
293 break;
294 case IXGBE_TDBAL(0):
295 for (i = 0; i < 64; i++)
296 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
297 break;
298 case IXGBE_TDBAH(0):
299 for (i = 0; i < 64; i++)
300 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
301 break;
302 case IXGBE_TDLEN(0):
303 for (i = 0; i < 64; i++)
304 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
305 break;
306 case IXGBE_TDH(0):
307 for (i = 0; i < 64; i++)
308 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
309 break;
310 case IXGBE_TDT(0):
311 for (i = 0; i < 64; i++)
312 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
313 break;
314 case IXGBE_TXDCTL(0):
315 for (i = 0; i < 64; i++)
316 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
317 break;
318 default:
319 pr_info("%-15s %08x\n", reginfo->name,
320 IXGBE_READ_REG(hw, reginfo->ofs));
321 return;
322 }
323
324 for (i = 0; i < 8; i++) {
325 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
326 pr_err("%-15s", rname);
327 for (j = 0; j < 8; j++)
328 pr_cont(" %08x", regs[i*8+j]);
329 pr_cont("\n");
330 }
331
332 }
333
334 /*
335 * ixgbe_dump - Print registers, tx-rings and rx-rings
336 */
337 static void ixgbe_dump(struct ixgbe_adapter *adapter)
338 {
339 struct net_device *netdev = adapter->netdev;
340 struct ixgbe_hw *hw = &adapter->hw;
341 struct ixgbe_reg_info *reginfo;
342 int n = 0;
343 struct ixgbe_ring *tx_ring;
344 struct ixgbe_tx_buffer *tx_buffer;
345 union ixgbe_adv_tx_desc *tx_desc;
346 struct my_u0 { u64 a; u64 b; } *u0;
347 struct ixgbe_ring *rx_ring;
348 union ixgbe_adv_rx_desc *rx_desc;
349 struct ixgbe_rx_buffer *rx_buffer_info;
350 u32 staterr;
351 int i = 0;
352
353 if (!netif_msg_hw(adapter))
354 return;
355
356 /* Print netdevice Info */
357 if (netdev) {
358 dev_info(&adapter->pdev->dev, "Net device Info\n");
359 pr_info("Device Name state "
360 "trans_start last_rx\n");
361 pr_info("%-15s %016lX %016lX %016lX\n",
362 netdev->name,
363 netdev->state,
364 netdev->trans_start,
365 netdev->last_rx);
366 }
367
368 /* Print Registers */
369 dev_info(&adapter->pdev->dev, "Register Dump\n");
370 pr_info(" Register Name Value\n");
371 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
372 reginfo->name; reginfo++) {
373 ixgbe_regdump(hw, reginfo);
374 }
375
376 /* Print TX Ring Summary */
377 if (!netdev || !netif_running(netdev))
378 goto exit;
379
380 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
381 pr_info(" %s %s %s %s\n",
382 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
383 "leng", "ntw", "timestamp");
384 for (n = 0; n < adapter->num_tx_queues; n++) {
385 tx_ring = adapter->tx_ring[n];
386 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
387 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
388 n, tx_ring->next_to_use, tx_ring->next_to_clean,
389 (u64)dma_unmap_addr(tx_buffer, dma),
390 dma_unmap_len(tx_buffer, len),
391 tx_buffer->next_to_watch,
392 (u64)tx_buffer->time_stamp);
393 }
394
395 /* Print TX Rings */
396 if (!netif_msg_tx_done(adapter))
397 goto rx_ring_summary;
398
399 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
400
401 /* Transmit Descriptor Formats
402 *
403 * 82598 Advanced Transmit Descriptor
404 * +--------------------------------------------------------------+
405 * 0 | Buffer Address [63:0] |
406 * +--------------------------------------------------------------+
407 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
408 * +--------------------------------------------------------------+
409 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
410 *
411 * 82598 Advanced Transmit Descriptor (Write-Back Format)
412 * +--------------------------------------------------------------+
413 * 0 | RSV [63:0] |
414 * +--------------------------------------------------------------+
415 * 8 | RSV | STA | NXTSEQ |
416 * +--------------------------------------------------------------+
417 * 63 36 35 32 31 0
418 *
419 * 82599+ Advanced Transmit Descriptor
420 * +--------------------------------------------------------------+
421 * 0 | Buffer Address [63:0] |
422 * +--------------------------------------------------------------+
423 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
424 * +--------------------------------------------------------------+
425 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
426 *
427 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
428 * +--------------------------------------------------------------+
429 * 0 | RSV [63:0] |
430 * +--------------------------------------------------------------+
431 * 8 | RSV | STA | RSV |
432 * +--------------------------------------------------------------+
433 * 63 36 35 32 31 0
434 */
435
436 for (n = 0; n < adapter->num_tx_queues; n++) {
437 tx_ring = adapter->tx_ring[n];
438 pr_info("------------------------------------\n");
439 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
440 pr_info("------------------------------------\n");
441 pr_info("%s%s %s %s %s %s\n",
442 "T [desc] [address 63:0 ] ",
443 "[PlPOIdStDDt Ln] [bi->dma ] ",
444 "leng", "ntw", "timestamp", "bi->skb");
445
446 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
447 tx_desc = IXGBE_TX_DESC(tx_ring, i);
448 tx_buffer = &tx_ring->tx_buffer_info[i];
449 u0 = (struct my_u0 *)tx_desc;
450 if (dma_unmap_len(tx_buffer, len) > 0) {
451 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
452 i,
453 le64_to_cpu(u0->a),
454 le64_to_cpu(u0->b),
455 (u64)dma_unmap_addr(tx_buffer, dma),
456 dma_unmap_len(tx_buffer, len),
457 tx_buffer->next_to_watch,
458 (u64)tx_buffer->time_stamp,
459 tx_buffer->skb);
460 if (i == tx_ring->next_to_use &&
461 i == tx_ring->next_to_clean)
462 pr_cont(" NTC/U\n");
463 else if (i == tx_ring->next_to_use)
464 pr_cont(" NTU\n");
465 else if (i == tx_ring->next_to_clean)
466 pr_cont(" NTC\n");
467 else
468 pr_cont("\n");
469
470 if (netif_msg_pktdata(adapter) &&
471 tx_buffer->skb)
472 print_hex_dump(KERN_INFO, "",
473 DUMP_PREFIX_ADDRESS, 16, 1,
474 tx_buffer->skb->data,
475 dma_unmap_len(tx_buffer, len),
476 true);
477 }
478 }
479 }
480
481 /* Print RX Rings Summary */
482 rx_ring_summary:
483 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
484 pr_info("Queue [NTU] [NTC]\n");
485 for (n = 0; n < adapter->num_rx_queues; n++) {
486 rx_ring = adapter->rx_ring[n];
487 pr_info("%5d %5X %5X\n",
488 n, rx_ring->next_to_use, rx_ring->next_to_clean);
489 }
490
491 /* Print RX Rings */
492 if (!netif_msg_rx_status(adapter))
493 goto exit;
494
495 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
496
497 /* Receive Descriptor Formats
498 *
499 * 82598 Advanced Receive Descriptor (Read) Format
500 * 63 1 0
501 * +-----------------------------------------------------+
502 * 0 | Packet Buffer Address [63:1] |A0/NSE|
503 * +----------------------------------------------+------+
504 * 8 | Header Buffer Address [63:1] | DD |
505 * +-----------------------------------------------------+
506 *
507 *
508 * 82598 Advanced Receive Descriptor (Write-Back) Format
509 *
510 * 63 48 47 32 31 30 21 20 16 15 4 3 0
511 * +------------------------------------------------------+
512 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
513 * | Packet | IP | | | | Type | Type |
514 * | Checksum | Ident | | | | | |
515 * +------------------------------------------------------+
516 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
517 * +------------------------------------------------------+
518 * 63 48 47 32 31 20 19 0
519 *
520 * 82599+ Advanced Receive Descriptor (Read) Format
521 * 63 1 0
522 * +-----------------------------------------------------+
523 * 0 | Packet Buffer Address [63:1] |A0/NSE|
524 * +----------------------------------------------+------+
525 * 8 | Header Buffer Address [63:1] | DD |
526 * +-----------------------------------------------------+
527 *
528 *
529 * 82599+ Advanced Receive Descriptor (Write-Back) Format
530 *
531 * 63 48 47 32 31 30 21 20 17 16 4 3 0
532 * +------------------------------------------------------+
533 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
534 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
535 * |/ Flow Dir Flt ID | | | | | |
536 * +------------------------------------------------------+
537 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
538 * +------------------------------------------------------+
539 * 63 48 47 32 31 20 19 0
540 */
541
542 for (n = 0; n < adapter->num_rx_queues; n++) {
543 rx_ring = adapter->rx_ring[n];
544 pr_info("------------------------------------\n");
545 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
546 pr_info("------------------------------------\n");
547 pr_info("%s%s%s",
548 "R [desc] [ PktBuf A0] ",
549 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
550 "<-- Adv Rx Read format\n");
551 pr_info("%s%s%s",
552 "RWB[desc] [PcsmIpSHl PtRs] ",
553 "[vl er S cks ln] ---------------- [bi->skb ] ",
554 "<-- Adv Rx Write-Back format\n");
555
556 for (i = 0; i < rx_ring->count; i++) {
557 rx_buffer_info = &rx_ring->rx_buffer_info[i];
558 rx_desc = IXGBE_RX_DESC(rx_ring, i);
559 u0 = (struct my_u0 *)rx_desc;
560 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
561 if (staterr & IXGBE_RXD_STAT_DD) {
562 /* Descriptor Done */
563 pr_info("RWB[0x%03X] %016llX "
564 "%016llX ---------------- %p", i,
565 le64_to_cpu(u0->a),
566 le64_to_cpu(u0->b),
567 rx_buffer_info->skb);
568 } else {
569 pr_info("R [0x%03X] %016llX "
570 "%016llX %016llX %p", i,
571 le64_to_cpu(u0->a),
572 le64_to_cpu(u0->b),
573 (u64)rx_buffer_info->dma,
574 rx_buffer_info->skb);
575
576 if (netif_msg_pktdata(adapter) &&
577 rx_buffer_info->dma) {
578 print_hex_dump(KERN_INFO, "",
579 DUMP_PREFIX_ADDRESS, 16, 1,
580 page_address(rx_buffer_info->page) +
581 rx_buffer_info->page_offset,
582 ixgbe_rx_bufsz(rx_ring), true);
583 }
584 }
585
586 if (i == rx_ring->next_to_use)
587 pr_cont(" NTU\n");
588 else if (i == rx_ring->next_to_clean)
589 pr_cont(" NTC\n");
590 else
591 pr_cont("\n");
592
593 }
594 }
595
596 exit:
597 return;
598 }
599
600 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
601 {
602 u32 ctrl_ext;
603
604 /* Let firmware take over control of h/w */
605 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
606 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
607 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
608 }
609
610 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
611 {
612 u32 ctrl_ext;
613
614 /* Let firmware know the driver has taken over */
615 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
616 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
617 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
618 }
619
620 /**
621 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
622 * @adapter: pointer to adapter struct
623 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
624 * @queue: queue to map the corresponding interrupt to
625 * @msix_vector: the vector to map to the corresponding queue
626 *
627 */
628 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
629 u8 queue, u8 msix_vector)
630 {
631 u32 ivar, index;
632 struct ixgbe_hw *hw = &adapter->hw;
633 switch (hw->mac.type) {
634 case ixgbe_mac_82598EB:
635 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
636 if (direction == -1)
637 direction = 0;
638 index = (((direction * 64) + queue) >> 2) & 0x1F;
639 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
640 ivar &= ~(0xFF << (8 * (queue & 0x3)));
641 ivar |= (msix_vector << (8 * (queue & 0x3)));
642 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
643 break;
644 case ixgbe_mac_82599EB:
645 case ixgbe_mac_X540:
646 if (direction == -1) {
647 /* other causes */
648 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
649 index = ((queue & 1) * 8);
650 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
651 ivar &= ~(0xFF << index);
652 ivar |= (msix_vector << index);
653 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
654 break;
655 } else {
656 /* tx or rx causes */
657 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
658 index = ((16 * (queue & 1)) + (8 * direction));
659 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
660 ivar &= ~(0xFF << index);
661 ivar |= (msix_vector << index);
662 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
663 break;
664 }
665 default:
666 break;
667 }
668 }
669
670 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
671 u64 qmask)
672 {
673 u32 mask;
674
675 switch (adapter->hw.mac.type) {
676 case ixgbe_mac_82598EB:
677 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
678 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
679 break;
680 case ixgbe_mac_82599EB:
681 case ixgbe_mac_X540:
682 mask = (qmask & 0xFFFFFFFF);
683 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
684 mask = (qmask >> 32);
685 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
686 break;
687 default:
688 break;
689 }
690 }
691
692 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
693 struct ixgbe_tx_buffer *tx_buffer)
694 {
695 if (tx_buffer->skb) {
696 dev_kfree_skb_any(tx_buffer->skb);
697 if (dma_unmap_len(tx_buffer, len))
698 dma_unmap_single(ring->dev,
699 dma_unmap_addr(tx_buffer, dma),
700 dma_unmap_len(tx_buffer, len),
701 DMA_TO_DEVICE);
702 } else if (dma_unmap_len(tx_buffer, len)) {
703 dma_unmap_page(ring->dev,
704 dma_unmap_addr(tx_buffer, dma),
705 dma_unmap_len(tx_buffer, len),
706 DMA_TO_DEVICE);
707 }
708 tx_buffer->next_to_watch = NULL;
709 tx_buffer->skb = NULL;
710 dma_unmap_len_set(tx_buffer, len, 0);
711 /* tx_buffer must be completely set up in the transmit path */
712 }
713
714 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
715 {
716 struct ixgbe_hw *hw = &adapter->hw;
717 struct ixgbe_hw_stats *hwstats = &adapter->stats;
718 int i;
719 u32 data;
720
721 if ((hw->fc.current_mode != ixgbe_fc_full) &&
722 (hw->fc.current_mode != ixgbe_fc_rx_pause))
723 return;
724
725 switch (hw->mac.type) {
726 case ixgbe_mac_82598EB:
727 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
728 break;
729 default:
730 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
731 }
732 hwstats->lxoffrxc += data;
733
734 /* refill credits (no tx hang) if we received xoff */
735 if (!data)
736 return;
737
738 for (i = 0; i < adapter->num_tx_queues; i++)
739 clear_bit(__IXGBE_HANG_CHECK_ARMED,
740 &adapter->tx_ring[i]->state);
741 }
742
743 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
744 {
745 struct ixgbe_hw *hw = &adapter->hw;
746 struct ixgbe_hw_stats *hwstats = &adapter->stats;
747 u32 xoff[8] = {0};
748 u8 tc;
749 int i;
750 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
751
752 if (adapter->ixgbe_ieee_pfc)
753 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
754
755 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
756 ixgbe_update_xoff_rx_lfc(adapter);
757 return;
758 }
759
760 /* update stats for each tc, only valid with PFC enabled */
761 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
762 u32 pxoffrxc;
763
764 switch (hw->mac.type) {
765 case ixgbe_mac_82598EB:
766 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
767 break;
768 default:
769 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
770 }
771 hwstats->pxoffrxc[i] += pxoffrxc;
772 /* Get the TC for given UP */
773 tc = netdev_get_prio_tc_map(adapter->netdev, i);
774 xoff[tc] += pxoffrxc;
775 }
776
777 /* disarm tx queues that have received xoff frames */
778 for (i = 0; i < adapter->num_tx_queues; i++) {
779 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
780
781 tc = tx_ring->dcb_tc;
782 if (xoff[tc])
783 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
784 }
785 }
786
787 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
788 {
789 return ring->stats.packets;
790 }
791
792 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
793 {
794 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
795 struct ixgbe_hw *hw = &adapter->hw;
796
797 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
798 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
799
800 if (head != tail)
801 return (head < tail) ?
802 tail - head : (tail + ring->count - head);
803
804 return 0;
805 }
806
807 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
808 {
809 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
810 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
811 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
812 bool ret = false;
813
814 clear_check_for_tx_hang(tx_ring);
815
816 /*
817 * Check for a hung queue, but be thorough. This verifies
818 * that a transmit has been completed since the previous
819 * check AND there is at least one packet pending. The
820 * ARMED bit is set to indicate a potential hang. The
821 * bit is cleared if a pause frame is received to remove
822 * false hang detection due to PFC or 802.3x frames. By
823 * requiring this to fail twice we avoid races with
824 * pfc clearing the ARMED bit and conditions where we
825 * run the check_tx_hang logic with a transmit completion
826 * pending but without time to complete it yet.
827 */
828 if ((tx_done_old == tx_done) && tx_pending) {
829 /* make sure it is true for two checks in a row */
830 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
831 &tx_ring->state);
832 } else {
833 /* update completed stats and continue */
834 tx_ring->tx_stats.tx_done_old = tx_done;
835 /* reset the countdown */
836 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
837 }
838
839 return ret;
840 }
841
842 /**
843 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
844 * @adapter: driver private struct
845 **/
846 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
847 {
848
849 /* Do the reset outside of interrupt context */
850 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
851 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
852 e_warn(drv, "initiating reset due to tx timeout\n");
853 ixgbe_service_event_schedule(adapter);
854 }
855 }
856
857 /**
858 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
859 * @q_vector: structure containing interrupt and ring information
860 * @tx_ring: tx ring to clean
861 **/
862 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
863 struct ixgbe_ring *tx_ring)
864 {
865 struct ixgbe_adapter *adapter = q_vector->adapter;
866 struct ixgbe_tx_buffer *tx_buffer;
867 union ixgbe_adv_tx_desc *tx_desc;
868 unsigned int total_bytes = 0, total_packets = 0;
869 unsigned int budget = q_vector->tx.work_limit;
870 unsigned int i = tx_ring->next_to_clean;
871
872 if (test_bit(__IXGBE_DOWN, &adapter->state))
873 return true;
874
875 tx_buffer = &tx_ring->tx_buffer_info[i];
876 tx_desc = IXGBE_TX_DESC(tx_ring, i);
877 i -= tx_ring->count;
878
879 do {
880 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
881
882 /* if next_to_watch is not set then there is no work pending */
883 if (!eop_desc)
884 break;
885
886 /* prevent any other reads prior to eop_desc */
887 read_barrier_depends();
888
889 /* if DD is not set pending work has not been completed */
890 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
891 break;
892
893 /* clear next_to_watch to prevent false hangs */
894 tx_buffer->next_to_watch = NULL;
895
896 /* update the statistics for this packet */
897 total_bytes += tx_buffer->bytecount;
898 total_packets += tx_buffer->gso_segs;
899
900 /* free the skb */
901 dev_kfree_skb_any(tx_buffer->skb);
902
903 /* unmap skb header data */
904 dma_unmap_single(tx_ring->dev,
905 dma_unmap_addr(tx_buffer, dma),
906 dma_unmap_len(tx_buffer, len),
907 DMA_TO_DEVICE);
908
909 /* clear tx_buffer data */
910 tx_buffer->skb = NULL;
911 dma_unmap_len_set(tx_buffer, len, 0);
912
913 /* unmap remaining buffers */
914 while (tx_desc != eop_desc) {
915 tx_buffer++;
916 tx_desc++;
917 i++;
918 if (unlikely(!i)) {
919 i -= tx_ring->count;
920 tx_buffer = tx_ring->tx_buffer_info;
921 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
922 }
923
924 /* unmap any remaining paged data */
925 if (dma_unmap_len(tx_buffer, len)) {
926 dma_unmap_page(tx_ring->dev,
927 dma_unmap_addr(tx_buffer, dma),
928 dma_unmap_len(tx_buffer, len),
929 DMA_TO_DEVICE);
930 dma_unmap_len_set(tx_buffer, len, 0);
931 }
932 }
933
934 /* move us one more past the eop_desc for start of next pkt */
935 tx_buffer++;
936 tx_desc++;
937 i++;
938 if (unlikely(!i)) {
939 i -= tx_ring->count;
940 tx_buffer = tx_ring->tx_buffer_info;
941 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
942 }
943
944 /* issue prefetch for next Tx descriptor */
945 prefetch(tx_desc);
946
947 /* update budget accounting */
948 budget--;
949 } while (likely(budget));
950
951 i += tx_ring->count;
952 tx_ring->next_to_clean = i;
953 u64_stats_update_begin(&tx_ring->syncp);
954 tx_ring->stats.bytes += total_bytes;
955 tx_ring->stats.packets += total_packets;
956 u64_stats_update_end(&tx_ring->syncp);
957 q_vector->tx.total_bytes += total_bytes;
958 q_vector->tx.total_packets += total_packets;
959
960 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
961 /* schedule immediate reset if we believe we hung */
962 struct ixgbe_hw *hw = &adapter->hw;
963 e_err(drv, "Detected Tx Unit Hang\n"
964 " Tx Queue <%d>\n"
965 " TDH, TDT <%x>, <%x>\n"
966 " next_to_use <%x>\n"
967 " next_to_clean <%x>\n"
968 "tx_buffer_info[next_to_clean]\n"
969 " time_stamp <%lx>\n"
970 " jiffies <%lx>\n",
971 tx_ring->queue_index,
972 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
973 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
974 tx_ring->next_to_use, i,
975 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
976
977 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
978
979 e_info(probe,
980 "tx hang %d detected on queue %d, resetting adapter\n",
981 adapter->tx_timeout_count + 1, tx_ring->queue_index);
982
983 /* schedule immediate reset if we believe we hung */
984 ixgbe_tx_timeout_reset(adapter);
985
986 /* the adapter is about to reset, no point in enabling stuff */
987 return true;
988 }
989
990 netdev_tx_completed_queue(txring_txq(tx_ring),
991 total_packets, total_bytes);
992
993 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
994 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
995 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
996 /* Make sure that anybody stopping the queue after this
997 * sees the new next_to_clean.
998 */
999 smp_mb();
1000 if (__netif_subqueue_stopped(tx_ring->netdev,
1001 tx_ring->queue_index)
1002 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1003 netif_wake_subqueue(tx_ring->netdev,
1004 tx_ring->queue_index);
1005 ++tx_ring->tx_stats.restart_queue;
1006 }
1007 }
1008
1009 return !!budget;
1010 }
1011
1012 #ifdef CONFIG_IXGBE_DCA
1013 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1014 struct ixgbe_ring *tx_ring,
1015 int cpu)
1016 {
1017 struct ixgbe_hw *hw = &adapter->hw;
1018 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1019 u16 reg_offset;
1020
1021 switch (hw->mac.type) {
1022 case ixgbe_mac_82598EB:
1023 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1024 break;
1025 case ixgbe_mac_82599EB:
1026 case ixgbe_mac_X540:
1027 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1028 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1029 break;
1030 default:
1031 /* for unknown hardware do not write register */
1032 return;
1033 }
1034
1035 /*
1036 * We can enable relaxed ordering for reads, but not writes when
1037 * DCA is enabled. This is due to a known issue in some chipsets
1038 * which will cause the DCA tag to be cleared.
1039 */
1040 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1041 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1042 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1043
1044 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1045 }
1046
1047 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1048 struct ixgbe_ring *rx_ring,
1049 int cpu)
1050 {
1051 struct ixgbe_hw *hw = &adapter->hw;
1052 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1053 u8 reg_idx = rx_ring->reg_idx;
1054
1055
1056 switch (hw->mac.type) {
1057 case ixgbe_mac_82599EB:
1058 case ixgbe_mac_X540:
1059 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1060 break;
1061 default:
1062 break;
1063 }
1064
1065 /*
1066 * We can enable relaxed ordering for reads, but not writes when
1067 * DCA is enabled. This is due to a known issue in some chipsets
1068 * which will cause the DCA tag to be cleared.
1069 */
1070 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1071 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1072
1073 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1074 }
1075
1076 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1077 {
1078 struct ixgbe_adapter *adapter = q_vector->adapter;
1079 struct ixgbe_ring *ring;
1080 int cpu = get_cpu();
1081
1082 if (q_vector->cpu == cpu)
1083 goto out_no_update;
1084
1085 ixgbe_for_each_ring(ring, q_vector->tx)
1086 ixgbe_update_tx_dca(adapter, ring, cpu);
1087
1088 ixgbe_for_each_ring(ring, q_vector->rx)
1089 ixgbe_update_rx_dca(adapter, ring, cpu);
1090
1091 q_vector->cpu = cpu;
1092 out_no_update:
1093 put_cpu();
1094 }
1095
1096 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1097 {
1098 int i;
1099
1100 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1101 return;
1102
1103 /* always use CB2 mode, difference is masked in the CB driver */
1104 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1105
1106 for (i = 0; i < adapter->num_q_vectors; i++) {
1107 adapter->q_vector[i]->cpu = -1;
1108 ixgbe_update_dca(adapter->q_vector[i]);
1109 }
1110 }
1111
1112 static int __ixgbe_notify_dca(struct device *dev, void *data)
1113 {
1114 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1115 unsigned long event = *(unsigned long *)data;
1116
1117 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1118 return 0;
1119
1120 switch (event) {
1121 case DCA_PROVIDER_ADD:
1122 /* if we're already enabled, don't do it again */
1123 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1124 break;
1125 if (dca_add_requester(dev) == 0) {
1126 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1127 ixgbe_setup_dca(adapter);
1128 break;
1129 }
1130 /* Fall Through since DCA is disabled. */
1131 case DCA_PROVIDER_REMOVE:
1132 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1133 dca_remove_requester(dev);
1134 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1135 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1136 }
1137 break;
1138 }
1139
1140 return 0;
1141 }
1142
1143 #endif /* CONFIG_IXGBE_DCA */
1144 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1145 union ixgbe_adv_rx_desc *rx_desc,
1146 struct sk_buff *skb)
1147 {
1148 if (ring->netdev->features & NETIF_F_RXHASH)
1149 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1150 }
1151
1152 #ifdef IXGBE_FCOE
1153 /**
1154 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1155 * @ring: structure containing ring specific data
1156 * @rx_desc: advanced rx descriptor
1157 *
1158 * Returns : true if it is FCoE pkt
1159 */
1160 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1161 union ixgbe_adv_rx_desc *rx_desc)
1162 {
1163 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1164
1165 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1166 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1167 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1168 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1169 }
1170
1171 #endif /* IXGBE_FCOE */
1172 /**
1173 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1174 * @ring: structure containing ring specific data
1175 * @rx_desc: current Rx descriptor being processed
1176 * @skb: skb currently being received and modified
1177 **/
1178 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1179 union ixgbe_adv_rx_desc *rx_desc,
1180 struct sk_buff *skb)
1181 {
1182 skb_checksum_none_assert(skb);
1183
1184 /* Rx csum disabled */
1185 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1186 return;
1187
1188 /* if IP and error */
1189 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1190 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1191 ring->rx_stats.csum_err++;
1192 return;
1193 }
1194
1195 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1196 return;
1197
1198 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1199 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1200
1201 /*
1202 * 82599 errata, UDP frames with a 0 checksum can be marked as
1203 * checksum errors.
1204 */
1205 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1206 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1207 return;
1208
1209 ring->rx_stats.csum_err++;
1210 return;
1211 }
1212
1213 /* It must be a TCP or UDP packet with a valid checksum */
1214 skb->ip_summed = CHECKSUM_UNNECESSARY;
1215 }
1216
1217 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1218 {
1219 rx_ring->next_to_use = val;
1220
1221 /* update next to alloc since we have filled the ring */
1222 rx_ring->next_to_alloc = val;
1223 /*
1224 * Force memory writes to complete before letting h/w
1225 * know there are new descriptors to fetch. (Only
1226 * applicable for weak-ordered memory model archs,
1227 * such as IA-64).
1228 */
1229 wmb();
1230 writel(val, rx_ring->tail);
1231 }
1232
1233 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1234 struct ixgbe_rx_buffer *bi)
1235 {
1236 struct page *page = bi->page;
1237 dma_addr_t dma = bi->dma;
1238
1239 /* since we are recycling buffers we should seldom need to alloc */
1240 if (likely(dma))
1241 return true;
1242
1243 /* alloc new page for storage */
1244 if (likely(!page)) {
1245 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1246 bi->skb, ixgbe_rx_pg_order(rx_ring));
1247 if (unlikely(!page)) {
1248 rx_ring->rx_stats.alloc_rx_page_failed++;
1249 return false;
1250 }
1251 bi->page = page;
1252 }
1253
1254 /* map page for use */
1255 dma = dma_map_page(rx_ring->dev, page, 0,
1256 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1257
1258 /*
1259 * if mapping failed free memory back to system since
1260 * there isn't much point in holding memory we can't use
1261 */
1262 if (dma_mapping_error(rx_ring->dev, dma)) {
1263 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1264 bi->page = NULL;
1265
1266 rx_ring->rx_stats.alloc_rx_page_failed++;
1267 return false;
1268 }
1269
1270 bi->dma = dma;
1271 bi->page_offset = 0;
1272
1273 return true;
1274 }
1275
1276 /**
1277 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1278 * @rx_ring: ring to place buffers on
1279 * @cleaned_count: number of buffers to replace
1280 **/
1281 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1282 {
1283 union ixgbe_adv_rx_desc *rx_desc;
1284 struct ixgbe_rx_buffer *bi;
1285 u16 i = rx_ring->next_to_use;
1286
1287 /* nothing to do */
1288 if (!cleaned_count)
1289 return;
1290
1291 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1292 bi = &rx_ring->rx_buffer_info[i];
1293 i -= rx_ring->count;
1294
1295 do {
1296 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1297 break;
1298
1299 /*
1300 * Refresh the desc even if buffer_addrs didn't change
1301 * because each write-back erases this info.
1302 */
1303 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1304
1305 rx_desc++;
1306 bi++;
1307 i++;
1308 if (unlikely(!i)) {
1309 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1310 bi = rx_ring->rx_buffer_info;
1311 i -= rx_ring->count;
1312 }
1313
1314 /* clear the hdr_addr for the next_to_use descriptor */
1315 rx_desc->read.hdr_addr = 0;
1316
1317 cleaned_count--;
1318 } while (cleaned_count);
1319
1320 i += rx_ring->count;
1321
1322 if (rx_ring->next_to_use != i)
1323 ixgbe_release_rx_desc(rx_ring, i);
1324 }
1325
1326 /**
1327 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1328 * @data: pointer to the start of the headers
1329 * @max_len: total length of section to find headers in
1330 *
1331 * This function is meant to determine the length of headers that will
1332 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1333 * motivation of doing this is to only perform one pull for IPv4 TCP
1334 * packets so that we can do basic things like calculating the gso_size
1335 * based on the average data per packet.
1336 **/
1337 static unsigned int ixgbe_get_headlen(unsigned char *data,
1338 unsigned int max_len)
1339 {
1340 union {
1341 unsigned char *network;
1342 /* l2 headers */
1343 struct ethhdr *eth;
1344 struct vlan_hdr *vlan;
1345 /* l3 headers */
1346 struct iphdr *ipv4;
1347 struct ipv6hdr *ipv6;
1348 } hdr;
1349 __be16 protocol;
1350 u8 nexthdr = 0; /* default to not TCP */
1351 u8 hlen;
1352
1353 /* this should never happen, but better safe than sorry */
1354 if (max_len < ETH_HLEN)
1355 return max_len;
1356
1357 /* initialize network frame pointer */
1358 hdr.network = data;
1359
1360 /* set first protocol and move network header forward */
1361 protocol = hdr.eth->h_proto;
1362 hdr.network += ETH_HLEN;
1363
1364 /* handle any vlan tag if present */
1365 if (protocol == __constant_htons(ETH_P_8021Q)) {
1366 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1367 return max_len;
1368
1369 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1370 hdr.network += VLAN_HLEN;
1371 }
1372
1373 /* handle L3 protocols */
1374 if (protocol == __constant_htons(ETH_P_IP)) {
1375 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1376 return max_len;
1377
1378 /* access ihl as a u8 to avoid unaligned access on ia64 */
1379 hlen = (hdr.network[0] & 0x0F) << 2;
1380
1381 /* verify hlen meets minimum size requirements */
1382 if (hlen < sizeof(struct iphdr))
1383 return hdr.network - data;
1384
1385 /* record next protocol if header is present */
1386 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
1387 nexthdr = hdr.ipv4->protocol;
1388 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1389 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1390 return max_len;
1391
1392 /* record next protocol */
1393 nexthdr = hdr.ipv6->nexthdr;
1394 hlen = sizeof(struct ipv6hdr);
1395 #ifdef IXGBE_FCOE
1396 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1397 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1398 return max_len;
1399 hlen = FCOE_HEADER_LEN;
1400 #endif
1401 } else {
1402 return hdr.network - data;
1403 }
1404
1405 /* relocate pointer to start of L4 header */
1406 hdr.network += hlen;
1407
1408 /* finally sort out TCP/UDP */
1409 if (nexthdr == IPPROTO_TCP) {
1410 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1411 return max_len;
1412
1413 /* access doff as a u8 to avoid unaligned access on ia64 */
1414 hlen = (hdr.network[12] & 0xF0) >> 2;
1415
1416 /* verify hlen meets minimum size requirements */
1417 if (hlen < sizeof(struct tcphdr))
1418 return hdr.network - data;
1419
1420 hdr.network += hlen;
1421 } else if (nexthdr == IPPROTO_UDP) {
1422 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1423 return max_len;
1424
1425 hdr.network += sizeof(struct udphdr);
1426 }
1427
1428 /*
1429 * If everything has gone correctly hdr.network should be the
1430 * data section of the packet and will be the end of the header.
1431 * If not then it probably represents the end of the last recognized
1432 * header.
1433 */
1434 if ((hdr.network - data) < max_len)
1435 return hdr.network - data;
1436 else
1437 return max_len;
1438 }
1439
1440 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1441 struct sk_buff *skb)
1442 {
1443 u16 hdr_len = skb_headlen(skb);
1444
1445 /* set gso_size to avoid messing up TCP MSS */
1446 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1447 IXGBE_CB(skb)->append_cnt);
1448 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1449 }
1450
1451 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1452 struct sk_buff *skb)
1453 {
1454 /* if append_cnt is 0 then frame is not RSC */
1455 if (!IXGBE_CB(skb)->append_cnt)
1456 return;
1457
1458 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1459 rx_ring->rx_stats.rsc_flush++;
1460
1461 ixgbe_set_rsc_gso_size(rx_ring, skb);
1462
1463 /* gso_size is computed using append_cnt so always clear it last */
1464 IXGBE_CB(skb)->append_cnt = 0;
1465 }
1466
1467 /**
1468 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1469 * @rx_ring: rx descriptor ring packet is being transacted on
1470 * @rx_desc: pointer to the EOP Rx descriptor
1471 * @skb: pointer to current skb being populated
1472 *
1473 * This function checks the ring, descriptor, and packet information in
1474 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1475 * other fields within the skb.
1476 **/
1477 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1478 union ixgbe_adv_rx_desc *rx_desc,
1479 struct sk_buff *skb)
1480 {
1481 struct net_device *dev = rx_ring->netdev;
1482
1483 ixgbe_update_rsc_stats(rx_ring, skb);
1484
1485 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1486
1487 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1488
1489 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1490
1491 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1492 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1493 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1494 __vlan_hwaccel_put_tag(skb, vid);
1495 }
1496
1497 skb_record_rx_queue(skb, rx_ring->queue_index);
1498
1499 skb->protocol = eth_type_trans(skb, dev);
1500 }
1501
1502 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1503 struct sk_buff *skb)
1504 {
1505 struct ixgbe_adapter *adapter = q_vector->adapter;
1506
1507 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1508 napi_gro_receive(&q_vector->napi, skb);
1509 else
1510 netif_rx(skb);
1511 }
1512
1513 /**
1514 * ixgbe_is_non_eop - process handling of non-EOP buffers
1515 * @rx_ring: Rx ring being processed
1516 * @rx_desc: Rx descriptor for current buffer
1517 * @skb: Current socket buffer containing buffer in progress
1518 *
1519 * This function updates next to clean. If the buffer is an EOP buffer
1520 * this function exits returning false, otherwise it will place the
1521 * sk_buff in the next buffer to be chained and return true indicating
1522 * that this is in fact a non-EOP buffer.
1523 **/
1524 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1525 union ixgbe_adv_rx_desc *rx_desc,
1526 struct sk_buff *skb)
1527 {
1528 u32 ntc = rx_ring->next_to_clean + 1;
1529
1530 /* fetch, update, and store next to clean */
1531 ntc = (ntc < rx_ring->count) ? ntc : 0;
1532 rx_ring->next_to_clean = ntc;
1533
1534 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1535
1536 /* update RSC append count if present */
1537 if (ring_is_rsc_enabled(rx_ring)) {
1538 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1539 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1540
1541 if (unlikely(rsc_enabled)) {
1542 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1543
1544 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1545 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1546
1547 /* update ntc based on RSC value */
1548 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1549 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1550 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1551 }
1552 }
1553
1554 /* if we are the last buffer then there is nothing else to do */
1555 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1556 return false;
1557
1558 /* place skb in next buffer to be received */
1559 rx_ring->rx_buffer_info[ntc].skb = skb;
1560 rx_ring->rx_stats.non_eop_descs++;
1561
1562 return true;
1563 }
1564
1565 /**
1566 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1567 * @rx_ring: rx descriptor ring packet is being transacted on
1568 * @skb: pointer to current skb being adjusted
1569 *
1570 * This function is an ixgbe specific version of __pskb_pull_tail. The
1571 * main difference between this version and the original function is that
1572 * this function can make several assumptions about the state of things
1573 * that allow for significant optimizations versus the standard function.
1574 * As a result we can do things like drop a frag and maintain an accurate
1575 * truesize for the skb.
1576 */
1577 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1578 struct sk_buff *skb)
1579 {
1580 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1581 unsigned char *va;
1582 unsigned int pull_len;
1583
1584 /*
1585 * it is valid to use page_address instead of kmap since we are
1586 * working with pages allocated out of the lomem pool per
1587 * alloc_page(GFP_ATOMIC)
1588 */
1589 va = skb_frag_address(frag);
1590
1591 /*
1592 * we need the header to contain the greater of either ETH_HLEN or
1593 * 60 bytes if the skb->len is less than 60 for skb_pad.
1594 */
1595 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
1596
1597 /* align pull length to size of long to optimize memcpy performance */
1598 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1599
1600 /* update all of the pointers */
1601 skb_frag_size_sub(frag, pull_len);
1602 frag->page_offset += pull_len;
1603 skb->data_len -= pull_len;
1604 skb->tail += pull_len;
1605 }
1606
1607 /**
1608 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1609 * @rx_ring: rx descriptor ring packet is being transacted on
1610 * @skb: pointer to current skb being updated
1611 *
1612 * This function provides a basic DMA sync up for the first fragment of an
1613 * skb. The reason for doing this is that the first fragment cannot be
1614 * unmapped until we have reached the end of packet descriptor for a buffer
1615 * chain.
1616 */
1617 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1618 struct sk_buff *skb)
1619 {
1620 /* if the page was released unmap it, else just sync our portion */
1621 if (unlikely(IXGBE_CB(skb)->page_released)) {
1622 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1623 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1624 IXGBE_CB(skb)->page_released = false;
1625 } else {
1626 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1627
1628 dma_sync_single_range_for_cpu(rx_ring->dev,
1629 IXGBE_CB(skb)->dma,
1630 frag->page_offset,
1631 ixgbe_rx_bufsz(rx_ring),
1632 DMA_FROM_DEVICE);
1633 }
1634 IXGBE_CB(skb)->dma = 0;
1635 }
1636
1637 /**
1638 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1639 * @rx_ring: rx descriptor ring packet is being transacted on
1640 * @rx_desc: pointer to the EOP Rx descriptor
1641 * @skb: pointer to current skb being fixed
1642 *
1643 * Check for corrupted packet headers caused by senders on the local L2
1644 * embedded NIC switch not setting up their Tx Descriptors right. These
1645 * should be very rare.
1646 *
1647 * Also address the case where we are pulling data in on pages only
1648 * and as such no data is present in the skb header.
1649 *
1650 * In addition if skb is not at least 60 bytes we need to pad it so that
1651 * it is large enough to qualify as a valid Ethernet frame.
1652 *
1653 * Returns true if an error was encountered and skb was freed.
1654 **/
1655 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1656 union ixgbe_adv_rx_desc *rx_desc,
1657 struct sk_buff *skb)
1658 {
1659 struct net_device *netdev = rx_ring->netdev;
1660
1661 /* verify that the packet does not have any known errors */
1662 if (unlikely(ixgbe_test_staterr(rx_desc,
1663 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1664 !(netdev->features & NETIF_F_RXALL))) {
1665 dev_kfree_skb_any(skb);
1666 return true;
1667 }
1668
1669 /* place header in linear portion of buffer */
1670 if (skb_is_nonlinear(skb))
1671 ixgbe_pull_tail(rx_ring, skb);
1672
1673 #ifdef IXGBE_FCOE
1674 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1675 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1676 return false;
1677
1678 #endif
1679 /* if skb_pad returns an error the skb was freed */
1680 if (unlikely(skb->len < 60)) {
1681 int pad_len = 60 - skb->len;
1682
1683 if (skb_pad(skb, pad_len))
1684 return true;
1685 __skb_put(skb, pad_len);
1686 }
1687
1688 return false;
1689 }
1690
1691 /**
1692 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1693 * @rx_ring: rx descriptor ring to store buffers on
1694 * @old_buff: donor buffer to have page reused
1695 *
1696 * Synchronizes page for reuse by the adapter
1697 **/
1698 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1699 struct ixgbe_rx_buffer *old_buff)
1700 {
1701 struct ixgbe_rx_buffer *new_buff;
1702 u16 nta = rx_ring->next_to_alloc;
1703
1704 new_buff = &rx_ring->rx_buffer_info[nta];
1705
1706 /* update, and store next to alloc */
1707 nta++;
1708 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1709
1710 /* transfer page from old buffer to new buffer */
1711 new_buff->page = old_buff->page;
1712 new_buff->dma = old_buff->dma;
1713 new_buff->page_offset = old_buff->page_offset;
1714
1715 /* sync the buffer for use by the device */
1716 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1717 new_buff->page_offset,
1718 ixgbe_rx_bufsz(rx_ring),
1719 DMA_FROM_DEVICE);
1720 }
1721
1722 /**
1723 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1724 * @rx_ring: rx descriptor ring to transact packets on
1725 * @rx_buffer: buffer containing page to add
1726 * @rx_desc: descriptor containing length of buffer written by hardware
1727 * @skb: sk_buff to place the data into
1728 *
1729 * This function will add the data contained in rx_buffer->page to the skb.
1730 * This is done either through a direct copy if the data in the buffer is
1731 * less than the skb header size, otherwise it will just attach the page as
1732 * a frag to the skb.
1733 *
1734 * The function will then update the page offset if necessary and return
1735 * true if the buffer can be reused by the adapter.
1736 **/
1737 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1738 struct ixgbe_rx_buffer *rx_buffer,
1739 union ixgbe_adv_rx_desc *rx_desc,
1740 struct sk_buff *skb)
1741 {
1742 struct page *page = rx_buffer->page;
1743 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1744 #if (PAGE_SIZE < 8192)
1745 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1746 #else
1747 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1748 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1749 ixgbe_rx_bufsz(rx_ring);
1750 #endif
1751
1752 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1753 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1754
1755 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1756
1757 /* we can reuse buffer as-is, just make sure it is local */
1758 if (likely(page_to_nid(page) == numa_node_id()))
1759 return true;
1760
1761 /* this page cannot be reused so discard it */
1762 put_page(page);
1763 return false;
1764 }
1765
1766 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1767 rx_buffer->page_offset, size, truesize);
1768
1769 /* avoid re-using remote pages */
1770 if (unlikely(page_to_nid(page) != numa_node_id()))
1771 return false;
1772
1773 #if (PAGE_SIZE < 8192)
1774 /* if we are only owner of page we can reuse it */
1775 if (unlikely(page_count(page) != 1))
1776 return false;
1777
1778 /* flip page offset to other buffer */
1779 rx_buffer->page_offset ^= truesize;
1780
1781 /*
1782 * since we are the only owner of the page and we need to
1783 * increment it, just set the value to 2 in order to avoid
1784 * an unecessary locked operation
1785 */
1786 atomic_set(&page->_count, 2);
1787 #else
1788 /* move offset up to the next cache line */
1789 rx_buffer->page_offset += truesize;
1790
1791 if (rx_buffer->page_offset > last_offset)
1792 return false;
1793
1794 /* bump ref count on page before it is given to the stack */
1795 get_page(page);
1796 #endif
1797
1798 return true;
1799 }
1800
1801 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1802 union ixgbe_adv_rx_desc *rx_desc)
1803 {
1804 struct ixgbe_rx_buffer *rx_buffer;
1805 struct sk_buff *skb;
1806 struct page *page;
1807
1808 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1809 page = rx_buffer->page;
1810 prefetchw(page);
1811
1812 skb = rx_buffer->skb;
1813
1814 if (likely(!skb)) {
1815 void *page_addr = page_address(page) +
1816 rx_buffer->page_offset;
1817
1818 /* prefetch first cache line of first page */
1819 prefetch(page_addr);
1820 #if L1_CACHE_BYTES < 128
1821 prefetch(page_addr + L1_CACHE_BYTES);
1822 #endif
1823
1824 /* allocate a skb to store the frags */
1825 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1826 IXGBE_RX_HDR_SIZE);
1827 if (unlikely(!skb)) {
1828 rx_ring->rx_stats.alloc_rx_buff_failed++;
1829 return NULL;
1830 }
1831
1832 /*
1833 * we will be copying header into skb->data in
1834 * pskb_may_pull so it is in our interest to prefetch
1835 * it now to avoid a possible cache miss
1836 */
1837 prefetchw(skb->data);
1838
1839 /*
1840 * Delay unmapping of the first packet. It carries the
1841 * header information, HW may still access the header
1842 * after the writeback. Only unmap it when EOP is
1843 * reached
1844 */
1845 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1846 goto dma_sync;
1847
1848 IXGBE_CB(skb)->dma = rx_buffer->dma;
1849 } else {
1850 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1851 ixgbe_dma_sync_frag(rx_ring, skb);
1852
1853 dma_sync:
1854 /* we are reusing so sync this buffer for CPU use */
1855 dma_sync_single_range_for_cpu(rx_ring->dev,
1856 rx_buffer->dma,
1857 rx_buffer->page_offset,
1858 ixgbe_rx_bufsz(rx_ring),
1859 DMA_FROM_DEVICE);
1860 }
1861
1862 /* pull page into skb */
1863 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1864 /* hand second half of page back to the ring */
1865 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1866 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1867 /* the page has been released from the ring */
1868 IXGBE_CB(skb)->page_released = true;
1869 } else {
1870 /* we are not reusing the buffer so unmap it */
1871 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1872 ixgbe_rx_pg_size(rx_ring),
1873 DMA_FROM_DEVICE);
1874 }
1875
1876 /* clear contents of buffer_info */
1877 rx_buffer->skb = NULL;
1878 rx_buffer->dma = 0;
1879 rx_buffer->page = NULL;
1880
1881 return skb;
1882 }
1883
1884 /**
1885 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1886 * @q_vector: structure containing interrupt and ring information
1887 * @rx_ring: rx descriptor ring to transact packets on
1888 * @budget: Total limit on number of packets to process
1889 *
1890 * This function provides a "bounce buffer" approach to Rx interrupt
1891 * processing. The advantage to this is that on systems that have
1892 * expensive overhead for IOMMU access this provides a means of avoiding
1893 * it by maintaining the mapping of the page to the syste.
1894 *
1895 * Returns true if all work is completed without reaching budget
1896 **/
1897 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1898 struct ixgbe_ring *rx_ring,
1899 const int budget)
1900 {
1901 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1902 #ifdef IXGBE_FCOE
1903 struct ixgbe_adapter *adapter = q_vector->adapter;
1904 int ddp_bytes;
1905 unsigned int mss = 0;
1906 #endif /* IXGBE_FCOE */
1907 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1908
1909 do {
1910 union ixgbe_adv_rx_desc *rx_desc;
1911 struct sk_buff *skb;
1912
1913 /* return some buffers to hardware, one at a time is too slow */
1914 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1915 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1916 cleaned_count = 0;
1917 }
1918
1919 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
1920
1921 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1922 break;
1923
1924 /*
1925 * This memory barrier is needed to keep us from reading
1926 * any other fields out of the rx_desc until we know the
1927 * RXD_STAT_DD bit is set
1928 */
1929 rmb();
1930
1931 /* retrieve a buffer from the ring */
1932 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
1933
1934 /* exit if we failed to retrieve a buffer */
1935 if (!skb)
1936 break;
1937
1938 cleaned_count++;
1939
1940 /* place incomplete frames back on ring for completion */
1941 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1942 continue;
1943
1944 /* verify the packet layout is correct */
1945 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1946 continue;
1947
1948 /* probably a little skewed due to removing CRC */
1949 total_rx_bytes += skb->len;
1950
1951 /* populate checksum, timestamp, VLAN, and protocol */
1952 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1953
1954 #ifdef IXGBE_FCOE
1955 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1956 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
1957 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1958 /* include DDPed FCoE data */
1959 if (ddp_bytes > 0) {
1960 if (!mss) {
1961 mss = rx_ring->netdev->mtu -
1962 sizeof(struct fcoe_hdr) -
1963 sizeof(struct fc_frame_header) -
1964 sizeof(struct fcoe_crc_eof);
1965 if (mss > 512)
1966 mss &= ~511;
1967 }
1968 total_rx_bytes += ddp_bytes;
1969 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
1970 mss);
1971 }
1972 if (!ddp_bytes) {
1973 dev_kfree_skb_any(skb);
1974 continue;
1975 }
1976 }
1977
1978 #endif /* IXGBE_FCOE */
1979 ixgbe_rx_skb(q_vector, skb);
1980
1981 /* update budget accounting */
1982 total_rx_packets++;
1983 } while (likely(total_rx_packets < budget));
1984
1985 u64_stats_update_begin(&rx_ring->syncp);
1986 rx_ring->stats.packets += total_rx_packets;
1987 rx_ring->stats.bytes += total_rx_bytes;
1988 u64_stats_update_end(&rx_ring->syncp);
1989 q_vector->rx.total_packets += total_rx_packets;
1990 q_vector->rx.total_bytes += total_rx_bytes;
1991
1992 if (cleaned_count)
1993 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1994
1995 return (total_rx_packets < budget);
1996 }
1997
1998 /**
1999 * ixgbe_configure_msix - Configure MSI-X hardware
2000 * @adapter: board private structure
2001 *
2002 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2003 * interrupts.
2004 **/
2005 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2006 {
2007 struct ixgbe_q_vector *q_vector;
2008 int v_idx;
2009 u32 mask;
2010
2011 /* Populate MSIX to EITR Select */
2012 if (adapter->num_vfs > 32) {
2013 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2014 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2015 }
2016
2017 /*
2018 * Populate the IVAR table and set the ITR values to the
2019 * corresponding register.
2020 */
2021 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2022 struct ixgbe_ring *ring;
2023 q_vector = adapter->q_vector[v_idx];
2024
2025 ixgbe_for_each_ring(ring, q_vector->rx)
2026 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2027
2028 ixgbe_for_each_ring(ring, q_vector->tx)
2029 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2030
2031 ixgbe_write_eitr(q_vector);
2032 }
2033
2034 switch (adapter->hw.mac.type) {
2035 case ixgbe_mac_82598EB:
2036 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2037 v_idx);
2038 break;
2039 case ixgbe_mac_82599EB:
2040 case ixgbe_mac_X540:
2041 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2042 break;
2043 default:
2044 break;
2045 }
2046 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2047
2048 /* set up to autoclear timer, and the vectors */
2049 mask = IXGBE_EIMS_ENABLE_MASK;
2050 mask &= ~(IXGBE_EIMS_OTHER |
2051 IXGBE_EIMS_MAILBOX |
2052 IXGBE_EIMS_LSC);
2053
2054 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2055 }
2056
2057 enum latency_range {
2058 lowest_latency = 0,
2059 low_latency = 1,
2060 bulk_latency = 2,
2061 latency_invalid = 255
2062 };
2063
2064 /**
2065 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2066 * @q_vector: structure containing interrupt and ring information
2067 * @ring_container: structure containing ring performance data
2068 *
2069 * Stores a new ITR value based on packets and byte
2070 * counts during the last interrupt. The advantage of per interrupt
2071 * computation is faster updates and more accurate ITR for the current
2072 * traffic pattern. Constants in this function were computed
2073 * based on theoretical maximum wire speed and thresholds were set based
2074 * on testing data as well as attempting to minimize response time
2075 * while increasing bulk throughput.
2076 * this functionality is controlled by the InterruptThrottleRate module
2077 * parameter (see ixgbe_param.c)
2078 **/
2079 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2080 struct ixgbe_ring_container *ring_container)
2081 {
2082 int bytes = ring_container->total_bytes;
2083 int packets = ring_container->total_packets;
2084 u32 timepassed_us;
2085 u64 bytes_perint;
2086 u8 itr_setting = ring_container->itr;
2087
2088 if (packets == 0)
2089 return;
2090
2091 /* simple throttlerate management
2092 * 0-10MB/s lowest (100000 ints/s)
2093 * 10-20MB/s low (20000 ints/s)
2094 * 20-1249MB/s bulk (8000 ints/s)
2095 */
2096 /* what was last interrupt timeslice? */
2097 timepassed_us = q_vector->itr >> 2;
2098 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2099
2100 switch (itr_setting) {
2101 case lowest_latency:
2102 if (bytes_perint > 10)
2103 itr_setting = low_latency;
2104 break;
2105 case low_latency:
2106 if (bytes_perint > 20)
2107 itr_setting = bulk_latency;
2108 else if (bytes_perint <= 10)
2109 itr_setting = lowest_latency;
2110 break;
2111 case bulk_latency:
2112 if (bytes_perint <= 20)
2113 itr_setting = low_latency;
2114 break;
2115 }
2116
2117 /* clear work counters since we have the values we need */
2118 ring_container->total_bytes = 0;
2119 ring_container->total_packets = 0;
2120
2121 /* write updated itr to ring container */
2122 ring_container->itr = itr_setting;
2123 }
2124
2125 /**
2126 * ixgbe_write_eitr - write EITR register in hardware specific way
2127 * @q_vector: structure containing interrupt and ring information
2128 *
2129 * This function is made to be called by ethtool and by the driver
2130 * when it needs to update EITR registers at runtime. Hardware
2131 * specific quirks/differences are taken care of here.
2132 */
2133 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2134 {
2135 struct ixgbe_adapter *adapter = q_vector->adapter;
2136 struct ixgbe_hw *hw = &adapter->hw;
2137 int v_idx = q_vector->v_idx;
2138 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2139
2140 switch (adapter->hw.mac.type) {
2141 case ixgbe_mac_82598EB:
2142 /* must write high and low 16 bits to reset counter */
2143 itr_reg |= (itr_reg << 16);
2144 break;
2145 case ixgbe_mac_82599EB:
2146 case ixgbe_mac_X540:
2147 /*
2148 * set the WDIS bit to not clear the timer bits and cause an
2149 * immediate assertion of the interrupt
2150 */
2151 itr_reg |= IXGBE_EITR_CNT_WDIS;
2152 break;
2153 default:
2154 break;
2155 }
2156 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2157 }
2158
2159 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2160 {
2161 u32 new_itr = q_vector->itr;
2162 u8 current_itr;
2163
2164 ixgbe_update_itr(q_vector, &q_vector->tx);
2165 ixgbe_update_itr(q_vector, &q_vector->rx);
2166
2167 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2168
2169 switch (current_itr) {
2170 /* counts and packets in update_itr are dependent on these numbers */
2171 case lowest_latency:
2172 new_itr = IXGBE_100K_ITR;
2173 break;
2174 case low_latency:
2175 new_itr = IXGBE_20K_ITR;
2176 break;
2177 case bulk_latency:
2178 new_itr = IXGBE_8K_ITR;
2179 break;
2180 default:
2181 break;
2182 }
2183
2184 if (new_itr != q_vector->itr) {
2185 /* do an exponential smoothing */
2186 new_itr = (10 * new_itr * q_vector->itr) /
2187 ((9 * new_itr) + q_vector->itr);
2188
2189 /* save the algorithm value here */
2190 q_vector->itr = new_itr;
2191
2192 ixgbe_write_eitr(q_vector);
2193 }
2194 }
2195
2196 /**
2197 * ixgbe_check_overtemp_subtask - check for over temperature
2198 * @adapter: pointer to adapter
2199 **/
2200 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2201 {
2202 struct ixgbe_hw *hw = &adapter->hw;
2203 u32 eicr = adapter->interrupt_event;
2204
2205 if (test_bit(__IXGBE_DOWN, &adapter->state))
2206 return;
2207
2208 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2209 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2210 return;
2211
2212 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2213
2214 switch (hw->device_id) {
2215 case IXGBE_DEV_ID_82599_T3_LOM:
2216 /*
2217 * Since the warning interrupt is for both ports
2218 * we don't have to check if:
2219 * - This interrupt wasn't for our port.
2220 * - We may have missed the interrupt so always have to
2221 * check if we got a LSC
2222 */
2223 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2224 !(eicr & IXGBE_EICR_LSC))
2225 return;
2226
2227 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2228 u32 speed;
2229 bool link_up = false;
2230
2231 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2232
2233 if (link_up)
2234 return;
2235 }
2236
2237 /* Check if this is not due to overtemp */
2238 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2239 return;
2240
2241 break;
2242 default:
2243 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2244 return;
2245 break;
2246 }
2247 e_crit(drv,
2248 "Network adapter has been stopped because it has over heated. "
2249 "Restart the computer. If the problem persists, "
2250 "power off the system and replace the adapter\n");
2251
2252 adapter->interrupt_event = 0;
2253 }
2254
2255 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2256 {
2257 struct ixgbe_hw *hw = &adapter->hw;
2258
2259 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2260 (eicr & IXGBE_EICR_GPI_SDP1)) {
2261 e_crit(probe, "Fan has stopped, replace the adapter\n");
2262 /* write to clear the interrupt */
2263 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2264 }
2265 }
2266
2267 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2268 {
2269 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2270 return;
2271
2272 switch (adapter->hw.mac.type) {
2273 case ixgbe_mac_82599EB:
2274 /*
2275 * Need to check link state so complete overtemp check
2276 * on service task
2277 */
2278 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2279 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2280 adapter->interrupt_event = eicr;
2281 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2282 ixgbe_service_event_schedule(adapter);
2283 return;
2284 }
2285 return;
2286 case ixgbe_mac_X540:
2287 if (!(eicr & IXGBE_EICR_TS))
2288 return;
2289 break;
2290 default:
2291 return;
2292 }
2293
2294 e_crit(drv,
2295 "Network adapter has been stopped because it has over heated. "
2296 "Restart the computer. If the problem persists, "
2297 "power off the system and replace the adapter\n");
2298 }
2299
2300 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2301 {
2302 struct ixgbe_hw *hw = &adapter->hw;
2303
2304 if (eicr & IXGBE_EICR_GPI_SDP2) {
2305 /* Clear the interrupt */
2306 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2307 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2308 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2309 ixgbe_service_event_schedule(adapter);
2310 }
2311 }
2312
2313 if (eicr & IXGBE_EICR_GPI_SDP1) {
2314 /* Clear the interrupt */
2315 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2316 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2317 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2318 ixgbe_service_event_schedule(adapter);
2319 }
2320 }
2321 }
2322
2323 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2324 {
2325 struct ixgbe_hw *hw = &adapter->hw;
2326
2327 adapter->lsc_int++;
2328 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2329 adapter->link_check_timeout = jiffies;
2330 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2331 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2332 IXGBE_WRITE_FLUSH(hw);
2333 ixgbe_service_event_schedule(adapter);
2334 }
2335 }
2336
2337 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2338 u64 qmask)
2339 {
2340 u32 mask;
2341 struct ixgbe_hw *hw = &adapter->hw;
2342
2343 switch (hw->mac.type) {
2344 case ixgbe_mac_82598EB:
2345 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2346 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2347 break;
2348 case ixgbe_mac_82599EB:
2349 case ixgbe_mac_X540:
2350 mask = (qmask & 0xFFFFFFFF);
2351 if (mask)
2352 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2353 mask = (qmask >> 32);
2354 if (mask)
2355 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2356 break;
2357 default:
2358 break;
2359 }
2360 /* skip the flush */
2361 }
2362
2363 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2364 u64 qmask)
2365 {
2366 u32 mask;
2367 struct ixgbe_hw *hw = &adapter->hw;
2368
2369 switch (hw->mac.type) {
2370 case ixgbe_mac_82598EB:
2371 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2372 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2373 break;
2374 case ixgbe_mac_82599EB:
2375 case ixgbe_mac_X540:
2376 mask = (qmask & 0xFFFFFFFF);
2377 if (mask)
2378 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2379 mask = (qmask >> 32);
2380 if (mask)
2381 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2382 break;
2383 default:
2384 break;
2385 }
2386 /* skip the flush */
2387 }
2388
2389 /**
2390 * ixgbe_irq_enable - Enable default interrupt generation settings
2391 * @adapter: board private structure
2392 **/
2393 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2394 bool flush)
2395 {
2396 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2397
2398 /* don't reenable LSC while waiting for link */
2399 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2400 mask &= ~IXGBE_EIMS_LSC;
2401
2402 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2403 switch (adapter->hw.mac.type) {
2404 case ixgbe_mac_82599EB:
2405 mask |= IXGBE_EIMS_GPI_SDP0;
2406 break;
2407 case ixgbe_mac_X540:
2408 mask |= IXGBE_EIMS_TS;
2409 break;
2410 default:
2411 break;
2412 }
2413 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2414 mask |= IXGBE_EIMS_GPI_SDP1;
2415 switch (adapter->hw.mac.type) {
2416 case ixgbe_mac_82599EB:
2417 mask |= IXGBE_EIMS_GPI_SDP1;
2418 mask |= IXGBE_EIMS_GPI_SDP2;
2419 case ixgbe_mac_X540:
2420 mask |= IXGBE_EIMS_ECC;
2421 mask |= IXGBE_EIMS_MAILBOX;
2422 break;
2423 default:
2424 break;
2425 }
2426
2427 if (adapter->hw.mac.type == ixgbe_mac_X540)
2428 mask |= IXGBE_EIMS_TIMESYNC;
2429
2430 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2431 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2432 mask |= IXGBE_EIMS_FLOW_DIR;
2433
2434 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2435 if (queues)
2436 ixgbe_irq_enable_queues(adapter, ~0);
2437 if (flush)
2438 IXGBE_WRITE_FLUSH(&adapter->hw);
2439 }
2440
2441 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2442 {
2443 struct ixgbe_adapter *adapter = data;
2444 struct ixgbe_hw *hw = &adapter->hw;
2445 u32 eicr;
2446
2447 /*
2448 * Workaround for Silicon errata. Use clear-by-write instead
2449 * of clear-by-read. Reading with EICS will return the
2450 * interrupt causes without clearing, which later be done
2451 * with the write to EICR.
2452 */
2453 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2454 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2455
2456 if (eicr & IXGBE_EICR_LSC)
2457 ixgbe_check_lsc(adapter);
2458
2459 if (eicr & IXGBE_EICR_MAILBOX)
2460 ixgbe_msg_task(adapter);
2461
2462 switch (hw->mac.type) {
2463 case ixgbe_mac_82599EB:
2464 case ixgbe_mac_X540:
2465 if (eicr & IXGBE_EICR_ECC)
2466 e_info(link, "Received unrecoverable ECC Err, please "
2467 "reboot\n");
2468 /* Handle Flow Director Full threshold interrupt */
2469 if (eicr & IXGBE_EICR_FLOW_DIR) {
2470 int reinit_count = 0;
2471 int i;
2472 for (i = 0; i < adapter->num_tx_queues; i++) {
2473 struct ixgbe_ring *ring = adapter->tx_ring[i];
2474 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2475 &ring->state))
2476 reinit_count++;
2477 }
2478 if (reinit_count) {
2479 /* no more flow director interrupts until after init */
2480 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2481 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2482 ixgbe_service_event_schedule(adapter);
2483 }
2484 }
2485 ixgbe_check_sfp_event(adapter, eicr);
2486 ixgbe_check_overtemp_event(adapter, eicr);
2487 break;
2488 default:
2489 break;
2490 }
2491
2492 ixgbe_check_fan_failure(adapter, eicr);
2493
2494 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2495 ixgbe_ptp_check_pps_event(adapter, eicr);
2496
2497 /* re-enable the original interrupt state, no lsc, no queues */
2498 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2499 ixgbe_irq_enable(adapter, false, false);
2500
2501 return IRQ_HANDLED;
2502 }
2503
2504 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2505 {
2506 struct ixgbe_q_vector *q_vector = data;
2507
2508 /* EIAM disabled interrupts (on this vector) for us */
2509
2510 if (q_vector->rx.ring || q_vector->tx.ring)
2511 napi_schedule(&q_vector->napi);
2512
2513 return IRQ_HANDLED;
2514 }
2515
2516 /**
2517 * ixgbe_poll - NAPI Rx polling callback
2518 * @napi: structure for representing this polling device
2519 * @budget: how many packets driver is allowed to clean
2520 *
2521 * This function is used for legacy and MSI, NAPI mode
2522 **/
2523 int ixgbe_poll(struct napi_struct *napi, int budget)
2524 {
2525 struct ixgbe_q_vector *q_vector =
2526 container_of(napi, struct ixgbe_q_vector, napi);
2527 struct ixgbe_adapter *adapter = q_vector->adapter;
2528 struct ixgbe_ring *ring;
2529 int per_ring_budget;
2530 bool clean_complete = true;
2531
2532 #ifdef CONFIG_IXGBE_DCA
2533 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2534 ixgbe_update_dca(q_vector);
2535 #endif
2536
2537 ixgbe_for_each_ring(ring, q_vector->tx)
2538 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2539
2540 /* attempt to distribute budget to each queue fairly, but don't allow
2541 * the budget to go below 1 because we'll exit polling */
2542 if (q_vector->rx.count > 1)
2543 per_ring_budget = max(budget/q_vector->rx.count, 1);
2544 else
2545 per_ring_budget = budget;
2546
2547 ixgbe_for_each_ring(ring, q_vector->rx)
2548 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2549 per_ring_budget);
2550
2551 /* If all work not completed, return budget and keep polling */
2552 if (!clean_complete)
2553 return budget;
2554
2555 /* all work done, exit the polling mode */
2556 napi_complete(napi);
2557 if (adapter->rx_itr_setting & 1)
2558 ixgbe_set_itr(q_vector);
2559 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2560 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2561
2562 return 0;
2563 }
2564
2565 /**
2566 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2567 * @adapter: board private structure
2568 *
2569 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2570 * interrupts from the kernel.
2571 **/
2572 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2573 {
2574 struct net_device *netdev = adapter->netdev;
2575 int vector, err;
2576 int ri = 0, ti = 0;
2577
2578 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2579 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2580 struct msix_entry *entry = &adapter->msix_entries[vector];
2581
2582 if (q_vector->tx.ring && q_vector->rx.ring) {
2583 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2584 "%s-%s-%d", netdev->name, "TxRx", ri++);
2585 ti++;
2586 } else if (q_vector->rx.ring) {
2587 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2588 "%s-%s-%d", netdev->name, "rx", ri++);
2589 } else if (q_vector->tx.ring) {
2590 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2591 "%s-%s-%d", netdev->name, "tx", ti++);
2592 } else {
2593 /* skip this unused q_vector */
2594 continue;
2595 }
2596 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2597 q_vector->name, q_vector);
2598 if (err) {
2599 e_err(probe, "request_irq failed for MSIX interrupt "
2600 "Error: %d\n", err);
2601 goto free_queue_irqs;
2602 }
2603 /* If Flow Director is enabled, set interrupt affinity */
2604 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2605 /* assign the mask for this irq */
2606 irq_set_affinity_hint(entry->vector,
2607 &q_vector->affinity_mask);
2608 }
2609 }
2610
2611 err = request_irq(adapter->msix_entries[vector].vector,
2612 ixgbe_msix_other, 0, netdev->name, adapter);
2613 if (err) {
2614 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2615 goto free_queue_irqs;
2616 }
2617
2618 return 0;
2619
2620 free_queue_irqs:
2621 while (vector) {
2622 vector--;
2623 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2624 NULL);
2625 free_irq(adapter->msix_entries[vector].vector,
2626 adapter->q_vector[vector]);
2627 }
2628 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2629 pci_disable_msix(adapter->pdev);
2630 kfree(adapter->msix_entries);
2631 adapter->msix_entries = NULL;
2632 return err;
2633 }
2634
2635 /**
2636 * ixgbe_intr - legacy mode Interrupt Handler
2637 * @irq: interrupt number
2638 * @data: pointer to a network interface device structure
2639 **/
2640 static irqreturn_t ixgbe_intr(int irq, void *data)
2641 {
2642 struct ixgbe_adapter *adapter = data;
2643 struct ixgbe_hw *hw = &adapter->hw;
2644 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2645 u32 eicr;
2646
2647 /*
2648 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2649 * before the read of EICR.
2650 */
2651 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2652
2653 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2654 * therefore no explicit interrupt disable is necessary */
2655 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2656 if (!eicr) {
2657 /*
2658 * shared interrupt alert!
2659 * make sure interrupts are enabled because the read will
2660 * have disabled interrupts due to EIAM
2661 * finish the workaround of silicon errata on 82598. Unmask
2662 * the interrupt that we masked before the EICR read.
2663 */
2664 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2665 ixgbe_irq_enable(adapter, true, true);
2666 return IRQ_NONE; /* Not our interrupt */
2667 }
2668
2669 if (eicr & IXGBE_EICR_LSC)
2670 ixgbe_check_lsc(adapter);
2671
2672 switch (hw->mac.type) {
2673 case ixgbe_mac_82599EB:
2674 ixgbe_check_sfp_event(adapter, eicr);
2675 /* Fall through */
2676 case ixgbe_mac_X540:
2677 if (eicr & IXGBE_EICR_ECC)
2678 e_info(link, "Received unrecoverable ECC err, please "
2679 "reboot\n");
2680 ixgbe_check_overtemp_event(adapter, eicr);
2681 break;
2682 default:
2683 break;
2684 }
2685
2686 ixgbe_check_fan_failure(adapter, eicr);
2687 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2688 ixgbe_ptp_check_pps_event(adapter, eicr);
2689
2690 /* would disable interrupts here but EIAM disabled it */
2691 napi_schedule(&q_vector->napi);
2692
2693 /*
2694 * re-enable link(maybe) and non-queue interrupts, no flush.
2695 * ixgbe_poll will re-enable the queue interrupts
2696 */
2697 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2698 ixgbe_irq_enable(adapter, false, false);
2699
2700 return IRQ_HANDLED;
2701 }
2702
2703 /**
2704 * ixgbe_request_irq - initialize interrupts
2705 * @adapter: board private structure
2706 *
2707 * Attempts to configure interrupts using the best available
2708 * capabilities of the hardware and kernel.
2709 **/
2710 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2711 {
2712 struct net_device *netdev = adapter->netdev;
2713 int err;
2714
2715 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2716 err = ixgbe_request_msix_irqs(adapter);
2717 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2718 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2719 netdev->name, adapter);
2720 else
2721 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2722 netdev->name, adapter);
2723
2724 if (err)
2725 e_err(probe, "request_irq failed, Error %d\n", err);
2726
2727 return err;
2728 }
2729
2730 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2731 {
2732 int vector;
2733
2734 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2735 free_irq(adapter->pdev->irq, adapter);
2736 return;
2737 }
2738
2739 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2740 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2741 struct msix_entry *entry = &adapter->msix_entries[vector];
2742
2743 /* free only the irqs that were actually requested */
2744 if (!q_vector->rx.ring && !q_vector->tx.ring)
2745 continue;
2746
2747 /* clear the affinity_mask in the IRQ descriptor */
2748 irq_set_affinity_hint(entry->vector, NULL);
2749
2750 free_irq(entry->vector, q_vector);
2751 }
2752
2753 free_irq(adapter->msix_entries[vector++].vector, adapter);
2754 }
2755
2756 /**
2757 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2758 * @adapter: board private structure
2759 **/
2760 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2761 {
2762 switch (adapter->hw.mac.type) {
2763 case ixgbe_mac_82598EB:
2764 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2765 break;
2766 case ixgbe_mac_82599EB:
2767 case ixgbe_mac_X540:
2768 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2769 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2770 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2771 break;
2772 default:
2773 break;
2774 }
2775 IXGBE_WRITE_FLUSH(&adapter->hw);
2776 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2777 int vector;
2778
2779 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2780 synchronize_irq(adapter->msix_entries[vector].vector);
2781
2782 synchronize_irq(adapter->msix_entries[vector++].vector);
2783 } else {
2784 synchronize_irq(adapter->pdev->irq);
2785 }
2786 }
2787
2788 /**
2789 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2790 *
2791 **/
2792 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2793 {
2794 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2795
2796 ixgbe_write_eitr(q_vector);
2797
2798 ixgbe_set_ivar(adapter, 0, 0, 0);
2799 ixgbe_set_ivar(adapter, 1, 0, 0);
2800
2801 e_info(hw, "Legacy interrupt IVAR setup done\n");
2802 }
2803
2804 /**
2805 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2806 * @adapter: board private structure
2807 * @ring: structure containing ring specific data
2808 *
2809 * Configure the Tx descriptor ring after a reset.
2810 **/
2811 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2812 struct ixgbe_ring *ring)
2813 {
2814 struct ixgbe_hw *hw = &adapter->hw;
2815 u64 tdba = ring->dma;
2816 int wait_loop = 10;
2817 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2818 u8 reg_idx = ring->reg_idx;
2819
2820 /* disable queue to avoid issues while updating state */
2821 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2822 IXGBE_WRITE_FLUSH(hw);
2823
2824 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2825 (tdba & DMA_BIT_MASK(32)));
2826 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2827 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2828 ring->count * sizeof(union ixgbe_adv_tx_desc));
2829 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2830 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2831 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2832
2833 /*
2834 * set WTHRESH to encourage burst writeback, it should not be set
2835 * higher than 1 when:
2836 * - ITR is 0 as it could cause false TX hangs
2837 * - ITR is set to > 100k int/sec and BQL is enabled
2838 *
2839 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2840 * to or less than the number of on chip descriptors, which is
2841 * currently 40.
2842 */
2843 #if IS_ENABLED(CONFIG_BQL)
2844 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
2845 #else
2846 if (!ring->q_vector || (ring->q_vector->itr < 8))
2847 #endif
2848 txdctl |= (1 << 16); /* WTHRESH = 1 */
2849 else
2850 txdctl |= (8 << 16); /* WTHRESH = 8 */
2851
2852 /*
2853 * Setting PTHRESH to 32 both improves performance
2854 * and avoids a TX hang with DFP enabled
2855 */
2856 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2857 32; /* PTHRESH = 32 */
2858
2859 /* reinitialize flowdirector state */
2860 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2861 ring->atr_sample_rate = adapter->atr_sample_rate;
2862 ring->atr_count = 0;
2863 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2864 } else {
2865 ring->atr_sample_rate = 0;
2866 }
2867
2868 /* initialize XPS */
2869 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
2870 struct ixgbe_q_vector *q_vector = ring->q_vector;
2871
2872 if (q_vector)
2873 netif_set_xps_queue(adapter->netdev,
2874 &q_vector->affinity_mask,
2875 ring->queue_index);
2876 }
2877
2878 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2879
2880 /* enable queue */
2881 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2882
2883 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2884 if (hw->mac.type == ixgbe_mac_82598EB &&
2885 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2886 return;
2887
2888 /* poll to verify queue is enabled */
2889 do {
2890 usleep_range(1000, 2000);
2891 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2892 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2893 if (!wait_loop)
2894 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2895 }
2896
2897 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2898 {
2899 struct ixgbe_hw *hw = &adapter->hw;
2900 u32 rttdcs, mtqc;
2901 u8 tcs = netdev_get_num_tc(adapter->netdev);
2902
2903 if (hw->mac.type == ixgbe_mac_82598EB)
2904 return;
2905
2906 /* disable the arbiter while setting MTQC */
2907 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2908 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2909 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2910
2911 /* set transmit pool layout */
2912 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2913 mtqc = IXGBE_MTQC_VT_ENA;
2914 if (tcs > 4)
2915 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2916 else if (tcs > 1)
2917 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2918 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2919 mtqc |= IXGBE_MTQC_32VF;
2920 else
2921 mtqc |= IXGBE_MTQC_64VF;
2922 } else {
2923 if (tcs > 4)
2924 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2925 else if (tcs > 1)
2926 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2927 else
2928 mtqc = IXGBE_MTQC_64Q_1PB;
2929 }
2930
2931 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
2932
2933 /* Enable Security TX Buffer IFG for multiple pb */
2934 if (tcs) {
2935 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2936 sectx |= IXGBE_SECTX_DCB;
2937 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
2938 }
2939
2940 /* re-enable the arbiter */
2941 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2942 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2943 }
2944
2945 /**
2946 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2947 * @adapter: board private structure
2948 *
2949 * Configure the Tx unit of the MAC after a reset.
2950 **/
2951 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2952 {
2953 struct ixgbe_hw *hw = &adapter->hw;
2954 u32 dmatxctl;
2955 u32 i;
2956
2957 ixgbe_setup_mtqc(adapter);
2958
2959 if (hw->mac.type != ixgbe_mac_82598EB) {
2960 /* DMATXCTL.EN must be before Tx queues are enabled */
2961 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2962 dmatxctl |= IXGBE_DMATXCTL_TE;
2963 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2964 }
2965
2966 /* Setup the HW Tx Head and Tail descriptor pointers */
2967 for (i = 0; i < adapter->num_tx_queues; i++)
2968 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2969 }
2970
2971 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2972 struct ixgbe_ring *ring)
2973 {
2974 struct ixgbe_hw *hw = &adapter->hw;
2975 u8 reg_idx = ring->reg_idx;
2976 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2977
2978 srrctl |= IXGBE_SRRCTL_DROP_EN;
2979
2980 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2981 }
2982
2983 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2984 struct ixgbe_ring *ring)
2985 {
2986 struct ixgbe_hw *hw = &adapter->hw;
2987 u8 reg_idx = ring->reg_idx;
2988 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2989
2990 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2991
2992 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2993 }
2994
2995 #ifdef CONFIG_IXGBE_DCB
2996 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2997 #else
2998 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2999 #endif
3000 {
3001 int i;
3002 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3003
3004 if (adapter->ixgbe_ieee_pfc)
3005 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3006
3007 /*
3008 * We should set the drop enable bit if:
3009 * SR-IOV is enabled
3010 * or
3011 * Number of Rx queues > 1 and flow control is disabled
3012 *
3013 * This allows us to avoid head of line blocking for security
3014 * and performance reasons.
3015 */
3016 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3017 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3018 for (i = 0; i < adapter->num_rx_queues; i++)
3019 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3020 } else {
3021 for (i = 0; i < adapter->num_rx_queues; i++)
3022 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3023 }
3024 }
3025
3026 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3027
3028 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3029 struct ixgbe_ring *rx_ring)
3030 {
3031 struct ixgbe_hw *hw = &adapter->hw;
3032 u32 srrctl;
3033 u8 reg_idx = rx_ring->reg_idx;
3034
3035 if (hw->mac.type == ixgbe_mac_82598EB) {
3036 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3037
3038 /*
3039 * if VMDq is not active we must program one srrctl register
3040 * per RSS queue since we have enabled RDRXCTL.MVMEN
3041 */
3042 reg_idx &= mask;
3043 }
3044
3045 /* configure header buffer length, needed for RSC */
3046 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3047
3048 /* configure the packet buffer length */
3049 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3050
3051 /* configure descriptor type */
3052 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3053
3054 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3055 }
3056
3057 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3058 {
3059 struct ixgbe_hw *hw = &adapter->hw;
3060 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
3061 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3062 0x6A3E67EA, 0x14364D17, 0x3BED200D};
3063 u32 mrqc = 0, reta = 0;
3064 u32 rxcsum;
3065 int i, j;
3066 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3067
3068 /*
3069 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3070 * make full use of any rings they may have. We will use the
3071 * PSRTYPE register to control how many rings we use within the PF.
3072 */
3073 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3074 rss_i = 2;
3075
3076 /* Fill out hash function seeds */
3077 for (i = 0; i < 10; i++)
3078 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3079
3080 /* Fill out redirection table */
3081 for (i = 0, j = 0; i < 128; i++, j++) {
3082 if (j == rss_i)
3083 j = 0;
3084 /* reta = 4-byte sliding window of
3085 * 0x00..(indices-1)(indices-1)00..etc. */
3086 reta = (reta << 8) | (j * 0x11);
3087 if ((i & 3) == 3)
3088 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3089 }
3090
3091 /* Disable indicating checksum in descriptor, enables RSS hash */
3092 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3093 rxcsum |= IXGBE_RXCSUM_PCSD;
3094 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3095
3096 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3097 if (adapter->ring_feature[RING_F_RSS].mask)
3098 mrqc = IXGBE_MRQC_RSSEN;
3099 } else {
3100 u8 tcs = netdev_get_num_tc(adapter->netdev);
3101
3102 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3103 if (tcs > 4)
3104 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3105 else if (tcs > 1)
3106 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3107 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3108 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3109 else
3110 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3111 } else {
3112 if (tcs > 4)
3113 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3114 else if (tcs > 1)
3115 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3116 else
3117 mrqc = IXGBE_MRQC_RSSEN;
3118 }
3119 }
3120
3121 /* Perform hash on these packet types */
3122 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3123 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3124 IXGBE_MRQC_RSS_FIELD_IPV6 |
3125 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3126
3127 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3128 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3129 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3130 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3131
3132 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3133 }
3134
3135 /**
3136 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3137 * @adapter: address of board private structure
3138 * @index: index of ring to set
3139 **/
3140 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3141 struct ixgbe_ring *ring)
3142 {
3143 struct ixgbe_hw *hw = &adapter->hw;
3144 u32 rscctrl;
3145 u8 reg_idx = ring->reg_idx;
3146
3147 if (!ring_is_rsc_enabled(ring))
3148 return;
3149
3150 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3151 rscctrl |= IXGBE_RSCCTL_RSCEN;
3152 /*
3153 * we must limit the number of descriptors so that the
3154 * total size of max desc * buf_len is not greater
3155 * than 65536
3156 */
3157 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3158 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3159 }
3160
3161 #define IXGBE_MAX_RX_DESC_POLL 10
3162 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3163 struct ixgbe_ring *ring)
3164 {
3165 struct ixgbe_hw *hw = &adapter->hw;
3166 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3167 u32 rxdctl;
3168 u8 reg_idx = ring->reg_idx;
3169
3170 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3171 if (hw->mac.type == ixgbe_mac_82598EB &&
3172 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3173 return;
3174
3175 do {
3176 usleep_range(1000, 2000);
3177 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3178 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3179
3180 if (!wait_loop) {
3181 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3182 "the polling period\n", reg_idx);
3183 }
3184 }
3185
3186 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3187 struct ixgbe_ring *ring)
3188 {
3189 struct ixgbe_hw *hw = &adapter->hw;
3190 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3191 u32 rxdctl;
3192 u8 reg_idx = ring->reg_idx;
3193
3194 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3195 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3196
3197 /* write value back with RXDCTL.ENABLE bit cleared */
3198 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3199
3200 if (hw->mac.type == ixgbe_mac_82598EB &&
3201 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3202 return;
3203
3204 /* the hardware may take up to 100us to really disable the rx queue */
3205 do {
3206 udelay(10);
3207 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3208 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3209
3210 if (!wait_loop) {
3211 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3212 "the polling period\n", reg_idx);
3213 }
3214 }
3215
3216 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3217 struct ixgbe_ring *ring)
3218 {
3219 struct ixgbe_hw *hw = &adapter->hw;
3220 u64 rdba = ring->dma;
3221 u32 rxdctl;
3222 u8 reg_idx = ring->reg_idx;
3223
3224 /* disable queue to avoid issues while updating state */
3225 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3226 ixgbe_disable_rx_queue(adapter, ring);
3227
3228 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3229 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3230 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3231 ring->count * sizeof(union ixgbe_adv_rx_desc));
3232 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3233 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3234 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3235
3236 ixgbe_configure_srrctl(adapter, ring);
3237 ixgbe_configure_rscctl(adapter, ring);
3238
3239 if (hw->mac.type == ixgbe_mac_82598EB) {
3240 /*
3241 * enable cache line friendly hardware writes:
3242 * PTHRESH=32 descriptors (half the internal cache),
3243 * this also removes ugly rx_no_buffer_count increment
3244 * HTHRESH=4 descriptors (to minimize latency on fetch)
3245 * WTHRESH=8 burst writeback up to two cache lines
3246 */
3247 rxdctl &= ~0x3FFFFF;
3248 rxdctl |= 0x080420;
3249 }
3250
3251 /* enable receive descriptor ring */
3252 rxdctl |= IXGBE_RXDCTL_ENABLE;
3253 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3254
3255 ixgbe_rx_desc_queue_enable(adapter, ring);
3256 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3257 }
3258
3259 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3260 {
3261 struct ixgbe_hw *hw = &adapter->hw;
3262 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3263 int p;
3264
3265 /* PSRTYPE must be initialized in non 82598 adapters */
3266 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3267 IXGBE_PSRTYPE_UDPHDR |
3268 IXGBE_PSRTYPE_IPV4HDR |
3269 IXGBE_PSRTYPE_L2HDR |
3270 IXGBE_PSRTYPE_IPV6HDR;
3271
3272 if (hw->mac.type == ixgbe_mac_82598EB)
3273 return;
3274
3275 if (rss_i > 3)
3276 psrtype |= 2 << 29;
3277 else if (rss_i > 1)
3278 psrtype |= 1 << 29;
3279
3280 for (p = 0; p < adapter->num_rx_pools; p++)
3281 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
3282 psrtype);
3283 }
3284
3285 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3286 {
3287 struct ixgbe_hw *hw = &adapter->hw;
3288 u32 reg_offset, vf_shift;
3289 u32 gcr_ext, vmdctl;
3290 int i;
3291
3292 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3293 return;
3294
3295 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3296 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3297 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3298 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3299 vmdctl |= IXGBE_VT_CTL_REPLEN;
3300 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3301
3302 vf_shift = VMDQ_P(0) % 32;
3303 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3304
3305 /* Enable only the PF's pool for Tx/Rx */
3306 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3307 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3308 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3309 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3310 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3311 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3312
3313 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3314 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3315
3316 /*
3317 * Set up VF register offsets for selected VT Mode,
3318 * i.e. 32 or 64 VFs for SR-IOV
3319 */
3320 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3321 case IXGBE_82599_VMDQ_8Q_MASK:
3322 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3323 break;
3324 case IXGBE_82599_VMDQ_4Q_MASK:
3325 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3326 break;
3327 default:
3328 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3329 break;
3330 }
3331
3332 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3333
3334
3335 /* Enable MAC Anti-Spoofing */
3336 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3337 adapter->num_vfs);
3338 /* For VFs that have spoof checking turned off */
3339 for (i = 0; i < adapter->num_vfs; i++) {
3340 if (!adapter->vfinfo[i].spoofchk_enabled)
3341 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3342 }
3343 }
3344
3345 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3346 {
3347 struct ixgbe_hw *hw = &adapter->hw;
3348 struct net_device *netdev = adapter->netdev;
3349 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3350 struct ixgbe_ring *rx_ring;
3351 int i;
3352 u32 mhadd, hlreg0;
3353
3354 #ifdef IXGBE_FCOE
3355 /* adjust max frame to be able to do baby jumbo for FCoE */
3356 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3357 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3358 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3359
3360 #endif /* IXGBE_FCOE */
3361
3362 /* adjust max frame to be at least the size of a standard frame */
3363 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3364 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3365
3366 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3367 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3368 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3369 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3370
3371 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3372 }
3373
3374 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3375 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3376 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3377 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3378
3379 /*
3380 * Setup the HW Rx Head and Tail Descriptor Pointers and
3381 * the Base and Length of the Rx Descriptor Ring
3382 */
3383 for (i = 0; i < adapter->num_rx_queues; i++) {
3384 rx_ring = adapter->rx_ring[i];
3385 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3386 set_ring_rsc_enabled(rx_ring);
3387 else
3388 clear_ring_rsc_enabled(rx_ring);
3389 }
3390 }
3391
3392 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3393 {
3394 struct ixgbe_hw *hw = &adapter->hw;
3395 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3396
3397 switch (hw->mac.type) {
3398 case ixgbe_mac_82598EB:
3399 /*
3400 * For VMDq support of different descriptor types or
3401 * buffer sizes through the use of multiple SRRCTL
3402 * registers, RDRXCTL.MVMEN must be set to 1
3403 *
3404 * also, the manual doesn't mention it clearly but DCA hints
3405 * will only use queue 0's tags unless this bit is set. Side
3406 * effects of setting this bit are only that SRRCTL must be
3407 * fully programmed [0..15]
3408 */
3409 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3410 break;
3411 case ixgbe_mac_82599EB:
3412 case ixgbe_mac_X540:
3413 /* Disable RSC for ACK packets */
3414 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3415 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3416 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3417 /* hardware requires some bits to be set by default */
3418 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3419 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3420 break;
3421 default:
3422 /* We should do nothing since we don't know this hardware */
3423 return;
3424 }
3425
3426 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3427 }
3428
3429 /**
3430 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3431 * @adapter: board private structure
3432 *
3433 * Configure the Rx unit of the MAC after a reset.
3434 **/
3435 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3436 {
3437 struct ixgbe_hw *hw = &adapter->hw;
3438 int i;
3439 u32 rxctrl;
3440
3441 /* disable receives while setting up the descriptors */
3442 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3443 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3444
3445 ixgbe_setup_psrtype(adapter);
3446 ixgbe_setup_rdrxctl(adapter);
3447
3448 /* Program registers for the distribution of queues */
3449 ixgbe_setup_mrqc(adapter);
3450
3451 /* set_rx_buffer_len must be called before ring initialization */
3452 ixgbe_set_rx_buffer_len(adapter);
3453
3454 /*
3455 * Setup the HW Rx Head and Tail Descriptor Pointers and
3456 * the Base and Length of the Rx Descriptor Ring
3457 */
3458 for (i = 0; i < adapter->num_rx_queues; i++)
3459 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3460
3461 /* disable drop enable for 82598 parts */
3462 if (hw->mac.type == ixgbe_mac_82598EB)
3463 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3464
3465 /* enable all receives */
3466 rxctrl |= IXGBE_RXCTRL_RXEN;
3467 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3468 }
3469
3470 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3471 {
3472 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3473 struct ixgbe_hw *hw = &adapter->hw;
3474
3475 /* add VID to filter table */
3476 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3477 set_bit(vid, adapter->active_vlans);
3478
3479 return 0;
3480 }
3481
3482 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3483 {
3484 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3485 struct ixgbe_hw *hw = &adapter->hw;
3486
3487 /* remove VID from filter table */
3488 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3489 clear_bit(vid, adapter->active_vlans);
3490
3491 return 0;
3492 }
3493
3494 /**
3495 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3496 * @adapter: driver data
3497 */
3498 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3499 {
3500 struct ixgbe_hw *hw = &adapter->hw;
3501 u32 vlnctrl;
3502
3503 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3504 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3505 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3506 }
3507
3508 /**
3509 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3510 * @adapter: driver data
3511 */
3512 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3513 {
3514 struct ixgbe_hw *hw = &adapter->hw;
3515 u32 vlnctrl;
3516
3517 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3518 vlnctrl |= IXGBE_VLNCTRL_VFE;
3519 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3520 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3521 }
3522
3523 /**
3524 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3525 * @adapter: driver data
3526 */
3527 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3528 {
3529 struct ixgbe_hw *hw = &adapter->hw;
3530 u32 vlnctrl;
3531 int i, j;
3532
3533 switch (hw->mac.type) {
3534 case ixgbe_mac_82598EB:
3535 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3536 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3537 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3538 break;
3539 case ixgbe_mac_82599EB:
3540 case ixgbe_mac_X540:
3541 for (i = 0; i < adapter->num_rx_queues; i++) {
3542 j = adapter->rx_ring[i]->reg_idx;
3543 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3544 vlnctrl &= ~IXGBE_RXDCTL_VME;
3545 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3546 }
3547 break;
3548 default:
3549 break;
3550 }
3551 }
3552
3553 /**
3554 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3555 * @adapter: driver data
3556 */
3557 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3558 {
3559 struct ixgbe_hw *hw = &adapter->hw;
3560 u32 vlnctrl;
3561 int i, j;
3562
3563 switch (hw->mac.type) {
3564 case ixgbe_mac_82598EB:
3565 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3566 vlnctrl |= IXGBE_VLNCTRL_VME;
3567 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3568 break;
3569 case ixgbe_mac_82599EB:
3570 case ixgbe_mac_X540:
3571 for (i = 0; i < adapter->num_rx_queues; i++) {
3572 j = adapter->rx_ring[i]->reg_idx;
3573 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3574 vlnctrl |= IXGBE_RXDCTL_VME;
3575 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3576 }
3577 break;
3578 default:
3579 break;
3580 }
3581 }
3582
3583 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3584 {
3585 u16 vid;
3586
3587 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3588
3589 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3590 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3591 }
3592
3593 /**
3594 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3595 * @netdev: network interface device structure
3596 *
3597 * Writes unicast address list to the RAR table.
3598 * Returns: -ENOMEM on failure/insufficient address space
3599 * 0 on no addresses written
3600 * X on writing X addresses to the RAR table
3601 **/
3602 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3603 {
3604 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3605 struct ixgbe_hw *hw = &adapter->hw;
3606 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
3607 int count = 0;
3608
3609 /* In SR-IOV mode significantly less RAR entries are available */
3610 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3611 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3612
3613 /* return ENOMEM indicating insufficient memory for addresses */
3614 if (netdev_uc_count(netdev) > rar_entries)
3615 return -ENOMEM;
3616
3617 if (!netdev_uc_empty(netdev)) {
3618 struct netdev_hw_addr *ha;
3619 /* return error if we do not support writing to RAR table */
3620 if (!hw->mac.ops.set_rar)
3621 return -ENOMEM;
3622
3623 netdev_for_each_uc_addr(ha, netdev) {
3624 if (!rar_entries)
3625 break;
3626 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3627 VMDQ_P(0), IXGBE_RAH_AV);
3628 count++;
3629 }
3630 }
3631 /* write the addresses in reverse order to avoid write combining */
3632 for (; rar_entries > 0 ; rar_entries--)
3633 hw->mac.ops.clear_rar(hw, rar_entries);
3634
3635 return count;
3636 }
3637
3638 /**
3639 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3640 * @netdev: network interface device structure
3641 *
3642 * The set_rx_method entry point is called whenever the unicast/multicast
3643 * address list or the network interface flags are updated. This routine is
3644 * responsible for configuring the hardware for proper unicast, multicast and
3645 * promiscuous mode.
3646 **/
3647 void ixgbe_set_rx_mode(struct net_device *netdev)
3648 {
3649 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3650 struct ixgbe_hw *hw = &adapter->hw;
3651 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3652 int count;
3653
3654 /* Check for Promiscuous and All Multicast modes */
3655
3656 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3657
3658 /* set all bits that we expect to always be set */
3659 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3660 fctrl |= IXGBE_FCTRL_BAM;
3661 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3662 fctrl |= IXGBE_FCTRL_PMCF;
3663
3664 /* clear the bits we are changing the status of */
3665 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3666
3667 if (netdev->flags & IFF_PROMISC) {
3668 hw->addr_ctrl.user_set_promisc = true;
3669 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3670 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3671 /* don't hardware filter vlans in promisc mode */
3672 ixgbe_vlan_filter_disable(adapter);
3673 } else {
3674 if (netdev->flags & IFF_ALLMULTI) {
3675 fctrl |= IXGBE_FCTRL_MPE;
3676 vmolr |= IXGBE_VMOLR_MPE;
3677 } else {
3678 /*
3679 * Write addresses to the MTA, if the attempt fails
3680 * then we should just turn on promiscuous mode so
3681 * that we can at least receive multicast traffic
3682 */
3683 hw->mac.ops.update_mc_addr_list(hw, netdev);
3684 vmolr |= IXGBE_VMOLR_ROMPE;
3685 }
3686 ixgbe_vlan_filter_enable(adapter);
3687 hw->addr_ctrl.user_set_promisc = false;
3688 }
3689
3690 /*
3691 * Write addresses to available RAR registers, if there is not
3692 * sufficient space to store all the addresses then enable
3693 * unicast promiscuous mode
3694 */
3695 count = ixgbe_write_uc_addr_list(netdev);
3696 if (count < 0) {
3697 fctrl |= IXGBE_FCTRL_UPE;
3698 vmolr |= IXGBE_VMOLR_ROPE;
3699 }
3700
3701 if (adapter->num_vfs)
3702 ixgbe_restore_vf_multicasts(adapter);
3703
3704 if (hw->mac.type != ixgbe_mac_82598EB) {
3705 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
3706 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3707 IXGBE_VMOLR_ROPE);
3708 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
3709 }
3710
3711 /* This is useful for sniffing bad packets. */
3712 if (adapter->netdev->features & NETIF_F_RXALL) {
3713 /* UPE and MPE will be handled by normal PROMISC logic
3714 * in e1000e_set_rx_mode */
3715 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3716 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3717 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3718
3719 fctrl &= ~(IXGBE_FCTRL_DPF);
3720 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3721 }
3722
3723 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3724
3725 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3726 ixgbe_vlan_strip_enable(adapter);
3727 else
3728 ixgbe_vlan_strip_disable(adapter);
3729 }
3730
3731 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3732 {
3733 int q_idx;
3734
3735 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3736 napi_enable(&adapter->q_vector[q_idx]->napi);
3737 }
3738
3739 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3740 {
3741 int q_idx;
3742
3743 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3744 napi_disable(&adapter->q_vector[q_idx]->napi);
3745 }
3746
3747 #ifdef CONFIG_IXGBE_DCB
3748 /**
3749 * ixgbe_configure_dcb - Configure DCB hardware
3750 * @adapter: ixgbe adapter struct
3751 *
3752 * This is called by the driver on open to configure the DCB hardware.
3753 * This is also called by the gennetlink interface when reconfiguring
3754 * the DCB state.
3755 */
3756 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3757 {
3758 struct ixgbe_hw *hw = &adapter->hw;
3759 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3760
3761 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3762 if (hw->mac.type == ixgbe_mac_82598EB)
3763 netif_set_gso_max_size(adapter->netdev, 65536);
3764 return;
3765 }
3766
3767 if (hw->mac.type == ixgbe_mac_82598EB)
3768 netif_set_gso_max_size(adapter->netdev, 32768);
3769
3770 #ifdef IXGBE_FCOE
3771 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3772 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3773 #endif
3774
3775 /* reconfigure the hardware */
3776 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3777 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3778 DCB_TX_CONFIG);
3779 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3780 DCB_RX_CONFIG);
3781 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3782 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3783 ixgbe_dcb_hw_ets(&adapter->hw,
3784 adapter->ixgbe_ieee_ets,
3785 max_frame);
3786 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3787 adapter->ixgbe_ieee_pfc->pfc_en,
3788 adapter->ixgbe_ieee_ets->prio_tc);
3789 }
3790
3791 /* Enable RSS Hash per TC */
3792 if (hw->mac.type != ixgbe_mac_82598EB) {
3793 u32 msb = 0;
3794 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
3795
3796 while (rss_i) {
3797 msb++;
3798 rss_i >>= 1;
3799 }
3800
3801 /* write msb to all 8 TCs in one write */
3802 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
3803 }
3804 }
3805 #endif
3806
3807 /* Additional bittime to account for IXGBE framing */
3808 #define IXGBE_ETH_FRAMING 20
3809
3810 /**
3811 * ixgbe_hpbthresh - calculate high water mark for flow control
3812 *
3813 * @adapter: board private structure to calculate for
3814 * @pb: packet buffer to calculate
3815 */
3816 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3817 {
3818 struct ixgbe_hw *hw = &adapter->hw;
3819 struct net_device *dev = adapter->netdev;
3820 int link, tc, kb, marker;
3821 u32 dv_id, rx_pba;
3822
3823 /* Calculate max LAN frame size */
3824 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3825
3826 #ifdef IXGBE_FCOE
3827 /* FCoE traffic class uses FCOE jumbo frames */
3828 if ((dev->features & NETIF_F_FCOE_MTU) &&
3829 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3830 (pb == ixgbe_fcoe_get_tc(adapter)))
3831 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3832
3833 #endif
3834 /* Calculate delay value for device */
3835 switch (hw->mac.type) {
3836 case ixgbe_mac_X540:
3837 dv_id = IXGBE_DV_X540(link, tc);
3838 break;
3839 default:
3840 dv_id = IXGBE_DV(link, tc);
3841 break;
3842 }
3843
3844 /* Loopback switch introduces additional latency */
3845 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3846 dv_id += IXGBE_B2BT(tc);
3847
3848 /* Delay value is calculated in bit times convert to KB */
3849 kb = IXGBE_BT2KB(dv_id);
3850 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3851
3852 marker = rx_pba - kb;
3853
3854 /* It is possible that the packet buffer is not large enough
3855 * to provide required headroom. In this case throw an error
3856 * to user and a do the best we can.
3857 */
3858 if (marker < 0) {
3859 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3860 "headroom to support flow control."
3861 "Decrease MTU or number of traffic classes\n", pb);
3862 marker = tc + 1;
3863 }
3864
3865 return marker;
3866 }
3867
3868 /**
3869 * ixgbe_lpbthresh - calculate low water mark for for flow control
3870 *
3871 * @adapter: board private structure to calculate for
3872 * @pb: packet buffer to calculate
3873 */
3874 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3875 {
3876 struct ixgbe_hw *hw = &adapter->hw;
3877 struct net_device *dev = adapter->netdev;
3878 int tc;
3879 u32 dv_id;
3880
3881 /* Calculate max LAN frame size */
3882 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3883
3884 /* Calculate delay value for device */
3885 switch (hw->mac.type) {
3886 case ixgbe_mac_X540:
3887 dv_id = IXGBE_LOW_DV_X540(tc);
3888 break;
3889 default:
3890 dv_id = IXGBE_LOW_DV(tc);
3891 break;
3892 }
3893
3894 /* Delay value is calculated in bit times convert to KB */
3895 return IXGBE_BT2KB(dv_id);
3896 }
3897
3898 /*
3899 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3900 */
3901 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3902 {
3903 struct ixgbe_hw *hw = &adapter->hw;
3904 int num_tc = netdev_get_num_tc(adapter->netdev);
3905 int i;
3906
3907 if (!num_tc)
3908 num_tc = 1;
3909
3910 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3911
3912 for (i = 0; i < num_tc; i++) {
3913 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3914
3915 /* Low water marks must not be larger than high water marks */
3916 if (hw->fc.low_water > hw->fc.high_water[i])
3917 hw->fc.low_water = 0;
3918 }
3919 }
3920
3921 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3922 {
3923 struct ixgbe_hw *hw = &adapter->hw;
3924 int hdrm;
3925 u8 tc = netdev_get_num_tc(adapter->netdev);
3926
3927 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3928 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3929 hdrm = 32 << adapter->fdir_pballoc;
3930 else
3931 hdrm = 0;
3932
3933 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3934 ixgbe_pbthresh_setup(adapter);
3935 }
3936
3937 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3938 {
3939 struct ixgbe_hw *hw = &adapter->hw;
3940 struct hlist_node *node2;
3941 struct ixgbe_fdir_filter *filter;
3942
3943 spin_lock(&adapter->fdir_perfect_lock);
3944
3945 if (!hlist_empty(&adapter->fdir_filter_list))
3946 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3947
3948 hlist_for_each_entry_safe(filter, node2,
3949 &adapter->fdir_filter_list, fdir_node) {
3950 ixgbe_fdir_write_perfect_filter_82599(hw,
3951 &filter->filter,
3952 filter->sw_idx,
3953 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3954 IXGBE_FDIR_DROP_QUEUE :
3955 adapter->rx_ring[filter->action]->reg_idx);
3956 }
3957
3958 spin_unlock(&adapter->fdir_perfect_lock);
3959 }
3960
3961 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3962 {
3963 struct ixgbe_hw *hw = &adapter->hw;
3964
3965 ixgbe_configure_pb(adapter);
3966 #ifdef CONFIG_IXGBE_DCB
3967 ixgbe_configure_dcb(adapter);
3968 #endif
3969 /*
3970 * We must restore virtualization before VLANs or else
3971 * the VLVF registers will not be populated
3972 */
3973 ixgbe_configure_virtualization(adapter);
3974
3975 ixgbe_set_rx_mode(adapter->netdev);
3976 ixgbe_restore_vlan(adapter);
3977
3978 switch (hw->mac.type) {
3979 case ixgbe_mac_82599EB:
3980 case ixgbe_mac_X540:
3981 hw->mac.ops.disable_rx_buff(hw);
3982 break;
3983 default:
3984 break;
3985 }
3986
3987 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3988 ixgbe_init_fdir_signature_82599(&adapter->hw,
3989 adapter->fdir_pballoc);
3990 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3991 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3992 adapter->fdir_pballoc);
3993 ixgbe_fdir_filter_restore(adapter);
3994 }
3995
3996 switch (hw->mac.type) {
3997 case ixgbe_mac_82599EB:
3998 case ixgbe_mac_X540:
3999 hw->mac.ops.enable_rx_buff(hw);
4000 break;
4001 default:
4002 break;
4003 }
4004
4005 #ifdef IXGBE_FCOE
4006 /* configure FCoE L2 filters, redirection table, and Rx control */
4007 ixgbe_configure_fcoe(adapter);
4008
4009 #endif /* IXGBE_FCOE */
4010 ixgbe_configure_tx(adapter);
4011 ixgbe_configure_rx(adapter);
4012 }
4013
4014 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4015 {
4016 switch (hw->phy.type) {
4017 case ixgbe_phy_sfp_avago:
4018 case ixgbe_phy_sfp_ftl:
4019 case ixgbe_phy_sfp_intel:
4020 case ixgbe_phy_sfp_unknown:
4021 case ixgbe_phy_sfp_passive_tyco:
4022 case ixgbe_phy_sfp_passive_unknown:
4023 case ixgbe_phy_sfp_active_unknown:
4024 case ixgbe_phy_sfp_ftl_active:
4025 return true;
4026 case ixgbe_phy_nl:
4027 if (hw->mac.type == ixgbe_mac_82598EB)
4028 return true;
4029 default:
4030 return false;
4031 }
4032 }
4033
4034 /**
4035 * ixgbe_sfp_link_config - set up SFP+ link
4036 * @adapter: pointer to private adapter struct
4037 **/
4038 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4039 {
4040 /*
4041 * We are assuming the worst case scenario here, and that
4042 * is that an SFP was inserted/removed after the reset
4043 * but before SFP detection was enabled. As such the best
4044 * solution is to just start searching as soon as we start
4045 */
4046 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4047 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4048
4049 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4050 }
4051
4052 /**
4053 * ixgbe_non_sfp_link_config - set up non-SFP+ link
4054 * @hw: pointer to private hardware struct
4055 *
4056 * Returns 0 on success, negative on failure
4057 **/
4058 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4059 {
4060 u32 speed;
4061 bool autoneg, link_up = false;
4062 u32 ret = IXGBE_ERR_LINK_SETUP;
4063
4064 if (hw->mac.ops.check_link)
4065 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
4066
4067 if (ret)
4068 goto link_cfg_out;
4069
4070 speed = hw->phy.autoneg_advertised;
4071 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4072 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4073 &autoneg);
4074 if (ret)
4075 goto link_cfg_out;
4076
4077 if (hw->mac.ops.setup_link)
4078 ret = hw->mac.ops.setup_link(hw, speed, link_up);
4079 link_cfg_out:
4080 return ret;
4081 }
4082
4083 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4084 {
4085 struct ixgbe_hw *hw = &adapter->hw;
4086 u32 gpie = 0;
4087
4088 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4089 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4090 IXGBE_GPIE_OCD;
4091 gpie |= IXGBE_GPIE_EIAME;
4092 /*
4093 * use EIAM to auto-mask when MSI-X interrupt is asserted
4094 * this saves a register write for every interrupt
4095 */
4096 switch (hw->mac.type) {
4097 case ixgbe_mac_82598EB:
4098 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4099 break;
4100 case ixgbe_mac_82599EB:
4101 case ixgbe_mac_X540:
4102 default:
4103 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4104 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4105 break;
4106 }
4107 } else {
4108 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4109 * specifically only auto mask tx and rx interrupts */
4110 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4111 }
4112
4113 /* XXX: to interrupt immediately for EICS writes, enable this */
4114 /* gpie |= IXGBE_GPIE_EIMEN; */
4115
4116 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4117 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4118
4119 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4120 case IXGBE_82599_VMDQ_8Q_MASK:
4121 gpie |= IXGBE_GPIE_VTMODE_16;
4122 break;
4123 case IXGBE_82599_VMDQ_4Q_MASK:
4124 gpie |= IXGBE_GPIE_VTMODE_32;
4125 break;
4126 default:
4127 gpie |= IXGBE_GPIE_VTMODE_64;
4128 break;
4129 }
4130 }
4131
4132 /* Enable Thermal over heat sensor interrupt */
4133 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4134 switch (adapter->hw.mac.type) {
4135 case ixgbe_mac_82599EB:
4136 gpie |= IXGBE_SDP0_GPIEN;
4137 break;
4138 case ixgbe_mac_X540:
4139 gpie |= IXGBE_EIMS_TS;
4140 break;
4141 default:
4142 break;
4143 }
4144 }
4145
4146 /* Enable fan failure interrupt */
4147 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4148 gpie |= IXGBE_SDP1_GPIEN;
4149
4150 if (hw->mac.type == ixgbe_mac_82599EB) {
4151 gpie |= IXGBE_SDP1_GPIEN;
4152 gpie |= IXGBE_SDP2_GPIEN;
4153 }
4154
4155 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4156 }
4157
4158 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4159 {
4160 struct ixgbe_hw *hw = &adapter->hw;
4161 int err;
4162 u32 ctrl_ext;
4163
4164 ixgbe_get_hw_control(adapter);
4165 ixgbe_setup_gpie(adapter);
4166
4167 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4168 ixgbe_configure_msix(adapter);
4169 else
4170 ixgbe_configure_msi_and_legacy(adapter);
4171
4172 /* enable the optics for 82599 SFP+ fiber */
4173 if (hw->mac.ops.enable_tx_laser)
4174 hw->mac.ops.enable_tx_laser(hw);
4175
4176 clear_bit(__IXGBE_DOWN, &adapter->state);
4177 ixgbe_napi_enable_all(adapter);
4178
4179 if (ixgbe_is_sfp(hw)) {
4180 ixgbe_sfp_link_config(adapter);
4181 } else {
4182 err = ixgbe_non_sfp_link_config(hw);
4183 if (err)
4184 e_err(probe, "link_config FAILED %d\n", err);
4185 }
4186
4187 /* clear any pending interrupts, may auto mask */
4188 IXGBE_READ_REG(hw, IXGBE_EICR);
4189 ixgbe_irq_enable(adapter, true, true);
4190
4191 /*
4192 * If this adapter has a fan, check to see if we had a failure
4193 * before we enabled the interrupt.
4194 */
4195 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4196 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4197 if (esdp & IXGBE_ESDP_SDP1)
4198 e_crit(drv, "Fan has stopped, replace the adapter\n");
4199 }
4200
4201 /* enable transmits */
4202 netif_tx_start_all_queues(adapter->netdev);
4203
4204 /* bring the link up in the watchdog, this could race with our first
4205 * link up interrupt but shouldn't be a problem */
4206 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4207 adapter->link_check_timeout = jiffies;
4208 mod_timer(&adapter->service_timer, jiffies);
4209
4210 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4211 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4212 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4213 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4214 }
4215
4216 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4217 {
4218 WARN_ON(in_interrupt());
4219 /* put off any impending NetWatchDogTimeout */
4220 adapter->netdev->trans_start = jiffies;
4221
4222 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4223 usleep_range(1000, 2000);
4224 ixgbe_down(adapter);
4225 /*
4226 * If SR-IOV enabled then wait a bit before bringing the adapter
4227 * back up to give the VFs time to respond to the reset. The
4228 * two second wait is based upon the watchdog timer cycle in
4229 * the VF driver.
4230 */
4231 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4232 msleep(2000);
4233 ixgbe_up(adapter);
4234 clear_bit(__IXGBE_RESETTING, &adapter->state);
4235 }
4236
4237 void ixgbe_up(struct ixgbe_adapter *adapter)
4238 {
4239 /* hardware has been reset, we need to reload some things */
4240 ixgbe_configure(adapter);
4241
4242 ixgbe_up_complete(adapter);
4243 }
4244
4245 void ixgbe_reset(struct ixgbe_adapter *adapter)
4246 {
4247 struct ixgbe_hw *hw = &adapter->hw;
4248 int err;
4249
4250 /* lock SFP init bit to prevent race conditions with the watchdog */
4251 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4252 usleep_range(1000, 2000);
4253
4254 /* clear all SFP and link config related flags while holding SFP_INIT */
4255 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4256 IXGBE_FLAG2_SFP_NEEDS_RESET);
4257 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4258
4259 err = hw->mac.ops.init_hw(hw);
4260 switch (err) {
4261 case 0:
4262 case IXGBE_ERR_SFP_NOT_PRESENT:
4263 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4264 break;
4265 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4266 e_dev_err("master disable timed out\n");
4267 break;
4268 case IXGBE_ERR_EEPROM_VERSION:
4269 /* We are running on a pre-production device, log a warning */
4270 e_dev_warn("This device is a pre-production adapter/LOM. "
4271 "Please be aware there may be issues associated with "
4272 "your hardware. If you are experiencing problems "
4273 "please contact your Intel or hardware "
4274 "representative who provided you with this "
4275 "hardware.\n");
4276 break;
4277 default:
4278 e_dev_err("Hardware Error: %d\n", err);
4279 }
4280
4281 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4282
4283 /* reprogram the RAR[0] in case user changed it. */
4284 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
4285
4286 /* update SAN MAC vmdq pool selection */
4287 if (hw->mac.san_mac_rar_index)
4288 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4289
4290 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
4291 ixgbe_ptp_reset(adapter);
4292 }
4293
4294 /**
4295 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4296 * @rx_ring: ring to free buffers from
4297 **/
4298 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4299 {
4300 struct device *dev = rx_ring->dev;
4301 unsigned long size;
4302 u16 i;
4303
4304 /* ring already cleared, nothing to do */
4305 if (!rx_ring->rx_buffer_info)
4306 return;
4307
4308 /* Free all the Rx ring sk_buffs */
4309 for (i = 0; i < rx_ring->count; i++) {
4310 struct ixgbe_rx_buffer *rx_buffer;
4311
4312 rx_buffer = &rx_ring->rx_buffer_info[i];
4313 if (rx_buffer->skb) {
4314 struct sk_buff *skb = rx_buffer->skb;
4315 if (IXGBE_CB(skb)->page_released) {
4316 dma_unmap_page(dev,
4317 IXGBE_CB(skb)->dma,
4318 ixgbe_rx_bufsz(rx_ring),
4319 DMA_FROM_DEVICE);
4320 IXGBE_CB(skb)->page_released = false;
4321 }
4322 dev_kfree_skb(skb);
4323 }
4324 rx_buffer->skb = NULL;
4325 if (rx_buffer->dma)
4326 dma_unmap_page(dev, rx_buffer->dma,
4327 ixgbe_rx_pg_size(rx_ring),
4328 DMA_FROM_DEVICE);
4329 rx_buffer->dma = 0;
4330 if (rx_buffer->page)
4331 __free_pages(rx_buffer->page,
4332 ixgbe_rx_pg_order(rx_ring));
4333 rx_buffer->page = NULL;
4334 }
4335
4336 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4337 memset(rx_ring->rx_buffer_info, 0, size);
4338
4339 /* Zero out the descriptor ring */
4340 memset(rx_ring->desc, 0, rx_ring->size);
4341
4342 rx_ring->next_to_alloc = 0;
4343 rx_ring->next_to_clean = 0;
4344 rx_ring->next_to_use = 0;
4345 }
4346
4347 /**
4348 * ixgbe_clean_tx_ring - Free Tx Buffers
4349 * @tx_ring: ring to be cleaned
4350 **/
4351 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4352 {
4353 struct ixgbe_tx_buffer *tx_buffer_info;
4354 unsigned long size;
4355 u16 i;
4356
4357 /* ring already cleared, nothing to do */
4358 if (!tx_ring->tx_buffer_info)
4359 return;
4360
4361 /* Free all the Tx ring sk_buffs */
4362 for (i = 0; i < tx_ring->count; i++) {
4363 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4364 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4365 }
4366
4367 netdev_tx_reset_queue(txring_txq(tx_ring));
4368
4369 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4370 memset(tx_ring->tx_buffer_info, 0, size);
4371
4372 /* Zero out the descriptor ring */
4373 memset(tx_ring->desc, 0, tx_ring->size);
4374
4375 tx_ring->next_to_use = 0;
4376 tx_ring->next_to_clean = 0;
4377 }
4378
4379 /**
4380 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4381 * @adapter: board private structure
4382 **/
4383 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4384 {
4385 int i;
4386
4387 for (i = 0; i < adapter->num_rx_queues; i++)
4388 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4389 }
4390
4391 /**
4392 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4393 * @adapter: board private structure
4394 **/
4395 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4396 {
4397 int i;
4398
4399 for (i = 0; i < adapter->num_tx_queues; i++)
4400 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4401 }
4402
4403 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4404 {
4405 struct hlist_node *node2;
4406 struct ixgbe_fdir_filter *filter;
4407
4408 spin_lock(&adapter->fdir_perfect_lock);
4409
4410 hlist_for_each_entry_safe(filter, node2,
4411 &adapter->fdir_filter_list, fdir_node) {
4412 hlist_del(&filter->fdir_node);
4413 kfree(filter);
4414 }
4415 adapter->fdir_filter_count = 0;
4416
4417 spin_unlock(&adapter->fdir_perfect_lock);
4418 }
4419
4420 void ixgbe_down(struct ixgbe_adapter *adapter)
4421 {
4422 struct net_device *netdev = adapter->netdev;
4423 struct ixgbe_hw *hw = &adapter->hw;
4424 u32 rxctrl;
4425 int i;
4426
4427 /* signal that we are down to the interrupt handler */
4428 set_bit(__IXGBE_DOWN, &adapter->state);
4429
4430 /* disable receives */
4431 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4432 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4433
4434 /* disable all enabled rx queues */
4435 for (i = 0; i < adapter->num_rx_queues; i++)
4436 /* this call also flushes the previous write */
4437 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4438
4439 usleep_range(10000, 20000);
4440
4441 netif_tx_stop_all_queues(netdev);
4442
4443 /* call carrier off first to avoid false dev_watchdog timeouts */
4444 netif_carrier_off(netdev);
4445 netif_tx_disable(netdev);
4446
4447 ixgbe_irq_disable(adapter);
4448
4449 ixgbe_napi_disable_all(adapter);
4450
4451 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4452 IXGBE_FLAG2_RESET_REQUESTED);
4453 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4454
4455 del_timer_sync(&adapter->service_timer);
4456
4457 if (adapter->num_vfs) {
4458 /* Clear EITR Select mapping */
4459 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4460
4461 /* Mark all the VFs as inactive */
4462 for (i = 0 ; i < adapter->num_vfs; i++)
4463 adapter->vfinfo[i].clear_to_send = false;
4464
4465 /* ping all the active vfs to let them know we are going down */
4466 ixgbe_ping_all_vfs(adapter);
4467
4468 /* Disable all VFTE/VFRE TX/RX */
4469 ixgbe_disable_tx_rx(adapter);
4470 }
4471
4472 /* disable transmits in the hardware now that interrupts are off */
4473 for (i = 0; i < adapter->num_tx_queues; i++) {
4474 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4475 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4476 }
4477
4478 /* Disable the Tx DMA engine on 82599 and X540 */
4479 switch (hw->mac.type) {
4480 case ixgbe_mac_82599EB:
4481 case ixgbe_mac_X540:
4482 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4483 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4484 ~IXGBE_DMATXCTL_TE));
4485 break;
4486 default:
4487 break;
4488 }
4489
4490 if (!pci_channel_offline(adapter->pdev))
4491 ixgbe_reset(adapter);
4492
4493 /* power down the optics for 82599 SFP+ fiber */
4494 if (hw->mac.ops.disable_tx_laser)
4495 hw->mac.ops.disable_tx_laser(hw);
4496
4497 ixgbe_clean_all_tx_rings(adapter);
4498 ixgbe_clean_all_rx_rings(adapter);
4499
4500 #ifdef CONFIG_IXGBE_DCA
4501 /* since we reset the hardware DCA settings were cleared */
4502 ixgbe_setup_dca(adapter);
4503 #endif
4504 }
4505
4506 /**
4507 * ixgbe_tx_timeout - Respond to a Tx Hang
4508 * @netdev: network interface device structure
4509 **/
4510 static void ixgbe_tx_timeout(struct net_device *netdev)
4511 {
4512 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4513
4514 /* Do the reset outside of interrupt context */
4515 ixgbe_tx_timeout_reset(adapter);
4516 }
4517
4518 /**
4519 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4520 * @adapter: board private structure to initialize
4521 *
4522 * ixgbe_sw_init initializes the Adapter private data structure.
4523 * Fields are initialized based on PCI device information and
4524 * OS network device settings (MTU size).
4525 **/
4526 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
4527 {
4528 struct ixgbe_hw *hw = &adapter->hw;
4529 struct pci_dev *pdev = adapter->pdev;
4530 unsigned int rss, fdir;
4531 u32 fwsm;
4532 #ifdef CONFIG_IXGBE_DCB
4533 int j;
4534 struct tc_configuration *tc;
4535 #endif
4536
4537 /* PCI config space info */
4538
4539 hw->vendor_id = pdev->vendor;
4540 hw->device_id = pdev->device;
4541 hw->revision_id = pdev->revision;
4542 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4543 hw->subsystem_device_id = pdev->subsystem_device;
4544
4545 /* Set common capability flags and settings */
4546 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4547 adapter->ring_feature[RING_F_RSS].limit = rss;
4548 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4549 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4550 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
4551 adapter->atr_sample_rate = 20;
4552 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
4553 adapter->ring_feature[RING_F_FDIR].limit = fdir;
4554 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4555 #ifdef CONFIG_IXGBE_DCA
4556 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
4557 #endif
4558 #ifdef IXGBE_FCOE
4559 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4560 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4561 #ifdef CONFIG_IXGBE_DCB
4562 /* Default traffic class to use for FCoE */
4563 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4564 #endif /* CONFIG_IXGBE_DCB */
4565 #endif /* IXGBE_FCOE */
4566
4567 /* Set MAC specific capability flags and exceptions */
4568 switch (hw->mac.type) {
4569 case ixgbe_mac_82598EB:
4570 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
4571 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
4572
4573 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4574 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4575
4576 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
4577 adapter->ring_feature[RING_F_FDIR].limit = 0;
4578 adapter->atr_sample_rate = 0;
4579 adapter->fdir_pballoc = 0;
4580 #ifdef IXGBE_FCOE
4581 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
4582 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4583 #ifdef CONFIG_IXGBE_DCB
4584 adapter->fcoe.up = 0;
4585 #endif /* IXGBE_DCB */
4586 #endif /* IXGBE_FCOE */
4587 break;
4588 case ixgbe_mac_82599EB:
4589 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4590 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4591 break;
4592 case ixgbe_mac_X540:
4593 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4594 if (fwsm & IXGBE_FWSM_TS_ENABLED)
4595 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4596 break;
4597 default:
4598 break;
4599 }
4600
4601 #ifdef IXGBE_FCOE
4602 /* FCoE support exists, always init the FCoE lock */
4603 spin_lock_init(&adapter->fcoe.lock);
4604
4605 #endif
4606 /* n-tuple support exists, always init our spinlock */
4607 spin_lock_init(&adapter->fdir_perfect_lock);
4608
4609 #ifdef CONFIG_IXGBE_DCB
4610 switch (hw->mac.type) {
4611 case ixgbe_mac_X540:
4612 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4613 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4614 break;
4615 default:
4616 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4617 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4618 break;
4619 }
4620
4621 /* Configure DCB traffic classes */
4622 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4623 tc = &adapter->dcb_cfg.tc_config[j];
4624 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4625 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4626 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4627 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4628 tc->dcb_pfc = pfc_disabled;
4629 }
4630
4631 /* Initialize default user to priority mapping, UPx->TC0 */
4632 tc = &adapter->dcb_cfg.tc_config[0];
4633 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4634 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4635
4636 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4637 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4638 adapter->dcb_cfg.pfc_mode_enable = false;
4639 adapter->dcb_set_bitmap = 0x00;
4640 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4641 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4642 sizeof(adapter->temp_dcb_cfg));
4643
4644 #endif
4645
4646 /* default flow control settings */
4647 hw->fc.requested_mode = ixgbe_fc_full;
4648 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4649 ixgbe_pbthresh_setup(adapter);
4650 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4651 hw->fc.send_xon = true;
4652 hw->fc.disable_fc_autoneg =
4653 (ixgbe_device_supports_autoneg_fc(hw) == 0) ? false : true;
4654
4655 #ifdef CONFIG_PCI_IOV
4656 /* assign number of SR-IOV VFs */
4657 if (hw->mac.type != ixgbe_mac_82598EB)
4658 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4659
4660 #endif
4661 /* enable itr by default in dynamic mode */
4662 adapter->rx_itr_setting = 1;
4663 adapter->tx_itr_setting = 1;
4664
4665 /* set default ring sizes */
4666 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4667 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4668
4669 /* set default work limits */
4670 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4671
4672 /* initialize eeprom parameters */
4673 if (ixgbe_init_eeprom_params_generic(hw)) {
4674 e_dev_err("EEPROM initialization failed\n");
4675 return -EIO;
4676 }
4677
4678 set_bit(__IXGBE_DOWN, &adapter->state);
4679
4680 return 0;
4681 }
4682
4683 /**
4684 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4685 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4686 *
4687 * Return 0 on success, negative on failure
4688 **/
4689 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4690 {
4691 struct device *dev = tx_ring->dev;
4692 int orig_node = dev_to_node(dev);
4693 int numa_node = -1;
4694 int size;
4695
4696 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4697
4698 if (tx_ring->q_vector)
4699 numa_node = tx_ring->q_vector->numa_node;
4700
4701 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4702 if (!tx_ring->tx_buffer_info)
4703 tx_ring->tx_buffer_info = vzalloc(size);
4704 if (!tx_ring->tx_buffer_info)
4705 goto err;
4706
4707 /* round up to nearest 4K */
4708 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4709 tx_ring->size = ALIGN(tx_ring->size, 4096);
4710
4711 set_dev_node(dev, numa_node);
4712 tx_ring->desc = dma_alloc_coherent(dev,
4713 tx_ring->size,
4714 &tx_ring->dma,
4715 GFP_KERNEL);
4716 set_dev_node(dev, orig_node);
4717 if (!tx_ring->desc)
4718 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4719 &tx_ring->dma, GFP_KERNEL);
4720 if (!tx_ring->desc)
4721 goto err;
4722
4723 tx_ring->next_to_use = 0;
4724 tx_ring->next_to_clean = 0;
4725 return 0;
4726
4727 err:
4728 vfree(tx_ring->tx_buffer_info);
4729 tx_ring->tx_buffer_info = NULL;
4730 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4731 return -ENOMEM;
4732 }
4733
4734 /**
4735 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4736 * @adapter: board private structure
4737 *
4738 * If this function returns with an error, then it's possible one or
4739 * more of the rings is populated (while the rest are not). It is the
4740 * callers duty to clean those orphaned rings.
4741 *
4742 * Return 0 on success, negative on failure
4743 **/
4744 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4745 {
4746 int i, err = 0;
4747
4748 for (i = 0; i < adapter->num_tx_queues; i++) {
4749 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4750 if (!err)
4751 continue;
4752
4753 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4754 goto err_setup_tx;
4755 }
4756
4757 return 0;
4758 err_setup_tx:
4759 /* rewind the index freeing the rings as we go */
4760 while (i--)
4761 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4762 return err;
4763 }
4764
4765 /**
4766 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4767 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4768 *
4769 * Returns 0 on success, negative on failure
4770 **/
4771 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4772 {
4773 struct device *dev = rx_ring->dev;
4774 int orig_node = dev_to_node(dev);
4775 int numa_node = -1;
4776 int size;
4777
4778 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4779
4780 if (rx_ring->q_vector)
4781 numa_node = rx_ring->q_vector->numa_node;
4782
4783 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4784 if (!rx_ring->rx_buffer_info)
4785 rx_ring->rx_buffer_info = vzalloc(size);
4786 if (!rx_ring->rx_buffer_info)
4787 goto err;
4788
4789 /* Round up to nearest 4K */
4790 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4791 rx_ring->size = ALIGN(rx_ring->size, 4096);
4792
4793 set_dev_node(dev, numa_node);
4794 rx_ring->desc = dma_alloc_coherent(dev,
4795 rx_ring->size,
4796 &rx_ring->dma,
4797 GFP_KERNEL);
4798 set_dev_node(dev, orig_node);
4799 if (!rx_ring->desc)
4800 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4801 &rx_ring->dma, GFP_KERNEL);
4802 if (!rx_ring->desc)
4803 goto err;
4804
4805 rx_ring->next_to_clean = 0;
4806 rx_ring->next_to_use = 0;
4807
4808 return 0;
4809 err:
4810 vfree(rx_ring->rx_buffer_info);
4811 rx_ring->rx_buffer_info = NULL;
4812 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4813 return -ENOMEM;
4814 }
4815
4816 /**
4817 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4818 * @adapter: board private structure
4819 *
4820 * If this function returns with an error, then it's possible one or
4821 * more of the rings is populated (while the rest are not). It is the
4822 * callers duty to clean those orphaned rings.
4823 *
4824 * Return 0 on success, negative on failure
4825 **/
4826 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4827 {
4828 int i, err = 0;
4829
4830 for (i = 0; i < adapter->num_rx_queues; i++) {
4831 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4832 if (!err)
4833 continue;
4834
4835 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4836 goto err_setup_rx;
4837 }
4838
4839 #ifdef IXGBE_FCOE
4840 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4841 if (!err)
4842 #endif
4843 return 0;
4844 err_setup_rx:
4845 /* rewind the index freeing the rings as we go */
4846 while (i--)
4847 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4848 return err;
4849 }
4850
4851 /**
4852 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4853 * @tx_ring: Tx descriptor ring for a specific queue
4854 *
4855 * Free all transmit software resources
4856 **/
4857 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
4858 {
4859 ixgbe_clean_tx_ring(tx_ring);
4860
4861 vfree(tx_ring->tx_buffer_info);
4862 tx_ring->tx_buffer_info = NULL;
4863
4864 /* if not set, then don't free */
4865 if (!tx_ring->desc)
4866 return;
4867
4868 dma_free_coherent(tx_ring->dev, tx_ring->size,
4869 tx_ring->desc, tx_ring->dma);
4870
4871 tx_ring->desc = NULL;
4872 }
4873
4874 /**
4875 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4876 * @adapter: board private structure
4877 *
4878 * Free all transmit software resources
4879 **/
4880 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4881 {
4882 int i;
4883
4884 for (i = 0; i < adapter->num_tx_queues; i++)
4885 if (adapter->tx_ring[i]->desc)
4886 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4887 }
4888
4889 /**
4890 * ixgbe_free_rx_resources - Free Rx Resources
4891 * @rx_ring: ring to clean the resources from
4892 *
4893 * Free all receive software resources
4894 **/
4895 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
4896 {
4897 ixgbe_clean_rx_ring(rx_ring);
4898
4899 vfree(rx_ring->rx_buffer_info);
4900 rx_ring->rx_buffer_info = NULL;
4901
4902 /* if not set, then don't free */
4903 if (!rx_ring->desc)
4904 return;
4905
4906 dma_free_coherent(rx_ring->dev, rx_ring->size,
4907 rx_ring->desc, rx_ring->dma);
4908
4909 rx_ring->desc = NULL;
4910 }
4911
4912 /**
4913 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4914 * @adapter: board private structure
4915 *
4916 * Free all receive software resources
4917 **/
4918 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4919 {
4920 int i;
4921
4922 #ifdef IXGBE_FCOE
4923 ixgbe_free_fcoe_ddp_resources(adapter);
4924
4925 #endif
4926 for (i = 0; i < adapter->num_rx_queues; i++)
4927 if (adapter->rx_ring[i]->desc)
4928 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4929 }
4930
4931 /**
4932 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4933 * @netdev: network interface device structure
4934 * @new_mtu: new value for maximum frame size
4935 *
4936 * Returns 0 on success, negative on failure
4937 **/
4938 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4939 {
4940 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4941 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4942
4943 /* MTU < 68 is an error and causes problems on some kernels */
4944 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4945 return -EINVAL;
4946
4947 /*
4948 * For 82599EB we cannot allow legacy VFs to enable their receive
4949 * paths when MTU greater than 1500 is configured. So display a
4950 * warning that legacy VFs will be disabled.
4951 */
4952 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4953 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4954 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
4955 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
4956
4957 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
4958
4959 /* must set new MTU before calling down or up */
4960 netdev->mtu = new_mtu;
4961
4962 if (netif_running(netdev))
4963 ixgbe_reinit_locked(adapter);
4964
4965 return 0;
4966 }
4967
4968 /**
4969 * ixgbe_open - Called when a network interface is made active
4970 * @netdev: network interface device structure
4971 *
4972 * Returns 0 on success, negative value on failure
4973 *
4974 * The open entry point is called when a network interface is made
4975 * active by the system (IFF_UP). At this point all resources needed
4976 * for transmit and receive operations are allocated, the interrupt
4977 * handler is registered with the OS, the watchdog timer is started,
4978 * and the stack is notified that the interface is ready.
4979 **/
4980 static int ixgbe_open(struct net_device *netdev)
4981 {
4982 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4983 int err;
4984
4985 /* disallow open during test */
4986 if (test_bit(__IXGBE_TESTING, &adapter->state))
4987 return -EBUSY;
4988
4989 netif_carrier_off(netdev);
4990
4991 /* allocate transmit descriptors */
4992 err = ixgbe_setup_all_tx_resources(adapter);
4993 if (err)
4994 goto err_setup_tx;
4995
4996 /* allocate receive descriptors */
4997 err = ixgbe_setup_all_rx_resources(adapter);
4998 if (err)
4999 goto err_setup_rx;
5000
5001 ixgbe_configure(adapter);
5002
5003 err = ixgbe_request_irq(adapter);
5004 if (err)
5005 goto err_req_irq;
5006
5007 /* Notify the stack of the actual queue counts. */
5008 err = netif_set_real_num_tx_queues(netdev,
5009 adapter->num_rx_pools > 1 ? 1 :
5010 adapter->num_tx_queues);
5011 if (err)
5012 goto err_set_queues;
5013
5014
5015 err = netif_set_real_num_rx_queues(netdev,
5016 adapter->num_rx_pools > 1 ? 1 :
5017 adapter->num_rx_queues);
5018 if (err)
5019 goto err_set_queues;
5020
5021 ixgbe_ptp_init(adapter);
5022
5023 ixgbe_up_complete(adapter);
5024
5025 return 0;
5026
5027 err_set_queues:
5028 ixgbe_free_irq(adapter);
5029 err_req_irq:
5030 ixgbe_free_all_rx_resources(adapter);
5031 err_setup_rx:
5032 ixgbe_free_all_tx_resources(adapter);
5033 err_setup_tx:
5034 ixgbe_reset(adapter);
5035
5036 return err;
5037 }
5038
5039 /**
5040 * ixgbe_close - Disables a network interface
5041 * @netdev: network interface device structure
5042 *
5043 * Returns 0, this is not allowed to fail
5044 *
5045 * The close entry point is called when an interface is de-activated
5046 * by the OS. The hardware is still under the drivers control, but
5047 * needs to be disabled. A global MAC reset is issued to stop the
5048 * hardware, and all transmit and receive resources are freed.
5049 **/
5050 static int ixgbe_close(struct net_device *netdev)
5051 {
5052 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5053
5054 ixgbe_ptp_stop(adapter);
5055
5056 ixgbe_down(adapter);
5057 ixgbe_free_irq(adapter);
5058
5059 ixgbe_fdir_filter_exit(adapter);
5060
5061 ixgbe_free_all_tx_resources(adapter);
5062 ixgbe_free_all_rx_resources(adapter);
5063
5064 ixgbe_release_hw_control(adapter);
5065
5066 return 0;
5067 }
5068
5069 #ifdef CONFIG_PM
5070 static int ixgbe_resume(struct pci_dev *pdev)
5071 {
5072 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5073 struct net_device *netdev = adapter->netdev;
5074 u32 err;
5075
5076 pci_set_power_state(pdev, PCI_D0);
5077 pci_restore_state(pdev);
5078 /*
5079 * pci_restore_state clears dev->state_saved so call
5080 * pci_save_state to restore it.
5081 */
5082 pci_save_state(pdev);
5083
5084 err = pci_enable_device_mem(pdev);
5085 if (err) {
5086 e_dev_err("Cannot enable PCI device from suspend\n");
5087 return err;
5088 }
5089 pci_set_master(pdev);
5090
5091 pci_wake_from_d3(pdev, false);
5092
5093 ixgbe_reset(adapter);
5094
5095 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5096
5097 rtnl_lock();
5098 err = ixgbe_init_interrupt_scheme(adapter);
5099 if (!err && netif_running(netdev))
5100 err = ixgbe_open(netdev);
5101
5102 rtnl_unlock();
5103
5104 if (err)
5105 return err;
5106
5107 netif_device_attach(netdev);
5108
5109 return 0;
5110 }
5111 #endif /* CONFIG_PM */
5112
5113 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5114 {
5115 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5116 struct net_device *netdev = adapter->netdev;
5117 struct ixgbe_hw *hw = &adapter->hw;
5118 u32 ctrl, fctrl;
5119 u32 wufc = adapter->wol;
5120 #ifdef CONFIG_PM
5121 int retval = 0;
5122 #endif
5123
5124 netif_device_detach(netdev);
5125
5126 rtnl_lock();
5127 if (netif_running(netdev)) {
5128 ixgbe_down(adapter);
5129 ixgbe_free_irq(adapter);
5130 ixgbe_free_all_tx_resources(adapter);
5131 ixgbe_free_all_rx_resources(adapter);
5132 }
5133 rtnl_unlock();
5134
5135 ixgbe_clear_interrupt_scheme(adapter);
5136
5137 #ifdef CONFIG_PM
5138 retval = pci_save_state(pdev);
5139 if (retval)
5140 return retval;
5141
5142 #endif
5143 if (wufc) {
5144 ixgbe_set_rx_mode(netdev);
5145
5146 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5147 if (hw->mac.ops.enable_tx_laser)
5148 hw->mac.ops.enable_tx_laser(hw);
5149
5150 /* turn on all-multi mode if wake on multicast is enabled */
5151 if (wufc & IXGBE_WUFC_MC) {
5152 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5153 fctrl |= IXGBE_FCTRL_MPE;
5154 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5155 }
5156
5157 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5158 ctrl |= IXGBE_CTRL_GIO_DIS;
5159 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5160
5161 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5162 } else {
5163 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5164 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5165 }
5166
5167 switch (hw->mac.type) {
5168 case ixgbe_mac_82598EB:
5169 pci_wake_from_d3(pdev, false);
5170 break;
5171 case ixgbe_mac_82599EB:
5172 case ixgbe_mac_X540:
5173 pci_wake_from_d3(pdev, !!wufc);
5174 break;
5175 default:
5176 break;
5177 }
5178
5179 *enable_wake = !!wufc;
5180
5181 ixgbe_release_hw_control(adapter);
5182
5183 pci_disable_device(pdev);
5184
5185 return 0;
5186 }
5187
5188 #ifdef CONFIG_PM
5189 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5190 {
5191 int retval;
5192 bool wake;
5193
5194 retval = __ixgbe_shutdown(pdev, &wake);
5195 if (retval)
5196 return retval;
5197
5198 if (wake) {
5199 pci_prepare_to_sleep(pdev);
5200 } else {
5201 pci_wake_from_d3(pdev, false);
5202 pci_set_power_state(pdev, PCI_D3hot);
5203 }
5204
5205 return 0;
5206 }
5207 #endif /* CONFIG_PM */
5208
5209 static void ixgbe_shutdown(struct pci_dev *pdev)
5210 {
5211 bool wake;
5212
5213 __ixgbe_shutdown(pdev, &wake);
5214
5215 if (system_state == SYSTEM_POWER_OFF) {
5216 pci_wake_from_d3(pdev, wake);
5217 pci_set_power_state(pdev, PCI_D3hot);
5218 }
5219 }
5220
5221 /**
5222 * ixgbe_update_stats - Update the board statistics counters.
5223 * @adapter: board private structure
5224 **/
5225 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5226 {
5227 struct net_device *netdev = adapter->netdev;
5228 struct ixgbe_hw *hw = &adapter->hw;
5229 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5230 u64 total_mpc = 0;
5231 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5232 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5233 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5234 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5235
5236 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5237 test_bit(__IXGBE_RESETTING, &adapter->state))
5238 return;
5239
5240 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5241 u64 rsc_count = 0;
5242 u64 rsc_flush = 0;
5243 for (i = 0; i < adapter->num_rx_queues; i++) {
5244 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5245 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5246 }
5247 adapter->rsc_total_count = rsc_count;
5248 adapter->rsc_total_flush = rsc_flush;
5249 }
5250
5251 for (i = 0; i < adapter->num_rx_queues; i++) {
5252 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5253 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5254 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5255 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5256 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5257 bytes += rx_ring->stats.bytes;
5258 packets += rx_ring->stats.packets;
5259 }
5260 adapter->non_eop_descs = non_eop_descs;
5261 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5262 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5263 adapter->hw_csum_rx_error = hw_csum_rx_error;
5264 netdev->stats.rx_bytes = bytes;
5265 netdev->stats.rx_packets = packets;
5266
5267 bytes = 0;
5268 packets = 0;
5269 /* gather some stats to the adapter struct that are per queue */
5270 for (i = 0; i < adapter->num_tx_queues; i++) {
5271 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5272 restart_queue += tx_ring->tx_stats.restart_queue;
5273 tx_busy += tx_ring->tx_stats.tx_busy;
5274 bytes += tx_ring->stats.bytes;
5275 packets += tx_ring->stats.packets;
5276 }
5277 adapter->restart_queue = restart_queue;
5278 adapter->tx_busy = tx_busy;
5279 netdev->stats.tx_bytes = bytes;
5280 netdev->stats.tx_packets = packets;
5281
5282 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5283
5284 /* 8 register reads */
5285 for (i = 0; i < 8; i++) {
5286 /* for packet buffers not used, the register should read 0 */
5287 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5288 missed_rx += mpc;
5289 hwstats->mpc[i] += mpc;
5290 total_mpc += hwstats->mpc[i];
5291 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5292 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5293 switch (hw->mac.type) {
5294 case ixgbe_mac_82598EB:
5295 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5296 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5297 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5298 hwstats->pxonrxc[i] +=
5299 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5300 break;
5301 case ixgbe_mac_82599EB:
5302 case ixgbe_mac_X540:
5303 hwstats->pxonrxc[i] +=
5304 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5305 break;
5306 default:
5307 break;
5308 }
5309 }
5310
5311 /*16 register reads */
5312 for (i = 0; i < 16; i++) {
5313 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5314 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5315 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5316 (hw->mac.type == ixgbe_mac_X540)) {
5317 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5318 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5319 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5320 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5321 }
5322 }
5323
5324 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5325 /* work around hardware counting issue */
5326 hwstats->gprc -= missed_rx;
5327
5328 ixgbe_update_xoff_received(adapter);
5329
5330 /* 82598 hardware only has a 32 bit counter in the high register */
5331 switch (hw->mac.type) {
5332 case ixgbe_mac_82598EB:
5333 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5334 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5335 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5336 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5337 break;
5338 case ixgbe_mac_X540:
5339 /* OS2BMC stats are X540 only*/
5340 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5341 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5342 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5343 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5344 case ixgbe_mac_82599EB:
5345 for (i = 0; i < 16; i++)
5346 adapter->hw_rx_no_dma_resources +=
5347 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5348 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5349 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5350 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5351 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5352 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5353 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5354 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5355 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5356 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5357 #ifdef IXGBE_FCOE
5358 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5359 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5360 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5361 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5362 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5363 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5364 /* Add up per cpu counters for total ddp aloc fail */
5365 if (adapter->fcoe.ddp_pool) {
5366 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5367 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5368 unsigned int cpu;
5369 u64 noddp = 0, noddp_ext_buff = 0;
5370 for_each_possible_cpu(cpu) {
5371 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5372 noddp += ddp_pool->noddp;
5373 noddp_ext_buff += ddp_pool->noddp_ext_buff;
5374 }
5375 hwstats->fcoe_noddp = noddp;
5376 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
5377 }
5378 #endif /* IXGBE_FCOE */
5379 break;
5380 default:
5381 break;
5382 }
5383 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5384 hwstats->bprc += bprc;
5385 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5386 if (hw->mac.type == ixgbe_mac_82598EB)
5387 hwstats->mprc -= bprc;
5388 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5389 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5390 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5391 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5392 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5393 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5394 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5395 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5396 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5397 hwstats->lxontxc += lxon;
5398 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5399 hwstats->lxofftxc += lxoff;
5400 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5401 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5402 /*
5403 * 82598 errata - tx of flow control packets is included in tx counters
5404 */
5405 xon_off_tot = lxon + lxoff;
5406 hwstats->gptc -= xon_off_tot;
5407 hwstats->mptc -= xon_off_tot;
5408 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5409 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5410 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5411 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5412 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5413 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5414 hwstats->ptc64 -= xon_off_tot;
5415 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5416 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5417 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5418 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5419 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5420 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5421
5422 /* Fill out the OS statistics structure */
5423 netdev->stats.multicast = hwstats->mprc;
5424
5425 /* Rx Errors */
5426 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5427 netdev->stats.rx_dropped = 0;
5428 netdev->stats.rx_length_errors = hwstats->rlec;
5429 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5430 netdev->stats.rx_missed_errors = total_mpc;
5431 }
5432
5433 /**
5434 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5435 * @adapter: pointer to the device adapter structure
5436 **/
5437 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5438 {
5439 struct ixgbe_hw *hw = &adapter->hw;
5440 int i;
5441
5442 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5443 return;
5444
5445 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5446
5447 /* if interface is down do nothing */
5448 if (test_bit(__IXGBE_DOWN, &adapter->state))
5449 return;
5450
5451 /* do nothing if we are not using signature filters */
5452 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5453 return;
5454
5455 adapter->fdir_overflow++;
5456
5457 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5458 for (i = 0; i < adapter->num_tx_queues; i++)
5459 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5460 &(adapter->tx_ring[i]->state));
5461 /* re-enable flow director interrupts */
5462 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5463 } else {
5464 e_err(probe, "failed to finish FDIR re-initialization, "
5465 "ignored adding FDIR ATR filters\n");
5466 }
5467 }
5468
5469 /**
5470 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5471 * @adapter: pointer to the device adapter structure
5472 *
5473 * This function serves two purposes. First it strobes the interrupt lines
5474 * in order to make certain interrupts are occurring. Secondly it sets the
5475 * bits needed to check for TX hangs. As a result we should immediately
5476 * determine if a hang has occurred.
5477 */
5478 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5479 {
5480 struct ixgbe_hw *hw = &adapter->hw;
5481 u64 eics = 0;
5482 int i;
5483
5484 /* If we're down or resetting, just bail */
5485 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5486 test_bit(__IXGBE_RESETTING, &adapter->state))
5487 return;
5488
5489 /* Force detection of hung controller */
5490 if (netif_carrier_ok(adapter->netdev)) {
5491 for (i = 0; i < adapter->num_tx_queues; i++)
5492 set_check_for_tx_hang(adapter->tx_ring[i]);
5493 }
5494
5495 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5496 /*
5497 * for legacy and MSI interrupts don't set any bits
5498 * that are enabled for EIAM, because this operation
5499 * would set *both* EIMS and EICS for any bit in EIAM
5500 */
5501 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5502 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5503 } else {
5504 /* get one bit for every active tx/rx interrupt vector */
5505 for (i = 0; i < adapter->num_q_vectors; i++) {
5506 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5507 if (qv->rx.ring || qv->tx.ring)
5508 eics |= ((u64)1 << i);
5509 }
5510 }
5511
5512 /* Cause software interrupt to ensure rings are cleaned */
5513 ixgbe_irq_rearm_queues(adapter, eics);
5514
5515 }
5516
5517 /**
5518 * ixgbe_watchdog_update_link - update the link status
5519 * @adapter: pointer to the device adapter structure
5520 * @link_speed: pointer to a u32 to store the link_speed
5521 **/
5522 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5523 {
5524 struct ixgbe_hw *hw = &adapter->hw;
5525 u32 link_speed = adapter->link_speed;
5526 bool link_up = adapter->link_up;
5527 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
5528
5529 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5530 return;
5531
5532 if (hw->mac.ops.check_link) {
5533 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5534 } else {
5535 /* always assume link is up, if no check link function */
5536 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5537 link_up = true;
5538 }
5539
5540 if (adapter->ixgbe_ieee_pfc)
5541 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5542
5543 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
5544 hw->mac.ops.fc_enable(hw);
5545 ixgbe_set_rx_drop_en(adapter);
5546 }
5547
5548 if (link_up ||
5549 time_after(jiffies, (adapter->link_check_timeout +
5550 IXGBE_TRY_LINK_TIMEOUT))) {
5551 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5552 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5553 IXGBE_WRITE_FLUSH(hw);
5554 }
5555
5556 adapter->link_up = link_up;
5557 adapter->link_speed = link_speed;
5558 }
5559
5560 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5561 {
5562 #ifdef CONFIG_IXGBE_DCB
5563 struct net_device *netdev = adapter->netdev;
5564 struct dcb_app app = {
5565 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5566 .protocol = 0,
5567 };
5568 u8 up = 0;
5569
5570 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5571 up = dcb_ieee_getapp_mask(netdev, &app);
5572
5573 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5574 #endif
5575 }
5576
5577 /**
5578 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5579 * print link up message
5580 * @adapter: pointer to the device adapter structure
5581 **/
5582 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5583 {
5584 struct net_device *netdev = adapter->netdev;
5585 struct ixgbe_hw *hw = &adapter->hw;
5586 u32 link_speed = adapter->link_speed;
5587 bool flow_rx, flow_tx;
5588
5589 /* only continue if link was previously down */
5590 if (netif_carrier_ok(netdev))
5591 return;
5592
5593 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5594
5595 switch (hw->mac.type) {
5596 case ixgbe_mac_82598EB: {
5597 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5598 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5599 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5600 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5601 }
5602 break;
5603 case ixgbe_mac_X540:
5604 case ixgbe_mac_82599EB: {
5605 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5606 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5607 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5608 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5609 }
5610 break;
5611 default:
5612 flow_tx = false;
5613 flow_rx = false;
5614 break;
5615 }
5616
5617 adapter->last_rx_ptp_check = jiffies;
5618
5619 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5620 ixgbe_ptp_start_cyclecounter(adapter);
5621
5622 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5623 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5624 "10 Gbps" :
5625 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5626 "1 Gbps" :
5627 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5628 "100 Mbps" :
5629 "unknown speed"))),
5630 ((flow_rx && flow_tx) ? "RX/TX" :
5631 (flow_rx ? "RX" :
5632 (flow_tx ? "TX" : "None"))));
5633
5634 netif_carrier_on(netdev);
5635 ixgbe_check_vf_rate_limit(adapter);
5636
5637 /* update the default user priority for VFs */
5638 ixgbe_update_default_up(adapter);
5639
5640 /* ping all the active vfs to let them know link has changed */
5641 ixgbe_ping_all_vfs(adapter);
5642 }
5643
5644 /**
5645 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5646 * print link down message
5647 * @adapter: pointer to the adapter structure
5648 **/
5649 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5650 {
5651 struct net_device *netdev = adapter->netdev;
5652 struct ixgbe_hw *hw = &adapter->hw;
5653
5654 adapter->link_up = false;
5655 adapter->link_speed = 0;
5656
5657 /* only continue if link was up previously */
5658 if (!netif_carrier_ok(netdev))
5659 return;
5660
5661 /* poll for SFP+ cable when link is down */
5662 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5663 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5664
5665 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5666 ixgbe_ptp_start_cyclecounter(adapter);
5667
5668 e_info(drv, "NIC Link is Down\n");
5669 netif_carrier_off(netdev);
5670
5671 /* ping all the active vfs to let them know link has changed */
5672 ixgbe_ping_all_vfs(adapter);
5673 }
5674
5675 /**
5676 * ixgbe_watchdog_flush_tx - flush queues on link down
5677 * @adapter: pointer to the device adapter structure
5678 **/
5679 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5680 {
5681 int i;
5682 int some_tx_pending = 0;
5683
5684 if (!netif_carrier_ok(adapter->netdev)) {
5685 for (i = 0; i < adapter->num_tx_queues; i++) {
5686 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5687 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5688 some_tx_pending = 1;
5689 break;
5690 }
5691 }
5692
5693 if (some_tx_pending) {
5694 /* We've lost link, so the controller stops DMA,
5695 * but we've got queued Tx work that's never going
5696 * to get done, so reset controller to flush Tx.
5697 * (Do the reset outside of interrupt context).
5698 */
5699 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
5700 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5701 }
5702 }
5703 }
5704
5705 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5706 {
5707 u32 ssvpc;
5708
5709 /* Do not perform spoof check for 82598 or if not in IOV mode */
5710 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5711 adapter->num_vfs == 0)
5712 return;
5713
5714 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5715
5716 /*
5717 * ssvpc register is cleared on read, if zero then no
5718 * spoofed packets in the last interval.
5719 */
5720 if (!ssvpc)
5721 return;
5722
5723 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
5724 }
5725
5726 /**
5727 * ixgbe_watchdog_subtask - check and bring link up
5728 * @adapter: pointer to the device adapter structure
5729 **/
5730 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5731 {
5732 /* if interface is down do nothing */
5733 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5734 test_bit(__IXGBE_RESETTING, &adapter->state))
5735 return;
5736
5737 ixgbe_watchdog_update_link(adapter);
5738
5739 if (adapter->link_up)
5740 ixgbe_watchdog_link_is_up(adapter);
5741 else
5742 ixgbe_watchdog_link_is_down(adapter);
5743
5744 ixgbe_spoof_check(adapter);
5745 ixgbe_update_stats(adapter);
5746
5747 ixgbe_watchdog_flush_tx(adapter);
5748 }
5749
5750 /**
5751 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5752 * @adapter: the ixgbe adapter structure
5753 **/
5754 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5755 {
5756 struct ixgbe_hw *hw = &adapter->hw;
5757 s32 err;
5758
5759 /* not searching for SFP so there is nothing to do here */
5760 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5761 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5762 return;
5763
5764 /* concurent i2c reads are not supported */
5765 if (test_bit(__IXGBE_READ_I2C, &adapter->state))
5766 return;
5767
5768 /* someone else is in init, wait until next service event */
5769 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5770 return;
5771
5772 err = hw->phy.ops.identify_sfp(hw);
5773 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5774 goto sfp_out;
5775
5776 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5777 /* If no cable is present, then we need to reset
5778 * the next time we find a good cable. */
5779 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5780 }
5781
5782 /* exit on error */
5783 if (err)
5784 goto sfp_out;
5785
5786 /* exit if reset not needed */
5787 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5788 goto sfp_out;
5789
5790 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5791
5792 /*
5793 * A module may be identified correctly, but the EEPROM may not have
5794 * support for that module. setup_sfp() will fail in that case, so
5795 * we should not allow that module to load.
5796 */
5797 if (hw->mac.type == ixgbe_mac_82598EB)
5798 err = hw->phy.ops.reset(hw);
5799 else
5800 err = hw->mac.ops.setup_sfp(hw);
5801
5802 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5803 goto sfp_out;
5804
5805 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5806 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5807
5808 sfp_out:
5809 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5810
5811 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5812 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5813 e_dev_err("failed to initialize because an unsupported "
5814 "SFP+ module type was detected.\n");
5815 e_dev_err("Reload the driver after installing a "
5816 "supported module.\n");
5817 unregister_netdev(adapter->netdev);
5818 }
5819 }
5820
5821 /**
5822 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5823 * @adapter: the ixgbe adapter structure
5824 **/
5825 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5826 {
5827 struct ixgbe_hw *hw = &adapter->hw;
5828 u32 speed;
5829 bool autoneg = false;
5830
5831 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5832 return;
5833
5834 /* someone else is in init, wait until next service event */
5835 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5836 return;
5837
5838 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5839
5840 speed = hw->phy.autoneg_advertised;
5841 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5842 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
5843 if (hw->mac.ops.setup_link)
5844 hw->mac.ops.setup_link(hw, speed, true);
5845
5846 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5847 adapter->link_check_timeout = jiffies;
5848 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5849 }
5850
5851 #ifdef CONFIG_PCI_IOV
5852 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5853 {
5854 int vf;
5855 struct ixgbe_hw *hw = &adapter->hw;
5856 struct net_device *netdev = adapter->netdev;
5857 u32 gpc;
5858 u32 ciaa, ciad;
5859
5860 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5861 if (gpc) /* If incrementing then no need for the check below */
5862 return;
5863 /*
5864 * Check to see if a bad DMA write target from an errant or
5865 * malicious VF has caused a PCIe error. If so then we can
5866 * issue a VFLR to the offending VF(s) and then resume without
5867 * requesting a full slot reset.
5868 */
5869
5870 for (vf = 0; vf < adapter->num_vfs; vf++) {
5871 ciaa = (vf << 16) | 0x80000000;
5872 /* 32 bit read so align, we really want status at offset 6 */
5873 ciaa |= PCI_COMMAND;
5874 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5875 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5876 ciaa &= 0x7FFFFFFF;
5877 /* disable debug mode asap after reading data */
5878 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5879 /* Get the upper 16 bits which will be the PCI status reg */
5880 ciad >>= 16;
5881 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5882 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5883 /* Issue VFLR */
5884 ciaa = (vf << 16) | 0x80000000;
5885 ciaa |= 0xA8;
5886 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5887 ciad = 0x00008000; /* VFLR */
5888 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5889 ciaa &= 0x7FFFFFFF;
5890 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5891 }
5892 }
5893 }
5894
5895 #endif
5896 /**
5897 * ixgbe_service_timer - Timer Call-back
5898 * @data: pointer to adapter cast into an unsigned long
5899 **/
5900 static void ixgbe_service_timer(unsigned long data)
5901 {
5902 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5903 unsigned long next_event_offset;
5904 bool ready = true;
5905
5906 /* poll faster when waiting for link */
5907 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5908 next_event_offset = HZ / 10;
5909 else
5910 next_event_offset = HZ * 2;
5911
5912 #ifdef CONFIG_PCI_IOV
5913 /*
5914 * don't bother with SR-IOV VF DMA hang check if there are
5915 * no VFs or the link is down
5916 */
5917 if (!adapter->num_vfs ||
5918 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5919 goto normal_timer_service;
5920
5921 /* If we have VFs allocated then we must check for DMA hangs */
5922 ixgbe_check_for_bad_vf(adapter);
5923 next_event_offset = HZ / 50;
5924 adapter->timer_event_accumulator++;
5925
5926 if (adapter->timer_event_accumulator >= 100)
5927 adapter->timer_event_accumulator = 0;
5928 else
5929 ready = false;
5930
5931 normal_timer_service:
5932 #endif
5933 /* Reset the timer */
5934 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5935
5936 if (ready)
5937 ixgbe_service_event_schedule(adapter);
5938 }
5939
5940 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5941 {
5942 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5943 return;
5944
5945 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5946
5947 /* If we're already down or resetting, just bail */
5948 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5949 test_bit(__IXGBE_RESETTING, &adapter->state))
5950 return;
5951
5952 ixgbe_dump(adapter);
5953 netdev_err(adapter->netdev, "Reset adapter\n");
5954 adapter->tx_timeout_count++;
5955
5956 ixgbe_reinit_locked(adapter);
5957 }
5958
5959 /**
5960 * ixgbe_service_task - manages and runs subtasks
5961 * @work: pointer to work_struct containing our data
5962 **/
5963 static void ixgbe_service_task(struct work_struct *work)
5964 {
5965 struct ixgbe_adapter *adapter = container_of(work,
5966 struct ixgbe_adapter,
5967 service_task);
5968 ixgbe_reset_subtask(adapter);
5969 ixgbe_sfp_detection_subtask(adapter);
5970 ixgbe_sfp_link_config_subtask(adapter);
5971 ixgbe_check_overtemp_subtask(adapter);
5972 ixgbe_watchdog_subtask(adapter);
5973 ixgbe_fdir_reinit_subtask(adapter);
5974 ixgbe_check_hang_subtask(adapter);
5975
5976 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED) {
5977 ixgbe_ptp_overflow_check(adapter);
5978 ixgbe_ptp_rx_hang(adapter);
5979 }
5980
5981 ixgbe_service_event_complete(adapter);
5982 }
5983
5984 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5985 struct ixgbe_tx_buffer *first,
5986 u8 *hdr_len)
5987 {
5988 struct sk_buff *skb = first->skb;
5989 u32 vlan_macip_lens, type_tucmd;
5990 u32 mss_l4len_idx, l4len;
5991
5992 if (skb->ip_summed != CHECKSUM_PARTIAL)
5993 return 0;
5994
5995 if (!skb_is_gso(skb))
5996 return 0;
5997
5998 if (skb_header_cloned(skb)) {
5999 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6000 if (err)
6001 return err;
6002 }
6003
6004 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6005 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6006
6007 if (first->protocol == __constant_htons(ETH_P_IP)) {
6008 struct iphdr *iph = ip_hdr(skb);
6009 iph->tot_len = 0;
6010 iph->check = 0;
6011 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6012 iph->daddr, 0,
6013 IPPROTO_TCP,
6014 0);
6015 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6016 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6017 IXGBE_TX_FLAGS_CSUM |
6018 IXGBE_TX_FLAGS_IPV4;
6019 } else if (skb_is_gso_v6(skb)) {
6020 ipv6_hdr(skb)->payload_len = 0;
6021 tcp_hdr(skb)->check =
6022 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6023 &ipv6_hdr(skb)->daddr,
6024 0, IPPROTO_TCP, 0);
6025 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6026 IXGBE_TX_FLAGS_CSUM;
6027 }
6028
6029 /* compute header lengths */
6030 l4len = tcp_hdrlen(skb);
6031 *hdr_len = skb_transport_offset(skb) + l4len;
6032
6033 /* update gso size and bytecount with header size */
6034 first->gso_segs = skb_shinfo(skb)->gso_segs;
6035 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6036
6037 /* mss_l4len_id: use 0 as index for TSO */
6038 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6039 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6040
6041 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6042 vlan_macip_lens = skb_network_header_len(skb);
6043 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6044 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6045
6046 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6047 mss_l4len_idx);
6048
6049 return 1;
6050 }
6051
6052 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6053 struct ixgbe_tx_buffer *first)
6054 {
6055 struct sk_buff *skb = first->skb;
6056 u32 vlan_macip_lens = 0;
6057 u32 mss_l4len_idx = 0;
6058 u32 type_tucmd = 0;
6059
6060 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6061 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6062 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6063 return;
6064 } else {
6065 u8 l4_hdr = 0;
6066 switch (first->protocol) {
6067 case __constant_htons(ETH_P_IP):
6068 vlan_macip_lens |= skb_network_header_len(skb);
6069 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6070 l4_hdr = ip_hdr(skb)->protocol;
6071 break;
6072 case __constant_htons(ETH_P_IPV6):
6073 vlan_macip_lens |= skb_network_header_len(skb);
6074 l4_hdr = ipv6_hdr(skb)->nexthdr;
6075 break;
6076 default:
6077 if (unlikely(net_ratelimit())) {
6078 dev_warn(tx_ring->dev,
6079 "partial checksum but proto=%x!\n",
6080 first->protocol);
6081 }
6082 break;
6083 }
6084
6085 switch (l4_hdr) {
6086 case IPPROTO_TCP:
6087 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6088 mss_l4len_idx = tcp_hdrlen(skb) <<
6089 IXGBE_ADVTXD_L4LEN_SHIFT;
6090 break;
6091 case IPPROTO_SCTP:
6092 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6093 mss_l4len_idx = sizeof(struct sctphdr) <<
6094 IXGBE_ADVTXD_L4LEN_SHIFT;
6095 break;
6096 case IPPROTO_UDP:
6097 mss_l4len_idx = sizeof(struct udphdr) <<
6098 IXGBE_ADVTXD_L4LEN_SHIFT;
6099 break;
6100 default:
6101 if (unlikely(net_ratelimit())) {
6102 dev_warn(tx_ring->dev,
6103 "partial checksum but l4 proto=%x!\n",
6104 l4_hdr);
6105 }
6106 break;
6107 }
6108
6109 /* update TX checksum flag */
6110 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
6111 }
6112
6113 /* vlan_macip_lens: MACLEN, VLAN tag */
6114 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6115 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6116
6117 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6118 type_tucmd, mss_l4len_idx);
6119 }
6120
6121 #define IXGBE_SET_FLAG(_input, _flag, _result) \
6122 ((_flag <= _result) ? \
6123 ((u32)(_input & _flag) * (_result / _flag)) : \
6124 ((u32)(_input & _flag) / (_flag / _result)))
6125
6126 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6127 {
6128 /* set type for advanced descriptor with frame checksum insertion */
6129 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6130 IXGBE_ADVTXD_DCMD_DEXT |
6131 IXGBE_ADVTXD_DCMD_IFCS;
6132
6133 /* set HW vlan bit if vlan is present */
6134 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6135 IXGBE_ADVTXD_DCMD_VLE);
6136
6137 /* set segmentation enable bits for TSO/FSO */
6138 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6139 IXGBE_ADVTXD_DCMD_TSE);
6140
6141 /* set timestamp bit if present */
6142 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6143 IXGBE_ADVTXD_MAC_TSTAMP);
6144
6145 /* insert frame checksum */
6146 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
6147
6148 return cmd_type;
6149 }
6150
6151 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6152 u32 tx_flags, unsigned int paylen)
6153 {
6154 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
6155
6156 /* enable L4 checksum for TSO and TX checksum offload */
6157 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6158 IXGBE_TX_FLAGS_CSUM,
6159 IXGBE_ADVTXD_POPTS_TXSM);
6160
6161 /* enble IPv4 checksum for TSO */
6162 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6163 IXGBE_TX_FLAGS_IPV4,
6164 IXGBE_ADVTXD_POPTS_IXSM);
6165
6166 /*
6167 * Check Context must be set if Tx switch is enabled, which it
6168 * always is for case where virtual functions are running
6169 */
6170 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6171 IXGBE_TX_FLAGS_CC,
6172 IXGBE_ADVTXD_CC);
6173
6174 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6175 }
6176
6177 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6178 IXGBE_TXD_CMD_RS)
6179
6180 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6181 struct ixgbe_tx_buffer *first,
6182 const u8 hdr_len)
6183 {
6184 struct sk_buff *skb = first->skb;
6185 struct ixgbe_tx_buffer *tx_buffer;
6186 union ixgbe_adv_tx_desc *tx_desc;
6187 struct skb_frag_struct *frag;
6188 dma_addr_t dma;
6189 unsigned int data_len, size;
6190 u32 tx_flags = first->tx_flags;
6191 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
6192 u16 i = tx_ring->next_to_use;
6193
6194 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6195
6196 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6197
6198 size = skb_headlen(skb);
6199 data_len = skb->data_len;
6200
6201 #ifdef IXGBE_FCOE
6202 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6203 if (data_len < sizeof(struct fcoe_crc_eof)) {
6204 size -= sizeof(struct fcoe_crc_eof) - data_len;
6205 data_len = 0;
6206 } else {
6207 data_len -= sizeof(struct fcoe_crc_eof);
6208 }
6209 }
6210
6211 #endif
6212 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6213
6214 tx_buffer = first;
6215
6216 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6217 if (dma_mapping_error(tx_ring->dev, dma))
6218 goto dma_error;
6219
6220 /* record length, and DMA address */
6221 dma_unmap_len_set(tx_buffer, len, size);
6222 dma_unmap_addr_set(tx_buffer, dma, dma);
6223
6224 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6225
6226 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6227 tx_desc->read.cmd_type_len =
6228 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
6229
6230 i++;
6231 tx_desc++;
6232 if (i == tx_ring->count) {
6233 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6234 i = 0;
6235 }
6236 tx_desc->read.olinfo_status = 0;
6237
6238 dma += IXGBE_MAX_DATA_PER_TXD;
6239 size -= IXGBE_MAX_DATA_PER_TXD;
6240
6241 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6242 }
6243
6244 if (likely(!data_len))
6245 break;
6246
6247 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6248
6249 i++;
6250 tx_desc++;
6251 if (i == tx_ring->count) {
6252 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6253 i = 0;
6254 }
6255 tx_desc->read.olinfo_status = 0;
6256
6257 #ifdef IXGBE_FCOE
6258 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6259 #else
6260 size = skb_frag_size(frag);
6261 #endif
6262 data_len -= size;
6263
6264 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6265 DMA_TO_DEVICE);
6266
6267 tx_buffer = &tx_ring->tx_buffer_info[i];
6268 }
6269
6270 /* write last descriptor with RS and EOP bits */
6271 cmd_type |= size | IXGBE_TXD_CMD;
6272 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6273
6274 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6275
6276 /* set the timestamp */
6277 first->time_stamp = jiffies;
6278
6279 /*
6280 * Force memory writes to complete before letting h/w know there
6281 * are new descriptors to fetch. (Only applicable for weak-ordered
6282 * memory model archs, such as IA-64).
6283 *
6284 * We also need this memory barrier to make certain all of the
6285 * status bits have been updated before next_to_watch is written.
6286 */
6287 wmb();
6288
6289 /* set next_to_watch value indicating a packet is present */
6290 first->next_to_watch = tx_desc;
6291
6292 i++;
6293 if (i == tx_ring->count)
6294 i = 0;
6295
6296 tx_ring->next_to_use = i;
6297
6298 /* notify HW of packet */
6299 writel(i, tx_ring->tail);
6300
6301 return;
6302 dma_error:
6303 dev_err(tx_ring->dev, "TX DMA map failed\n");
6304
6305 /* clear dma mappings for failed tx_buffer_info map */
6306 for (;;) {
6307 tx_buffer = &tx_ring->tx_buffer_info[i];
6308 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6309 if (tx_buffer == first)
6310 break;
6311 if (i == 0)
6312 i = tx_ring->count;
6313 i--;
6314 }
6315
6316 tx_ring->next_to_use = i;
6317 }
6318
6319 static void ixgbe_atr(struct ixgbe_ring *ring,
6320 struct ixgbe_tx_buffer *first)
6321 {
6322 struct ixgbe_q_vector *q_vector = ring->q_vector;
6323 union ixgbe_atr_hash_dword input = { .dword = 0 };
6324 union ixgbe_atr_hash_dword common = { .dword = 0 };
6325 union {
6326 unsigned char *network;
6327 struct iphdr *ipv4;
6328 struct ipv6hdr *ipv6;
6329 } hdr;
6330 struct tcphdr *th;
6331 __be16 vlan_id;
6332
6333 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6334 if (!q_vector)
6335 return;
6336
6337 /* do nothing if sampling is disabled */
6338 if (!ring->atr_sample_rate)
6339 return;
6340
6341 ring->atr_count++;
6342
6343 /* snag network header to get L4 type and address */
6344 hdr.network = skb_network_header(first->skb);
6345
6346 /* Currently only IPv4/IPv6 with TCP is supported */
6347 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6348 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6349 (first->protocol != __constant_htons(ETH_P_IP) ||
6350 hdr.ipv4->protocol != IPPROTO_TCP))
6351 return;
6352
6353 th = tcp_hdr(first->skb);
6354
6355 /* skip this packet since it is invalid or the socket is closing */
6356 if (!th || th->fin)
6357 return;
6358
6359 /* sample on all syn packets or once every atr sample count */
6360 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6361 return;
6362
6363 /* reset sample count */
6364 ring->atr_count = 0;
6365
6366 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6367
6368 /*
6369 * src and dst are inverted, think how the receiver sees them
6370 *
6371 * The input is broken into two sections, a non-compressed section
6372 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6373 * is XORed together and stored in the compressed dword.
6374 */
6375 input.formatted.vlan_id = vlan_id;
6376
6377 /*
6378 * since src port and flex bytes occupy the same word XOR them together
6379 * and write the value to source port portion of compressed dword
6380 */
6381 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6382 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6383 else
6384 common.port.src ^= th->dest ^ first->protocol;
6385 common.port.dst ^= th->source;
6386
6387 if (first->protocol == __constant_htons(ETH_P_IP)) {
6388 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6389 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6390 } else {
6391 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6392 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6393 hdr.ipv6->saddr.s6_addr32[1] ^
6394 hdr.ipv6->saddr.s6_addr32[2] ^
6395 hdr.ipv6->saddr.s6_addr32[3] ^
6396 hdr.ipv6->daddr.s6_addr32[0] ^
6397 hdr.ipv6->daddr.s6_addr32[1] ^
6398 hdr.ipv6->daddr.s6_addr32[2] ^
6399 hdr.ipv6->daddr.s6_addr32[3];
6400 }
6401
6402 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6403 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6404 input, common, ring->queue_index);
6405 }
6406
6407 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6408 {
6409 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6410 /* Herbert's original patch had:
6411 * smp_mb__after_netif_stop_queue();
6412 * but since that doesn't exist yet, just open code it. */
6413 smp_mb();
6414
6415 /* We need to check again in a case another CPU has just
6416 * made room available. */
6417 if (likely(ixgbe_desc_unused(tx_ring) < size))
6418 return -EBUSY;
6419
6420 /* A reprieve! - use start_queue because it doesn't call schedule */
6421 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6422 ++tx_ring->tx_stats.restart_queue;
6423 return 0;
6424 }
6425
6426 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6427 {
6428 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6429 return 0;
6430 return __ixgbe_maybe_stop_tx(tx_ring, size);
6431 }
6432
6433 #ifdef IXGBE_FCOE
6434 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6435 {
6436 struct ixgbe_adapter *adapter;
6437 struct ixgbe_ring_feature *f;
6438 int txq;
6439
6440 /*
6441 * only execute the code below if protocol is FCoE
6442 * or FIP and we have FCoE enabled on the adapter
6443 */
6444 switch (vlan_get_protocol(skb)) {
6445 case __constant_htons(ETH_P_FCOE):
6446 case __constant_htons(ETH_P_FIP):
6447 adapter = netdev_priv(dev);
6448
6449 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6450 break;
6451 default:
6452 return __netdev_pick_tx(dev, skb);
6453 }
6454
6455 f = &adapter->ring_feature[RING_F_FCOE];
6456
6457 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6458 smp_processor_id();
6459
6460 while (txq >= f->indices)
6461 txq -= f->indices;
6462
6463 return txq + f->offset;
6464 }
6465
6466 #endif
6467 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6468 struct ixgbe_adapter *adapter,
6469 struct ixgbe_ring *tx_ring)
6470 {
6471 struct ixgbe_tx_buffer *first;
6472 int tso;
6473 u32 tx_flags = 0;
6474 unsigned short f;
6475 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6476 __be16 protocol = skb->protocol;
6477 u8 hdr_len = 0;
6478
6479 /*
6480 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6481 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6482 * + 2 desc gap to keep tail from touching head,
6483 * + 1 desc for context descriptor,
6484 * otherwise try next time
6485 */
6486 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6487 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6488
6489 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6490 tx_ring->tx_stats.tx_busy++;
6491 return NETDEV_TX_BUSY;
6492 }
6493
6494 /* record the location of the first descriptor for this packet */
6495 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6496 first->skb = skb;
6497 first->bytecount = skb->len;
6498 first->gso_segs = 1;
6499
6500 /* if we have a HW VLAN tag being added default to the HW one */
6501 if (vlan_tx_tag_present(skb)) {
6502 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6503 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6504 /* else if it is a SW VLAN check the next protocol and store the tag */
6505 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6506 struct vlan_hdr *vhdr, _vhdr;
6507 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6508 if (!vhdr)
6509 goto out_drop;
6510
6511 protocol = vhdr->h_vlan_encapsulated_proto;
6512 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6513 IXGBE_TX_FLAGS_VLAN_SHIFT;
6514 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6515 }
6516
6517 skb_tx_timestamp(skb);
6518
6519 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6520 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6521 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6522
6523 /* schedule check for Tx timestamp */
6524 adapter->ptp_tx_skb = skb_get(skb);
6525 adapter->ptp_tx_start = jiffies;
6526 schedule_work(&adapter->ptp_tx_work);
6527 }
6528
6529 #ifdef CONFIG_PCI_IOV
6530 /*
6531 * Use the l2switch_enable flag - would be false if the DMA
6532 * Tx switch had been disabled.
6533 */
6534 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6535 tx_flags |= IXGBE_TX_FLAGS_CC;
6536
6537 #endif
6538 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6539 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6540 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6541 (skb->priority != TC_PRIO_CONTROL))) {
6542 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6543 tx_flags |= (skb->priority & 0x7) <<
6544 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6545 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6546 struct vlan_ethhdr *vhdr;
6547 if (skb_header_cloned(skb) &&
6548 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6549 goto out_drop;
6550 vhdr = (struct vlan_ethhdr *)skb->data;
6551 vhdr->h_vlan_TCI = htons(tx_flags >>
6552 IXGBE_TX_FLAGS_VLAN_SHIFT);
6553 } else {
6554 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6555 }
6556 }
6557
6558 /* record initial flags and protocol */
6559 first->tx_flags = tx_flags;
6560 first->protocol = protocol;
6561
6562 #ifdef IXGBE_FCOE
6563 /* setup tx offload for FCoE */
6564 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6565 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
6566 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6567 if (tso < 0)
6568 goto out_drop;
6569
6570 goto xmit_fcoe;
6571 }
6572
6573 #endif /* IXGBE_FCOE */
6574 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6575 if (tso < 0)
6576 goto out_drop;
6577 else if (!tso)
6578 ixgbe_tx_csum(tx_ring, first);
6579
6580 /* add the ATR filter if ATR is on */
6581 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6582 ixgbe_atr(tx_ring, first);
6583
6584 #ifdef IXGBE_FCOE
6585 xmit_fcoe:
6586 #endif /* IXGBE_FCOE */
6587 ixgbe_tx_map(tx_ring, first, hdr_len);
6588
6589 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6590
6591 return NETDEV_TX_OK;
6592
6593 out_drop:
6594 dev_kfree_skb_any(first->skb);
6595 first->skb = NULL;
6596
6597 return NETDEV_TX_OK;
6598 }
6599
6600 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6601 struct net_device *netdev)
6602 {
6603 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6604 struct ixgbe_ring *tx_ring;
6605
6606 /*
6607 * The minimum packet size for olinfo paylen is 17 so pad the skb
6608 * in order to meet this minimum size requirement.
6609 */
6610 if (unlikely(skb->len < 17)) {
6611 if (skb_pad(skb, 17 - skb->len))
6612 return NETDEV_TX_OK;
6613 skb->len = 17;
6614 skb_set_tail_pointer(skb, 17);
6615 }
6616
6617 tx_ring = adapter->tx_ring[skb->queue_mapping];
6618 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6619 }
6620
6621 /**
6622 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6623 * @netdev: network interface device structure
6624 * @p: pointer to an address structure
6625 *
6626 * Returns 0 on success, negative on failure
6627 **/
6628 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6629 {
6630 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6631 struct ixgbe_hw *hw = &adapter->hw;
6632 struct sockaddr *addr = p;
6633
6634 if (!is_valid_ether_addr(addr->sa_data))
6635 return -EADDRNOTAVAIL;
6636
6637 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6638 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6639
6640 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
6641
6642 return 0;
6643 }
6644
6645 static int
6646 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6647 {
6648 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6649 struct ixgbe_hw *hw = &adapter->hw;
6650 u16 value;
6651 int rc;
6652
6653 if (prtad != hw->phy.mdio.prtad)
6654 return -EINVAL;
6655 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6656 if (!rc)
6657 rc = value;
6658 return rc;
6659 }
6660
6661 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6662 u16 addr, u16 value)
6663 {
6664 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6665 struct ixgbe_hw *hw = &adapter->hw;
6666
6667 if (prtad != hw->phy.mdio.prtad)
6668 return -EINVAL;
6669 return hw->phy.ops.write_reg(hw, addr, devad, value);
6670 }
6671
6672 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6673 {
6674 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6675
6676 switch (cmd) {
6677 case SIOCSHWTSTAMP:
6678 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6679 default:
6680 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6681 }
6682 }
6683
6684 /**
6685 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6686 * netdev->dev_addrs
6687 * @netdev: network interface device structure
6688 *
6689 * Returns non-zero on failure
6690 **/
6691 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6692 {
6693 int err = 0;
6694 struct ixgbe_adapter *adapter = netdev_priv(dev);
6695 struct ixgbe_hw *hw = &adapter->hw;
6696
6697 if (is_valid_ether_addr(hw->mac.san_addr)) {
6698 rtnl_lock();
6699 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
6700 rtnl_unlock();
6701
6702 /* update SAN MAC vmdq pool selection */
6703 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
6704 }
6705 return err;
6706 }
6707
6708 /**
6709 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6710 * netdev->dev_addrs
6711 * @netdev: network interface device structure
6712 *
6713 * Returns non-zero on failure
6714 **/
6715 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6716 {
6717 int err = 0;
6718 struct ixgbe_adapter *adapter = netdev_priv(dev);
6719 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6720
6721 if (is_valid_ether_addr(mac->san_addr)) {
6722 rtnl_lock();
6723 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6724 rtnl_unlock();
6725 }
6726 return err;
6727 }
6728
6729 #ifdef CONFIG_NET_POLL_CONTROLLER
6730 /*
6731 * Polling 'interrupt' - used by things like netconsole to send skbs
6732 * without having to re-enable interrupts. It's not called while
6733 * the interrupt routine is executing.
6734 */
6735 static void ixgbe_netpoll(struct net_device *netdev)
6736 {
6737 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6738 int i;
6739
6740 /* if interface is down do nothing */
6741 if (test_bit(__IXGBE_DOWN, &adapter->state))
6742 return;
6743
6744 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6745 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6746 for (i = 0; i < adapter->num_q_vectors; i++)
6747 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
6748 } else {
6749 ixgbe_intr(adapter->pdev->irq, netdev);
6750 }
6751 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6752 }
6753
6754 #endif
6755 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6756 struct rtnl_link_stats64 *stats)
6757 {
6758 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6759 int i;
6760
6761 rcu_read_lock();
6762 for (i = 0; i < adapter->num_rx_queues; i++) {
6763 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6764 u64 bytes, packets;
6765 unsigned int start;
6766
6767 if (ring) {
6768 do {
6769 start = u64_stats_fetch_begin_bh(&ring->syncp);
6770 packets = ring->stats.packets;
6771 bytes = ring->stats.bytes;
6772 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6773 stats->rx_packets += packets;
6774 stats->rx_bytes += bytes;
6775 }
6776 }
6777
6778 for (i = 0; i < adapter->num_tx_queues; i++) {
6779 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6780 u64 bytes, packets;
6781 unsigned int start;
6782
6783 if (ring) {
6784 do {
6785 start = u64_stats_fetch_begin_bh(&ring->syncp);
6786 packets = ring->stats.packets;
6787 bytes = ring->stats.bytes;
6788 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6789 stats->tx_packets += packets;
6790 stats->tx_bytes += bytes;
6791 }
6792 }
6793 rcu_read_unlock();
6794 /* following stats updated by ixgbe_watchdog_task() */
6795 stats->multicast = netdev->stats.multicast;
6796 stats->rx_errors = netdev->stats.rx_errors;
6797 stats->rx_length_errors = netdev->stats.rx_length_errors;
6798 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6799 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6800 return stats;
6801 }
6802
6803 #ifdef CONFIG_IXGBE_DCB
6804 /**
6805 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6806 * @adapter: pointer to ixgbe_adapter
6807 * @tc: number of traffic classes currently enabled
6808 *
6809 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6810 * 802.1Q priority maps to a packet buffer that exists.
6811 */
6812 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6813 {
6814 struct ixgbe_hw *hw = &adapter->hw;
6815 u32 reg, rsave;
6816 int i;
6817
6818 /* 82598 have a static priority to TC mapping that can not
6819 * be changed so no validation is needed.
6820 */
6821 if (hw->mac.type == ixgbe_mac_82598EB)
6822 return;
6823
6824 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6825 rsave = reg;
6826
6827 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6828 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6829
6830 /* If up2tc is out of bounds default to zero */
6831 if (up2tc > tc)
6832 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6833 }
6834
6835 if (reg != rsave)
6836 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6837
6838 return;
6839 }
6840
6841 /**
6842 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6843 * @adapter: Pointer to adapter struct
6844 *
6845 * Populate the netdev user priority to tc map
6846 */
6847 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6848 {
6849 struct net_device *dev = adapter->netdev;
6850 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6851 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6852 u8 prio;
6853
6854 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6855 u8 tc = 0;
6856
6857 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6858 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6859 else if (ets)
6860 tc = ets->prio_tc[prio];
6861
6862 netdev_set_prio_tc_map(dev, prio, tc);
6863 }
6864 }
6865
6866 #endif /* CONFIG_IXGBE_DCB */
6867 /**
6868 * ixgbe_setup_tc - configure net_device for multiple traffic classes
6869 *
6870 * @netdev: net device to configure
6871 * @tc: number of traffic classes to enable
6872 */
6873 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6874 {
6875 struct ixgbe_adapter *adapter = netdev_priv(dev);
6876 struct ixgbe_hw *hw = &adapter->hw;
6877
6878 /* Hardware supports up to 8 traffic classes */
6879 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
6880 (hw->mac.type == ixgbe_mac_82598EB &&
6881 tc < MAX_TRAFFIC_CLASS))
6882 return -EINVAL;
6883
6884 /* Hardware has to reinitialize queues and interrupts to
6885 * match packet buffer alignment. Unfortunately, the
6886 * hardware is not flexible enough to do this dynamically.
6887 */
6888 if (netif_running(dev))
6889 ixgbe_close(dev);
6890 ixgbe_clear_interrupt_scheme(adapter);
6891
6892 #ifdef CONFIG_IXGBE_DCB
6893 if (tc) {
6894 netdev_set_num_tc(dev, tc);
6895 ixgbe_set_prio_tc_map(adapter);
6896
6897 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6898
6899 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6900 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
6901 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6902 }
6903 } else {
6904 netdev_reset_tc(dev);
6905
6906 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6907 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6908
6909 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6910
6911 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6912 adapter->dcb_cfg.pfc_mode_enable = false;
6913 }
6914
6915 ixgbe_validate_rtr(adapter, tc);
6916
6917 #endif /* CONFIG_IXGBE_DCB */
6918 ixgbe_init_interrupt_scheme(adapter);
6919
6920 if (netif_running(dev))
6921 return ixgbe_open(dev);
6922
6923 return 0;
6924 }
6925
6926 #ifdef CONFIG_PCI_IOV
6927 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
6928 {
6929 struct net_device *netdev = adapter->netdev;
6930
6931 rtnl_lock();
6932 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
6933 rtnl_unlock();
6934 }
6935
6936 #endif
6937 void ixgbe_do_reset(struct net_device *netdev)
6938 {
6939 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6940
6941 if (netif_running(netdev))
6942 ixgbe_reinit_locked(adapter);
6943 else
6944 ixgbe_reset(adapter);
6945 }
6946
6947 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
6948 netdev_features_t features)
6949 {
6950 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6951
6952 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6953 if (!(features & NETIF_F_RXCSUM))
6954 features &= ~NETIF_F_LRO;
6955
6956 /* Turn off LRO if not RSC capable */
6957 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6958 features &= ~NETIF_F_LRO;
6959
6960 return features;
6961 }
6962
6963 static int ixgbe_set_features(struct net_device *netdev,
6964 netdev_features_t features)
6965 {
6966 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6967 netdev_features_t changed = netdev->features ^ features;
6968 bool need_reset = false;
6969
6970 /* Make sure RSC matches LRO, reset if change */
6971 if (!(features & NETIF_F_LRO)) {
6972 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6973 need_reset = true;
6974 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6975 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6976 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6977 if (adapter->rx_itr_setting == 1 ||
6978 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6979 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6980 need_reset = true;
6981 } else if ((changed ^ features) & NETIF_F_LRO) {
6982 e_info(probe, "rx-usecs set too low, "
6983 "disabling RSC\n");
6984 }
6985 }
6986
6987 /*
6988 * Check if Flow Director n-tuple support was enabled or disabled. If
6989 * the state changed, we need to reset.
6990 */
6991 switch (features & NETIF_F_NTUPLE) {
6992 case NETIF_F_NTUPLE:
6993 /* turn off ATR, enable perfect filters and reset */
6994 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
6995 need_reset = true;
6996
6997 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6998 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6999 break;
7000 default:
7001 /* turn off perfect filters, enable ATR and reset */
7002 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7003 need_reset = true;
7004
7005 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7006
7007 /* We cannot enable ATR if SR-IOV is enabled */
7008 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7009 break;
7010
7011 /* We cannot enable ATR if we have 2 or more traffic classes */
7012 if (netdev_get_num_tc(netdev) > 1)
7013 break;
7014
7015 /* We cannot enable ATR if RSS is disabled */
7016 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7017 break;
7018
7019 /* A sample rate of 0 indicates ATR disabled */
7020 if (!adapter->atr_sample_rate)
7021 break;
7022
7023 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7024 break;
7025 }
7026
7027 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7028 ixgbe_vlan_strip_enable(adapter);
7029 else
7030 ixgbe_vlan_strip_disable(adapter);
7031
7032 if (changed & NETIF_F_RXALL)
7033 need_reset = true;
7034
7035 netdev->features = features;
7036 if (need_reset)
7037 ixgbe_do_reset(netdev);
7038
7039 return 0;
7040 }
7041
7042 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7043 struct net_device *dev,
7044 const unsigned char *addr,
7045 u16 flags)
7046 {
7047 struct ixgbe_adapter *adapter = netdev_priv(dev);
7048 int err;
7049
7050 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7051 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
7052
7053 /* Hardware does not support aging addresses so if a
7054 * ndm_state is given only allow permanent addresses
7055 */
7056 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7057 pr_info("%s: FDB only supports static addresses\n",
7058 ixgbe_driver_name);
7059 return -EINVAL;
7060 }
7061
7062 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
7063 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7064
7065 if (netdev_uc_count(dev) < rar_uc_entries)
7066 err = dev_uc_add_excl(dev, addr);
7067 else
7068 err = -ENOMEM;
7069 } else if (is_multicast_ether_addr(addr)) {
7070 err = dev_mc_add_excl(dev, addr);
7071 } else {
7072 err = -EINVAL;
7073 }
7074
7075 /* Only return duplicate errors if NLM_F_EXCL is set */
7076 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7077 err = 0;
7078
7079 return err;
7080 }
7081
7082 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7083 struct nlmsghdr *nlh)
7084 {
7085 struct ixgbe_adapter *adapter = netdev_priv(dev);
7086 struct nlattr *attr, *br_spec;
7087 int rem;
7088
7089 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7090 return -EOPNOTSUPP;
7091
7092 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7093
7094 nla_for_each_nested(attr, br_spec, rem) {
7095 __u16 mode;
7096 u32 reg = 0;
7097
7098 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7099 continue;
7100
7101 mode = nla_get_u16(attr);
7102 if (mode == BRIDGE_MODE_VEPA) {
7103 reg = 0;
7104 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7105 } else if (mode == BRIDGE_MODE_VEB) {
7106 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7107 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7108 } else
7109 return -EINVAL;
7110
7111 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7112
7113 e_info(drv, "enabling bridge mode: %s\n",
7114 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7115 }
7116
7117 return 0;
7118 }
7119
7120 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7121 struct net_device *dev,
7122 u32 filter_mask)
7123 {
7124 struct ixgbe_adapter *adapter = netdev_priv(dev);
7125 u16 mode;
7126
7127 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7128 return 0;
7129
7130 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
7131 mode = BRIDGE_MODE_VEB;
7132 else
7133 mode = BRIDGE_MODE_VEPA;
7134
7135 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7136 }
7137
7138 static const struct net_device_ops ixgbe_netdev_ops = {
7139 .ndo_open = ixgbe_open,
7140 .ndo_stop = ixgbe_close,
7141 .ndo_start_xmit = ixgbe_xmit_frame,
7142 #ifdef IXGBE_FCOE
7143 .ndo_select_queue = ixgbe_select_queue,
7144 #endif
7145 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7146 .ndo_validate_addr = eth_validate_addr,
7147 .ndo_set_mac_address = ixgbe_set_mac,
7148 .ndo_change_mtu = ixgbe_change_mtu,
7149 .ndo_tx_timeout = ixgbe_tx_timeout,
7150 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7151 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7152 .ndo_do_ioctl = ixgbe_ioctl,
7153 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7154 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7155 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7156 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7157 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7158 .ndo_get_stats64 = ixgbe_get_stats64,
7159 #ifdef CONFIG_IXGBE_DCB
7160 .ndo_setup_tc = ixgbe_setup_tc,
7161 #endif
7162 #ifdef CONFIG_NET_POLL_CONTROLLER
7163 .ndo_poll_controller = ixgbe_netpoll,
7164 #endif
7165 #ifdef IXGBE_FCOE
7166 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7167 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7168 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7169 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7170 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7171 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7172 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7173 #endif /* IXGBE_FCOE */
7174 .ndo_set_features = ixgbe_set_features,
7175 .ndo_fix_features = ixgbe_fix_features,
7176 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7177 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7178 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
7179 };
7180
7181 /**
7182 * ixgbe_wol_supported - Check whether device supports WoL
7183 * @hw: hw specific details
7184 * @device_id: the device ID
7185 * @subdev_id: the subsystem device ID
7186 *
7187 * This function is used by probe and ethtool to determine
7188 * which devices have WoL support
7189 *
7190 **/
7191 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7192 u16 subdevice_id)
7193 {
7194 struct ixgbe_hw *hw = &adapter->hw;
7195 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7196 int is_wol_supported = 0;
7197
7198 switch (device_id) {
7199 case IXGBE_DEV_ID_82599_SFP:
7200 /* Only these subdevices could supports WOL */
7201 switch (subdevice_id) {
7202 case IXGBE_SUBDEV_ID_82599_560FLR:
7203 /* only support first port */
7204 if (hw->bus.func != 0)
7205 break;
7206 case IXGBE_SUBDEV_ID_82599_SFP:
7207 case IXGBE_SUBDEV_ID_82599_RNDC:
7208 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
7209 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
7210 is_wol_supported = 1;
7211 break;
7212 }
7213 break;
7214 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7215 /* All except this subdevice support WOL */
7216 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7217 is_wol_supported = 1;
7218 break;
7219 case IXGBE_DEV_ID_82599_KX4:
7220 is_wol_supported = 1;
7221 break;
7222 case IXGBE_DEV_ID_X540T:
7223 case IXGBE_DEV_ID_X540T1:
7224 /* check eeprom to see if enabled wol */
7225 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7226 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7227 (hw->bus.func == 0))) {
7228 is_wol_supported = 1;
7229 }
7230 break;
7231 }
7232
7233 return is_wol_supported;
7234 }
7235
7236 /**
7237 * ixgbe_probe - Device Initialization Routine
7238 * @pdev: PCI device information struct
7239 * @ent: entry in ixgbe_pci_tbl
7240 *
7241 * Returns 0 on success, negative on failure
7242 *
7243 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7244 * The OS initialization, configuring of the adapter private structure,
7245 * and a hardware reset occur.
7246 **/
7247 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7248 {
7249 struct net_device *netdev;
7250 struct ixgbe_adapter *adapter = NULL;
7251 struct ixgbe_hw *hw;
7252 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7253 static int cards_found;
7254 int i, err, pci_using_dac;
7255 unsigned int indices = MAX_TX_QUEUES;
7256 u8 part_str[IXGBE_PBANUM_LENGTH];
7257 #ifdef IXGBE_FCOE
7258 u16 device_caps;
7259 #endif
7260 u32 eec;
7261
7262 /* Catch broken hardware that put the wrong VF device ID in
7263 * the PCIe SR-IOV capability.
7264 */
7265 if (pdev->is_virtfn) {
7266 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7267 pci_name(pdev), pdev->vendor, pdev->device);
7268 return -EINVAL;
7269 }
7270
7271 err = pci_enable_device_mem(pdev);
7272 if (err)
7273 return err;
7274
7275 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7276 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7277 pci_using_dac = 1;
7278 } else {
7279 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7280 if (err) {
7281 err = dma_set_coherent_mask(&pdev->dev,
7282 DMA_BIT_MASK(32));
7283 if (err) {
7284 dev_err(&pdev->dev,
7285 "No usable DMA configuration, aborting\n");
7286 goto err_dma;
7287 }
7288 }
7289 pci_using_dac = 0;
7290 }
7291
7292 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7293 IORESOURCE_MEM), ixgbe_driver_name);
7294 if (err) {
7295 dev_err(&pdev->dev,
7296 "pci_request_selected_regions failed 0x%x\n", err);
7297 goto err_pci_reg;
7298 }
7299
7300 pci_enable_pcie_error_reporting(pdev);
7301
7302 pci_set_master(pdev);
7303 pci_save_state(pdev);
7304
7305 if (ii->mac == ixgbe_mac_82598EB) {
7306 #ifdef CONFIG_IXGBE_DCB
7307 /* 8 TC w/ 4 queues per TC */
7308 indices = 4 * MAX_TRAFFIC_CLASS;
7309 #else
7310 indices = IXGBE_MAX_RSS_INDICES;
7311 #endif
7312 }
7313
7314 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7315 if (!netdev) {
7316 err = -ENOMEM;
7317 goto err_alloc_etherdev;
7318 }
7319
7320 SET_NETDEV_DEV(netdev, &pdev->dev);
7321
7322 adapter = netdev_priv(netdev);
7323 pci_set_drvdata(pdev, adapter);
7324
7325 adapter->netdev = netdev;
7326 adapter->pdev = pdev;
7327 hw = &adapter->hw;
7328 hw->back = adapter;
7329 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7330
7331 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7332 pci_resource_len(pdev, 0));
7333 if (!hw->hw_addr) {
7334 err = -EIO;
7335 goto err_ioremap;
7336 }
7337
7338 netdev->netdev_ops = &ixgbe_netdev_ops;
7339 ixgbe_set_ethtool_ops(netdev);
7340 netdev->watchdog_timeo = 5 * HZ;
7341 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7342
7343 adapter->bd_number = cards_found;
7344
7345 /* Setup hw api */
7346 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7347 hw->mac.type = ii->mac;
7348
7349 /* EEPROM */
7350 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7351 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7352 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7353 if (!(eec & (1 << 8)))
7354 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7355
7356 /* PHY */
7357 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7358 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7359 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7360 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7361 hw->phy.mdio.mmds = 0;
7362 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7363 hw->phy.mdio.dev = netdev;
7364 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7365 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7366
7367 ii->get_invariants(hw);
7368
7369 /* setup the private structure */
7370 err = ixgbe_sw_init(adapter);
7371 if (err)
7372 goto err_sw_init;
7373
7374 /* Cache if MNG FW is up so we don't have to read the REG later */
7375 if (hw->mac.ops.mng_fw_enabled)
7376 hw->mng_fw_enabled = hw->mac.ops.mng_fw_enabled(hw);
7377
7378 /* Make it possible the adapter to be woken up via WOL */
7379 switch (adapter->hw.mac.type) {
7380 case ixgbe_mac_82599EB:
7381 case ixgbe_mac_X540:
7382 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7383 break;
7384 default:
7385 break;
7386 }
7387
7388 /*
7389 * If there is a fan on this device and it has failed log the
7390 * failure.
7391 */
7392 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7393 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7394 if (esdp & IXGBE_ESDP_SDP1)
7395 e_crit(probe, "Fan has stopped, replace the adapter\n");
7396 }
7397
7398 if (allow_unsupported_sfp)
7399 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7400
7401 /* reset_hw fills in the perm_addr as well */
7402 hw->phy.reset_if_overtemp = true;
7403 err = hw->mac.ops.reset_hw(hw);
7404 hw->phy.reset_if_overtemp = false;
7405 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7406 hw->mac.type == ixgbe_mac_82598EB) {
7407 err = 0;
7408 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7409 e_dev_err("failed to load because an unsupported SFP+ "
7410 "module type was detected.\n");
7411 e_dev_err("Reload the driver after installing a supported "
7412 "module.\n");
7413 goto err_sw_init;
7414 } else if (err) {
7415 e_dev_err("HW Init failed: %d\n", err);
7416 goto err_sw_init;
7417 }
7418
7419 #ifdef CONFIG_PCI_IOV
7420 /* SR-IOV not supported on the 82598 */
7421 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7422 goto skip_sriov;
7423 /* Mailbox */
7424 ixgbe_init_mbx_params_pf(hw);
7425 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
7426 ixgbe_enable_sriov(adapter);
7427 pci_sriov_set_totalvfs(pdev, 63);
7428 skip_sriov:
7429
7430 #endif
7431 netdev->features = NETIF_F_SG |
7432 NETIF_F_IP_CSUM |
7433 NETIF_F_IPV6_CSUM |
7434 NETIF_F_HW_VLAN_CTAG_TX |
7435 NETIF_F_HW_VLAN_CTAG_RX |
7436 NETIF_F_HW_VLAN_CTAG_FILTER |
7437 NETIF_F_TSO |
7438 NETIF_F_TSO6 |
7439 NETIF_F_RXHASH |
7440 NETIF_F_RXCSUM;
7441
7442 netdev->hw_features = netdev->features;
7443
7444 switch (adapter->hw.mac.type) {
7445 case ixgbe_mac_82599EB:
7446 case ixgbe_mac_X540:
7447 netdev->features |= NETIF_F_SCTP_CSUM;
7448 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7449 NETIF_F_NTUPLE;
7450 break;
7451 default:
7452 break;
7453 }
7454
7455 netdev->hw_features |= NETIF_F_RXALL;
7456
7457 netdev->vlan_features |= NETIF_F_TSO;
7458 netdev->vlan_features |= NETIF_F_TSO6;
7459 netdev->vlan_features |= NETIF_F_IP_CSUM;
7460 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7461 netdev->vlan_features |= NETIF_F_SG;
7462
7463 netdev->priv_flags |= IFF_UNICAST_FLT;
7464 netdev->priv_flags |= IFF_SUPP_NOFCS;
7465
7466 #ifdef CONFIG_IXGBE_DCB
7467 netdev->dcbnl_ops = &dcbnl_ops;
7468 #endif
7469
7470 #ifdef IXGBE_FCOE
7471 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7472 unsigned int fcoe_l;
7473
7474 if (hw->mac.ops.get_device_caps) {
7475 hw->mac.ops.get_device_caps(hw, &device_caps);
7476 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7477 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7478 }
7479
7480
7481 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
7482 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7483
7484 netdev->features |= NETIF_F_FSO |
7485 NETIF_F_FCOE_CRC;
7486
7487 netdev->vlan_features |= NETIF_F_FSO |
7488 NETIF_F_FCOE_CRC |
7489 NETIF_F_FCOE_MTU;
7490 }
7491 #endif /* IXGBE_FCOE */
7492 if (pci_using_dac) {
7493 netdev->features |= NETIF_F_HIGHDMA;
7494 netdev->vlan_features |= NETIF_F_HIGHDMA;
7495 }
7496
7497 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7498 netdev->hw_features |= NETIF_F_LRO;
7499 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7500 netdev->features |= NETIF_F_LRO;
7501
7502 /* make sure the EEPROM is good */
7503 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7504 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7505 err = -EIO;
7506 goto err_sw_init;
7507 }
7508
7509 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7510
7511 if (!is_valid_ether_addr(netdev->dev_addr)) {
7512 e_dev_err("invalid MAC address\n");
7513 err = -EIO;
7514 goto err_sw_init;
7515 }
7516
7517 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7518 (unsigned long) adapter);
7519
7520 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7521 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7522
7523 err = ixgbe_init_interrupt_scheme(adapter);
7524 if (err)
7525 goto err_sw_init;
7526
7527 /* WOL not supported for all devices */
7528 adapter->wol = 0;
7529 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7530 hw->wol_supported = ixgbe_wol_supported(adapter, pdev->device,
7531 pdev->subsystem_device);
7532 if (hw->wol_supported)
7533 adapter->wol = IXGBE_WUFC_MAG;
7534
7535 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7536
7537 /* save off EEPROM version number */
7538 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7539 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7540
7541 /* pick up the PCI bus settings for reporting later */
7542 hw->mac.ops.get_bus_info(hw);
7543 if (hw->device_id == IXGBE_DEV_ID_82599_SFP_SF_QP)
7544 ixgbe_get_parent_bus_info(adapter);
7545
7546 /* print bus type/speed/width info */
7547 e_dev_info("(PCI Express:%s:%s) %pM\n",
7548 (hw->bus.speed == ixgbe_bus_speed_8000 ? "8.0GT/s" :
7549 hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7550 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7551 "Unknown"),
7552 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7553 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7554 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7555 "Unknown"),
7556 netdev->dev_addr);
7557
7558 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7559 if (err)
7560 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7561 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7562 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7563 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7564 part_str);
7565 else
7566 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7567 hw->mac.type, hw->phy.type, part_str);
7568
7569 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7570 e_dev_warn("PCI-Express bandwidth available for this card is "
7571 "not sufficient for optimal performance.\n");
7572 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7573 "is required.\n");
7574 }
7575
7576 /* reset the hardware with the new settings */
7577 err = hw->mac.ops.start_hw(hw);
7578 if (err == IXGBE_ERR_EEPROM_VERSION) {
7579 /* We are running on a pre-production device, log a warning */
7580 e_dev_warn("This device is a pre-production adapter/LOM. "
7581 "Please be aware there may be issues associated "
7582 "with your hardware. If you are experiencing "
7583 "problems please contact your Intel or hardware "
7584 "representative who provided you with this "
7585 "hardware.\n");
7586 }
7587 strcpy(netdev->name, "eth%d");
7588 err = register_netdev(netdev);
7589 if (err)
7590 goto err_register;
7591
7592 /* power down the optics for 82599 SFP+ fiber */
7593 if (hw->mac.ops.disable_tx_laser)
7594 hw->mac.ops.disable_tx_laser(hw);
7595
7596 /* carrier off reporting is important to ethtool even BEFORE open */
7597 netif_carrier_off(netdev);
7598
7599 #ifdef CONFIG_IXGBE_DCA
7600 if (dca_add_requester(&pdev->dev) == 0) {
7601 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7602 ixgbe_setup_dca(adapter);
7603 }
7604 #endif
7605 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7606 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7607 for (i = 0; i < adapter->num_vfs; i++)
7608 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7609 }
7610
7611 /* firmware requires driver version to be 0xFFFFFFFF
7612 * since os does not support feature
7613 */
7614 if (hw->mac.ops.set_fw_drv_ver)
7615 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7616 0xFF);
7617
7618 /* add san mac addr to netdev */
7619 ixgbe_add_sanmac_netdev(netdev);
7620
7621 e_dev_info("%s\n", ixgbe_default_device_descr);
7622 cards_found++;
7623
7624 #ifdef CONFIG_IXGBE_HWMON
7625 if (ixgbe_sysfs_init(adapter))
7626 e_err(probe, "failed to allocate sysfs resources\n");
7627 #endif /* CONFIG_IXGBE_HWMON */
7628
7629 ixgbe_dbg_adapter_init(adapter);
7630
7631 /* Need link setup for MNG FW, else wait for IXGBE_UP */
7632 if (hw->mng_fw_enabled && hw->mac.ops.setup_link)
7633 hw->mac.ops.setup_link(hw,
7634 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
7635 true);
7636
7637 return 0;
7638
7639 err_register:
7640 ixgbe_release_hw_control(adapter);
7641 ixgbe_clear_interrupt_scheme(adapter);
7642 err_sw_init:
7643 ixgbe_disable_sriov(adapter);
7644 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7645 iounmap(hw->hw_addr);
7646 err_ioremap:
7647 free_netdev(netdev);
7648 err_alloc_etherdev:
7649 pci_release_selected_regions(pdev,
7650 pci_select_bars(pdev, IORESOURCE_MEM));
7651 err_pci_reg:
7652 err_dma:
7653 pci_disable_device(pdev);
7654 return err;
7655 }
7656
7657 /**
7658 * ixgbe_remove - Device Removal Routine
7659 * @pdev: PCI device information struct
7660 *
7661 * ixgbe_remove is called by the PCI subsystem to alert the driver
7662 * that it should release a PCI device. The could be caused by a
7663 * Hot-Plug event, or because the driver is going to be removed from
7664 * memory.
7665 **/
7666 static void ixgbe_remove(struct pci_dev *pdev)
7667 {
7668 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7669 struct net_device *netdev = adapter->netdev;
7670
7671 ixgbe_dbg_adapter_exit(adapter);
7672
7673 set_bit(__IXGBE_DOWN, &adapter->state);
7674 cancel_work_sync(&adapter->service_task);
7675
7676
7677 #ifdef CONFIG_IXGBE_DCA
7678 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7679 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7680 dca_remove_requester(&pdev->dev);
7681 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7682 }
7683
7684 #endif
7685 #ifdef CONFIG_IXGBE_HWMON
7686 ixgbe_sysfs_exit(adapter);
7687 #endif /* CONFIG_IXGBE_HWMON */
7688
7689 /* remove the added san mac */
7690 ixgbe_del_sanmac_netdev(netdev);
7691
7692 if (netdev->reg_state == NETREG_REGISTERED)
7693 unregister_netdev(netdev);
7694
7695 #ifdef CONFIG_PCI_IOV
7696 /*
7697 * Only disable SR-IOV on unload if the user specified the now
7698 * deprecated max_vfs module parameter.
7699 */
7700 if (max_vfs)
7701 ixgbe_disable_sriov(adapter);
7702 #endif
7703 ixgbe_clear_interrupt_scheme(adapter);
7704
7705 ixgbe_release_hw_control(adapter);
7706
7707 #ifdef CONFIG_DCB
7708 kfree(adapter->ixgbe_ieee_pfc);
7709 kfree(adapter->ixgbe_ieee_ets);
7710
7711 #endif
7712 iounmap(adapter->hw.hw_addr);
7713 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7714 IORESOURCE_MEM));
7715
7716 e_dev_info("complete\n");
7717
7718 free_netdev(netdev);
7719
7720 pci_disable_pcie_error_reporting(pdev);
7721
7722 pci_disable_device(pdev);
7723 }
7724
7725 /**
7726 * ixgbe_io_error_detected - called when PCI error is detected
7727 * @pdev: Pointer to PCI device
7728 * @state: The current pci connection state
7729 *
7730 * This function is called after a PCI bus error affecting
7731 * this device has been detected.
7732 */
7733 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7734 pci_channel_state_t state)
7735 {
7736 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7737 struct net_device *netdev = adapter->netdev;
7738
7739 #ifdef CONFIG_PCI_IOV
7740 struct pci_dev *bdev, *vfdev;
7741 u32 dw0, dw1, dw2, dw3;
7742 int vf, pos;
7743 u16 req_id, pf_func;
7744
7745 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7746 adapter->num_vfs == 0)
7747 goto skip_bad_vf_detection;
7748
7749 bdev = pdev->bus->self;
7750 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
7751 bdev = bdev->bus->self;
7752
7753 if (!bdev)
7754 goto skip_bad_vf_detection;
7755
7756 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7757 if (!pos)
7758 goto skip_bad_vf_detection;
7759
7760 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7761 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7762 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7763 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7764
7765 req_id = dw1 >> 16;
7766 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7767 if (!(req_id & 0x0080))
7768 goto skip_bad_vf_detection;
7769
7770 pf_func = req_id & 0x01;
7771 if ((pf_func & 1) == (pdev->devfn & 1)) {
7772 unsigned int device_id;
7773
7774 vf = (req_id & 0x7F) >> 1;
7775 e_dev_err("VF %d has caused a PCIe error\n", vf);
7776 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7777 "%8.8x\tdw3: %8.8x\n",
7778 dw0, dw1, dw2, dw3);
7779 switch (adapter->hw.mac.type) {
7780 case ixgbe_mac_82599EB:
7781 device_id = IXGBE_82599_VF_DEVICE_ID;
7782 break;
7783 case ixgbe_mac_X540:
7784 device_id = IXGBE_X540_VF_DEVICE_ID;
7785 break;
7786 default:
7787 device_id = 0;
7788 break;
7789 }
7790
7791 /* Find the pci device of the offending VF */
7792 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
7793 while (vfdev) {
7794 if (vfdev->devfn == (req_id & 0xFF))
7795 break;
7796 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
7797 device_id, vfdev);
7798 }
7799 /*
7800 * There's a slim chance the VF could have been hot plugged,
7801 * so if it is no longer present we don't need to issue the
7802 * VFLR. Just clean up the AER in that case.
7803 */
7804 if (vfdev) {
7805 e_dev_err("Issuing VFLR to VF %d\n", vf);
7806 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7807 /* Free device reference count */
7808 pci_dev_put(vfdev);
7809 }
7810
7811 pci_cleanup_aer_uncorrect_error_status(pdev);
7812 }
7813
7814 /*
7815 * Even though the error may have occurred on the other port
7816 * we still need to increment the vf error reference count for
7817 * both ports because the I/O resume function will be called
7818 * for both of them.
7819 */
7820 adapter->vferr_refcount++;
7821
7822 return PCI_ERS_RESULT_RECOVERED;
7823
7824 skip_bad_vf_detection:
7825 #endif /* CONFIG_PCI_IOV */
7826 netif_device_detach(netdev);
7827
7828 if (state == pci_channel_io_perm_failure)
7829 return PCI_ERS_RESULT_DISCONNECT;
7830
7831 if (netif_running(netdev))
7832 ixgbe_down(adapter);
7833 pci_disable_device(pdev);
7834
7835 /* Request a slot reset. */
7836 return PCI_ERS_RESULT_NEED_RESET;
7837 }
7838
7839 /**
7840 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7841 * @pdev: Pointer to PCI device
7842 *
7843 * Restart the card from scratch, as if from a cold-boot.
7844 */
7845 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7846 {
7847 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7848 pci_ers_result_t result;
7849 int err;
7850
7851 if (pci_enable_device_mem(pdev)) {
7852 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7853 result = PCI_ERS_RESULT_DISCONNECT;
7854 } else {
7855 pci_set_master(pdev);
7856 pci_restore_state(pdev);
7857 pci_save_state(pdev);
7858
7859 pci_wake_from_d3(pdev, false);
7860
7861 ixgbe_reset(adapter);
7862 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7863 result = PCI_ERS_RESULT_RECOVERED;
7864 }
7865
7866 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7867 if (err) {
7868 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7869 "failed 0x%0x\n", err);
7870 /* non-fatal, continue */
7871 }
7872
7873 return result;
7874 }
7875
7876 /**
7877 * ixgbe_io_resume - called when traffic can start flowing again.
7878 * @pdev: Pointer to PCI device
7879 *
7880 * This callback is called when the error recovery driver tells us that
7881 * its OK to resume normal operation.
7882 */
7883 static void ixgbe_io_resume(struct pci_dev *pdev)
7884 {
7885 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7886 struct net_device *netdev = adapter->netdev;
7887
7888 #ifdef CONFIG_PCI_IOV
7889 if (adapter->vferr_refcount) {
7890 e_info(drv, "Resuming after VF err\n");
7891 adapter->vferr_refcount--;
7892 return;
7893 }
7894
7895 #endif
7896 if (netif_running(netdev))
7897 ixgbe_up(adapter);
7898
7899 netif_device_attach(netdev);
7900 }
7901
7902 static const struct pci_error_handlers ixgbe_err_handler = {
7903 .error_detected = ixgbe_io_error_detected,
7904 .slot_reset = ixgbe_io_slot_reset,
7905 .resume = ixgbe_io_resume,
7906 };
7907
7908 static struct pci_driver ixgbe_driver = {
7909 .name = ixgbe_driver_name,
7910 .id_table = ixgbe_pci_tbl,
7911 .probe = ixgbe_probe,
7912 .remove = ixgbe_remove,
7913 #ifdef CONFIG_PM
7914 .suspend = ixgbe_suspend,
7915 .resume = ixgbe_resume,
7916 #endif
7917 .shutdown = ixgbe_shutdown,
7918 .sriov_configure = ixgbe_pci_sriov_configure,
7919 .err_handler = &ixgbe_err_handler
7920 };
7921
7922 /**
7923 * ixgbe_init_module - Driver Registration Routine
7924 *
7925 * ixgbe_init_module is the first routine called when the driver is
7926 * loaded. All it does is register with the PCI subsystem.
7927 **/
7928 static int __init ixgbe_init_module(void)
7929 {
7930 int ret;
7931 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7932 pr_info("%s\n", ixgbe_copyright);
7933
7934 ixgbe_dbg_init();
7935
7936 ret = pci_register_driver(&ixgbe_driver);
7937 if (ret) {
7938 ixgbe_dbg_exit();
7939 return ret;
7940 }
7941
7942 #ifdef CONFIG_IXGBE_DCA
7943 dca_register_notify(&dca_notifier);
7944 #endif
7945
7946 return 0;
7947 }
7948
7949 module_init(ixgbe_init_module);
7950
7951 /**
7952 * ixgbe_exit_module - Driver Exit Cleanup Routine
7953 *
7954 * ixgbe_exit_module is called just before the driver is removed
7955 * from memory.
7956 **/
7957 static void __exit ixgbe_exit_module(void)
7958 {
7959 #ifdef CONFIG_IXGBE_DCA
7960 dca_unregister_notify(&dca_notifier);
7961 #endif
7962 pci_unregister_driver(&ixgbe_driver);
7963
7964 ixgbe_dbg_exit();
7965
7966 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7967 }
7968
7969 #ifdef CONFIG_IXGBE_DCA
7970 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7971 void *p)
7972 {
7973 int ret_val;
7974
7975 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7976 __ixgbe_notify_dca);
7977
7978 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7979 }
7980
7981 #endif /* CONFIG_IXGBE_DCA */
7982
7983 module_exit(ixgbe_exit_module);
7984
7985 /* ixgbe_main.c */
Linux kernel - Deliverables
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