projects / deliverable / linux.git / blob
? search:


3f5c5a4291a6cbf0ffad8c2fc17d320313bb5d86
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/prefetch.h>
48 #include <scsi/fc/fc_fcoe.h>
49
50 #include "ixgbe.h"
51 #include "ixgbe_common.h"
52 #include "ixgbe_dcb_82599.h"
53 #include "ixgbe_sriov.h"
54
55 char ixgbe_driver_name[] = "ixgbe";
56 static const char ixgbe_driver_string[] =
57 "Intel(R) 10 Gigabit PCI Express Network Driver";
58 #define MAJ 3
59 #define MIN 4
60 #define BUILD 8
61 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
62 __stringify(BUILD) "-k"
63 const char ixgbe_driver_version[] = DRV_VERSION;
64 static const char ixgbe_copyright[] =
65 "Copyright (c) 1999-2011 Intel Corporation.";
66
67 static const struct ixgbe_info *ixgbe_info_tbl[] = {
68 [board_82598] = &ixgbe_82598_info,
69 [board_82599] = &ixgbe_82599_info,
70 [board_X540] = &ixgbe_X540_info,
71 };
72
73 /* ixgbe_pci_tbl - PCI Device ID Table
74 *
75 * Wildcard entries (PCI_ANY_ID) should come last
76 * Last entry must be all 0s
77 *
78 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
79 * Class, Class Mask, private data (not used) }
80 */
81 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
108 /* required last entry */
109 {0, }
110 };
111 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
112
113 #ifdef CONFIG_IXGBE_DCA
114 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
115 void *p);
116 static struct notifier_block dca_notifier = {
117 .notifier_call = ixgbe_notify_dca,
118 .next = NULL,
119 .priority = 0
120 };
121 #endif
122
123 #ifdef CONFIG_PCI_IOV
124 static unsigned int max_vfs;
125 module_param(max_vfs, uint, 0);
126 MODULE_PARM_DESC(max_vfs,
127 "Maximum number of virtual functions to allocate per physical function");
128 #endif /* CONFIG_PCI_IOV */
129
130 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
131 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
132 MODULE_LICENSE("GPL");
133 MODULE_VERSION(DRV_VERSION);
134
135 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
136
137 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
138 {
139 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
140 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
141 schedule_work(&adapter->service_task);
142 }
143
144 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
145 {
146 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
147
148 /* flush memory to make sure state is correct before next watchog */
149 smp_mb__before_clear_bit();
150 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
151 }
152
153 struct ixgbe_reg_info {
154 u32 ofs;
155 char *name;
156 };
157
158 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
159
160 /* General Registers */
161 {IXGBE_CTRL, "CTRL"},
162 {IXGBE_STATUS, "STATUS"},
163 {IXGBE_CTRL_EXT, "CTRL_EXT"},
164
165 /* Interrupt Registers */
166 {IXGBE_EICR, "EICR"},
167
168 /* RX Registers */
169 {IXGBE_SRRCTL(0), "SRRCTL"},
170 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
171 {IXGBE_RDLEN(0), "RDLEN"},
172 {IXGBE_RDH(0), "RDH"},
173 {IXGBE_RDT(0), "RDT"},
174 {IXGBE_RXDCTL(0), "RXDCTL"},
175 {IXGBE_RDBAL(0), "RDBAL"},
176 {IXGBE_RDBAH(0), "RDBAH"},
177
178 /* TX Registers */
179 {IXGBE_TDBAL(0), "TDBAL"},
180 {IXGBE_TDBAH(0), "TDBAH"},
181 {IXGBE_TDLEN(0), "TDLEN"},
182 {IXGBE_TDH(0), "TDH"},
183 {IXGBE_TDT(0), "TDT"},
184 {IXGBE_TXDCTL(0), "TXDCTL"},
185
186 /* List Terminator */
187 {}
188 };
189
190
191 /*
192 * ixgbe_regdump - register printout routine
193 */
194 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
195 {
196 int i = 0, j = 0;
197 char rname[16];
198 u32 regs[64];
199
200 switch (reginfo->ofs) {
201 case IXGBE_SRRCTL(0):
202 for (i = 0; i < 64; i++)
203 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
204 break;
205 case IXGBE_DCA_RXCTRL(0):
206 for (i = 0; i < 64; i++)
207 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
208 break;
209 case IXGBE_RDLEN(0):
210 for (i = 0; i < 64; i++)
211 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
212 break;
213 case IXGBE_RDH(0):
214 for (i = 0; i < 64; i++)
215 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
216 break;
217 case IXGBE_RDT(0):
218 for (i = 0; i < 64; i++)
219 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
220 break;
221 case IXGBE_RXDCTL(0):
222 for (i = 0; i < 64; i++)
223 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
224 break;
225 case IXGBE_RDBAL(0):
226 for (i = 0; i < 64; i++)
227 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
228 break;
229 case IXGBE_RDBAH(0):
230 for (i = 0; i < 64; i++)
231 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
232 break;
233 case IXGBE_TDBAL(0):
234 for (i = 0; i < 64; i++)
235 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
236 break;
237 case IXGBE_TDBAH(0):
238 for (i = 0; i < 64; i++)
239 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
240 break;
241 case IXGBE_TDLEN(0):
242 for (i = 0; i < 64; i++)
243 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
244 break;
245 case IXGBE_TDH(0):
246 for (i = 0; i < 64; i++)
247 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
248 break;
249 case IXGBE_TDT(0):
250 for (i = 0; i < 64; i++)
251 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
252 break;
253 case IXGBE_TXDCTL(0):
254 for (i = 0; i < 64; i++)
255 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
256 break;
257 default:
258 pr_info("%-15s %08x\n", reginfo->name,
259 IXGBE_READ_REG(hw, reginfo->ofs));
260 return;
261 }
262
263 for (i = 0; i < 8; i++) {
264 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
265 pr_err("%-15s", rname);
266 for (j = 0; j < 8; j++)
267 pr_cont(" %08x", regs[i*8+j]);
268 pr_cont("\n");
269 }
270
271 }
272
273 /*
274 * ixgbe_dump - Print registers, tx-rings and rx-rings
275 */
276 static void ixgbe_dump(struct ixgbe_adapter *adapter)
277 {
278 struct net_device *netdev = adapter->netdev;
279 struct ixgbe_hw *hw = &adapter->hw;
280 struct ixgbe_reg_info *reginfo;
281 int n = 0;
282 struct ixgbe_ring *tx_ring;
283 struct ixgbe_tx_buffer *tx_buffer_info;
284 union ixgbe_adv_tx_desc *tx_desc;
285 struct my_u0 { u64 a; u64 b; } *u0;
286 struct ixgbe_ring *rx_ring;
287 union ixgbe_adv_rx_desc *rx_desc;
288 struct ixgbe_rx_buffer *rx_buffer_info;
289 u32 staterr;
290 int i = 0;
291
292 if (!netif_msg_hw(adapter))
293 return;
294
295 /* Print netdevice Info */
296 if (netdev) {
297 dev_info(&adapter->pdev->dev, "Net device Info\n");
298 pr_info("Device Name state "
299 "trans_start last_rx\n");
300 pr_info("%-15s %016lX %016lX %016lX\n",
301 netdev->name,
302 netdev->state,
303 netdev->trans_start,
304 netdev->last_rx);
305 }
306
307 /* Print Registers */
308 dev_info(&adapter->pdev->dev, "Register Dump\n");
309 pr_info(" Register Name Value\n");
310 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
311 reginfo->name; reginfo++) {
312 ixgbe_regdump(hw, reginfo);
313 }
314
315 /* Print TX Ring Summary */
316 if (!netdev || !netif_running(netdev))
317 goto exit;
318
319 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
320 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
321 for (n = 0; n < adapter->num_tx_queues; n++) {
322 tx_ring = adapter->tx_ring[n];
323 tx_buffer_info =
324 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
325 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
326 n, tx_ring->next_to_use, tx_ring->next_to_clean,
327 (u64)tx_buffer_info->dma,
328 tx_buffer_info->length,
329 tx_buffer_info->next_to_watch,
330 (u64)tx_buffer_info->time_stamp);
331 }
332
333 /* Print TX Rings */
334 if (!netif_msg_tx_done(adapter))
335 goto rx_ring_summary;
336
337 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
338
339 /* Transmit Descriptor Formats
340 *
341 * Advanced Transmit Descriptor
342 * +--------------------------------------------------------------+
343 * 0 | Buffer Address [63:0] |
344 * +--------------------------------------------------------------+
345 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
346 * +--------------------------------------------------------------+
347 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
348 */
349
350 for (n = 0; n < adapter->num_tx_queues; n++) {
351 tx_ring = adapter->tx_ring[n];
352 pr_info("------------------------------------\n");
353 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
354 pr_info("------------------------------------\n");
355 pr_info("T [desc] [address 63:0 ] "
356 "[PlPOIdStDDt Ln] [bi->dma ] "
357 "leng ntw timestamp bi->skb\n");
358
359 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
360 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
361 tx_buffer_info = &tx_ring->tx_buffer_info[i];
362 u0 = (struct my_u0 *)tx_desc;
363 pr_info("T [0x%03X] %016llX %016llX %016llX"
364 " %04X %p %016llX %p", i,
365 le64_to_cpu(u0->a),
366 le64_to_cpu(u0->b),
367 (u64)tx_buffer_info->dma,
368 tx_buffer_info->length,
369 tx_buffer_info->next_to_watch,
370 (u64)tx_buffer_info->time_stamp,
371 tx_buffer_info->skb);
372 if (i == tx_ring->next_to_use &&
373 i == tx_ring->next_to_clean)
374 pr_cont(" NTC/U\n");
375 else if (i == tx_ring->next_to_use)
376 pr_cont(" NTU\n");
377 else if (i == tx_ring->next_to_clean)
378 pr_cont(" NTC\n");
379 else
380 pr_cont("\n");
381
382 if (netif_msg_pktdata(adapter) &&
383 tx_buffer_info->dma != 0)
384 print_hex_dump(KERN_INFO, "",
385 DUMP_PREFIX_ADDRESS, 16, 1,
386 phys_to_virt(tx_buffer_info->dma),
387 tx_buffer_info->length, true);
388 }
389 }
390
391 /* Print RX Rings Summary */
392 rx_ring_summary:
393 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
394 pr_info("Queue [NTU] [NTC]\n");
395 for (n = 0; n < adapter->num_rx_queues; n++) {
396 rx_ring = adapter->rx_ring[n];
397 pr_info("%5d %5X %5X\n",
398 n, rx_ring->next_to_use, rx_ring->next_to_clean);
399 }
400
401 /* Print RX Rings */
402 if (!netif_msg_rx_status(adapter))
403 goto exit;
404
405 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
406
407 /* Advanced Receive Descriptor (Read) Format
408 * 63 1 0
409 * +-----------------------------------------------------+
410 * 0 | Packet Buffer Address [63:1] |A0/NSE|
411 * +----------------------------------------------+------+
412 * 8 | Header Buffer Address [63:1] | DD |
413 * +-----------------------------------------------------+
414 *
415 *
416 * Advanced Receive Descriptor (Write-Back) Format
417 *
418 * 63 48 47 32 31 30 21 20 16 15 4 3 0
419 * +------------------------------------------------------+
420 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
421 * | Checksum Ident | | | | Type | Type |
422 * +------------------------------------------------------+
423 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
424 * +------------------------------------------------------+
425 * 63 48 47 32 31 20 19 0
426 */
427 for (n = 0; n < adapter->num_rx_queues; n++) {
428 rx_ring = adapter->rx_ring[n];
429 pr_info("------------------------------------\n");
430 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
431 pr_info("------------------------------------\n");
432 pr_info("R [desc] [ PktBuf A0] "
433 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
434 "<-- Adv Rx Read format\n");
435 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
436 "[vl er S cks ln] ---------------- [bi->skb] "
437 "<-- Adv Rx Write-Back format\n");
438
439 for (i = 0; i < rx_ring->count; i++) {
440 rx_buffer_info = &rx_ring->rx_buffer_info[i];
441 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
442 u0 = (struct my_u0 *)rx_desc;
443 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
444 if (staterr & IXGBE_RXD_STAT_DD) {
445 /* Descriptor Done */
446 pr_info("RWB[0x%03X] %016llX "
447 "%016llX ---------------- %p", i,
448 le64_to_cpu(u0->a),
449 le64_to_cpu(u0->b),
450 rx_buffer_info->skb);
451 } else {
452 pr_info("R [0x%03X] %016llX "
453 "%016llX %016llX %p", i,
454 le64_to_cpu(u0->a),
455 le64_to_cpu(u0->b),
456 (u64)rx_buffer_info->dma,
457 rx_buffer_info->skb);
458
459 if (netif_msg_pktdata(adapter)) {
460 print_hex_dump(KERN_INFO, "",
461 DUMP_PREFIX_ADDRESS, 16, 1,
462 phys_to_virt(rx_buffer_info->dma),
463 rx_ring->rx_buf_len, true);
464
465 if (rx_ring->rx_buf_len
466 < IXGBE_RXBUFFER_2K)
467 print_hex_dump(KERN_INFO, "",
468 DUMP_PREFIX_ADDRESS, 16, 1,
469 phys_to_virt(
470 rx_buffer_info->page_dma +
471 rx_buffer_info->page_offset
472 ),
473 PAGE_SIZE/2, true);
474 }
475 }
476
477 if (i == rx_ring->next_to_use)
478 pr_cont(" NTU\n");
479 else if (i == rx_ring->next_to_clean)
480 pr_cont(" NTC\n");
481 else
482 pr_cont("\n");
483
484 }
485 }
486
487 exit:
488 return;
489 }
490
491 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
492 {
493 u32 ctrl_ext;
494
495 /* Let firmware take over control of h/w */
496 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
497 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
498 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
499 }
500
501 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
502 {
503 u32 ctrl_ext;
504
505 /* Let firmware know the driver has taken over */
506 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
507 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
508 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
509 }
510
511 /*
512 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
513 * @adapter: pointer to adapter struct
514 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
515 * @queue: queue to map the corresponding interrupt to
516 * @msix_vector: the vector to map to the corresponding queue
517 *
518 */
519 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
520 u8 queue, u8 msix_vector)
521 {
522 u32 ivar, index;
523 struct ixgbe_hw *hw = &adapter->hw;
524 switch (hw->mac.type) {
525 case ixgbe_mac_82598EB:
526 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
527 if (direction == -1)
528 direction = 0;
529 index = (((direction * 64) + queue) >> 2) & 0x1F;
530 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
531 ivar &= ~(0xFF << (8 * (queue & 0x3)));
532 ivar |= (msix_vector << (8 * (queue & 0x3)));
533 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
534 break;
535 case ixgbe_mac_82599EB:
536 case ixgbe_mac_X540:
537 if (direction == -1) {
538 /* other causes */
539 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
540 index = ((queue & 1) * 8);
541 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
542 ivar &= ~(0xFF << index);
543 ivar |= (msix_vector << index);
544 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
545 break;
546 } else {
547 /* tx or rx causes */
548 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
549 index = ((16 * (queue & 1)) + (8 * direction));
550 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
551 ivar &= ~(0xFF << index);
552 ivar |= (msix_vector << index);
553 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
554 break;
555 }
556 default:
557 break;
558 }
559 }
560
561 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
562 u64 qmask)
563 {
564 u32 mask;
565
566 switch (adapter->hw.mac.type) {
567 case ixgbe_mac_82598EB:
568 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
569 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
570 break;
571 case ixgbe_mac_82599EB:
572 case ixgbe_mac_X540:
573 mask = (qmask & 0xFFFFFFFF);
574 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
575 mask = (qmask >> 32);
576 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
577 break;
578 default:
579 break;
580 }
581 }
582
583 static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
584 struct ixgbe_tx_buffer *tx_buffer)
585 {
586 if (tx_buffer->dma) {
587 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
588 dma_unmap_page(ring->dev,
589 tx_buffer->dma,
590 tx_buffer->length,
591 DMA_TO_DEVICE);
592 else
593 dma_unmap_single(ring->dev,
594 tx_buffer->dma,
595 tx_buffer->length,
596 DMA_TO_DEVICE);
597 }
598 tx_buffer->dma = 0;
599 }
600
601 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
602 struct ixgbe_tx_buffer *tx_buffer_info)
603 {
604 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
605 if (tx_buffer_info->skb)
606 dev_kfree_skb_any(tx_buffer_info->skb);
607 tx_buffer_info->skb = NULL;
608 /* tx_buffer_info must be completely set up in the transmit path */
609 }
610
611 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
612 {
613 struct ixgbe_hw *hw = &adapter->hw;
614 struct ixgbe_hw_stats *hwstats = &adapter->stats;
615 u32 data = 0;
616 u32 xoff[8] = {0};
617 int i;
618
619 if ((hw->fc.current_mode == ixgbe_fc_full) ||
620 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
621 switch (hw->mac.type) {
622 case ixgbe_mac_82598EB:
623 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
624 break;
625 default:
626 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
627 }
628 hwstats->lxoffrxc += data;
629
630 /* refill credits (no tx hang) if we received xoff */
631 if (!data)
632 return;
633
634 for (i = 0; i < adapter->num_tx_queues; i++)
635 clear_bit(__IXGBE_HANG_CHECK_ARMED,
636 &adapter->tx_ring[i]->state);
637 return;
638 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
639 return;
640
641 /* update stats for each tc, only valid with PFC enabled */
642 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
643 switch (hw->mac.type) {
644 case ixgbe_mac_82598EB:
645 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
646 break;
647 default:
648 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
649 }
650 hwstats->pxoffrxc[i] += xoff[i];
651 }
652
653 /* disarm tx queues that have received xoff frames */
654 for (i = 0; i < adapter->num_tx_queues; i++) {
655 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
656 u8 tc = tx_ring->dcb_tc;
657
658 if (xoff[tc])
659 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
660 }
661 }
662
663 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
664 {
665 return ring->tx_stats.completed;
666 }
667
668 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
669 {
670 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
671 struct ixgbe_hw *hw = &adapter->hw;
672
673 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
674 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
675
676 if (head != tail)
677 return (head < tail) ?
678 tail - head : (tail + ring->count - head);
679
680 return 0;
681 }
682
683 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
684 {
685 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
686 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
687 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
688 bool ret = false;
689
690 clear_check_for_tx_hang(tx_ring);
691
692 /*
693 * Check for a hung queue, but be thorough. This verifies
694 * that a transmit has been completed since the previous
695 * check AND there is at least one packet pending. The
696 * ARMED bit is set to indicate a potential hang. The
697 * bit is cleared if a pause frame is received to remove
698 * false hang detection due to PFC or 802.3x frames. By
699 * requiring this to fail twice we avoid races with
700 * pfc clearing the ARMED bit and conditions where we
701 * run the check_tx_hang logic with a transmit completion
702 * pending but without time to complete it yet.
703 */
704 if ((tx_done_old == tx_done) && tx_pending) {
705 /* make sure it is true for two checks in a row */
706 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
707 &tx_ring->state);
708 } else {
709 /* update completed stats and continue */
710 tx_ring->tx_stats.tx_done_old = tx_done;
711 /* reset the countdown */
712 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
713 }
714
715 return ret;
716 }
717
718 /**
719 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
720 * @adapter: driver private struct
721 **/
722 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
723 {
724
725 /* Do the reset outside of interrupt context */
726 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
727 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
728 ixgbe_service_event_schedule(adapter);
729 }
730 }
731
732 /**
733 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
734 * @q_vector: structure containing interrupt and ring information
735 * @tx_ring: tx ring to clean
736 **/
737 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
738 struct ixgbe_ring *tx_ring)
739 {
740 struct ixgbe_adapter *adapter = q_vector->adapter;
741 struct ixgbe_tx_buffer *tx_buffer;
742 union ixgbe_adv_tx_desc *tx_desc;
743 unsigned int total_bytes = 0, total_packets = 0;
744 unsigned int budget = q_vector->tx.work_limit;
745 u16 i = tx_ring->next_to_clean;
746
747 tx_buffer = &tx_ring->tx_buffer_info[i];
748 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
749
750 for (; budget; budget--) {
751 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
752
753 /* if next_to_watch is not set then there is no work pending */
754 if (!eop_desc)
755 break;
756
757 /* if DD is not set pending work has not been completed */
758 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
759 break;
760
761 /* count the packet as being completed */
762 tx_ring->tx_stats.completed++;
763
764 /* clear next_to_watch to prevent false hangs */
765 tx_buffer->next_to_watch = NULL;
766
767 /* prevent any other reads prior to eop_desc being verified */
768 rmb();
769
770 do {
771 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
772 tx_desc->wb.status = 0;
773 if (likely(tx_desc == eop_desc)) {
774 eop_desc = NULL;
775 dev_kfree_skb_any(tx_buffer->skb);
776 tx_buffer->skb = NULL;
777
778 total_bytes += tx_buffer->bytecount;
779 total_packets += tx_buffer->gso_segs;
780 }
781
782 tx_buffer++;
783 tx_desc++;
784 i++;
785 if (unlikely(i == tx_ring->count)) {
786 i = 0;
787
788 tx_buffer = tx_ring->tx_buffer_info;
789 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
790 }
791
792 } while (eop_desc);
793 }
794
795 tx_ring->next_to_clean = i;
796 u64_stats_update_begin(&tx_ring->syncp);
797 tx_ring->stats.bytes += total_bytes;
798 tx_ring->stats.packets += total_packets;
799 u64_stats_update_end(&tx_ring->syncp);
800 q_vector->tx.total_bytes += total_bytes;
801 q_vector->tx.total_packets += total_packets;
802
803 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
804 /* schedule immediate reset if we believe we hung */
805 struct ixgbe_hw *hw = &adapter->hw;
806 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
807 e_err(drv, "Detected Tx Unit Hang\n"
808 " Tx Queue <%d>\n"
809 " TDH, TDT <%x>, <%x>\n"
810 " next_to_use <%x>\n"
811 " next_to_clean <%x>\n"
812 "tx_buffer_info[next_to_clean]\n"
813 " time_stamp <%lx>\n"
814 " jiffies <%lx>\n",
815 tx_ring->queue_index,
816 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
817 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
818 tx_ring->next_to_use, i,
819 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
820
821 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
822
823 e_info(probe,
824 "tx hang %d detected on queue %d, resetting adapter\n",
825 adapter->tx_timeout_count + 1, tx_ring->queue_index);
826
827 /* schedule immediate reset if we believe we hung */
828 ixgbe_tx_timeout_reset(adapter);
829
830 /* the adapter is about to reset, no point in enabling stuff */
831 return true;
832 }
833
834 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
835 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
836 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
837 /* Make sure that anybody stopping the queue after this
838 * sees the new next_to_clean.
839 */
840 smp_mb();
841 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
842 !test_bit(__IXGBE_DOWN, &adapter->state)) {
843 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
844 ++tx_ring->tx_stats.restart_queue;
845 }
846 }
847
848 return !!budget;
849 }
850
851 #ifdef CONFIG_IXGBE_DCA
852 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
853 struct ixgbe_ring *rx_ring,
854 int cpu)
855 {
856 struct ixgbe_hw *hw = &adapter->hw;
857 u32 rxctrl;
858 u8 reg_idx = rx_ring->reg_idx;
859
860 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
861 switch (hw->mac.type) {
862 case ixgbe_mac_82598EB:
863 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
864 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
865 break;
866 case ixgbe_mac_82599EB:
867 case ixgbe_mac_X540:
868 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
869 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
870 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
871 break;
872 default:
873 break;
874 }
875 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
876 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
877 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
878 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
879 }
880
881 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
882 struct ixgbe_ring *tx_ring,
883 int cpu)
884 {
885 struct ixgbe_hw *hw = &adapter->hw;
886 u32 txctrl;
887 u8 reg_idx = tx_ring->reg_idx;
888
889 switch (hw->mac.type) {
890 case ixgbe_mac_82598EB:
891 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
892 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
893 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
894 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
895 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
896 break;
897 case ixgbe_mac_82599EB:
898 case ixgbe_mac_X540:
899 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
900 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
901 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
902 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
903 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
904 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
905 break;
906 default:
907 break;
908 }
909 }
910
911 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
912 {
913 struct ixgbe_adapter *adapter = q_vector->adapter;
914 struct ixgbe_ring *ring;
915 int cpu = get_cpu();
916
917 if (q_vector->cpu == cpu)
918 goto out_no_update;
919
920 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
921 ixgbe_update_tx_dca(adapter, ring, cpu);
922
923 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
924 ixgbe_update_rx_dca(adapter, ring, cpu);
925
926 q_vector->cpu = cpu;
927 out_no_update:
928 put_cpu();
929 }
930
931 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
932 {
933 int num_q_vectors;
934 int i;
935
936 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
937 return;
938
939 /* always use CB2 mode, difference is masked in the CB driver */
940 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
941
942 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
943 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
944 else
945 num_q_vectors = 1;
946
947 for (i = 0; i < num_q_vectors; i++) {
948 adapter->q_vector[i]->cpu = -1;
949 ixgbe_update_dca(adapter->q_vector[i]);
950 }
951 }
952
953 static int __ixgbe_notify_dca(struct device *dev, void *data)
954 {
955 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
956 unsigned long event = *(unsigned long *)data;
957
958 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
959 return 0;
960
961 switch (event) {
962 case DCA_PROVIDER_ADD:
963 /* if we're already enabled, don't do it again */
964 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
965 break;
966 if (dca_add_requester(dev) == 0) {
967 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
968 ixgbe_setup_dca(adapter);
969 break;
970 }
971 /* Fall Through since DCA is disabled. */
972 case DCA_PROVIDER_REMOVE:
973 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
974 dca_remove_requester(dev);
975 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
976 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
977 }
978 break;
979 }
980
981 return 0;
982 }
983 #endif /* CONFIG_IXGBE_DCA */
984
985 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
986 struct sk_buff *skb)
987 {
988 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
989 }
990
991 /**
992 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
993 * @adapter: address of board private structure
994 * @rx_desc: advanced rx descriptor
995 *
996 * Returns : true if it is FCoE pkt
997 */
998 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
999 union ixgbe_adv_rx_desc *rx_desc)
1000 {
1001 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1002
1003 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1004 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1005 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1006 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1007 }
1008
1009 /**
1010 * ixgbe_receive_skb - Send a completed packet up the stack
1011 * @adapter: board private structure
1012 * @skb: packet to send up
1013 * @status: hardware indication of status of receive
1014 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1015 * @rx_desc: rx descriptor
1016 **/
1017 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1018 struct sk_buff *skb, u8 status,
1019 struct ixgbe_ring *ring,
1020 union ixgbe_adv_rx_desc *rx_desc)
1021 {
1022 struct ixgbe_adapter *adapter = q_vector->adapter;
1023 struct napi_struct *napi = &q_vector->napi;
1024 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1025 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1026
1027 if (is_vlan && (tag & VLAN_VID_MASK))
1028 __vlan_hwaccel_put_tag(skb, tag);
1029
1030 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1031 napi_gro_receive(napi, skb);
1032 else
1033 netif_rx(skb);
1034 }
1035
1036 /**
1037 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1038 * @adapter: address of board private structure
1039 * @status_err: hardware indication of status of receive
1040 * @skb: skb currently being received and modified
1041 * @status_err: status error value of last descriptor in packet
1042 **/
1043 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1044 union ixgbe_adv_rx_desc *rx_desc,
1045 struct sk_buff *skb,
1046 u32 status_err)
1047 {
1048 skb->ip_summed = CHECKSUM_NONE;
1049
1050 /* Rx csum disabled */
1051 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1052 return;
1053
1054 /* if IP and error */
1055 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1056 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1057 adapter->hw_csum_rx_error++;
1058 return;
1059 }
1060
1061 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1062 return;
1063
1064 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1065 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1066
1067 /*
1068 * 82599 errata, UDP frames with a 0 checksum can be marked as
1069 * checksum errors.
1070 */
1071 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1072 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1073 return;
1074
1075 adapter->hw_csum_rx_error++;
1076 return;
1077 }
1078
1079 /* It must be a TCP or UDP packet with a valid checksum */
1080 skb->ip_summed = CHECKSUM_UNNECESSARY;
1081 }
1082
1083 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1084 {
1085 /*
1086 * Force memory writes to complete before letting h/w
1087 * know there are new descriptors to fetch. (Only
1088 * applicable for weak-ordered memory model archs,
1089 * such as IA-64).
1090 */
1091 wmb();
1092 writel(val, rx_ring->tail);
1093 }
1094
1095 /**
1096 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1097 * @rx_ring: ring to place buffers on
1098 * @cleaned_count: number of buffers to replace
1099 **/
1100 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1101 {
1102 union ixgbe_adv_rx_desc *rx_desc;
1103 struct ixgbe_rx_buffer *bi;
1104 struct sk_buff *skb;
1105 u16 i = rx_ring->next_to_use;
1106
1107 /* do nothing if no valid netdev defined */
1108 if (!rx_ring->netdev)
1109 return;
1110
1111 while (cleaned_count--) {
1112 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1113 bi = &rx_ring->rx_buffer_info[i];
1114 skb = bi->skb;
1115
1116 if (!skb) {
1117 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1118 rx_ring->rx_buf_len);
1119 if (!skb) {
1120 rx_ring->rx_stats.alloc_rx_buff_failed++;
1121 goto no_buffers;
1122 }
1123 /* initialize queue mapping */
1124 skb_record_rx_queue(skb, rx_ring->queue_index);
1125 bi->skb = skb;
1126 }
1127
1128 if (!bi->dma) {
1129 bi->dma = dma_map_single(rx_ring->dev,
1130 skb->data,
1131 rx_ring->rx_buf_len,
1132 DMA_FROM_DEVICE);
1133 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1134 rx_ring->rx_stats.alloc_rx_buff_failed++;
1135 bi->dma = 0;
1136 goto no_buffers;
1137 }
1138 }
1139
1140 if (ring_is_ps_enabled(rx_ring)) {
1141 if (!bi->page) {
1142 bi->page = netdev_alloc_page(rx_ring->netdev);
1143 if (!bi->page) {
1144 rx_ring->rx_stats.alloc_rx_page_failed++;
1145 goto no_buffers;
1146 }
1147 }
1148
1149 if (!bi->page_dma) {
1150 /* use a half page if we're re-using */
1151 bi->page_offset ^= PAGE_SIZE / 2;
1152 bi->page_dma = dma_map_page(rx_ring->dev,
1153 bi->page,
1154 bi->page_offset,
1155 PAGE_SIZE / 2,
1156 DMA_FROM_DEVICE);
1157 if (dma_mapping_error(rx_ring->dev,
1158 bi->page_dma)) {
1159 rx_ring->rx_stats.alloc_rx_page_failed++;
1160 bi->page_dma = 0;
1161 goto no_buffers;
1162 }
1163 }
1164
1165 /* Refresh the desc even if buffer_addrs didn't change
1166 * because each write-back erases this info. */
1167 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1168 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1169 } else {
1170 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1171 rx_desc->read.hdr_addr = 0;
1172 }
1173
1174 i++;
1175 if (i == rx_ring->count)
1176 i = 0;
1177 }
1178
1179 no_buffers:
1180 if (rx_ring->next_to_use != i) {
1181 rx_ring->next_to_use = i;
1182 ixgbe_release_rx_desc(rx_ring, i);
1183 }
1184 }
1185
1186 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1187 {
1188 /* HW will not DMA in data larger than the given buffer, even if it
1189 * parses the (NFS, of course) header to be larger. In that case, it
1190 * fills the header buffer and spills the rest into the page.
1191 */
1192 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1193 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1194 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1195 if (hlen > IXGBE_RX_HDR_SIZE)
1196 hlen = IXGBE_RX_HDR_SIZE;
1197 return hlen;
1198 }
1199
1200 /**
1201 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1202 * @skb: pointer to the last skb in the rsc queue
1203 *
1204 * This function changes a queue full of hw rsc buffers into a completed
1205 * packet. It uses the ->prev pointers to find the first packet and then
1206 * turns it into the frag list owner.
1207 **/
1208 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1209 {
1210 unsigned int frag_list_size = 0;
1211 unsigned int skb_cnt = 1;
1212
1213 while (skb->prev) {
1214 struct sk_buff *prev = skb->prev;
1215 frag_list_size += skb->len;
1216 skb->prev = NULL;
1217 skb = prev;
1218 skb_cnt++;
1219 }
1220
1221 skb_shinfo(skb)->frag_list = skb->next;
1222 skb->next = NULL;
1223 skb->len += frag_list_size;
1224 skb->data_len += frag_list_size;
1225 skb->truesize += frag_list_size;
1226 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1227
1228 return skb;
1229 }
1230
1231 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1232 {
1233 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1234 IXGBE_RXDADV_RSCCNT_MASK);
1235 }
1236
1237 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1238 struct ixgbe_ring *rx_ring,
1239 int budget)
1240 {
1241 struct ixgbe_adapter *adapter = q_vector->adapter;
1242 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1243 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1244 struct sk_buff *skb;
1245 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1246 const int current_node = numa_node_id();
1247 #ifdef IXGBE_FCOE
1248 int ddp_bytes = 0;
1249 #endif /* IXGBE_FCOE */
1250 u32 staterr;
1251 u16 i;
1252 u16 cleaned_count = 0;
1253 bool pkt_is_rsc = false;
1254
1255 i = rx_ring->next_to_clean;
1256 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1257 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1258
1259 while (staterr & IXGBE_RXD_STAT_DD) {
1260 u32 upper_len = 0;
1261
1262 rmb(); /* read descriptor and rx_buffer_info after status DD */
1263
1264 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1265
1266 skb = rx_buffer_info->skb;
1267 rx_buffer_info->skb = NULL;
1268 prefetch(skb->data);
1269
1270 if (ring_is_rsc_enabled(rx_ring))
1271 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1272
1273 /* linear means we are building an skb from multiple pages */
1274 if (!skb_is_nonlinear(skb)) {
1275 u16 hlen;
1276 if (pkt_is_rsc &&
1277 !(staterr & IXGBE_RXD_STAT_EOP) &&
1278 !skb->prev) {
1279 /*
1280 * When HWRSC is enabled, delay unmapping
1281 * of the first packet. It carries the
1282 * header information, HW may still
1283 * access the header after the writeback.
1284 * Only unmap it when EOP is reached
1285 */
1286 IXGBE_RSC_CB(skb)->delay_unmap = true;
1287 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1288 } else {
1289 dma_unmap_single(rx_ring->dev,
1290 rx_buffer_info->dma,
1291 rx_ring->rx_buf_len,
1292 DMA_FROM_DEVICE);
1293 }
1294 rx_buffer_info->dma = 0;
1295
1296 if (ring_is_ps_enabled(rx_ring)) {
1297 hlen = ixgbe_get_hlen(rx_desc);
1298 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1299 } else {
1300 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1301 }
1302
1303 skb_put(skb, hlen);
1304 } else {
1305 /* assume packet split since header is unmapped */
1306 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1307 }
1308
1309 if (upper_len) {
1310 dma_unmap_page(rx_ring->dev,
1311 rx_buffer_info->page_dma,
1312 PAGE_SIZE / 2,
1313 DMA_FROM_DEVICE);
1314 rx_buffer_info->page_dma = 0;
1315 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1316 rx_buffer_info->page,
1317 rx_buffer_info->page_offset,
1318 upper_len);
1319
1320 if ((page_count(rx_buffer_info->page) == 1) &&
1321 (page_to_nid(rx_buffer_info->page) == current_node))
1322 get_page(rx_buffer_info->page);
1323 else
1324 rx_buffer_info->page = NULL;
1325
1326 skb->len += upper_len;
1327 skb->data_len += upper_len;
1328 skb->truesize += upper_len;
1329 }
1330
1331 i++;
1332 if (i == rx_ring->count)
1333 i = 0;
1334
1335 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1336 prefetch(next_rxd);
1337 cleaned_count++;
1338
1339 if (pkt_is_rsc) {
1340 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1341 IXGBE_RXDADV_NEXTP_SHIFT;
1342 next_buffer = &rx_ring->rx_buffer_info[nextp];
1343 } else {
1344 next_buffer = &rx_ring->rx_buffer_info[i];
1345 }
1346
1347 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1348 if (ring_is_ps_enabled(rx_ring)) {
1349 rx_buffer_info->skb = next_buffer->skb;
1350 rx_buffer_info->dma = next_buffer->dma;
1351 next_buffer->skb = skb;
1352 next_buffer->dma = 0;
1353 } else {
1354 skb->next = next_buffer->skb;
1355 skb->next->prev = skb;
1356 }
1357 rx_ring->rx_stats.non_eop_descs++;
1358 goto next_desc;
1359 }
1360
1361 if (skb->prev) {
1362 skb = ixgbe_transform_rsc_queue(skb);
1363 /* if we got here without RSC the packet is invalid */
1364 if (!pkt_is_rsc) {
1365 __pskb_trim(skb, 0);
1366 rx_buffer_info->skb = skb;
1367 goto next_desc;
1368 }
1369 }
1370
1371 if (ring_is_rsc_enabled(rx_ring)) {
1372 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1373 dma_unmap_single(rx_ring->dev,
1374 IXGBE_RSC_CB(skb)->dma,
1375 rx_ring->rx_buf_len,
1376 DMA_FROM_DEVICE);
1377 IXGBE_RSC_CB(skb)->dma = 0;
1378 IXGBE_RSC_CB(skb)->delay_unmap = false;
1379 }
1380 }
1381 if (pkt_is_rsc) {
1382 if (ring_is_ps_enabled(rx_ring))
1383 rx_ring->rx_stats.rsc_count +=
1384 skb_shinfo(skb)->nr_frags;
1385 else
1386 rx_ring->rx_stats.rsc_count +=
1387 IXGBE_RSC_CB(skb)->skb_cnt;
1388 rx_ring->rx_stats.rsc_flush++;
1389 }
1390
1391 /* ERR_MASK will only have valid bits if EOP set */
1392 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1393 dev_kfree_skb_any(skb);
1394 goto next_desc;
1395 }
1396
1397 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
1398 if (adapter->netdev->features & NETIF_F_RXHASH)
1399 ixgbe_rx_hash(rx_desc, skb);
1400
1401 /* probably a little skewed due to removing CRC */
1402 total_rx_bytes += skb->len;
1403 total_rx_packets++;
1404
1405 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1406 #ifdef IXGBE_FCOE
1407 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1408 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1409 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1410 staterr);
1411 if (!ddp_bytes) {
1412 dev_kfree_skb_any(skb);
1413 goto next_desc;
1414 }
1415 }
1416 #endif /* IXGBE_FCOE */
1417 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1418
1419 budget--;
1420 next_desc:
1421 rx_desc->wb.upper.status_error = 0;
1422
1423 if (!budget)
1424 break;
1425
1426 /* return some buffers to hardware, one at a time is too slow */
1427 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1428 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1429 cleaned_count = 0;
1430 }
1431
1432 /* use prefetched values */
1433 rx_desc = next_rxd;
1434 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1435 }
1436
1437 rx_ring->next_to_clean = i;
1438 cleaned_count = ixgbe_desc_unused(rx_ring);
1439
1440 if (cleaned_count)
1441 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1442
1443 #ifdef IXGBE_FCOE
1444 /* include DDPed FCoE data */
1445 if (ddp_bytes > 0) {
1446 unsigned int mss;
1447
1448 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1449 sizeof(struct fc_frame_header) -
1450 sizeof(struct fcoe_crc_eof);
1451 if (mss > 512)
1452 mss &= ~511;
1453 total_rx_bytes += ddp_bytes;
1454 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1455 }
1456 #endif /* IXGBE_FCOE */
1457
1458 u64_stats_update_begin(&rx_ring->syncp);
1459 rx_ring->stats.packets += total_rx_packets;
1460 rx_ring->stats.bytes += total_rx_bytes;
1461 u64_stats_update_end(&rx_ring->syncp);
1462 q_vector->rx.total_packets += total_rx_packets;
1463 q_vector->rx.total_bytes += total_rx_bytes;
1464
1465 return !!budget;
1466 }
1467
1468 /**
1469 * ixgbe_configure_msix - Configure MSI-X hardware
1470 * @adapter: board private structure
1471 *
1472 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1473 * interrupts.
1474 **/
1475 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1476 {
1477 struct ixgbe_q_vector *q_vector;
1478 int q_vectors, v_idx;
1479 u32 mask;
1480
1481 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1482
1483 /* Populate MSIX to EITR Select */
1484 if (adapter->num_vfs > 32) {
1485 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1486 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1487 }
1488
1489 /*
1490 * Populate the IVAR table and set the ITR values to the
1491 * corresponding register.
1492 */
1493 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1494 struct ixgbe_ring *ring;
1495 q_vector = adapter->q_vector[v_idx];
1496
1497 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1498 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1499
1500 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1501 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1502
1503 if (q_vector->tx.ring && !q_vector->rx.ring) {
1504 /* tx only vector */
1505 if (adapter->tx_itr_setting == 1)
1506 q_vector->itr = IXGBE_10K_ITR;
1507 else
1508 q_vector->itr = adapter->tx_itr_setting;
1509 } else {
1510 /* rx or rx/tx vector */
1511 if (adapter->rx_itr_setting == 1)
1512 q_vector->itr = IXGBE_20K_ITR;
1513 else
1514 q_vector->itr = adapter->rx_itr_setting;
1515 }
1516
1517 ixgbe_write_eitr(q_vector);
1518 }
1519
1520 switch (adapter->hw.mac.type) {
1521 case ixgbe_mac_82598EB:
1522 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1523 v_idx);
1524 break;
1525 case ixgbe_mac_82599EB:
1526 case ixgbe_mac_X540:
1527 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1528 break;
1529 default:
1530 break;
1531 }
1532 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1533
1534 /* set up to autoclear timer, and the vectors */
1535 mask = IXGBE_EIMS_ENABLE_MASK;
1536 mask &= ~(IXGBE_EIMS_OTHER |
1537 IXGBE_EIMS_MAILBOX |
1538 IXGBE_EIMS_LSC);
1539
1540 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1541 }
1542
1543 enum latency_range {
1544 lowest_latency = 0,
1545 low_latency = 1,
1546 bulk_latency = 2,
1547 latency_invalid = 255
1548 };
1549
1550 /**
1551 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1552 * @q_vector: structure containing interrupt and ring information
1553 * @ring_container: structure containing ring performance data
1554 *
1555 * Stores a new ITR value based on packets and byte
1556 * counts during the last interrupt. The advantage of per interrupt
1557 * computation is faster updates and more accurate ITR for the current
1558 * traffic pattern. Constants in this function were computed
1559 * based on theoretical maximum wire speed and thresholds were set based
1560 * on testing data as well as attempting to minimize response time
1561 * while increasing bulk throughput.
1562 * this functionality is controlled by the InterruptThrottleRate module
1563 * parameter (see ixgbe_param.c)
1564 **/
1565 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1566 struct ixgbe_ring_container *ring_container)
1567 {
1568 u64 bytes_perint;
1569 struct ixgbe_adapter *adapter = q_vector->adapter;
1570 int bytes = ring_container->total_bytes;
1571 int packets = ring_container->total_packets;
1572 u32 timepassed_us;
1573 u8 itr_setting = ring_container->itr;
1574
1575 if (packets == 0)
1576 return;
1577
1578 /* simple throttlerate management
1579 * 0-20MB/s lowest (100000 ints/s)
1580 * 20-100MB/s low (20000 ints/s)
1581 * 100-1249MB/s bulk (8000 ints/s)
1582 */
1583 /* what was last interrupt timeslice? */
1584 timepassed_us = q_vector->itr >> 2;
1585 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1586
1587 switch (itr_setting) {
1588 case lowest_latency:
1589 if (bytes_perint > adapter->eitr_low)
1590 itr_setting = low_latency;
1591 break;
1592 case low_latency:
1593 if (bytes_perint > adapter->eitr_high)
1594 itr_setting = bulk_latency;
1595 else if (bytes_perint <= adapter->eitr_low)
1596 itr_setting = lowest_latency;
1597 break;
1598 case bulk_latency:
1599 if (bytes_perint <= adapter->eitr_high)
1600 itr_setting = low_latency;
1601 break;
1602 }
1603
1604 /* clear work counters since we have the values we need */
1605 ring_container->total_bytes = 0;
1606 ring_container->total_packets = 0;
1607
1608 /* write updated itr to ring container */
1609 ring_container->itr = itr_setting;
1610 }
1611
1612 /**
1613 * ixgbe_write_eitr - write EITR register in hardware specific way
1614 * @q_vector: structure containing interrupt and ring information
1615 *
1616 * This function is made to be called by ethtool and by the driver
1617 * when it needs to update EITR registers at runtime. Hardware
1618 * specific quirks/differences are taken care of here.
1619 */
1620 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1621 {
1622 struct ixgbe_adapter *adapter = q_vector->adapter;
1623 struct ixgbe_hw *hw = &adapter->hw;
1624 int v_idx = q_vector->v_idx;
1625 u32 itr_reg = q_vector->itr;
1626
1627 switch (adapter->hw.mac.type) {
1628 case ixgbe_mac_82598EB:
1629 /* must write high and low 16 bits to reset counter */
1630 itr_reg |= (itr_reg << 16);
1631 break;
1632 case ixgbe_mac_82599EB:
1633 case ixgbe_mac_X540:
1634 /*
1635 * set the WDIS bit to not clear the timer bits and cause an
1636 * immediate assertion of the interrupt
1637 */
1638 itr_reg |= IXGBE_EITR_CNT_WDIS;
1639 break;
1640 default:
1641 break;
1642 }
1643 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1644 }
1645
1646 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1647 {
1648 u32 new_itr = q_vector->itr;
1649 u8 current_itr;
1650
1651 ixgbe_update_itr(q_vector, &q_vector->tx);
1652 ixgbe_update_itr(q_vector, &q_vector->rx);
1653
1654 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1655
1656 switch (current_itr) {
1657 /* counts and packets in update_itr are dependent on these numbers */
1658 case lowest_latency:
1659 new_itr = IXGBE_100K_ITR;
1660 break;
1661 case low_latency:
1662 new_itr = IXGBE_20K_ITR;
1663 break;
1664 case bulk_latency:
1665 new_itr = IXGBE_8K_ITR;
1666 break;
1667 default:
1668 break;
1669 }
1670
1671 if (new_itr != q_vector->itr) {
1672 /* do an exponential smoothing */
1673 new_itr = (10 * new_itr * q_vector->itr) /
1674 ((9 * new_itr) + q_vector->itr);
1675
1676 /* save the algorithm value here */
1677 q_vector->itr = new_itr & IXGBE_MAX_EITR;
1678
1679 ixgbe_write_eitr(q_vector);
1680 }
1681 }
1682
1683 /**
1684 * ixgbe_check_overtemp_subtask - check for over tempurature
1685 * @adapter: pointer to adapter
1686 **/
1687 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1688 {
1689 struct ixgbe_hw *hw = &adapter->hw;
1690 u32 eicr = adapter->interrupt_event;
1691
1692 if (test_bit(__IXGBE_DOWN, &adapter->state))
1693 return;
1694
1695 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1696 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1697 return;
1698
1699 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1700
1701 switch (hw->device_id) {
1702 case IXGBE_DEV_ID_82599_T3_LOM:
1703 /*
1704 * Since the warning interrupt is for both ports
1705 * we don't have to check if:
1706 * - This interrupt wasn't for our port.
1707 * - We may have missed the interrupt so always have to
1708 * check if we got a LSC
1709 */
1710 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1711 !(eicr & IXGBE_EICR_LSC))
1712 return;
1713
1714 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1715 u32 autoneg;
1716 bool link_up = false;
1717
1718 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1719
1720 if (link_up)
1721 return;
1722 }
1723
1724 /* Check if this is not due to overtemp */
1725 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1726 return;
1727
1728 break;
1729 default:
1730 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1731 return;
1732 break;
1733 }
1734 e_crit(drv,
1735 "Network adapter has been stopped because it has over heated. "
1736 "Restart the computer. If the problem persists, "
1737 "power off the system and replace the adapter\n");
1738
1739 adapter->interrupt_event = 0;
1740 }
1741
1742 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1743 {
1744 struct ixgbe_hw *hw = &adapter->hw;
1745
1746 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1747 (eicr & IXGBE_EICR_GPI_SDP1)) {
1748 e_crit(probe, "Fan has stopped, replace the adapter\n");
1749 /* write to clear the interrupt */
1750 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1751 }
1752 }
1753
1754 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
1755 {
1756 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1757 return;
1758
1759 switch (adapter->hw.mac.type) {
1760 case ixgbe_mac_82599EB:
1761 /*
1762 * Need to check link state so complete overtemp check
1763 * on service task
1764 */
1765 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
1766 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
1767 adapter->interrupt_event = eicr;
1768 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1769 ixgbe_service_event_schedule(adapter);
1770 return;
1771 }
1772 return;
1773 case ixgbe_mac_X540:
1774 if (!(eicr & IXGBE_EICR_TS))
1775 return;
1776 break;
1777 default:
1778 return;
1779 }
1780
1781 e_crit(drv,
1782 "Network adapter has been stopped because it has over heated. "
1783 "Restart the computer. If the problem persists, "
1784 "power off the system and replace the adapter\n");
1785 }
1786
1787 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1788 {
1789 struct ixgbe_hw *hw = &adapter->hw;
1790
1791 if (eicr & IXGBE_EICR_GPI_SDP2) {
1792 /* Clear the interrupt */
1793 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1794 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1795 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1796 ixgbe_service_event_schedule(adapter);
1797 }
1798 }
1799
1800 if (eicr & IXGBE_EICR_GPI_SDP1) {
1801 /* Clear the interrupt */
1802 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1803 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1804 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1805 ixgbe_service_event_schedule(adapter);
1806 }
1807 }
1808 }
1809
1810 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1811 {
1812 struct ixgbe_hw *hw = &adapter->hw;
1813
1814 adapter->lsc_int++;
1815 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1816 adapter->link_check_timeout = jiffies;
1817 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1818 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1819 IXGBE_WRITE_FLUSH(hw);
1820 ixgbe_service_event_schedule(adapter);
1821 }
1822 }
1823
1824 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1825 u64 qmask)
1826 {
1827 u32 mask;
1828 struct ixgbe_hw *hw = &adapter->hw;
1829
1830 switch (hw->mac.type) {
1831 case ixgbe_mac_82598EB:
1832 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1833 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1834 break;
1835 case ixgbe_mac_82599EB:
1836 case ixgbe_mac_X540:
1837 mask = (qmask & 0xFFFFFFFF);
1838 if (mask)
1839 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1840 mask = (qmask >> 32);
1841 if (mask)
1842 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1843 break;
1844 default:
1845 break;
1846 }
1847 /* skip the flush */
1848 }
1849
1850 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1851 u64 qmask)
1852 {
1853 u32 mask;
1854 struct ixgbe_hw *hw = &adapter->hw;
1855
1856 switch (hw->mac.type) {
1857 case ixgbe_mac_82598EB:
1858 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1859 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1860 break;
1861 case ixgbe_mac_82599EB:
1862 case ixgbe_mac_X540:
1863 mask = (qmask & 0xFFFFFFFF);
1864 if (mask)
1865 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1866 mask = (qmask >> 32);
1867 if (mask)
1868 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1869 break;
1870 default:
1871 break;
1872 }
1873 /* skip the flush */
1874 }
1875
1876 /**
1877 * ixgbe_irq_enable - Enable default interrupt generation settings
1878 * @adapter: board private structure
1879 **/
1880 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
1881 bool flush)
1882 {
1883 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1884
1885 /* don't reenable LSC while waiting for link */
1886 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
1887 mask &= ~IXGBE_EIMS_LSC;
1888
1889 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
1890 switch (adapter->hw.mac.type) {
1891 case ixgbe_mac_82599EB:
1892 mask |= IXGBE_EIMS_GPI_SDP0;
1893 break;
1894 case ixgbe_mac_X540:
1895 mask |= IXGBE_EIMS_TS;
1896 break;
1897 default:
1898 break;
1899 }
1900 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1901 mask |= IXGBE_EIMS_GPI_SDP1;
1902 switch (adapter->hw.mac.type) {
1903 case ixgbe_mac_82599EB:
1904 mask |= IXGBE_EIMS_GPI_SDP1;
1905 mask |= IXGBE_EIMS_GPI_SDP2;
1906 case ixgbe_mac_X540:
1907 mask |= IXGBE_EIMS_ECC;
1908 mask |= IXGBE_EIMS_MAILBOX;
1909 break;
1910 default:
1911 break;
1912 }
1913 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
1914 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
1915 mask |= IXGBE_EIMS_FLOW_DIR;
1916
1917 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1918 if (queues)
1919 ixgbe_irq_enable_queues(adapter, ~0);
1920 if (flush)
1921 IXGBE_WRITE_FLUSH(&adapter->hw);
1922 }
1923
1924 static irqreturn_t ixgbe_msix_other(int irq, void *data)
1925 {
1926 struct ixgbe_adapter *adapter = data;
1927 struct ixgbe_hw *hw = &adapter->hw;
1928 u32 eicr;
1929
1930 /*
1931 * Workaround for Silicon errata. Use clear-by-write instead
1932 * of clear-by-read. Reading with EICS will return the
1933 * interrupt causes without clearing, which later be done
1934 * with the write to EICR.
1935 */
1936 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1937 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1938
1939 if (eicr & IXGBE_EICR_LSC)
1940 ixgbe_check_lsc(adapter);
1941
1942 if (eicr & IXGBE_EICR_MAILBOX)
1943 ixgbe_msg_task(adapter);
1944
1945 switch (hw->mac.type) {
1946 case ixgbe_mac_82599EB:
1947 case ixgbe_mac_X540:
1948 if (eicr & IXGBE_EICR_ECC)
1949 e_info(link, "Received unrecoverable ECC Err, please "
1950 "reboot\n");
1951 /* Handle Flow Director Full threshold interrupt */
1952 if (eicr & IXGBE_EICR_FLOW_DIR) {
1953 int reinit_count = 0;
1954 int i;
1955 for (i = 0; i < adapter->num_tx_queues; i++) {
1956 struct ixgbe_ring *ring = adapter->tx_ring[i];
1957 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1958 &ring->state))
1959 reinit_count++;
1960 }
1961 if (reinit_count) {
1962 /* no more flow director interrupts until after init */
1963 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1964 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1965 ixgbe_service_event_schedule(adapter);
1966 }
1967 }
1968 ixgbe_check_sfp_event(adapter, eicr);
1969 ixgbe_check_overtemp_event(adapter, eicr);
1970 break;
1971 default:
1972 break;
1973 }
1974
1975 ixgbe_check_fan_failure(adapter, eicr);
1976
1977 /* re-enable the original interrupt state, no lsc, no queues */
1978 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1979 ixgbe_irq_enable(adapter, false, false);
1980
1981 return IRQ_HANDLED;
1982 }
1983
1984 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
1985 {
1986 struct ixgbe_q_vector *q_vector = data;
1987
1988 /* EIAM disabled interrupts (on this vector) for us */
1989
1990 if (q_vector->rx.ring || q_vector->tx.ring)
1991 napi_schedule(&q_vector->napi);
1992
1993 return IRQ_HANDLED;
1994 }
1995
1996 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1997 int r_idx)
1998 {
1999 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2000 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2001
2002 rx_ring->q_vector = q_vector;
2003 rx_ring->next = q_vector->rx.ring;
2004 q_vector->rx.ring = rx_ring;
2005 q_vector->rx.count++;
2006 }
2007
2008 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2009 int t_idx)
2010 {
2011 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2012 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2013
2014 tx_ring->q_vector = q_vector;
2015 tx_ring->next = q_vector->tx.ring;
2016 q_vector->tx.ring = tx_ring;
2017 q_vector->tx.count++;
2018 q_vector->tx.work_limit = a->tx_work_limit;
2019 }
2020
2021 /**
2022 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2023 * @adapter: board private structure to initialize
2024 *
2025 * This function maps descriptor rings to the queue-specific vectors
2026 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2027 * one vector per ring/queue, but on a constrained vector budget, we
2028 * group the rings as "efficiently" as possible. You would add new
2029 * mapping configurations in here.
2030 **/
2031 static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2032 {
2033 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2034 int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2035 int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
2036 int v_start = 0;
2037
2038 /* only one q_vector if MSI-X is disabled. */
2039 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2040 q_vectors = 1;
2041
2042 /*
2043 * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2044 * group them so there are multiple queues per vector.
2045 *
2046 * Re-adjusting *qpv takes care of the remainder.
2047 */
2048 for (; v_start < q_vectors && rxr_remaining; v_start++) {
2049 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2050 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
2051 map_vector_to_rxq(adapter, v_start, rxr_idx);
2052 }
2053
2054 /*
2055 * If there are not enough q_vectors for each ring to have it's own
2056 * vector then we must pair up Rx/Tx on a each vector
2057 */
2058 if ((v_start + txr_remaining) > q_vectors)
2059 v_start = 0;
2060
2061 for (; v_start < q_vectors && txr_remaining; v_start++) {
2062 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2063 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2064 map_vector_to_txq(adapter, v_start, txr_idx);
2065 }
2066 }
2067
2068 /**
2069 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2070 * @adapter: board private structure
2071 *
2072 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2073 * interrupts from the kernel.
2074 **/
2075 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2076 {
2077 struct net_device *netdev = adapter->netdev;
2078 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2079 int vector, err;
2080 int ri = 0, ti = 0;
2081
2082 for (vector = 0; vector < q_vectors; vector++) {
2083 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2084 struct msix_entry *entry = &adapter->msix_entries[vector];
2085
2086 if (q_vector->tx.ring && q_vector->rx.ring) {
2087 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2088 "%s-%s-%d", netdev->name, "TxRx", ri++);
2089 ti++;
2090 } else if (q_vector->rx.ring) {
2091 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2092 "%s-%s-%d", netdev->name, "rx", ri++);
2093 } else if (q_vector->tx.ring) {
2094 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2095 "%s-%s-%d", netdev->name, "tx", ti++);
2096 } else {
2097 /* skip this unused q_vector */
2098 continue;
2099 }
2100 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2101 q_vector->name, q_vector);
2102 if (err) {
2103 e_err(probe, "request_irq failed for MSIX interrupt "
2104 "Error: %d\n", err);
2105 goto free_queue_irqs;
2106 }
2107 /* If Flow Director is enabled, set interrupt affinity */
2108 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2109 /* assign the mask for this irq */
2110 irq_set_affinity_hint(entry->vector,
2111 q_vector->affinity_mask);
2112 }
2113 }
2114
2115 err = request_irq(adapter->msix_entries[vector].vector,
2116 ixgbe_msix_other, 0, netdev->name, adapter);
2117 if (err) {
2118 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2119 goto free_queue_irqs;
2120 }
2121
2122 return 0;
2123
2124 free_queue_irqs:
2125 while (vector) {
2126 vector--;
2127 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2128 NULL);
2129 free_irq(adapter->msix_entries[vector].vector,
2130 adapter->q_vector[vector]);
2131 }
2132 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2133 pci_disable_msix(adapter->pdev);
2134 kfree(adapter->msix_entries);
2135 adapter->msix_entries = NULL;
2136 return err;
2137 }
2138
2139 /**
2140 * ixgbe_intr - legacy mode Interrupt Handler
2141 * @irq: interrupt number
2142 * @data: pointer to a network interface device structure
2143 **/
2144 static irqreturn_t ixgbe_intr(int irq, void *data)
2145 {
2146 struct ixgbe_adapter *adapter = data;
2147 struct ixgbe_hw *hw = &adapter->hw;
2148 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2149 u32 eicr;
2150
2151 /*
2152 * Workaround for silicon errata on 82598. Mask the interrupts
2153 * before the read of EICR.
2154 */
2155 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2156
2157 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2158 * therefore no explict interrupt disable is necessary */
2159 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2160 if (!eicr) {
2161 /*
2162 * shared interrupt alert!
2163 * make sure interrupts are enabled because the read will
2164 * have disabled interrupts due to EIAM
2165 * finish the workaround of silicon errata on 82598. Unmask
2166 * the interrupt that we masked before the EICR read.
2167 */
2168 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2169 ixgbe_irq_enable(adapter, true, true);
2170 return IRQ_NONE; /* Not our interrupt */
2171 }
2172
2173 if (eicr & IXGBE_EICR_LSC)
2174 ixgbe_check_lsc(adapter);
2175
2176 switch (hw->mac.type) {
2177 case ixgbe_mac_82599EB:
2178 case ixgbe_mac_X540:
2179 ixgbe_check_sfp_event(adapter, eicr);
2180 ixgbe_check_overtemp_event(adapter, eicr);
2181 break;
2182 default:
2183 break;
2184 }
2185
2186 ixgbe_check_fan_failure(adapter, eicr);
2187
2188 if (napi_schedule_prep(&(q_vector->napi))) {
2189 /* would disable interrupts here but EIAM disabled it */
2190 __napi_schedule(&(q_vector->napi));
2191 }
2192
2193 /*
2194 * re-enable link(maybe) and non-queue interrupts, no flush.
2195 * ixgbe_poll will re-enable the queue interrupts
2196 */
2197
2198 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2199 ixgbe_irq_enable(adapter, false, false);
2200
2201 return IRQ_HANDLED;
2202 }
2203
2204 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2205 {
2206 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2207 int i;
2208
2209 /* legacy and MSI only use one vector */
2210 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2211 q_vectors = 1;
2212
2213 for (i = 0; i < adapter->num_rx_queues; i++) {
2214 adapter->rx_ring[i]->q_vector = NULL;
2215 adapter->rx_ring[i]->next = NULL;
2216 }
2217 for (i = 0; i < adapter->num_tx_queues; i++) {
2218 adapter->tx_ring[i]->q_vector = NULL;
2219 adapter->tx_ring[i]->next = NULL;
2220 }
2221
2222 for (i = 0; i < q_vectors; i++) {
2223 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2224 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2225 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
2226 }
2227 }
2228
2229 /**
2230 * ixgbe_request_irq - initialize interrupts
2231 * @adapter: board private structure
2232 *
2233 * Attempts to configure interrupts using the best available
2234 * capabilities of the hardware and kernel.
2235 **/
2236 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2237 {
2238 struct net_device *netdev = adapter->netdev;
2239 int err;
2240
2241 /* map all of the rings to the q_vectors */
2242 ixgbe_map_rings_to_vectors(adapter);
2243
2244 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2245 err = ixgbe_request_msix_irqs(adapter);
2246 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2247 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2248 netdev->name, adapter);
2249 else
2250 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2251 netdev->name, adapter);
2252
2253 if (err) {
2254 e_err(probe, "request_irq failed, Error %d\n", err);
2255
2256 /* place q_vectors and rings back into a known good state */
2257 ixgbe_reset_q_vectors(adapter);
2258 }
2259
2260 return err;
2261 }
2262
2263 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2264 {
2265 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2266 int i, q_vectors;
2267
2268 q_vectors = adapter->num_msix_vectors;
2269 i = q_vectors - 1;
2270 free_irq(adapter->msix_entries[i].vector, adapter);
2271 i--;
2272
2273 for (; i >= 0; i--) {
2274 /* free only the irqs that were actually requested */
2275 if (!adapter->q_vector[i]->rx.ring &&
2276 !adapter->q_vector[i]->tx.ring)
2277 continue;
2278
2279 /* clear the affinity_mask in the IRQ descriptor */
2280 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2281 NULL);
2282
2283 free_irq(adapter->msix_entries[i].vector,
2284 adapter->q_vector[i]);
2285 }
2286 } else {
2287 free_irq(adapter->pdev->irq, adapter);
2288 }
2289
2290 /* clear q_vector state information */
2291 ixgbe_reset_q_vectors(adapter);
2292 }
2293
2294 /**
2295 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2296 * @adapter: board private structure
2297 **/
2298 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2299 {
2300 switch (adapter->hw.mac.type) {
2301 case ixgbe_mac_82598EB:
2302 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2303 break;
2304 case ixgbe_mac_82599EB:
2305 case ixgbe_mac_X540:
2306 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2307 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2308 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2309 break;
2310 default:
2311 break;
2312 }
2313 IXGBE_WRITE_FLUSH(&adapter->hw);
2314 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2315 int i;
2316 for (i = 0; i < adapter->num_msix_vectors; i++)
2317 synchronize_irq(adapter->msix_entries[i].vector);
2318 } else {
2319 synchronize_irq(adapter->pdev->irq);
2320 }
2321 }
2322
2323 /**
2324 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2325 *
2326 **/
2327 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2328 {
2329 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2330
2331 /* rx/tx vector */
2332 if (adapter->rx_itr_setting == 1)
2333 q_vector->itr = IXGBE_20K_ITR;
2334 else
2335 q_vector->itr = adapter->rx_itr_setting;
2336
2337 ixgbe_write_eitr(q_vector);
2338
2339 ixgbe_set_ivar(adapter, 0, 0, 0);
2340 ixgbe_set_ivar(adapter, 1, 0, 0);
2341
2342 e_info(hw, "Legacy interrupt IVAR setup done\n");
2343 }
2344
2345 /**
2346 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2347 * @adapter: board private structure
2348 * @ring: structure containing ring specific data
2349 *
2350 * Configure the Tx descriptor ring after a reset.
2351 **/
2352 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2353 struct ixgbe_ring *ring)
2354 {
2355 struct ixgbe_hw *hw = &adapter->hw;
2356 u64 tdba = ring->dma;
2357 int wait_loop = 10;
2358 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2359 u8 reg_idx = ring->reg_idx;
2360
2361 /* disable queue to avoid issues while updating state */
2362 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2363 IXGBE_WRITE_FLUSH(hw);
2364
2365 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2366 (tdba & DMA_BIT_MASK(32)));
2367 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2368 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2369 ring->count * sizeof(union ixgbe_adv_tx_desc));
2370 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2371 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2372 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2373
2374 /*
2375 * set WTHRESH to encourage burst writeback, it should not be set
2376 * higher than 1 when ITR is 0 as it could cause false TX hangs
2377 *
2378 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2379 * to or less than the number of on chip descriptors, which is
2380 * currently 40.
2381 */
2382 if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
2383 txdctl |= (1 << 16); /* WTHRESH = 1 */
2384 else
2385 txdctl |= (8 << 16); /* WTHRESH = 8 */
2386
2387 /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2388 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2389 32; /* PTHRESH = 32 */
2390
2391 /* reinitialize flowdirector state */
2392 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2393 adapter->atr_sample_rate) {
2394 ring->atr_sample_rate = adapter->atr_sample_rate;
2395 ring->atr_count = 0;
2396 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2397 } else {
2398 ring->atr_sample_rate = 0;
2399 }
2400
2401 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2402
2403 /* enable queue */
2404 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2405
2406 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2407 if (hw->mac.type == ixgbe_mac_82598EB &&
2408 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2409 return;
2410
2411 /* poll to verify queue is enabled */
2412 do {
2413 usleep_range(1000, 2000);
2414 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2415 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2416 if (!wait_loop)
2417 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2418 }
2419
2420 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2421 {
2422 struct ixgbe_hw *hw = &adapter->hw;
2423 u32 rttdcs;
2424 u32 reg;
2425 u8 tcs = netdev_get_num_tc(adapter->netdev);
2426
2427 if (hw->mac.type == ixgbe_mac_82598EB)
2428 return;
2429
2430 /* disable the arbiter while setting MTQC */
2431 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2432 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2433 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2434
2435 /* set transmit pool layout */
2436 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2437 case (IXGBE_FLAG_SRIOV_ENABLED):
2438 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2439 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2440 break;
2441 default:
2442 if (!tcs)
2443 reg = IXGBE_MTQC_64Q_1PB;
2444 else if (tcs <= 4)
2445 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2446 else
2447 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2448
2449 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2450
2451 /* Enable Security TX Buffer IFG for multiple pb */
2452 if (tcs) {
2453 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2454 reg |= IXGBE_SECTX_DCB;
2455 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2456 }
2457 break;
2458 }
2459
2460 /* re-enable the arbiter */
2461 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2462 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2463 }
2464
2465 /**
2466 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2467 * @adapter: board private structure
2468 *
2469 * Configure the Tx unit of the MAC after a reset.
2470 **/
2471 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2472 {
2473 struct ixgbe_hw *hw = &adapter->hw;
2474 u32 dmatxctl;
2475 u32 i;
2476
2477 ixgbe_setup_mtqc(adapter);
2478
2479 if (hw->mac.type != ixgbe_mac_82598EB) {
2480 /* DMATXCTL.EN must be before Tx queues are enabled */
2481 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2482 dmatxctl |= IXGBE_DMATXCTL_TE;
2483 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2484 }
2485
2486 /* Setup the HW Tx Head and Tail descriptor pointers */
2487 for (i = 0; i < adapter->num_tx_queues; i++)
2488 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2489 }
2490
2491 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2492
2493 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2494 struct ixgbe_ring *rx_ring)
2495 {
2496 u32 srrctl;
2497 u8 reg_idx = rx_ring->reg_idx;
2498
2499 switch (adapter->hw.mac.type) {
2500 case ixgbe_mac_82598EB: {
2501 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2502 const int mask = feature[RING_F_RSS].mask;
2503 reg_idx = reg_idx & mask;
2504 }
2505 break;
2506 case ixgbe_mac_82599EB:
2507 case ixgbe_mac_X540:
2508 default:
2509 break;
2510 }
2511
2512 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2513
2514 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2515 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2516 if (adapter->num_vfs)
2517 srrctl |= IXGBE_SRRCTL_DROP_EN;
2518
2519 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2520 IXGBE_SRRCTL_BSIZEHDR_MASK;
2521
2522 if (ring_is_ps_enabled(rx_ring)) {
2523 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2524 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2525 #else
2526 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2527 #endif
2528 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2529 } else {
2530 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2531 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2532 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2533 }
2534
2535 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2536 }
2537
2538 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2539 {
2540 struct ixgbe_hw *hw = &adapter->hw;
2541 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2542 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2543 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2544 u32 mrqc = 0, reta = 0;
2545 u32 rxcsum;
2546 int i, j;
2547 u8 tcs = netdev_get_num_tc(adapter->netdev);
2548 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2549
2550 if (tcs)
2551 maxq = min(maxq, adapter->num_tx_queues / tcs);
2552
2553 /* Fill out hash function seeds */
2554 for (i = 0; i < 10; i++)
2555 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2556
2557 /* Fill out redirection table */
2558 for (i = 0, j = 0; i < 128; i++, j++) {
2559 if (j == maxq)
2560 j = 0;
2561 /* reta = 4-byte sliding window of
2562 * 0x00..(indices-1)(indices-1)00..etc. */
2563 reta = (reta << 8) | (j * 0x11);
2564 if ((i & 3) == 3)
2565 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2566 }
2567
2568 /* Disable indicating checksum in descriptor, enables RSS hash */
2569 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2570 rxcsum |= IXGBE_RXCSUM_PCSD;
2571 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2572
2573 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2574 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2575 mrqc = IXGBE_MRQC_RSSEN;
2576 } else {
2577 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2578 | IXGBE_FLAG_SRIOV_ENABLED);
2579
2580 switch (mask) {
2581 case (IXGBE_FLAG_RSS_ENABLED):
2582 if (!tcs)
2583 mrqc = IXGBE_MRQC_RSSEN;
2584 else if (tcs <= 4)
2585 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2586 else
2587 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2588 break;
2589 case (IXGBE_FLAG_SRIOV_ENABLED):
2590 mrqc = IXGBE_MRQC_VMDQEN;
2591 break;
2592 default:
2593 break;
2594 }
2595 }
2596
2597 /* Perform hash on these packet types */
2598 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2599 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2600 | IXGBE_MRQC_RSS_FIELD_IPV6
2601 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2602
2603 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2604 }
2605
2606 /**
2607 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2608 * @adapter: address of board private structure
2609 * @index: index of ring to set
2610 **/
2611 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2612 struct ixgbe_ring *ring)
2613 {
2614 struct ixgbe_hw *hw = &adapter->hw;
2615 u32 rscctrl;
2616 int rx_buf_len;
2617 u8 reg_idx = ring->reg_idx;
2618
2619 if (!ring_is_rsc_enabled(ring))
2620 return;
2621
2622 rx_buf_len = ring->rx_buf_len;
2623 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2624 rscctrl |= IXGBE_RSCCTL_RSCEN;
2625 /*
2626 * we must limit the number of descriptors so that the
2627 * total size of max desc * buf_len is not greater
2628 * than 65535
2629 */
2630 if (ring_is_ps_enabled(ring)) {
2631 #if (MAX_SKB_FRAGS > 16)
2632 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2633 #elif (MAX_SKB_FRAGS > 8)
2634 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2635 #elif (MAX_SKB_FRAGS > 4)
2636 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2637 #else
2638 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2639 #endif
2640 } else {
2641 if (rx_buf_len < IXGBE_RXBUFFER_4K)
2642 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2643 else if (rx_buf_len < IXGBE_RXBUFFER_8K)
2644 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2645 else
2646 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2647 }
2648 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2649 }
2650
2651 /**
2652 * ixgbe_set_uta - Set unicast filter table address
2653 * @adapter: board private structure
2654 *
2655 * The unicast table address is a register array of 32-bit registers.
2656 * The table is meant to be used in a way similar to how the MTA is used
2657 * however due to certain limitations in the hardware it is necessary to
2658 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2659 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2660 **/
2661 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2662 {
2663 struct ixgbe_hw *hw = &adapter->hw;
2664 int i;
2665
2666 /* The UTA table only exists on 82599 hardware and newer */
2667 if (hw->mac.type < ixgbe_mac_82599EB)
2668 return;
2669
2670 /* we only need to do this if VMDq is enabled */
2671 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2672 return;
2673
2674 for (i = 0; i < 128; i++)
2675 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2676 }
2677
2678 #define IXGBE_MAX_RX_DESC_POLL 10
2679 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2680 struct ixgbe_ring *ring)
2681 {
2682 struct ixgbe_hw *hw = &adapter->hw;
2683 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2684 u32 rxdctl;
2685 u8 reg_idx = ring->reg_idx;
2686
2687 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2688 if (hw->mac.type == ixgbe_mac_82598EB &&
2689 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2690 return;
2691
2692 do {
2693 usleep_range(1000, 2000);
2694 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2695 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2696
2697 if (!wait_loop) {
2698 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2699 "the polling period\n", reg_idx);
2700 }
2701 }
2702
2703 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2704 struct ixgbe_ring *ring)
2705 {
2706 struct ixgbe_hw *hw = &adapter->hw;
2707 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2708 u32 rxdctl;
2709 u8 reg_idx = ring->reg_idx;
2710
2711 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2712 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2713
2714 /* write value back with RXDCTL.ENABLE bit cleared */
2715 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2716
2717 if (hw->mac.type == ixgbe_mac_82598EB &&
2718 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2719 return;
2720
2721 /* the hardware may take up to 100us to really disable the rx queue */
2722 do {
2723 udelay(10);
2724 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2725 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2726
2727 if (!wait_loop) {
2728 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2729 "the polling period\n", reg_idx);
2730 }
2731 }
2732
2733 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2734 struct ixgbe_ring *ring)
2735 {
2736 struct ixgbe_hw *hw = &adapter->hw;
2737 u64 rdba = ring->dma;
2738 u32 rxdctl;
2739 u8 reg_idx = ring->reg_idx;
2740
2741 /* disable queue to avoid issues while updating state */
2742 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2743 ixgbe_disable_rx_queue(adapter, ring);
2744
2745 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2746 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2747 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2748 ring->count * sizeof(union ixgbe_adv_rx_desc));
2749 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2750 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2751 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2752
2753 ixgbe_configure_srrctl(adapter, ring);
2754 ixgbe_configure_rscctl(adapter, ring);
2755
2756 /* If operating in IOV mode set RLPML for X540 */
2757 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2758 hw->mac.type == ixgbe_mac_X540) {
2759 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2760 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2761 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2762 }
2763
2764 if (hw->mac.type == ixgbe_mac_82598EB) {
2765 /*
2766 * enable cache line friendly hardware writes:
2767 * PTHRESH=32 descriptors (half the internal cache),
2768 * this also removes ugly rx_no_buffer_count increment
2769 * HTHRESH=4 descriptors (to minimize latency on fetch)
2770 * WTHRESH=8 burst writeback up to two cache lines
2771 */
2772 rxdctl &= ~0x3FFFFF;
2773 rxdctl |= 0x080420;
2774 }
2775
2776 /* enable receive descriptor ring */
2777 rxdctl |= IXGBE_RXDCTL_ENABLE;
2778 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2779
2780 ixgbe_rx_desc_queue_enable(adapter, ring);
2781 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
2782 }
2783
2784 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2785 {
2786 struct ixgbe_hw *hw = &adapter->hw;
2787 int p;
2788
2789 /* PSRTYPE must be initialized in non 82598 adapters */
2790 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2791 IXGBE_PSRTYPE_UDPHDR |
2792 IXGBE_PSRTYPE_IPV4HDR |
2793 IXGBE_PSRTYPE_L2HDR |
2794 IXGBE_PSRTYPE_IPV6HDR;
2795
2796 if (hw->mac.type == ixgbe_mac_82598EB)
2797 return;
2798
2799 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2800 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2801
2802 for (p = 0; p < adapter->num_rx_pools; p++)
2803 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2804 psrtype);
2805 }
2806
2807 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2808 {
2809 struct ixgbe_hw *hw = &adapter->hw;
2810 u32 gcr_ext;
2811 u32 vt_reg_bits;
2812 u32 reg_offset, vf_shift;
2813 u32 vmdctl;
2814
2815 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2816 return;
2817
2818 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2819 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2820 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2821 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2822
2823 vf_shift = adapter->num_vfs % 32;
2824 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2825
2826 /* Enable only the PF's pool for Tx/Rx */
2827 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2828 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2829 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2830 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2831 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2832
2833 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2834 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2835
2836 /*
2837 * Set up VF register offsets for selected VT Mode,
2838 * i.e. 32 or 64 VFs for SR-IOV
2839 */
2840 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2841 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2842 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2843 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2844
2845 /* enable Tx loopback for VF/PF communication */
2846 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2847 /* Enable MAC Anti-Spoofing */
2848 hw->mac.ops.set_mac_anti_spoofing(hw,
2849 (adapter->antispoofing_enabled =
2850 (adapter->num_vfs != 0)),
2851 adapter->num_vfs);
2852 }
2853
2854 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2855 {
2856 struct ixgbe_hw *hw = &adapter->hw;
2857 struct net_device *netdev = adapter->netdev;
2858 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2859 int rx_buf_len;
2860 struct ixgbe_ring *rx_ring;
2861 int i;
2862 u32 mhadd, hlreg0;
2863
2864 /* Decide whether to use packet split mode or not */
2865 /* On by default */
2866 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2867
2868 /* Do not use packet split if we're in SR-IOV Mode */
2869 if (adapter->num_vfs)
2870 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2871
2872 /* Disable packet split due to 82599 erratum #45 */
2873 if (hw->mac.type == ixgbe_mac_82599EB)
2874 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2875
2876 #ifdef IXGBE_FCOE
2877 /* adjust max frame to be able to do baby jumbo for FCoE */
2878 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2879 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2880 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2881
2882 #endif /* IXGBE_FCOE */
2883 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2884 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2885 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2886 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2887
2888 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2889 }
2890
2891 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
2892 max_frame += VLAN_HLEN;
2893
2894 /* Set the RX buffer length according to the mode */
2895 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2896 rx_buf_len = IXGBE_RX_HDR_SIZE;
2897 } else {
2898 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2899 (netdev->mtu <= ETH_DATA_LEN))
2900 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2901 /*
2902 * Make best use of allocation by using all but 1K of a
2903 * power of 2 allocation that will be used for skb->head.
2904 */
2905 else if (max_frame <= IXGBE_RXBUFFER_3K)
2906 rx_buf_len = IXGBE_RXBUFFER_3K;
2907 else if (max_frame <= IXGBE_RXBUFFER_7K)
2908 rx_buf_len = IXGBE_RXBUFFER_7K;
2909 else if (max_frame <= IXGBE_RXBUFFER_15K)
2910 rx_buf_len = IXGBE_RXBUFFER_15K;
2911 else
2912 rx_buf_len = IXGBE_MAX_RXBUFFER;
2913 }
2914
2915 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2916 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2917 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2918 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2919
2920 /*
2921 * Setup the HW Rx Head and Tail Descriptor Pointers and
2922 * the Base and Length of the Rx Descriptor Ring
2923 */
2924 for (i = 0; i < adapter->num_rx_queues; i++) {
2925 rx_ring = adapter->rx_ring[i];
2926 rx_ring->rx_buf_len = rx_buf_len;
2927
2928 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2929 set_ring_ps_enabled(rx_ring);
2930 else
2931 clear_ring_ps_enabled(rx_ring);
2932
2933 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2934 set_ring_rsc_enabled(rx_ring);
2935 else
2936 clear_ring_rsc_enabled(rx_ring);
2937
2938 #ifdef IXGBE_FCOE
2939 if (netdev->features & NETIF_F_FCOE_MTU) {
2940 struct ixgbe_ring_feature *f;
2941 f = &adapter->ring_feature[RING_F_FCOE];
2942 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2943 clear_ring_ps_enabled(rx_ring);
2944 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2945 rx_ring->rx_buf_len =
2946 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2947 } else if (!ring_is_rsc_enabled(rx_ring) &&
2948 !ring_is_ps_enabled(rx_ring)) {
2949 rx_ring->rx_buf_len =
2950 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2951 }
2952 }
2953 #endif /* IXGBE_FCOE */
2954 }
2955 }
2956
2957 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2958 {
2959 struct ixgbe_hw *hw = &adapter->hw;
2960 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2961
2962 switch (hw->mac.type) {
2963 case ixgbe_mac_82598EB:
2964 /*
2965 * For VMDq support of different descriptor types or
2966 * buffer sizes through the use of multiple SRRCTL
2967 * registers, RDRXCTL.MVMEN must be set to 1
2968 *
2969 * also, the manual doesn't mention it clearly but DCA hints
2970 * will only use queue 0's tags unless this bit is set. Side
2971 * effects of setting this bit are only that SRRCTL must be
2972 * fully programmed [0..15]
2973 */
2974 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2975 break;
2976 case ixgbe_mac_82599EB:
2977 case ixgbe_mac_X540:
2978 /* Disable RSC for ACK packets */
2979 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2980 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2981 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2982 /* hardware requires some bits to be set by default */
2983 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2984 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2985 break;
2986 default:
2987 /* We should do nothing since we don't know this hardware */
2988 return;
2989 }
2990
2991 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2992 }
2993
2994 /**
2995 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2996 * @adapter: board private structure
2997 *
2998 * Configure the Rx unit of the MAC after a reset.
2999 **/
3000 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3001 {
3002 struct ixgbe_hw *hw = &adapter->hw;
3003 int i;
3004 u32 rxctrl;
3005
3006 /* disable receives while setting up the descriptors */
3007 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3008 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3009
3010 ixgbe_setup_psrtype(adapter);
3011 ixgbe_setup_rdrxctl(adapter);
3012
3013 /* Program registers for the distribution of queues */
3014 ixgbe_setup_mrqc(adapter);
3015
3016 ixgbe_set_uta(adapter);
3017
3018 /* set_rx_buffer_len must be called before ring initialization */
3019 ixgbe_set_rx_buffer_len(adapter);
3020
3021 /*
3022 * Setup the HW Rx Head and Tail Descriptor Pointers and
3023 * the Base and Length of the Rx Descriptor Ring
3024 */
3025 for (i = 0; i < adapter->num_rx_queues; i++)
3026 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3027
3028 /* disable drop enable for 82598 parts */
3029 if (hw->mac.type == ixgbe_mac_82598EB)
3030 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3031
3032 /* enable all receives */
3033 rxctrl |= IXGBE_RXCTRL_RXEN;
3034 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3035 }
3036
3037 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3038 {
3039 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3040 struct ixgbe_hw *hw = &adapter->hw;
3041 int pool_ndx = adapter->num_vfs;
3042
3043 /* add VID to filter table */
3044 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3045 set_bit(vid, adapter->active_vlans);
3046 }
3047
3048 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3049 {
3050 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3051 struct ixgbe_hw *hw = &adapter->hw;
3052 int pool_ndx = adapter->num_vfs;
3053
3054 /* remove VID from filter table */
3055 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3056 clear_bit(vid, adapter->active_vlans);
3057 }
3058
3059 /**
3060 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3061 * @adapter: driver data
3062 */
3063 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3064 {
3065 struct ixgbe_hw *hw = &adapter->hw;
3066 u32 vlnctrl;
3067
3068 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3069 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3070 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3071 }
3072
3073 /**
3074 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3075 * @adapter: driver data
3076 */
3077 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3078 {
3079 struct ixgbe_hw *hw = &adapter->hw;
3080 u32 vlnctrl;
3081
3082 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3083 vlnctrl |= IXGBE_VLNCTRL_VFE;
3084 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3085 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3086 }
3087
3088 /**
3089 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3090 * @adapter: driver data
3091 */
3092 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3093 {
3094 struct ixgbe_hw *hw = &adapter->hw;
3095 u32 vlnctrl;
3096 int i, j;
3097
3098 switch (hw->mac.type) {
3099 case ixgbe_mac_82598EB:
3100 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3101 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3102 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3103 break;
3104 case ixgbe_mac_82599EB:
3105 case ixgbe_mac_X540:
3106 for (i = 0; i < adapter->num_rx_queues; i++) {
3107 j = adapter->rx_ring[i]->reg_idx;
3108 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3109 vlnctrl &= ~IXGBE_RXDCTL_VME;
3110 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3111 }
3112 break;
3113 default:
3114 break;
3115 }
3116 }
3117
3118 /**
3119 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3120 * @adapter: driver data
3121 */
3122 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3123 {
3124 struct ixgbe_hw *hw = &adapter->hw;
3125 u32 vlnctrl;
3126 int i, j;
3127
3128 switch (hw->mac.type) {
3129 case ixgbe_mac_82598EB:
3130 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3131 vlnctrl |= IXGBE_VLNCTRL_VME;
3132 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3133 break;
3134 case ixgbe_mac_82599EB:
3135 case ixgbe_mac_X540:
3136 for (i = 0; i < adapter->num_rx_queues; i++) {
3137 j = adapter->rx_ring[i]->reg_idx;
3138 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3139 vlnctrl |= IXGBE_RXDCTL_VME;
3140 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3141 }
3142 break;
3143 default:
3144 break;
3145 }
3146 }
3147
3148 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3149 {
3150 u16 vid;
3151
3152 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3153
3154 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3155 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3156 }
3157
3158 /**
3159 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3160 * @netdev: network interface device structure
3161 *
3162 * Writes unicast address list to the RAR table.
3163 * Returns: -ENOMEM on failure/insufficient address space
3164 * 0 on no addresses written
3165 * X on writing X addresses to the RAR table
3166 **/
3167 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3168 {
3169 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3170 struct ixgbe_hw *hw = &adapter->hw;
3171 unsigned int vfn = adapter->num_vfs;
3172 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3173 int count = 0;
3174
3175 /* return ENOMEM indicating insufficient memory for addresses */
3176 if (netdev_uc_count(netdev) > rar_entries)
3177 return -ENOMEM;
3178
3179 if (!netdev_uc_empty(netdev) && rar_entries) {
3180 struct netdev_hw_addr *ha;
3181 /* return error if we do not support writing to RAR table */
3182 if (!hw->mac.ops.set_rar)
3183 return -ENOMEM;
3184
3185 netdev_for_each_uc_addr(ha, netdev) {
3186 if (!rar_entries)
3187 break;
3188 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3189 vfn, IXGBE_RAH_AV);
3190 count++;
3191 }
3192 }
3193 /* write the addresses in reverse order to avoid write combining */
3194 for (; rar_entries > 0 ; rar_entries--)
3195 hw->mac.ops.clear_rar(hw, rar_entries);
3196
3197 return count;
3198 }
3199
3200 /**
3201 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3202 * @netdev: network interface device structure
3203 *
3204 * The set_rx_method entry point is called whenever the unicast/multicast
3205 * address list or the network interface flags are updated. This routine is
3206 * responsible for configuring the hardware for proper unicast, multicast and
3207 * promiscuous mode.
3208 **/
3209 void ixgbe_set_rx_mode(struct net_device *netdev)
3210 {
3211 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3212 struct ixgbe_hw *hw = &adapter->hw;
3213 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3214 int count;
3215
3216 /* Check for Promiscuous and All Multicast modes */
3217
3218 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3219
3220 /* set all bits that we expect to always be set */
3221 fctrl |= IXGBE_FCTRL_BAM;
3222 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3223 fctrl |= IXGBE_FCTRL_PMCF;
3224
3225 /* clear the bits we are changing the status of */
3226 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3227
3228 if (netdev->flags & IFF_PROMISC) {
3229 hw->addr_ctrl.user_set_promisc = true;
3230 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3231 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3232 /* don't hardware filter vlans in promisc mode */
3233 ixgbe_vlan_filter_disable(adapter);
3234 } else {
3235 if (netdev->flags & IFF_ALLMULTI) {
3236 fctrl |= IXGBE_FCTRL_MPE;
3237 vmolr |= IXGBE_VMOLR_MPE;
3238 } else {
3239 /*
3240 * Write addresses to the MTA, if the attempt fails
3241 * then we should just turn on promiscuous mode so
3242 * that we can at least receive multicast traffic
3243 */
3244 hw->mac.ops.update_mc_addr_list(hw, netdev);
3245 vmolr |= IXGBE_VMOLR_ROMPE;
3246 }
3247 ixgbe_vlan_filter_enable(adapter);
3248 hw->addr_ctrl.user_set_promisc = false;
3249 /*
3250 * Write addresses to available RAR registers, if there is not
3251 * sufficient space to store all the addresses then enable
3252 * unicast promiscuous mode
3253 */
3254 count = ixgbe_write_uc_addr_list(netdev);
3255 if (count < 0) {
3256 fctrl |= IXGBE_FCTRL_UPE;
3257 vmolr |= IXGBE_VMOLR_ROPE;
3258 }
3259 }
3260
3261 if (adapter->num_vfs) {
3262 ixgbe_restore_vf_multicasts(adapter);
3263 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3264 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3265 IXGBE_VMOLR_ROPE);
3266 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3267 }
3268
3269 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3270
3271 if (netdev->features & NETIF_F_HW_VLAN_RX)
3272 ixgbe_vlan_strip_enable(adapter);
3273 else
3274 ixgbe_vlan_strip_disable(adapter);
3275 }
3276
3277 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3278 {
3279 int q_idx;
3280 struct ixgbe_q_vector *q_vector;
3281 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3282
3283 /* legacy and MSI only use one vector */
3284 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3285 q_vectors = 1;
3286
3287 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3288 q_vector = adapter->q_vector[q_idx];
3289 napi_enable(&q_vector->napi);
3290 }
3291 }
3292
3293 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3294 {
3295 int q_idx;
3296 struct ixgbe_q_vector *q_vector;
3297 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3298
3299 /* legacy and MSI only use one vector */
3300 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3301 q_vectors = 1;
3302
3303 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3304 q_vector = adapter->q_vector[q_idx];
3305 napi_disable(&q_vector->napi);
3306 }
3307 }
3308
3309 #ifdef CONFIG_IXGBE_DCB
3310 /*
3311 * ixgbe_configure_dcb - Configure DCB hardware
3312 * @adapter: ixgbe adapter struct
3313 *
3314 * This is called by the driver on open to configure the DCB hardware.
3315 * This is also called by the gennetlink interface when reconfiguring
3316 * the DCB state.
3317 */
3318 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3319 {
3320 struct ixgbe_hw *hw = &adapter->hw;
3321 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3322
3323 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3324 if (hw->mac.type == ixgbe_mac_82598EB)
3325 netif_set_gso_max_size(adapter->netdev, 65536);
3326 return;
3327 }
3328
3329 if (hw->mac.type == ixgbe_mac_82598EB)
3330 netif_set_gso_max_size(adapter->netdev, 32768);
3331
3332
3333 /* Enable VLAN tag insert/strip */
3334 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3335
3336 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3337
3338 /* reconfigure the hardware */
3339 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3340 #ifdef IXGBE_FCOE
3341 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3342 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3343 #endif
3344 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3345 DCB_TX_CONFIG);
3346 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3347 DCB_RX_CONFIG);
3348 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3349 } else {
3350 struct net_device *dev = adapter->netdev;
3351
3352 if (adapter->ixgbe_ieee_ets) {
3353 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
3354 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3355
3356 ixgbe_dcb_hw_ets(&adapter->hw, ets, max_frame);
3357 }
3358
3359 if (adapter->ixgbe_ieee_pfc) {
3360 struct ieee_pfc *pfc = adapter->ixgbe_ieee_pfc;
3361
3362 ixgbe_dcb_hw_pfc_config(&adapter->hw, pfc->pfc_en);
3363 }
3364 }
3365
3366 /* Enable RSS Hash per TC */
3367 if (hw->mac.type != ixgbe_mac_82598EB) {
3368 int i;
3369 u32 reg = 0;
3370
3371 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3372 u8 msb = 0;
3373 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3374
3375 while (cnt >>= 1)
3376 msb++;
3377
3378 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3379 }
3380 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3381 }
3382 }
3383 #endif
3384
3385 /* Additional bittime to account for IXGBE framing */
3386 #define IXGBE_ETH_FRAMING 20
3387
3388 /*
3389 * ixgbe_hpbthresh - calculate high water mark for flow control
3390 *
3391 * @adapter: board private structure to calculate for
3392 * @pb - packet buffer to calculate
3393 */
3394 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3395 {
3396 struct ixgbe_hw *hw = &adapter->hw;
3397 struct net_device *dev = adapter->netdev;
3398 int link, tc, kb, marker;
3399 u32 dv_id, rx_pba;
3400
3401 /* Calculate max LAN frame size */
3402 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3403
3404 #ifdef IXGBE_FCOE
3405 /* FCoE traffic class uses FCOE jumbo frames */
3406 if (dev->features & NETIF_F_FCOE_MTU) {
3407 int fcoe_pb = 0;
3408
3409 #ifdef CONFIG_IXGBE_DCB
3410 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3411
3412 #endif
3413 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3414 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3415 }
3416 #endif
3417
3418 /* Calculate delay value for device */
3419 switch (hw->mac.type) {
3420 case ixgbe_mac_X540:
3421 dv_id = IXGBE_DV_X540(link, tc);
3422 break;
3423 default:
3424 dv_id = IXGBE_DV(link, tc);
3425 break;
3426 }
3427
3428 /* Loopback switch introduces additional latency */
3429 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3430 dv_id += IXGBE_B2BT(tc);
3431
3432 /* Delay value is calculated in bit times convert to KB */
3433 kb = IXGBE_BT2KB(dv_id);
3434 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3435
3436 marker = rx_pba - kb;
3437
3438 /* It is possible that the packet buffer is not large enough
3439 * to provide required headroom. In this case throw an error
3440 * to user and a do the best we can.
3441 */
3442 if (marker < 0) {
3443 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3444 "headroom to support flow control."
3445 "Decrease MTU or number of traffic classes\n", pb);
3446 marker = tc + 1;
3447 }
3448
3449 return marker;
3450 }
3451
3452 /*
3453 * ixgbe_lpbthresh - calculate low water mark for for flow control
3454 *
3455 * @adapter: board private structure to calculate for
3456 * @pb - packet buffer to calculate
3457 */
3458 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3459 {
3460 struct ixgbe_hw *hw = &adapter->hw;
3461 struct net_device *dev = adapter->netdev;
3462 int tc;
3463 u32 dv_id;
3464
3465 /* Calculate max LAN frame size */
3466 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3467
3468 /* Calculate delay value for device */
3469 switch (hw->mac.type) {
3470 case ixgbe_mac_X540:
3471 dv_id = IXGBE_LOW_DV_X540(tc);
3472 break;
3473 default:
3474 dv_id = IXGBE_LOW_DV(tc);
3475 break;
3476 }
3477
3478 /* Delay value is calculated in bit times convert to KB */
3479 return IXGBE_BT2KB(dv_id);
3480 }
3481
3482 /*
3483 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3484 */
3485 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3486 {
3487 struct ixgbe_hw *hw = &adapter->hw;
3488 int num_tc = netdev_get_num_tc(adapter->netdev);
3489 int i;
3490
3491 if (!num_tc)
3492 num_tc = 1;
3493
3494 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3495
3496 for (i = 0; i < num_tc; i++) {
3497 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3498
3499 /* Low water marks must not be larger than high water marks */
3500 if (hw->fc.low_water > hw->fc.high_water[i])
3501 hw->fc.low_water = 0;
3502 }
3503 }
3504
3505 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3506 {
3507 struct ixgbe_hw *hw = &adapter->hw;
3508 int hdrm;
3509 u8 tc = netdev_get_num_tc(adapter->netdev);
3510
3511 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3512 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3513 hdrm = 32 << adapter->fdir_pballoc;
3514 else
3515 hdrm = 0;
3516
3517 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3518 ixgbe_pbthresh_setup(adapter);
3519 }
3520
3521 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3522 {
3523 struct ixgbe_hw *hw = &adapter->hw;
3524 struct hlist_node *node, *node2;
3525 struct ixgbe_fdir_filter *filter;
3526
3527 spin_lock(&adapter->fdir_perfect_lock);
3528
3529 if (!hlist_empty(&adapter->fdir_filter_list))
3530 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3531
3532 hlist_for_each_entry_safe(filter, node, node2,
3533 &adapter->fdir_filter_list, fdir_node) {
3534 ixgbe_fdir_write_perfect_filter_82599(hw,
3535 &filter->filter,
3536 filter->sw_idx,
3537 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3538 IXGBE_FDIR_DROP_QUEUE :
3539 adapter->rx_ring[filter->action]->reg_idx);
3540 }
3541
3542 spin_unlock(&adapter->fdir_perfect_lock);
3543 }
3544
3545 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3546 {
3547 ixgbe_configure_pb(adapter);
3548 #ifdef CONFIG_IXGBE_DCB
3549 ixgbe_configure_dcb(adapter);
3550 #endif
3551
3552 ixgbe_set_rx_mode(adapter->netdev);
3553 ixgbe_restore_vlan(adapter);
3554
3555 #ifdef IXGBE_FCOE
3556 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3557 ixgbe_configure_fcoe(adapter);
3558
3559 #endif /* IXGBE_FCOE */
3560 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3561 ixgbe_init_fdir_signature_82599(&adapter->hw,
3562 adapter->fdir_pballoc);
3563 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3564 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3565 adapter->fdir_pballoc);
3566 ixgbe_fdir_filter_restore(adapter);
3567 }
3568
3569 ixgbe_configure_virtualization(adapter);
3570
3571 ixgbe_configure_tx(adapter);
3572 ixgbe_configure_rx(adapter);
3573 }
3574
3575 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3576 {
3577 switch (hw->phy.type) {
3578 case ixgbe_phy_sfp_avago:
3579 case ixgbe_phy_sfp_ftl:
3580 case ixgbe_phy_sfp_intel:
3581 case ixgbe_phy_sfp_unknown:
3582 case ixgbe_phy_sfp_passive_tyco:
3583 case ixgbe_phy_sfp_passive_unknown:
3584 case ixgbe_phy_sfp_active_unknown:
3585 case ixgbe_phy_sfp_ftl_active:
3586 return true;
3587 case ixgbe_phy_nl:
3588 if (hw->mac.type == ixgbe_mac_82598EB)
3589 return true;
3590 default:
3591 return false;
3592 }
3593 }
3594
3595 /**
3596 * ixgbe_sfp_link_config - set up SFP+ link
3597 * @adapter: pointer to private adapter struct
3598 **/
3599 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3600 {
3601 /*
3602 * We are assuming the worst case scenerio here, and that
3603 * is that an SFP was inserted/removed after the reset
3604 * but before SFP detection was enabled. As such the best
3605 * solution is to just start searching as soon as we start
3606 */
3607 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3608 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3609
3610 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3611 }
3612
3613 /**
3614 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3615 * @hw: pointer to private hardware struct
3616 *
3617 * Returns 0 on success, negative on failure
3618 **/
3619 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3620 {
3621 u32 autoneg;
3622 bool negotiation, link_up = false;
3623 u32 ret = IXGBE_ERR_LINK_SETUP;
3624
3625 if (hw->mac.ops.check_link)
3626 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3627
3628 if (ret)
3629 goto link_cfg_out;
3630
3631 autoneg = hw->phy.autoneg_advertised;
3632 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3633 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3634 &negotiation);
3635 if (ret)
3636 goto link_cfg_out;
3637
3638 if (hw->mac.ops.setup_link)
3639 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3640 link_cfg_out:
3641 return ret;
3642 }
3643
3644 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3645 {
3646 struct ixgbe_hw *hw = &adapter->hw;
3647 u32 gpie = 0;
3648
3649 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3650 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3651 IXGBE_GPIE_OCD;
3652 gpie |= IXGBE_GPIE_EIAME;
3653 /*
3654 * use EIAM to auto-mask when MSI-X interrupt is asserted
3655 * this saves a register write for every interrupt
3656 */
3657 switch (hw->mac.type) {
3658 case ixgbe_mac_82598EB:
3659 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3660 break;
3661 case ixgbe_mac_82599EB:
3662 case ixgbe_mac_X540:
3663 default:
3664 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3665 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3666 break;
3667 }
3668 } else {
3669 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3670 * specifically only auto mask tx and rx interrupts */
3671 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3672 }
3673
3674 /* XXX: to interrupt immediately for EICS writes, enable this */
3675 /* gpie |= IXGBE_GPIE_EIMEN; */
3676
3677 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3678 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3679 gpie |= IXGBE_GPIE_VTMODE_64;
3680 }
3681
3682 /* Enable Thermal over heat sensor interrupt */
3683 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3684 switch (adapter->hw.mac.type) {
3685 case ixgbe_mac_82599EB:
3686 gpie |= IXGBE_SDP0_GPIEN;
3687 break;
3688 case ixgbe_mac_X540:
3689 gpie |= IXGBE_EIMS_TS;
3690 break;
3691 default:
3692 break;
3693 }
3694 }
3695
3696 /* Enable fan failure interrupt */
3697 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3698 gpie |= IXGBE_SDP1_GPIEN;
3699
3700 if (hw->mac.type == ixgbe_mac_82599EB) {
3701 gpie |= IXGBE_SDP1_GPIEN;
3702 gpie |= IXGBE_SDP2_GPIEN;
3703 }
3704
3705 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3706 }
3707
3708 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
3709 {
3710 struct ixgbe_hw *hw = &adapter->hw;
3711 int err;
3712 u32 ctrl_ext;
3713
3714 ixgbe_get_hw_control(adapter);
3715 ixgbe_setup_gpie(adapter);
3716
3717 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3718 ixgbe_configure_msix(adapter);
3719 else
3720 ixgbe_configure_msi_and_legacy(adapter);
3721
3722 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3723 if (hw->mac.ops.enable_tx_laser &&
3724 ((hw->phy.multispeed_fiber) ||
3725 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3726 (hw->mac.type == ixgbe_mac_82599EB))))
3727 hw->mac.ops.enable_tx_laser(hw);
3728
3729 clear_bit(__IXGBE_DOWN, &adapter->state);
3730 ixgbe_napi_enable_all(adapter);
3731
3732 if (ixgbe_is_sfp(hw)) {
3733 ixgbe_sfp_link_config(adapter);
3734 } else {
3735 err = ixgbe_non_sfp_link_config(hw);
3736 if (err)
3737 e_err(probe, "link_config FAILED %d\n", err);
3738 }
3739
3740 /* clear any pending interrupts, may auto mask */
3741 IXGBE_READ_REG(hw, IXGBE_EICR);
3742 ixgbe_irq_enable(adapter, true, true);
3743
3744 /*
3745 * If this adapter has a fan, check to see if we had a failure
3746 * before we enabled the interrupt.
3747 */
3748 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3749 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3750 if (esdp & IXGBE_ESDP_SDP1)
3751 e_crit(drv, "Fan has stopped, replace the adapter\n");
3752 }
3753
3754 /* enable transmits */
3755 netif_tx_start_all_queues(adapter->netdev);
3756
3757 /* bring the link up in the watchdog, this could race with our first
3758 * link up interrupt but shouldn't be a problem */
3759 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3760 adapter->link_check_timeout = jiffies;
3761 mod_timer(&adapter->service_timer, jiffies);
3762
3763 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3764 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3765 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3766 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3767 }
3768
3769 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3770 {
3771 WARN_ON(in_interrupt());
3772 /* put off any impending NetWatchDogTimeout */
3773 adapter->netdev->trans_start = jiffies;
3774
3775 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3776 usleep_range(1000, 2000);
3777 ixgbe_down(adapter);
3778 /*
3779 * If SR-IOV enabled then wait a bit before bringing the adapter
3780 * back up to give the VFs time to respond to the reset. The
3781 * two second wait is based upon the watchdog timer cycle in
3782 * the VF driver.
3783 */
3784 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3785 msleep(2000);
3786 ixgbe_up(adapter);
3787 clear_bit(__IXGBE_RESETTING, &adapter->state);
3788 }
3789
3790 void ixgbe_up(struct ixgbe_adapter *adapter)
3791 {
3792 /* hardware has been reset, we need to reload some things */
3793 ixgbe_configure(adapter);
3794
3795 ixgbe_up_complete(adapter);
3796 }
3797
3798 void ixgbe_reset(struct ixgbe_adapter *adapter)
3799 {
3800 struct ixgbe_hw *hw = &adapter->hw;
3801 int err;
3802
3803 /* lock SFP init bit to prevent race conditions with the watchdog */
3804 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3805 usleep_range(1000, 2000);
3806
3807 /* clear all SFP and link config related flags while holding SFP_INIT */
3808 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3809 IXGBE_FLAG2_SFP_NEEDS_RESET);
3810 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3811
3812 err = hw->mac.ops.init_hw(hw);
3813 switch (err) {
3814 case 0:
3815 case IXGBE_ERR_SFP_NOT_PRESENT:
3816 case IXGBE_ERR_SFP_NOT_SUPPORTED:
3817 break;
3818 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3819 e_dev_err("master disable timed out\n");
3820 break;
3821 case IXGBE_ERR_EEPROM_VERSION:
3822 /* We are running on a pre-production device, log a warning */
3823 e_dev_warn("This device is a pre-production adapter/LOM. "
3824 "Please be aware there may be issuesassociated with "
3825 "your hardware. If you are experiencing problems "
3826 "please contact your Intel or hardware "
3827 "representative who provided you with this "
3828 "hardware.\n");
3829 break;
3830 default:
3831 e_dev_err("Hardware Error: %d\n", err);
3832 }
3833
3834 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3835
3836 /* reprogram the RAR[0] in case user changed it. */
3837 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3838 IXGBE_RAH_AV);
3839 }
3840
3841 /**
3842 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3843 * @rx_ring: ring to free buffers from
3844 **/
3845 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3846 {
3847 struct device *dev = rx_ring->dev;
3848 unsigned long size;
3849 u16 i;
3850
3851 /* ring already cleared, nothing to do */
3852 if (!rx_ring->rx_buffer_info)
3853 return;
3854
3855 /* Free all the Rx ring sk_buffs */
3856 for (i = 0; i < rx_ring->count; i++) {
3857 struct ixgbe_rx_buffer *rx_buffer_info;
3858
3859 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3860 if (rx_buffer_info->dma) {
3861 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3862 rx_ring->rx_buf_len,
3863 DMA_FROM_DEVICE);
3864 rx_buffer_info->dma = 0;
3865 }
3866 if (rx_buffer_info->skb) {
3867 struct sk_buff *skb = rx_buffer_info->skb;
3868 rx_buffer_info->skb = NULL;
3869 do {
3870 struct sk_buff *this = skb;
3871 if (IXGBE_RSC_CB(this)->delay_unmap) {
3872 dma_unmap_single(dev,
3873 IXGBE_RSC_CB(this)->dma,
3874 rx_ring->rx_buf_len,
3875 DMA_FROM_DEVICE);
3876 IXGBE_RSC_CB(this)->dma = 0;
3877 IXGBE_RSC_CB(skb)->delay_unmap = false;
3878 }
3879 skb = skb->prev;
3880 dev_kfree_skb(this);
3881 } while (skb);
3882 }
3883 if (!rx_buffer_info->page)
3884 continue;
3885 if (rx_buffer_info->page_dma) {
3886 dma_unmap_page(dev, rx_buffer_info->page_dma,
3887 PAGE_SIZE / 2, DMA_FROM_DEVICE);
3888 rx_buffer_info->page_dma = 0;
3889 }
3890 put_page(rx_buffer_info->page);
3891 rx_buffer_info->page = NULL;
3892 rx_buffer_info->page_offset = 0;
3893 }
3894
3895 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3896 memset(rx_ring->rx_buffer_info, 0, size);
3897
3898 /* Zero out the descriptor ring */
3899 memset(rx_ring->desc, 0, rx_ring->size);
3900
3901 rx_ring->next_to_clean = 0;
3902 rx_ring->next_to_use = 0;
3903 }
3904
3905 /**
3906 * ixgbe_clean_tx_ring - Free Tx Buffers
3907 * @tx_ring: ring to be cleaned
3908 **/
3909 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3910 {
3911 struct ixgbe_tx_buffer *tx_buffer_info;
3912 unsigned long size;
3913 u16 i;
3914
3915 /* ring already cleared, nothing to do */
3916 if (!tx_ring->tx_buffer_info)
3917 return;
3918
3919 /* Free all the Tx ring sk_buffs */
3920 for (i = 0; i < tx_ring->count; i++) {
3921 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3922 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3923 }
3924
3925 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3926 memset(tx_ring->tx_buffer_info, 0, size);
3927
3928 /* Zero out the descriptor ring */
3929 memset(tx_ring->desc, 0, tx_ring->size);
3930
3931 tx_ring->next_to_use = 0;
3932 tx_ring->next_to_clean = 0;
3933 }
3934
3935 /**
3936 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3937 * @adapter: board private structure
3938 **/
3939 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3940 {
3941 int i;
3942
3943 for (i = 0; i < adapter->num_rx_queues; i++)
3944 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3945 }
3946
3947 /**
3948 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3949 * @adapter: board private structure
3950 **/
3951 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3952 {
3953 int i;
3954
3955 for (i = 0; i < adapter->num_tx_queues; i++)
3956 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3957 }
3958
3959 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
3960 {
3961 struct hlist_node *node, *node2;
3962 struct ixgbe_fdir_filter *filter;
3963
3964 spin_lock(&adapter->fdir_perfect_lock);
3965
3966 hlist_for_each_entry_safe(filter, node, node2,
3967 &adapter->fdir_filter_list, fdir_node) {
3968 hlist_del(&filter->fdir_node);
3969 kfree(filter);
3970 }
3971 adapter->fdir_filter_count = 0;
3972
3973 spin_unlock(&adapter->fdir_perfect_lock);
3974 }
3975
3976 void ixgbe_down(struct ixgbe_adapter *adapter)
3977 {
3978 struct net_device *netdev = adapter->netdev;
3979 struct ixgbe_hw *hw = &adapter->hw;
3980 u32 rxctrl;
3981 int i;
3982
3983 /* signal that we are down to the interrupt handler */
3984 set_bit(__IXGBE_DOWN, &adapter->state);
3985
3986 /* disable receives */
3987 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3988 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3989
3990 /* disable all enabled rx queues */
3991 for (i = 0; i < adapter->num_rx_queues; i++)
3992 /* this call also flushes the previous write */
3993 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
3994
3995 usleep_range(10000, 20000);
3996
3997 netif_tx_stop_all_queues(netdev);
3998
3999 /* call carrier off first to avoid false dev_watchdog timeouts */
4000 netif_carrier_off(netdev);
4001 netif_tx_disable(netdev);
4002
4003 ixgbe_irq_disable(adapter);
4004
4005 ixgbe_napi_disable_all(adapter);
4006
4007 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4008 IXGBE_FLAG2_RESET_REQUESTED);
4009 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4010
4011 del_timer_sync(&adapter->service_timer);
4012
4013 if (adapter->num_vfs) {
4014 /* Clear EITR Select mapping */
4015 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4016
4017 /* Mark all the VFs as inactive */
4018 for (i = 0 ; i < adapter->num_vfs; i++)
4019 adapter->vfinfo[i].clear_to_send = 0;
4020
4021 /* ping all the active vfs to let them know we are going down */
4022 ixgbe_ping_all_vfs(adapter);
4023
4024 /* Disable all VFTE/VFRE TX/RX */
4025 ixgbe_disable_tx_rx(adapter);
4026 }
4027
4028 /* disable transmits in the hardware now that interrupts are off */
4029 for (i = 0; i < adapter->num_tx_queues; i++) {
4030 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4031 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4032 }
4033
4034 /* Disable the Tx DMA engine on 82599 and X540 */
4035 switch (hw->mac.type) {
4036 case ixgbe_mac_82599EB:
4037 case ixgbe_mac_X540:
4038 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4039 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4040 ~IXGBE_DMATXCTL_TE));
4041 break;
4042 default:
4043 break;
4044 }
4045
4046 if (!pci_channel_offline(adapter->pdev))
4047 ixgbe_reset(adapter);
4048
4049 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4050 if (hw->mac.ops.disable_tx_laser &&
4051 ((hw->phy.multispeed_fiber) ||
4052 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4053 (hw->mac.type == ixgbe_mac_82599EB))))
4054 hw->mac.ops.disable_tx_laser(hw);
4055
4056 ixgbe_clean_all_tx_rings(adapter);
4057 ixgbe_clean_all_rx_rings(adapter);
4058
4059 #ifdef CONFIG_IXGBE_DCA
4060 /* since we reset the hardware DCA settings were cleared */
4061 ixgbe_setup_dca(adapter);
4062 #endif
4063 }
4064
4065 /**
4066 * ixgbe_poll - NAPI Rx polling callback
4067 * @napi: structure for representing this polling device
4068 * @budget: how many packets driver is allowed to clean
4069 *
4070 * This function is used for legacy and MSI, NAPI mode
4071 **/
4072 static int ixgbe_poll(struct napi_struct *napi, int budget)
4073 {
4074 struct ixgbe_q_vector *q_vector =
4075 container_of(napi, struct ixgbe_q_vector, napi);
4076 struct ixgbe_adapter *adapter = q_vector->adapter;
4077 struct ixgbe_ring *ring;
4078 int per_ring_budget;
4079 bool clean_complete = true;
4080
4081 #ifdef CONFIG_IXGBE_DCA
4082 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4083 ixgbe_update_dca(q_vector);
4084 #endif
4085
4086 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
4087 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
4088
4089 /* attempt to distribute budget to each queue fairly, but don't allow
4090 * the budget to go below 1 because we'll exit polling */
4091 if (q_vector->rx.count > 1)
4092 per_ring_budget = max(budget/q_vector->rx.count, 1);
4093 else
4094 per_ring_budget = budget;
4095
4096 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
4097 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
4098 per_ring_budget);
4099
4100 /* If all work not completed, return budget and keep polling */
4101 if (!clean_complete)
4102 return budget;
4103
4104 /* all work done, exit the polling mode */
4105 napi_complete(napi);
4106 if (adapter->rx_itr_setting & 1)
4107 ixgbe_set_itr(q_vector);
4108 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4109 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4110
4111 return 0;
4112 }
4113
4114 /**
4115 * ixgbe_tx_timeout - Respond to a Tx Hang
4116 * @netdev: network interface device structure
4117 **/
4118 static void ixgbe_tx_timeout(struct net_device *netdev)
4119 {
4120 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4121
4122 /* Do the reset outside of interrupt context */
4123 ixgbe_tx_timeout_reset(adapter);
4124 }
4125
4126 /**
4127 * ixgbe_set_rss_queues: Allocate queues for RSS
4128 * @adapter: board private structure to initialize
4129 *
4130 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4131 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4132 *
4133 **/
4134 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4135 {
4136 bool ret = false;
4137 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4138
4139 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4140 f->mask = 0xF;
4141 adapter->num_rx_queues = f->indices;
4142 adapter->num_tx_queues = f->indices;
4143 ret = true;
4144 } else {
4145 ret = false;
4146 }
4147
4148 return ret;
4149 }
4150
4151 /**
4152 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4153 * @adapter: board private structure to initialize
4154 *
4155 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4156 * to the original CPU that initiated the Tx session. This runs in addition
4157 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4158 * Rx load across CPUs using RSS.
4159 *
4160 **/
4161 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4162 {
4163 bool ret = false;
4164 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4165
4166 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4167 f_fdir->mask = 0;
4168
4169 /* Flow Director must have RSS enabled */
4170 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4171 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4172 adapter->num_tx_queues = f_fdir->indices;
4173 adapter->num_rx_queues = f_fdir->indices;
4174 ret = true;
4175 } else {
4176 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4177 }
4178 return ret;
4179 }
4180
4181 #ifdef IXGBE_FCOE
4182 /**
4183 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4184 * @adapter: board private structure to initialize
4185 *
4186 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4187 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4188 * rx queues out of the max number of rx queues, instead, it is used as the
4189 * index of the first rx queue used by FCoE.
4190 *
4191 **/
4192 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4193 {
4194 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4195
4196 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4197 return false;
4198
4199 f->indices = min((int)num_online_cpus(), f->indices);
4200
4201 adapter->num_rx_queues = 1;
4202 adapter->num_tx_queues = 1;
4203
4204 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4205 e_info(probe, "FCoE enabled with RSS\n");
4206 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4207 ixgbe_set_fdir_queues(adapter);
4208 else
4209 ixgbe_set_rss_queues(adapter);
4210 }
4211
4212 /* adding FCoE rx rings to the end */
4213 f->mask = adapter->num_rx_queues;
4214 adapter->num_rx_queues += f->indices;
4215 adapter->num_tx_queues += f->indices;
4216
4217 return true;
4218 }
4219 #endif /* IXGBE_FCOE */
4220
4221 /* Artificial max queue cap per traffic class in DCB mode */
4222 #define DCB_QUEUE_CAP 8
4223
4224 #ifdef CONFIG_IXGBE_DCB
4225 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4226 {
4227 int per_tc_q, q, i, offset = 0;
4228 struct net_device *dev = adapter->netdev;
4229 int tcs = netdev_get_num_tc(dev);
4230
4231 if (!tcs)
4232 return false;
4233
4234 /* Map queue offset and counts onto allocated tx queues */
4235 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4236 q = min((int)num_online_cpus(), per_tc_q);
4237
4238 for (i = 0; i < tcs; i++) {
4239 netdev_set_prio_tc_map(dev, i, i);
4240 netdev_set_tc_queue(dev, i, q, offset);
4241 offset += q;
4242 }
4243
4244 adapter->num_tx_queues = q * tcs;
4245 adapter->num_rx_queues = q * tcs;
4246
4247 #ifdef IXGBE_FCOE
4248 /* FCoE enabled queues require special configuration indexed
4249 * by feature specific indices and mask. Here we map FCoE
4250 * indices onto the DCB queue pairs allowing FCoE to own
4251 * configuration later.
4252 */
4253 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4254 int tc;
4255 struct ixgbe_ring_feature *f =
4256 &adapter->ring_feature[RING_F_FCOE];
4257
4258 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4259 f->indices = dev->tc_to_txq[tc].count;
4260 f->mask = dev->tc_to_txq[tc].offset;
4261 }
4262 #endif
4263
4264 return true;
4265 }
4266 #endif
4267
4268 /**
4269 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4270 * @adapter: board private structure to initialize
4271 *
4272 * IOV doesn't actually use anything, so just NAK the
4273 * request for now and let the other queue routines
4274 * figure out what to do.
4275 */
4276 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4277 {
4278 return false;
4279 }
4280
4281 /*
4282 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4283 * @adapter: board private structure to initialize
4284 *
4285 * This is the top level queue allocation routine. The order here is very
4286 * important, starting with the "most" number of features turned on at once,
4287 * and ending with the smallest set of features. This way large combinations
4288 * can be allocated if they're turned on, and smaller combinations are the
4289 * fallthrough conditions.
4290 *
4291 **/
4292 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4293 {
4294 /* Start with base case */
4295 adapter->num_rx_queues = 1;
4296 adapter->num_tx_queues = 1;
4297 adapter->num_rx_pools = adapter->num_rx_queues;
4298 adapter->num_rx_queues_per_pool = 1;
4299
4300 if (ixgbe_set_sriov_queues(adapter))
4301 goto done;
4302
4303 #ifdef CONFIG_IXGBE_DCB
4304 if (ixgbe_set_dcb_queues(adapter))
4305 goto done;
4306
4307 #endif
4308 #ifdef IXGBE_FCOE
4309 if (ixgbe_set_fcoe_queues(adapter))
4310 goto done;
4311
4312 #endif /* IXGBE_FCOE */
4313 if (ixgbe_set_fdir_queues(adapter))
4314 goto done;
4315
4316 if (ixgbe_set_rss_queues(adapter))
4317 goto done;
4318
4319 /* fallback to base case */
4320 adapter->num_rx_queues = 1;
4321 adapter->num_tx_queues = 1;
4322
4323 done:
4324 /* Notify the stack of the (possibly) reduced queue counts. */
4325 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4326 return netif_set_real_num_rx_queues(adapter->netdev,
4327 adapter->num_rx_queues);
4328 }
4329
4330 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4331 int vectors)
4332 {
4333 int err, vector_threshold;
4334
4335 /* We'll want at least 3 (vector_threshold):
4336 * 1) TxQ[0] Cleanup
4337 * 2) RxQ[0] Cleanup
4338 * 3) Other (Link Status Change, etc.)
4339 * 4) TCP Timer (optional)
4340 */
4341 vector_threshold = MIN_MSIX_COUNT;
4342
4343 /* The more we get, the more we will assign to Tx/Rx Cleanup
4344 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4345 * Right now, we simply care about how many we'll get; we'll
4346 * set them up later while requesting irq's.
4347 */
4348 while (vectors >= vector_threshold) {
4349 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4350 vectors);
4351 if (!err) /* Success in acquiring all requested vectors. */
4352 break;
4353 else if (err < 0)
4354 vectors = 0; /* Nasty failure, quit now */
4355 else /* err == number of vectors we should try again with */
4356 vectors = err;
4357 }
4358
4359 if (vectors < vector_threshold) {
4360 /* Can't allocate enough MSI-X interrupts? Oh well.
4361 * This just means we'll go with either a single MSI
4362 * vector or fall back to legacy interrupts.
4363 */
4364 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4365 "Unable to allocate MSI-X interrupts\n");
4366 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4367 kfree(adapter->msix_entries);
4368 adapter->msix_entries = NULL;
4369 } else {
4370 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4371 /*
4372 * Adjust for only the vectors we'll use, which is minimum
4373 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4374 * vectors we were allocated.
4375 */
4376 adapter->num_msix_vectors = min(vectors,
4377 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4378 }
4379 }
4380
4381 /**
4382 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4383 * @adapter: board private structure to initialize
4384 *
4385 * Cache the descriptor ring offsets for RSS to the assigned rings.
4386 *
4387 **/
4388 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4389 {
4390 int i;
4391
4392 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4393 return false;
4394
4395 for (i = 0; i < adapter->num_rx_queues; i++)
4396 adapter->rx_ring[i]->reg_idx = i;
4397 for (i = 0; i < adapter->num_tx_queues; i++)
4398 adapter->tx_ring[i]->reg_idx = i;
4399
4400 return true;
4401 }
4402
4403 #ifdef CONFIG_IXGBE_DCB
4404
4405 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4406 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4407 unsigned int *tx, unsigned int *rx)
4408 {
4409 struct net_device *dev = adapter->netdev;
4410 struct ixgbe_hw *hw = &adapter->hw;
4411 u8 num_tcs = netdev_get_num_tc(dev);
4412
4413 *tx = 0;
4414 *rx = 0;
4415
4416 switch (hw->mac.type) {
4417 case ixgbe_mac_82598EB:
4418 *tx = tc << 2;
4419 *rx = tc << 3;
4420 break;
4421 case ixgbe_mac_82599EB:
4422 case ixgbe_mac_X540:
4423 if (num_tcs > 4) {
4424 if (tc < 3) {
4425 *tx = tc << 5;
4426 *rx = tc << 4;
4427 } else if (tc < 5) {
4428 *tx = ((tc + 2) << 4);
4429 *rx = tc << 4;
4430 } else if (tc < num_tcs) {
4431 *tx = ((tc + 8) << 3);
4432 *rx = tc << 4;
4433 }
4434 } else {
4435 *rx = tc << 5;
4436 switch (tc) {
4437 case 0:
4438 *tx = 0;
4439 break;
4440 case 1:
4441 *tx = 64;
4442 break;
4443 case 2:
4444 *tx = 96;
4445 break;
4446 case 3:
4447 *tx = 112;
4448 break;
4449 default:
4450 break;
4451 }
4452 }
4453 break;
4454 default:
4455 break;
4456 }
4457 }
4458
4459 /**
4460 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4461 * @adapter: board private structure to initialize
4462 *
4463 * Cache the descriptor ring offsets for DCB to the assigned rings.
4464 *
4465 **/
4466 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4467 {
4468 struct net_device *dev = adapter->netdev;
4469 int i, j, k;
4470 u8 num_tcs = netdev_get_num_tc(dev);
4471
4472 if (!num_tcs)
4473 return false;
4474
4475 for (i = 0, k = 0; i < num_tcs; i++) {
4476 unsigned int tx_s, rx_s;
4477 u16 count = dev->tc_to_txq[i].count;
4478
4479 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4480 for (j = 0; j < count; j++, k++) {
4481 adapter->tx_ring[k]->reg_idx = tx_s + j;
4482 adapter->rx_ring[k]->reg_idx = rx_s + j;
4483 adapter->tx_ring[k]->dcb_tc = i;
4484 adapter->rx_ring[k]->dcb_tc = i;
4485 }
4486 }
4487
4488 return true;
4489 }
4490 #endif
4491
4492 /**
4493 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4494 * @adapter: board private structure to initialize
4495 *
4496 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4497 *
4498 **/
4499 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4500 {
4501 int i;
4502 bool ret = false;
4503
4504 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4505 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4506 for (i = 0; i < adapter->num_rx_queues; i++)
4507 adapter->rx_ring[i]->reg_idx = i;
4508 for (i = 0; i < adapter->num_tx_queues; i++)
4509 adapter->tx_ring[i]->reg_idx = i;
4510 ret = true;
4511 }
4512
4513 return ret;
4514 }
4515
4516 #ifdef IXGBE_FCOE
4517 /**
4518 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4519 * @adapter: board private structure to initialize
4520 *
4521 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4522 *
4523 */
4524 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4525 {
4526 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4527 int i;
4528 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4529
4530 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4531 return false;
4532
4533 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4534 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4535 ixgbe_cache_ring_fdir(adapter);
4536 else
4537 ixgbe_cache_ring_rss(adapter);
4538
4539 fcoe_rx_i = f->mask;
4540 fcoe_tx_i = f->mask;
4541 }
4542 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4543 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4544 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4545 }
4546 return true;
4547 }
4548
4549 #endif /* IXGBE_FCOE */
4550 /**
4551 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4552 * @adapter: board private structure to initialize
4553 *
4554 * SR-IOV doesn't use any descriptor rings but changes the default if
4555 * no other mapping is used.
4556 *
4557 */
4558 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4559 {
4560 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4561 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4562 if (adapter->num_vfs)
4563 return true;
4564 else
4565 return false;
4566 }
4567
4568 /**
4569 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4570 * @adapter: board private structure to initialize
4571 *
4572 * Once we know the feature-set enabled for the device, we'll cache
4573 * the register offset the descriptor ring is assigned to.
4574 *
4575 * Note, the order the various feature calls is important. It must start with
4576 * the "most" features enabled at the same time, then trickle down to the
4577 * least amount of features turned on at once.
4578 **/
4579 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4580 {
4581 /* start with default case */
4582 adapter->rx_ring[0]->reg_idx = 0;
4583 adapter->tx_ring[0]->reg_idx = 0;
4584
4585 if (ixgbe_cache_ring_sriov(adapter))
4586 return;
4587
4588 #ifdef CONFIG_IXGBE_DCB
4589 if (ixgbe_cache_ring_dcb(adapter))
4590 return;
4591 #endif
4592
4593 #ifdef IXGBE_FCOE
4594 if (ixgbe_cache_ring_fcoe(adapter))
4595 return;
4596 #endif /* IXGBE_FCOE */
4597
4598 if (ixgbe_cache_ring_fdir(adapter))
4599 return;
4600
4601 if (ixgbe_cache_ring_rss(adapter))
4602 return;
4603 }
4604
4605 /**
4606 * ixgbe_alloc_queues - Allocate memory for all rings
4607 * @adapter: board private structure to initialize
4608 *
4609 * We allocate one ring per queue at run-time since we don't know the
4610 * number of queues at compile-time. The polling_netdev array is
4611 * intended for Multiqueue, but should work fine with a single queue.
4612 **/
4613 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4614 {
4615 int rx = 0, tx = 0, nid = adapter->node;
4616
4617 if (nid < 0 || !node_online(nid))
4618 nid = first_online_node;
4619
4620 for (; tx < adapter->num_tx_queues; tx++) {
4621 struct ixgbe_ring *ring;
4622
4623 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4624 if (!ring)
4625 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4626 if (!ring)
4627 goto err_allocation;
4628 ring->count = adapter->tx_ring_count;
4629 ring->queue_index = tx;
4630 ring->numa_node = nid;
4631 ring->dev = &adapter->pdev->dev;
4632 ring->netdev = adapter->netdev;
4633
4634 adapter->tx_ring[tx] = ring;
4635 }
4636
4637 for (; rx < adapter->num_rx_queues; rx++) {
4638 struct ixgbe_ring *ring;
4639
4640 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4641 if (!ring)
4642 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4643 if (!ring)
4644 goto err_allocation;
4645 ring->count = adapter->rx_ring_count;
4646 ring->queue_index = rx;
4647 ring->numa_node = nid;
4648 ring->dev = &adapter->pdev->dev;
4649 ring->netdev = adapter->netdev;
4650
4651 adapter->rx_ring[rx] = ring;
4652 }
4653
4654 ixgbe_cache_ring_register(adapter);
4655
4656 return 0;
4657
4658 err_allocation:
4659 while (tx)
4660 kfree(adapter->tx_ring[--tx]);
4661
4662 while (rx)
4663 kfree(adapter->rx_ring[--rx]);
4664 return -ENOMEM;
4665 }
4666
4667 /**
4668 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4669 * @adapter: board private structure to initialize
4670 *
4671 * Attempt to configure the interrupts using the best available
4672 * capabilities of the hardware and the kernel.
4673 **/
4674 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4675 {
4676 struct ixgbe_hw *hw = &adapter->hw;
4677 int err = 0;
4678 int vector, v_budget;
4679
4680 /*
4681 * It's easy to be greedy for MSI-X vectors, but it really
4682 * doesn't do us much good if we have a lot more vectors
4683 * than CPU's. So let's be conservative and only ask for
4684 * (roughly) the same number of vectors as there are CPU's.
4685 */
4686 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4687 (int)num_online_cpus()) + NON_Q_VECTORS;
4688
4689 /*
4690 * At the same time, hardware can only support a maximum of
4691 * hw.mac->max_msix_vectors vectors. With features
4692 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4693 * descriptor queues supported by our device. Thus, we cap it off in
4694 * those rare cases where the cpu count also exceeds our vector limit.
4695 */
4696 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4697
4698 /* A failure in MSI-X entry allocation isn't fatal, but it does
4699 * mean we disable MSI-X capabilities of the adapter. */
4700 adapter->msix_entries = kcalloc(v_budget,
4701 sizeof(struct msix_entry), GFP_KERNEL);
4702 if (adapter->msix_entries) {
4703 for (vector = 0; vector < v_budget; vector++)
4704 adapter->msix_entries[vector].entry = vector;
4705
4706 ixgbe_acquire_msix_vectors(adapter, v_budget);
4707
4708 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4709 goto out;
4710 }
4711
4712 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4713 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4714 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4715 e_err(probe,
4716 "ATR is not supported while multiple "
4717 "queues are disabled. Disabling Flow Director\n");
4718 }
4719 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4720 adapter->atr_sample_rate = 0;
4721 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4722 ixgbe_disable_sriov(adapter);
4723
4724 err = ixgbe_set_num_queues(adapter);
4725 if (err)
4726 return err;
4727
4728 err = pci_enable_msi(adapter->pdev);
4729 if (!err) {
4730 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4731 } else {
4732 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4733 "Unable to allocate MSI interrupt, "
4734 "falling back to legacy. Error: %d\n", err);
4735 /* reset err */
4736 err = 0;
4737 }
4738
4739 out:
4740 return err;
4741 }
4742
4743 /**
4744 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4745 * @adapter: board private structure to initialize
4746 *
4747 * We allocate one q_vector per queue interrupt. If allocation fails we
4748 * return -ENOMEM.
4749 **/
4750 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4751 {
4752 int v_idx, num_q_vectors;
4753 struct ixgbe_q_vector *q_vector;
4754
4755 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4756 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4757 else
4758 num_q_vectors = 1;
4759
4760 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4761 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4762 GFP_KERNEL, adapter->node);
4763 if (!q_vector)
4764 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4765 GFP_KERNEL);
4766 if (!q_vector)
4767 goto err_out;
4768
4769 q_vector->adapter = adapter;
4770 q_vector->v_idx = v_idx;
4771
4772 /* Allocate the affinity_hint cpumask, configure the mask */
4773 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4774 goto err_out;
4775 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4776 netif_napi_add(adapter->netdev, &q_vector->napi,
4777 ixgbe_poll, 64);
4778 adapter->q_vector[v_idx] = q_vector;
4779 }
4780
4781 return 0;
4782
4783 err_out:
4784 while (v_idx) {
4785 v_idx--;
4786 q_vector = adapter->q_vector[v_idx];
4787 netif_napi_del(&q_vector->napi);
4788 free_cpumask_var(q_vector->affinity_mask);
4789 kfree(q_vector);
4790 adapter->q_vector[v_idx] = NULL;
4791 }
4792 return -ENOMEM;
4793 }
4794
4795 /**
4796 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4797 * @adapter: board private structure to initialize
4798 *
4799 * This function frees the memory allocated to the q_vectors. In addition if
4800 * NAPI is enabled it will delete any references to the NAPI struct prior
4801 * to freeing the q_vector.
4802 **/
4803 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4804 {
4805 int v_idx, num_q_vectors;
4806
4807 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4808 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4809 else
4810 num_q_vectors = 1;
4811
4812 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4813 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4814 adapter->q_vector[v_idx] = NULL;
4815 netif_napi_del(&q_vector->napi);
4816 free_cpumask_var(q_vector->affinity_mask);
4817 kfree(q_vector);
4818 }
4819 }
4820
4821 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4822 {
4823 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4824 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4825 pci_disable_msix(adapter->pdev);
4826 kfree(adapter->msix_entries);
4827 adapter->msix_entries = NULL;
4828 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4829 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4830 pci_disable_msi(adapter->pdev);
4831 }
4832 }
4833
4834 /**
4835 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4836 * @adapter: board private structure to initialize
4837 *
4838 * We determine which interrupt scheme to use based on...
4839 * - Kernel support (MSI, MSI-X)
4840 * - which can be user-defined (via MODULE_PARAM)
4841 * - Hardware queue count (num_*_queues)
4842 * - defined by miscellaneous hardware support/features (RSS, etc.)
4843 **/
4844 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4845 {
4846 int err;
4847
4848 /* Number of supported queues */
4849 err = ixgbe_set_num_queues(adapter);
4850 if (err)
4851 return err;
4852
4853 err = ixgbe_set_interrupt_capability(adapter);
4854 if (err) {
4855 e_dev_err("Unable to setup interrupt capabilities\n");
4856 goto err_set_interrupt;
4857 }
4858
4859 err = ixgbe_alloc_q_vectors(adapter);
4860 if (err) {
4861 e_dev_err("Unable to allocate memory for queue vectors\n");
4862 goto err_alloc_q_vectors;
4863 }
4864
4865 err = ixgbe_alloc_queues(adapter);
4866 if (err) {
4867 e_dev_err("Unable to allocate memory for queues\n");
4868 goto err_alloc_queues;
4869 }
4870
4871 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4872 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4873 adapter->num_rx_queues, adapter->num_tx_queues);
4874
4875 set_bit(__IXGBE_DOWN, &adapter->state);
4876
4877 return 0;
4878
4879 err_alloc_queues:
4880 ixgbe_free_q_vectors(adapter);
4881 err_alloc_q_vectors:
4882 ixgbe_reset_interrupt_capability(adapter);
4883 err_set_interrupt:
4884 return err;
4885 }
4886
4887 /**
4888 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4889 * @adapter: board private structure to clear interrupt scheme on
4890 *
4891 * We go through and clear interrupt specific resources and reset the structure
4892 * to pre-load conditions
4893 **/
4894 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4895 {
4896 int i;
4897
4898 for (i = 0; i < adapter->num_tx_queues; i++) {
4899 kfree(adapter->tx_ring[i]);
4900 adapter->tx_ring[i] = NULL;
4901 }
4902 for (i = 0; i < adapter->num_rx_queues; i++) {
4903 struct ixgbe_ring *ring = adapter->rx_ring[i];
4904
4905 /* ixgbe_get_stats64() might access this ring, we must wait
4906 * a grace period before freeing it.
4907 */
4908 kfree_rcu(ring, rcu);
4909 adapter->rx_ring[i] = NULL;
4910 }
4911
4912 adapter->num_tx_queues = 0;
4913 adapter->num_rx_queues = 0;
4914
4915 ixgbe_free_q_vectors(adapter);
4916 ixgbe_reset_interrupt_capability(adapter);
4917 }
4918
4919 /**
4920 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4921 * @adapter: board private structure to initialize
4922 *
4923 * ixgbe_sw_init initializes the Adapter private data structure.
4924 * Fields are initialized based on PCI device information and
4925 * OS network device settings (MTU size).
4926 **/
4927 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4928 {
4929 struct ixgbe_hw *hw = &adapter->hw;
4930 struct pci_dev *pdev = adapter->pdev;
4931 unsigned int rss;
4932 #ifdef CONFIG_IXGBE_DCB
4933 int j;
4934 struct tc_configuration *tc;
4935 #endif
4936
4937 /* PCI config space info */
4938
4939 hw->vendor_id = pdev->vendor;
4940 hw->device_id = pdev->device;
4941 hw->revision_id = pdev->revision;
4942 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4943 hw->subsystem_device_id = pdev->subsystem_device;
4944
4945 /* Set capability flags */
4946 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4947 adapter->ring_feature[RING_F_RSS].indices = rss;
4948 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4949 switch (hw->mac.type) {
4950 case ixgbe_mac_82598EB:
4951 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4952 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4953 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4954 break;
4955 case ixgbe_mac_X540:
4956 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4957 case ixgbe_mac_82599EB:
4958 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4959 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4960 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4961 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4962 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4963 /* Flow Director hash filters enabled */
4964 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4965 adapter->atr_sample_rate = 20;
4966 adapter->ring_feature[RING_F_FDIR].indices =
4967 IXGBE_MAX_FDIR_INDICES;
4968 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4969 #ifdef IXGBE_FCOE
4970 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4971 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4972 adapter->ring_feature[RING_F_FCOE].indices = 0;
4973 #ifdef CONFIG_IXGBE_DCB
4974 /* Default traffic class to use for FCoE */
4975 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4976 #endif
4977 #endif /* IXGBE_FCOE */
4978 break;
4979 default:
4980 break;
4981 }
4982
4983 /* n-tuple support exists, always init our spinlock */
4984 spin_lock_init(&adapter->fdir_perfect_lock);
4985
4986 #ifdef CONFIG_IXGBE_DCB
4987 /* Configure DCB traffic classes */
4988 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4989 tc = &adapter->dcb_cfg.tc_config[j];
4990 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4991 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4992 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4993 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4994 tc->dcb_pfc = pfc_disabled;
4995 }
4996 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4997 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4998 adapter->dcb_cfg.pfc_mode_enable = false;
4999 adapter->dcb_set_bitmap = 0x00;
5000 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5001 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5002 MAX_TRAFFIC_CLASS);
5003
5004 #endif
5005
5006 /* default flow control settings */
5007 hw->fc.requested_mode = ixgbe_fc_full;
5008 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5009 #ifdef CONFIG_DCB
5010 adapter->last_lfc_mode = hw->fc.current_mode;
5011 #endif
5012 ixgbe_pbthresh_setup(adapter);
5013 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5014 hw->fc.send_xon = true;
5015 hw->fc.disable_fc_autoneg = false;
5016
5017 /* enable itr by default in dynamic mode */
5018 adapter->rx_itr_setting = 1;
5019 adapter->tx_itr_setting = 1;
5020
5021 /* set defaults for eitr in MegaBytes */
5022 adapter->eitr_low = 10;
5023 adapter->eitr_high = 20;
5024
5025 /* set default ring sizes */
5026 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5027 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5028
5029 /* set default work limits */
5030 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5031
5032 /* initialize eeprom parameters */
5033 if (ixgbe_init_eeprom_params_generic(hw)) {
5034 e_dev_err("EEPROM initialization failed\n");
5035 return -EIO;
5036 }
5037
5038 /* enable rx csum by default */
5039 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5040
5041 /* get assigned NUMA node */
5042 adapter->node = dev_to_node(&pdev->dev);
5043
5044 set_bit(__IXGBE_DOWN, &adapter->state);
5045
5046 return 0;
5047 }
5048
5049 /**
5050 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5051 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5052 *
5053 * Return 0 on success, negative on failure
5054 **/
5055 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5056 {
5057 struct device *dev = tx_ring->dev;
5058 int size;
5059
5060 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5061 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5062 if (!tx_ring->tx_buffer_info)
5063 tx_ring->tx_buffer_info = vzalloc(size);
5064 if (!tx_ring->tx_buffer_info)
5065 goto err;
5066
5067 /* round up to nearest 4K */
5068 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5069 tx_ring->size = ALIGN(tx_ring->size, 4096);
5070
5071 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5072 &tx_ring->dma, GFP_KERNEL);
5073 if (!tx_ring->desc)
5074 goto err;
5075
5076 tx_ring->next_to_use = 0;
5077 tx_ring->next_to_clean = 0;
5078 return 0;
5079
5080 err:
5081 vfree(tx_ring->tx_buffer_info);
5082 tx_ring->tx_buffer_info = NULL;
5083 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5084 return -ENOMEM;
5085 }
5086
5087 /**
5088 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5089 * @adapter: board private structure
5090 *
5091 * If this function returns with an error, then it's possible one or
5092 * more of the rings is populated (while the rest are not). It is the
5093 * callers duty to clean those orphaned rings.
5094 *
5095 * Return 0 on success, negative on failure
5096 **/
5097 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5098 {
5099 int i, err = 0;
5100
5101 for (i = 0; i < adapter->num_tx_queues; i++) {
5102 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5103 if (!err)
5104 continue;
5105 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5106 break;
5107 }
5108
5109 return err;
5110 }
5111
5112 /**
5113 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5114 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5115 *
5116 * Returns 0 on success, negative on failure
5117 **/
5118 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5119 {
5120 struct device *dev = rx_ring->dev;
5121 int size;
5122
5123 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5124 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5125 if (!rx_ring->rx_buffer_info)
5126 rx_ring->rx_buffer_info = vzalloc(size);
5127 if (!rx_ring->rx_buffer_info)
5128 goto err;
5129
5130 /* Round up to nearest 4K */
5131 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5132 rx_ring->size = ALIGN(rx_ring->size, 4096);
5133
5134 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5135 &rx_ring->dma, GFP_KERNEL);
5136
5137 if (!rx_ring->desc)
5138 goto err;
5139
5140 rx_ring->next_to_clean = 0;
5141 rx_ring->next_to_use = 0;
5142
5143 return 0;
5144 err:
5145 vfree(rx_ring->rx_buffer_info);
5146 rx_ring->rx_buffer_info = NULL;
5147 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5148 return -ENOMEM;
5149 }
5150
5151 /**
5152 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5153 * @adapter: board private structure
5154 *
5155 * If this function returns with an error, then it's possible one or
5156 * more of the rings is populated (while the rest are not). It is the
5157 * callers duty to clean those orphaned rings.
5158 *
5159 * Return 0 on success, negative on failure
5160 **/
5161 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5162 {
5163 int i, err = 0;
5164
5165 for (i = 0; i < adapter->num_rx_queues; i++) {
5166 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5167 if (!err)
5168 continue;
5169 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5170 break;
5171 }
5172
5173 return err;
5174 }
5175
5176 /**
5177 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5178 * @tx_ring: Tx descriptor ring for a specific queue
5179 *
5180 * Free all transmit software resources
5181 **/
5182 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5183 {
5184 ixgbe_clean_tx_ring(tx_ring);
5185
5186 vfree(tx_ring->tx_buffer_info);
5187 tx_ring->tx_buffer_info = NULL;
5188
5189 /* if not set, then don't free */
5190 if (!tx_ring->desc)
5191 return;
5192
5193 dma_free_coherent(tx_ring->dev, tx_ring->size,
5194 tx_ring->desc, tx_ring->dma);
5195
5196 tx_ring->desc = NULL;
5197 }
5198
5199 /**
5200 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5201 * @adapter: board private structure
5202 *
5203 * Free all transmit software resources
5204 **/
5205 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5206 {
5207 int i;
5208
5209 for (i = 0; i < adapter->num_tx_queues; i++)
5210 if (adapter->tx_ring[i]->desc)
5211 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5212 }
5213
5214 /**
5215 * ixgbe_free_rx_resources - Free Rx Resources
5216 * @rx_ring: ring to clean the resources from
5217 *
5218 * Free all receive software resources
5219 **/
5220 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5221 {
5222 ixgbe_clean_rx_ring(rx_ring);
5223
5224 vfree(rx_ring->rx_buffer_info);
5225 rx_ring->rx_buffer_info = NULL;
5226
5227 /* if not set, then don't free */
5228 if (!rx_ring->desc)
5229 return;
5230
5231 dma_free_coherent(rx_ring->dev, rx_ring->size,
5232 rx_ring->desc, rx_ring->dma);
5233
5234 rx_ring->desc = NULL;
5235 }
5236
5237 /**
5238 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5239 * @adapter: board private structure
5240 *
5241 * Free all receive software resources
5242 **/
5243 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5244 {
5245 int i;
5246
5247 for (i = 0; i < adapter->num_rx_queues; i++)
5248 if (adapter->rx_ring[i]->desc)
5249 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5250 }
5251
5252 /**
5253 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5254 * @netdev: network interface device structure
5255 * @new_mtu: new value for maximum frame size
5256 *
5257 * Returns 0 on success, negative on failure
5258 **/
5259 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5260 {
5261 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5262 struct ixgbe_hw *hw = &adapter->hw;
5263 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5264
5265 /* MTU < 68 is an error and causes problems on some kernels */
5266 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5267 hw->mac.type != ixgbe_mac_X540) {
5268 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5269 return -EINVAL;
5270 } else {
5271 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5272 return -EINVAL;
5273 }
5274
5275 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5276 /* must set new MTU before calling down or up */
5277 netdev->mtu = new_mtu;
5278
5279 if (netif_running(netdev))
5280 ixgbe_reinit_locked(adapter);
5281
5282 return 0;
5283 }
5284
5285 /**
5286 * ixgbe_open - Called when a network interface is made active
5287 * @netdev: network interface device structure
5288 *
5289 * Returns 0 on success, negative value on failure
5290 *
5291 * The open entry point is called when a network interface is made
5292 * active by the system (IFF_UP). At this point all resources needed
5293 * for transmit and receive operations are allocated, the interrupt
5294 * handler is registered with the OS, the watchdog timer is started,
5295 * and the stack is notified that the interface is ready.
5296 **/
5297 static int ixgbe_open(struct net_device *netdev)
5298 {
5299 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5300 int err;
5301
5302 /* disallow open during test */
5303 if (test_bit(__IXGBE_TESTING, &adapter->state))
5304 return -EBUSY;
5305
5306 netif_carrier_off(netdev);
5307
5308 /* allocate transmit descriptors */
5309 err = ixgbe_setup_all_tx_resources(adapter);
5310 if (err)
5311 goto err_setup_tx;
5312
5313 /* allocate receive descriptors */
5314 err = ixgbe_setup_all_rx_resources(adapter);
5315 if (err)
5316 goto err_setup_rx;
5317
5318 ixgbe_configure(adapter);
5319
5320 err = ixgbe_request_irq(adapter);
5321 if (err)
5322 goto err_req_irq;
5323
5324 ixgbe_up_complete(adapter);
5325
5326 return 0;
5327
5328 err_req_irq:
5329 err_setup_rx:
5330 ixgbe_free_all_rx_resources(adapter);
5331 err_setup_tx:
5332 ixgbe_free_all_tx_resources(adapter);
5333 ixgbe_reset(adapter);
5334
5335 return err;
5336 }
5337
5338 /**
5339 * ixgbe_close - Disables a network interface
5340 * @netdev: network interface device structure
5341 *
5342 * Returns 0, this is not allowed to fail
5343 *
5344 * The close entry point is called when an interface is de-activated
5345 * by the OS. The hardware is still under the drivers control, but
5346 * needs to be disabled. A global MAC reset is issued to stop the
5347 * hardware, and all transmit and receive resources are freed.
5348 **/
5349 static int ixgbe_close(struct net_device *netdev)
5350 {
5351 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5352
5353 ixgbe_down(adapter);
5354 ixgbe_free_irq(adapter);
5355
5356 ixgbe_fdir_filter_exit(adapter);
5357
5358 ixgbe_free_all_tx_resources(adapter);
5359 ixgbe_free_all_rx_resources(adapter);
5360
5361 ixgbe_release_hw_control(adapter);
5362
5363 return 0;
5364 }
5365
5366 #ifdef CONFIG_PM
5367 static int ixgbe_resume(struct pci_dev *pdev)
5368 {
5369 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5370 struct net_device *netdev = adapter->netdev;
5371 u32 err;
5372
5373 pci_set_power_state(pdev, PCI_D0);
5374 pci_restore_state(pdev);
5375 /*
5376 * pci_restore_state clears dev->state_saved so call
5377 * pci_save_state to restore it.
5378 */
5379 pci_save_state(pdev);
5380
5381 err = pci_enable_device_mem(pdev);
5382 if (err) {
5383 e_dev_err("Cannot enable PCI device from suspend\n");
5384 return err;
5385 }
5386 pci_set_master(pdev);
5387
5388 pci_wake_from_d3(pdev, false);
5389
5390 err = ixgbe_init_interrupt_scheme(adapter);
5391 if (err) {
5392 e_dev_err("Cannot initialize interrupts for device\n");
5393 return err;
5394 }
5395
5396 ixgbe_reset(adapter);
5397
5398 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5399
5400 if (netif_running(netdev)) {
5401 err = ixgbe_open(netdev);
5402 if (err)
5403 return err;
5404 }
5405
5406 netif_device_attach(netdev);
5407
5408 return 0;
5409 }
5410 #endif /* CONFIG_PM */
5411
5412 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5413 {
5414 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5415 struct net_device *netdev = adapter->netdev;
5416 struct ixgbe_hw *hw = &adapter->hw;
5417 u32 ctrl, fctrl;
5418 u32 wufc = adapter->wol;
5419 #ifdef CONFIG_PM
5420 int retval = 0;
5421 #endif
5422
5423 netif_device_detach(netdev);
5424
5425 if (netif_running(netdev)) {
5426 ixgbe_down(adapter);
5427 ixgbe_free_irq(adapter);
5428 ixgbe_free_all_tx_resources(adapter);
5429 ixgbe_free_all_rx_resources(adapter);
5430 }
5431
5432 ixgbe_clear_interrupt_scheme(adapter);
5433 #ifdef CONFIG_DCB
5434 kfree(adapter->ixgbe_ieee_pfc);
5435 kfree(adapter->ixgbe_ieee_ets);
5436 #endif
5437
5438 #ifdef CONFIG_PM
5439 retval = pci_save_state(pdev);
5440 if (retval)
5441 return retval;
5442
5443 #endif
5444 if (wufc) {
5445 ixgbe_set_rx_mode(netdev);
5446
5447 /* turn on all-multi mode if wake on multicast is enabled */
5448 if (wufc & IXGBE_WUFC_MC) {
5449 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5450 fctrl |= IXGBE_FCTRL_MPE;
5451 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5452 }
5453
5454 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5455 ctrl |= IXGBE_CTRL_GIO_DIS;
5456 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5457
5458 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5459 } else {
5460 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5461 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5462 }
5463
5464 switch (hw->mac.type) {
5465 case ixgbe_mac_82598EB:
5466 pci_wake_from_d3(pdev, false);
5467 break;
5468 case ixgbe_mac_82599EB:
5469 case ixgbe_mac_X540:
5470 pci_wake_from_d3(pdev, !!wufc);
5471 break;
5472 default:
5473 break;
5474 }
5475
5476 *enable_wake = !!wufc;
5477
5478 ixgbe_release_hw_control(adapter);
5479
5480 pci_disable_device(pdev);
5481
5482 return 0;
5483 }
5484
5485 #ifdef CONFIG_PM
5486 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5487 {
5488 int retval;
5489 bool wake;
5490
5491 retval = __ixgbe_shutdown(pdev, &wake);
5492 if (retval)
5493 return retval;
5494
5495 if (wake) {
5496 pci_prepare_to_sleep(pdev);
5497 } else {
5498 pci_wake_from_d3(pdev, false);
5499 pci_set_power_state(pdev, PCI_D3hot);
5500 }
5501
5502 return 0;
5503 }
5504 #endif /* CONFIG_PM */
5505
5506 static void ixgbe_shutdown(struct pci_dev *pdev)
5507 {
5508 bool wake;
5509
5510 __ixgbe_shutdown(pdev, &wake);
5511
5512 if (system_state == SYSTEM_POWER_OFF) {
5513 pci_wake_from_d3(pdev, wake);
5514 pci_set_power_state(pdev, PCI_D3hot);
5515 }
5516 }
5517
5518 /**
5519 * ixgbe_update_stats - Update the board statistics counters.
5520 * @adapter: board private structure
5521 **/
5522 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5523 {
5524 struct net_device *netdev = adapter->netdev;
5525 struct ixgbe_hw *hw = &adapter->hw;
5526 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5527 u64 total_mpc = 0;
5528 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5529 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5530 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5531 u64 bytes = 0, packets = 0;
5532
5533 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5534 test_bit(__IXGBE_RESETTING, &adapter->state))
5535 return;
5536
5537 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5538 u64 rsc_count = 0;
5539 u64 rsc_flush = 0;
5540 for (i = 0; i < 16; i++)
5541 adapter->hw_rx_no_dma_resources +=
5542 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5543 for (i = 0; i < adapter->num_rx_queues; i++) {
5544 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5545 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5546 }
5547 adapter->rsc_total_count = rsc_count;
5548 adapter->rsc_total_flush = rsc_flush;
5549 }
5550
5551 for (i = 0; i < adapter->num_rx_queues; i++) {
5552 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5553 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5554 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5555 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5556 bytes += rx_ring->stats.bytes;
5557 packets += rx_ring->stats.packets;
5558 }
5559 adapter->non_eop_descs = non_eop_descs;
5560 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5561 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5562 netdev->stats.rx_bytes = bytes;
5563 netdev->stats.rx_packets = packets;
5564
5565 bytes = 0;
5566 packets = 0;
5567 /* gather some stats to the adapter struct that are per queue */
5568 for (i = 0; i < adapter->num_tx_queues; i++) {
5569 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5570 restart_queue += tx_ring->tx_stats.restart_queue;
5571 tx_busy += tx_ring->tx_stats.tx_busy;
5572 bytes += tx_ring->stats.bytes;
5573 packets += tx_ring->stats.packets;
5574 }
5575 adapter->restart_queue = restart_queue;
5576 adapter->tx_busy = tx_busy;
5577 netdev->stats.tx_bytes = bytes;
5578 netdev->stats.tx_packets = packets;
5579
5580 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5581
5582 /* 8 register reads */
5583 for (i = 0; i < 8; i++) {
5584 /* for packet buffers not used, the register should read 0 */
5585 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5586 missed_rx += mpc;
5587 hwstats->mpc[i] += mpc;
5588 total_mpc += hwstats->mpc[i];
5589 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5590 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5591 switch (hw->mac.type) {
5592 case ixgbe_mac_82598EB:
5593 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5594 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5595 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5596 hwstats->pxonrxc[i] +=
5597 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5598 break;
5599 case ixgbe_mac_82599EB:
5600 case ixgbe_mac_X540:
5601 hwstats->pxonrxc[i] +=
5602 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5603 break;
5604 default:
5605 break;
5606 }
5607 }
5608
5609 /*16 register reads */
5610 for (i = 0; i < 16; i++) {
5611 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5612 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5613 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5614 (hw->mac.type == ixgbe_mac_X540)) {
5615 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5616 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5617 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5618 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5619 }
5620 }
5621
5622 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5623 /* work around hardware counting issue */
5624 hwstats->gprc -= missed_rx;
5625
5626 ixgbe_update_xoff_received(adapter);
5627
5628 /* 82598 hardware only has a 32 bit counter in the high register */
5629 switch (hw->mac.type) {
5630 case ixgbe_mac_82598EB:
5631 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5632 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5633 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5634 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5635 break;
5636 case ixgbe_mac_X540:
5637 /* OS2BMC stats are X540 only*/
5638 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5639 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5640 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5641 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5642 case ixgbe_mac_82599EB:
5643 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5644 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5645 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5646 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5647 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5648 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5649 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5650 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5651 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5652 #ifdef IXGBE_FCOE
5653 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5654 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5655 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5656 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5657 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5658 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5659 #endif /* IXGBE_FCOE */
5660 break;
5661 default:
5662 break;
5663 }
5664 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5665 hwstats->bprc += bprc;
5666 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5667 if (hw->mac.type == ixgbe_mac_82598EB)
5668 hwstats->mprc -= bprc;
5669 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5670 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5671 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5672 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5673 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5674 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5675 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5676 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5677 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5678 hwstats->lxontxc += lxon;
5679 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5680 hwstats->lxofftxc += lxoff;
5681 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5682 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5683 /*
5684 * 82598 errata - tx of flow control packets is included in tx counters
5685 */
5686 xon_off_tot = lxon + lxoff;
5687 hwstats->gptc -= xon_off_tot;
5688 hwstats->mptc -= xon_off_tot;
5689 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5690 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5691 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5692 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5693 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5694 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5695 hwstats->ptc64 -= xon_off_tot;
5696 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5697 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5698 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5699 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5700 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5701 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5702
5703 /* Fill out the OS statistics structure */
5704 netdev->stats.multicast = hwstats->mprc;
5705
5706 /* Rx Errors */
5707 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5708 netdev->stats.rx_dropped = 0;
5709 netdev->stats.rx_length_errors = hwstats->rlec;
5710 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5711 netdev->stats.rx_missed_errors = total_mpc;
5712 }
5713
5714 /**
5715 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5716 * @adapter - pointer to the device adapter structure
5717 **/
5718 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5719 {
5720 struct ixgbe_hw *hw = &adapter->hw;
5721 int i;
5722
5723 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5724 return;
5725
5726 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5727
5728 /* if interface is down do nothing */
5729 if (test_bit(__IXGBE_DOWN, &adapter->state))
5730 return;
5731
5732 /* do nothing if we are not using signature filters */
5733 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5734 return;
5735
5736 adapter->fdir_overflow++;
5737
5738 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5739 for (i = 0; i < adapter->num_tx_queues; i++)
5740 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5741 &(adapter->tx_ring[i]->state));
5742 /* re-enable flow director interrupts */
5743 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5744 } else {
5745 e_err(probe, "failed to finish FDIR re-initialization, "
5746 "ignored adding FDIR ATR filters\n");
5747 }
5748 }
5749
5750 /**
5751 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5752 * @adapter - pointer to the device adapter structure
5753 *
5754 * This function serves two purposes. First it strobes the interrupt lines
5755 * in order to make certain interrupts are occuring. Secondly it sets the
5756 * bits needed to check for TX hangs. As a result we should immediately
5757 * determine if a hang has occured.
5758 */
5759 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5760 {
5761 struct ixgbe_hw *hw = &adapter->hw;
5762 u64 eics = 0;
5763 int i;
5764
5765 /* If we're down or resetting, just bail */
5766 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5767 test_bit(__IXGBE_RESETTING, &adapter->state))
5768 return;
5769
5770 /* Force detection of hung controller */
5771 if (netif_carrier_ok(adapter->netdev)) {
5772 for (i = 0; i < adapter->num_tx_queues; i++)
5773 set_check_for_tx_hang(adapter->tx_ring[i]);
5774 }
5775
5776 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5777 /*
5778 * for legacy and MSI interrupts don't set any bits
5779 * that are enabled for EIAM, because this operation
5780 * would set *both* EIMS and EICS for any bit in EIAM
5781 */
5782 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5783 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5784 } else {
5785 /* get one bit for every active tx/rx interrupt vector */
5786 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5787 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5788 if (qv->rx.ring || qv->tx.ring)
5789 eics |= ((u64)1 << i);
5790 }
5791 }
5792
5793 /* Cause software interrupt to ensure rings are cleaned */
5794 ixgbe_irq_rearm_queues(adapter, eics);
5795
5796 }
5797
5798 /**
5799 * ixgbe_watchdog_update_link - update the link status
5800 * @adapter - pointer to the device adapter structure
5801 * @link_speed - pointer to a u32 to store the link_speed
5802 **/
5803 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5804 {
5805 struct ixgbe_hw *hw = &adapter->hw;
5806 u32 link_speed = adapter->link_speed;
5807 bool link_up = adapter->link_up;
5808 int i;
5809
5810 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5811 return;
5812
5813 if (hw->mac.ops.check_link) {
5814 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5815 } else {
5816 /* always assume link is up, if no check link function */
5817 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5818 link_up = true;
5819 }
5820 if (link_up) {
5821 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5822 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5823 hw->mac.ops.fc_enable(hw, i);
5824 } else {
5825 hw->mac.ops.fc_enable(hw, 0);
5826 }
5827 }
5828
5829 if (link_up ||
5830 time_after(jiffies, (adapter->link_check_timeout +
5831 IXGBE_TRY_LINK_TIMEOUT))) {
5832 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5833 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5834 IXGBE_WRITE_FLUSH(hw);
5835 }
5836
5837 adapter->link_up = link_up;
5838 adapter->link_speed = link_speed;
5839 }
5840
5841 /**
5842 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5843 * print link up message
5844 * @adapter - pointer to the device adapter structure
5845 **/
5846 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5847 {
5848 struct net_device *netdev = adapter->netdev;
5849 struct ixgbe_hw *hw = &adapter->hw;
5850 u32 link_speed = adapter->link_speed;
5851 bool flow_rx, flow_tx;
5852
5853 /* only continue if link was previously down */
5854 if (netif_carrier_ok(netdev))
5855 return;
5856
5857 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5858
5859 switch (hw->mac.type) {
5860 case ixgbe_mac_82598EB: {
5861 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5862 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5863 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5864 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5865 }
5866 break;
5867 case ixgbe_mac_X540:
5868 case ixgbe_mac_82599EB: {
5869 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5870 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5871 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5872 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5873 }
5874 break;
5875 default:
5876 flow_tx = false;
5877 flow_rx = false;
5878 break;
5879 }
5880 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5881 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5882 "10 Gbps" :
5883 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5884 "1 Gbps" :
5885 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5886 "100 Mbps" :
5887 "unknown speed"))),
5888 ((flow_rx && flow_tx) ? "RX/TX" :
5889 (flow_rx ? "RX" :
5890 (flow_tx ? "TX" : "None"))));
5891
5892 netif_carrier_on(netdev);
5893 ixgbe_check_vf_rate_limit(adapter);
5894 }
5895
5896 /**
5897 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5898 * print link down message
5899 * @adapter - pointer to the adapter structure
5900 **/
5901 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
5902 {
5903 struct net_device *netdev = adapter->netdev;
5904 struct ixgbe_hw *hw = &adapter->hw;
5905
5906 adapter->link_up = false;
5907 adapter->link_speed = 0;
5908
5909 /* only continue if link was up previously */
5910 if (!netif_carrier_ok(netdev))
5911 return;
5912
5913 /* poll for SFP+ cable when link is down */
5914 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5915 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5916
5917 e_info(drv, "NIC Link is Down\n");
5918 netif_carrier_off(netdev);
5919 }
5920
5921 /**
5922 * ixgbe_watchdog_flush_tx - flush queues on link down
5923 * @adapter - pointer to the device adapter structure
5924 **/
5925 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5926 {
5927 int i;
5928 int some_tx_pending = 0;
5929
5930 if (!netif_carrier_ok(adapter->netdev)) {
5931 for (i = 0; i < adapter->num_tx_queues; i++) {
5932 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5933 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5934 some_tx_pending = 1;
5935 break;
5936 }
5937 }
5938
5939 if (some_tx_pending) {
5940 /* We've lost link, so the controller stops DMA,
5941 * but we've got queued Tx work that's never going
5942 * to get done, so reset controller to flush Tx.
5943 * (Do the reset outside of interrupt context).
5944 */
5945 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5946 }
5947 }
5948 }
5949
5950 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5951 {
5952 u32 ssvpc;
5953
5954 /* Do not perform spoof check for 82598 */
5955 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5956 return;
5957
5958 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5959
5960 /*
5961 * ssvpc register is cleared on read, if zero then no
5962 * spoofed packets in the last interval.
5963 */
5964 if (!ssvpc)
5965 return;
5966
5967 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5968 }
5969
5970 /**
5971 * ixgbe_watchdog_subtask - check and bring link up
5972 * @adapter - pointer to the device adapter structure
5973 **/
5974 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5975 {
5976 /* if interface is down do nothing */
5977 if (test_bit(__IXGBE_DOWN, &adapter->state))
5978 return;
5979
5980 ixgbe_watchdog_update_link(adapter);
5981
5982 if (adapter->link_up)
5983 ixgbe_watchdog_link_is_up(adapter);
5984 else
5985 ixgbe_watchdog_link_is_down(adapter);
5986
5987 ixgbe_spoof_check(adapter);
5988 ixgbe_update_stats(adapter);
5989
5990 ixgbe_watchdog_flush_tx(adapter);
5991 }
5992
5993 /**
5994 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5995 * @adapter - the ixgbe adapter structure
5996 **/
5997 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5998 {
5999 struct ixgbe_hw *hw = &adapter->hw;
6000 s32 err;
6001
6002 /* not searching for SFP so there is nothing to do here */
6003 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6004 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6005 return;
6006
6007 /* someone else is in init, wait until next service event */
6008 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6009 return;
6010
6011 err = hw->phy.ops.identify_sfp(hw);
6012 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6013 goto sfp_out;
6014
6015 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6016 /* If no cable is present, then we need to reset
6017 * the next time we find a good cable. */
6018 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6019 }
6020
6021 /* exit on error */
6022 if (err)
6023 goto sfp_out;
6024
6025 /* exit if reset not needed */
6026 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6027 goto sfp_out;
6028
6029 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6030
6031 /*
6032 * A module may be identified correctly, but the EEPROM may not have
6033 * support for that module. setup_sfp() will fail in that case, so
6034 * we should not allow that module to load.
6035 */
6036 if (hw->mac.type == ixgbe_mac_82598EB)
6037 err = hw->phy.ops.reset(hw);
6038 else
6039 err = hw->mac.ops.setup_sfp(hw);
6040
6041 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6042 goto sfp_out;
6043
6044 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6045 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6046
6047 sfp_out:
6048 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6049
6050 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6051 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6052 e_dev_err("failed to initialize because an unsupported "
6053 "SFP+ module type was detected.\n");
6054 e_dev_err("Reload the driver after installing a "
6055 "supported module.\n");
6056 unregister_netdev(adapter->netdev);
6057 }
6058 }
6059
6060 /**
6061 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6062 * @adapter - the ixgbe adapter structure
6063 **/
6064 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6065 {
6066 struct ixgbe_hw *hw = &adapter->hw;
6067 u32 autoneg;
6068 bool negotiation;
6069
6070 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6071 return;
6072
6073 /* someone else is in init, wait until next service event */
6074 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6075 return;
6076
6077 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6078
6079 autoneg = hw->phy.autoneg_advertised;
6080 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6081 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6082 hw->mac.autotry_restart = false;
6083 if (hw->mac.ops.setup_link)
6084 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6085
6086 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6087 adapter->link_check_timeout = jiffies;
6088 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6089 }
6090
6091 /**
6092 * ixgbe_service_timer - Timer Call-back
6093 * @data: pointer to adapter cast into an unsigned long
6094 **/
6095 static void ixgbe_service_timer(unsigned long data)
6096 {
6097 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6098 unsigned long next_event_offset;
6099
6100 /* poll faster when waiting for link */
6101 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6102 next_event_offset = HZ / 10;
6103 else
6104 next_event_offset = HZ * 2;
6105
6106 /* Reset the timer */
6107 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6108
6109 ixgbe_service_event_schedule(adapter);
6110 }
6111
6112 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6113 {
6114 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6115 return;
6116
6117 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6118
6119 /* If we're already down or resetting, just bail */
6120 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6121 test_bit(__IXGBE_RESETTING, &adapter->state))
6122 return;
6123
6124 ixgbe_dump(adapter);
6125 netdev_err(adapter->netdev, "Reset adapter\n");
6126 adapter->tx_timeout_count++;
6127
6128 ixgbe_reinit_locked(adapter);
6129 }
6130
6131 /**
6132 * ixgbe_service_task - manages and runs subtasks
6133 * @work: pointer to work_struct containing our data
6134 **/
6135 static void ixgbe_service_task(struct work_struct *work)
6136 {
6137 struct ixgbe_adapter *adapter = container_of(work,
6138 struct ixgbe_adapter,
6139 service_task);
6140
6141 ixgbe_reset_subtask(adapter);
6142 ixgbe_sfp_detection_subtask(adapter);
6143 ixgbe_sfp_link_config_subtask(adapter);
6144 ixgbe_check_overtemp_subtask(adapter);
6145 ixgbe_watchdog_subtask(adapter);
6146 ixgbe_fdir_reinit_subtask(adapter);
6147 ixgbe_check_hang_subtask(adapter);
6148
6149 ixgbe_service_event_complete(adapter);
6150 }
6151
6152 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6153 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6154 {
6155 struct ixgbe_adv_tx_context_desc *context_desc;
6156 u16 i = tx_ring->next_to_use;
6157
6158 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6159
6160 i++;
6161 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6162
6163 /* set bits to identify this as an advanced context descriptor */
6164 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6165
6166 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6167 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6168 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6169 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6170 }
6171
6172 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6173 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6174 {
6175 int err;
6176 u32 vlan_macip_lens, type_tucmd;
6177 u32 mss_l4len_idx, l4len;
6178
6179 if (!skb_is_gso(skb))
6180 return 0;
6181
6182 if (skb_header_cloned(skb)) {
6183 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6184 if (err)
6185 return err;
6186 }
6187
6188 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6189 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6190
6191 if (protocol == __constant_htons(ETH_P_IP)) {
6192 struct iphdr *iph = ip_hdr(skb);
6193 iph->tot_len = 0;
6194 iph->check = 0;
6195 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6196 iph->daddr, 0,
6197 IPPROTO_TCP,
6198 0);
6199 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6200 } else if (skb_is_gso_v6(skb)) {
6201 ipv6_hdr(skb)->payload_len = 0;
6202 tcp_hdr(skb)->check =
6203 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6204 &ipv6_hdr(skb)->daddr,
6205 0, IPPROTO_TCP, 0);
6206 }
6207
6208 l4len = tcp_hdrlen(skb);
6209 *hdr_len = skb_transport_offset(skb) + l4len;
6210
6211 /* mss_l4len_id: use 1 as index for TSO */
6212 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6213 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6214 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6215
6216 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6217 vlan_macip_lens = skb_network_header_len(skb);
6218 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6219 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6220
6221 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6222 mss_l4len_idx);
6223
6224 return 1;
6225 }
6226
6227 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6228 struct sk_buff *skb, u32 tx_flags,
6229 __be16 protocol)
6230 {
6231 u32 vlan_macip_lens = 0;
6232 u32 mss_l4len_idx = 0;
6233 u32 type_tucmd = 0;
6234
6235 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6236 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6237 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
6238 return false;
6239 } else {
6240 u8 l4_hdr = 0;
6241 switch (protocol) {
6242 case __constant_htons(ETH_P_IP):
6243 vlan_macip_lens |= skb_network_header_len(skb);
6244 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6245 l4_hdr = ip_hdr(skb)->protocol;
6246 break;
6247 case __constant_htons(ETH_P_IPV6):
6248 vlan_macip_lens |= skb_network_header_len(skb);
6249 l4_hdr = ipv6_hdr(skb)->nexthdr;
6250 break;
6251 default:
6252 if (unlikely(net_ratelimit())) {
6253 dev_warn(tx_ring->dev,
6254 "partial checksum but proto=%x!\n",
6255 skb->protocol);
6256 }
6257 break;
6258 }
6259
6260 switch (l4_hdr) {
6261 case IPPROTO_TCP:
6262 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6263 mss_l4len_idx = tcp_hdrlen(skb) <<
6264 IXGBE_ADVTXD_L4LEN_SHIFT;
6265 break;
6266 case IPPROTO_SCTP:
6267 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6268 mss_l4len_idx = sizeof(struct sctphdr) <<
6269 IXGBE_ADVTXD_L4LEN_SHIFT;
6270 break;
6271 case IPPROTO_UDP:
6272 mss_l4len_idx = sizeof(struct udphdr) <<
6273 IXGBE_ADVTXD_L4LEN_SHIFT;
6274 break;
6275 default:
6276 if (unlikely(net_ratelimit())) {
6277 dev_warn(tx_ring->dev,
6278 "partial checksum but l4 proto=%x!\n",
6279 skb->protocol);
6280 }
6281 break;
6282 }
6283 }
6284
6285 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6286 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6287
6288 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6289 type_tucmd, mss_l4len_idx);
6290
6291 return (skb->ip_summed == CHECKSUM_PARTIAL);
6292 }
6293
6294 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6295 {
6296 /* set type for advanced descriptor with frame checksum insertion */
6297 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6298 IXGBE_ADVTXD_DCMD_IFCS |
6299 IXGBE_ADVTXD_DCMD_DEXT);
6300
6301 /* set HW vlan bit if vlan is present */
6302 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6303 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6304
6305 /* set segmentation enable bits for TSO/FSO */
6306 #ifdef IXGBE_FCOE
6307 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6308 #else
6309 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6310 #endif
6311 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6312
6313 return cmd_type;
6314 }
6315
6316 static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6317 {
6318 __le32 olinfo_status =
6319 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6320
6321 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6322 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6323 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6324 /* enble IPv4 checksum for TSO */
6325 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6326 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6327 }
6328
6329 /* enable L4 checksum for TSO and TX checksum offload */
6330 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6331 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6332
6333 #ifdef IXGBE_FCOE
6334 /* use index 1 context for FCOE/FSO */
6335 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6336 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6337 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6338
6339 #endif
6340 /*
6341 * Check Context must be set if Tx switch is enabled, which it
6342 * always is for case where virtual functions are running
6343 */
6344 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6345 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6346
6347 return olinfo_status;
6348 }
6349
6350 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6351 IXGBE_TXD_CMD_RS)
6352
6353 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6354 struct sk_buff *skb,
6355 struct ixgbe_tx_buffer *first,
6356 u32 tx_flags,
6357 const u8 hdr_len)
6358 {
6359 struct device *dev = tx_ring->dev;
6360 struct ixgbe_tx_buffer *tx_buffer_info;
6361 union ixgbe_adv_tx_desc *tx_desc;
6362 dma_addr_t dma;
6363 __le32 cmd_type, olinfo_status;
6364 struct skb_frag_struct *frag;
6365 unsigned int f = 0;
6366 unsigned int data_len = skb->data_len;
6367 unsigned int size = skb_headlen(skb);
6368 u32 offset = 0;
6369 u32 paylen = skb->len - hdr_len;
6370 u16 i = tx_ring->next_to_use;
6371 u16 gso_segs;
6372
6373 #ifdef IXGBE_FCOE
6374 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6375 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6376 data_len -= sizeof(struct fcoe_crc_eof);
6377 } else {
6378 size -= sizeof(struct fcoe_crc_eof) - data_len;
6379 data_len = 0;
6380 }
6381 }
6382
6383 #endif
6384 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6385 if (dma_mapping_error(dev, dma))
6386 goto dma_error;
6387
6388 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6389 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
6390
6391 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6392
6393 for (;;) {
6394 while (size > IXGBE_MAX_DATA_PER_TXD) {
6395 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6396 tx_desc->read.cmd_type_len =
6397 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6398 tx_desc->read.olinfo_status = olinfo_status;
6399
6400 offset += IXGBE_MAX_DATA_PER_TXD;
6401 size -= IXGBE_MAX_DATA_PER_TXD;
6402
6403 tx_desc++;
6404 i++;
6405 if (i == tx_ring->count) {
6406 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6407 i = 0;
6408 }
6409 }
6410
6411 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6412 tx_buffer_info->length = offset + size;
6413 tx_buffer_info->tx_flags = tx_flags;
6414 tx_buffer_info->dma = dma;
6415
6416 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6417 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6418 tx_desc->read.olinfo_status = olinfo_status;
6419
6420 if (!data_len)
6421 break;
6422
6423 frag = &skb_shinfo(skb)->frags[f];
6424 #ifdef IXGBE_FCOE
6425 size = min_t(unsigned int, data_len, frag->size);
6426 #else
6427 size = frag->size;
6428 #endif
6429 data_len -= size;
6430 f++;
6431
6432 offset = 0;
6433 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
6434
6435 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
6436 if (dma_mapping_error(dev, dma))
6437 goto dma_error;
6438
6439 tx_desc++;
6440 i++;
6441 if (i == tx_ring->count) {
6442 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6443 i = 0;
6444 }
6445 }
6446
6447 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
6448
6449 i++;
6450 if (i == tx_ring->count)
6451 i = 0;
6452
6453 tx_ring->next_to_use = i;
6454
6455 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6456 gso_segs = skb_shinfo(skb)->gso_segs;
6457 #ifdef IXGBE_FCOE
6458 /* adjust for FCoE Sequence Offload */
6459 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6460 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6461 skb_shinfo(skb)->gso_size);
6462 #endif /* IXGBE_FCOE */
6463 else
6464 gso_segs = 1;
6465
6466 /* multiply data chunks by size of headers */
6467 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6468 tx_buffer_info->gso_segs = gso_segs;
6469 tx_buffer_info->skb = skb;
6470
6471 /* set the timestamp */
6472 first->time_stamp = jiffies;
6473
6474 /*
6475 * Force memory writes to complete before letting h/w
6476 * know there are new descriptors to fetch. (Only
6477 * applicable for weak-ordered memory model archs,
6478 * such as IA-64).
6479 */
6480 wmb();
6481
6482 /* set next_to_watch value indicating a packet is present */
6483 first->next_to_watch = tx_desc;
6484
6485 /* notify HW of packet */
6486 writel(i, tx_ring->tail);
6487
6488 return;
6489 dma_error:
6490 dev_err(dev, "TX DMA map failed\n");
6491
6492 /* clear dma mappings for failed tx_buffer_info map */
6493 for (;;) {
6494 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6495 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6496 if (tx_buffer_info == first)
6497 break;
6498 if (i == 0)
6499 i = tx_ring->count;
6500 i--;
6501 }
6502
6503 dev_kfree_skb_any(skb);
6504
6505 tx_ring->next_to_use = i;
6506 }
6507
6508 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6509 u32 tx_flags, __be16 protocol)
6510 {
6511 struct ixgbe_q_vector *q_vector = ring->q_vector;
6512 union ixgbe_atr_hash_dword input = { .dword = 0 };
6513 union ixgbe_atr_hash_dword common = { .dword = 0 };
6514 union {
6515 unsigned char *network;
6516 struct iphdr *ipv4;
6517 struct ipv6hdr *ipv6;
6518 } hdr;
6519 struct tcphdr *th;
6520 __be16 vlan_id;
6521
6522 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6523 if (!q_vector)
6524 return;
6525
6526 /* do nothing if sampling is disabled */
6527 if (!ring->atr_sample_rate)
6528 return;
6529
6530 ring->atr_count++;
6531
6532 /* snag network header to get L4 type and address */
6533 hdr.network = skb_network_header(skb);
6534
6535 /* Currently only IPv4/IPv6 with TCP is supported */
6536 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6537 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6538 (protocol != __constant_htons(ETH_P_IP) ||
6539 hdr.ipv4->protocol != IPPROTO_TCP))
6540 return;
6541
6542 th = tcp_hdr(skb);
6543
6544 /* skip this packet since it is invalid or the socket is closing */
6545 if (!th || th->fin)
6546 return;
6547
6548 /* sample on all syn packets or once every atr sample count */
6549 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6550 return;
6551
6552 /* reset sample count */
6553 ring->atr_count = 0;
6554
6555 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6556
6557 /*
6558 * src and dst are inverted, think how the receiver sees them
6559 *
6560 * The input is broken into two sections, a non-compressed section
6561 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6562 * is XORed together and stored in the compressed dword.
6563 */
6564 input.formatted.vlan_id = vlan_id;
6565
6566 /*
6567 * since src port and flex bytes occupy the same word XOR them together
6568 * and write the value to source port portion of compressed dword
6569 */
6570 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6571 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6572 else
6573 common.port.src ^= th->dest ^ protocol;
6574 common.port.dst ^= th->source;
6575
6576 if (protocol == __constant_htons(ETH_P_IP)) {
6577 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6578 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6579 } else {
6580 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6581 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6582 hdr.ipv6->saddr.s6_addr32[1] ^
6583 hdr.ipv6->saddr.s6_addr32[2] ^
6584 hdr.ipv6->saddr.s6_addr32[3] ^
6585 hdr.ipv6->daddr.s6_addr32[0] ^
6586 hdr.ipv6->daddr.s6_addr32[1] ^
6587 hdr.ipv6->daddr.s6_addr32[2] ^
6588 hdr.ipv6->daddr.s6_addr32[3];
6589 }
6590
6591 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6592 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6593 input, common, ring->queue_index);
6594 }
6595
6596 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6597 {
6598 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6599 /* Herbert's original patch had:
6600 * smp_mb__after_netif_stop_queue();
6601 * but since that doesn't exist yet, just open code it. */
6602 smp_mb();
6603
6604 /* We need to check again in a case another CPU has just
6605 * made room available. */
6606 if (likely(ixgbe_desc_unused(tx_ring) < size))
6607 return -EBUSY;
6608
6609 /* A reprieve! - use start_queue because it doesn't call schedule */
6610 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6611 ++tx_ring->tx_stats.restart_queue;
6612 return 0;
6613 }
6614
6615 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6616 {
6617 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6618 return 0;
6619 return __ixgbe_maybe_stop_tx(tx_ring, size);
6620 }
6621
6622 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6623 {
6624 struct ixgbe_adapter *adapter = netdev_priv(dev);
6625 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6626 smp_processor_id();
6627 #ifdef IXGBE_FCOE
6628 __be16 protocol = vlan_get_protocol(skb);
6629
6630 if (((protocol == htons(ETH_P_FCOE)) ||
6631 (protocol == htons(ETH_P_FIP))) &&
6632 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6633 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6634 txq += adapter->ring_feature[RING_F_FCOE].mask;
6635 return txq;
6636 }
6637 #endif
6638
6639 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6640 while (unlikely(txq >= dev->real_num_tx_queues))
6641 txq -= dev->real_num_tx_queues;
6642 return txq;
6643 }
6644
6645 return skb_tx_hash(dev, skb);
6646 }
6647
6648 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6649 struct ixgbe_adapter *adapter,
6650 struct ixgbe_ring *tx_ring)
6651 {
6652 struct ixgbe_tx_buffer *first;
6653 int tso;
6654 u32 tx_flags = 0;
6655 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6656 unsigned short f;
6657 #endif
6658 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6659 __be16 protocol = skb->protocol;
6660 u8 hdr_len = 0;
6661
6662 /*
6663 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6664 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6665 * + 2 desc gap to keep tail from touching head,
6666 * + 1 desc for context descriptor,
6667 * otherwise try next time
6668 */
6669 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6670 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6671 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6672 #else
6673 count += skb_shinfo(skb)->nr_frags;
6674 #endif
6675 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6676 tx_ring->tx_stats.tx_busy++;
6677 return NETDEV_TX_BUSY;
6678 }
6679
6680 #ifdef CONFIG_PCI_IOV
6681 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6682 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6683
6684 #endif
6685 /* if we have a HW VLAN tag being added default to the HW one */
6686 if (vlan_tx_tag_present(skb)) {
6687 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6688 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6689 /* else if it is a SW VLAN check the next protocol and store the tag */
6690 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6691 struct vlan_hdr *vhdr, _vhdr;
6692 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6693 if (!vhdr)
6694 goto out_drop;
6695
6696 protocol = vhdr->h_vlan_encapsulated_proto;
6697 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6698 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6699 }
6700
6701 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6702 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6703 (skb->priority != TC_PRIO_CONTROL))) {
6704 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6705 tx_flags |= tx_ring->dcb_tc <<
6706 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6707 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6708 struct vlan_ethhdr *vhdr;
6709 if (skb_header_cloned(skb) &&
6710 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6711 goto out_drop;
6712 vhdr = (struct vlan_ethhdr *)skb->data;
6713 vhdr->h_vlan_TCI = htons(tx_flags >>
6714 IXGBE_TX_FLAGS_VLAN_SHIFT);
6715 } else {
6716 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6717 }
6718 }
6719
6720 /* record the location of the first descriptor for this packet */
6721 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6722
6723 #ifdef IXGBE_FCOE
6724 /* setup tx offload for FCoE */
6725 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6726 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6727 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6728 if (tso < 0)
6729 goto out_drop;
6730 else if (tso)
6731 tx_flags |= IXGBE_TX_FLAGS_FSO |
6732 IXGBE_TX_FLAGS_FCOE;
6733 else
6734 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6735
6736 goto xmit_fcoe;
6737 }
6738
6739 #endif /* IXGBE_FCOE */
6740 /* setup IPv4/IPv6 offloads */
6741 if (protocol == __constant_htons(ETH_P_IP))
6742 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6743
6744 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6745 if (tso < 0)
6746 goto out_drop;
6747 else if (tso)
6748 tx_flags |= IXGBE_TX_FLAGS_TSO;
6749 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6750 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6751
6752 /* add the ATR filter if ATR is on */
6753 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6754 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6755
6756 #ifdef IXGBE_FCOE
6757 xmit_fcoe:
6758 #endif /* IXGBE_FCOE */
6759 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6760
6761 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6762
6763 return NETDEV_TX_OK;
6764
6765 out_drop:
6766 dev_kfree_skb_any(skb);
6767 return NETDEV_TX_OK;
6768 }
6769
6770 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6771 {
6772 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6773 struct ixgbe_ring *tx_ring;
6774
6775 tx_ring = adapter->tx_ring[skb->queue_mapping];
6776 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6777 }
6778
6779 /**
6780 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6781 * @netdev: network interface device structure
6782 * @p: pointer to an address structure
6783 *
6784 * Returns 0 on success, negative on failure
6785 **/
6786 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6787 {
6788 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6789 struct ixgbe_hw *hw = &adapter->hw;
6790 struct sockaddr *addr = p;
6791
6792 if (!is_valid_ether_addr(addr->sa_data))
6793 return -EADDRNOTAVAIL;
6794
6795 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6796 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6797
6798 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6799 IXGBE_RAH_AV);
6800
6801 return 0;
6802 }
6803
6804 static int
6805 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6806 {
6807 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6808 struct ixgbe_hw *hw = &adapter->hw;
6809 u16 value;
6810 int rc;
6811
6812 if (prtad != hw->phy.mdio.prtad)
6813 return -EINVAL;
6814 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6815 if (!rc)
6816 rc = value;
6817 return rc;
6818 }
6819
6820 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6821 u16 addr, u16 value)
6822 {
6823 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6824 struct ixgbe_hw *hw = &adapter->hw;
6825
6826 if (prtad != hw->phy.mdio.prtad)
6827 return -EINVAL;
6828 return hw->phy.ops.write_reg(hw, addr, devad, value);
6829 }
6830
6831 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6832 {
6833 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6834
6835 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6836 }
6837
6838 /**
6839 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6840 * netdev->dev_addrs
6841 * @netdev: network interface device structure
6842 *
6843 * Returns non-zero on failure
6844 **/
6845 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6846 {
6847 int err = 0;
6848 struct ixgbe_adapter *adapter = netdev_priv(dev);
6849 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6850
6851 if (is_valid_ether_addr(mac->san_addr)) {
6852 rtnl_lock();
6853 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6854 rtnl_unlock();
6855 }
6856 return err;
6857 }
6858
6859 /**
6860 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6861 * netdev->dev_addrs
6862 * @netdev: network interface device structure
6863 *
6864 * Returns non-zero on failure
6865 **/
6866 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6867 {
6868 int err = 0;
6869 struct ixgbe_adapter *adapter = netdev_priv(dev);
6870 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6871
6872 if (is_valid_ether_addr(mac->san_addr)) {
6873 rtnl_lock();
6874 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6875 rtnl_unlock();
6876 }
6877 return err;
6878 }
6879
6880 #ifdef CONFIG_NET_POLL_CONTROLLER
6881 /*
6882 * Polling 'interrupt' - used by things like netconsole to send skbs
6883 * without having to re-enable interrupts. It's not called while
6884 * the interrupt routine is executing.
6885 */
6886 static void ixgbe_netpoll(struct net_device *netdev)
6887 {
6888 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6889 int i;
6890
6891 /* if interface is down do nothing */
6892 if (test_bit(__IXGBE_DOWN, &adapter->state))
6893 return;
6894
6895 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6896 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6897 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6898 for (i = 0; i < num_q_vectors; i++) {
6899 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6900 ixgbe_msix_clean_rings(0, q_vector);
6901 }
6902 } else {
6903 ixgbe_intr(adapter->pdev->irq, netdev);
6904 }
6905 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6906 }
6907 #endif
6908
6909 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6910 struct rtnl_link_stats64 *stats)
6911 {
6912 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6913 int i;
6914
6915 rcu_read_lock();
6916 for (i = 0; i < adapter->num_rx_queues; i++) {
6917 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6918 u64 bytes, packets;
6919 unsigned int start;
6920
6921 if (ring) {
6922 do {
6923 start = u64_stats_fetch_begin_bh(&ring->syncp);
6924 packets = ring->stats.packets;
6925 bytes = ring->stats.bytes;
6926 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6927 stats->rx_packets += packets;
6928 stats->rx_bytes += bytes;
6929 }
6930 }
6931
6932 for (i = 0; i < adapter->num_tx_queues; i++) {
6933 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6934 u64 bytes, packets;
6935 unsigned int start;
6936
6937 if (ring) {
6938 do {
6939 start = u64_stats_fetch_begin_bh(&ring->syncp);
6940 packets = ring->stats.packets;
6941 bytes = ring->stats.bytes;
6942 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6943 stats->tx_packets += packets;
6944 stats->tx_bytes += bytes;
6945 }
6946 }
6947 rcu_read_unlock();
6948 /* following stats updated by ixgbe_watchdog_task() */
6949 stats->multicast = netdev->stats.multicast;
6950 stats->rx_errors = netdev->stats.rx_errors;
6951 stats->rx_length_errors = netdev->stats.rx_length_errors;
6952 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6953 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6954 return stats;
6955 }
6956
6957 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6958 * #adapter: pointer to ixgbe_adapter
6959 * @tc: number of traffic classes currently enabled
6960 *
6961 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6962 * 802.1Q priority maps to a packet buffer that exists.
6963 */
6964 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6965 {
6966 struct ixgbe_hw *hw = &adapter->hw;
6967 u32 reg, rsave;
6968 int i;
6969
6970 /* 82598 have a static priority to TC mapping that can not
6971 * be changed so no validation is needed.
6972 */
6973 if (hw->mac.type == ixgbe_mac_82598EB)
6974 return;
6975
6976 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6977 rsave = reg;
6978
6979 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6980 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6981
6982 /* If up2tc is out of bounds default to zero */
6983 if (up2tc > tc)
6984 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6985 }
6986
6987 if (reg != rsave)
6988 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6989
6990 return;
6991 }
6992
6993
6994 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
6995 * classes.
6996 *
6997 * @netdev: net device to configure
6998 * @tc: number of traffic classes to enable
6999 */
7000 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7001 {
7002 struct ixgbe_adapter *adapter = netdev_priv(dev);
7003 struct ixgbe_hw *hw = &adapter->hw;
7004
7005 /* Multiple traffic classes requires multiple queues */
7006 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7007 e_err(drv, "Enable failed, needs MSI-X\n");
7008 return -EINVAL;
7009 }
7010
7011 /* Hardware supports up to 8 traffic classes */
7012 if (tc > MAX_TRAFFIC_CLASS ||
7013 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7014 return -EINVAL;
7015
7016 /* Hardware has to reinitialize queues and interrupts to
7017 * match packet buffer alignment. Unfortunantly, the
7018 * hardware is not flexible enough to do this dynamically.
7019 */
7020 if (netif_running(dev))
7021 ixgbe_close(dev);
7022 ixgbe_clear_interrupt_scheme(adapter);
7023
7024 if (tc) {
7025 netdev_set_num_tc(dev, tc);
7026 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
7027
7028 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7029 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7030
7031 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7032 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7033 } else {
7034 netdev_reset_tc(dev);
7035
7036 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7037
7038 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7039 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7040
7041 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7042 adapter->dcb_cfg.pfc_mode_enable = false;
7043 }
7044
7045 ixgbe_init_interrupt_scheme(adapter);
7046 ixgbe_validate_rtr(adapter, tc);
7047 if (netif_running(dev))
7048 ixgbe_open(dev);
7049
7050 return 0;
7051 }
7052
7053 void ixgbe_do_reset(struct net_device *netdev)
7054 {
7055 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7056
7057 if (netif_running(netdev))
7058 ixgbe_reinit_locked(adapter);
7059 else
7060 ixgbe_reset(adapter);
7061 }
7062
7063 static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
7064 {
7065 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7066
7067 #ifdef CONFIG_DCB
7068 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7069 data &= ~NETIF_F_HW_VLAN_RX;
7070 #endif
7071
7072 /* return error if RXHASH is being enabled when RSS is not supported */
7073 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7074 data &= ~NETIF_F_RXHASH;
7075
7076 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7077 if (!(data & NETIF_F_RXCSUM))
7078 data &= ~NETIF_F_LRO;
7079
7080 /* Turn off LRO if not RSC capable or invalid ITR settings */
7081 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7082 data &= ~NETIF_F_LRO;
7083 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7084 (adapter->rx_itr_setting != 1 &&
7085 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7086 data &= ~NETIF_F_LRO;
7087 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7088 }
7089
7090 return data;
7091 }
7092
7093 static int ixgbe_set_features(struct net_device *netdev, u32 data)
7094 {
7095 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7096 bool need_reset = false;
7097
7098 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7099 if (!(data & NETIF_F_RXCSUM))
7100 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7101 else
7102 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7103
7104 /* Make sure RSC matches LRO, reset if change */
7105 if (!!(data & NETIF_F_LRO) !=
7106 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7107 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7108 switch (adapter->hw.mac.type) {
7109 case ixgbe_mac_X540:
7110 case ixgbe_mac_82599EB:
7111 need_reset = true;
7112 break;
7113 default:
7114 break;
7115 }
7116 }
7117
7118 /*
7119 * Check if Flow Director n-tuple support was enabled or disabled. If
7120 * the state changed, we need to reset.
7121 */
7122 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7123 /* turn off ATR, enable perfect filters and reset */
7124 if (data & NETIF_F_NTUPLE) {
7125 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7126 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7127 need_reset = true;
7128 }
7129 } else if (!(data & NETIF_F_NTUPLE)) {
7130 /* turn off Flow Director, set ATR and reset */
7131 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7132 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7133 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7134 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7135 need_reset = true;
7136 }
7137
7138 if (need_reset)
7139 ixgbe_do_reset(netdev);
7140
7141 return 0;
7142
7143 }
7144
7145 static const struct net_device_ops ixgbe_netdev_ops = {
7146 .ndo_open = ixgbe_open,
7147 .ndo_stop = ixgbe_close,
7148 .ndo_start_xmit = ixgbe_xmit_frame,
7149 .ndo_select_queue = ixgbe_select_queue,
7150 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7151 .ndo_validate_addr = eth_validate_addr,
7152 .ndo_set_mac_address = ixgbe_set_mac,
7153 .ndo_change_mtu = ixgbe_change_mtu,
7154 .ndo_tx_timeout = ixgbe_tx_timeout,
7155 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7156 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7157 .ndo_do_ioctl = ixgbe_ioctl,
7158 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7159 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7160 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7161 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7162 .ndo_get_stats64 = ixgbe_get_stats64,
7163 .ndo_setup_tc = ixgbe_setup_tc,
7164 #ifdef CONFIG_NET_POLL_CONTROLLER
7165 .ndo_poll_controller = ixgbe_netpoll,
7166 #endif
7167 #ifdef IXGBE_FCOE
7168 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7169 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7170 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7171 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7172 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7173 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7174 #endif /* IXGBE_FCOE */
7175 .ndo_set_features = ixgbe_set_features,
7176 .ndo_fix_features = ixgbe_fix_features,
7177 };
7178
7179 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7180 const struct ixgbe_info *ii)
7181 {
7182 #ifdef CONFIG_PCI_IOV
7183 struct ixgbe_hw *hw = &adapter->hw;
7184
7185 if (hw->mac.type == ixgbe_mac_82598EB)
7186 return;
7187
7188 /* The 82599 supports up to 64 VFs per physical function
7189 * but this implementation limits allocation to 63 so that
7190 * basic networking resources are still available to the
7191 * physical function
7192 */
7193 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7194 ixgbe_enable_sriov(adapter, ii);
7195 #endif /* CONFIG_PCI_IOV */
7196 }
7197
7198 /**
7199 * ixgbe_probe - Device Initialization Routine
7200 * @pdev: PCI device information struct
7201 * @ent: entry in ixgbe_pci_tbl
7202 *
7203 * Returns 0 on success, negative on failure
7204 *
7205 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7206 * The OS initialization, configuring of the adapter private structure,
7207 * and a hardware reset occur.
7208 **/
7209 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7210 const struct pci_device_id *ent)
7211 {
7212 struct net_device *netdev;
7213 struct ixgbe_adapter *adapter = NULL;
7214 struct ixgbe_hw *hw;
7215 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7216 static int cards_found;
7217 int i, err, pci_using_dac;
7218 u8 part_str[IXGBE_PBANUM_LENGTH];
7219 unsigned int indices = num_possible_cpus();
7220 #ifdef IXGBE_FCOE
7221 u16 device_caps;
7222 #endif
7223 u32 eec;
7224 u16 wol_cap;
7225
7226 /* Catch broken hardware that put the wrong VF device ID in
7227 * the PCIe SR-IOV capability.
7228 */
7229 if (pdev->is_virtfn) {
7230 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7231 pci_name(pdev), pdev->vendor, pdev->device);
7232 return -EINVAL;
7233 }
7234
7235 err = pci_enable_device_mem(pdev);
7236 if (err)
7237 return err;
7238
7239 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7240 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7241 pci_using_dac = 1;
7242 } else {
7243 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7244 if (err) {
7245 err = dma_set_coherent_mask(&pdev->dev,
7246 DMA_BIT_MASK(32));
7247 if (err) {
7248 dev_err(&pdev->dev,
7249 "No usable DMA configuration, aborting\n");
7250 goto err_dma;
7251 }
7252 }
7253 pci_using_dac = 0;
7254 }
7255
7256 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7257 IORESOURCE_MEM), ixgbe_driver_name);
7258 if (err) {
7259 dev_err(&pdev->dev,
7260 "pci_request_selected_regions failed 0x%x\n", err);
7261 goto err_pci_reg;
7262 }
7263
7264 pci_enable_pcie_error_reporting(pdev);
7265
7266 pci_set_master(pdev);
7267 pci_save_state(pdev);
7268
7269 #ifdef CONFIG_IXGBE_DCB
7270 indices *= MAX_TRAFFIC_CLASS;
7271 #endif
7272
7273 if (ii->mac == ixgbe_mac_82598EB)
7274 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7275 else
7276 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7277
7278 #ifdef IXGBE_FCOE
7279 indices += min_t(unsigned int, num_possible_cpus(),
7280 IXGBE_MAX_FCOE_INDICES);
7281 #endif
7282 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7283 if (!netdev) {
7284 err = -ENOMEM;
7285 goto err_alloc_etherdev;
7286 }
7287
7288 SET_NETDEV_DEV(netdev, &pdev->dev);
7289
7290 adapter = netdev_priv(netdev);
7291 pci_set_drvdata(pdev, adapter);
7292
7293 adapter->netdev = netdev;
7294 adapter->pdev = pdev;
7295 hw = &adapter->hw;
7296 hw->back = adapter;
7297 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7298
7299 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7300 pci_resource_len(pdev, 0));
7301 if (!hw->hw_addr) {
7302 err = -EIO;
7303 goto err_ioremap;
7304 }
7305
7306 for (i = 1; i <= 5; i++) {
7307 if (pci_resource_len(pdev, i) == 0)
7308 continue;
7309 }
7310
7311 netdev->netdev_ops = &ixgbe_netdev_ops;
7312 ixgbe_set_ethtool_ops(netdev);
7313 netdev->watchdog_timeo = 5 * HZ;
7314 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7315
7316 adapter->bd_number = cards_found;
7317
7318 /* Setup hw api */
7319 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7320 hw->mac.type = ii->mac;
7321
7322 /* EEPROM */
7323 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7324 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7325 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7326 if (!(eec & (1 << 8)))
7327 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7328
7329 /* PHY */
7330 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7331 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7332 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7333 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7334 hw->phy.mdio.mmds = 0;
7335 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7336 hw->phy.mdio.dev = netdev;
7337 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7338 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7339
7340 ii->get_invariants(hw);
7341
7342 /* setup the private structure */
7343 err = ixgbe_sw_init(adapter);
7344 if (err)
7345 goto err_sw_init;
7346
7347 /* Make it possible the adapter to be woken up via WOL */
7348 switch (adapter->hw.mac.type) {
7349 case ixgbe_mac_82599EB:
7350 case ixgbe_mac_X540:
7351 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7352 break;
7353 default:
7354 break;
7355 }
7356
7357 /*
7358 * If there is a fan on this device and it has failed log the
7359 * failure.
7360 */
7361 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7362 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7363 if (esdp & IXGBE_ESDP_SDP1)
7364 e_crit(probe, "Fan has stopped, replace the adapter\n");
7365 }
7366
7367 /* reset_hw fills in the perm_addr as well */
7368 hw->phy.reset_if_overtemp = true;
7369 err = hw->mac.ops.reset_hw(hw);
7370 hw->phy.reset_if_overtemp = false;
7371 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7372 hw->mac.type == ixgbe_mac_82598EB) {
7373 err = 0;
7374 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7375 e_dev_err("failed to load because an unsupported SFP+ "
7376 "module type was detected.\n");
7377 e_dev_err("Reload the driver after installing a supported "
7378 "module.\n");
7379 goto err_sw_init;
7380 } else if (err) {
7381 e_dev_err("HW Init failed: %d\n", err);
7382 goto err_sw_init;
7383 }
7384
7385 ixgbe_probe_vf(adapter, ii);
7386
7387 netdev->features = NETIF_F_SG |
7388 NETIF_F_IP_CSUM |
7389 NETIF_F_IPV6_CSUM |
7390 NETIF_F_HW_VLAN_TX |
7391 NETIF_F_HW_VLAN_RX |
7392 NETIF_F_HW_VLAN_FILTER |
7393 NETIF_F_TSO |
7394 NETIF_F_TSO6 |
7395 NETIF_F_RXHASH |
7396 NETIF_F_RXCSUM;
7397
7398 netdev->hw_features = netdev->features;
7399
7400 switch (adapter->hw.mac.type) {
7401 case ixgbe_mac_82599EB:
7402 case ixgbe_mac_X540:
7403 netdev->features |= NETIF_F_SCTP_CSUM;
7404 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7405 NETIF_F_NTUPLE;
7406 break;
7407 default:
7408 break;
7409 }
7410
7411 netdev->vlan_features |= NETIF_F_TSO;
7412 netdev->vlan_features |= NETIF_F_TSO6;
7413 netdev->vlan_features |= NETIF_F_IP_CSUM;
7414 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7415 netdev->vlan_features |= NETIF_F_SG;
7416
7417 netdev->priv_flags |= IFF_UNICAST_FLT;
7418
7419 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7420 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7421 IXGBE_FLAG_DCB_ENABLED);
7422
7423 #ifdef CONFIG_IXGBE_DCB
7424 netdev->dcbnl_ops = &dcbnl_ops;
7425 #endif
7426
7427 #ifdef IXGBE_FCOE
7428 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7429 if (hw->mac.ops.get_device_caps) {
7430 hw->mac.ops.get_device_caps(hw, &device_caps);
7431 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7432 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7433 }
7434 }
7435 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7436 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7437 netdev->vlan_features |= NETIF_F_FSO;
7438 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7439 }
7440 #endif /* IXGBE_FCOE */
7441 if (pci_using_dac) {
7442 netdev->features |= NETIF_F_HIGHDMA;
7443 netdev->vlan_features |= NETIF_F_HIGHDMA;
7444 }
7445
7446 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7447 netdev->hw_features |= NETIF_F_LRO;
7448 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7449 netdev->features |= NETIF_F_LRO;
7450
7451 /* make sure the EEPROM is good */
7452 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7453 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7454 err = -EIO;
7455 goto err_eeprom;
7456 }
7457
7458 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7459 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7460
7461 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7462 e_dev_err("invalid MAC address\n");
7463 err = -EIO;
7464 goto err_eeprom;
7465 }
7466
7467 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7468 if (hw->mac.ops.disable_tx_laser &&
7469 ((hw->phy.multispeed_fiber) ||
7470 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7471 (hw->mac.type == ixgbe_mac_82599EB))))
7472 hw->mac.ops.disable_tx_laser(hw);
7473
7474 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7475 (unsigned long) adapter);
7476
7477 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7478 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7479
7480 err = ixgbe_init_interrupt_scheme(adapter);
7481 if (err)
7482 goto err_sw_init;
7483
7484 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7485 netdev->hw_features &= ~NETIF_F_RXHASH;
7486 netdev->features &= ~NETIF_F_RXHASH;
7487 }
7488
7489 /* WOL not supported for all but the following */
7490 adapter->wol = 0;
7491 switch (pdev->device) {
7492 case IXGBE_DEV_ID_82599_SFP:
7493 /* Only this subdevice supports WOL */
7494 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7495 adapter->wol = IXGBE_WUFC_MAG;
7496 break;
7497 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7498 /* All except this subdevice support WOL */
7499 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7500 adapter->wol = IXGBE_WUFC_MAG;
7501 break;
7502 case IXGBE_DEV_ID_82599_KX4:
7503 adapter->wol = IXGBE_WUFC_MAG;
7504 break;
7505 case IXGBE_DEV_ID_X540T:
7506 /* Check eeprom to see if it is enabled */
7507 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7508 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7509
7510 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7511 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7512 (hw->bus.func == 0)))
7513 adapter->wol = IXGBE_WUFC_MAG;
7514 break;
7515 }
7516 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7517
7518 /* pick up the PCI bus settings for reporting later */
7519 hw->mac.ops.get_bus_info(hw);
7520
7521 /* print bus type/speed/width info */
7522 e_dev_info("(PCI Express:%s:%s) %pM\n",
7523 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7524 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7525 "Unknown"),
7526 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7527 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7528 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7529 "Unknown"),
7530 netdev->dev_addr);
7531
7532 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7533 if (err)
7534 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7535 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7536 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7537 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7538 part_str);
7539 else
7540 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7541 hw->mac.type, hw->phy.type, part_str);
7542
7543 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7544 e_dev_warn("PCI-Express bandwidth available for this card is "
7545 "not sufficient for optimal performance.\n");
7546 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7547 "is required.\n");
7548 }
7549
7550 /* save off EEPROM version number */
7551 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7552
7553 /* reset the hardware with the new settings */
7554 err = hw->mac.ops.start_hw(hw);
7555
7556 if (err == IXGBE_ERR_EEPROM_VERSION) {
7557 /* We are running on a pre-production device, log a warning */
7558 e_dev_warn("This device is a pre-production adapter/LOM. "
7559 "Please be aware there may be issues associated "
7560 "with your hardware. If you are experiencing "
7561 "problems please contact your Intel or hardware "
7562 "representative who provided you with this "
7563 "hardware.\n");
7564 }
7565 strcpy(netdev->name, "eth%d");
7566 err = register_netdev(netdev);
7567 if (err)
7568 goto err_register;
7569
7570 /* carrier off reporting is important to ethtool even BEFORE open */
7571 netif_carrier_off(netdev);
7572
7573 #ifdef CONFIG_IXGBE_DCA
7574 if (dca_add_requester(&pdev->dev) == 0) {
7575 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7576 ixgbe_setup_dca(adapter);
7577 }
7578 #endif
7579 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7580 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7581 for (i = 0; i < adapter->num_vfs; i++)
7582 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7583 }
7584
7585 /* Inform firmware of driver version */
7586 if (hw->mac.ops.set_fw_drv_ver)
7587 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7588 FW_CEM_UNUSED_VER);
7589
7590 /* add san mac addr to netdev */
7591 ixgbe_add_sanmac_netdev(netdev);
7592
7593 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7594 cards_found++;
7595 return 0;
7596
7597 err_register:
7598 ixgbe_release_hw_control(adapter);
7599 ixgbe_clear_interrupt_scheme(adapter);
7600 err_sw_init:
7601 err_eeprom:
7602 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7603 ixgbe_disable_sriov(adapter);
7604 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7605 iounmap(hw->hw_addr);
7606 err_ioremap:
7607 free_netdev(netdev);
7608 err_alloc_etherdev:
7609 pci_release_selected_regions(pdev,
7610 pci_select_bars(pdev, IORESOURCE_MEM));
7611 err_pci_reg:
7612 err_dma:
7613 pci_disable_device(pdev);
7614 return err;
7615 }
7616
7617 /**
7618 * ixgbe_remove - Device Removal Routine
7619 * @pdev: PCI device information struct
7620 *
7621 * ixgbe_remove is called by the PCI subsystem to alert the driver
7622 * that it should release a PCI device. The could be caused by a
7623 * Hot-Plug event, or because the driver is going to be removed from
7624 * memory.
7625 **/
7626 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7627 {
7628 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7629 struct net_device *netdev = adapter->netdev;
7630
7631 set_bit(__IXGBE_DOWN, &adapter->state);
7632 cancel_work_sync(&adapter->service_task);
7633
7634 #ifdef CONFIG_IXGBE_DCA
7635 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7636 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7637 dca_remove_requester(&pdev->dev);
7638 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7639 }
7640
7641 #endif
7642 #ifdef IXGBE_FCOE
7643 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7644 ixgbe_cleanup_fcoe(adapter);
7645
7646 #endif /* IXGBE_FCOE */
7647
7648 /* remove the added san mac */
7649 ixgbe_del_sanmac_netdev(netdev);
7650
7651 if (netdev->reg_state == NETREG_REGISTERED)
7652 unregister_netdev(netdev);
7653
7654 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7655 if (!(ixgbe_check_vf_assignment(adapter)))
7656 ixgbe_disable_sriov(adapter);
7657 else
7658 e_dev_warn("Unloading driver while VFs are assigned "
7659 "- VFs will not be deallocated\n");
7660 }
7661
7662 ixgbe_clear_interrupt_scheme(adapter);
7663
7664 ixgbe_release_hw_control(adapter);
7665
7666 iounmap(adapter->hw.hw_addr);
7667 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7668 IORESOURCE_MEM));
7669
7670 e_dev_info("complete\n");
7671
7672 free_netdev(netdev);
7673
7674 pci_disable_pcie_error_reporting(pdev);
7675
7676 pci_disable_device(pdev);
7677 }
7678
7679 /**
7680 * ixgbe_io_error_detected - called when PCI error is detected
7681 * @pdev: Pointer to PCI device
7682 * @state: The current pci connection state
7683 *
7684 * This function is called after a PCI bus error affecting
7685 * this device has been detected.
7686 */
7687 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7688 pci_channel_state_t state)
7689 {
7690 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7691 struct net_device *netdev = adapter->netdev;
7692
7693 netif_device_detach(netdev);
7694
7695 if (state == pci_channel_io_perm_failure)
7696 return PCI_ERS_RESULT_DISCONNECT;
7697
7698 if (netif_running(netdev))
7699 ixgbe_down(adapter);
7700 pci_disable_device(pdev);
7701
7702 /* Request a slot reset. */
7703 return PCI_ERS_RESULT_NEED_RESET;
7704 }
7705
7706 /**
7707 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7708 * @pdev: Pointer to PCI device
7709 *
7710 * Restart the card from scratch, as if from a cold-boot.
7711 */
7712 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7713 {
7714 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7715 pci_ers_result_t result;
7716 int err;
7717
7718 if (pci_enable_device_mem(pdev)) {
7719 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7720 result = PCI_ERS_RESULT_DISCONNECT;
7721 } else {
7722 pci_set_master(pdev);
7723 pci_restore_state(pdev);
7724 pci_save_state(pdev);
7725
7726 pci_wake_from_d3(pdev, false);
7727
7728 ixgbe_reset(adapter);
7729 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7730 result = PCI_ERS_RESULT_RECOVERED;
7731 }
7732
7733 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7734 if (err) {
7735 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7736 "failed 0x%0x\n", err);
7737 /* non-fatal, continue */
7738 }
7739
7740 return result;
7741 }
7742
7743 /**
7744 * ixgbe_io_resume - called when traffic can start flowing again.
7745 * @pdev: Pointer to PCI device
7746 *
7747 * This callback is called when the error recovery driver tells us that
7748 * its OK to resume normal operation.
7749 */
7750 static void ixgbe_io_resume(struct pci_dev *pdev)
7751 {
7752 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7753 struct net_device *netdev = adapter->netdev;
7754
7755 if (netif_running(netdev))
7756 ixgbe_up(adapter);
7757
7758 netif_device_attach(netdev);
7759 }
7760
7761 static struct pci_error_handlers ixgbe_err_handler = {
7762 .error_detected = ixgbe_io_error_detected,
7763 .slot_reset = ixgbe_io_slot_reset,
7764 .resume = ixgbe_io_resume,
7765 };
7766
7767 static struct pci_driver ixgbe_driver = {
7768 .name = ixgbe_driver_name,
7769 .id_table = ixgbe_pci_tbl,
7770 .probe = ixgbe_probe,
7771 .remove = __devexit_p(ixgbe_remove),
7772 #ifdef CONFIG_PM
7773 .suspend = ixgbe_suspend,
7774 .resume = ixgbe_resume,
7775 #endif
7776 .shutdown = ixgbe_shutdown,
7777 .err_handler = &ixgbe_err_handler
7778 };
7779
7780 /**
7781 * ixgbe_init_module - Driver Registration Routine
7782 *
7783 * ixgbe_init_module is the first routine called when the driver is
7784 * loaded. All it does is register with the PCI subsystem.
7785 **/
7786 static int __init ixgbe_init_module(void)
7787 {
7788 int ret;
7789 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7790 pr_info("%s\n", ixgbe_copyright);
7791
7792 #ifdef CONFIG_IXGBE_DCA
7793 dca_register_notify(&dca_notifier);
7794 #endif
7795
7796 ret = pci_register_driver(&ixgbe_driver);
7797 return ret;
7798 }
7799
7800 module_init(ixgbe_init_module);
7801
7802 /**
7803 * ixgbe_exit_module - Driver Exit Cleanup Routine
7804 *
7805 * ixgbe_exit_module is called just before the driver is removed
7806 * from memory.
7807 **/
7808 static void __exit ixgbe_exit_module(void)
7809 {
7810 #ifdef CONFIG_IXGBE_DCA
7811 dca_unregister_notify(&dca_notifier);
7812 #endif
7813 pci_unregister_driver(&ixgbe_driver);
7814 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7815 }
7816
7817 #ifdef CONFIG_IXGBE_DCA
7818 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7819 void *p)
7820 {
7821 int ret_val;
7822
7823 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7824 __ixgbe_notify_dca);
7825
7826 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7827 }
7828
7829 #endif /* CONFIG_IXGBE_DCA */
7830
7831 module_exit(ixgbe_exit_module);
7832
7833 /* ixgbe_main.c */
Linux kernel - Deliverables
This page took 0.265808 seconds and 4 git commands to generate.