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ixgbe: flush when in xmit_more mode and under descriptor pressure
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2014 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/types.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/vmalloc.h>
34 #include <linux/string.h>
35 #include <linux/in.h>
36 #include <linux/interrupt.h>
37 #include <linux/ip.h>
38 #include <linux/tcp.h>
39 #include <linux/sctp.h>
40 #include <linux/pkt_sched.h>
41 #include <linux/ipv6.h>
42 #include <linux/slab.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/ethtool.h>
46 #include <linux/if.h>
47 #include <linux/if_vlan.h>
48 #include <linux/if_macvlan.h>
49 #include <linux/if_bridge.h>
50 #include <linux/prefetch.h>
51 #include <scsi/fc/fc_fcoe.h>
52
53 #include "ixgbe.h"
54 #include "ixgbe_common.h"
55 #include "ixgbe_dcb_82599.h"
56 #include "ixgbe_sriov.h"
57
58 char ixgbe_driver_name[] = "ixgbe";
59 static const char ixgbe_driver_string[] =
60 "Intel(R) 10 Gigabit PCI Express Network Driver";
61 #ifdef IXGBE_FCOE
62 char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
64 #else
65 static char ixgbe_default_device_descr[] =
66 "Intel(R) 10 Gigabit Network Connection";
67 #endif
68 #define DRV_VERSION "3.19.1-k"
69 const char ixgbe_driver_version[] = DRV_VERSION;
70 static const char ixgbe_copyright[] =
71 "Copyright (c) 1999-2014 Intel Corporation.";
72
73 static const struct ixgbe_info *ixgbe_info_tbl[] = {
74 [board_82598] = &ixgbe_82598_info,
75 [board_82599] = &ixgbe_82599_info,
76 [board_X540] = &ixgbe_X540_info,
77 };
78
79 /* ixgbe_pci_tbl - PCI Device ID Table
80 *
81 * Wildcard entries (PCI_ANY_ID) should come last
82 * Last entry must be all 0s
83 *
84 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
85 * Class, Class Mask, private data (not used) }
86 */
87 static const struct pci_device_id ixgbe_pci_tbl[] = {
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
118 /* required last entry */
119 {0, }
120 };
121 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
122
123 #ifdef CONFIG_IXGBE_DCA
124 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
125 void *p);
126 static struct notifier_block dca_notifier = {
127 .notifier_call = ixgbe_notify_dca,
128 .next = NULL,
129 .priority = 0
130 };
131 #endif
132
133 #ifdef CONFIG_PCI_IOV
134 static unsigned int max_vfs;
135 module_param(max_vfs, uint, 0);
136 MODULE_PARM_DESC(max_vfs,
137 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
138 #endif /* CONFIG_PCI_IOV */
139
140 static unsigned int allow_unsupported_sfp;
141 module_param(allow_unsupported_sfp, uint, 0);
142 MODULE_PARM_DESC(allow_unsupported_sfp,
143 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
144
145 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
146 static int debug = -1;
147 module_param(debug, int, 0);
148 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
149
150 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
151 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
152 MODULE_LICENSE("GPL");
153 MODULE_VERSION(DRV_VERSION);
154
155 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
156
157 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
158 u32 reg, u16 *value)
159 {
160 struct pci_dev *parent_dev;
161 struct pci_bus *parent_bus;
162
163 parent_bus = adapter->pdev->bus->parent;
164 if (!parent_bus)
165 return -1;
166
167 parent_dev = parent_bus->self;
168 if (!parent_dev)
169 return -1;
170
171 if (!pci_is_pcie(parent_dev))
172 return -1;
173
174 pcie_capability_read_word(parent_dev, reg, value);
175 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
176 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
177 return -1;
178 return 0;
179 }
180
181 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
182 {
183 struct ixgbe_hw *hw = &adapter->hw;
184 u16 link_status = 0;
185 int err;
186
187 hw->bus.type = ixgbe_bus_type_pci_express;
188
189 /* Get the negotiated link width and speed from PCI config space of the
190 * parent, as this device is behind a switch
191 */
192 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
193
194 /* assume caller will handle error case */
195 if (err)
196 return err;
197
198 hw->bus.width = ixgbe_convert_bus_width(link_status);
199 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
200
201 return 0;
202 }
203
204 /**
205 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
206 * @hw: hw specific details
207 *
208 * This function is used by probe to determine whether a device's PCI-Express
209 * bandwidth details should be gathered from the parent bus instead of from the
210 * device. Used to ensure that various locations all have the correct device ID
211 * checks.
212 */
213 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
214 {
215 switch (hw->device_id) {
216 case IXGBE_DEV_ID_82599_SFP_SF_QP:
217 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
218 return true;
219 default:
220 return false;
221 }
222 }
223
224 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
225 int expected_gts)
226 {
227 int max_gts = 0;
228 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
229 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
230 struct pci_dev *pdev;
231
232 /* determine whether to use the the parent device
233 */
234 if (ixgbe_pcie_from_parent(&adapter->hw))
235 pdev = adapter->pdev->bus->parent->self;
236 else
237 pdev = adapter->pdev;
238
239 if (pcie_get_minimum_link(pdev, &speed, &width) ||
240 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
241 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
242 return;
243 }
244
245 switch (speed) {
246 case PCIE_SPEED_2_5GT:
247 /* 8b/10b encoding reduces max throughput by 20% */
248 max_gts = 2 * width;
249 break;
250 case PCIE_SPEED_5_0GT:
251 /* 8b/10b encoding reduces max throughput by 20% */
252 max_gts = 4 * width;
253 break;
254 case PCIE_SPEED_8_0GT:
255 /* 128b/130b encoding reduces throughput by less than 2% */
256 max_gts = 8 * width;
257 break;
258 default:
259 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
260 return;
261 }
262
263 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
264 max_gts);
265 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
266 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
267 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
268 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
269 "Unknown"),
270 width,
271 (speed == PCIE_SPEED_2_5GT ? "20%" :
272 speed == PCIE_SPEED_5_0GT ? "20%" :
273 speed == PCIE_SPEED_8_0GT ? "<2%" :
274 "Unknown"));
275
276 if (max_gts < expected_gts) {
277 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
278 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
279 expected_gts);
280 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
281 }
282 }
283
284 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
285 {
286 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
287 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
288 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
289 schedule_work(&adapter->service_task);
290 }
291
292 static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
293 {
294 struct ixgbe_adapter *adapter = hw->back;
295
296 if (!hw->hw_addr)
297 return;
298 hw->hw_addr = NULL;
299 e_dev_err("Adapter removed\n");
300 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
301 ixgbe_service_event_schedule(adapter);
302 }
303
304 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
305 {
306 u32 value;
307
308 /* The following check not only optimizes a bit by not
309 * performing a read on the status register when the
310 * register just read was a status register read that
311 * returned IXGBE_FAILED_READ_REG. It also blocks any
312 * potential recursion.
313 */
314 if (reg == IXGBE_STATUS) {
315 ixgbe_remove_adapter(hw);
316 return;
317 }
318 value = ixgbe_read_reg(hw, IXGBE_STATUS);
319 if (value == IXGBE_FAILED_READ_REG)
320 ixgbe_remove_adapter(hw);
321 }
322
323 /**
324 * ixgbe_read_reg - Read from device register
325 * @hw: hw specific details
326 * @reg: offset of register to read
327 *
328 * Returns : value read or IXGBE_FAILED_READ_REG if removed
329 *
330 * This function is used to read device registers. It checks for device
331 * removal by confirming any read that returns all ones by checking the
332 * status register value for all ones. This function avoids reading from
333 * the hardware if a removal was previously detected in which case it
334 * returns IXGBE_FAILED_READ_REG (all ones).
335 */
336 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
337 {
338 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
339 u32 value;
340
341 if (ixgbe_removed(reg_addr))
342 return IXGBE_FAILED_READ_REG;
343 value = readl(reg_addr + reg);
344 if (unlikely(value == IXGBE_FAILED_READ_REG))
345 ixgbe_check_remove(hw, reg);
346 return value;
347 }
348
349 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
350 {
351 u16 value;
352
353 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
354 if (value == IXGBE_FAILED_READ_CFG_WORD) {
355 ixgbe_remove_adapter(hw);
356 return true;
357 }
358 return false;
359 }
360
361 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
362 {
363 struct ixgbe_adapter *adapter = hw->back;
364 u16 value;
365
366 if (ixgbe_removed(hw->hw_addr))
367 return IXGBE_FAILED_READ_CFG_WORD;
368 pci_read_config_word(adapter->pdev, reg, &value);
369 if (value == IXGBE_FAILED_READ_CFG_WORD &&
370 ixgbe_check_cfg_remove(hw, adapter->pdev))
371 return IXGBE_FAILED_READ_CFG_WORD;
372 return value;
373 }
374
375 #ifdef CONFIG_PCI_IOV
376 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
377 {
378 struct ixgbe_adapter *adapter = hw->back;
379 u32 value;
380
381 if (ixgbe_removed(hw->hw_addr))
382 return IXGBE_FAILED_READ_CFG_DWORD;
383 pci_read_config_dword(adapter->pdev, reg, &value);
384 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
385 ixgbe_check_cfg_remove(hw, adapter->pdev))
386 return IXGBE_FAILED_READ_CFG_DWORD;
387 return value;
388 }
389 #endif /* CONFIG_PCI_IOV */
390
391 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
392 {
393 struct ixgbe_adapter *adapter = hw->back;
394
395 if (ixgbe_removed(hw->hw_addr))
396 return;
397 pci_write_config_word(adapter->pdev, reg, value);
398 }
399
400 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
401 {
402 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
403
404 /* flush memory to make sure state is correct before next watchdog */
405 smp_mb__before_atomic();
406 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
407 }
408
409 struct ixgbe_reg_info {
410 u32 ofs;
411 char *name;
412 };
413
414 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
415
416 /* General Registers */
417 {IXGBE_CTRL, "CTRL"},
418 {IXGBE_STATUS, "STATUS"},
419 {IXGBE_CTRL_EXT, "CTRL_EXT"},
420
421 /* Interrupt Registers */
422 {IXGBE_EICR, "EICR"},
423
424 /* RX Registers */
425 {IXGBE_SRRCTL(0), "SRRCTL"},
426 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
427 {IXGBE_RDLEN(0), "RDLEN"},
428 {IXGBE_RDH(0), "RDH"},
429 {IXGBE_RDT(0), "RDT"},
430 {IXGBE_RXDCTL(0), "RXDCTL"},
431 {IXGBE_RDBAL(0), "RDBAL"},
432 {IXGBE_RDBAH(0), "RDBAH"},
433
434 /* TX Registers */
435 {IXGBE_TDBAL(0), "TDBAL"},
436 {IXGBE_TDBAH(0), "TDBAH"},
437 {IXGBE_TDLEN(0), "TDLEN"},
438 {IXGBE_TDH(0), "TDH"},
439 {IXGBE_TDT(0), "TDT"},
440 {IXGBE_TXDCTL(0), "TXDCTL"},
441
442 /* List Terminator */
443 {}
444 };
445
446
447 /*
448 * ixgbe_regdump - register printout routine
449 */
450 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
451 {
452 int i = 0, j = 0;
453 char rname[16];
454 u32 regs[64];
455
456 switch (reginfo->ofs) {
457 case IXGBE_SRRCTL(0):
458 for (i = 0; i < 64; i++)
459 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
460 break;
461 case IXGBE_DCA_RXCTRL(0):
462 for (i = 0; i < 64; i++)
463 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
464 break;
465 case IXGBE_RDLEN(0):
466 for (i = 0; i < 64; i++)
467 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
468 break;
469 case IXGBE_RDH(0):
470 for (i = 0; i < 64; i++)
471 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
472 break;
473 case IXGBE_RDT(0):
474 for (i = 0; i < 64; i++)
475 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
476 break;
477 case IXGBE_RXDCTL(0):
478 for (i = 0; i < 64; i++)
479 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
480 break;
481 case IXGBE_RDBAL(0):
482 for (i = 0; i < 64; i++)
483 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
484 break;
485 case IXGBE_RDBAH(0):
486 for (i = 0; i < 64; i++)
487 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
488 break;
489 case IXGBE_TDBAL(0):
490 for (i = 0; i < 64; i++)
491 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
492 break;
493 case IXGBE_TDBAH(0):
494 for (i = 0; i < 64; i++)
495 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
496 break;
497 case IXGBE_TDLEN(0):
498 for (i = 0; i < 64; i++)
499 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
500 break;
501 case IXGBE_TDH(0):
502 for (i = 0; i < 64; i++)
503 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
504 break;
505 case IXGBE_TDT(0):
506 for (i = 0; i < 64; i++)
507 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
508 break;
509 case IXGBE_TXDCTL(0):
510 for (i = 0; i < 64; i++)
511 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
512 break;
513 default:
514 pr_info("%-15s %08x\n", reginfo->name,
515 IXGBE_READ_REG(hw, reginfo->ofs));
516 return;
517 }
518
519 for (i = 0; i < 8; i++) {
520 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
521 pr_err("%-15s", rname);
522 for (j = 0; j < 8; j++)
523 pr_cont(" %08x", regs[i*8+j]);
524 pr_cont("\n");
525 }
526
527 }
528
529 /*
530 * ixgbe_dump - Print registers, tx-rings and rx-rings
531 */
532 static void ixgbe_dump(struct ixgbe_adapter *adapter)
533 {
534 struct net_device *netdev = adapter->netdev;
535 struct ixgbe_hw *hw = &adapter->hw;
536 struct ixgbe_reg_info *reginfo;
537 int n = 0;
538 struct ixgbe_ring *tx_ring;
539 struct ixgbe_tx_buffer *tx_buffer;
540 union ixgbe_adv_tx_desc *tx_desc;
541 struct my_u0 { u64 a; u64 b; } *u0;
542 struct ixgbe_ring *rx_ring;
543 union ixgbe_adv_rx_desc *rx_desc;
544 struct ixgbe_rx_buffer *rx_buffer_info;
545 u32 staterr;
546 int i = 0;
547
548 if (!netif_msg_hw(adapter))
549 return;
550
551 /* Print netdevice Info */
552 if (netdev) {
553 dev_info(&adapter->pdev->dev, "Net device Info\n");
554 pr_info("Device Name state "
555 "trans_start last_rx\n");
556 pr_info("%-15s %016lX %016lX %016lX\n",
557 netdev->name,
558 netdev->state,
559 netdev->trans_start,
560 netdev->last_rx);
561 }
562
563 /* Print Registers */
564 dev_info(&adapter->pdev->dev, "Register Dump\n");
565 pr_info(" Register Name Value\n");
566 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
567 reginfo->name; reginfo++) {
568 ixgbe_regdump(hw, reginfo);
569 }
570
571 /* Print TX Ring Summary */
572 if (!netdev || !netif_running(netdev))
573 return;
574
575 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
576 pr_info(" %s %s %s %s\n",
577 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
578 "leng", "ntw", "timestamp");
579 for (n = 0; n < adapter->num_tx_queues; n++) {
580 tx_ring = adapter->tx_ring[n];
581 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
582 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
583 n, tx_ring->next_to_use, tx_ring->next_to_clean,
584 (u64)dma_unmap_addr(tx_buffer, dma),
585 dma_unmap_len(tx_buffer, len),
586 tx_buffer->next_to_watch,
587 (u64)tx_buffer->time_stamp);
588 }
589
590 /* Print TX Rings */
591 if (!netif_msg_tx_done(adapter))
592 goto rx_ring_summary;
593
594 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
595
596 /* Transmit Descriptor Formats
597 *
598 * 82598 Advanced Transmit Descriptor
599 * +--------------------------------------------------------------+
600 * 0 | Buffer Address [63:0] |
601 * +--------------------------------------------------------------+
602 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
603 * +--------------------------------------------------------------+
604 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
605 *
606 * 82598 Advanced Transmit Descriptor (Write-Back Format)
607 * +--------------------------------------------------------------+
608 * 0 | RSV [63:0] |
609 * +--------------------------------------------------------------+
610 * 8 | RSV | STA | NXTSEQ |
611 * +--------------------------------------------------------------+
612 * 63 36 35 32 31 0
613 *
614 * 82599+ Advanced Transmit Descriptor
615 * +--------------------------------------------------------------+
616 * 0 | Buffer Address [63:0] |
617 * +--------------------------------------------------------------+
618 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
619 * +--------------------------------------------------------------+
620 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
621 *
622 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
623 * +--------------------------------------------------------------+
624 * 0 | RSV [63:0] |
625 * +--------------------------------------------------------------+
626 * 8 | RSV | STA | RSV |
627 * +--------------------------------------------------------------+
628 * 63 36 35 32 31 0
629 */
630
631 for (n = 0; n < adapter->num_tx_queues; n++) {
632 tx_ring = adapter->tx_ring[n];
633 pr_info("------------------------------------\n");
634 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
635 pr_info("------------------------------------\n");
636 pr_info("%s%s %s %s %s %s\n",
637 "T [desc] [address 63:0 ] ",
638 "[PlPOIdStDDt Ln] [bi->dma ] ",
639 "leng", "ntw", "timestamp", "bi->skb");
640
641 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
642 tx_desc = IXGBE_TX_DESC(tx_ring, i);
643 tx_buffer = &tx_ring->tx_buffer_info[i];
644 u0 = (struct my_u0 *)tx_desc;
645 if (dma_unmap_len(tx_buffer, len) > 0) {
646 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
647 i,
648 le64_to_cpu(u0->a),
649 le64_to_cpu(u0->b),
650 (u64)dma_unmap_addr(tx_buffer, dma),
651 dma_unmap_len(tx_buffer, len),
652 tx_buffer->next_to_watch,
653 (u64)tx_buffer->time_stamp,
654 tx_buffer->skb);
655 if (i == tx_ring->next_to_use &&
656 i == tx_ring->next_to_clean)
657 pr_cont(" NTC/U\n");
658 else if (i == tx_ring->next_to_use)
659 pr_cont(" NTU\n");
660 else if (i == tx_ring->next_to_clean)
661 pr_cont(" NTC\n");
662 else
663 pr_cont("\n");
664
665 if (netif_msg_pktdata(adapter) &&
666 tx_buffer->skb)
667 print_hex_dump(KERN_INFO, "",
668 DUMP_PREFIX_ADDRESS, 16, 1,
669 tx_buffer->skb->data,
670 dma_unmap_len(tx_buffer, len),
671 true);
672 }
673 }
674 }
675
676 /* Print RX Rings Summary */
677 rx_ring_summary:
678 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
679 pr_info("Queue [NTU] [NTC]\n");
680 for (n = 0; n < adapter->num_rx_queues; n++) {
681 rx_ring = adapter->rx_ring[n];
682 pr_info("%5d %5X %5X\n",
683 n, rx_ring->next_to_use, rx_ring->next_to_clean);
684 }
685
686 /* Print RX Rings */
687 if (!netif_msg_rx_status(adapter))
688 return;
689
690 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
691
692 /* Receive Descriptor Formats
693 *
694 * 82598 Advanced Receive Descriptor (Read) Format
695 * 63 1 0
696 * +-----------------------------------------------------+
697 * 0 | Packet Buffer Address [63:1] |A0/NSE|
698 * +----------------------------------------------+------+
699 * 8 | Header Buffer Address [63:1] | DD |
700 * +-----------------------------------------------------+
701 *
702 *
703 * 82598 Advanced Receive Descriptor (Write-Back) Format
704 *
705 * 63 48 47 32 31 30 21 20 16 15 4 3 0
706 * +------------------------------------------------------+
707 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
708 * | Packet | IP | | | | Type | Type |
709 * | Checksum | Ident | | | | | |
710 * +------------------------------------------------------+
711 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
712 * +------------------------------------------------------+
713 * 63 48 47 32 31 20 19 0
714 *
715 * 82599+ Advanced Receive Descriptor (Read) Format
716 * 63 1 0
717 * +-----------------------------------------------------+
718 * 0 | Packet Buffer Address [63:1] |A0/NSE|
719 * +----------------------------------------------+------+
720 * 8 | Header Buffer Address [63:1] | DD |
721 * +-----------------------------------------------------+
722 *
723 *
724 * 82599+ Advanced Receive Descriptor (Write-Back) Format
725 *
726 * 63 48 47 32 31 30 21 20 17 16 4 3 0
727 * +------------------------------------------------------+
728 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
729 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
730 * |/ Flow Dir Flt ID | | | | | |
731 * +------------------------------------------------------+
732 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
733 * +------------------------------------------------------+
734 * 63 48 47 32 31 20 19 0
735 */
736
737 for (n = 0; n < adapter->num_rx_queues; n++) {
738 rx_ring = adapter->rx_ring[n];
739 pr_info("------------------------------------\n");
740 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
741 pr_info("------------------------------------\n");
742 pr_info("%s%s%s",
743 "R [desc] [ PktBuf A0] ",
744 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
745 "<-- Adv Rx Read format\n");
746 pr_info("%s%s%s",
747 "RWB[desc] [PcsmIpSHl PtRs] ",
748 "[vl er S cks ln] ---------------- [bi->skb ] ",
749 "<-- Adv Rx Write-Back format\n");
750
751 for (i = 0; i < rx_ring->count; i++) {
752 rx_buffer_info = &rx_ring->rx_buffer_info[i];
753 rx_desc = IXGBE_RX_DESC(rx_ring, i);
754 u0 = (struct my_u0 *)rx_desc;
755 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
756 if (staterr & IXGBE_RXD_STAT_DD) {
757 /* Descriptor Done */
758 pr_info("RWB[0x%03X] %016llX "
759 "%016llX ---------------- %p", i,
760 le64_to_cpu(u0->a),
761 le64_to_cpu(u0->b),
762 rx_buffer_info->skb);
763 } else {
764 pr_info("R [0x%03X] %016llX "
765 "%016llX %016llX %p", i,
766 le64_to_cpu(u0->a),
767 le64_to_cpu(u0->b),
768 (u64)rx_buffer_info->dma,
769 rx_buffer_info->skb);
770
771 if (netif_msg_pktdata(adapter) &&
772 rx_buffer_info->dma) {
773 print_hex_dump(KERN_INFO, "",
774 DUMP_PREFIX_ADDRESS, 16, 1,
775 page_address(rx_buffer_info->page) +
776 rx_buffer_info->page_offset,
777 ixgbe_rx_bufsz(rx_ring), true);
778 }
779 }
780
781 if (i == rx_ring->next_to_use)
782 pr_cont(" NTU\n");
783 else if (i == rx_ring->next_to_clean)
784 pr_cont(" NTC\n");
785 else
786 pr_cont("\n");
787
788 }
789 }
790 }
791
792 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
793 {
794 u32 ctrl_ext;
795
796 /* Let firmware take over control of h/w */
797 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
798 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
799 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
800 }
801
802 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
803 {
804 u32 ctrl_ext;
805
806 /* Let firmware know the driver has taken over */
807 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
808 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
809 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
810 }
811
812 /**
813 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
814 * @adapter: pointer to adapter struct
815 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
816 * @queue: queue to map the corresponding interrupt to
817 * @msix_vector: the vector to map to the corresponding queue
818 *
819 */
820 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
821 u8 queue, u8 msix_vector)
822 {
823 u32 ivar, index;
824 struct ixgbe_hw *hw = &adapter->hw;
825 switch (hw->mac.type) {
826 case ixgbe_mac_82598EB:
827 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
828 if (direction == -1)
829 direction = 0;
830 index = (((direction * 64) + queue) >> 2) & 0x1F;
831 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
832 ivar &= ~(0xFF << (8 * (queue & 0x3)));
833 ivar |= (msix_vector << (8 * (queue & 0x3)));
834 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
835 break;
836 case ixgbe_mac_82599EB:
837 case ixgbe_mac_X540:
838 if (direction == -1) {
839 /* other causes */
840 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
841 index = ((queue & 1) * 8);
842 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
843 ivar &= ~(0xFF << index);
844 ivar |= (msix_vector << index);
845 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
846 break;
847 } else {
848 /* tx or rx causes */
849 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
850 index = ((16 * (queue & 1)) + (8 * direction));
851 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
852 ivar &= ~(0xFF << index);
853 ivar |= (msix_vector << index);
854 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
855 break;
856 }
857 default:
858 break;
859 }
860 }
861
862 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
863 u64 qmask)
864 {
865 u32 mask;
866
867 switch (adapter->hw.mac.type) {
868 case ixgbe_mac_82598EB:
869 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
870 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
871 break;
872 case ixgbe_mac_82599EB:
873 case ixgbe_mac_X540:
874 mask = (qmask & 0xFFFFFFFF);
875 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
876 mask = (qmask >> 32);
877 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
878 break;
879 default:
880 break;
881 }
882 }
883
884 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
885 struct ixgbe_tx_buffer *tx_buffer)
886 {
887 if (tx_buffer->skb) {
888 dev_kfree_skb_any(tx_buffer->skb);
889 if (dma_unmap_len(tx_buffer, len))
890 dma_unmap_single(ring->dev,
891 dma_unmap_addr(tx_buffer, dma),
892 dma_unmap_len(tx_buffer, len),
893 DMA_TO_DEVICE);
894 } else if (dma_unmap_len(tx_buffer, len)) {
895 dma_unmap_page(ring->dev,
896 dma_unmap_addr(tx_buffer, dma),
897 dma_unmap_len(tx_buffer, len),
898 DMA_TO_DEVICE);
899 }
900 tx_buffer->next_to_watch = NULL;
901 tx_buffer->skb = NULL;
902 dma_unmap_len_set(tx_buffer, len, 0);
903 /* tx_buffer must be completely set up in the transmit path */
904 }
905
906 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
907 {
908 struct ixgbe_hw *hw = &adapter->hw;
909 struct ixgbe_hw_stats *hwstats = &adapter->stats;
910 int i;
911 u32 data;
912
913 if ((hw->fc.current_mode != ixgbe_fc_full) &&
914 (hw->fc.current_mode != ixgbe_fc_rx_pause))
915 return;
916
917 switch (hw->mac.type) {
918 case ixgbe_mac_82598EB:
919 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
920 break;
921 default:
922 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
923 }
924 hwstats->lxoffrxc += data;
925
926 /* refill credits (no tx hang) if we received xoff */
927 if (!data)
928 return;
929
930 for (i = 0; i < adapter->num_tx_queues; i++)
931 clear_bit(__IXGBE_HANG_CHECK_ARMED,
932 &adapter->tx_ring[i]->state);
933 }
934
935 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
936 {
937 struct ixgbe_hw *hw = &adapter->hw;
938 struct ixgbe_hw_stats *hwstats = &adapter->stats;
939 u32 xoff[8] = {0};
940 u8 tc;
941 int i;
942 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
943
944 if (adapter->ixgbe_ieee_pfc)
945 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
946
947 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
948 ixgbe_update_xoff_rx_lfc(adapter);
949 return;
950 }
951
952 /* update stats for each tc, only valid with PFC enabled */
953 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
954 u32 pxoffrxc;
955
956 switch (hw->mac.type) {
957 case ixgbe_mac_82598EB:
958 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
959 break;
960 default:
961 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
962 }
963 hwstats->pxoffrxc[i] += pxoffrxc;
964 /* Get the TC for given UP */
965 tc = netdev_get_prio_tc_map(adapter->netdev, i);
966 xoff[tc] += pxoffrxc;
967 }
968
969 /* disarm tx queues that have received xoff frames */
970 for (i = 0; i < adapter->num_tx_queues; i++) {
971 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
972
973 tc = tx_ring->dcb_tc;
974 if (xoff[tc])
975 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
976 }
977 }
978
979 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
980 {
981 return ring->stats.packets;
982 }
983
984 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
985 {
986 struct ixgbe_adapter *adapter;
987 struct ixgbe_hw *hw;
988 u32 head, tail;
989
990 if (ring->l2_accel_priv)
991 adapter = ring->l2_accel_priv->real_adapter;
992 else
993 adapter = netdev_priv(ring->netdev);
994
995 hw = &adapter->hw;
996 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
997 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
998
999 if (head != tail)
1000 return (head < tail) ?
1001 tail - head : (tail + ring->count - head);
1002
1003 return 0;
1004 }
1005
1006 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1007 {
1008 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1009 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1010 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1011
1012 clear_check_for_tx_hang(tx_ring);
1013
1014 /*
1015 * Check for a hung queue, but be thorough. This verifies
1016 * that a transmit has been completed since the previous
1017 * check AND there is at least one packet pending. The
1018 * ARMED bit is set to indicate a potential hang. The
1019 * bit is cleared if a pause frame is received to remove
1020 * false hang detection due to PFC or 802.3x frames. By
1021 * requiring this to fail twice we avoid races with
1022 * pfc clearing the ARMED bit and conditions where we
1023 * run the check_tx_hang logic with a transmit completion
1024 * pending but without time to complete it yet.
1025 */
1026 if (tx_done_old == tx_done && tx_pending)
1027 /* make sure it is true for two checks in a row */
1028 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1029 &tx_ring->state);
1030 /* update completed stats and continue */
1031 tx_ring->tx_stats.tx_done_old = tx_done;
1032 /* reset the countdown */
1033 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1034
1035 return false;
1036 }
1037
1038 /**
1039 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1040 * @adapter: driver private struct
1041 **/
1042 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1043 {
1044
1045 /* Do the reset outside of interrupt context */
1046 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1047 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
1048 e_warn(drv, "initiating reset due to tx timeout\n");
1049 ixgbe_service_event_schedule(adapter);
1050 }
1051 }
1052
1053 /**
1054 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
1055 * @q_vector: structure containing interrupt and ring information
1056 * @tx_ring: tx ring to clean
1057 **/
1058 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
1059 struct ixgbe_ring *tx_ring)
1060 {
1061 struct ixgbe_adapter *adapter = q_vector->adapter;
1062 struct ixgbe_tx_buffer *tx_buffer;
1063 union ixgbe_adv_tx_desc *tx_desc;
1064 unsigned int total_bytes = 0, total_packets = 0;
1065 unsigned int budget = q_vector->tx.work_limit;
1066 unsigned int i = tx_ring->next_to_clean;
1067
1068 if (test_bit(__IXGBE_DOWN, &adapter->state))
1069 return true;
1070
1071 tx_buffer = &tx_ring->tx_buffer_info[i];
1072 tx_desc = IXGBE_TX_DESC(tx_ring, i);
1073 i -= tx_ring->count;
1074
1075 do {
1076 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1077
1078 /* if next_to_watch is not set then there is no work pending */
1079 if (!eop_desc)
1080 break;
1081
1082 /* prevent any other reads prior to eop_desc */
1083 read_barrier_depends();
1084
1085 /* if DD is not set pending work has not been completed */
1086 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1087 break;
1088
1089 /* clear next_to_watch to prevent false hangs */
1090 tx_buffer->next_to_watch = NULL;
1091
1092 /* update the statistics for this packet */
1093 total_bytes += tx_buffer->bytecount;
1094 total_packets += tx_buffer->gso_segs;
1095
1096 /* free the skb */
1097 dev_kfree_skb_any(tx_buffer->skb);
1098
1099 /* unmap skb header data */
1100 dma_unmap_single(tx_ring->dev,
1101 dma_unmap_addr(tx_buffer, dma),
1102 dma_unmap_len(tx_buffer, len),
1103 DMA_TO_DEVICE);
1104
1105 /* clear tx_buffer data */
1106 tx_buffer->skb = NULL;
1107 dma_unmap_len_set(tx_buffer, len, 0);
1108
1109 /* unmap remaining buffers */
1110 while (tx_desc != eop_desc) {
1111 tx_buffer++;
1112 tx_desc++;
1113 i++;
1114 if (unlikely(!i)) {
1115 i -= tx_ring->count;
1116 tx_buffer = tx_ring->tx_buffer_info;
1117 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1118 }
1119
1120 /* unmap any remaining paged data */
1121 if (dma_unmap_len(tx_buffer, len)) {
1122 dma_unmap_page(tx_ring->dev,
1123 dma_unmap_addr(tx_buffer, dma),
1124 dma_unmap_len(tx_buffer, len),
1125 DMA_TO_DEVICE);
1126 dma_unmap_len_set(tx_buffer, len, 0);
1127 }
1128 }
1129
1130 /* move us one more past the eop_desc for start of next pkt */
1131 tx_buffer++;
1132 tx_desc++;
1133 i++;
1134 if (unlikely(!i)) {
1135 i -= tx_ring->count;
1136 tx_buffer = tx_ring->tx_buffer_info;
1137 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1138 }
1139
1140 /* issue prefetch for next Tx descriptor */
1141 prefetch(tx_desc);
1142
1143 /* update budget accounting */
1144 budget--;
1145 } while (likely(budget));
1146
1147 i += tx_ring->count;
1148 tx_ring->next_to_clean = i;
1149 u64_stats_update_begin(&tx_ring->syncp);
1150 tx_ring->stats.bytes += total_bytes;
1151 tx_ring->stats.packets += total_packets;
1152 u64_stats_update_end(&tx_ring->syncp);
1153 q_vector->tx.total_bytes += total_bytes;
1154 q_vector->tx.total_packets += total_packets;
1155
1156 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1157 /* schedule immediate reset if we believe we hung */
1158 struct ixgbe_hw *hw = &adapter->hw;
1159 e_err(drv, "Detected Tx Unit Hang\n"
1160 " Tx Queue <%d>\n"
1161 " TDH, TDT <%x>, <%x>\n"
1162 " next_to_use <%x>\n"
1163 " next_to_clean <%x>\n"
1164 "tx_buffer_info[next_to_clean]\n"
1165 " time_stamp <%lx>\n"
1166 " jiffies <%lx>\n",
1167 tx_ring->queue_index,
1168 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1169 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1170 tx_ring->next_to_use, i,
1171 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1172
1173 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1174
1175 e_info(probe,
1176 "tx hang %d detected on queue %d, resetting adapter\n",
1177 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1178
1179 /* schedule immediate reset if we believe we hung */
1180 ixgbe_tx_timeout_reset(adapter);
1181
1182 /* the adapter is about to reset, no point in enabling stuff */
1183 return true;
1184 }
1185
1186 netdev_tx_completed_queue(txring_txq(tx_ring),
1187 total_packets, total_bytes);
1188
1189 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1190 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1191 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1192 /* Make sure that anybody stopping the queue after this
1193 * sees the new next_to_clean.
1194 */
1195 smp_mb();
1196 if (__netif_subqueue_stopped(tx_ring->netdev,
1197 tx_ring->queue_index)
1198 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1199 netif_wake_subqueue(tx_ring->netdev,
1200 tx_ring->queue_index);
1201 ++tx_ring->tx_stats.restart_queue;
1202 }
1203 }
1204
1205 return !!budget;
1206 }
1207
1208 #ifdef CONFIG_IXGBE_DCA
1209 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1210 struct ixgbe_ring *tx_ring,
1211 int cpu)
1212 {
1213 struct ixgbe_hw *hw = &adapter->hw;
1214 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1215 u16 reg_offset;
1216
1217 switch (hw->mac.type) {
1218 case ixgbe_mac_82598EB:
1219 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1220 break;
1221 case ixgbe_mac_82599EB:
1222 case ixgbe_mac_X540:
1223 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1224 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1225 break;
1226 default:
1227 /* for unknown hardware do not write register */
1228 return;
1229 }
1230
1231 /*
1232 * We can enable relaxed ordering for reads, but not writes when
1233 * DCA is enabled. This is due to a known issue in some chipsets
1234 * which will cause the DCA tag to be cleared.
1235 */
1236 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1237 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1238 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1239
1240 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1241 }
1242
1243 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1244 struct ixgbe_ring *rx_ring,
1245 int cpu)
1246 {
1247 struct ixgbe_hw *hw = &adapter->hw;
1248 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1249 u8 reg_idx = rx_ring->reg_idx;
1250
1251
1252 switch (hw->mac.type) {
1253 case ixgbe_mac_82599EB:
1254 case ixgbe_mac_X540:
1255 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1256 break;
1257 default:
1258 break;
1259 }
1260
1261 /*
1262 * We can enable relaxed ordering for reads, but not writes when
1263 * DCA is enabled. This is due to a known issue in some chipsets
1264 * which will cause the DCA tag to be cleared.
1265 */
1266 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1267 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1268
1269 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1270 }
1271
1272 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1273 {
1274 struct ixgbe_adapter *adapter = q_vector->adapter;
1275 struct ixgbe_ring *ring;
1276 int cpu = get_cpu();
1277
1278 if (q_vector->cpu == cpu)
1279 goto out_no_update;
1280
1281 ixgbe_for_each_ring(ring, q_vector->tx)
1282 ixgbe_update_tx_dca(adapter, ring, cpu);
1283
1284 ixgbe_for_each_ring(ring, q_vector->rx)
1285 ixgbe_update_rx_dca(adapter, ring, cpu);
1286
1287 q_vector->cpu = cpu;
1288 out_no_update:
1289 put_cpu();
1290 }
1291
1292 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1293 {
1294 int i;
1295
1296 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1297 return;
1298
1299 /* always use CB2 mode, difference is masked in the CB driver */
1300 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1301
1302 for (i = 0; i < adapter->num_q_vectors; i++) {
1303 adapter->q_vector[i]->cpu = -1;
1304 ixgbe_update_dca(adapter->q_vector[i]);
1305 }
1306 }
1307
1308 static int __ixgbe_notify_dca(struct device *dev, void *data)
1309 {
1310 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1311 unsigned long event = *(unsigned long *)data;
1312
1313 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1314 return 0;
1315
1316 switch (event) {
1317 case DCA_PROVIDER_ADD:
1318 /* if we're already enabled, don't do it again */
1319 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1320 break;
1321 if (dca_add_requester(dev) == 0) {
1322 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1323 ixgbe_setup_dca(adapter);
1324 break;
1325 }
1326 /* Fall Through since DCA is disabled. */
1327 case DCA_PROVIDER_REMOVE:
1328 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1329 dca_remove_requester(dev);
1330 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1331 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1332 }
1333 break;
1334 }
1335
1336 return 0;
1337 }
1338
1339 #endif /* CONFIG_IXGBE_DCA */
1340 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1341 union ixgbe_adv_rx_desc *rx_desc,
1342 struct sk_buff *skb)
1343 {
1344 if (ring->netdev->features & NETIF_F_RXHASH)
1345 skb_set_hash(skb,
1346 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1347 PKT_HASH_TYPE_L3);
1348 }
1349
1350 #ifdef IXGBE_FCOE
1351 /**
1352 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1353 * @ring: structure containing ring specific data
1354 * @rx_desc: advanced rx descriptor
1355 *
1356 * Returns : true if it is FCoE pkt
1357 */
1358 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1359 union ixgbe_adv_rx_desc *rx_desc)
1360 {
1361 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1362
1363 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1364 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1365 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1366 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1367 }
1368
1369 #endif /* IXGBE_FCOE */
1370 /**
1371 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1372 * @ring: structure containing ring specific data
1373 * @rx_desc: current Rx descriptor being processed
1374 * @skb: skb currently being received and modified
1375 **/
1376 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1377 union ixgbe_adv_rx_desc *rx_desc,
1378 struct sk_buff *skb)
1379 {
1380 skb_checksum_none_assert(skb);
1381
1382 /* Rx csum disabled */
1383 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1384 return;
1385
1386 /* if IP and error */
1387 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1388 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1389 ring->rx_stats.csum_err++;
1390 return;
1391 }
1392
1393 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1394 return;
1395
1396 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1397 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1398
1399 /*
1400 * 82599 errata, UDP frames with a 0 checksum can be marked as
1401 * checksum errors.
1402 */
1403 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1404 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1405 return;
1406
1407 ring->rx_stats.csum_err++;
1408 return;
1409 }
1410
1411 /* It must be a TCP or UDP packet with a valid checksum */
1412 skb->ip_summed = CHECKSUM_UNNECESSARY;
1413 }
1414
1415 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1416 {
1417 rx_ring->next_to_use = val;
1418
1419 /* update next to alloc since we have filled the ring */
1420 rx_ring->next_to_alloc = val;
1421 /*
1422 * Force memory writes to complete before letting h/w
1423 * know there are new descriptors to fetch. (Only
1424 * applicable for weak-ordered memory model archs,
1425 * such as IA-64).
1426 */
1427 wmb();
1428 ixgbe_write_tail(rx_ring, val);
1429 }
1430
1431 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1432 struct ixgbe_rx_buffer *bi)
1433 {
1434 struct page *page = bi->page;
1435 dma_addr_t dma = bi->dma;
1436
1437 /* since we are recycling buffers we should seldom need to alloc */
1438 if (likely(dma))
1439 return true;
1440
1441 /* alloc new page for storage */
1442 if (likely(!page)) {
1443 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1444 bi->skb, ixgbe_rx_pg_order(rx_ring));
1445 if (unlikely(!page)) {
1446 rx_ring->rx_stats.alloc_rx_page_failed++;
1447 return false;
1448 }
1449 bi->page = page;
1450 }
1451
1452 /* map page for use */
1453 dma = dma_map_page(rx_ring->dev, page, 0,
1454 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1455
1456 /*
1457 * if mapping failed free memory back to system since
1458 * there isn't much point in holding memory we can't use
1459 */
1460 if (dma_mapping_error(rx_ring->dev, dma)) {
1461 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1462 bi->page = NULL;
1463
1464 rx_ring->rx_stats.alloc_rx_page_failed++;
1465 return false;
1466 }
1467
1468 bi->dma = dma;
1469 bi->page_offset = 0;
1470
1471 return true;
1472 }
1473
1474 /**
1475 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1476 * @rx_ring: ring to place buffers on
1477 * @cleaned_count: number of buffers to replace
1478 **/
1479 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1480 {
1481 union ixgbe_adv_rx_desc *rx_desc;
1482 struct ixgbe_rx_buffer *bi;
1483 u16 i = rx_ring->next_to_use;
1484
1485 /* nothing to do */
1486 if (!cleaned_count)
1487 return;
1488
1489 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1490 bi = &rx_ring->rx_buffer_info[i];
1491 i -= rx_ring->count;
1492
1493 do {
1494 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1495 break;
1496
1497 /*
1498 * Refresh the desc even if buffer_addrs didn't change
1499 * because each write-back erases this info.
1500 */
1501 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1502
1503 rx_desc++;
1504 bi++;
1505 i++;
1506 if (unlikely(!i)) {
1507 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1508 bi = rx_ring->rx_buffer_info;
1509 i -= rx_ring->count;
1510 }
1511
1512 /* clear the hdr_addr for the next_to_use descriptor */
1513 rx_desc->read.hdr_addr = 0;
1514
1515 cleaned_count--;
1516 } while (cleaned_count);
1517
1518 i += rx_ring->count;
1519
1520 if (rx_ring->next_to_use != i)
1521 ixgbe_release_rx_desc(rx_ring, i);
1522 }
1523
1524 /**
1525 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1526 * @data: pointer to the start of the headers
1527 * @max_len: total length of section to find headers in
1528 *
1529 * This function is meant to determine the length of headers that will
1530 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1531 * motivation of doing this is to only perform one pull for IPv4 TCP
1532 * packets so that we can do basic things like calculating the gso_size
1533 * based on the average data per packet.
1534 **/
1535 static unsigned int ixgbe_get_headlen(unsigned char *data,
1536 unsigned int max_len)
1537 {
1538 union {
1539 unsigned char *network;
1540 /* l2 headers */
1541 struct ethhdr *eth;
1542 struct vlan_hdr *vlan;
1543 /* l3 headers */
1544 struct iphdr *ipv4;
1545 struct ipv6hdr *ipv6;
1546 } hdr;
1547 __be16 protocol;
1548 u8 nexthdr = 0; /* default to not TCP */
1549 u8 hlen;
1550
1551 /* this should never happen, but better safe than sorry */
1552 if (max_len < ETH_HLEN)
1553 return max_len;
1554
1555 /* initialize network frame pointer */
1556 hdr.network = data;
1557
1558 /* set first protocol and move network header forward */
1559 protocol = hdr.eth->h_proto;
1560 hdr.network += ETH_HLEN;
1561
1562 /* handle any vlan tag if present */
1563 if (protocol == htons(ETH_P_8021Q)) {
1564 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1565 return max_len;
1566
1567 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1568 hdr.network += VLAN_HLEN;
1569 }
1570
1571 /* handle L3 protocols */
1572 if (protocol == htons(ETH_P_IP)) {
1573 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1574 return max_len;
1575
1576 /* access ihl as a u8 to avoid unaligned access on ia64 */
1577 hlen = (hdr.network[0] & 0x0F) << 2;
1578
1579 /* verify hlen meets minimum size requirements */
1580 if (hlen < sizeof(struct iphdr))
1581 return hdr.network - data;
1582
1583 /* record next protocol if header is present */
1584 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
1585 nexthdr = hdr.ipv4->protocol;
1586 } else if (protocol == htons(ETH_P_IPV6)) {
1587 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1588 return max_len;
1589
1590 /* record next protocol */
1591 nexthdr = hdr.ipv6->nexthdr;
1592 hlen = sizeof(struct ipv6hdr);
1593 #ifdef IXGBE_FCOE
1594 } else if (protocol == htons(ETH_P_FCOE)) {
1595 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1596 return max_len;
1597 hlen = FCOE_HEADER_LEN;
1598 #endif
1599 } else {
1600 return hdr.network - data;
1601 }
1602
1603 /* relocate pointer to start of L4 header */
1604 hdr.network += hlen;
1605
1606 /* finally sort out TCP/UDP */
1607 if (nexthdr == IPPROTO_TCP) {
1608 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1609 return max_len;
1610
1611 /* access doff as a u8 to avoid unaligned access on ia64 */
1612 hlen = (hdr.network[12] & 0xF0) >> 2;
1613
1614 /* verify hlen meets minimum size requirements */
1615 if (hlen < sizeof(struct tcphdr))
1616 return hdr.network - data;
1617
1618 hdr.network += hlen;
1619 } else if (nexthdr == IPPROTO_UDP) {
1620 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1621 return max_len;
1622
1623 hdr.network += sizeof(struct udphdr);
1624 }
1625
1626 /*
1627 * If everything has gone correctly hdr.network should be the
1628 * data section of the packet and will be the end of the header.
1629 * If not then it probably represents the end of the last recognized
1630 * header.
1631 */
1632 if ((hdr.network - data) < max_len)
1633 return hdr.network - data;
1634 else
1635 return max_len;
1636 }
1637
1638 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1639 struct sk_buff *skb)
1640 {
1641 u16 hdr_len = skb_headlen(skb);
1642
1643 /* set gso_size to avoid messing up TCP MSS */
1644 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1645 IXGBE_CB(skb)->append_cnt);
1646 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1647 }
1648
1649 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1650 struct sk_buff *skb)
1651 {
1652 /* if append_cnt is 0 then frame is not RSC */
1653 if (!IXGBE_CB(skb)->append_cnt)
1654 return;
1655
1656 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1657 rx_ring->rx_stats.rsc_flush++;
1658
1659 ixgbe_set_rsc_gso_size(rx_ring, skb);
1660
1661 /* gso_size is computed using append_cnt so always clear it last */
1662 IXGBE_CB(skb)->append_cnt = 0;
1663 }
1664
1665 /**
1666 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1667 * @rx_ring: rx descriptor ring packet is being transacted on
1668 * @rx_desc: pointer to the EOP Rx descriptor
1669 * @skb: pointer to current skb being populated
1670 *
1671 * This function checks the ring, descriptor, and packet information in
1672 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1673 * other fields within the skb.
1674 **/
1675 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1676 union ixgbe_adv_rx_desc *rx_desc,
1677 struct sk_buff *skb)
1678 {
1679 struct net_device *dev = rx_ring->netdev;
1680
1681 ixgbe_update_rsc_stats(rx_ring, skb);
1682
1683 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1684
1685 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1686
1687 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1688 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
1689
1690 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1691 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1692 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1693 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1694 }
1695
1696 skb_record_rx_queue(skb, rx_ring->queue_index);
1697
1698 skb->protocol = eth_type_trans(skb, dev);
1699 }
1700
1701 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1702 struct sk_buff *skb)
1703 {
1704 struct ixgbe_adapter *adapter = q_vector->adapter;
1705
1706 if (ixgbe_qv_busy_polling(q_vector))
1707 netif_receive_skb(skb);
1708 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1709 napi_gro_receive(&q_vector->napi, skb);
1710 else
1711 netif_rx(skb);
1712 }
1713
1714 /**
1715 * ixgbe_is_non_eop - process handling of non-EOP buffers
1716 * @rx_ring: Rx ring being processed
1717 * @rx_desc: Rx descriptor for current buffer
1718 * @skb: Current socket buffer containing buffer in progress
1719 *
1720 * This function updates next to clean. If the buffer is an EOP buffer
1721 * this function exits returning false, otherwise it will place the
1722 * sk_buff in the next buffer to be chained and return true indicating
1723 * that this is in fact a non-EOP buffer.
1724 **/
1725 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1726 union ixgbe_adv_rx_desc *rx_desc,
1727 struct sk_buff *skb)
1728 {
1729 u32 ntc = rx_ring->next_to_clean + 1;
1730
1731 /* fetch, update, and store next to clean */
1732 ntc = (ntc < rx_ring->count) ? ntc : 0;
1733 rx_ring->next_to_clean = ntc;
1734
1735 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1736
1737 /* update RSC append count if present */
1738 if (ring_is_rsc_enabled(rx_ring)) {
1739 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1740 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1741
1742 if (unlikely(rsc_enabled)) {
1743 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1744
1745 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1746 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1747
1748 /* update ntc based on RSC value */
1749 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1750 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1751 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1752 }
1753 }
1754
1755 /* if we are the last buffer then there is nothing else to do */
1756 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1757 return false;
1758
1759 /* place skb in next buffer to be received */
1760 rx_ring->rx_buffer_info[ntc].skb = skb;
1761 rx_ring->rx_stats.non_eop_descs++;
1762
1763 return true;
1764 }
1765
1766 /**
1767 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1768 * @rx_ring: rx descriptor ring packet is being transacted on
1769 * @skb: pointer to current skb being adjusted
1770 *
1771 * This function is an ixgbe specific version of __pskb_pull_tail. The
1772 * main difference between this version and the original function is that
1773 * this function can make several assumptions about the state of things
1774 * that allow for significant optimizations versus the standard function.
1775 * As a result we can do things like drop a frag and maintain an accurate
1776 * truesize for the skb.
1777 */
1778 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1779 struct sk_buff *skb)
1780 {
1781 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1782 unsigned char *va;
1783 unsigned int pull_len;
1784
1785 /*
1786 * it is valid to use page_address instead of kmap since we are
1787 * working with pages allocated out of the lomem pool per
1788 * alloc_page(GFP_ATOMIC)
1789 */
1790 va = skb_frag_address(frag);
1791
1792 /*
1793 * we need the header to contain the greater of either ETH_HLEN or
1794 * 60 bytes if the skb->len is less than 60 for skb_pad.
1795 */
1796 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
1797
1798 /* align pull length to size of long to optimize memcpy performance */
1799 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1800
1801 /* update all of the pointers */
1802 skb_frag_size_sub(frag, pull_len);
1803 frag->page_offset += pull_len;
1804 skb->data_len -= pull_len;
1805 skb->tail += pull_len;
1806 }
1807
1808 /**
1809 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1810 * @rx_ring: rx descriptor ring packet is being transacted on
1811 * @skb: pointer to current skb being updated
1812 *
1813 * This function provides a basic DMA sync up for the first fragment of an
1814 * skb. The reason for doing this is that the first fragment cannot be
1815 * unmapped until we have reached the end of packet descriptor for a buffer
1816 * chain.
1817 */
1818 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1819 struct sk_buff *skb)
1820 {
1821 /* if the page was released unmap it, else just sync our portion */
1822 if (unlikely(IXGBE_CB(skb)->page_released)) {
1823 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1824 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1825 IXGBE_CB(skb)->page_released = false;
1826 } else {
1827 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1828
1829 dma_sync_single_range_for_cpu(rx_ring->dev,
1830 IXGBE_CB(skb)->dma,
1831 frag->page_offset,
1832 ixgbe_rx_bufsz(rx_ring),
1833 DMA_FROM_DEVICE);
1834 }
1835 IXGBE_CB(skb)->dma = 0;
1836 }
1837
1838 /**
1839 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1840 * @rx_ring: rx descriptor ring packet is being transacted on
1841 * @rx_desc: pointer to the EOP Rx descriptor
1842 * @skb: pointer to current skb being fixed
1843 *
1844 * Check for corrupted packet headers caused by senders on the local L2
1845 * embedded NIC switch not setting up their Tx Descriptors right. These
1846 * should be very rare.
1847 *
1848 * Also address the case where we are pulling data in on pages only
1849 * and as such no data is present in the skb header.
1850 *
1851 * In addition if skb is not at least 60 bytes we need to pad it so that
1852 * it is large enough to qualify as a valid Ethernet frame.
1853 *
1854 * Returns true if an error was encountered and skb was freed.
1855 **/
1856 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1857 union ixgbe_adv_rx_desc *rx_desc,
1858 struct sk_buff *skb)
1859 {
1860 struct net_device *netdev = rx_ring->netdev;
1861
1862 /* verify that the packet does not have any known errors */
1863 if (unlikely(ixgbe_test_staterr(rx_desc,
1864 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1865 !(netdev->features & NETIF_F_RXALL))) {
1866 dev_kfree_skb_any(skb);
1867 return true;
1868 }
1869
1870 /* place header in linear portion of buffer */
1871 if (skb_is_nonlinear(skb))
1872 ixgbe_pull_tail(rx_ring, skb);
1873
1874 #ifdef IXGBE_FCOE
1875 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1876 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1877 return false;
1878
1879 #endif
1880 /* if skb_pad returns an error the skb was freed */
1881 if (unlikely(skb->len < 60)) {
1882 int pad_len = 60 - skb->len;
1883
1884 if (skb_pad(skb, pad_len))
1885 return true;
1886 __skb_put(skb, pad_len);
1887 }
1888
1889 return false;
1890 }
1891
1892 /**
1893 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1894 * @rx_ring: rx descriptor ring to store buffers on
1895 * @old_buff: donor buffer to have page reused
1896 *
1897 * Synchronizes page for reuse by the adapter
1898 **/
1899 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1900 struct ixgbe_rx_buffer *old_buff)
1901 {
1902 struct ixgbe_rx_buffer *new_buff;
1903 u16 nta = rx_ring->next_to_alloc;
1904
1905 new_buff = &rx_ring->rx_buffer_info[nta];
1906
1907 /* update, and store next to alloc */
1908 nta++;
1909 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1910
1911 /* transfer page from old buffer to new buffer */
1912 new_buff->page = old_buff->page;
1913 new_buff->dma = old_buff->dma;
1914 new_buff->page_offset = old_buff->page_offset;
1915
1916 /* sync the buffer for use by the device */
1917 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1918 new_buff->page_offset,
1919 ixgbe_rx_bufsz(rx_ring),
1920 DMA_FROM_DEVICE);
1921 }
1922
1923 /**
1924 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1925 * @rx_ring: rx descriptor ring to transact packets on
1926 * @rx_buffer: buffer containing page to add
1927 * @rx_desc: descriptor containing length of buffer written by hardware
1928 * @skb: sk_buff to place the data into
1929 *
1930 * This function will add the data contained in rx_buffer->page to the skb.
1931 * This is done either through a direct copy if the data in the buffer is
1932 * less than the skb header size, otherwise it will just attach the page as
1933 * a frag to the skb.
1934 *
1935 * The function will then update the page offset if necessary and return
1936 * true if the buffer can be reused by the adapter.
1937 **/
1938 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1939 struct ixgbe_rx_buffer *rx_buffer,
1940 union ixgbe_adv_rx_desc *rx_desc,
1941 struct sk_buff *skb)
1942 {
1943 struct page *page = rx_buffer->page;
1944 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1945 #if (PAGE_SIZE < 8192)
1946 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1947 #else
1948 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1949 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1950 ixgbe_rx_bufsz(rx_ring);
1951 #endif
1952
1953 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1954 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1955
1956 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1957
1958 /* we can reuse buffer as-is, just make sure it is local */
1959 if (likely(page_to_nid(page) == numa_node_id()))
1960 return true;
1961
1962 /* this page cannot be reused so discard it */
1963 put_page(page);
1964 return false;
1965 }
1966
1967 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1968 rx_buffer->page_offset, size, truesize);
1969
1970 /* avoid re-using remote pages */
1971 if (unlikely(page_to_nid(page) != numa_node_id()))
1972 return false;
1973
1974 #if (PAGE_SIZE < 8192)
1975 /* if we are only owner of page we can reuse it */
1976 if (unlikely(page_count(page) != 1))
1977 return false;
1978
1979 /* flip page offset to other buffer */
1980 rx_buffer->page_offset ^= truesize;
1981
1982 /*
1983 * since we are the only owner of the page and we need to
1984 * increment it, just set the value to 2 in order to avoid
1985 * an unecessary locked operation
1986 */
1987 atomic_set(&page->_count, 2);
1988 #else
1989 /* move offset up to the next cache line */
1990 rx_buffer->page_offset += truesize;
1991
1992 if (rx_buffer->page_offset > last_offset)
1993 return false;
1994
1995 /* bump ref count on page before it is given to the stack */
1996 get_page(page);
1997 #endif
1998
1999 return true;
2000 }
2001
2002 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
2003 union ixgbe_adv_rx_desc *rx_desc)
2004 {
2005 struct ixgbe_rx_buffer *rx_buffer;
2006 struct sk_buff *skb;
2007 struct page *page;
2008
2009 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2010 page = rx_buffer->page;
2011 prefetchw(page);
2012
2013 skb = rx_buffer->skb;
2014
2015 if (likely(!skb)) {
2016 void *page_addr = page_address(page) +
2017 rx_buffer->page_offset;
2018
2019 /* prefetch first cache line of first page */
2020 prefetch(page_addr);
2021 #if L1_CACHE_BYTES < 128
2022 prefetch(page_addr + L1_CACHE_BYTES);
2023 #endif
2024
2025 /* allocate a skb to store the frags */
2026 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
2027 IXGBE_RX_HDR_SIZE);
2028 if (unlikely(!skb)) {
2029 rx_ring->rx_stats.alloc_rx_buff_failed++;
2030 return NULL;
2031 }
2032
2033 /*
2034 * we will be copying header into skb->data in
2035 * pskb_may_pull so it is in our interest to prefetch
2036 * it now to avoid a possible cache miss
2037 */
2038 prefetchw(skb->data);
2039
2040 /*
2041 * Delay unmapping of the first packet. It carries the
2042 * header information, HW may still access the header
2043 * after the writeback. Only unmap it when EOP is
2044 * reached
2045 */
2046 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
2047 goto dma_sync;
2048
2049 IXGBE_CB(skb)->dma = rx_buffer->dma;
2050 } else {
2051 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2052 ixgbe_dma_sync_frag(rx_ring, skb);
2053
2054 dma_sync:
2055 /* we are reusing so sync this buffer for CPU use */
2056 dma_sync_single_range_for_cpu(rx_ring->dev,
2057 rx_buffer->dma,
2058 rx_buffer->page_offset,
2059 ixgbe_rx_bufsz(rx_ring),
2060 DMA_FROM_DEVICE);
2061 }
2062
2063 /* pull page into skb */
2064 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2065 /* hand second half of page back to the ring */
2066 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2067 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2068 /* the page has been released from the ring */
2069 IXGBE_CB(skb)->page_released = true;
2070 } else {
2071 /* we are not reusing the buffer so unmap it */
2072 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2073 ixgbe_rx_pg_size(rx_ring),
2074 DMA_FROM_DEVICE);
2075 }
2076
2077 /* clear contents of buffer_info */
2078 rx_buffer->skb = NULL;
2079 rx_buffer->dma = 0;
2080 rx_buffer->page = NULL;
2081
2082 return skb;
2083 }
2084
2085 /**
2086 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2087 * @q_vector: structure containing interrupt and ring information
2088 * @rx_ring: rx descriptor ring to transact packets on
2089 * @budget: Total limit on number of packets to process
2090 *
2091 * This function provides a "bounce buffer" approach to Rx interrupt
2092 * processing. The advantage to this is that on systems that have
2093 * expensive overhead for IOMMU access this provides a means of avoiding
2094 * it by maintaining the mapping of the page to the syste.
2095 *
2096 * Returns amount of work completed
2097 **/
2098 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
2099 struct ixgbe_ring *rx_ring,
2100 const int budget)
2101 {
2102 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2103 #ifdef IXGBE_FCOE
2104 struct ixgbe_adapter *adapter = q_vector->adapter;
2105 int ddp_bytes;
2106 unsigned int mss = 0;
2107 #endif /* IXGBE_FCOE */
2108 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
2109
2110 while (likely(total_rx_packets < budget)) {
2111 union ixgbe_adv_rx_desc *rx_desc;
2112 struct sk_buff *skb;
2113
2114 /* return some buffers to hardware, one at a time is too slow */
2115 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2116 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2117 cleaned_count = 0;
2118 }
2119
2120 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2121
2122 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2123 break;
2124
2125 /*
2126 * This memory barrier is needed to keep us from reading
2127 * any other fields out of the rx_desc until we know the
2128 * RXD_STAT_DD bit is set
2129 */
2130 rmb();
2131
2132 /* retrieve a buffer from the ring */
2133 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
2134
2135 /* exit if we failed to retrieve a buffer */
2136 if (!skb)
2137 break;
2138
2139 cleaned_count++;
2140
2141 /* place incomplete frames back on ring for completion */
2142 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2143 continue;
2144
2145 /* verify the packet layout is correct */
2146 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2147 continue;
2148
2149 /* probably a little skewed due to removing CRC */
2150 total_rx_bytes += skb->len;
2151
2152 /* populate checksum, timestamp, VLAN, and protocol */
2153 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2154
2155 #ifdef IXGBE_FCOE
2156 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2157 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2158 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2159 /* include DDPed FCoE data */
2160 if (ddp_bytes > 0) {
2161 if (!mss) {
2162 mss = rx_ring->netdev->mtu -
2163 sizeof(struct fcoe_hdr) -
2164 sizeof(struct fc_frame_header) -
2165 sizeof(struct fcoe_crc_eof);
2166 if (mss > 512)
2167 mss &= ~511;
2168 }
2169 total_rx_bytes += ddp_bytes;
2170 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2171 mss);
2172 }
2173 if (!ddp_bytes) {
2174 dev_kfree_skb_any(skb);
2175 continue;
2176 }
2177 }
2178
2179 #endif /* IXGBE_FCOE */
2180 skb_mark_napi_id(skb, &q_vector->napi);
2181 ixgbe_rx_skb(q_vector, skb);
2182
2183 /* update budget accounting */
2184 total_rx_packets++;
2185 }
2186
2187 u64_stats_update_begin(&rx_ring->syncp);
2188 rx_ring->stats.packets += total_rx_packets;
2189 rx_ring->stats.bytes += total_rx_bytes;
2190 u64_stats_update_end(&rx_ring->syncp);
2191 q_vector->rx.total_packets += total_rx_packets;
2192 q_vector->rx.total_bytes += total_rx_bytes;
2193
2194 if (cleaned_count)
2195 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2196
2197 return total_rx_packets;
2198 }
2199
2200 #ifdef CONFIG_NET_RX_BUSY_POLL
2201 /* must be called with local_bh_disable()d */
2202 static int ixgbe_low_latency_recv(struct napi_struct *napi)
2203 {
2204 struct ixgbe_q_vector *q_vector =
2205 container_of(napi, struct ixgbe_q_vector, napi);
2206 struct ixgbe_adapter *adapter = q_vector->adapter;
2207 struct ixgbe_ring *ring;
2208 int found = 0;
2209
2210 if (test_bit(__IXGBE_DOWN, &adapter->state))
2211 return LL_FLUSH_FAILED;
2212
2213 if (!ixgbe_qv_lock_poll(q_vector))
2214 return LL_FLUSH_BUSY;
2215
2216 ixgbe_for_each_ring(ring, q_vector->rx) {
2217 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
2218 #ifdef BP_EXTENDED_STATS
2219 if (found)
2220 ring->stats.cleaned += found;
2221 else
2222 ring->stats.misses++;
2223 #endif
2224 if (found)
2225 break;
2226 }
2227
2228 ixgbe_qv_unlock_poll(q_vector);
2229
2230 return found;
2231 }
2232 #endif /* CONFIG_NET_RX_BUSY_POLL */
2233
2234 /**
2235 * ixgbe_configure_msix - Configure MSI-X hardware
2236 * @adapter: board private structure
2237 *
2238 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2239 * interrupts.
2240 **/
2241 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2242 {
2243 struct ixgbe_q_vector *q_vector;
2244 int v_idx;
2245 u32 mask;
2246
2247 /* Populate MSIX to EITR Select */
2248 if (adapter->num_vfs > 32) {
2249 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2250 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2251 }
2252
2253 /*
2254 * Populate the IVAR table and set the ITR values to the
2255 * corresponding register.
2256 */
2257 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2258 struct ixgbe_ring *ring;
2259 q_vector = adapter->q_vector[v_idx];
2260
2261 ixgbe_for_each_ring(ring, q_vector->rx)
2262 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2263
2264 ixgbe_for_each_ring(ring, q_vector->tx)
2265 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2266
2267 ixgbe_write_eitr(q_vector);
2268 }
2269
2270 switch (adapter->hw.mac.type) {
2271 case ixgbe_mac_82598EB:
2272 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2273 v_idx);
2274 break;
2275 case ixgbe_mac_82599EB:
2276 case ixgbe_mac_X540:
2277 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2278 break;
2279 default:
2280 break;
2281 }
2282 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2283
2284 /* set up to autoclear timer, and the vectors */
2285 mask = IXGBE_EIMS_ENABLE_MASK;
2286 mask &= ~(IXGBE_EIMS_OTHER |
2287 IXGBE_EIMS_MAILBOX |
2288 IXGBE_EIMS_LSC);
2289
2290 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2291 }
2292
2293 enum latency_range {
2294 lowest_latency = 0,
2295 low_latency = 1,
2296 bulk_latency = 2,
2297 latency_invalid = 255
2298 };
2299
2300 /**
2301 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2302 * @q_vector: structure containing interrupt and ring information
2303 * @ring_container: structure containing ring performance data
2304 *
2305 * Stores a new ITR value based on packets and byte
2306 * counts during the last interrupt. The advantage of per interrupt
2307 * computation is faster updates and more accurate ITR for the current
2308 * traffic pattern. Constants in this function were computed
2309 * based on theoretical maximum wire speed and thresholds were set based
2310 * on testing data as well as attempting to minimize response time
2311 * while increasing bulk throughput.
2312 * this functionality is controlled by the InterruptThrottleRate module
2313 * parameter (see ixgbe_param.c)
2314 **/
2315 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2316 struct ixgbe_ring_container *ring_container)
2317 {
2318 int bytes = ring_container->total_bytes;
2319 int packets = ring_container->total_packets;
2320 u32 timepassed_us;
2321 u64 bytes_perint;
2322 u8 itr_setting = ring_container->itr;
2323
2324 if (packets == 0)
2325 return;
2326
2327 /* simple throttlerate management
2328 * 0-10MB/s lowest (100000 ints/s)
2329 * 10-20MB/s low (20000 ints/s)
2330 * 20-1249MB/s bulk (8000 ints/s)
2331 */
2332 /* what was last interrupt timeslice? */
2333 timepassed_us = q_vector->itr >> 2;
2334 if (timepassed_us == 0)
2335 return;
2336
2337 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2338
2339 switch (itr_setting) {
2340 case lowest_latency:
2341 if (bytes_perint > 10)
2342 itr_setting = low_latency;
2343 break;
2344 case low_latency:
2345 if (bytes_perint > 20)
2346 itr_setting = bulk_latency;
2347 else if (bytes_perint <= 10)
2348 itr_setting = lowest_latency;
2349 break;
2350 case bulk_latency:
2351 if (bytes_perint <= 20)
2352 itr_setting = low_latency;
2353 break;
2354 }
2355
2356 /* clear work counters since we have the values we need */
2357 ring_container->total_bytes = 0;
2358 ring_container->total_packets = 0;
2359
2360 /* write updated itr to ring container */
2361 ring_container->itr = itr_setting;
2362 }
2363
2364 /**
2365 * ixgbe_write_eitr - write EITR register in hardware specific way
2366 * @q_vector: structure containing interrupt and ring information
2367 *
2368 * This function is made to be called by ethtool and by the driver
2369 * when it needs to update EITR registers at runtime. Hardware
2370 * specific quirks/differences are taken care of here.
2371 */
2372 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2373 {
2374 struct ixgbe_adapter *adapter = q_vector->adapter;
2375 struct ixgbe_hw *hw = &adapter->hw;
2376 int v_idx = q_vector->v_idx;
2377 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2378
2379 switch (adapter->hw.mac.type) {
2380 case ixgbe_mac_82598EB:
2381 /* must write high and low 16 bits to reset counter */
2382 itr_reg |= (itr_reg << 16);
2383 break;
2384 case ixgbe_mac_82599EB:
2385 case ixgbe_mac_X540:
2386 /*
2387 * set the WDIS bit to not clear the timer bits and cause an
2388 * immediate assertion of the interrupt
2389 */
2390 itr_reg |= IXGBE_EITR_CNT_WDIS;
2391 break;
2392 default:
2393 break;
2394 }
2395 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2396 }
2397
2398 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2399 {
2400 u32 new_itr = q_vector->itr;
2401 u8 current_itr;
2402
2403 ixgbe_update_itr(q_vector, &q_vector->tx);
2404 ixgbe_update_itr(q_vector, &q_vector->rx);
2405
2406 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2407
2408 switch (current_itr) {
2409 /* counts and packets in update_itr are dependent on these numbers */
2410 case lowest_latency:
2411 new_itr = IXGBE_100K_ITR;
2412 break;
2413 case low_latency:
2414 new_itr = IXGBE_20K_ITR;
2415 break;
2416 case bulk_latency:
2417 new_itr = IXGBE_8K_ITR;
2418 break;
2419 default:
2420 break;
2421 }
2422
2423 if (new_itr != q_vector->itr) {
2424 /* do an exponential smoothing */
2425 new_itr = (10 * new_itr * q_vector->itr) /
2426 ((9 * new_itr) + q_vector->itr);
2427
2428 /* save the algorithm value here */
2429 q_vector->itr = new_itr;
2430
2431 ixgbe_write_eitr(q_vector);
2432 }
2433 }
2434
2435 /**
2436 * ixgbe_check_overtemp_subtask - check for over temperature
2437 * @adapter: pointer to adapter
2438 **/
2439 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2440 {
2441 struct ixgbe_hw *hw = &adapter->hw;
2442 u32 eicr = adapter->interrupt_event;
2443
2444 if (test_bit(__IXGBE_DOWN, &adapter->state))
2445 return;
2446
2447 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2448 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2449 return;
2450
2451 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2452
2453 switch (hw->device_id) {
2454 case IXGBE_DEV_ID_82599_T3_LOM:
2455 /*
2456 * Since the warning interrupt is for both ports
2457 * we don't have to check if:
2458 * - This interrupt wasn't for our port.
2459 * - We may have missed the interrupt so always have to
2460 * check if we got a LSC
2461 */
2462 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2463 !(eicr & IXGBE_EICR_LSC))
2464 return;
2465
2466 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2467 u32 speed;
2468 bool link_up = false;
2469
2470 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2471
2472 if (link_up)
2473 return;
2474 }
2475
2476 /* Check if this is not due to overtemp */
2477 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2478 return;
2479
2480 break;
2481 default:
2482 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2483 return;
2484 break;
2485 }
2486 e_crit(drv,
2487 "Network adapter has been stopped because it has over heated. "
2488 "Restart the computer. If the problem persists, "
2489 "power off the system and replace the adapter\n");
2490
2491 adapter->interrupt_event = 0;
2492 }
2493
2494 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2495 {
2496 struct ixgbe_hw *hw = &adapter->hw;
2497
2498 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2499 (eicr & IXGBE_EICR_GPI_SDP1)) {
2500 e_crit(probe, "Fan has stopped, replace the adapter\n");
2501 /* write to clear the interrupt */
2502 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2503 }
2504 }
2505
2506 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2507 {
2508 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2509 return;
2510
2511 switch (adapter->hw.mac.type) {
2512 case ixgbe_mac_82599EB:
2513 /*
2514 * Need to check link state so complete overtemp check
2515 * on service task
2516 */
2517 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2518 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2519 adapter->interrupt_event = eicr;
2520 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2521 ixgbe_service_event_schedule(adapter);
2522 return;
2523 }
2524 return;
2525 case ixgbe_mac_X540:
2526 if (!(eicr & IXGBE_EICR_TS))
2527 return;
2528 break;
2529 default:
2530 return;
2531 }
2532
2533 e_crit(drv,
2534 "Network adapter has been stopped because it has over heated. "
2535 "Restart the computer. If the problem persists, "
2536 "power off the system and replace the adapter\n");
2537 }
2538
2539 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2540 {
2541 struct ixgbe_hw *hw = &adapter->hw;
2542
2543 if (eicr & IXGBE_EICR_GPI_SDP2) {
2544 /* Clear the interrupt */
2545 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2546 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2547 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2548 ixgbe_service_event_schedule(adapter);
2549 }
2550 }
2551
2552 if (eicr & IXGBE_EICR_GPI_SDP1) {
2553 /* Clear the interrupt */
2554 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2555 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2556 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2557 ixgbe_service_event_schedule(adapter);
2558 }
2559 }
2560 }
2561
2562 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2563 {
2564 struct ixgbe_hw *hw = &adapter->hw;
2565
2566 adapter->lsc_int++;
2567 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2568 adapter->link_check_timeout = jiffies;
2569 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2570 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2571 IXGBE_WRITE_FLUSH(hw);
2572 ixgbe_service_event_schedule(adapter);
2573 }
2574 }
2575
2576 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2577 u64 qmask)
2578 {
2579 u32 mask;
2580 struct ixgbe_hw *hw = &adapter->hw;
2581
2582 switch (hw->mac.type) {
2583 case ixgbe_mac_82598EB:
2584 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2585 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2586 break;
2587 case ixgbe_mac_82599EB:
2588 case ixgbe_mac_X540:
2589 mask = (qmask & 0xFFFFFFFF);
2590 if (mask)
2591 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2592 mask = (qmask >> 32);
2593 if (mask)
2594 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2595 break;
2596 default:
2597 break;
2598 }
2599 /* skip the flush */
2600 }
2601
2602 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2603 u64 qmask)
2604 {
2605 u32 mask;
2606 struct ixgbe_hw *hw = &adapter->hw;
2607
2608 switch (hw->mac.type) {
2609 case ixgbe_mac_82598EB:
2610 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2611 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2612 break;
2613 case ixgbe_mac_82599EB:
2614 case ixgbe_mac_X540:
2615 mask = (qmask & 0xFFFFFFFF);
2616 if (mask)
2617 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2618 mask = (qmask >> 32);
2619 if (mask)
2620 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2621 break;
2622 default:
2623 break;
2624 }
2625 /* skip the flush */
2626 }
2627
2628 /**
2629 * ixgbe_irq_enable - Enable default interrupt generation settings
2630 * @adapter: board private structure
2631 **/
2632 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2633 bool flush)
2634 {
2635 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2636
2637 /* don't reenable LSC while waiting for link */
2638 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2639 mask &= ~IXGBE_EIMS_LSC;
2640
2641 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2642 switch (adapter->hw.mac.type) {
2643 case ixgbe_mac_82599EB:
2644 mask |= IXGBE_EIMS_GPI_SDP0;
2645 break;
2646 case ixgbe_mac_X540:
2647 mask |= IXGBE_EIMS_TS;
2648 break;
2649 default:
2650 break;
2651 }
2652 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2653 mask |= IXGBE_EIMS_GPI_SDP1;
2654 switch (adapter->hw.mac.type) {
2655 case ixgbe_mac_82599EB:
2656 mask |= IXGBE_EIMS_GPI_SDP1;
2657 mask |= IXGBE_EIMS_GPI_SDP2;
2658 case ixgbe_mac_X540:
2659 mask |= IXGBE_EIMS_ECC;
2660 mask |= IXGBE_EIMS_MAILBOX;
2661 break;
2662 default:
2663 break;
2664 }
2665
2666 if (adapter->hw.mac.type == ixgbe_mac_X540)
2667 mask |= IXGBE_EIMS_TIMESYNC;
2668
2669 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2670 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2671 mask |= IXGBE_EIMS_FLOW_DIR;
2672
2673 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2674 if (queues)
2675 ixgbe_irq_enable_queues(adapter, ~0);
2676 if (flush)
2677 IXGBE_WRITE_FLUSH(&adapter->hw);
2678 }
2679
2680 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2681 {
2682 struct ixgbe_adapter *adapter = data;
2683 struct ixgbe_hw *hw = &adapter->hw;
2684 u32 eicr;
2685
2686 /*
2687 * Workaround for Silicon errata. Use clear-by-write instead
2688 * of clear-by-read. Reading with EICS will return the
2689 * interrupt causes without clearing, which later be done
2690 * with the write to EICR.
2691 */
2692 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2693
2694 /* The lower 16bits of the EICR register are for the queue interrupts
2695 * which should be masked here in order to not accidently clear them if
2696 * the bits are high when ixgbe_msix_other is called. There is a race
2697 * condition otherwise which results in possible performance loss
2698 * especially if the ixgbe_msix_other interrupt is triggering
2699 * consistently (as it would when PPS is turned on for the X540 device)
2700 */
2701 eicr &= 0xFFFF0000;
2702
2703 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2704
2705 if (eicr & IXGBE_EICR_LSC)
2706 ixgbe_check_lsc(adapter);
2707
2708 if (eicr & IXGBE_EICR_MAILBOX)
2709 ixgbe_msg_task(adapter);
2710
2711 switch (hw->mac.type) {
2712 case ixgbe_mac_82599EB:
2713 case ixgbe_mac_X540:
2714 if (eicr & IXGBE_EICR_ECC) {
2715 e_info(link, "Received ECC Err, initiating reset\n");
2716 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2717 ixgbe_service_event_schedule(adapter);
2718 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2719 }
2720 /* Handle Flow Director Full threshold interrupt */
2721 if (eicr & IXGBE_EICR_FLOW_DIR) {
2722 int reinit_count = 0;
2723 int i;
2724 for (i = 0; i < adapter->num_tx_queues; i++) {
2725 struct ixgbe_ring *ring = adapter->tx_ring[i];
2726 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2727 &ring->state))
2728 reinit_count++;
2729 }
2730 if (reinit_count) {
2731 /* no more flow director interrupts until after init */
2732 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2733 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2734 ixgbe_service_event_schedule(adapter);
2735 }
2736 }
2737 ixgbe_check_sfp_event(adapter, eicr);
2738 ixgbe_check_overtemp_event(adapter, eicr);
2739 break;
2740 default:
2741 break;
2742 }
2743
2744 ixgbe_check_fan_failure(adapter, eicr);
2745
2746 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2747 ixgbe_ptp_check_pps_event(adapter, eicr);
2748
2749 /* re-enable the original interrupt state, no lsc, no queues */
2750 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2751 ixgbe_irq_enable(adapter, false, false);
2752
2753 return IRQ_HANDLED;
2754 }
2755
2756 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2757 {
2758 struct ixgbe_q_vector *q_vector = data;
2759
2760 /* EIAM disabled interrupts (on this vector) for us */
2761
2762 if (q_vector->rx.ring || q_vector->tx.ring)
2763 napi_schedule(&q_vector->napi);
2764
2765 return IRQ_HANDLED;
2766 }
2767
2768 /**
2769 * ixgbe_poll - NAPI Rx polling callback
2770 * @napi: structure for representing this polling device
2771 * @budget: how many packets driver is allowed to clean
2772 *
2773 * This function is used for legacy and MSI, NAPI mode
2774 **/
2775 int ixgbe_poll(struct napi_struct *napi, int budget)
2776 {
2777 struct ixgbe_q_vector *q_vector =
2778 container_of(napi, struct ixgbe_q_vector, napi);
2779 struct ixgbe_adapter *adapter = q_vector->adapter;
2780 struct ixgbe_ring *ring;
2781 int per_ring_budget;
2782 bool clean_complete = true;
2783
2784 #ifdef CONFIG_IXGBE_DCA
2785 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2786 ixgbe_update_dca(q_vector);
2787 #endif
2788
2789 ixgbe_for_each_ring(ring, q_vector->tx)
2790 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2791
2792 if (!ixgbe_qv_lock_napi(q_vector))
2793 return budget;
2794
2795 /* attempt to distribute budget to each queue fairly, but don't allow
2796 * the budget to go below 1 because we'll exit polling */
2797 if (q_vector->rx.count > 1)
2798 per_ring_budget = max(budget/q_vector->rx.count, 1);
2799 else
2800 per_ring_budget = budget;
2801
2802 ixgbe_for_each_ring(ring, q_vector->rx)
2803 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2804 per_ring_budget) < per_ring_budget);
2805
2806 ixgbe_qv_unlock_napi(q_vector);
2807 /* If all work not completed, return budget and keep polling */
2808 if (!clean_complete)
2809 return budget;
2810
2811 /* all work done, exit the polling mode */
2812 napi_complete(napi);
2813 if (adapter->rx_itr_setting & 1)
2814 ixgbe_set_itr(q_vector);
2815 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2816 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2817
2818 return 0;
2819 }
2820
2821 /**
2822 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2823 * @adapter: board private structure
2824 *
2825 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2826 * interrupts from the kernel.
2827 **/
2828 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2829 {
2830 struct net_device *netdev = adapter->netdev;
2831 int vector, err;
2832 int ri = 0, ti = 0;
2833
2834 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2835 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2836 struct msix_entry *entry = &adapter->msix_entries[vector];
2837
2838 if (q_vector->tx.ring && q_vector->rx.ring) {
2839 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2840 "%s-%s-%d", netdev->name, "TxRx", ri++);
2841 ti++;
2842 } else if (q_vector->rx.ring) {
2843 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2844 "%s-%s-%d", netdev->name, "rx", ri++);
2845 } else if (q_vector->tx.ring) {
2846 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2847 "%s-%s-%d", netdev->name, "tx", ti++);
2848 } else {
2849 /* skip this unused q_vector */
2850 continue;
2851 }
2852 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2853 q_vector->name, q_vector);
2854 if (err) {
2855 e_err(probe, "request_irq failed for MSIX interrupt "
2856 "Error: %d\n", err);
2857 goto free_queue_irqs;
2858 }
2859 /* If Flow Director is enabled, set interrupt affinity */
2860 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2861 /* assign the mask for this irq */
2862 irq_set_affinity_hint(entry->vector,
2863 &q_vector->affinity_mask);
2864 }
2865 }
2866
2867 err = request_irq(adapter->msix_entries[vector].vector,
2868 ixgbe_msix_other, 0, netdev->name, adapter);
2869 if (err) {
2870 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2871 goto free_queue_irqs;
2872 }
2873
2874 return 0;
2875
2876 free_queue_irqs:
2877 while (vector) {
2878 vector--;
2879 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2880 NULL);
2881 free_irq(adapter->msix_entries[vector].vector,
2882 adapter->q_vector[vector]);
2883 }
2884 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2885 pci_disable_msix(adapter->pdev);
2886 kfree(adapter->msix_entries);
2887 adapter->msix_entries = NULL;
2888 return err;
2889 }
2890
2891 /**
2892 * ixgbe_intr - legacy mode Interrupt Handler
2893 * @irq: interrupt number
2894 * @data: pointer to a network interface device structure
2895 **/
2896 static irqreturn_t ixgbe_intr(int irq, void *data)
2897 {
2898 struct ixgbe_adapter *adapter = data;
2899 struct ixgbe_hw *hw = &adapter->hw;
2900 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2901 u32 eicr;
2902
2903 /*
2904 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2905 * before the read of EICR.
2906 */
2907 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2908
2909 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2910 * therefore no explicit interrupt disable is necessary */
2911 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2912 if (!eicr) {
2913 /*
2914 * shared interrupt alert!
2915 * make sure interrupts are enabled because the read will
2916 * have disabled interrupts due to EIAM
2917 * finish the workaround of silicon errata on 82598. Unmask
2918 * the interrupt that we masked before the EICR read.
2919 */
2920 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2921 ixgbe_irq_enable(adapter, true, true);
2922 return IRQ_NONE; /* Not our interrupt */
2923 }
2924
2925 if (eicr & IXGBE_EICR_LSC)
2926 ixgbe_check_lsc(adapter);
2927
2928 switch (hw->mac.type) {
2929 case ixgbe_mac_82599EB:
2930 ixgbe_check_sfp_event(adapter, eicr);
2931 /* Fall through */
2932 case ixgbe_mac_X540:
2933 if (eicr & IXGBE_EICR_ECC) {
2934 e_info(link, "Received ECC Err, initiating reset\n");
2935 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2936 ixgbe_service_event_schedule(adapter);
2937 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2938 }
2939 ixgbe_check_overtemp_event(adapter, eicr);
2940 break;
2941 default:
2942 break;
2943 }
2944
2945 ixgbe_check_fan_failure(adapter, eicr);
2946 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2947 ixgbe_ptp_check_pps_event(adapter, eicr);
2948
2949 /* would disable interrupts here but EIAM disabled it */
2950 napi_schedule(&q_vector->napi);
2951
2952 /*
2953 * re-enable link(maybe) and non-queue interrupts, no flush.
2954 * ixgbe_poll will re-enable the queue interrupts
2955 */
2956 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2957 ixgbe_irq_enable(adapter, false, false);
2958
2959 return IRQ_HANDLED;
2960 }
2961
2962 /**
2963 * ixgbe_request_irq - initialize interrupts
2964 * @adapter: board private structure
2965 *
2966 * Attempts to configure interrupts using the best available
2967 * capabilities of the hardware and kernel.
2968 **/
2969 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2970 {
2971 struct net_device *netdev = adapter->netdev;
2972 int err;
2973
2974 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2975 err = ixgbe_request_msix_irqs(adapter);
2976 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2977 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2978 netdev->name, adapter);
2979 else
2980 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2981 netdev->name, adapter);
2982
2983 if (err)
2984 e_err(probe, "request_irq failed, Error %d\n", err);
2985
2986 return err;
2987 }
2988
2989 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2990 {
2991 int vector;
2992
2993 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2994 free_irq(adapter->pdev->irq, adapter);
2995 return;
2996 }
2997
2998 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2999 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3000 struct msix_entry *entry = &adapter->msix_entries[vector];
3001
3002 /* free only the irqs that were actually requested */
3003 if (!q_vector->rx.ring && !q_vector->tx.ring)
3004 continue;
3005
3006 /* clear the affinity_mask in the IRQ descriptor */
3007 irq_set_affinity_hint(entry->vector, NULL);
3008
3009 free_irq(entry->vector, q_vector);
3010 }
3011
3012 free_irq(adapter->msix_entries[vector++].vector, adapter);
3013 }
3014
3015 /**
3016 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3017 * @adapter: board private structure
3018 **/
3019 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3020 {
3021 switch (adapter->hw.mac.type) {
3022 case ixgbe_mac_82598EB:
3023 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
3024 break;
3025 case ixgbe_mac_82599EB:
3026 case ixgbe_mac_X540:
3027 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3028 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
3029 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
3030 break;
3031 default:
3032 break;
3033 }
3034 IXGBE_WRITE_FLUSH(&adapter->hw);
3035 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3036 int vector;
3037
3038 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3039 synchronize_irq(adapter->msix_entries[vector].vector);
3040
3041 synchronize_irq(adapter->msix_entries[vector++].vector);
3042 } else {
3043 synchronize_irq(adapter->pdev->irq);
3044 }
3045 }
3046
3047 /**
3048 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3049 *
3050 **/
3051 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3052 {
3053 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3054
3055 ixgbe_write_eitr(q_vector);
3056
3057 ixgbe_set_ivar(adapter, 0, 0, 0);
3058 ixgbe_set_ivar(adapter, 1, 0, 0);
3059
3060 e_info(hw, "Legacy interrupt IVAR setup done\n");
3061 }
3062
3063 /**
3064 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3065 * @adapter: board private structure
3066 * @ring: structure containing ring specific data
3067 *
3068 * Configure the Tx descriptor ring after a reset.
3069 **/
3070 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3071 struct ixgbe_ring *ring)
3072 {
3073 struct ixgbe_hw *hw = &adapter->hw;
3074 u64 tdba = ring->dma;
3075 int wait_loop = 10;
3076 u32 txdctl = IXGBE_TXDCTL_ENABLE;
3077 u8 reg_idx = ring->reg_idx;
3078
3079 /* disable queue to avoid issues while updating state */
3080 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
3081 IXGBE_WRITE_FLUSH(hw);
3082
3083 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
3084 (tdba & DMA_BIT_MASK(32)));
3085 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3086 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3087 ring->count * sizeof(union ixgbe_adv_tx_desc));
3088 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3089 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
3090 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
3091
3092 /*
3093 * set WTHRESH to encourage burst writeback, it should not be set
3094 * higher than 1 when:
3095 * - ITR is 0 as it could cause false TX hangs
3096 * - ITR is set to > 100k int/sec and BQL is enabled
3097 *
3098 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3099 * to or less than the number of on chip descriptors, which is
3100 * currently 40.
3101 */
3102 #if IS_ENABLED(CONFIG_BQL)
3103 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3104 #else
3105 if (!ring->q_vector || (ring->q_vector->itr < 8))
3106 #endif
3107 txdctl |= (1 << 16); /* WTHRESH = 1 */
3108 else
3109 txdctl |= (8 << 16); /* WTHRESH = 8 */
3110
3111 /*
3112 * Setting PTHRESH to 32 both improves performance
3113 * and avoids a TX hang with DFP enabled
3114 */
3115 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3116 32; /* PTHRESH = 32 */
3117
3118 /* reinitialize flowdirector state */
3119 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3120 ring->atr_sample_rate = adapter->atr_sample_rate;
3121 ring->atr_count = 0;
3122 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3123 } else {
3124 ring->atr_sample_rate = 0;
3125 }
3126
3127 /* initialize XPS */
3128 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3129 struct ixgbe_q_vector *q_vector = ring->q_vector;
3130
3131 if (q_vector)
3132 netif_set_xps_queue(ring->netdev,
3133 &q_vector->affinity_mask,
3134 ring->queue_index);
3135 }
3136
3137 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3138
3139 /* enable queue */
3140 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3141
3142 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3143 if (hw->mac.type == ixgbe_mac_82598EB &&
3144 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3145 return;
3146
3147 /* poll to verify queue is enabled */
3148 do {
3149 usleep_range(1000, 2000);
3150 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3151 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3152 if (!wait_loop)
3153 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
3154 }
3155
3156 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3157 {
3158 struct ixgbe_hw *hw = &adapter->hw;
3159 u32 rttdcs, mtqc;
3160 u8 tcs = netdev_get_num_tc(adapter->netdev);
3161
3162 if (hw->mac.type == ixgbe_mac_82598EB)
3163 return;
3164
3165 /* disable the arbiter while setting MTQC */
3166 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3167 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3168 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3169
3170 /* set transmit pool layout */
3171 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3172 mtqc = IXGBE_MTQC_VT_ENA;
3173 if (tcs > 4)
3174 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3175 else if (tcs > 1)
3176 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3177 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3178 mtqc |= IXGBE_MTQC_32VF;
3179 else
3180 mtqc |= IXGBE_MTQC_64VF;
3181 } else {
3182 if (tcs > 4)
3183 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3184 else if (tcs > 1)
3185 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3186 else
3187 mtqc = IXGBE_MTQC_64Q_1PB;
3188 }
3189
3190 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3191
3192 /* Enable Security TX Buffer IFG for multiple pb */
3193 if (tcs) {
3194 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3195 sectx |= IXGBE_SECTX_DCB;
3196 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3197 }
3198
3199 /* re-enable the arbiter */
3200 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3201 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3202 }
3203
3204 /**
3205 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3206 * @adapter: board private structure
3207 *
3208 * Configure the Tx unit of the MAC after a reset.
3209 **/
3210 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3211 {
3212 struct ixgbe_hw *hw = &adapter->hw;
3213 u32 dmatxctl;
3214 u32 i;
3215
3216 ixgbe_setup_mtqc(adapter);
3217
3218 if (hw->mac.type != ixgbe_mac_82598EB) {
3219 /* DMATXCTL.EN must be before Tx queues are enabled */
3220 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3221 dmatxctl |= IXGBE_DMATXCTL_TE;
3222 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3223 }
3224
3225 /* Setup the HW Tx Head and Tail descriptor pointers */
3226 for (i = 0; i < adapter->num_tx_queues; i++)
3227 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3228 }
3229
3230 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3231 struct ixgbe_ring *ring)
3232 {
3233 struct ixgbe_hw *hw = &adapter->hw;
3234 u8 reg_idx = ring->reg_idx;
3235 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3236
3237 srrctl |= IXGBE_SRRCTL_DROP_EN;
3238
3239 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3240 }
3241
3242 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3243 struct ixgbe_ring *ring)
3244 {
3245 struct ixgbe_hw *hw = &adapter->hw;
3246 u8 reg_idx = ring->reg_idx;
3247 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3248
3249 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3250
3251 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3252 }
3253
3254 #ifdef CONFIG_IXGBE_DCB
3255 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3256 #else
3257 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3258 #endif
3259 {
3260 int i;
3261 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3262
3263 if (adapter->ixgbe_ieee_pfc)
3264 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3265
3266 /*
3267 * We should set the drop enable bit if:
3268 * SR-IOV is enabled
3269 * or
3270 * Number of Rx queues > 1 and flow control is disabled
3271 *
3272 * This allows us to avoid head of line blocking for security
3273 * and performance reasons.
3274 */
3275 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3276 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3277 for (i = 0; i < adapter->num_rx_queues; i++)
3278 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3279 } else {
3280 for (i = 0; i < adapter->num_rx_queues; i++)
3281 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3282 }
3283 }
3284
3285 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3286
3287 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3288 struct ixgbe_ring *rx_ring)
3289 {
3290 struct ixgbe_hw *hw = &adapter->hw;
3291 u32 srrctl;
3292 u8 reg_idx = rx_ring->reg_idx;
3293
3294 if (hw->mac.type == ixgbe_mac_82598EB) {
3295 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3296
3297 /*
3298 * if VMDq is not active we must program one srrctl register
3299 * per RSS queue since we have enabled RDRXCTL.MVMEN
3300 */
3301 reg_idx &= mask;
3302 }
3303
3304 /* configure header buffer length, needed for RSC */
3305 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3306
3307 /* configure the packet buffer length */
3308 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3309
3310 /* configure descriptor type */
3311 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3312
3313 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3314 }
3315
3316 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3317 {
3318 struct ixgbe_hw *hw = &adapter->hw;
3319 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
3320 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3321 0x6A3E67EA, 0x14364D17, 0x3BED200D};
3322 u32 mrqc = 0, reta = 0;
3323 u32 rxcsum;
3324 int i, j;
3325 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3326
3327 /*
3328 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3329 * make full use of any rings they may have. We will use the
3330 * PSRTYPE register to control how many rings we use within the PF.
3331 */
3332 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3333 rss_i = 2;
3334
3335 /* Fill out hash function seeds */
3336 for (i = 0; i < 10; i++)
3337 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3338
3339 /* Fill out redirection table */
3340 for (i = 0, j = 0; i < 128; i++, j++) {
3341 if (j == rss_i)
3342 j = 0;
3343 /* reta = 4-byte sliding window of
3344 * 0x00..(indices-1)(indices-1)00..etc. */
3345 reta = (reta << 8) | (j * 0x11);
3346 if ((i & 3) == 3)
3347 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3348 }
3349
3350 /* Disable indicating checksum in descriptor, enables RSS hash */
3351 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3352 rxcsum |= IXGBE_RXCSUM_PCSD;
3353 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3354
3355 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3356 if (adapter->ring_feature[RING_F_RSS].mask)
3357 mrqc = IXGBE_MRQC_RSSEN;
3358 } else {
3359 u8 tcs = netdev_get_num_tc(adapter->netdev);
3360
3361 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3362 if (tcs > 4)
3363 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3364 else if (tcs > 1)
3365 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3366 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3367 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3368 else
3369 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3370 } else {
3371 if (tcs > 4)
3372 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3373 else if (tcs > 1)
3374 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3375 else
3376 mrqc = IXGBE_MRQC_RSSEN;
3377 }
3378 }
3379
3380 /* Perform hash on these packet types */
3381 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3382 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3383 IXGBE_MRQC_RSS_FIELD_IPV6 |
3384 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3385
3386 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3387 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3388 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3389 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3390
3391 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3392 }
3393
3394 /**
3395 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3396 * @adapter: address of board private structure
3397 * @index: index of ring to set
3398 **/
3399 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3400 struct ixgbe_ring *ring)
3401 {
3402 struct ixgbe_hw *hw = &adapter->hw;
3403 u32 rscctrl;
3404 u8 reg_idx = ring->reg_idx;
3405
3406 if (!ring_is_rsc_enabled(ring))
3407 return;
3408
3409 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3410 rscctrl |= IXGBE_RSCCTL_RSCEN;
3411 /*
3412 * we must limit the number of descriptors so that the
3413 * total size of max desc * buf_len is not greater
3414 * than 65536
3415 */
3416 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3417 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3418 }
3419
3420 #define IXGBE_MAX_RX_DESC_POLL 10
3421 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3422 struct ixgbe_ring *ring)
3423 {
3424 struct ixgbe_hw *hw = &adapter->hw;
3425 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3426 u32 rxdctl;
3427 u8 reg_idx = ring->reg_idx;
3428
3429 if (ixgbe_removed(hw->hw_addr))
3430 return;
3431 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3432 if (hw->mac.type == ixgbe_mac_82598EB &&
3433 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3434 return;
3435
3436 do {
3437 usleep_range(1000, 2000);
3438 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3439 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3440
3441 if (!wait_loop) {
3442 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3443 "the polling period\n", reg_idx);
3444 }
3445 }
3446
3447 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3448 struct ixgbe_ring *ring)
3449 {
3450 struct ixgbe_hw *hw = &adapter->hw;
3451 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3452 u32 rxdctl;
3453 u8 reg_idx = ring->reg_idx;
3454
3455 if (ixgbe_removed(hw->hw_addr))
3456 return;
3457 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3458 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3459
3460 /* write value back with RXDCTL.ENABLE bit cleared */
3461 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3462
3463 if (hw->mac.type == ixgbe_mac_82598EB &&
3464 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3465 return;
3466
3467 /* the hardware may take up to 100us to really disable the rx queue */
3468 do {
3469 udelay(10);
3470 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3471 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3472
3473 if (!wait_loop) {
3474 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3475 "the polling period\n", reg_idx);
3476 }
3477 }
3478
3479 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3480 struct ixgbe_ring *ring)
3481 {
3482 struct ixgbe_hw *hw = &adapter->hw;
3483 u64 rdba = ring->dma;
3484 u32 rxdctl;
3485 u8 reg_idx = ring->reg_idx;
3486
3487 /* disable queue to avoid issues while updating state */
3488 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3489 ixgbe_disable_rx_queue(adapter, ring);
3490
3491 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3492 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3493 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3494 ring->count * sizeof(union ixgbe_adv_rx_desc));
3495 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3496 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3497 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
3498
3499 ixgbe_configure_srrctl(adapter, ring);
3500 ixgbe_configure_rscctl(adapter, ring);
3501
3502 if (hw->mac.type == ixgbe_mac_82598EB) {
3503 /*
3504 * enable cache line friendly hardware writes:
3505 * PTHRESH=32 descriptors (half the internal cache),
3506 * this also removes ugly rx_no_buffer_count increment
3507 * HTHRESH=4 descriptors (to minimize latency on fetch)
3508 * WTHRESH=8 burst writeback up to two cache lines
3509 */
3510 rxdctl &= ~0x3FFFFF;
3511 rxdctl |= 0x080420;
3512 }
3513
3514 /* enable receive descriptor ring */
3515 rxdctl |= IXGBE_RXDCTL_ENABLE;
3516 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3517
3518 ixgbe_rx_desc_queue_enable(adapter, ring);
3519 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3520 }
3521
3522 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3523 {
3524 struct ixgbe_hw *hw = &adapter->hw;
3525 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3526 u16 pool;
3527
3528 /* PSRTYPE must be initialized in non 82598 adapters */
3529 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3530 IXGBE_PSRTYPE_UDPHDR |
3531 IXGBE_PSRTYPE_IPV4HDR |
3532 IXGBE_PSRTYPE_L2HDR |
3533 IXGBE_PSRTYPE_IPV6HDR;
3534
3535 if (hw->mac.type == ixgbe_mac_82598EB)
3536 return;
3537
3538 if (rss_i > 3)
3539 psrtype |= 2 << 29;
3540 else if (rss_i > 1)
3541 psrtype |= 1 << 29;
3542
3543 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3544 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
3545 }
3546
3547 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3548 {
3549 struct ixgbe_hw *hw = &adapter->hw;
3550 u32 reg_offset, vf_shift;
3551 u32 gcr_ext, vmdctl;
3552 int i;
3553
3554 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3555 return;
3556
3557 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3558 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3559 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3560 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3561 vmdctl |= IXGBE_VT_CTL_REPLEN;
3562 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3563
3564 vf_shift = VMDQ_P(0) % 32;
3565 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3566
3567 /* Enable only the PF's pool for Tx/Rx */
3568 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3569 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3570 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3571 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3572 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3573 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3574
3575 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3576 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3577
3578 /*
3579 * Set up VF register offsets for selected VT Mode,
3580 * i.e. 32 or 64 VFs for SR-IOV
3581 */
3582 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3583 case IXGBE_82599_VMDQ_8Q_MASK:
3584 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3585 break;
3586 case IXGBE_82599_VMDQ_4Q_MASK:
3587 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3588 break;
3589 default:
3590 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3591 break;
3592 }
3593
3594 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3595
3596
3597 /* Enable MAC Anti-Spoofing */
3598 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3599 adapter->num_vfs);
3600 /* For VFs that have spoof checking turned off */
3601 for (i = 0; i < adapter->num_vfs; i++) {
3602 if (!adapter->vfinfo[i].spoofchk_enabled)
3603 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3604 }
3605 }
3606
3607 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3608 {
3609 struct ixgbe_hw *hw = &adapter->hw;
3610 struct net_device *netdev = adapter->netdev;
3611 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3612 struct ixgbe_ring *rx_ring;
3613 int i;
3614 u32 mhadd, hlreg0;
3615
3616 #ifdef IXGBE_FCOE
3617 /* adjust max frame to be able to do baby jumbo for FCoE */
3618 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3619 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3620 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3621
3622 #endif /* IXGBE_FCOE */
3623
3624 /* adjust max frame to be at least the size of a standard frame */
3625 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3626 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3627
3628 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3629 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3630 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3631 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3632
3633 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3634 }
3635
3636 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3637 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3638 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3639 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3640
3641 /*
3642 * Setup the HW Rx Head and Tail Descriptor Pointers and
3643 * the Base and Length of the Rx Descriptor Ring
3644 */
3645 for (i = 0; i < adapter->num_rx_queues; i++) {
3646 rx_ring = adapter->rx_ring[i];
3647 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3648 set_ring_rsc_enabled(rx_ring);
3649 else
3650 clear_ring_rsc_enabled(rx_ring);
3651 }
3652 }
3653
3654 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3655 {
3656 struct ixgbe_hw *hw = &adapter->hw;
3657 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3658
3659 switch (hw->mac.type) {
3660 case ixgbe_mac_82598EB:
3661 /*
3662 * For VMDq support of different descriptor types or
3663 * buffer sizes through the use of multiple SRRCTL
3664 * registers, RDRXCTL.MVMEN must be set to 1
3665 *
3666 * also, the manual doesn't mention it clearly but DCA hints
3667 * will only use queue 0's tags unless this bit is set. Side
3668 * effects of setting this bit are only that SRRCTL must be
3669 * fully programmed [0..15]
3670 */
3671 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3672 break;
3673 case ixgbe_mac_82599EB:
3674 case ixgbe_mac_X540:
3675 /* Disable RSC for ACK packets */
3676 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3677 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3678 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3679 /* hardware requires some bits to be set by default */
3680 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3681 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3682 break;
3683 default:
3684 /* We should do nothing since we don't know this hardware */
3685 return;
3686 }
3687
3688 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3689 }
3690
3691 /**
3692 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3693 * @adapter: board private structure
3694 *
3695 * Configure the Rx unit of the MAC after a reset.
3696 **/
3697 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3698 {
3699 struct ixgbe_hw *hw = &adapter->hw;
3700 int i;
3701 u32 rxctrl, rfctl;
3702
3703 /* disable receives while setting up the descriptors */
3704 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3705 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3706
3707 ixgbe_setup_psrtype(adapter);
3708 ixgbe_setup_rdrxctl(adapter);
3709
3710 /* RSC Setup */
3711 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3712 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3713 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3714 rfctl |= IXGBE_RFCTL_RSC_DIS;
3715 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3716
3717 /* Program registers for the distribution of queues */
3718 ixgbe_setup_mrqc(adapter);
3719
3720 /* set_rx_buffer_len must be called before ring initialization */
3721 ixgbe_set_rx_buffer_len(adapter);
3722
3723 /*
3724 * Setup the HW Rx Head and Tail Descriptor Pointers and
3725 * the Base and Length of the Rx Descriptor Ring
3726 */
3727 for (i = 0; i < adapter->num_rx_queues; i++)
3728 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3729
3730 /* disable drop enable for 82598 parts */
3731 if (hw->mac.type == ixgbe_mac_82598EB)
3732 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3733
3734 /* enable all receives */
3735 rxctrl |= IXGBE_RXCTRL_RXEN;
3736 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3737 }
3738
3739 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3740 __be16 proto, u16 vid)
3741 {
3742 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3743 struct ixgbe_hw *hw = &adapter->hw;
3744
3745 /* add VID to filter table */
3746 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3747 set_bit(vid, adapter->active_vlans);
3748
3749 return 0;
3750 }
3751
3752 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3753 __be16 proto, u16 vid)
3754 {
3755 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3756 struct ixgbe_hw *hw = &adapter->hw;
3757
3758 /* remove VID from filter table */
3759 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3760 clear_bit(vid, adapter->active_vlans);
3761
3762 return 0;
3763 }
3764
3765 /**
3766 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3767 * @adapter: driver data
3768 */
3769 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3770 {
3771 struct ixgbe_hw *hw = &adapter->hw;
3772 u32 vlnctrl;
3773 int i, j;
3774
3775 switch (hw->mac.type) {
3776 case ixgbe_mac_82598EB:
3777 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3778 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3779 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3780 break;
3781 case ixgbe_mac_82599EB:
3782 case ixgbe_mac_X540:
3783 for (i = 0; i < adapter->num_rx_queues; i++) {
3784 struct ixgbe_ring *ring = adapter->rx_ring[i];
3785
3786 if (ring->l2_accel_priv)
3787 continue;
3788 j = ring->reg_idx;
3789 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3790 vlnctrl &= ~IXGBE_RXDCTL_VME;
3791 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3792 }
3793 break;
3794 default:
3795 break;
3796 }
3797 }
3798
3799 /**
3800 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3801 * @adapter: driver data
3802 */
3803 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3804 {
3805 struct ixgbe_hw *hw = &adapter->hw;
3806 u32 vlnctrl;
3807 int i, j;
3808
3809 switch (hw->mac.type) {
3810 case ixgbe_mac_82598EB:
3811 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3812 vlnctrl |= IXGBE_VLNCTRL_VME;
3813 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3814 break;
3815 case ixgbe_mac_82599EB:
3816 case ixgbe_mac_X540:
3817 for (i = 0; i < adapter->num_rx_queues; i++) {
3818 struct ixgbe_ring *ring = adapter->rx_ring[i];
3819
3820 if (ring->l2_accel_priv)
3821 continue;
3822 j = ring->reg_idx;
3823 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3824 vlnctrl |= IXGBE_RXDCTL_VME;
3825 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3826 }
3827 break;
3828 default:
3829 break;
3830 }
3831 }
3832
3833 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3834 {
3835 u16 vid;
3836
3837 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
3838
3839 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3840 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
3841 }
3842
3843 /**
3844 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
3845 * @netdev: network interface device structure
3846 *
3847 * Writes multicast address list to the MTA hash table.
3848 * Returns: -ENOMEM on failure
3849 * 0 on no addresses written
3850 * X on writing X addresses to MTA
3851 **/
3852 static int ixgbe_write_mc_addr_list(struct net_device *netdev)
3853 {
3854 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3855 struct ixgbe_hw *hw = &adapter->hw;
3856
3857 if (!netif_running(netdev))
3858 return 0;
3859
3860 if (hw->mac.ops.update_mc_addr_list)
3861 hw->mac.ops.update_mc_addr_list(hw, netdev);
3862 else
3863 return -ENOMEM;
3864
3865 #ifdef CONFIG_PCI_IOV
3866 ixgbe_restore_vf_multicasts(adapter);
3867 #endif
3868
3869 return netdev_mc_count(netdev);
3870 }
3871
3872 #ifdef CONFIG_PCI_IOV
3873 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
3874 {
3875 struct ixgbe_hw *hw = &adapter->hw;
3876 int i;
3877 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3878 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3879 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
3880 adapter->mac_table[i].queue,
3881 IXGBE_RAH_AV);
3882 else
3883 hw->mac.ops.clear_rar(hw, i);
3884
3885 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED);
3886 }
3887 }
3888 #endif
3889
3890 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
3891 {
3892 struct ixgbe_hw *hw = &adapter->hw;
3893 int i;
3894 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3895 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
3896 if (adapter->mac_table[i].state &
3897 IXGBE_MAC_STATE_IN_USE)
3898 hw->mac.ops.set_rar(hw, i,
3899 adapter->mac_table[i].addr,
3900 adapter->mac_table[i].queue,
3901 IXGBE_RAH_AV);
3902 else
3903 hw->mac.ops.clear_rar(hw, i);
3904
3905 adapter->mac_table[i].state &=
3906 ~(IXGBE_MAC_STATE_MODIFIED);
3907 }
3908 }
3909 }
3910
3911 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
3912 {
3913 int i;
3914 struct ixgbe_hw *hw = &adapter->hw;
3915
3916 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3917 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3918 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
3919 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
3920 adapter->mac_table[i].queue = 0;
3921 }
3922 ixgbe_sync_mac_table(adapter);
3923 }
3924
3925 static int ixgbe_available_rars(struct ixgbe_adapter *adapter)
3926 {
3927 struct ixgbe_hw *hw = &adapter->hw;
3928 int i, count = 0;
3929
3930 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3931 if (adapter->mac_table[i].state == 0)
3932 count++;
3933 }
3934 return count;
3935 }
3936
3937 /* this function destroys the first RAR entry */
3938 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter,
3939 u8 *addr)
3940 {
3941 struct ixgbe_hw *hw = &adapter->hw;
3942
3943 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN);
3944 adapter->mac_table[0].queue = VMDQ_P(0);
3945 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
3946 IXGBE_MAC_STATE_IN_USE);
3947 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
3948 adapter->mac_table[0].queue,
3949 IXGBE_RAH_AV);
3950 }
3951
3952 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3953 {
3954 struct ixgbe_hw *hw = &adapter->hw;
3955 int i;
3956
3957 if (is_zero_ether_addr(addr))
3958 return -EINVAL;
3959
3960 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3961 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3962 continue;
3963 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
3964 IXGBE_MAC_STATE_IN_USE);
3965 ether_addr_copy(adapter->mac_table[i].addr, addr);
3966 adapter->mac_table[i].queue = queue;
3967 ixgbe_sync_mac_table(adapter);
3968 return i;
3969 }
3970 return -ENOMEM;
3971 }
3972
3973 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3974 {
3975 /* search table for addr, if found, set to 0 and sync */
3976 int i;
3977 struct ixgbe_hw *hw = &adapter->hw;
3978
3979 if (is_zero_ether_addr(addr))
3980 return -EINVAL;
3981
3982 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3983 if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
3984 adapter->mac_table[i].queue == queue) {
3985 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3986 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
3987 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
3988 adapter->mac_table[i].queue = 0;
3989 ixgbe_sync_mac_table(adapter);
3990 return 0;
3991 }
3992 }
3993 return -ENOMEM;
3994 }
3995 /**
3996 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3997 * @netdev: network interface device structure
3998 *
3999 * Writes unicast address list to the RAR table.
4000 * Returns: -ENOMEM on failure/insufficient address space
4001 * 0 on no addresses written
4002 * X on writing X addresses to the RAR table
4003 **/
4004 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
4005 {
4006 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4007 int count = 0;
4008
4009 /* return ENOMEM indicating insufficient memory for addresses */
4010 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
4011 return -ENOMEM;
4012
4013 if (!netdev_uc_empty(netdev)) {
4014 struct netdev_hw_addr *ha;
4015 netdev_for_each_uc_addr(ha, netdev) {
4016 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4017 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
4018 count++;
4019 }
4020 }
4021 return count;
4022 }
4023
4024 /**
4025 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
4026 * @netdev: network interface device structure
4027 *
4028 * The set_rx_method entry point is called whenever the unicast/multicast
4029 * address list or the network interface flags are updated. This routine is
4030 * responsible for configuring the hardware for proper unicast, multicast and
4031 * promiscuous mode.
4032 **/
4033 void ixgbe_set_rx_mode(struct net_device *netdev)
4034 {
4035 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4036 struct ixgbe_hw *hw = &adapter->hw;
4037 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
4038 u32 vlnctrl;
4039 int count;
4040
4041 /* Check for Promiscuous and All Multicast modes */
4042 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4043 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4044
4045 /* set all bits that we expect to always be set */
4046 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
4047 fctrl |= IXGBE_FCTRL_BAM;
4048 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4049 fctrl |= IXGBE_FCTRL_PMCF;
4050
4051 /* clear the bits we are changing the status of */
4052 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4053 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4054 if (netdev->flags & IFF_PROMISC) {
4055 hw->addr_ctrl.user_set_promisc = true;
4056 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4057 vmolr |= IXGBE_VMOLR_MPE;
4058 /* Only disable hardware filter vlans in promiscuous mode
4059 * if SR-IOV and VMDQ are disabled - otherwise ensure
4060 * that hardware VLAN filters remain enabled.
4061 */
4062 if (!(adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
4063 IXGBE_FLAG_SRIOV_ENABLED)))
4064 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4065 } else {
4066 if (netdev->flags & IFF_ALLMULTI) {
4067 fctrl |= IXGBE_FCTRL_MPE;
4068 vmolr |= IXGBE_VMOLR_MPE;
4069 }
4070 vlnctrl |= IXGBE_VLNCTRL_VFE;
4071 hw->addr_ctrl.user_set_promisc = false;
4072 }
4073
4074 /*
4075 * Write addresses to available RAR registers, if there is not
4076 * sufficient space to store all the addresses then enable
4077 * unicast promiscuous mode
4078 */
4079 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0));
4080 if (count < 0) {
4081 fctrl |= IXGBE_FCTRL_UPE;
4082 vmolr |= IXGBE_VMOLR_ROPE;
4083 }
4084
4085 /* Write addresses to the MTA, if the attempt fails
4086 * then we should just turn on promiscuous mode so
4087 * that we can at least receive multicast traffic
4088 */
4089 count = ixgbe_write_mc_addr_list(netdev);
4090 if (count < 0) {
4091 fctrl |= IXGBE_FCTRL_MPE;
4092 vmolr |= IXGBE_VMOLR_MPE;
4093 } else if (count) {
4094 vmolr |= IXGBE_VMOLR_ROMPE;
4095 }
4096
4097 if (hw->mac.type != ixgbe_mac_82598EB) {
4098 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
4099 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4100 IXGBE_VMOLR_ROPE);
4101 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
4102 }
4103
4104 /* This is useful for sniffing bad packets. */
4105 if (adapter->netdev->features & NETIF_F_RXALL) {
4106 /* UPE and MPE will be handled by normal PROMISC logic
4107 * in e1000e_set_rx_mode */
4108 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4109 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4110 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4111
4112 fctrl &= ~(IXGBE_FCTRL_DPF);
4113 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4114 }
4115
4116 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4117 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4118
4119 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
4120 ixgbe_vlan_strip_enable(adapter);
4121 else
4122 ixgbe_vlan_strip_disable(adapter);
4123 }
4124
4125 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4126 {
4127 int q_idx;
4128
4129 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4130 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
4131 napi_enable(&adapter->q_vector[q_idx]->napi);
4132 }
4133 }
4134
4135 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4136 {
4137 int q_idx;
4138
4139 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4140 napi_disable(&adapter->q_vector[q_idx]->napi);
4141 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
4142 pr_info("QV %d locked\n", q_idx);
4143 usleep_range(1000, 20000);
4144 }
4145 }
4146 }
4147
4148 #ifdef CONFIG_IXGBE_DCB
4149 /**
4150 * ixgbe_configure_dcb - Configure DCB hardware
4151 * @adapter: ixgbe adapter struct
4152 *
4153 * This is called by the driver on open to configure the DCB hardware.
4154 * This is also called by the gennetlink interface when reconfiguring
4155 * the DCB state.
4156 */
4157 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4158 {
4159 struct ixgbe_hw *hw = &adapter->hw;
4160 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4161
4162 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4163 if (hw->mac.type == ixgbe_mac_82598EB)
4164 netif_set_gso_max_size(adapter->netdev, 65536);
4165 return;
4166 }
4167
4168 if (hw->mac.type == ixgbe_mac_82598EB)
4169 netif_set_gso_max_size(adapter->netdev, 32768);
4170
4171 #ifdef IXGBE_FCOE
4172 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4173 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
4174 #endif
4175
4176 /* reconfigure the hardware */
4177 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
4178 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4179 DCB_TX_CONFIG);
4180 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4181 DCB_RX_CONFIG);
4182 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
4183 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4184 ixgbe_dcb_hw_ets(&adapter->hw,
4185 adapter->ixgbe_ieee_ets,
4186 max_frame);
4187 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4188 adapter->ixgbe_ieee_pfc->pfc_en,
4189 adapter->ixgbe_ieee_ets->prio_tc);
4190 }
4191
4192 /* Enable RSS Hash per TC */
4193 if (hw->mac.type != ixgbe_mac_82598EB) {
4194 u32 msb = 0;
4195 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
4196
4197 while (rss_i) {
4198 msb++;
4199 rss_i >>= 1;
4200 }
4201
4202 /* write msb to all 8 TCs in one write */
4203 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
4204 }
4205 }
4206 #endif
4207
4208 /* Additional bittime to account for IXGBE framing */
4209 #define IXGBE_ETH_FRAMING 20
4210
4211 /**
4212 * ixgbe_hpbthresh - calculate high water mark for flow control
4213 *
4214 * @adapter: board private structure to calculate for
4215 * @pb: packet buffer to calculate
4216 */
4217 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4218 {
4219 struct ixgbe_hw *hw = &adapter->hw;
4220 struct net_device *dev = adapter->netdev;
4221 int link, tc, kb, marker;
4222 u32 dv_id, rx_pba;
4223
4224 /* Calculate max LAN frame size */
4225 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4226
4227 #ifdef IXGBE_FCOE
4228 /* FCoE traffic class uses FCOE jumbo frames */
4229 if ((dev->features & NETIF_F_FCOE_MTU) &&
4230 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4231 (pb == ixgbe_fcoe_get_tc(adapter)))
4232 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4233 #endif
4234
4235 /* Calculate delay value for device */
4236 switch (hw->mac.type) {
4237 case ixgbe_mac_X540:
4238 dv_id = IXGBE_DV_X540(link, tc);
4239 break;
4240 default:
4241 dv_id = IXGBE_DV(link, tc);
4242 break;
4243 }
4244
4245 /* Loopback switch introduces additional latency */
4246 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4247 dv_id += IXGBE_B2BT(tc);
4248
4249 /* Delay value is calculated in bit times convert to KB */
4250 kb = IXGBE_BT2KB(dv_id);
4251 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4252
4253 marker = rx_pba - kb;
4254
4255 /* It is possible that the packet buffer is not large enough
4256 * to provide required headroom. In this case throw an error
4257 * to user and a do the best we can.
4258 */
4259 if (marker < 0) {
4260 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4261 "headroom to support flow control."
4262 "Decrease MTU or number of traffic classes\n", pb);
4263 marker = tc + 1;
4264 }
4265
4266 return marker;
4267 }
4268
4269 /**
4270 * ixgbe_lpbthresh - calculate low water mark for for flow control
4271 *
4272 * @adapter: board private structure to calculate for
4273 * @pb: packet buffer to calculate
4274 */
4275 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
4276 {
4277 struct ixgbe_hw *hw = &adapter->hw;
4278 struct net_device *dev = adapter->netdev;
4279 int tc;
4280 u32 dv_id;
4281
4282 /* Calculate max LAN frame size */
4283 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4284
4285 #ifdef IXGBE_FCOE
4286 /* FCoE traffic class uses FCOE jumbo frames */
4287 if ((dev->features & NETIF_F_FCOE_MTU) &&
4288 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4289 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4290 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4291 #endif
4292
4293 /* Calculate delay value for device */
4294 switch (hw->mac.type) {
4295 case ixgbe_mac_X540:
4296 dv_id = IXGBE_LOW_DV_X540(tc);
4297 break;
4298 default:
4299 dv_id = IXGBE_LOW_DV(tc);
4300 break;
4301 }
4302
4303 /* Delay value is calculated in bit times convert to KB */
4304 return IXGBE_BT2KB(dv_id);
4305 }
4306
4307 /*
4308 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4309 */
4310 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4311 {
4312 struct ixgbe_hw *hw = &adapter->hw;
4313 int num_tc = netdev_get_num_tc(adapter->netdev);
4314 int i;
4315
4316 if (!num_tc)
4317 num_tc = 1;
4318
4319 for (i = 0; i < num_tc; i++) {
4320 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4321 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
4322
4323 /* Low water marks must not be larger than high water marks */
4324 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4325 hw->fc.low_water[i] = 0;
4326 }
4327
4328 for (; i < MAX_TRAFFIC_CLASS; i++)
4329 hw->fc.high_water[i] = 0;
4330 }
4331
4332 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4333 {
4334 struct ixgbe_hw *hw = &adapter->hw;
4335 int hdrm;
4336 u8 tc = netdev_get_num_tc(adapter->netdev);
4337
4338 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4339 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4340 hdrm = 32 << adapter->fdir_pballoc;
4341 else
4342 hdrm = 0;
4343
4344 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
4345 ixgbe_pbthresh_setup(adapter);
4346 }
4347
4348 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4349 {
4350 struct ixgbe_hw *hw = &adapter->hw;
4351 struct hlist_node *node2;
4352 struct ixgbe_fdir_filter *filter;
4353
4354 spin_lock(&adapter->fdir_perfect_lock);
4355
4356 if (!hlist_empty(&adapter->fdir_filter_list))
4357 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4358
4359 hlist_for_each_entry_safe(filter, node2,
4360 &adapter->fdir_filter_list, fdir_node) {
4361 ixgbe_fdir_write_perfect_filter_82599(hw,
4362 &filter->filter,
4363 filter->sw_idx,
4364 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4365 IXGBE_FDIR_DROP_QUEUE :
4366 adapter->rx_ring[filter->action]->reg_idx);
4367 }
4368
4369 spin_unlock(&adapter->fdir_perfect_lock);
4370 }
4371
4372 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4373 struct ixgbe_adapter *adapter)
4374 {
4375 struct ixgbe_hw *hw = &adapter->hw;
4376 u32 vmolr;
4377
4378 /* No unicast promiscuous support for VMDQ devices. */
4379 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4380 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4381
4382 /* clear the affected bit */
4383 vmolr &= ~IXGBE_VMOLR_MPE;
4384
4385 if (dev->flags & IFF_ALLMULTI) {
4386 vmolr |= IXGBE_VMOLR_MPE;
4387 } else {
4388 vmolr |= IXGBE_VMOLR_ROMPE;
4389 hw->mac.ops.update_mc_addr_list(hw, dev);
4390 }
4391 ixgbe_write_uc_addr_list(adapter->netdev, pool);
4392 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4393 }
4394
4395 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4396 {
4397 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4398 int rss_i = adapter->num_rx_queues_per_pool;
4399 struct ixgbe_hw *hw = &adapter->hw;
4400 u16 pool = vadapter->pool;
4401 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4402 IXGBE_PSRTYPE_UDPHDR |
4403 IXGBE_PSRTYPE_IPV4HDR |
4404 IXGBE_PSRTYPE_L2HDR |
4405 IXGBE_PSRTYPE_IPV6HDR;
4406
4407 if (hw->mac.type == ixgbe_mac_82598EB)
4408 return;
4409
4410 if (rss_i > 3)
4411 psrtype |= 2 << 29;
4412 else if (rss_i > 1)
4413 psrtype |= 1 << 29;
4414
4415 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4416 }
4417
4418 /**
4419 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4420 * @rx_ring: ring to free buffers from
4421 **/
4422 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4423 {
4424 struct device *dev = rx_ring->dev;
4425 unsigned long size;
4426 u16 i;
4427
4428 /* ring already cleared, nothing to do */
4429 if (!rx_ring->rx_buffer_info)
4430 return;
4431
4432 /* Free all the Rx ring sk_buffs */
4433 for (i = 0; i < rx_ring->count; i++) {
4434 struct ixgbe_rx_buffer *rx_buffer;
4435
4436 rx_buffer = &rx_ring->rx_buffer_info[i];
4437 if (rx_buffer->skb) {
4438 struct sk_buff *skb = rx_buffer->skb;
4439 if (IXGBE_CB(skb)->page_released) {
4440 dma_unmap_page(dev,
4441 IXGBE_CB(skb)->dma,
4442 ixgbe_rx_bufsz(rx_ring),
4443 DMA_FROM_DEVICE);
4444 IXGBE_CB(skb)->page_released = false;
4445 }
4446 dev_kfree_skb(skb);
4447 }
4448 rx_buffer->skb = NULL;
4449 if (rx_buffer->dma)
4450 dma_unmap_page(dev, rx_buffer->dma,
4451 ixgbe_rx_pg_size(rx_ring),
4452 DMA_FROM_DEVICE);
4453 rx_buffer->dma = 0;
4454 if (rx_buffer->page)
4455 __free_pages(rx_buffer->page,
4456 ixgbe_rx_pg_order(rx_ring));
4457 rx_buffer->page = NULL;
4458 }
4459
4460 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4461 memset(rx_ring->rx_buffer_info, 0, size);
4462
4463 /* Zero out the descriptor ring */
4464 memset(rx_ring->desc, 0, rx_ring->size);
4465
4466 rx_ring->next_to_alloc = 0;
4467 rx_ring->next_to_clean = 0;
4468 rx_ring->next_to_use = 0;
4469 }
4470
4471 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4472 struct ixgbe_ring *rx_ring)
4473 {
4474 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4475 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4476
4477 /* shutdown specific queue receive and wait for dma to settle */
4478 ixgbe_disable_rx_queue(adapter, rx_ring);
4479 usleep_range(10000, 20000);
4480 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4481 ixgbe_clean_rx_ring(rx_ring);
4482 rx_ring->l2_accel_priv = NULL;
4483 }
4484
4485 static int ixgbe_fwd_ring_down(struct net_device *vdev,
4486 struct ixgbe_fwd_adapter *accel)
4487 {
4488 struct ixgbe_adapter *adapter = accel->real_adapter;
4489 unsigned int rxbase = accel->rx_base_queue;
4490 unsigned int txbase = accel->tx_base_queue;
4491 int i;
4492
4493 netif_tx_stop_all_queues(vdev);
4494
4495 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4496 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4497 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4498 }
4499
4500 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4501 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4502 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4503 }
4504
4505
4506 return 0;
4507 }
4508
4509 static int ixgbe_fwd_ring_up(struct net_device *vdev,
4510 struct ixgbe_fwd_adapter *accel)
4511 {
4512 struct ixgbe_adapter *adapter = accel->real_adapter;
4513 unsigned int rxbase, txbase, queues;
4514 int i, baseq, err = 0;
4515
4516 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4517 return 0;
4518
4519 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4520 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4521 accel->pool, adapter->num_rx_pools,
4522 baseq, baseq + adapter->num_rx_queues_per_pool,
4523 adapter->fwd_bitmask);
4524
4525 accel->netdev = vdev;
4526 accel->rx_base_queue = rxbase = baseq;
4527 accel->tx_base_queue = txbase = baseq;
4528
4529 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4530 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4531
4532 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4533 adapter->rx_ring[rxbase + i]->netdev = vdev;
4534 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4535 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4536 }
4537
4538 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4539 adapter->tx_ring[txbase + i]->netdev = vdev;
4540 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4541 }
4542
4543 queues = min_t(unsigned int,
4544 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4545 err = netif_set_real_num_tx_queues(vdev, queues);
4546 if (err)
4547 goto fwd_queue_err;
4548
4549 err = netif_set_real_num_rx_queues(vdev, queues);
4550 if (err)
4551 goto fwd_queue_err;
4552
4553 if (is_valid_ether_addr(vdev->dev_addr))
4554 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4555
4556 ixgbe_fwd_psrtype(accel);
4557 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4558 return err;
4559 fwd_queue_err:
4560 ixgbe_fwd_ring_down(vdev, accel);
4561 return err;
4562 }
4563
4564 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4565 {
4566 struct net_device *upper;
4567 struct list_head *iter;
4568 int err;
4569
4570 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4571 if (netif_is_macvlan(upper)) {
4572 struct macvlan_dev *dfwd = netdev_priv(upper);
4573 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4574
4575 if (dfwd->fwd_priv) {
4576 err = ixgbe_fwd_ring_up(upper, vadapter);
4577 if (err)
4578 continue;
4579 }
4580 }
4581 }
4582 }
4583
4584 static void ixgbe_configure(struct ixgbe_adapter *adapter)
4585 {
4586 struct ixgbe_hw *hw = &adapter->hw;
4587
4588 ixgbe_configure_pb(adapter);
4589 #ifdef CONFIG_IXGBE_DCB
4590 ixgbe_configure_dcb(adapter);
4591 #endif
4592 /*
4593 * We must restore virtualization before VLANs or else
4594 * the VLVF registers will not be populated
4595 */
4596 ixgbe_configure_virtualization(adapter);
4597
4598 ixgbe_set_rx_mode(adapter->netdev);
4599 ixgbe_restore_vlan(adapter);
4600
4601 switch (hw->mac.type) {
4602 case ixgbe_mac_82599EB:
4603 case ixgbe_mac_X540:
4604 hw->mac.ops.disable_rx_buff(hw);
4605 break;
4606 default:
4607 break;
4608 }
4609
4610 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4611 ixgbe_init_fdir_signature_82599(&adapter->hw,
4612 adapter->fdir_pballoc);
4613 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4614 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4615 adapter->fdir_pballoc);
4616 ixgbe_fdir_filter_restore(adapter);
4617 }
4618
4619 switch (hw->mac.type) {
4620 case ixgbe_mac_82599EB:
4621 case ixgbe_mac_X540:
4622 hw->mac.ops.enable_rx_buff(hw);
4623 break;
4624 default:
4625 break;
4626 }
4627
4628 #ifdef IXGBE_FCOE
4629 /* configure FCoE L2 filters, redirection table, and Rx control */
4630 ixgbe_configure_fcoe(adapter);
4631
4632 #endif /* IXGBE_FCOE */
4633 ixgbe_configure_tx(adapter);
4634 ixgbe_configure_rx(adapter);
4635 ixgbe_configure_dfwd(adapter);
4636 }
4637
4638 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4639 {
4640 switch (hw->phy.type) {
4641 case ixgbe_phy_sfp_avago:
4642 case ixgbe_phy_sfp_ftl:
4643 case ixgbe_phy_sfp_intel:
4644 case ixgbe_phy_sfp_unknown:
4645 case ixgbe_phy_sfp_passive_tyco:
4646 case ixgbe_phy_sfp_passive_unknown:
4647 case ixgbe_phy_sfp_active_unknown:
4648 case ixgbe_phy_sfp_ftl_active:
4649 case ixgbe_phy_qsfp_passive_unknown:
4650 case ixgbe_phy_qsfp_active_unknown:
4651 case ixgbe_phy_qsfp_intel:
4652 case ixgbe_phy_qsfp_unknown:
4653 /* ixgbe_phy_none is set when no SFP module is present */
4654 case ixgbe_phy_none:
4655 return true;
4656 case ixgbe_phy_nl:
4657 if (hw->mac.type == ixgbe_mac_82598EB)
4658 return true;
4659 default:
4660 return false;
4661 }
4662 }
4663
4664 /**
4665 * ixgbe_sfp_link_config - set up SFP+ link
4666 * @adapter: pointer to private adapter struct
4667 **/
4668 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4669 {
4670 /*
4671 * We are assuming the worst case scenario here, and that
4672 * is that an SFP was inserted/removed after the reset
4673 * but before SFP detection was enabled. As such the best
4674 * solution is to just start searching as soon as we start
4675 */
4676 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4677 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4678
4679 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4680 }
4681
4682 /**
4683 * ixgbe_non_sfp_link_config - set up non-SFP+ link
4684 * @hw: pointer to private hardware struct
4685 *
4686 * Returns 0 on success, negative on failure
4687 **/
4688 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4689 {
4690 u32 speed;
4691 bool autoneg, link_up = false;
4692 u32 ret = IXGBE_ERR_LINK_SETUP;
4693
4694 if (hw->mac.ops.check_link)
4695 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
4696
4697 if (ret)
4698 return ret;
4699
4700 speed = hw->phy.autoneg_advertised;
4701 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4702 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4703 &autoneg);
4704 if (ret)
4705 return ret;
4706
4707 if (hw->mac.ops.setup_link)
4708 ret = hw->mac.ops.setup_link(hw, speed, link_up);
4709
4710 return ret;
4711 }
4712
4713 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4714 {
4715 struct ixgbe_hw *hw = &adapter->hw;
4716 u32 gpie = 0;
4717
4718 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4719 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4720 IXGBE_GPIE_OCD;
4721 gpie |= IXGBE_GPIE_EIAME;
4722 /*
4723 * use EIAM to auto-mask when MSI-X interrupt is asserted
4724 * this saves a register write for every interrupt
4725 */
4726 switch (hw->mac.type) {
4727 case ixgbe_mac_82598EB:
4728 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4729 break;
4730 case ixgbe_mac_82599EB:
4731 case ixgbe_mac_X540:
4732 default:
4733 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4734 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4735 break;
4736 }
4737 } else {
4738 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4739 * specifically only auto mask tx and rx interrupts */
4740 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4741 }
4742
4743 /* XXX: to interrupt immediately for EICS writes, enable this */
4744 /* gpie |= IXGBE_GPIE_EIMEN; */
4745
4746 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4747 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4748
4749 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4750 case IXGBE_82599_VMDQ_8Q_MASK:
4751 gpie |= IXGBE_GPIE_VTMODE_16;
4752 break;
4753 case IXGBE_82599_VMDQ_4Q_MASK:
4754 gpie |= IXGBE_GPIE_VTMODE_32;
4755 break;
4756 default:
4757 gpie |= IXGBE_GPIE_VTMODE_64;
4758 break;
4759 }
4760 }
4761
4762 /* Enable Thermal over heat sensor interrupt */
4763 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4764 switch (adapter->hw.mac.type) {
4765 case ixgbe_mac_82599EB:
4766 gpie |= IXGBE_SDP0_GPIEN;
4767 break;
4768 case ixgbe_mac_X540:
4769 gpie |= IXGBE_EIMS_TS;
4770 break;
4771 default:
4772 break;
4773 }
4774 }
4775
4776 /* Enable fan failure interrupt */
4777 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4778 gpie |= IXGBE_SDP1_GPIEN;
4779
4780 if (hw->mac.type == ixgbe_mac_82599EB) {
4781 gpie |= IXGBE_SDP1_GPIEN;
4782 gpie |= IXGBE_SDP2_GPIEN;
4783 }
4784
4785 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4786 }
4787
4788 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4789 {
4790 struct ixgbe_hw *hw = &adapter->hw;
4791 int err;
4792 u32 ctrl_ext;
4793
4794 ixgbe_get_hw_control(adapter);
4795 ixgbe_setup_gpie(adapter);
4796
4797 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4798 ixgbe_configure_msix(adapter);
4799 else
4800 ixgbe_configure_msi_and_legacy(adapter);
4801
4802 /* enable the optics for 82599 SFP+ fiber */
4803 if (hw->mac.ops.enable_tx_laser)
4804 hw->mac.ops.enable_tx_laser(hw);
4805
4806 smp_mb__before_atomic();
4807 clear_bit(__IXGBE_DOWN, &adapter->state);
4808 ixgbe_napi_enable_all(adapter);
4809
4810 if (ixgbe_is_sfp(hw)) {
4811 ixgbe_sfp_link_config(adapter);
4812 } else {
4813 err = ixgbe_non_sfp_link_config(hw);
4814 if (err)
4815 e_err(probe, "link_config FAILED %d\n", err);
4816 }
4817
4818 /* clear any pending interrupts, may auto mask */
4819 IXGBE_READ_REG(hw, IXGBE_EICR);
4820 ixgbe_irq_enable(adapter, true, true);
4821
4822 /*
4823 * If this adapter has a fan, check to see if we had a failure
4824 * before we enabled the interrupt.
4825 */
4826 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4827 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4828 if (esdp & IXGBE_ESDP_SDP1)
4829 e_crit(drv, "Fan has stopped, replace the adapter\n");
4830 }
4831
4832 /* bring the link up in the watchdog, this could race with our first
4833 * link up interrupt but shouldn't be a problem */
4834 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4835 adapter->link_check_timeout = jiffies;
4836 mod_timer(&adapter->service_timer, jiffies);
4837
4838 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4839 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4840 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4841 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4842 }
4843
4844 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4845 {
4846 WARN_ON(in_interrupt());
4847 /* put off any impending NetWatchDogTimeout */
4848 adapter->netdev->trans_start = jiffies;
4849
4850 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4851 usleep_range(1000, 2000);
4852 ixgbe_down(adapter);
4853 /*
4854 * If SR-IOV enabled then wait a bit before bringing the adapter
4855 * back up to give the VFs time to respond to the reset. The
4856 * two second wait is based upon the watchdog timer cycle in
4857 * the VF driver.
4858 */
4859 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4860 msleep(2000);
4861 ixgbe_up(adapter);
4862 clear_bit(__IXGBE_RESETTING, &adapter->state);
4863 }
4864
4865 void ixgbe_up(struct ixgbe_adapter *adapter)
4866 {
4867 /* hardware has been reset, we need to reload some things */
4868 ixgbe_configure(adapter);
4869
4870 ixgbe_up_complete(adapter);
4871 }
4872
4873 void ixgbe_reset(struct ixgbe_adapter *adapter)
4874 {
4875 struct ixgbe_hw *hw = &adapter->hw;
4876 struct net_device *netdev = adapter->netdev;
4877 int err;
4878 u8 old_addr[ETH_ALEN];
4879
4880 if (ixgbe_removed(hw->hw_addr))
4881 return;
4882 /* lock SFP init bit to prevent race conditions with the watchdog */
4883 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4884 usleep_range(1000, 2000);
4885
4886 /* clear all SFP and link config related flags while holding SFP_INIT */
4887 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4888 IXGBE_FLAG2_SFP_NEEDS_RESET);
4889 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4890
4891 err = hw->mac.ops.init_hw(hw);
4892 switch (err) {
4893 case 0:
4894 case IXGBE_ERR_SFP_NOT_PRESENT:
4895 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4896 break;
4897 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4898 e_dev_err("master disable timed out\n");
4899 break;
4900 case IXGBE_ERR_EEPROM_VERSION:
4901 /* We are running on a pre-production device, log a warning */
4902 e_dev_warn("This device is a pre-production adapter/LOM. "
4903 "Please be aware there may be issues associated with "
4904 "your hardware. If you are experiencing problems "
4905 "please contact your Intel or hardware "
4906 "representative who provided you with this "
4907 "hardware.\n");
4908 break;
4909 default:
4910 e_dev_err("Hardware Error: %d\n", err);
4911 }
4912
4913 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4914 /* do not flush user set addresses */
4915 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len);
4916 ixgbe_flush_sw_mac_table(adapter);
4917 ixgbe_mac_set_default_filter(adapter, old_addr);
4918
4919 /* update SAN MAC vmdq pool selection */
4920 if (hw->mac.san_mac_rar_index)
4921 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4922
4923 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
4924 ixgbe_ptp_reset(adapter);
4925 }
4926
4927 /**
4928 * ixgbe_clean_tx_ring - Free Tx Buffers
4929 * @tx_ring: ring to be cleaned
4930 **/
4931 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4932 {
4933 struct ixgbe_tx_buffer *tx_buffer_info;
4934 unsigned long size;
4935 u16 i;
4936
4937 /* ring already cleared, nothing to do */
4938 if (!tx_ring->tx_buffer_info)
4939 return;
4940
4941 /* Free all the Tx ring sk_buffs */
4942 for (i = 0; i < tx_ring->count; i++) {
4943 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4944 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4945 }
4946
4947 netdev_tx_reset_queue(txring_txq(tx_ring));
4948
4949 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4950 memset(tx_ring->tx_buffer_info, 0, size);
4951
4952 /* Zero out the descriptor ring */
4953 memset(tx_ring->desc, 0, tx_ring->size);
4954
4955 tx_ring->next_to_use = 0;
4956 tx_ring->next_to_clean = 0;
4957 }
4958
4959 /**
4960 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4961 * @adapter: board private structure
4962 **/
4963 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4964 {
4965 int i;
4966
4967 for (i = 0; i < adapter->num_rx_queues; i++)
4968 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4969 }
4970
4971 /**
4972 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4973 * @adapter: board private structure
4974 **/
4975 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4976 {
4977 int i;
4978
4979 for (i = 0; i < adapter->num_tx_queues; i++)
4980 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4981 }
4982
4983 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4984 {
4985 struct hlist_node *node2;
4986 struct ixgbe_fdir_filter *filter;
4987
4988 spin_lock(&adapter->fdir_perfect_lock);
4989
4990 hlist_for_each_entry_safe(filter, node2,
4991 &adapter->fdir_filter_list, fdir_node) {
4992 hlist_del(&filter->fdir_node);
4993 kfree(filter);
4994 }
4995 adapter->fdir_filter_count = 0;
4996
4997 spin_unlock(&adapter->fdir_perfect_lock);
4998 }
4999
5000 void ixgbe_down(struct ixgbe_adapter *adapter)
5001 {
5002 struct net_device *netdev = adapter->netdev;
5003 struct ixgbe_hw *hw = &adapter->hw;
5004 struct net_device *upper;
5005 struct list_head *iter;
5006 u32 rxctrl;
5007 int i;
5008
5009 /* signal that we are down to the interrupt handler */
5010 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5011 return; /* do nothing if already down */
5012
5013 /* disable receives */
5014 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5015 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
5016
5017 /* disable all enabled rx queues */
5018 for (i = 0; i < adapter->num_rx_queues; i++)
5019 /* this call also flushes the previous write */
5020 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5021
5022 usleep_range(10000, 20000);
5023
5024 netif_tx_stop_all_queues(netdev);
5025
5026 /* call carrier off first to avoid false dev_watchdog timeouts */
5027 netif_carrier_off(netdev);
5028 netif_tx_disable(netdev);
5029
5030 /* disable any upper devices */
5031 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5032 if (netif_is_macvlan(upper)) {
5033 struct macvlan_dev *vlan = netdev_priv(upper);
5034
5035 if (vlan->fwd_priv) {
5036 netif_tx_stop_all_queues(upper);
5037 netif_carrier_off(upper);
5038 netif_tx_disable(upper);
5039 }
5040 }
5041 }
5042
5043 ixgbe_irq_disable(adapter);
5044
5045 ixgbe_napi_disable_all(adapter);
5046
5047 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5048 IXGBE_FLAG2_RESET_REQUESTED);
5049 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5050
5051 del_timer_sync(&adapter->service_timer);
5052
5053 if (adapter->num_vfs) {
5054 /* Clear EITR Select mapping */
5055 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
5056
5057 /* Mark all the VFs as inactive */
5058 for (i = 0 ; i < adapter->num_vfs; i++)
5059 adapter->vfinfo[i].clear_to_send = false;
5060
5061 /* ping all the active vfs to let them know we are going down */
5062 ixgbe_ping_all_vfs(adapter);
5063
5064 /* Disable all VFTE/VFRE TX/RX */
5065 ixgbe_disable_tx_rx(adapter);
5066 }
5067
5068 /* disable transmits in the hardware now that interrupts are off */
5069 for (i = 0; i < adapter->num_tx_queues; i++) {
5070 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
5071 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5072 }
5073
5074 /* Disable the Tx DMA engine on 82599 and X540 */
5075 switch (hw->mac.type) {
5076 case ixgbe_mac_82599EB:
5077 case ixgbe_mac_X540:
5078 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
5079 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5080 ~IXGBE_DMATXCTL_TE));
5081 break;
5082 default:
5083 break;
5084 }
5085
5086 if (!pci_channel_offline(adapter->pdev))
5087 ixgbe_reset(adapter);
5088
5089 /* power down the optics for 82599 SFP+ fiber */
5090 if (hw->mac.ops.disable_tx_laser)
5091 hw->mac.ops.disable_tx_laser(hw);
5092
5093 ixgbe_clean_all_tx_rings(adapter);
5094 ixgbe_clean_all_rx_rings(adapter);
5095
5096 #ifdef CONFIG_IXGBE_DCA
5097 /* since we reset the hardware DCA settings were cleared */
5098 ixgbe_setup_dca(adapter);
5099 #endif
5100 }
5101
5102 /**
5103 * ixgbe_tx_timeout - Respond to a Tx Hang
5104 * @netdev: network interface device structure
5105 **/
5106 static void ixgbe_tx_timeout(struct net_device *netdev)
5107 {
5108 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5109
5110 /* Do the reset outside of interrupt context */
5111 ixgbe_tx_timeout_reset(adapter);
5112 }
5113
5114 /**
5115 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5116 * @adapter: board private structure to initialize
5117 *
5118 * ixgbe_sw_init initializes the Adapter private data structure.
5119 * Fields are initialized based on PCI device information and
5120 * OS network device settings (MTU size).
5121 **/
5122 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
5123 {
5124 struct ixgbe_hw *hw = &adapter->hw;
5125 struct pci_dev *pdev = adapter->pdev;
5126 unsigned int rss, fdir;
5127 u32 fwsm;
5128 #ifdef CONFIG_IXGBE_DCB
5129 int j;
5130 struct tc_configuration *tc;
5131 #endif
5132
5133 /* PCI config space info */
5134
5135 hw->vendor_id = pdev->vendor;
5136 hw->device_id = pdev->device;
5137 hw->revision_id = pdev->revision;
5138 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5139 hw->subsystem_device_id = pdev->subsystem_device;
5140
5141 /* Set common capability flags and settings */
5142 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
5143 adapter->ring_feature[RING_F_RSS].limit = rss;
5144 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5145 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5146 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5147 adapter->atr_sample_rate = 20;
5148 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5149 adapter->ring_feature[RING_F_FDIR].limit = fdir;
5150 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5151 #ifdef CONFIG_IXGBE_DCA
5152 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5153 #endif
5154 #ifdef IXGBE_FCOE
5155 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5156 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5157 #ifdef CONFIG_IXGBE_DCB
5158 /* Default traffic class to use for FCoE */
5159 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5160 #endif /* CONFIG_IXGBE_DCB */
5161 #endif /* IXGBE_FCOE */
5162
5163 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5164 hw->mac.num_rar_entries,
5165 GFP_ATOMIC);
5166
5167 /* Set MAC specific capability flags and exceptions */
5168 switch (hw->mac.type) {
5169 case ixgbe_mac_82598EB:
5170 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5171 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5172
5173 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5174 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5175
5176 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
5177 adapter->ring_feature[RING_F_FDIR].limit = 0;
5178 adapter->atr_sample_rate = 0;
5179 adapter->fdir_pballoc = 0;
5180 #ifdef IXGBE_FCOE
5181 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5182 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5183 #ifdef CONFIG_IXGBE_DCB
5184 adapter->fcoe.up = 0;
5185 #endif /* IXGBE_DCB */
5186 #endif /* IXGBE_FCOE */
5187 break;
5188 case ixgbe_mac_82599EB:
5189 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5190 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5191 break;
5192 case ixgbe_mac_X540:
5193 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
5194 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5195 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5196 break;
5197 default:
5198 break;
5199 }
5200
5201 #ifdef IXGBE_FCOE
5202 /* FCoE support exists, always init the FCoE lock */
5203 spin_lock_init(&adapter->fcoe.lock);
5204
5205 #endif
5206 /* n-tuple support exists, always init our spinlock */
5207 spin_lock_init(&adapter->fdir_perfect_lock);
5208
5209 #ifdef CONFIG_IXGBE_DCB
5210 switch (hw->mac.type) {
5211 case ixgbe_mac_X540:
5212 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5213 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5214 break;
5215 default:
5216 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5217 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5218 break;
5219 }
5220
5221 /* Configure DCB traffic classes */
5222 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5223 tc = &adapter->dcb_cfg.tc_config[j];
5224 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5225 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5226 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5227 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5228 tc->dcb_pfc = pfc_disabled;
5229 }
5230
5231 /* Initialize default user to priority mapping, UPx->TC0 */
5232 tc = &adapter->dcb_cfg.tc_config[0];
5233 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5234 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5235
5236 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5237 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5238 adapter->dcb_cfg.pfc_mode_enable = false;
5239 adapter->dcb_set_bitmap = 0x00;
5240 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5241 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5242 sizeof(adapter->temp_dcb_cfg));
5243
5244 #endif
5245
5246 /* default flow control settings */
5247 hw->fc.requested_mode = ixgbe_fc_full;
5248 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5249 ixgbe_pbthresh_setup(adapter);
5250 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5251 hw->fc.send_xon = true;
5252 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
5253
5254 #ifdef CONFIG_PCI_IOV
5255 if (max_vfs > 0)
5256 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5257
5258 /* assign number of SR-IOV VFs */
5259 if (hw->mac.type != ixgbe_mac_82598EB) {
5260 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
5261 adapter->num_vfs = 0;
5262 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5263 } else {
5264 adapter->num_vfs = max_vfs;
5265 }
5266 }
5267 #endif /* CONFIG_PCI_IOV */
5268
5269 /* enable itr by default in dynamic mode */
5270 adapter->rx_itr_setting = 1;
5271 adapter->tx_itr_setting = 1;
5272
5273 /* set default ring sizes */
5274 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5275 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5276
5277 /* set default work limits */
5278 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5279
5280 /* initialize eeprom parameters */
5281 if (ixgbe_init_eeprom_params_generic(hw)) {
5282 e_dev_err("EEPROM initialization failed\n");
5283 return -EIO;
5284 }
5285
5286 /* PF holds first pool slot */
5287 set_bit(0, &adapter->fwd_bitmask);
5288 set_bit(__IXGBE_DOWN, &adapter->state);
5289
5290 return 0;
5291 }
5292
5293 /**
5294 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5295 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5296 *
5297 * Return 0 on success, negative on failure
5298 **/
5299 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5300 {
5301 struct device *dev = tx_ring->dev;
5302 int orig_node = dev_to_node(dev);
5303 int numa_node = -1;
5304 int size;
5305
5306 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5307
5308 if (tx_ring->q_vector)
5309 numa_node = tx_ring->q_vector->numa_node;
5310
5311 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
5312 if (!tx_ring->tx_buffer_info)
5313 tx_ring->tx_buffer_info = vzalloc(size);
5314 if (!tx_ring->tx_buffer_info)
5315 goto err;
5316
5317 u64_stats_init(&tx_ring->syncp);
5318
5319 /* round up to nearest 4K */
5320 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5321 tx_ring->size = ALIGN(tx_ring->size, 4096);
5322
5323 set_dev_node(dev, numa_node);
5324 tx_ring->desc = dma_alloc_coherent(dev,
5325 tx_ring->size,
5326 &tx_ring->dma,
5327 GFP_KERNEL);
5328 set_dev_node(dev, orig_node);
5329 if (!tx_ring->desc)
5330 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5331 &tx_ring->dma, GFP_KERNEL);
5332 if (!tx_ring->desc)
5333 goto err;
5334
5335 tx_ring->next_to_use = 0;
5336 tx_ring->next_to_clean = 0;
5337 return 0;
5338
5339 err:
5340 vfree(tx_ring->tx_buffer_info);
5341 tx_ring->tx_buffer_info = NULL;
5342 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5343 return -ENOMEM;
5344 }
5345
5346 /**
5347 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5348 * @adapter: board private structure
5349 *
5350 * If this function returns with an error, then it's possible one or
5351 * more of the rings is populated (while the rest are not). It is the
5352 * callers duty to clean those orphaned rings.
5353 *
5354 * Return 0 on success, negative on failure
5355 **/
5356 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5357 {
5358 int i, err = 0;
5359
5360 for (i = 0; i < adapter->num_tx_queues; i++) {
5361 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5362 if (!err)
5363 continue;
5364
5365 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5366 goto err_setup_tx;
5367 }
5368
5369 return 0;
5370 err_setup_tx:
5371 /* rewind the index freeing the rings as we go */
5372 while (i--)
5373 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5374 return err;
5375 }
5376
5377 /**
5378 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5379 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5380 *
5381 * Returns 0 on success, negative on failure
5382 **/
5383 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5384 {
5385 struct device *dev = rx_ring->dev;
5386 int orig_node = dev_to_node(dev);
5387 int numa_node = -1;
5388 int size;
5389
5390 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5391
5392 if (rx_ring->q_vector)
5393 numa_node = rx_ring->q_vector->numa_node;
5394
5395 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
5396 if (!rx_ring->rx_buffer_info)
5397 rx_ring->rx_buffer_info = vzalloc(size);
5398 if (!rx_ring->rx_buffer_info)
5399 goto err;
5400
5401 u64_stats_init(&rx_ring->syncp);
5402
5403 /* Round up to nearest 4K */
5404 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5405 rx_ring->size = ALIGN(rx_ring->size, 4096);
5406
5407 set_dev_node(dev, numa_node);
5408 rx_ring->desc = dma_alloc_coherent(dev,
5409 rx_ring->size,
5410 &rx_ring->dma,
5411 GFP_KERNEL);
5412 set_dev_node(dev, orig_node);
5413 if (!rx_ring->desc)
5414 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5415 &rx_ring->dma, GFP_KERNEL);
5416 if (!rx_ring->desc)
5417 goto err;
5418
5419 rx_ring->next_to_clean = 0;
5420 rx_ring->next_to_use = 0;
5421
5422 return 0;
5423 err:
5424 vfree(rx_ring->rx_buffer_info);
5425 rx_ring->rx_buffer_info = NULL;
5426 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5427 return -ENOMEM;
5428 }
5429
5430 /**
5431 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5432 * @adapter: board private structure
5433 *
5434 * If this function returns with an error, then it's possible one or
5435 * more of the rings is populated (while the rest are not). It is the
5436 * callers duty to clean those orphaned rings.
5437 *
5438 * Return 0 on success, negative on failure
5439 **/
5440 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5441 {
5442 int i, err = 0;
5443
5444 for (i = 0; i < adapter->num_rx_queues; i++) {
5445 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5446 if (!err)
5447 continue;
5448
5449 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5450 goto err_setup_rx;
5451 }
5452
5453 #ifdef IXGBE_FCOE
5454 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5455 if (!err)
5456 #endif
5457 return 0;
5458 err_setup_rx:
5459 /* rewind the index freeing the rings as we go */
5460 while (i--)
5461 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5462 return err;
5463 }
5464
5465 /**
5466 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5467 * @tx_ring: Tx descriptor ring for a specific queue
5468 *
5469 * Free all transmit software resources
5470 **/
5471 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5472 {
5473 ixgbe_clean_tx_ring(tx_ring);
5474
5475 vfree(tx_ring->tx_buffer_info);
5476 tx_ring->tx_buffer_info = NULL;
5477
5478 /* if not set, then don't free */
5479 if (!tx_ring->desc)
5480 return;
5481
5482 dma_free_coherent(tx_ring->dev, tx_ring->size,
5483 tx_ring->desc, tx_ring->dma);
5484
5485 tx_ring->desc = NULL;
5486 }
5487
5488 /**
5489 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5490 * @adapter: board private structure
5491 *
5492 * Free all transmit software resources
5493 **/
5494 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5495 {
5496 int i;
5497
5498 for (i = 0; i < adapter->num_tx_queues; i++)
5499 if (adapter->tx_ring[i]->desc)
5500 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5501 }
5502
5503 /**
5504 * ixgbe_free_rx_resources - Free Rx Resources
5505 * @rx_ring: ring to clean the resources from
5506 *
5507 * Free all receive software resources
5508 **/
5509 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5510 {
5511 ixgbe_clean_rx_ring(rx_ring);
5512
5513 vfree(rx_ring->rx_buffer_info);
5514 rx_ring->rx_buffer_info = NULL;
5515
5516 /* if not set, then don't free */
5517 if (!rx_ring->desc)
5518 return;
5519
5520 dma_free_coherent(rx_ring->dev, rx_ring->size,
5521 rx_ring->desc, rx_ring->dma);
5522
5523 rx_ring->desc = NULL;
5524 }
5525
5526 /**
5527 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5528 * @adapter: board private structure
5529 *
5530 * Free all receive software resources
5531 **/
5532 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5533 {
5534 int i;
5535
5536 #ifdef IXGBE_FCOE
5537 ixgbe_free_fcoe_ddp_resources(adapter);
5538
5539 #endif
5540 for (i = 0; i < adapter->num_rx_queues; i++)
5541 if (adapter->rx_ring[i]->desc)
5542 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5543 }
5544
5545 /**
5546 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5547 * @netdev: network interface device structure
5548 * @new_mtu: new value for maximum frame size
5549 *
5550 * Returns 0 on success, negative on failure
5551 **/
5552 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5553 {
5554 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5555 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5556
5557 /* MTU < 68 is an error and causes problems on some kernels */
5558 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5559 return -EINVAL;
5560
5561 /*
5562 * For 82599EB we cannot allow legacy VFs to enable their receive
5563 * paths when MTU greater than 1500 is configured. So display a
5564 * warning that legacy VFs will be disabled.
5565 */
5566 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5567 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
5568 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
5569 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
5570
5571 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5572
5573 /* must set new MTU before calling down or up */
5574 netdev->mtu = new_mtu;
5575
5576 if (netif_running(netdev))
5577 ixgbe_reinit_locked(adapter);
5578
5579 return 0;
5580 }
5581
5582 /**
5583 * ixgbe_open - Called when a network interface is made active
5584 * @netdev: network interface device structure
5585 *
5586 * Returns 0 on success, negative value on failure
5587 *
5588 * The open entry point is called when a network interface is made
5589 * active by the system (IFF_UP). At this point all resources needed
5590 * for transmit and receive operations are allocated, the interrupt
5591 * handler is registered with the OS, the watchdog timer is started,
5592 * and the stack is notified that the interface is ready.
5593 **/
5594 static int ixgbe_open(struct net_device *netdev)
5595 {
5596 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5597 int err, queues;
5598
5599 /* disallow open during test */
5600 if (test_bit(__IXGBE_TESTING, &adapter->state))
5601 return -EBUSY;
5602
5603 netif_carrier_off(netdev);
5604
5605 /* allocate transmit descriptors */
5606 err = ixgbe_setup_all_tx_resources(adapter);
5607 if (err)
5608 goto err_setup_tx;
5609
5610 /* allocate receive descriptors */
5611 err = ixgbe_setup_all_rx_resources(adapter);
5612 if (err)
5613 goto err_setup_rx;
5614
5615 ixgbe_configure(adapter);
5616
5617 err = ixgbe_request_irq(adapter);
5618 if (err)
5619 goto err_req_irq;
5620
5621 /* Notify the stack of the actual queue counts. */
5622 if (adapter->num_rx_pools > 1)
5623 queues = adapter->num_rx_queues_per_pool;
5624 else
5625 queues = adapter->num_tx_queues;
5626
5627 err = netif_set_real_num_tx_queues(netdev, queues);
5628 if (err)
5629 goto err_set_queues;
5630
5631 if (adapter->num_rx_pools > 1 &&
5632 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5633 queues = IXGBE_MAX_L2A_QUEUES;
5634 else
5635 queues = adapter->num_rx_queues;
5636 err = netif_set_real_num_rx_queues(netdev, queues);
5637 if (err)
5638 goto err_set_queues;
5639
5640 ixgbe_ptp_init(adapter);
5641
5642 ixgbe_up_complete(adapter);
5643
5644 return 0;
5645
5646 err_set_queues:
5647 ixgbe_free_irq(adapter);
5648 err_req_irq:
5649 ixgbe_free_all_rx_resources(adapter);
5650 err_setup_rx:
5651 ixgbe_free_all_tx_resources(adapter);
5652 err_setup_tx:
5653 ixgbe_reset(adapter);
5654
5655 return err;
5656 }
5657
5658 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5659 {
5660 ixgbe_ptp_suspend(adapter);
5661
5662 ixgbe_down(adapter);
5663 ixgbe_free_irq(adapter);
5664
5665 ixgbe_free_all_tx_resources(adapter);
5666 ixgbe_free_all_rx_resources(adapter);
5667 }
5668
5669 /**
5670 * ixgbe_close - Disables a network interface
5671 * @netdev: network interface device structure
5672 *
5673 * Returns 0, this is not allowed to fail
5674 *
5675 * The close entry point is called when an interface is de-activated
5676 * by the OS. The hardware is still under the drivers control, but
5677 * needs to be disabled. A global MAC reset is issued to stop the
5678 * hardware, and all transmit and receive resources are freed.
5679 **/
5680 static int ixgbe_close(struct net_device *netdev)
5681 {
5682 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5683
5684 ixgbe_ptp_stop(adapter);
5685
5686 ixgbe_close_suspend(adapter);
5687
5688 ixgbe_fdir_filter_exit(adapter);
5689
5690 ixgbe_release_hw_control(adapter);
5691
5692 return 0;
5693 }
5694
5695 #ifdef CONFIG_PM
5696 static int ixgbe_resume(struct pci_dev *pdev)
5697 {
5698 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5699 struct net_device *netdev = adapter->netdev;
5700 u32 err;
5701
5702 adapter->hw.hw_addr = adapter->io_addr;
5703 pci_set_power_state(pdev, PCI_D0);
5704 pci_restore_state(pdev);
5705 /*
5706 * pci_restore_state clears dev->state_saved so call
5707 * pci_save_state to restore it.
5708 */
5709 pci_save_state(pdev);
5710
5711 err = pci_enable_device_mem(pdev);
5712 if (err) {
5713 e_dev_err("Cannot enable PCI device from suspend\n");
5714 return err;
5715 }
5716 smp_mb__before_atomic();
5717 clear_bit(__IXGBE_DISABLED, &adapter->state);
5718 pci_set_master(pdev);
5719
5720 pci_wake_from_d3(pdev, false);
5721
5722 ixgbe_reset(adapter);
5723
5724 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5725
5726 rtnl_lock();
5727 err = ixgbe_init_interrupt_scheme(adapter);
5728 if (!err && netif_running(netdev))
5729 err = ixgbe_open(netdev);
5730
5731 rtnl_unlock();
5732
5733 if (err)
5734 return err;
5735
5736 netif_device_attach(netdev);
5737
5738 return 0;
5739 }
5740 #endif /* CONFIG_PM */
5741
5742 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5743 {
5744 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5745 struct net_device *netdev = adapter->netdev;
5746 struct ixgbe_hw *hw = &adapter->hw;
5747 u32 ctrl, fctrl;
5748 u32 wufc = adapter->wol;
5749 #ifdef CONFIG_PM
5750 int retval = 0;
5751 #endif
5752
5753 netif_device_detach(netdev);
5754
5755 rtnl_lock();
5756 if (netif_running(netdev))
5757 ixgbe_close_suspend(adapter);
5758 rtnl_unlock();
5759
5760 ixgbe_clear_interrupt_scheme(adapter);
5761
5762 #ifdef CONFIG_PM
5763 retval = pci_save_state(pdev);
5764 if (retval)
5765 return retval;
5766
5767 #endif
5768 if (hw->mac.ops.stop_link_on_d3)
5769 hw->mac.ops.stop_link_on_d3(hw);
5770
5771 if (wufc) {
5772 ixgbe_set_rx_mode(netdev);
5773
5774 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5775 if (hw->mac.ops.enable_tx_laser)
5776 hw->mac.ops.enable_tx_laser(hw);
5777
5778 /* turn on all-multi mode if wake on multicast is enabled */
5779 if (wufc & IXGBE_WUFC_MC) {
5780 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5781 fctrl |= IXGBE_FCTRL_MPE;
5782 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5783 }
5784
5785 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5786 ctrl |= IXGBE_CTRL_GIO_DIS;
5787 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5788
5789 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5790 } else {
5791 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5792 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5793 }
5794
5795 switch (hw->mac.type) {
5796 case ixgbe_mac_82598EB:
5797 pci_wake_from_d3(pdev, false);
5798 break;
5799 case ixgbe_mac_82599EB:
5800 case ixgbe_mac_X540:
5801 pci_wake_from_d3(pdev, !!wufc);
5802 break;
5803 default:
5804 break;
5805 }
5806
5807 *enable_wake = !!wufc;
5808
5809 ixgbe_release_hw_control(adapter);
5810
5811 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
5812 pci_disable_device(pdev);
5813
5814 return 0;
5815 }
5816
5817 #ifdef CONFIG_PM
5818 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5819 {
5820 int retval;
5821 bool wake;
5822
5823 retval = __ixgbe_shutdown(pdev, &wake);
5824 if (retval)
5825 return retval;
5826
5827 if (wake) {
5828 pci_prepare_to_sleep(pdev);
5829 } else {
5830 pci_wake_from_d3(pdev, false);
5831 pci_set_power_state(pdev, PCI_D3hot);
5832 }
5833
5834 return 0;
5835 }
5836 #endif /* CONFIG_PM */
5837
5838 static void ixgbe_shutdown(struct pci_dev *pdev)
5839 {
5840 bool wake;
5841
5842 __ixgbe_shutdown(pdev, &wake);
5843
5844 if (system_state == SYSTEM_POWER_OFF) {
5845 pci_wake_from_d3(pdev, wake);
5846 pci_set_power_state(pdev, PCI_D3hot);
5847 }
5848 }
5849
5850 /**
5851 * ixgbe_update_stats - Update the board statistics counters.
5852 * @adapter: board private structure
5853 **/
5854 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5855 {
5856 struct net_device *netdev = adapter->netdev;
5857 struct ixgbe_hw *hw = &adapter->hw;
5858 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5859 u64 total_mpc = 0;
5860 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5861 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5862 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5863 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5864
5865 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5866 test_bit(__IXGBE_RESETTING, &adapter->state))
5867 return;
5868
5869 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5870 u64 rsc_count = 0;
5871 u64 rsc_flush = 0;
5872 for (i = 0; i < adapter->num_rx_queues; i++) {
5873 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5874 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5875 }
5876 adapter->rsc_total_count = rsc_count;
5877 adapter->rsc_total_flush = rsc_flush;
5878 }
5879
5880 for (i = 0; i < adapter->num_rx_queues; i++) {
5881 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5882 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5883 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5884 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5885 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5886 bytes += rx_ring->stats.bytes;
5887 packets += rx_ring->stats.packets;
5888 }
5889 adapter->non_eop_descs = non_eop_descs;
5890 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5891 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5892 adapter->hw_csum_rx_error = hw_csum_rx_error;
5893 netdev->stats.rx_bytes = bytes;
5894 netdev->stats.rx_packets = packets;
5895
5896 bytes = 0;
5897 packets = 0;
5898 /* gather some stats to the adapter struct that are per queue */
5899 for (i = 0; i < adapter->num_tx_queues; i++) {
5900 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5901 restart_queue += tx_ring->tx_stats.restart_queue;
5902 tx_busy += tx_ring->tx_stats.tx_busy;
5903 bytes += tx_ring->stats.bytes;
5904 packets += tx_ring->stats.packets;
5905 }
5906 adapter->restart_queue = restart_queue;
5907 adapter->tx_busy = tx_busy;
5908 netdev->stats.tx_bytes = bytes;
5909 netdev->stats.tx_packets = packets;
5910
5911 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5912
5913 /* 8 register reads */
5914 for (i = 0; i < 8; i++) {
5915 /* for packet buffers not used, the register should read 0 */
5916 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5917 missed_rx += mpc;
5918 hwstats->mpc[i] += mpc;
5919 total_mpc += hwstats->mpc[i];
5920 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5921 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5922 switch (hw->mac.type) {
5923 case ixgbe_mac_82598EB:
5924 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5925 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5926 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5927 hwstats->pxonrxc[i] +=
5928 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5929 break;
5930 case ixgbe_mac_82599EB:
5931 case ixgbe_mac_X540:
5932 hwstats->pxonrxc[i] +=
5933 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5934 break;
5935 default:
5936 break;
5937 }
5938 }
5939
5940 /*16 register reads */
5941 for (i = 0; i < 16; i++) {
5942 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5943 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5944 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5945 (hw->mac.type == ixgbe_mac_X540)) {
5946 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5947 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5948 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5949 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5950 }
5951 }
5952
5953 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5954 /* work around hardware counting issue */
5955 hwstats->gprc -= missed_rx;
5956
5957 ixgbe_update_xoff_received(adapter);
5958
5959 /* 82598 hardware only has a 32 bit counter in the high register */
5960 switch (hw->mac.type) {
5961 case ixgbe_mac_82598EB:
5962 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5963 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5964 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5965 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5966 break;
5967 case ixgbe_mac_X540:
5968 /* OS2BMC stats are X540 only*/
5969 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5970 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5971 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5972 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5973 case ixgbe_mac_82599EB:
5974 for (i = 0; i < 16; i++)
5975 adapter->hw_rx_no_dma_resources +=
5976 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5977 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5978 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5979 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5980 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5981 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5982 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5983 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5984 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5985 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5986 #ifdef IXGBE_FCOE
5987 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5988 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5989 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5990 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5991 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5992 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5993 /* Add up per cpu counters for total ddp aloc fail */
5994 if (adapter->fcoe.ddp_pool) {
5995 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5996 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5997 unsigned int cpu;
5998 u64 noddp = 0, noddp_ext_buff = 0;
5999 for_each_possible_cpu(cpu) {
6000 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6001 noddp += ddp_pool->noddp;
6002 noddp_ext_buff += ddp_pool->noddp_ext_buff;
6003 }
6004 hwstats->fcoe_noddp = noddp;
6005 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
6006 }
6007 #endif /* IXGBE_FCOE */
6008 break;
6009 default:
6010 break;
6011 }
6012 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
6013 hwstats->bprc += bprc;
6014 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
6015 if (hw->mac.type == ixgbe_mac_82598EB)
6016 hwstats->mprc -= bprc;
6017 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6018 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6019 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6020 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6021 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6022 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6023 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6024 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6025 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
6026 hwstats->lxontxc += lxon;
6027 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
6028 hwstats->lxofftxc += lxoff;
6029 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6030 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6031 /*
6032 * 82598 errata - tx of flow control packets is included in tx counters
6033 */
6034 xon_off_tot = lxon + lxoff;
6035 hwstats->gptc -= xon_off_tot;
6036 hwstats->mptc -= xon_off_tot;
6037 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6038 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6039 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6040 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6041 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6042 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6043 hwstats->ptc64 -= xon_off_tot;
6044 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6045 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6046 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6047 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6048 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6049 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
6050
6051 /* Fill out the OS statistics structure */
6052 netdev->stats.multicast = hwstats->mprc;
6053
6054 /* Rx Errors */
6055 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
6056 netdev->stats.rx_dropped = 0;
6057 netdev->stats.rx_length_errors = hwstats->rlec;
6058 netdev->stats.rx_crc_errors = hwstats->crcerrs;
6059 netdev->stats.rx_missed_errors = total_mpc;
6060 }
6061
6062 /**
6063 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
6064 * @adapter: pointer to the device adapter structure
6065 **/
6066 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
6067 {
6068 struct ixgbe_hw *hw = &adapter->hw;
6069 int i;
6070
6071 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6072 return;
6073
6074 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
6075
6076 /* if interface is down do nothing */
6077 if (test_bit(__IXGBE_DOWN, &adapter->state))
6078 return;
6079
6080 /* do nothing if we are not using signature filters */
6081 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6082 return;
6083
6084 adapter->fdir_overflow++;
6085
6086 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6087 for (i = 0; i < adapter->num_tx_queues; i++)
6088 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
6089 &(adapter->tx_ring[i]->state));
6090 /* re-enable flow director interrupts */
6091 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
6092 } else {
6093 e_err(probe, "failed to finish FDIR re-initialization, "
6094 "ignored adding FDIR ATR filters\n");
6095 }
6096 }
6097
6098 /**
6099 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
6100 * @adapter: pointer to the device adapter structure
6101 *
6102 * This function serves two purposes. First it strobes the interrupt lines
6103 * in order to make certain interrupts are occurring. Secondly it sets the
6104 * bits needed to check for TX hangs. As a result we should immediately
6105 * determine if a hang has occurred.
6106 */
6107 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
6108 {
6109 struct ixgbe_hw *hw = &adapter->hw;
6110 u64 eics = 0;
6111 int i;
6112
6113 /* If we're down, removing or resetting, just bail */
6114 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6115 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6116 test_bit(__IXGBE_RESETTING, &adapter->state))
6117 return;
6118
6119 /* Force detection of hung controller */
6120 if (netif_carrier_ok(adapter->netdev)) {
6121 for (i = 0; i < adapter->num_tx_queues; i++)
6122 set_check_for_tx_hang(adapter->tx_ring[i]);
6123 }
6124
6125 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6126 /*
6127 * for legacy and MSI interrupts don't set any bits
6128 * that are enabled for EIAM, because this operation
6129 * would set *both* EIMS and EICS for any bit in EIAM
6130 */
6131 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6132 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
6133 } else {
6134 /* get one bit for every active tx/rx interrupt vector */
6135 for (i = 0; i < adapter->num_q_vectors; i++) {
6136 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6137 if (qv->rx.ring || qv->tx.ring)
6138 eics |= ((u64)1 << i);
6139 }
6140 }
6141
6142 /* Cause software interrupt to ensure rings are cleaned */
6143 ixgbe_irq_rearm_queues(adapter, eics);
6144
6145 }
6146
6147 /**
6148 * ixgbe_watchdog_update_link - update the link status
6149 * @adapter: pointer to the device adapter structure
6150 * @link_speed: pointer to a u32 to store the link_speed
6151 **/
6152 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
6153 {
6154 struct ixgbe_hw *hw = &adapter->hw;
6155 u32 link_speed = adapter->link_speed;
6156 bool link_up = adapter->link_up;
6157 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
6158
6159 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6160 return;
6161
6162 if (hw->mac.ops.check_link) {
6163 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6164 } else {
6165 /* always assume link is up, if no check link function */
6166 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6167 link_up = true;
6168 }
6169
6170 if (adapter->ixgbe_ieee_pfc)
6171 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6172
6173 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
6174 hw->mac.ops.fc_enable(hw);
6175 ixgbe_set_rx_drop_en(adapter);
6176 }
6177
6178 if (link_up ||
6179 time_after(jiffies, (adapter->link_check_timeout +
6180 IXGBE_TRY_LINK_TIMEOUT))) {
6181 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6182 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6183 IXGBE_WRITE_FLUSH(hw);
6184 }
6185
6186 adapter->link_up = link_up;
6187 adapter->link_speed = link_speed;
6188 }
6189
6190 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6191 {
6192 #ifdef CONFIG_IXGBE_DCB
6193 struct net_device *netdev = adapter->netdev;
6194 struct dcb_app app = {
6195 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6196 .protocol = 0,
6197 };
6198 u8 up = 0;
6199
6200 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6201 up = dcb_ieee_getapp_mask(netdev, &app);
6202
6203 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6204 #endif
6205 }
6206
6207 /**
6208 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6209 * print link up message
6210 * @adapter: pointer to the device adapter structure
6211 **/
6212 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
6213 {
6214 struct net_device *netdev = adapter->netdev;
6215 struct ixgbe_hw *hw = &adapter->hw;
6216 struct net_device *upper;
6217 struct list_head *iter;
6218 u32 link_speed = adapter->link_speed;
6219 bool flow_rx, flow_tx;
6220
6221 /* only continue if link was previously down */
6222 if (netif_carrier_ok(netdev))
6223 return;
6224
6225 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
6226
6227 switch (hw->mac.type) {
6228 case ixgbe_mac_82598EB: {
6229 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6230 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6231 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6232 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6233 }
6234 break;
6235 case ixgbe_mac_X540:
6236 case ixgbe_mac_82599EB: {
6237 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6238 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6239 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6240 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6241 }
6242 break;
6243 default:
6244 flow_tx = false;
6245 flow_rx = false;
6246 break;
6247 }
6248
6249 adapter->last_rx_ptp_check = jiffies;
6250
6251 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6252 ixgbe_ptp_start_cyclecounter(adapter);
6253
6254 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6255 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6256 "10 Gbps" :
6257 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6258 "1 Gbps" :
6259 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6260 "100 Mbps" :
6261 "unknown speed"))),
6262 ((flow_rx && flow_tx) ? "RX/TX" :
6263 (flow_rx ? "RX" :
6264 (flow_tx ? "TX" : "None"))));
6265
6266 netif_carrier_on(netdev);
6267 ixgbe_check_vf_rate_limit(adapter);
6268
6269 /* enable transmits */
6270 netif_tx_wake_all_queues(adapter->netdev);
6271
6272 /* enable any upper devices */
6273 rtnl_lock();
6274 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6275 if (netif_is_macvlan(upper)) {
6276 struct macvlan_dev *vlan = netdev_priv(upper);
6277
6278 if (vlan->fwd_priv)
6279 netif_tx_wake_all_queues(upper);
6280 }
6281 }
6282 rtnl_unlock();
6283
6284 /* update the default user priority for VFs */
6285 ixgbe_update_default_up(adapter);
6286
6287 /* ping all the active vfs to let them know link has changed */
6288 ixgbe_ping_all_vfs(adapter);
6289 }
6290
6291 /**
6292 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6293 * print link down message
6294 * @adapter: pointer to the adapter structure
6295 **/
6296 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
6297 {
6298 struct net_device *netdev = adapter->netdev;
6299 struct ixgbe_hw *hw = &adapter->hw;
6300
6301 adapter->link_up = false;
6302 adapter->link_speed = 0;
6303
6304 /* only continue if link was up previously */
6305 if (!netif_carrier_ok(netdev))
6306 return;
6307
6308 /* poll for SFP+ cable when link is down */
6309 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6310 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6311
6312 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6313 ixgbe_ptp_start_cyclecounter(adapter);
6314
6315 e_info(drv, "NIC Link is Down\n");
6316 netif_carrier_off(netdev);
6317
6318 /* ping all the active vfs to let them know link has changed */
6319 ixgbe_ping_all_vfs(adapter);
6320 }
6321
6322 /**
6323 * ixgbe_watchdog_flush_tx - flush queues on link down
6324 * @adapter: pointer to the device adapter structure
6325 **/
6326 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6327 {
6328 int i;
6329 int some_tx_pending = 0;
6330
6331 if (!netif_carrier_ok(adapter->netdev)) {
6332 for (i = 0; i < adapter->num_tx_queues; i++) {
6333 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6334 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6335 some_tx_pending = 1;
6336 break;
6337 }
6338 }
6339
6340 if (some_tx_pending) {
6341 /* We've lost link, so the controller stops DMA,
6342 * but we've got queued Tx work that's never going
6343 * to get done, so reset controller to flush Tx.
6344 * (Do the reset outside of interrupt context).
6345 */
6346 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
6347 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6348 }
6349 }
6350 }
6351
6352 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6353 {
6354 u32 ssvpc;
6355
6356 /* Do not perform spoof check for 82598 or if not in IOV mode */
6357 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6358 adapter->num_vfs == 0)
6359 return;
6360
6361 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6362
6363 /*
6364 * ssvpc register is cleared on read, if zero then no
6365 * spoofed packets in the last interval.
6366 */
6367 if (!ssvpc)
6368 return;
6369
6370 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
6371 }
6372
6373 /**
6374 * ixgbe_watchdog_subtask - check and bring link up
6375 * @adapter: pointer to the device adapter structure
6376 **/
6377 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6378 {
6379 /* if interface is down, removing or resetting, do nothing */
6380 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6381 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6382 test_bit(__IXGBE_RESETTING, &adapter->state))
6383 return;
6384
6385 ixgbe_watchdog_update_link(adapter);
6386
6387 if (adapter->link_up)
6388 ixgbe_watchdog_link_is_up(adapter);
6389 else
6390 ixgbe_watchdog_link_is_down(adapter);
6391
6392 ixgbe_spoof_check(adapter);
6393 ixgbe_update_stats(adapter);
6394
6395 ixgbe_watchdog_flush_tx(adapter);
6396 }
6397
6398 /**
6399 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6400 * @adapter: the ixgbe adapter structure
6401 **/
6402 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6403 {
6404 struct ixgbe_hw *hw = &adapter->hw;
6405 s32 err;
6406
6407 /* not searching for SFP so there is nothing to do here */
6408 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6409 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6410 return;
6411
6412 /* someone else is in init, wait until next service event */
6413 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6414 return;
6415
6416 err = hw->phy.ops.identify_sfp(hw);
6417 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6418 goto sfp_out;
6419
6420 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6421 /* If no cable is present, then we need to reset
6422 * the next time we find a good cable. */
6423 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6424 }
6425
6426 /* exit on error */
6427 if (err)
6428 goto sfp_out;
6429
6430 /* exit if reset not needed */
6431 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6432 goto sfp_out;
6433
6434 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6435
6436 /*
6437 * A module may be identified correctly, but the EEPROM may not have
6438 * support for that module. setup_sfp() will fail in that case, so
6439 * we should not allow that module to load.
6440 */
6441 if (hw->mac.type == ixgbe_mac_82598EB)
6442 err = hw->phy.ops.reset(hw);
6443 else
6444 err = hw->mac.ops.setup_sfp(hw);
6445
6446 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6447 goto sfp_out;
6448
6449 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6450 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6451
6452 sfp_out:
6453 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6454
6455 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6456 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6457 e_dev_err("failed to initialize because an unsupported "
6458 "SFP+ module type was detected.\n");
6459 e_dev_err("Reload the driver after installing a "
6460 "supported module.\n");
6461 unregister_netdev(adapter->netdev);
6462 }
6463 }
6464
6465 /**
6466 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6467 * @adapter: the ixgbe adapter structure
6468 **/
6469 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6470 {
6471 struct ixgbe_hw *hw = &adapter->hw;
6472 u32 speed;
6473 bool autoneg = false;
6474
6475 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6476 return;
6477
6478 /* someone else is in init, wait until next service event */
6479 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6480 return;
6481
6482 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6483
6484 speed = hw->phy.autoneg_advertised;
6485 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
6486 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
6487
6488 /* setup the highest link when no autoneg */
6489 if (!autoneg) {
6490 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6491 speed = IXGBE_LINK_SPEED_10GB_FULL;
6492 }
6493 }
6494
6495 if (hw->mac.ops.setup_link)
6496 hw->mac.ops.setup_link(hw, speed, true);
6497
6498 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6499 adapter->link_check_timeout = jiffies;
6500 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6501 }
6502
6503 #ifdef CONFIG_PCI_IOV
6504 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6505 {
6506 int vf;
6507 struct ixgbe_hw *hw = &adapter->hw;
6508 struct net_device *netdev = adapter->netdev;
6509 u32 gpc;
6510 u32 ciaa, ciad;
6511
6512 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6513 if (gpc) /* If incrementing then no need for the check below */
6514 return;
6515 /*
6516 * Check to see if a bad DMA write target from an errant or
6517 * malicious VF has caused a PCIe error. If so then we can
6518 * issue a VFLR to the offending VF(s) and then resume without
6519 * requesting a full slot reset.
6520 */
6521
6522 for (vf = 0; vf < adapter->num_vfs; vf++) {
6523 ciaa = (vf << 16) | 0x80000000;
6524 /* 32 bit read so align, we really want status at offset 6 */
6525 ciaa |= PCI_COMMAND;
6526 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6527 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6528 ciaa &= 0x7FFFFFFF;
6529 /* disable debug mode asap after reading data */
6530 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6531 /* Get the upper 16 bits which will be the PCI status reg */
6532 ciad >>= 16;
6533 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6534 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6535 /* Issue VFLR */
6536 ciaa = (vf << 16) | 0x80000000;
6537 ciaa |= 0xA8;
6538 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6539 ciad = 0x00008000; /* VFLR */
6540 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6541 ciaa &= 0x7FFFFFFF;
6542 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6543 }
6544 }
6545 }
6546
6547 #endif
6548 /**
6549 * ixgbe_service_timer - Timer Call-back
6550 * @data: pointer to adapter cast into an unsigned long
6551 **/
6552 static void ixgbe_service_timer(unsigned long data)
6553 {
6554 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6555 unsigned long next_event_offset;
6556 bool ready = true;
6557
6558 /* poll faster when waiting for link */
6559 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6560 next_event_offset = HZ / 10;
6561 else
6562 next_event_offset = HZ * 2;
6563
6564 #ifdef CONFIG_PCI_IOV
6565 /*
6566 * don't bother with SR-IOV VF DMA hang check if there are
6567 * no VFs or the link is down
6568 */
6569 if (!adapter->num_vfs ||
6570 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6571 goto normal_timer_service;
6572
6573 /* If we have VFs allocated then we must check for DMA hangs */
6574 ixgbe_check_for_bad_vf(adapter);
6575 next_event_offset = HZ / 50;
6576 adapter->timer_event_accumulator++;
6577
6578 if (adapter->timer_event_accumulator >= 100)
6579 adapter->timer_event_accumulator = 0;
6580 else
6581 ready = false;
6582
6583 normal_timer_service:
6584 #endif
6585 /* Reset the timer */
6586 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6587
6588 if (ready)
6589 ixgbe_service_event_schedule(adapter);
6590 }
6591
6592 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6593 {
6594 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6595 return;
6596
6597 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6598
6599 /* If we're already down, removing or resetting, just bail */
6600 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6601 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6602 test_bit(__IXGBE_RESETTING, &adapter->state))
6603 return;
6604
6605 ixgbe_dump(adapter);
6606 netdev_err(adapter->netdev, "Reset adapter\n");
6607 adapter->tx_timeout_count++;
6608
6609 rtnl_lock();
6610 ixgbe_reinit_locked(adapter);
6611 rtnl_unlock();
6612 }
6613
6614 /**
6615 * ixgbe_service_task - manages and runs subtasks
6616 * @work: pointer to work_struct containing our data
6617 **/
6618 static void ixgbe_service_task(struct work_struct *work)
6619 {
6620 struct ixgbe_adapter *adapter = container_of(work,
6621 struct ixgbe_adapter,
6622 service_task);
6623 if (ixgbe_removed(adapter->hw.hw_addr)) {
6624 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6625 rtnl_lock();
6626 ixgbe_down(adapter);
6627 rtnl_unlock();
6628 }
6629 ixgbe_service_event_complete(adapter);
6630 return;
6631 }
6632 ixgbe_reset_subtask(adapter);
6633 ixgbe_sfp_detection_subtask(adapter);
6634 ixgbe_sfp_link_config_subtask(adapter);
6635 ixgbe_check_overtemp_subtask(adapter);
6636 ixgbe_watchdog_subtask(adapter);
6637 ixgbe_fdir_reinit_subtask(adapter);
6638 ixgbe_check_hang_subtask(adapter);
6639
6640 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
6641 ixgbe_ptp_overflow_check(adapter);
6642 ixgbe_ptp_rx_hang(adapter);
6643 }
6644
6645 ixgbe_service_event_complete(adapter);
6646 }
6647
6648 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6649 struct ixgbe_tx_buffer *first,
6650 u8 *hdr_len)
6651 {
6652 struct sk_buff *skb = first->skb;
6653 u32 vlan_macip_lens, type_tucmd;
6654 u32 mss_l4len_idx, l4len;
6655 int err;
6656
6657 if (skb->ip_summed != CHECKSUM_PARTIAL)
6658 return 0;
6659
6660 if (!skb_is_gso(skb))
6661 return 0;
6662
6663 err = skb_cow_head(skb, 0);
6664 if (err < 0)
6665 return err;
6666
6667 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6668 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6669
6670 if (first->protocol == htons(ETH_P_IP)) {
6671 struct iphdr *iph = ip_hdr(skb);
6672 iph->tot_len = 0;
6673 iph->check = 0;
6674 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6675 iph->daddr, 0,
6676 IPPROTO_TCP,
6677 0);
6678 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6679 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6680 IXGBE_TX_FLAGS_CSUM |
6681 IXGBE_TX_FLAGS_IPV4;
6682 } else if (skb_is_gso_v6(skb)) {
6683 ipv6_hdr(skb)->payload_len = 0;
6684 tcp_hdr(skb)->check =
6685 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6686 &ipv6_hdr(skb)->daddr,
6687 0, IPPROTO_TCP, 0);
6688 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6689 IXGBE_TX_FLAGS_CSUM;
6690 }
6691
6692 /* compute header lengths */
6693 l4len = tcp_hdrlen(skb);
6694 *hdr_len = skb_transport_offset(skb) + l4len;
6695
6696 /* update gso size and bytecount with header size */
6697 first->gso_segs = skb_shinfo(skb)->gso_segs;
6698 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6699
6700 /* mss_l4len_id: use 0 as index for TSO */
6701 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6702 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6703
6704 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6705 vlan_macip_lens = skb_network_header_len(skb);
6706 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6707 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6708
6709 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6710 mss_l4len_idx);
6711
6712 return 1;
6713 }
6714
6715 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6716 struct ixgbe_tx_buffer *first)
6717 {
6718 struct sk_buff *skb = first->skb;
6719 u32 vlan_macip_lens = 0;
6720 u32 mss_l4len_idx = 0;
6721 u32 type_tucmd = 0;
6722
6723 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6724 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6725 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6726 return;
6727 } else {
6728 u8 l4_hdr = 0;
6729 switch (first->protocol) {
6730 case htons(ETH_P_IP):
6731 vlan_macip_lens |= skb_network_header_len(skb);
6732 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6733 l4_hdr = ip_hdr(skb)->protocol;
6734 break;
6735 case htons(ETH_P_IPV6):
6736 vlan_macip_lens |= skb_network_header_len(skb);
6737 l4_hdr = ipv6_hdr(skb)->nexthdr;
6738 break;
6739 default:
6740 if (unlikely(net_ratelimit())) {
6741 dev_warn(tx_ring->dev,
6742 "partial checksum but proto=%x!\n",
6743 first->protocol);
6744 }
6745 break;
6746 }
6747
6748 switch (l4_hdr) {
6749 case IPPROTO_TCP:
6750 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6751 mss_l4len_idx = tcp_hdrlen(skb) <<
6752 IXGBE_ADVTXD_L4LEN_SHIFT;
6753 break;
6754 case IPPROTO_SCTP:
6755 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6756 mss_l4len_idx = sizeof(struct sctphdr) <<
6757 IXGBE_ADVTXD_L4LEN_SHIFT;
6758 break;
6759 case IPPROTO_UDP:
6760 mss_l4len_idx = sizeof(struct udphdr) <<
6761 IXGBE_ADVTXD_L4LEN_SHIFT;
6762 break;
6763 default:
6764 if (unlikely(net_ratelimit())) {
6765 dev_warn(tx_ring->dev,
6766 "partial checksum but l4 proto=%x!\n",
6767 l4_hdr);
6768 }
6769 break;
6770 }
6771
6772 /* update TX checksum flag */
6773 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
6774 }
6775
6776 /* vlan_macip_lens: MACLEN, VLAN tag */
6777 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6778 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6779
6780 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6781 type_tucmd, mss_l4len_idx);
6782 }
6783
6784 #define IXGBE_SET_FLAG(_input, _flag, _result) \
6785 ((_flag <= _result) ? \
6786 ((u32)(_input & _flag) * (_result / _flag)) : \
6787 ((u32)(_input & _flag) / (_flag / _result)))
6788
6789 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6790 {
6791 /* set type for advanced descriptor with frame checksum insertion */
6792 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6793 IXGBE_ADVTXD_DCMD_DEXT |
6794 IXGBE_ADVTXD_DCMD_IFCS;
6795
6796 /* set HW vlan bit if vlan is present */
6797 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6798 IXGBE_ADVTXD_DCMD_VLE);
6799
6800 /* set segmentation enable bits for TSO/FSO */
6801 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6802 IXGBE_ADVTXD_DCMD_TSE);
6803
6804 /* set timestamp bit if present */
6805 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6806 IXGBE_ADVTXD_MAC_TSTAMP);
6807
6808 /* insert frame checksum */
6809 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
6810
6811 return cmd_type;
6812 }
6813
6814 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6815 u32 tx_flags, unsigned int paylen)
6816 {
6817 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
6818
6819 /* enable L4 checksum for TSO and TX checksum offload */
6820 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6821 IXGBE_TX_FLAGS_CSUM,
6822 IXGBE_ADVTXD_POPTS_TXSM);
6823
6824 /* enble IPv4 checksum for TSO */
6825 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6826 IXGBE_TX_FLAGS_IPV4,
6827 IXGBE_ADVTXD_POPTS_IXSM);
6828
6829 /*
6830 * Check Context must be set if Tx switch is enabled, which it
6831 * always is for case where virtual functions are running
6832 */
6833 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6834 IXGBE_TX_FLAGS_CC,
6835 IXGBE_ADVTXD_CC);
6836
6837 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6838 }
6839
6840 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6841 {
6842 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6843
6844 /* Herbert's original patch had:
6845 * smp_mb__after_netif_stop_queue();
6846 * but since that doesn't exist yet, just open code it.
6847 */
6848 smp_mb();
6849
6850 /* We need to check again in a case another CPU has just
6851 * made room available.
6852 */
6853 if (likely(ixgbe_desc_unused(tx_ring) < size))
6854 return -EBUSY;
6855
6856 /* A reprieve! - use start_queue because it doesn't call schedule */
6857 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6858 ++tx_ring->tx_stats.restart_queue;
6859 return 0;
6860 }
6861
6862 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6863 {
6864 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6865 return 0;
6866
6867 return __ixgbe_maybe_stop_tx(tx_ring, size);
6868 }
6869
6870 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6871 IXGBE_TXD_CMD_RS)
6872
6873 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6874 struct ixgbe_tx_buffer *first,
6875 const u8 hdr_len)
6876 {
6877 struct sk_buff *skb = first->skb;
6878 struct ixgbe_tx_buffer *tx_buffer;
6879 union ixgbe_adv_tx_desc *tx_desc;
6880 struct skb_frag_struct *frag;
6881 dma_addr_t dma;
6882 unsigned int data_len, size;
6883 u32 tx_flags = first->tx_flags;
6884 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
6885 u16 i = tx_ring->next_to_use;
6886
6887 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6888
6889 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6890
6891 size = skb_headlen(skb);
6892 data_len = skb->data_len;
6893
6894 #ifdef IXGBE_FCOE
6895 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6896 if (data_len < sizeof(struct fcoe_crc_eof)) {
6897 size -= sizeof(struct fcoe_crc_eof) - data_len;
6898 data_len = 0;
6899 } else {
6900 data_len -= sizeof(struct fcoe_crc_eof);
6901 }
6902 }
6903
6904 #endif
6905 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6906
6907 tx_buffer = first;
6908
6909 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6910 if (dma_mapping_error(tx_ring->dev, dma))
6911 goto dma_error;
6912
6913 /* record length, and DMA address */
6914 dma_unmap_len_set(tx_buffer, len, size);
6915 dma_unmap_addr_set(tx_buffer, dma, dma);
6916
6917 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6918
6919 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6920 tx_desc->read.cmd_type_len =
6921 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
6922
6923 i++;
6924 tx_desc++;
6925 if (i == tx_ring->count) {
6926 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6927 i = 0;
6928 }
6929 tx_desc->read.olinfo_status = 0;
6930
6931 dma += IXGBE_MAX_DATA_PER_TXD;
6932 size -= IXGBE_MAX_DATA_PER_TXD;
6933
6934 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6935 }
6936
6937 if (likely(!data_len))
6938 break;
6939
6940 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6941
6942 i++;
6943 tx_desc++;
6944 if (i == tx_ring->count) {
6945 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6946 i = 0;
6947 }
6948 tx_desc->read.olinfo_status = 0;
6949
6950 #ifdef IXGBE_FCOE
6951 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6952 #else
6953 size = skb_frag_size(frag);
6954 #endif
6955 data_len -= size;
6956
6957 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6958 DMA_TO_DEVICE);
6959
6960 tx_buffer = &tx_ring->tx_buffer_info[i];
6961 }
6962
6963 /* write last descriptor with RS and EOP bits */
6964 cmd_type |= size | IXGBE_TXD_CMD;
6965 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6966
6967 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6968
6969 /* set the timestamp */
6970 first->time_stamp = jiffies;
6971
6972 /*
6973 * Force memory writes to complete before letting h/w know there
6974 * are new descriptors to fetch. (Only applicable for weak-ordered
6975 * memory model archs, such as IA-64).
6976 *
6977 * We also need this memory barrier to make certain all of the
6978 * status bits have been updated before next_to_watch is written.
6979 */
6980 wmb();
6981
6982 /* set next_to_watch value indicating a packet is present */
6983 first->next_to_watch = tx_desc;
6984
6985 i++;
6986 if (i == tx_ring->count)
6987 i = 0;
6988
6989 tx_ring->next_to_use = i;
6990
6991 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6992
6993 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
6994 /* notify HW of packet */
6995 ixgbe_write_tail(tx_ring, i);
6996 }
6997
6998 return;
6999 dma_error:
7000 dev_err(tx_ring->dev, "TX DMA map failed\n");
7001
7002 /* clear dma mappings for failed tx_buffer_info map */
7003 for (;;) {
7004 tx_buffer = &tx_ring->tx_buffer_info[i];
7005 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7006 if (tx_buffer == first)
7007 break;
7008 if (i == 0)
7009 i = tx_ring->count;
7010 i--;
7011 }
7012
7013 tx_ring->next_to_use = i;
7014 }
7015
7016 static void ixgbe_atr(struct ixgbe_ring *ring,
7017 struct ixgbe_tx_buffer *first)
7018 {
7019 struct ixgbe_q_vector *q_vector = ring->q_vector;
7020 union ixgbe_atr_hash_dword input = { .dword = 0 };
7021 union ixgbe_atr_hash_dword common = { .dword = 0 };
7022 union {
7023 unsigned char *network;
7024 struct iphdr *ipv4;
7025 struct ipv6hdr *ipv6;
7026 } hdr;
7027 struct tcphdr *th;
7028 __be16 vlan_id;
7029
7030 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7031 if (!q_vector)
7032 return;
7033
7034 /* do nothing if sampling is disabled */
7035 if (!ring->atr_sample_rate)
7036 return;
7037
7038 ring->atr_count++;
7039
7040 /* snag network header to get L4 type and address */
7041 hdr.network = skb_network_header(first->skb);
7042
7043 /* Currently only IPv4/IPv6 with TCP is supported */
7044 if ((first->protocol != htons(ETH_P_IPV6) ||
7045 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
7046 (first->protocol != htons(ETH_P_IP) ||
7047 hdr.ipv4->protocol != IPPROTO_TCP))
7048 return;
7049
7050 th = tcp_hdr(first->skb);
7051
7052 /* skip this packet since it is invalid or the socket is closing */
7053 if (!th || th->fin)
7054 return;
7055
7056 /* sample on all syn packets or once every atr sample count */
7057 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7058 return;
7059
7060 /* reset sample count */
7061 ring->atr_count = 0;
7062
7063 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
7064
7065 /*
7066 * src and dst are inverted, think how the receiver sees them
7067 *
7068 * The input is broken into two sections, a non-compressed section
7069 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7070 * is XORed together and stored in the compressed dword.
7071 */
7072 input.formatted.vlan_id = vlan_id;
7073
7074 /*
7075 * since src port and flex bytes occupy the same word XOR them together
7076 * and write the value to source port portion of compressed dword
7077 */
7078 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
7079 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
7080 else
7081 common.port.src ^= th->dest ^ first->protocol;
7082 common.port.dst ^= th->source;
7083
7084 if (first->protocol == htons(ETH_P_IP)) {
7085 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7086 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7087 } else {
7088 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7089 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7090 hdr.ipv6->saddr.s6_addr32[1] ^
7091 hdr.ipv6->saddr.s6_addr32[2] ^
7092 hdr.ipv6->saddr.s6_addr32[3] ^
7093 hdr.ipv6->daddr.s6_addr32[0] ^
7094 hdr.ipv6->daddr.s6_addr32[1] ^
7095 hdr.ipv6->daddr.s6_addr32[2] ^
7096 hdr.ipv6->daddr.s6_addr32[3];
7097 }
7098
7099 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
7100 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7101 input, common, ring->queue_index);
7102 }
7103
7104 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
7105 void *accel_priv, select_queue_fallback_t fallback)
7106 {
7107 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7108 #ifdef IXGBE_FCOE
7109 struct ixgbe_adapter *adapter;
7110 struct ixgbe_ring_feature *f;
7111 int txq;
7112 #endif
7113
7114 if (fwd_adapter)
7115 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7116
7117 #ifdef IXGBE_FCOE
7118
7119 /*
7120 * only execute the code below if protocol is FCoE
7121 * or FIP and we have FCoE enabled on the adapter
7122 */
7123 switch (vlan_get_protocol(skb)) {
7124 case htons(ETH_P_FCOE):
7125 case htons(ETH_P_FIP):
7126 adapter = netdev_priv(dev);
7127
7128 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7129 break;
7130 default:
7131 return fallback(dev, skb);
7132 }
7133
7134 f = &adapter->ring_feature[RING_F_FCOE];
7135
7136 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7137 smp_processor_id();
7138
7139 while (txq >= f->indices)
7140 txq -= f->indices;
7141
7142 return txq + f->offset;
7143 #else
7144 return fallback(dev, skb);
7145 #endif
7146 }
7147
7148 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
7149 struct ixgbe_adapter *adapter,
7150 struct ixgbe_ring *tx_ring)
7151 {
7152 struct ixgbe_tx_buffer *first;
7153 int tso;
7154 u32 tx_flags = 0;
7155 unsigned short f;
7156 u16 count = TXD_USE_COUNT(skb_headlen(skb));
7157 __be16 protocol = skb->protocol;
7158 u8 hdr_len = 0;
7159
7160 /*
7161 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
7162 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
7163 * + 2 desc gap to keep tail from touching head,
7164 * + 1 desc for context descriptor,
7165 * otherwise try next time
7166 */
7167 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7168 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7169
7170 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7171 tx_ring->tx_stats.tx_busy++;
7172 return NETDEV_TX_BUSY;
7173 }
7174
7175 /* record the location of the first descriptor for this packet */
7176 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7177 first->skb = skb;
7178 first->bytecount = skb->len;
7179 first->gso_segs = 1;
7180
7181 /* if we have a HW VLAN tag being added default to the HW one */
7182 if (vlan_tx_tag_present(skb)) {
7183 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7184 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7185 /* else if it is a SW VLAN check the next protocol and store the tag */
7186 } else if (protocol == htons(ETH_P_8021Q)) {
7187 struct vlan_hdr *vhdr, _vhdr;
7188 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7189 if (!vhdr)
7190 goto out_drop;
7191
7192 protocol = vhdr->h_vlan_encapsulated_proto;
7193 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7194 IXGBE_TX_FLAGS_VLAN_SHIFT;
7195 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7196 }
7197
7198 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
7199 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7200 &adapter->state))) {
7201 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7202 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
7203
7204 /* schedule check for Tx timestamp */
7205 adapter->ptp_tx_skb = skb_get(skb);
7206 adapter->ptp_tx_start = jiffies;
7207 schedule_work(&adapter->ptp_tx_work);
7208 }
7209
7210 skb_tx_timestamp(skb);
7211
7212 #ifdef CONFIG_PCI_IOV
7213 /*
7214 * Use the l2switch_enable flag - would be false if the DMA
7215 * Tx switch had been disabled.
7216 */
7217 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7218 tx_flags |= IXGBE_TX_FLAGS_CC;
7219
7220 #endif
7221 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
7222 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7223 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7224 (skb->priority != TC_PRIO_CONTROL))) {
7225 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
7226 tx_flags |= (skb->priority & 0x7) <<
7227 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
7228 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7229 struct vlan_ethhdr *vhdr;
7230
7231 if (skb_cow_head(skb, 0))
7232 goto out_drop;
7233 vhdr = (struct vlan_ethhdr *)skb->data;
7234 vhdr->h_vlan_TCI = htons(tx_flags >>
7235 IXGBE_TX_FLAGS_VLAN_SHIFT);
7236 } else {
7237 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7238 }
7239 }
7240
7241 /* record initial flags and protocol */
7242 first->tx_flags = tx_flags;
7243 first->protocol = protocol;
7244
7245 #ifdef IXGBE_FCOE
7246 /* setup tx offload for FCoE */
7247 if ((protocol == htons(ETH_P_FCOE)) &&
7248 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
7249 tso = ixgbe_fso(tx_ring, first, &hdr_len);
7250 if (tso < 0)
7251 goto out_drop;
7252
7253 goto xmit_fcoe;
7254 }
7255
7256 #endif /* IXGBE_FCOE */
7257 tso = ixgbe_tso(tx_ring, first, &hdr_len);
7258 if (tso < 0)
7259 goto out_drop;
7260 else if (!tso)
7261 ixgbe_tx_csum(tx_ring, first);
7262
7263 /* add the ATR filter if ATR is on */
7264 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7265 ixgbe_atr(tx_ring, first);
7266
7267 #ifdef IXGBE_FCOE
7268 xmit_fcoe:
7269 #endif /* IXGBE_FCOE */
7270 ixgbe_tx_map(tx_ring, first, hdr_len);
7271
7272 return NETDEV_TX_OK;
7273
7274 out_drop:
7275 dev_kfree_skb_any(first->skb);
7276 first->skb = NULL;
7277
7278 return NETDEV_TX_OK;
7279 }
7280
7281 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7282 struct net_device *netdev,
7283 struct ixgbe_ring *ring)
7284 {
7285 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7286 struct ixgbe_ring *tx_ring;
7287
7288 /*
7289 * The minimum packet size for olinfo paylen is 17 so pad the skb
7290 * in order to meet this minimum size requirement.
7291 */
7292 if (unlikely(skb->len < 17)) {
7293 if (skb_pad(skb, 17 - skb->len))
7294 return NETDEV_TX_OK;
7295 skb->len = 17;
7296 skb_set_tail_pointer(skb, 17);
7297 }
7298
7299 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7300
7301 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
7302 }
7303
7304 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7305 struct net_device *netdev)
7306 {
7307 return __ixgbe_xmit_frame(skb, netdev, NULL);
7308 }
7309
7310 /**
7311 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7312 * @netdev: network interface device structure
7313 * @p: pointer to an address structure
7314 *
7315 * Returns 0 on success, negative on failure
7316 **/
7317 static int ixgbe_set_mac(struct net_device *netdev, void *p)
7318 {
7319 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7320 struct ixgbe_hw *hw = &adapter->hw;
7321 struct sockaddr *addr = p;
7322 int ret;
7323
7324 if (!is_valid_ether_addr(addr->sa_data))
7325 return -EADDRNOTAVAIL;
7326
7327 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7328 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
7329 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
7330
7331 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7332 return ret > 0 ? 0 : ret;
7333 }
7334
7335 static int
7336 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7337 {
7338 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7339 struct ixgbe_hw *hw = &adapter->hw;
7340 u16 value;
7341 int rc;
7342
7343 if (prtad != hw->phy.mdio.prtad)
7344 return -EINVAL;
7345 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7346 if (!rc)
7347 rc = value;
7348 return rc;
7349 }
7350
7351 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7352 u16 addr, u16 value)
7353 {
7354 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7355 struct ixgbe_hw *hw = &adapter->hw;
7356
7357 if (prtad != hw->phy.mdio.prtad)
7358 return -EINVAL;
7359 return hw->phy.ops.write_reg(hw, addr, devad, value);
7360 }
7361
7362 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7363 {
7364 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7365
7366 switch (cmd) {
7367 case SIOCSHWTSTAMP:
7368 return ixgbe_ptp_set_ts_config(adapter, req);
7369 case SIOCGHWTSTAMP:
7370 return ixgbe_ptp_get_ts_config(adapter, req);
7371 default:
7372 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7373 }
7374 }
7375
7376 /**
7377 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
7378 * netdev->dev_addrs
7379 * @netdev: network interface device structure
7380 *
7381 * Returns non-zero on failure
7382 **/
7383 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7384 {
7385 int err = 0;
7386 struct ixgbe_adapter *adapter = netdev_priv(dev);
7387 struct ixgbe_hw *hw = &adapter->hw;
7388
7389 if (is_valid_ether_addr(hw->mac.san_addr)) {
7390 rtnl_lock();
7391 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
7392 rtnl_unlock();
7393
7394 /* update SAN MAC vmdq pool selection */
7395 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
7396 }
7397 return err;
7398 }
7399
7400 /**
7401 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7402 * netdev->dev_addrs
7403 * @netdev: network interface device structure
7404 *
7405 * Returns non-zero on failure
7406 **/
7407 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7408 {
7409 int err = 0;
7410 struct ixgbe_adapter *adapter = netdev_priv(dev);
7411 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7412
7413 if (is_valid_ether_addr(mac->san_addr)) {
7414 rtnl_lock();
7415 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7416 rtnl_unlock();
7417 }
7418 return err;
7419 }
7420
7421 #ifdef CONFIG_NET_POLL_CONTROLLER
7422 /*
7423 * Polling 'interrupt' - used by things like netconsole to send skbs
7424 * without having to re-enable interrupts. It's not called while
7425 * the interrupt routine is executing.
7426 */
7427 static void ixgbe_netpoll(struct net_device *netdev)
7428 {
7429 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7430 int i;
7431
7432 /* if interface is down do nothing */
7433 if (test_bit(__IXGBE_DOWN, &adapter->state))
7434 return;
7435
7436 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
7437 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7438 for (i = 0; i < adapter->num_q_vectors; i++)
7439 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
7440 } else {
7441 ixgbe_intr(adapter->pdev->irq, netdev);
7442 }
7443 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7444 }
7445
7446 #endif
7447 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7448 struct rtnl_link_stats64 *stats)
7449 {
7450 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7451 int i;
7452
7453 rcu_read_lock();
7454 for (i = 0; i < adapter->num_rx_queues; i++) {
7455 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7456 u64 bytes, packets;
7457 unsigned int start;
7458
7459 if (ring) {
7460 do {
7461 start = u64_stats_fetch_begin_irq(&ring->syncp);
7462 packets = ring->stats.packets;
7463 bytes = ring->stats.bytes;
7464 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
7465 stats->rx_packets += packets;
7466 stats->rx_bytes += bytes;
7467 }
7468 }
7469
7470 for (i = 0; i < adapter->num_tx_queues; i++) {
7471 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7472 u64 bytes, packets;
7473 unsigned int start;
7474
7475 if (ring) {
7476 do {
7477 start = u64_stats_fetch_begin_irq(&ring->syncp);
7478 packets = ring->stats.packets;
7479 bytes = ring->stats.bytes;
7480 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
7481 stats->tx_packets += packets;
7482 stats->tx_bytes += bytes;
7483 }
7484 }
7485 rcu_read_unlock();
7486 /* following stats updated by ixgbe_watchdog_task() */
7487 stats->multicast = netdev->stats.multicast;
7488 stats->rx_errors = netdev->stats.rx_errors;
7489 stats->rx_length_errors = netdev->stats.rx_length_errors;
7490 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7491 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7492 return stats;
7493 }
7494
7495 #ifdef CONFIG_IXGBE_DCB
7496 /**
7497 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7498 * @adapter: pointer to ixgbe_adapter
7499 * @tc: number of traffic classes currently enabled
7500 *
7501 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7502 * 802.1Q priority maps to a packet buffer that exists.
7503 */
7504 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7505 {
7506 struct ixgbe_hw *hw = &adapter->hw;
7507 u32 reg, rsave;
7508 int i;
7509
7510 /* 82598 have a static priority to TC mapping that can not
7511 * be changed so no validation is needed.
7512 */
7513 if (hw->mac.type == ixgbe_mac_82598EB)
7514 return;
7515
7516 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7517 rsave = reg;
7518
7519 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7520 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7521
7522 /* If up2tc is out of bounds default to zero */
7523 if (up2tc > tc)
7524 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7525 }
7526
7527 if (reg != rsave)
7528 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7529
7530 return;
7531 }
7532
7533 /**
7534 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7535 * @adapter: Pointer to adapter struct
7536 *
7537 * Populate the netdev user priority to tc map
7538 */
7539 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7540 {
7541 struct net_device *dev = adapter->netdev;
7542 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7543 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7544 u8 prio;
7545
7546 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7547 u8 tc = 0;
7548
7549 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7550 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7551 else if (ets)
7552 tc = ets->prio_tc[prio];
7553
7554 netdev_set_prio_tc_map(dev, prio, tc);
7555 }
7556 }
7557
7558 #endif /* CONFIG_IXGBE_DCB */
7559 /**
7560 * ixgbe_setup_tc - configure net_device for multiple traffic classes
7561 *
7562 * @netdev: net device to configure
7563 * @tc: number of traffic classes to enable
7564 */
7565 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7566 {
7567 struct ixgbe_adapter *adapter = netdev_priv(dev);
7568 struct ixgbe_hw *hw = &adapter->hw;
7569 bool pools;
7570
7571 /* Hardware supports up to 8 traffic classes */
7572 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
7573 (hw->mac.type == ixgbe_mac_82598EB &&
7574 tc < MAX_TRAFFIC_CLASS))
7575 return -EINVAL;
7576
7577 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7578 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7579 return -EBUSY;
7580
7581 /* Hardware has to reinitialize queues and interrupts to
7582 * match packet buffer alignment. Unfortunately, the
7583 * hardware is not flexible enough to do this dynamically.
7584 */
7585 if (netif_running(dev))
7586 ixgbe_close(dev);
7587 ixgbe_clear_interrupt_scheme(adapter);
7588
7589 #ifdef CONFIG_IXGBE_DCB
7590 if (tc) {
7591 netdev_set_num_tc(dev, tc);
7592 ixgbe_set_prio_tc_map(adapter);
7593
7594 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7595
7596 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7597 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
7598 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7599 }
7600 } else {
7601 netdev_reset_tc(dev);
7602
7603 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7604 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7605
7606 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7607
7608 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7609 adapter->dcb_cfg.pfc_mode_enable = false;
7610 }
7611
7612 ixgbe_validate_rtr(adapter, tc);
7613
7614 #endif /* CONFIG_IXGBE_DCB */
7615 ixgbe_init_interrupt_scheme(adapter);
7616
7617 if (netif_running(dev))
7618 return ixgbe_open(dev);
7619
7620 return 0;
7621 }
7622
7623 #ifdef CONFIG_PCI_IOV
7624 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7625 {
7626 struct net_device *netdev = adapter->netdev;
7627
7628 rtnl_lock();
7629 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
7630 rtnl_unlock();
7631 }
7632
7633 #endif
7634 void ixgbe_do_reset(struct net_device *netdev)
7635 {
7636 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7637
7638 if (netif_running(netdev))
7639 ixgbe_reinit_locked(adapter);
7640 else
7641 ixgbe_reset(adapter);
7642 }
7643
7644 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7645 netdev_features_t features)
7646 {
7647 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7648
7649 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7650 if (!(features & NETIF_F_RXCSUM))
7651 features &= ~NETIF_F_LRO;
7652
7653 /* Turn off LRO if not RSC capable */
7654 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7655 features &= ~NETIF_F_LRO;
7656
7657 return features;
7658 }
7659
7660 static int ixgbe_set_features(struct net_device *netdev,
7661 netdev_features_t features)
7662 {
7663 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7664 netdev_features_t changed = netdev->features ^ features;
7665 bool need_reset = false;
7666
7667 /* Make sure RSC matches LRO, reset if change */
7668 if (!(features & NETIF_F_LRO)) {
7669 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7670 need_reset = true;
7671 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7672 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7673 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7674 if (adapter->rx_itr_setting == 1 ||
7675 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7676 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7677 need_reset = true;
7678 } else if ((changed ^ features) & NETIF_F_LRO) {
7679 e_info(probe, "rx-usecs set too low, "
7680 "disabling RSC\n");
7681 }
7682 }
7683
7684 /*
7685 * Check if Flow Director n-tuple support was enabled or disabled. If
7686 * the state changed, we need to reset.
7687 */
7688 switch (features & NETIF_F_NTUPLE) {
7689 case NETIF_F_NTUPLE:
7690 /* turn off ATR, enable perfect filters and reset */
7691 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7692 need_reset = true;
7693
7694 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7695 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7696 break;
7697 default:
7698 /* turn off perfect filters, enable ATR and reset */
7699 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7700 need_reset = true;
7701
7702 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7703
7704 /* We cannot enable ATR if SR-IOV is enabled */
7705 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7706 break;
7707
7708 /* We cannot enable ATR if we have 2 or more traffic classes */
7709 if (netdev_get_num_tc(netdev) > 1)
7710 break;
7711
7712 /* We cannot enable ATR if RSS is disabled */
7713 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7714 break;
7715
7716 /* A sample rate of 0 indicates ATR disabled */
7717 if (!adapter->atr_sample_rate)
7718 break;
7719
7720 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7721 break;
7722 }
7723
7724 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7725 ixgbe_vlan_strip_enable(adapter);
7726 else
7727 ixgbe_vlan_strip_disable(adapter);
7728
7729 if (changed & NETIF_F_RXALL)
7730 need_reset = true;
7731
7732 netdev->features = features;
7733 if (need_reset)
7734 ixgbe_do_reset(netdev);
7735
7736 return 0;
7737 }
7738
7739 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7740 struct net_device *dev,
7741 const unsigned char *addr,
7742 u16 flags)
7743 {
7744 struct ixgbe_adapter *adapter = netdev_priv(dev);
7745 int err;
7746
7747 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7748 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
7749
7750 /* Hardware does not support aging addresses so if a
7751 * ndm_state is given only allow permanent addresses
7752 */
7753 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7754 pr_info("%s: FDB only supports static addresses\n",
7755 ixgbe_driver_name);
7756 return -EINVAL;
7757 }
7758
7759 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
7760 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7761
7762 if (netdev_uc_count(dev) < rar_uc_entries)
7763 err = dev_uc_add_excl(dev, addr);
7764 else
7765 err = -ENOMEM;
7766 } else if (is_multicast_ether_addr(addr)) {
7767 err = dev_mc_add_excl(dev, addr);
7768 } else {
7769 err = -EINVAL;
7770 }
7771
7772 /* Only return duplicate errors if NLM_F_EXCL is set */
7773 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7774 err = 0;
7775
7776 return err;
7777 }
7778
7779 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7780 struct nlmsghdr *nlh)
7781 {
7782 struct ixgbe_adapter *adapter = netdev_priv(dev);
7783 struct nlattr *attr, *br_spec;
7784 int rem;
7785
7786 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7787 return -EOPNOTSUPP;
7788
7789 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7790
7791 nla_for_each_nested(attr, br_spec, rem) {
7792 __u16 mode;
7793 u32 reg = 0;
7794
7795 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7796 continue;
7797
7798 mode = nla_get_u16(attr);
7799 if (mode == BRIDGE_MODE_VEPA) {
7800 reg = 0;
7801 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7802 } else if (mode == BRIDGE_MODE_VEB) {
7803 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7804 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7805 } else
7806 return -EINVAL;
7807
7808 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7809
7810 e_info(drv, "enabling bridge mode: %s\n",
7811 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7812 }
7813
7814 return 0;
7815 }
7816
7817 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7818 struct net_device *dev,
7819 u32 filter_mask)
7820 {
7821 struct ixgbe_adapter *adapter = netdev_priv(dev);
7822 u16 mode;
7823
7824 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7825 return 0;
7826
7827 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
7828 mode = BRIDGE_MODE_VEB;
7829 else
7830 mode = BRIDGE_MODE_VEPA;
7831
7832 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7833 }
7834
7835 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
7836 {
7837 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
7838 struct ixgbe_adapter *adapter = netdev_priv(pdev);
7839 unsigned int limit;
7840 int pool, err;
7841
7842 #ifdef CONFIG_RPS
7843 if (vdev->num_rx_queues != vdev->num_tx_queues) {
7844 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
7845 vdev->name);
7846 return ERR_PTR(-EINVAL);
7847 }
7848 #endif
7849 /* Check for hardware restriction on number of rx/tx queues */
7850 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
7851 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
7852 netdev_info(pdev,
7853 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
7854 pdev->name);
7855 return ERR_PTR(-EINVAL);
7856 }
7857
7858 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7859 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
7860 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
7861 return ERR_PTR(-EBUSY);
7862
7863 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL);
7864 if (!fwd_adapter)
7865 return ERR_PTR(-ENOMEM);
7866
7867 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
7868 adapter->num_rx_pools++;
7869 set_bit(pool, &adapter->fwd_bitmask);
7870 limit = find_last_bit(&adapter->fwd_bitmask, 32);
7871
7872 /* Enable VMDq flag so device will be set in VM mode */
7873 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
7874 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
7875 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
7876
7877 /* Force reinit of ring allocation with VMDQ enabled */
7878 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7879 if (err)
7880 goto fwd_add_err;
7881 fwd_adapter->pool = pool;
7882 fwd_adapter->real_adapter = adapter;
7883 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
7884 if (err)
7885 goto fwd_add_err;
7886 netif_tx_start_all_queues(vdev);
7887 return fwd_adapter;
7888 fwd_add_err:
7889 /* unwind counter and free adapter struct */
7890 netdev_info(pdev,
7891 "%s: dfwd hardware acceleration failed\n", vdev->name);
7892 clear_bit(pool, &adapter->fwd_bitmask);
7893 adapter->num_rx_pools--;
7894 kfree(fwd_adapter);
7895 return ERR_PTR(err);
7896 }
7897
7898 static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
7899 {
7900 struct ixgbe_fwd_adapter *fwd_adapter = priv;
7901 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
7902 unsigned int limit;
7903
7904 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
7905 adapter->num_rx_pools--;
7906
7907 limit = find_last_bit(&adapter->fwd_bitmask, 32);
7908 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
7909 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
7910 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7911 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
7912 fwd_adapter->pool, adapter->num_rx_pools,
7913 fwd_adapter->rx_base_queue,
7914 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
7915 adapter->fwd_bitmask);
7916 kfree(fwd_adapter);
7917 }
7918
7919 static const struct net_device_ops ixgbe_netdev_ops = {
7920 .ndo_open = ixgbe_open,
7921 .ndo_stop = ixgbe_close,
7922 .ndo_start_xmit = ixgbe_xmit_frame,
7923 .ndo_select_queue = ixgbe_select_queue,
7924 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7925 .ndo_validate_addr = eth_validate_addr,
7926 .ndo_set_mac_address = ixgbe_set_mac,
7927 .ndo_change_mtu = ixgbe_change_mtu,
7928 .ndo_tx_timeout = ixgbe_tx_timeout,
7929 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7930 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7931 .ndo_do_ioctl = ixgbe_ioctl,
7932 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7933 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7934 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
7935 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7936 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7937 .ndo_get_stats64 = ixgbe_get_stats64,
7938 #ifdef CONFIG_IXGBE_DCB
7939 .ndo_setup_tc = ixgbe_setup_tc,
7940 #endif
7941 #ifdef CONFIG_NET_POLL_CONTROLLER
7942 .ndo_poll_controller = ixgbe_netpoll,
7943 #endif
7944 #ifdef CONFIG_NET_RX_BUSY_POLL
7945 .ndo_busy_poll = ixgbe_low_latency_recv,
7946 #endif
7947 #ifdef IXGBE_FCOE
7948 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7949 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7950 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7951 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7952 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7953 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7954 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7955 #endif /* IXGBE_FCOE */
7956 .ndo_set_features = ixgbe_set_features,
7957 .ndo_fix_features = ixgbe_fix_features,
7958 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7959 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7960 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
7961 .ndo_dfwd_add_station = ixgbe_fwd_add,
7962 .ndo_dfwd_del_station = ixgbe_fwd_del,
7963 };
7964
7965 /**
7966 * ixgbe_enumerate_functions - Get the number of ports this device has
7967 * @adapter: adapter structure
7968 *
7969 * This function enumerates the phsyical functions co-located on a single slot,
7970 * in order to determine how many ports a device has. This is most useful in
7971 * determining the required GT/s of PCIe bandwidth necessary for optimal
7972 * performance.
7973 **/
7974 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7975 {
7976 struct pci_dev *entry, *pdev = adapter->pdev;
7977 int physfns = 0;
7978
7979 /* Some cards can not use the generic count PCIe functions method,
7980 * because they are behind a parent switch, so we hardcode these with
7981 * the correct number of functions.
7982 */
7983 if (ixgbe_pcie_from_parent(&adapter->hw))
7984 physfns = 4;
7985
7986 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
7987 /* don't count virtual functions */
7988 if (entry->is_virtfn)
7989 continue;
7990
7991 /* When the devices on the bus don't all match our device ID,
7992 * we can't reliably determine the correct number of
7993 * functions. This can occur if a function has been direct
7994 * attached to a virtual machine using VT-d, for example. In
7995 * this case, simply return -1 to indicate this.
7996 */
7997 if ((entry->vendor != pdev->vendor) ||
7998 (entry->device != pdev->device))
7999 return -1;
8000
8001 physfns++;
8002 }
8003
8004 return physfns;
8005 }
8006
8007 /**
8008 * ixgbe_wol_supported - Check whether device supports WoL
8009 * @hw: hw specific details
8010 * @device_id: the device ID
8011 * @subdev_id: the subsystem device ID
8012 *
8013 * This function is used by probe and ethtool to determine
8014 * which devices have WoL support
8015 *
8016 **/
8017 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8018 u16 subdevice_id)
8019 {
8020 struct ixgbe_hw *hw = &adapter->hw;
8021 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8022 int is_wol_supported = 0;
8023
8024 switch (device_id) {
8025 case IXGBE_DEV_ID_82599_SFP:
8026 /* Only these subdevices could supports WOL */
8027 switch (subdevice_id) {
8028 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8029 case IXGBE_SUBDEV_ID_82599_560FLR:
8030 /* only support first port */
8031 if (hw->bus.func != 0)
8032 break;
8033 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8034 case IXGBE_SUBDEV_ID_82599_SFP:
8035 case IXGBE_SUBDEV_ID_82599_RNDC:
8036 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
8037 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8038 is_wol_supported = 1;
8039 break;
8040 }
8041 break;
8042 case IXGBE_DEV_ID_82599EN_SFP:
8043 /* Only this subdevice supports WOL */
8044 switch (subdevice_id) {
8045 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8046 is_wol_supported = 1;
8047 break;
8048 }
8049 break;
8050 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8051 /* All except this subdevice support WOL */
8052 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8053 is_wol_supported = 1;
8054 break;
8055 case IXGBE_DEV_ID_82599_KX4:
8056 is_wol_supported = 1;
8057 break;
8058 case IXGBE_DEV_ID_X540T:
8059 case IXGBE_DEV_ID_X540T1:
8060 /* check eeprom to see if enabled wol */
8061 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8062 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8063 (hw->bus.func == 0))) {
8064 is_wol_supported = 1;
8065 }
8066 break;
8067 }
8068
8069 return is_wol_supported;
8070 }
8071
8072 /**
8073 * ixgbe_probe - Device Initialization Routine
8074 * @pdev: PCI device information struct
8075 * @ent: entry in ixgbe_pci_tbl
8076 *
8077 * Returns 0 on success, negative on failure
8078 *
8079 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
8080 * The OS initialization, configuring of the adapter private structure,
8081 * and a hardware reset occur.
8082 **/
8083 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8084 {
8085 struct net_device *netdev;
8086 struct ixgbe_adapter *adapter = NULL;
8087 struct ixgbe_hw *hw;
8088 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
8089 static int cards_found;
8090 int i, err, pci_using_dac, expected_gts;
8091 unsigned int indices = MAX_TX_QUEUES;
8092 u8 part_str[IXGBE_PBANUM_LENGTH];
8093 #ifdef IXGBE_FCOE
8094 u16 device_caps;
8095 #endif
8096 u32 eec;
8097
8098 /* Catch broken hardware that put the wrong VF device ID in
8099 * the PCIe SR-IOV capability.
8100 */
8101 if (pdev->is_virtfn) {
8102 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
8103 pci_name(pdev), pdev->vendor, pdev->device);
8104 return -EINVAL;
8105 }
8106
8107 err = pci_enable_device_mem(pdev);
8108 if (err)
8109 return err;
8110
8111 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
8112 pci_using_dac = 1;
8113 } else {
8114 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8115 if (err) {
8116 dev_err(&pdev->dev,
8117 "No usable DMA configuration, aborting\n");
8118 goto err_dma;
8119 }
8120 pci_using_dac = 0;
8121 }
8122
8123 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8124 IORESOURCE_MEM), ixgbe_driver_name);
8125 if (err) {
8126 dev_err(&pdev->dev,
8127 "pci_request_selected_regions failed 0x%x\n", err);
8128 goto err_pci_reg;
8129 }
8130
8131 pci_enable_pcie_error_reporting(pdev);
8132
8133 pci_set_master(pdev);
8134 pci_save_state(pdev);
8135
8136 if (ii->mac == ixgbe_mac_82598EB) {
8137 #ifdef CONFIG_IXGBE_DCB
8138 /* 8 TC w/ 4 queues per TC */
8139 indices = 4 * MAX_TRAFFIC_CLASS;
8140 #else
8141 indices = IXGBE_MAX_RSS_INDICES;
8142 #endif
8143 }
8144
8145 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
8146 if (!netdev) {
8147 err = -ENOMEM;
8148 goto err_alloc_etherdev;
8149 }
8150
8151 SET_NETDEV_DEV(netdev, &pdev->dev);
8152
8153 adapter = netdev_priv(netdev);
8154 pci_set_drvdata(pdev, adapter);
8155
8156 adapter->netdev = netdev;
8157 adapter->pdev = pdev;
8158 hw = &adapter->hw;
8159 hw->back = adapter;
8160 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
8161
8162 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8163 pci_resource_len(pdev, 0));
8164 adapter->io_addr = hw->hw_addr;
8165 if (!hw->hw_addr) {
8166 err = -EIO;
8167 goto err_ioremap;
8168 }
8169
8170 netdev->netdev_ops = &ixgbe_netdev_ops;
8171 ixgbe_set_ethtool_ops(netdev);
8172 netdev->watchdog_timeo = 5 * HZ;
8173 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
8174
8175 adapter->bd_number = cards_found;
8176
8177 /* Setup hw api */
8178 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
8179 hw->mac.type = ii->mac;
8180
8181 /* EEPROM */
8182 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
8183 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
8184 if (ixgbe_removed(hw->hw_addr)) {
8185 err = -EIO;
8186 goto err_ioremap;
8187 }
8188 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8189 if (!(eec & (1 << 8)))
8190 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8191
8192 /* PHY */
8193 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
8194 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
8195 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8196 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8197 hw->phy.mdio.mmds = 0;
8198 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8199 hw->phy.mdio.dev = netdev;
8200 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8201 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
8202
8203 ii->get_invariants(hw);
8204
8205 /* setup the private structure */
8206 err = ixgbe_sw_init(adapter);
8207 if (err)
8208 goto err_sw_init;
8209
8210 /* Make it possible the adapter to be woken up via WOL */
8211 switch (adapter->hw.mac.type) {
8212 case ixgbe_mac_82599EB:
8213 case ixgbe_mac_X540:
8214 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
8215 break;
8216 default:
8217 break;
8218 }
8219
8220 /*
8221 * If there is a fan on this device and it has failed log the
8222 * failure.
8223 */
8224 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8225 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8226 if (esdp & IXGBE_ESDP_SDP1)
8227 e_crit(probe, "Fan has stopped, replace the adapter\n");
8228 }
8229
8230 if (allow_unsupported_sfp)
8231 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8232
8233 /* reset_hw fills in the perm_addr as well */
8234 hw->phy.reset_if_overtemp = true;
8235 err = hw->mac.ops.reset_hw(hw);
8236 hw->phy.reset_if_overtemp = false;
8237 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
8238 hw->mac.type == ixgbe_mac_82598EB) {
8239 err = 0;
8240 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
8241 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8242 e_dev_err("Reload the driver after installing a supported module.\n");
8243 goto err_sw_init;
8244 } else if (err) {
8245 e_dev_err("HW Init failed: %d\n", err);
8246 goto err_sw_init;
8247 }
8248
8249 #ifdef CONFIG_PCI_IOV
8250 /* SR-IOV not supported on the 82598 */
8251 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8252 goto skip_sriov;
8253 /* Mailbox */
8254 ixgbe_init_mbx_params_pf(hw);
8255 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
8256 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
8257 ixgbe_enable_sriov(adapter);
8258 skip_sriov:
8259
8260 #endif
8261 netdev->features = NETIF_F_SG |
8262 NETIF_F_IP_CSUM |
8263 NETIF_F_IPV6_CSUM |
8264 NETIF_F_HW_VLAN_CTAG_TX |
8265 NETIF_F_HW_VLAN_CTAG_RX |
8266 NETIF_F_HW_VLAN_CTAG_FILTER |
8267 NETIF_F_TSO |
8268 NETIF_F_TSO6 |
8269 NETIF_F_RXHASH |
8270 NETIF_F_RXCSUM;
8271
8272 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
8273
8274 switch (adapter->hw.mac.type) {
8275 case ixgbe_mac_82599EB:
8276 case ixgbe_mac_X540:
8277 netdev->features |= NETIF_F_SCTP_CSUM;
8278 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8279 NETIF_F_NTUPLE;
8280 break;
8281 default:
8282 break;
8283 }
8284
8285 netdev->hw_features |= NETIF_F_RXALL;
8286
8287 netdev->vlan_features |= NETIF_F_TSO;
8288 netdev->vlan_features |= NETIF_F_TSO6;
8289 netdev->vlan_features |= NETIF_F_IP_CSUM;
8290 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
8291 netdev->vlan_features |= NETIF_F_SG;
8292
8293 netdev->priv_flags |= IFF_UNICAST_FLT;
8294 netdev->priv_flags |= IFF_SUPP_NOFCS;
8295
8296 #ifdef CONFIG_IXGBE_DCB
8297 netdev->dcbnl_ops = &dcbnl_ops;
8298 #endif
8299
8300 #ifdef IXGBE_FCOE
8301 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
8302 unsigned int fcoe_l;
8303
8304 if (hw->mac.ops.get_device_caps) {
8305 hw->mac.ops.get_device_caps(hw, &device_caps);
8306 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8307 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
8308 }
8309
8310
8311 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8312 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
8313
8314 netdev->features |= NETIF_F_FSO |
8315 NETIF_F_FCOE_CRC;
8316
8317 netdev->vlan_features |= NETIF_F_FSO |
8318 NETIF_F_FCOE_CRC |
8319 NETIF_F_FCOE_MTU;
8320 }
8321 #endif /* IXGBE_FCOE */
8322 if (pci_using_dac) {
8323 netdev->features |= NETIF_F_HIGHDMA;
8324 netdev->vlan_features |= NETIF_F_HIGHDMA;
8325 }
8326
8327 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8328 netdev->hw_features |= NETIF_F_LRO;
8329 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
8330 netdev->features |= NETIF_F_LRO;
8331
8332 /* make sure the EEPROM is good */
8333 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
8334 e_dev_err("The EEPROM Checksum Is Not Valid\n");
8335 err = -EIO;
8336 goto err_sw_init;
8337 }
8338
8339 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
8340
8341 if (!is_valid_ether_addr(netdev->dev_addr)) {
8342 e_dev_err("invalid MAC address\n");
8343 err = -EIO;
8344 goto err_sw_init;
8345 }
8346
8347 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr);
8348
8349 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
8350 (unsigned long) adapter);
8351
8352 if (ixgbe_removed(hw->hw_addr)) {
8353 err = -EIO;
8354 goto err_sw_init;
8355 }
8356 INIT_WORK(&adapter->service_task, ixgbe_service_task);
8357 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
8358 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
8359
8360 err = ixgbe_init_interrupt_scheme(adapter);
8361 if (err)
8362 goto err_sw_init;
8363
8364 /* WOL not supported for all devices */
8365 adapter->wol = 0;
8366 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
8367 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
8368 pdev->subsystem_device);
8369 if (hw->wol_enabled)
8370 adapter->wol = IXGBE_WUFC_MAG;
8371
8372 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8373
8374 /* save off EEPROM version number */
8375 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8376 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8377
8378 /* pick up the PCI bus settings for reporting later */
8379 hw->mac.ops.get_bus_info(hw);
8380 if (ixgbe_pcie_from_parent(hw))
8381 ixgbe_get_parent_bus_info(adapter);
8382
8383 /* calculate the expected PCIe bandwidth required for optimal
8384 * performance. Note that some older parts will never have enough
8385 * bandwidth due to being older generation PCIe parts. We clamp these
8386 * parts to ensure no warning is displayed if it can't be fixed.
8387 */
8388 switch (hw->mac.type) {
8389 case ixgbe_mac_82598EB:
8390 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8391 break;
8392 default:
8393 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8394 break;
8395 }
8396
8397 /* don't check link if we failed to enumerate functions */
8398 if (expected_gts > 0)
8399 ixgbe_check_minimum_link(adapter, expected_gts);
8400
8401 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
8402 if (err)
8403 strlcpy(part_str, "Unknown", sizeof(part_str));
8404 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8405 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8406 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
8407 part_str);
8408 else
8409 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8410 hw->mac.type, hw->phy.type, part_str);
8411
8412 e_dev_info("%pM\n", netdev->dev_addr);
8413
8414 /* reset the hardware with the new settings */
8415 err = hw->mac.ops.start_hw(hw);
8416 if (err == IXGBE_ERR_EEPROM_VERSION) {
8417 /* We are running on a pre-production device, log a warning */
8418 e_dev_warn("This device is a pre-production adapter/LOM. "
8419 "Please be aware there may be issues associated "
8420 "with your hardware. If you are experiencing "
8421 "problems please contact your Intel or hardware "
8422 "representative who provided you with this "
8423 "hardware.\n");
8424 }
8425 strcpy(netdev->name, "eth%d");
8426 err = register_netdev(netdev);
8427 if (err)
8428 goto err_register;
8429
8430 /* power down the optics for 82599 SFP+ fiber */
8431 if (hw->mac.ops.disable_tx_laser)
8432 hw->mac.ops.disable_tx_laser(hw);
8433
8434 /* carrier off reporting is important to ethtool even BEFORE open */
8435 netif_carrier_off(netdev);
8436
8437 #ifdef CONFIG_IXGBE_DCA
8438 if (dca_add_requester(&pdev->dev) == 0) {
8439 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
8440 ixgbe_setup_dca(adapter);
8441 }
8442 #endif
8443 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
8444 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
8445 for (i = 0; i < adapter->num_vfs; i++)
8446 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8447 }
8448
8449 /* firmware requires driver version to be 0xFFFFFFFF
8450 * since os does not support feature
8451 */
8452 if (hw->mac.ops.set_fw_drv_ver)
8453 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8454 0xFF);
8455
8456 /* add san mac addr to netdev */
8457 ixgbe_add_sanmac_netdev(netdev);
8458
8459 e_dev_info("%s\n", ixgbe_default_device_descr);
8460 cards_found++;
8461
8462 #ifdef CONFIG_IXGBE_HWMON
8463 if (ixgbe_sysfs_init(adapter))
8464 e_err(probe, "failed to allocate sysfs resources\n");
8465 #endif /* CONFIG_IXGBE_HWMON */
8466
8467 ixgbe_dbg_adapter_init(adapter);
8468
8469 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
8470 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
8471 hw->mac.ops.setup_link(hw,
8472 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8473 true);
8474
8475 return 0;
8476
8477 err_register:
8478 ixgbe_release_hw_control(adapter);
8479 ixgbe_clear_interrupt_scheme(adapter);
8480 err_sw_init:
8481 ixgbe_disable_sriov(adapter);
8482 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
8483 iounmap(adapter->io_addr);
8484 kfree(adapter->mac_table);
8485 err_ioremap:
8486 free_netdev(netdev);
8487 err_alloc_etherdev:
8488 pci_release_selected_regions(pdev,
8489 pci_select_bars(pdev, IORESOURCE_MEM));
8490 err_pci_reg:
8491 err_dma:
8492 if (!adapter || !test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8493 pci_disable_device(pdev);
8494 return err;
8495 }
8496
8497 /**
8498 * ixgbe_remove - Device Removal Routine
8499 * @pdev: PCI device information struct
8500 *
8501 * ixgbe_remove is called by the PCI subsystem to alert the driver
8502 * that it should release a PCI device. The could be caused by a
8503 * Hot-Plug event, or because the driver is going to be removed from
8504 * memory.
8505 **/
8506 static void ixgbe_remove(struct pci_dev *pdev)
8507 {
8508 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8509 struct net_device *netdev = adapter->netdev;
8510
8511 ixgbe_dbg_adapter_exit(adapter);
8512
8513 set_bit(__IXGBE_REMOVING, &adapter->state);
8514 cancel_work_sync(&adapter->service_task);
8515
8516
8517 #ifdef CONFIG_IXGBE_DCA
8518 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8519 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8520 dca_remove_requester(&pdev->dev);
8521 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8522 }
8523
8524 #endif
8525 #ifdef CONFIG_IXGBE_HWMON
8526 ixgbe_sysfs_exit(adapter);
8527 #endif /* CONFIG_IXGBE_HWMON */
8528
8529 /* remove the added san mac */
8530 ixgbe_del_sanmac_netdev(netdev);
8531
8532 if (netdev->reg_state == NETREG_REGISTERED)
8533 unregister_netdev(netdev);
8534
8535 #ifdef CONFIG_PCI_IOV
8536 /*
8537 * Only disable SR-IOV on unload if the user specified the now
8538 * deprecated max_vfs module parameter.
8539 */
8540 if (max_vfs)
8541 ixgbe_disable_sriov(adapter);
8542 #endif
8543 ixgbe_clear_interrupt_scheme(adapter);
8544
8545 ixgbe_release_hw_control(adapter);
8546
8547 #ifdef CONFIG_DCB
8548 kfree(adapter->ixgbe_ieee_pfc);
8549 kfree(adapter->ixgbe_ieee_ets);
8550
8551 #endif
8552 iounmap(adapter->io_addr);
8553 pci_release_selected_regions(pdev, pci_select_bars(pdev,
8554 IORESOURCE_MEM));
8555
8556 e_dev_info("complete\n");
8557
8558 kfree(adapter->mac_table);
8559 free_netdev(netdev);
8560
8561 pci_disable_pcie_error_reporting(pdev);
8562
8563 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8564 pci_disable_device(pdev);
8565 }
8566
8567 /**
8568 * ixgbe_io_error_detected - called when PCI error is detected
8569 * @pdev: Pointer to PCI device
8570 * @state: The current pci connection state
8571 *
8572 * This function is called after a PCI bus error affecting
8573 * this device has been detected.
8574 */
8575 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
8576 pci_channel_state_t state)
8577 {
8578 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8579 struct net_device *netdev = adapter->netdev;
8580
8581 #ifdef CONFIG_PCI_IOV
8582 struct ixgbe_hw *hw = &adapter->hw;
8583 struct pci_dev *bdev, *vfdev;
8584 u32 dw0, dw1, dw2, dw3;
8585 int vf, pos;
8586 u16 req_id, pf_func;
8587
8588 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8589 adapter->num_vfs == 0)
8590 goto skip_bad_vf_detection;
8591
8592 bdev = pdev->bus->self;
8593 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
8594 bdev = bdev->bus->self;
8595
8596 if (!bdev)
8597 goto skip_bad_vf_detection;
8598
8599 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8600 if (!pos)
8601 goto skip_bad_vf_detection;
8602
8603 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
8604 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
8605 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
8606 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
8607 if (ixgbe_removed(hw->hw_addr))
8608 goto skip_bad_vf_detection;
8609
8610 req_id = dw1 >> 16;
8611 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8612 if (!(req_id & 0x0080))
8613 goto skip_bad_vf_detection;
8614
8615 pf_func = req_id & 0x01;
8616 if ((pf_func & 1) == (pdev->devfn & 1)) {
8617 unsigned int device_id;
8618
8619 vf = (req_id & 0x7F) >> 1;
8620 e_dev_err("VF %d has caused a PCIe error\n", vf);
8621 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8622 "%8.8x\tdw3: %8.8x\n",
8623 dw0, dw1, dw2, dw3);
8624 switch (adapter->hw.mac.type) {
8625 case ixgbe_mac_82599EB:
8626 device_id = IXGBE_82599_VF_DEVICE_ID;
8627 break;
8628 case ixgbe_mac_X540:
8629 device_id = IXGBE_X540_VF_DEVICE_ID;
8630 break;
8631 default:
8632 device_id = 0;
8633 break;
8634 }
8635
8636 /* Find the pci device of the offending VF */
8637 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
8638 while (vfdev) {
8639 if (vfdev->devfn == (req_id & 0xFF))
8640 break;
8641 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
8642 device_id, vfdev);
8643 }
8644 /*
8645 * There's a slim chance the VF could have been hot plugged,
8646 * so if it is no longer present we don't need to issue the
8647 * VFLR. Just clean up the AER in that case.
8648 */
8649 if (vfdev) {
8650 e_dev_err("Issuing VFLR to VF %d\n", vf);
8651 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
8652 /* Free device reference count */
8653 pci_dev_put(vfdev);
8654 }
8655
8656 pci_cleanup_aer_uncorrect_error_status(pdev);
8657 }
8658
8659 /*
8660 * Even though the error may have occurred on the other port
8661 * we still need to increment the vf error reference count for
8662 * both ports because the I/O resume function will be called
8663 * for both of them.
8664 */
8665 adapter->vferr_refcount++;
8666
8667 return PCI_ERS_RESULT_RECOVERED;
8668
8669 skip_bad_vf_detection:
8670 #endif /* CONFIG_PCI_IOV */
8671 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
8672 return PCI_ERS_RESULT_DISCONNECT;
8673
8674 rtnl_lock();
8675 netif_device_detach(netdev);
8676
8677 if (state == pci_channel_io_perm_failure) {
8678 rtnl_unlock();
8679 return PCI_ERS_RESULT_DISCONNECT;
8680 }
8681
8682 if (netif_running(netdev))
8683 ixgbe_down(adapter);
8684
8685 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8686 pci_disable_device(pdev);
8687 rtnl_unlock();
8688
8689 /* Request a slot reset. */
8690 return PCI_ERS_RESULT_NEED_RESET;
8691 }
8692
8693 /**
8694 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8695 * @pdev: Pointer to PCI device
8696 *
8697 * Restart the card from scratch, as if from a cold-boot.
8698 */
8699 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8700 {
8701 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8702 pci_ers_result_t result;
8703 int err;
8704
8705 if (pci_enable_device_mem(pdev)) {
8706 e_err(probe, "Cannot re-enable PCI device after reset.\n");
8707 result = PCI_ERS_RESULT_DISCONNECT;
8708 } else {
8709 smp_mb__before_atomic();
8710 clear_bit(__IXGBE_DISABLED, &adapter->state);
8711 adapter->hw.hw_addr = adapter->io_addr;
8712 pci_set_master(pdev);
8713 pci_restore_state(pdev);
8714 pci_save_state(pdev);
8715
8716 pci_wake_from_d3(pdev, false);
8717
8718 ixgbe_reset(adapter);
8719 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
8720 result = PCI_ERS_RESULT_RECOVERED;
8721 }
8722
8723 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8724 if (err) {
8725 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8726 "failed 0x%0x\n", err);
8727 /* non-fatal, continue */
8728 }
8729
8730 return result;
8731 }
8732
8733 /**
8734 * ixgbe_io_resume - called when traffic can start flowing again.
8735 * @pdev: Pointer to PCI device
8736 *
8737 * This callback is called when the error recovery driver tells us that
8738 * its OK to resume normal operation.
8739 */
8740 static void ixgbe_io_resume(struct pci_dev *pdev)
8741 {
8742 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8743 struct net_device *netdev = adapter->netdev;
8744
8745 #ifdef CONFIG_PCI_IOV
8746 if (adapter->vferr_refcount) {
8747 e_info(drv, "Resuming after VF err\n");
8748 adapter->vferr_refcount--;
8749 return;
8750 }
8751
8752 #endif
8753 if (netif_running(netdev))
8754 ixgbe_up(adapter);
8755
8756 netif_device_attach(netdev);
8757 }
8758
8759 static const struct pci_error_handlers ixgbe_err_handler = {
8760 .error_detected = ixgbe_io_error_detected,
8761 .slot_reset = ixgbe_io_slot_reset,
8762 .resume = ixgbe_io_resume,
8763 };
8764
8765 static struct pci_driver ixgbe_driver = {
8766 .name = ixgbe_driver_name,
8767 .id_table = ixgbe_pci_tbl,
8768 .probe = ixgbe_probe,
8769 .remove = ixgbe_remove,
8770 #ifdef CONFIG_PM
8771 .suspend = ixgbe_suspend,
8772 .resume = ixgbe_resume,
8773 #endif
8774 .shutdown = ixgbe_shutdown,
8775 .sriov_configure = ixgbe_pci_sriov_configure,
8776 .err_handler = &ixgbe_err_handler
8777 };
8778
8779 /**
8780 * ixgbe_init_module - Driver Registration Routine
8781 *
8782 * ixgbe_init_module is the first routine called when the driver is
8783 * loaded. All it does is register with the PCI subsystem.
8784 **/
8785 static int __init ixgbe_init_module(void)
8786 {
8787 int ret;
8788 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
8789 pr_info("%s\n", ixgbe_copyright);
8790
8791 ixgbe_dbg_init();
8792
8793 ret = pci_register_driver(&ixgbe_driver);
8794 if (ret) {
8795 ixgbe_dbg_exit();
8796 return ret;
8797 }
8798
8799 #ifdef CONFIG_IXGBE_DCA
8800 dca_register_notify(&dca_notifier);
8801 #endif
8802
8803 return 0;
8804 }
8805
8806 module_init(ixgbe_init_module);
8807
8808 /**
8809 * ixgbe_exit_module - Driver Exit Cleanup Routine
8810 *
8811 * ixgbe_exit_module is called just before the driver is removed
8812 * from memory.
8813 **/
8814 static void __exit ixgbe_exit_module(void)
8815 {
8816 #ifdef CONFIG_IXGBE_DCA
8817 dca_unregister_notify(&dca_notifier);
8818 #endif
8819 pci_unregister_driver(&ixgbe_driver);
8820
8821 ixgbe_dbg_exit();
8822
8823 rcu_barrier(); /* Wait for completion of call_rcu()'s */
8824 }
8825
8826 #ifdef CONFIG_IXGBE_DCA
8827 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
8828 void *p)
8829 {
8830 int ret_val;
8831
8832 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
8833 __ixgbe_notify_dca);
8834
8835 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8836 }
8837
8838 #endif /* CONFIG_IXGBE_DCA */
8839
8840 module_exit(ixgbe_exit_module);
8841
8842 /* ixgbe_main.c */
Linux kernel - Deliverables
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