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[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2014 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/types.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/vmalloc.h>
34 #include <linux/string.h>
35 #include <linux/in.h>
36 #include <linux/interrupt.h>
37 #include <linux/ip.h>
38 #include <linux/tcp.h>
39 #include <linux/sctp.h>
40 #include <linux/pkt_sched.h>
41 #include <linux/ipv6.h>
42 #include <linux/slab.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/ethtool.h>
46 #include <linux/if.h>
47 #include <linux/if_vlan.h>
48 #include <linux/if_macvlan.h>
49 #include <linux/if_bridge.h>
50 #include <linux/prefetch.h>
51 #include <scsi/fc/fc_fcoe.h>
52
53 #include "ixgbe.h"
54 #include "ixgbe_common.h"
55 #include "ixgbe_dcb_82599.h"
56 #include "ixgbe_sriov.h"
57
58 char ixgbe_driver_name[] = "ixgbe";
59 static const char ixgbe_driver_string[] =
60 "Intel(R) 10 Gigabit PCI Express Network Driver";
61 #ifdef IXGBE_FCOE
62 char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
64 #else
65 static char ixgbe_default_device_descr[] =
66 "Intel(R) 10 Gigabit Network Connection";
67 #endif
68 #define DRV_VERSION "3.19.1-k"
69 const char ixgbe_driver_version[] = DRV_VERSION;
70 static const char ixgbe_copyright[] =
71 "Copyright (c) 1999-2014 Intel Corporation.";
72
73 static const struct ixgbe_info *ixgbe_info_tbl[] = {
74 [board_82598] = &ixgbe_82598_info,
75 [board_82599] = &ixgbe_82599_info,
76 [board_X540] = &ixgbe_X540_info,
77 };
78
79 /* ixgbe_pci_tbl - PCI Device ID Table
80 *
81 * Wildcard entries (PCI_ANY_ID) should come last
82 * Last entry must be all 0s
83 *
84 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
85 * Class, Class Mask, private data (not used) }
86 */
87 static const struct pci_device_id ixgbe_pci_tbl[] = {
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
118 /* required last entry */
119 {0, }
120 };
121 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
122
123 #ifdef CONFIG_IXGBE_DCA
124 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
125 void *p);
126 static struct notifier_block dca_notifier = {
127 .notifier_call = ixgbe_notify_dca,
128 .next = NULL,
129 .priority = 0
130 };
131 #endif
132
133 #ifdef CONFIG_PCI_IOV
134 static unsigned int max_vfs;
135 module_param(max_vfs, uint, 0);
136 MODULE_PARM_DESC(max_vfs,
137 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
138 #endif /* CONFIG_PCI_IOV */
139
140 static unsigned int allow_unsupported_sfp;
141 module_param(allow_unsupported_sfp, uint, 0);
142 MODULE_PARM_DESC(allow_unsupported_sfp,
143 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
144
145 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
146 static int debug = -1;
147 module_param(debug, int, 0);
148 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
149
150 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
151 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
152 MODULE_LICENSE("GPL");
153 MODULE_VERSION(DRV_VERSION);
154
155 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
156
157 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
158 u32 reg, u16 *value)
159 {
160 struct pci_dev *parent_dev;
161 struct pci_bus *parent_bus;
162
163 parent_bus = adapter->pdev->bus->parent;
164 if (!parent_bus)
165 return -1;
166
167 parent_dev = parent_bus->self;
168 if (!parent_dev)
169 return -1;
170
171 if (!pci_is_pcie(parent_dev))
172 return -1;
173
174 pcie_capability_read_word(parent_dev, reg, value);
175 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
176 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
177 return -1;
178 return 0;
179 }
180
181 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
182 {
183 struct ixgbe_hw *hw = &adapter->hw;
184 u16 link_status = 0;
185 int err;
186
187 hw->bus.type = ixgbe_bus_type_pci_express;
188
189 /* Get the negotiated link width and speed from PCI config space of the
190 * parent, as this device is behind a switch
191 */
192 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
193
194 /* assume caller will handle error case */
195 if (err)
196 return err;
197
198 hw->bus.width = ixgbe_convert_bus_width(link_status);
199 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
200
201 return 0;
202 }
203
204 /**
205 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
206 * @hw: hw specific details
207 *
208 * This function is used by probe to determine whether a device's PCI-Express
209 * bandwidth details should be gathered from the parent bus instead of from the
210 * device. Used to ensure that various locations all have the correct device ID
211 * checks.
212 */
213 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
214 {
215 switch (hw->device_id) {
216 case IXGBE_DEV_ID_82599_SFP_SF_QP:
217 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
218 return true;
219 default:
220 return false;
221 }
222 }
223
224 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
225 int expected_gts)
226 {
227 int max_gts = 0;
228 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
229 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
230 struct pci_dev *pdev;
231
232 /* determine whether to use the the parent device
233 */
234 if (ixgbe_pcie_from_parent(&adapter->hw))
235 pdev = adapter->pdev->bus->parent->self;
236 else
237 pdev = adapter->pdev;
238
239 if (pcie_get_minimum_link(pdev, &speed, &width) ||
240 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
241 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
242 return;
243 }
244
245 switch (speed) {
246 case PCIE_SPEED_2_5GT:
247 /* 8b/10b encoding reduces max throughput by 20% */
248 max_gts = 2 * width;
249 break;
250 case PCIE_SPEED_5_0GT:
251 /* 8b/10b encoding reduces max throughput by 20% */
252 max_gts = 4 * width;
253 break;
254 case PCIE_SPEED_8_0GT:
255 /* 128b/130b encoding reduces throughput by less than 2% */
256 max_gts = 8 * width;
257 break;
258 default:
259 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
260 return;
261 }
262
263 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
264 max_gts);
265 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
266 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
267 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
268 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
269 "Unknown"),
270 width,
271 (speed == PCIE_SPEED_2_5GT ? "20%" :
272 speed == PCIE_SPEED_5_0GT ? "20%" :
273 speed == PCIE_SPEED_8_0GT ? "<2%" :
274 "Unknown"));
275
276 if (max_gts < expected_gts) {
277 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
278 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
279 expected_gts);
280 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
281 }
282 }
283
284 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
285 {
286 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
287 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
288 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
289 schedule_work(&adapter->service_task);
290 }
291
292 static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
293 {
294 struct ixgbe_adapter *adapter = hw->back;
295
296 if (!hw->hw_addr)
297 return;
298 hw->hw_addr = NULL;
299 e_dev_err("Adapter removed\n");
300 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
301 ixgbe_service_event_schedule(adapter);
302 }
303
304 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
305 {
306 u32 value;
307
308 /* The following check not only optimizes a bit by not
309 * performing a read on the status register when the
310 * register just read was a status register read that
311 * returned IXGBE_FAILED_READ_REG. It also blocks any
312 * potential recursion.
313 */
314 if (reg == IXGBE_STATUS) {
315 ixgbe_remove_adapter(hw);
316 return;
317 }
318 value = ixgbe_read_reg(hw, IXGBE_STATUS);
319 if (value == IXGBE_FAILED_READ_REG)
320 ixgbe_remove_adapter(hw);
321 }
322
323 /**
324 * ixgbe_read_reg - Read from device register
325 * @hw: hw specific details
326 * @reg: offset of register to read
327 *
328 * Returns : value read or IXGBE_FAILED_READ_REG if removed
329 *
330 * This function is used to read device registers. It checks for device
331 * removal by confirming any read that returns all ones by checking the
332 * status register value for all ones. This function avoids reading from
333 * the hardware if a removal was previously detected in which case it
334 * returns IXGBE_FAILED_READ_REG (all ones).
335 */
336 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
337 {
338 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
339 u32 value;
340
341 if (ixgbe_removed(reg_addr))
342 return IXGBE_FAILED_READ_REG;
343 value = readl(reg_addr + reg);
344 if (unlikely(value == IXGBE_FAILED_READ_REG))
345 ixgbe_check_remove(hw, reg);
346 return value;
347 }
348
349 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
350 {
351 u16 value;
352
353 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
354 if (value == IXGBE_FAILED_READ_CFG_WORD) {
355 ixgbe_remove_adapter(hw);
356 return true;
357 }
358 return false;
359 }
360
361 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
362 {
363 struct ixgbe_adapter *adapter = hw->back;
364 u16 value;
365
366 if (ixgbe_removed(hw->hw_addr))
367 return IXGBE_FAILED_READ_CFG_WORD;
368 pci_read_config_word(adapter->pdev, reg, &value);
369 if (value == IXGBE_FAILED_READ_CFG_WORD &&
370 ixgbe_check_cfg_remove(hw, adapter->pdev))
371 return IXGBE_FAILED_READ_CFG_WORD;
372 return value;
373 }
374
375 #ifdef CONFIG_PCI_IOV
376 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
377 {
378 struct ixgbe_adapter *adapter = hw->back;
379 u32 value;
380
381 if (ixgbe_removed(hw->hw_addr))
382 return IXGBE_FAILED_READ_CFG_DWORD;
383 pci_read_config_dword(adapter->pdev, reg, &value);
384 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
385 ixgbe_check_cfg_remove(hw, adapter->pdev))
386 return IXGBE_FAILED_READ_CFG_DWORD;
387 return value;
388 }
389 #endif /* CONFIG_PCI_IOV */
390
391 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
392 {
393 struct ixgbe_adapter *adapter = hw->back;
394
395 if (ixgbe_removed(hw->hw_addr))
396 return;
397 pci_write_config_word(adapter->pdev, reg, value);
398 }
399
400 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
401 {
402 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
403
404 /* flush memory to make sure state is correct before next watchdog */
405 smp_mb__before_atomic();
406 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
407 }
408
409 struct ixgbe_reg_info {
410 u32 ofs;
411 char *name;
412 };
413
414 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
415
416 /* General Registers */
417 {IXGBE_CTRL, "CTRL"},
418 {IXGBE_STATUS, "STATUS"},
419 {IXGBE_CTRL_EXT, "CTRL_EXT"},
420
421 /* Interrupt Registers */
422 {IXGBE_EICR, "EICR"},
423
424 /* RX Registers */
425 {IXGBE_SRRCTL(0), "SRRCTL"},
426 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
427 {IXGBE_RDLEN(0), "RDLEN"},
428 {IXGBE_RDH(0), "RDH"},
429 {IXGBE_RDT(0), "RDT"},
430 {IXGBE_RXDCTL(0), "RXDCTL"},
431 {IXGBE_RDBAL(0), "RDBAL"},
432 {IXGBE_RDBAH(0), "RDBAH"},
433
434 /* TX Registers */
435 {IXGBE_TDBAL(0), "TDBAL"},
436 {IXGBE_TDBAH(0), "TDBAH"},
437 {IXGBE_TDLEN(0), "TDLEN"},
438 {IXGBE_TDH(0), "TDH"},
439 {IXGBE_TDT(0), "TDT"},
440 {IXGBE_TXDCTL(0), "TXDCTL"},
441
442 /* List Terminator */
443 { .name = NULL }
444 };
445
446
447 /*
448 * ixgbe_regdump - register printout routine
449 */
450 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
451 {
452 int i = 0, j = 0;
453 char rname[16];
454 u32 regs[64];
455
456 switch (reginfo->ofs) {
457 case IXGBE_SRRCTL(0):
458 for (i = 0; i < 64; i++)
459 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
460 break;
461 case IXGBE_DCA_RXCTRL(0):
462 for (i = 0; i < 64; i++)
463 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
464 break;
465 case IXGBE_RDLEN(0):
466 for (i = 0; i < 64; i++)
467 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
468 break;
469 case IXGBE_RDH(0):
470 for (i = 0; i < 64; i++)
471 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
472 break;
473 case IXGBE_RDT(0):
474 for (i = 0; i < 64; i++)
475 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
476 break;
477 case IXGBE_RXDCTL(0):
478 for (i = 0; i < 64; i++)
479 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
480 break;
481 case IXGBE_RDBAL(0):
482 for (i = 0; i < 64; i++)
483 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
484 break;
485 case IXGBE_RDBAH(0):
486 for (i = 0; i < 64; i++)
487 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
488 break;
489 case IXGBE_TDBAL(0):
490 for (i = 0; i < 64; i++)
491 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
492 break;
493 case IXGBE_TDBAH(0):
494 for (i = 0; i < 64; i++)
495 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
496 break;
497 case IXGBE_TDLEN(0):
498 for (i = 0; i < 64; i++)
499 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
500 break;
501 case IXGBE_TDH(0):
502 for (i = 0; i < 64; i++)
503 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
504 break;
505 case IXGBE_TDT(0):
506 for (i = 0; i < 64; i++)
507 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
508 break;
509 case IXGBE_TXDCTL(0):
510 for (i = 0; i < 64; i++)
511 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
512 break;
513 default:
514 pr_info("%-15s %08x\n", reginfo->name,
515 IXGBE_READ_REG(hw, reginfo->ofs));
516 return;
517 }
518
519 for (i = 0; i < 8; i++) {
520 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
521 pr_err("%-15s", rname);
522 for (j = 0; j < 8; j++)
523 pr_cont(" %08x", regs[i*8+j]);
524 pr_cont("\n");
525 }
526
527 }
528
529 /*
530 * ixgbe_dump - Print registers, tx-rings and rx-rings
531 */
532 static void ixgbe_dump(struct ixgbe_adapter *adapter)
533 {
534 struct net_device *netdev = adapter->netdev;
535 struct ixgbe_hw *hw = &adapter->hw;
536 struct ixgbe_reg_info *reginfo;
537 int n = 0;
538 struct ixgbe_ring *tx_ring;
539 struct ixgbe_tx_buffer *tx_buffer;
540 union ixgbe_adv_tx_desc *tx_desc;
541 struct my_u0 { u64 a; u64 b; } *u0;
542 struct ixgbe_ring *rx_ring;
543 union ixgbe_adv_rx_desc *rx_desc;
544 struct ixgbe_rx_buffer *rx_buffer_info;
545 u32 staterr;
546 int i = 0;
547
548 if (!netif_msg_hw(adapter))
549 return;
550
551 /* Print netdevice Info */
552 if (netdev) {
553 dev_info(&adapter->pdev->dev, "Net device Info\n");
554 pr_info("Device Name state "
555 "trans_start last_rx\n");
556 pr_info("%-15s %016lX %016lX %016lX\n",
557 netdev->name,
558 netdev->state,
559 netdev->trans_start,
560 netdev->last_rx);
561 }
562
563 /* Print Registers */
564 dev_info(&adapter->pdev->dev, "Register Dump\n");
565 pr_info(" Register Name Value\n");
566 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
567 reginfo->name; reginfo++) {
568 ixgbe_regdump(hw, reginfo);
569 }
570
571 /* Print TX Ring Summary */
572 if (!netdev || !netif_running(netdev))
573 return;
574
575 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
576 pr_info(" %s %s %s %s\n",
577 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
578 "leng", "ntw", "timestamp");
579 for (n = 0; n < adapter->num_tx_queues; n++) {
580 tx_ring = adapter->tx_ring[n];
581 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
582 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
583 n, tx_ring->next_to_use, tx_ring->next_to_clean,
584 (u64)dma_unmap_addr(tx_buffer, dma),
585 dma_unmap_len(tx_buffer, len),
586 tx_buffer->next_to_watch,
587 (u64)tx_buffer->time_stamp);
588 }
589
590 /* Print TX Rings */
591 if (!netif_msg_tx_done(adapter))
592 goto rx_ring_summary;
593
594 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
595
596 /* Transmit Descriptor Formats
597 *
598 * 82598 Advanced Transmit Descriptor
599 * +--------------------------------------------------------------+
600 * 0 | Buffer Address [63:0] |
601 * +--------------------------------------------------------------+
602 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
603 * +--------------------------------------------------------------+
604 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
605 *
606 * 82598 Advanced Transmit Descriptor (Write-Back Format)
607 * +--------------------------------------------------------------+
608 * 0 | RSV [63:0] |
609 * +--------------------------------------------------------------+
610 * 8 | RSV | STA | NXTSEQ |
611 * +--------------------------------------------------------------+
612 * 63 36 35 32 31 0
613 *
614 * 82599+ Advanced Transmit Descriptor
615 * +--------------------------------------------------------------+
616 * 0 | Buffer Address [63:0] |
617 * +--------------------------------------------------------------+
618 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
619 * +--------------------------------------------------------------+
620 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
621 *
622 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
623 * +--------------------------------------------------------------+
624 * 0 | RSV [63:0] |
625 * +--------------------------------------------------------------+
626 * 8 | RSV | STA | RSV |
627 * +--------------------------------------------------------------+
628 * 63 36 35 32 31 0
629 */
630
631 for (n = 0; n < adapter->num_tx_queues; n++) {
632 tx_ring = adapter->tx_ring[n];
633 pr_info("------------------------------------\n");
634 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
635 pr_info("------------------------------------\n");
636 pr_info("%s%s %s %s %s %s\n",
637 "T [desc] [address 63:0 ] ",
638 "[PlPOIdStDDt Ln] [bi->dma ] ",
639 "leng", "ntw", "timestamp", "bi->skb");
640
641 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
642 tx_desc = IXGBE_TX_DESC(tx_ring, i);
643 tx_buffer = &tx_ring->tx_buffer_info[i];
644 u0 = (struct my_u0 *)tx_desc;
645 if (dma_unmap_len(tx_buffer, len) > 0) {
646 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
647 i,
648 le64_to_cpu(u0->a),
649 le64_to_cpu(u0->b),
650 (u64)dma_unmap_addr(tx_buffer, dma),
651 dma_unmap_len(tx_buffer, len),
652 tx_buffer->next_to_watch,
653 (u64)tx_buffer->time_stamp,
654 tx_buffer->skb);
655 if (i == tx_ring->next_to_use &&
656 i == tx_ring->next_to_clean)
657 pr_cont(" NTC/U\n");
658 else if (i == tx_ring->next_to_use)
659 pr_cont(" NTU\n");
660 else if (i == tx_ring->next_to_clean)
661 pr_cont(" NTC\n");
662 else
663 pr_cont("\n");
664
665 if (netif_msg_pktdata(adapter) &&
666 tx_buffer->skb)
667 print_hex_dump(KERN_INFO, "",
668 DUMP_PREFIX_ADDRESS, 16, 1,
669 tx_buffer->skb->data,
670 dma_unmap_len(tx_buffer, len),
671 true);
672 }
673 }
674 }
675
676 /* Print RX Rings Summary */
677 rx_ring_summary:
678 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
679 pr_info("Queue [NTU] [NTC]\n");
680 for (n = 0; n < adapter->num_rx_queues; n++) {
681 rx_ring = adapter->rx_ring[n];
682 pr_info("%5d %5X %5X\n",
683 n, rx_ring->next_to_use, rx_ring->next_to_clean);
684 }
685
686 /* Print RX Rings */
687 if (!netif_msg_rx_status(adapter))
688 return;
689
690 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
691
692 /* Receive Descriptor Formats
693 *
694 * 82598 Advanced Receive Descriptor (Read) Format
695 * 63 1 0
696 * +-----------------------------------------------------+
697 * 0 | Packet Buffer Address [63:1] |A0/NSE|
698 * +----------------------------------------------+------+
699 * 8 | Header Buffer Address [63:1] | DD |
700 * +-----------------------------------------------------+
701 *
702 *
703 * 82598 Advanced Receive Descriptor (Write-Back) Format
704 *
705 * 63 48 47 32 31 30 21 20 16 15 4 3 0
706 * +------------------------------------------------------+
707 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
708 * | Packet | IP | | | | Type | Type |
709 * | Checksum | Ident | | | | | |
710 * +------------------------------------------------------+
711 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
712 * +------------------------------------------------------+
713 * 63 48 47 32 31 20 19 0
714 *
715 * 82599+ Advanced Receive Descriptor (Read) Format
716 * 63 1 0
717 * +-----------------------------------------------------+
718 * 0 | Packet Buffer Address [63:1] |A0/NSE|
719 * +----------------------------------------------+------+
720 * 8 | Header Buffer Address [63:1] | DD |
721 * +-----------------------------------------------------+
722 *
723 *
724 * 82599+ Advanced Receive Descriptor (Write-Back) Format
725 *
726 * 63 48 47 32 31 30 21 20 17 16 4 3 0
727 * +------------------------------------------------------+
728 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
729 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
730 * |/ Flow Dir Flt ID | | | | | |
731 * +------------------------------------------------------+
732 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
733 * +------------------------------------------------------+
734 * 63 48 47 32 31 20 19 0
735 */
736
737 for (n = 0; n < adapter->num_rx_queues; n++) {
738 rx_ring = adapter->rx_ring[n];
739 pr_info("------------------------------------\n");
740 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
741 pr_info("------------------------------------\n");
742 pr_info("%s%s%s",
743 "R [desc] [ PktBuf A0] ",
744 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
745 "<-- Adv Rx Read format\n");
746 pr_info("%s%s%s",
747 "RWB[desc] [PcsmIpSHl PtRs] ",
748 "[vl er S cks ln] ---------------- [bi->skb ] ",
749 "<-- Adv Rx Write-Back format\n");
750
751 for (i = 0; i < rx_ring->count; i++) {
752 rx_buffer_info = &rx_ring->rx_buffer_info[i];
753 rx_desc = IXGBE_RX_DESC(rx_ring, i);
754 u0 = (struct my_u0 *)rx_desc;
755 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
756 if (staterr & IXGBE_RXD_STAT_DD) {
757 /* Descriptor Done */
758 pr_info("RWB[0x%03X] %016llX "
759 "%016llX ---------------- %p", i,
760 le64_to_cpu(u0->a),
761 le64_to_cpu(u0->b),
762 rx_buffer_info->skb);
763 } else {
764 pr_info("R [0x%03X] %016llX "
765 "%016llX %016llX %p", i,
766 le64_to_cpu(u0->a),
767 le64_to_cpu(u0->b),
768 (u64)rx_buffer_info->dma,
769 rx_buffer_info->skb);
770
771 if (netif_msg_pktdata(adapter) &&
772 rx_buffer_info->dma) {
773 print_hex_dump(KERN_INFO, "",
774 DUMP_PREFIX_ADDRESS, 16, 1,
775 page_address(rx_buffer_info->page) +
776 rx_buffer_info->page_offset,
777 ixgbe_rx_bufsz(rx_ring), true);
778 }
779 }
780
781 if (i == rx_ring->next_to_use)
782 pr_cont(" NTU\n");
783 else if (i == rx_ring->next_to_clean)
784 pr_cont(" NTC\n");
785 else
786 pr_cont("\n");
787
788 }
789 }
790 }
791
792 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
793 {
794 u32 ctrl_ext;
795
796 /* Let firmware take over control of h/w */
797 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
798 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
799 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
800 }
801
802 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
803 {
804 u32 ctrl_ext;
805
806 /* Let firmware know the driver has taken over */
807 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
808 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
809 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
810 }
811
812 /**
813 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
814 * @adapter: pointer to adapter struct
815 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
816 * @queue: queue to map the corresponding interrupt to
817 * @msix_vector: the vector to map to the corresponding queue
818 *
819 */
820 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
821 u8 queue, u8 msix_vector)
822 {
823 u32 ivar, index;
824 struct ixgbe_hw *hw = &adapter->hw;
825 switch (hw->mac.type) {
826 case ixgbe_mac_82598EB:
827 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
828 if (direction == -1)
829 direction = 0;
830 index = (((direction * 64) + queue) >> 2) & 0x1F;
831 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
832 ivar &= ~(0xFF << (8 * (queue & 0x3)));
833 ivar |= (msix_vector << (8 * (queue & 0x3)));
834 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
835 break;
836 case ixgbe_mac_82599EB:
837 case ixgbe_mac_X540:
838 if (direction == -1) {
839 /* other causes */
840 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
841 index = ((queue & 1) * 8);
842 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
843 ivar &= ~(0xFF << index);
844 ivar |= (msix_vector << index);
845 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
846 break;
847 } else {
848 /* tx or rx causes */
849 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
850 index = ((16 * (queue & 1)) + (8 * direction));
851 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
852 ivar &= ~(0xFF << index);
853 ivar |= (msix_vector << index);
854 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
855 break;
856 }
857 default:
858 break;
859 }
860 }
861
862 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
863 u64 qmask)
864 {
865 u32 mask;
866
867 switch (adapter->hw.mac.type) {
868 case ixgbe_mac_82598EB:
869 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
870 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
871 break;
872 case ixgbe_mac_82599EB:
873 case ixgbe_mac_X540:
874 mask = (qmask & 0xFFFFFFFF);
875 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
876 mask = (qmask >> 32);
877 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
878 break;
879 default:
880 break;
881 }
882 }
883
884 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
885 struct ixgbe_tx_buffer *tx_buffer)
886 {
887 if (tx_buffer->skb) {
888 dev_kfree_skb_any(tx_buffer->skb);
889 if (dma_unmap_len(tx_buffer, len))
890 dma_unmap_single(ring->dev,
891 dma_unmap_addr(tx_buffer, dma),
892 dma_unmap_len(tx_buffer, len),
893 DMA_TO_DEVICE);
894 } else if (dma_unmap_len(tx_buffer, len)) {
895 dma_unmap_page(ring->dev,
896 dma_unmap_addr(tx_buffer, dma),
897 dma_unmap_len(tx_buffer, len),
898 DMA_TO_DEVICE);
899 }
900 tx_buffer->next_to_watch = NULL;
901 tx_buffer->skb = NULL;
902 dma_unmap_len_set(tx_buffer, len, 0);
903 /* tx_buffer must be completely set up in the transmit path */
904 }
905
906 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
907 {
908 struct ixgbe_hw *hw = &adapter->hw;
909 struct ixgbe_hw_stats *hwstats = &adapter->stats;
910 int i;
911 u32 data;
912
913 if ((hw->fc.current_mode != ixgbe_fc_full) &&
914 (hw->fc.current_mode != ixgbe_fc_rx_pause))
915 return;
916
917 switch (hw->mac.type) {
918 case ixgbe_mac_82598EB:
919 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
920 break;
921 default:
922 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
923 }
924 hwstats->lxoffrxc += data;
925
926 /* refill credits (no tx hang) if we received xoff */
927 if (!data)
928 return;
929
930 for (i = 0; i < adapter->num_tx_queues; i++)
931 clear_bit(__IXGBE_HANG_CHECK_ARMED,
932 &adapter->tx_ring[i]->state);
933 }
934
935 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
936 {
937 struct ixgbe_hw *hw = &adapter->hw;
938 struct ixgbe_hw_stats *hwstats = &adapter->stats;
939 u32 xoff[8] = {0};
940 u8 tc;
941 int i;
942 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
943
944 if (adapter->ixgbe_ieee_pfc)
945 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
946
947 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
948 ixgbe_update_xoff_rx_lfc(adapter);
949 return;
950 }
951
952 /* update stats for each tc, only valid with PFC enabled */
953 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
954 u32 pxoffrxc;
955
956 switch (hw->mac.type) {
957 case ixgbe_mac_82598EB:
958 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
959 break;
960 default:
961 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
962 }
963 hwstats->pxoffrxc[i] += pxoffrxc;
964 /* Get the TC for given UP */
965 tc = netdev_get_prio_tc_map(adapter->netdev, i);
966 xoff[tc] += pxoffrxc;
967 }
968
969 /* disarm tx queues that have received xoff frames */
970 for (i = 0; i < adapter->num_tx_queues; i++) {
971 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
972
973 tc = tx_ring->dcb_tc;
974 if (xoff[tc])
975 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
976 }
977 }
978
979 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
980 {
981 return ring->stats.packets;
982 }
983
984 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
985 {
986 struct ixgbe_adapter *adapter;
987 struct ixgbe_hw *hw;
988 u32 head, tail;
989
990 if (ring->l2_accel_priv)
991 adapter = ring->l2_accel_priv->real_adapter;
992 else
993 adapter = netdev_priv(ring->netdev);
994
995 hw = &adapter->hw;
996 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
997 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
998
999 if (head != tail)
1000 return (head < tail) ?
1001 tail - head : (tail + ring->count - head);
1002
1003 return 0;
1004 }
1005
1006 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1007 {
1008 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1009 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1010 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1011
1012 clear_check_for_tx_hang(tx_ring);
1013
1014 /*
1015 * Check for a hung queue, but be thorough. This verifies
1016 * that a transmit has been completed since the previous
1017 * check AND there is at least one packet pending. The
1018 * ARMED bit is set to indicate a potential hang. The
1019 * bit is cleared if a pause frame is received to remove
1020 * false hang detection due to PFC or 802.3x frames. By
1021 * requiring this to fail twice we avoid races with
1022 * pfc clearing the ARMED bit and conditions where we
1023 * run the check_tx_hang logic with a transmit completion
1024 * pending but without time to complete it yet.
1025 */
1026 if (tx_done_old == tx_done && tx_pending)
1027 /* make sure it is true for two checks in a row */
1028 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1029 &tx_ring->state);
1030 /* update completed stats and continue */
1031 tx_ring->tx_stats.tx_done_old = tx_done;
1032 /* reset the countdown */
1033 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1034
1035 return false;
1036 }
1037
1038 /**
1039 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1040 * @adapter: driver private struct
1041 **/
1042 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1043 {
1044
1045 /* Do the reset outside of interrupt context */
1046 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1047 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
1048 e_warn(drv, "initiating reset due to tx timeout\n");
1049 ixgbe_service_event_schedule(adapter);
1050 }
1051 }
1052
1053 /**
1054 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
1055 * @q_vector: structure containing interrupt and ring information
1056 * @tx_ring: tx ring to clean
1057 **/
1058 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
1059 struct ixgbe_ring *tx_ring)
1060 {
1061 struct ixgbe_adapter *adapter = q_vector->adapter;
1062 struct ixgbe_tx_buffer *tx_buffer;
1063 union ixgbe_adv_tx_desc *tx_desc;
1064 unsigned int total_bytes = 0, total_packets = 0;
1065 unsigned int budget = q_vector->tx.work_limit;
1066 unsigned int i = tx_ring->next_to_clean;
1067
1068 if (test_bit(__IXGBE_DOWN, &adapter->state))
1069 return true;
1070
1071 tx_buffer = &tx_ring->tx_buffer_info[i];
1072 tx_desc = IXGBE_TX_DESC(tx_ring, i);
1073 i -= tx_ring->count;
1074
1075 do {
1076 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1077
1078 /* if next_to_watch is not set then there is no work pending */
1079 if (!eop_desc)
1080 break;
1081
1082 /* prevent any other reads prior to eop_desc */
1083 read_barrier_depends();
1084
1085 /* if DD is not set pending work has not been completed */
1086 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1087 break;
1088
1089 /* clear next_to_watch to prevent false hangs */
1090 tx_buffer->next_to_watch = NULL;
1091
1092 /* update the statistics for this packet */
1093 total_bytes += tx_buffer->bytecount;
1094 total_packets += tx_buffer->gso_segs;
1095
1096 /* free the skb */
1097 dev_kfree_skb_any(tx_buffer->skb);
1098
1099 /* unmap skb header data */
1100 dma_unmap_single(tx_ring->dev,
1101 dma_unmap_addr(tx_buffer, dma),
1102 dma_unmap_len(tx_buffer, len),
1103 DMA_TO_DEVICE);
1104
1105 /* clear tx_buffer data */
1106 tx_buffer->skb = NULL;
1107 dma_unmap_len_set(tx_buffer, len, 0);
1108
1109 /* unmap remaining buffers */
1110 while (tx_desc != eop_desc) {
1111 tx_buffer++;
1112 tx_desc++;
1113 i++;
1114 if (unlikely(!i)) {
1115 i -= tx_ring->count;
1116 tx_buffer = tx_ring->tx_buffer_info;
1117 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1118 }
1119
1120 /* unmap any remaining paged data */
1121 if (dma_unmap_len(tx_buffer, len)) {
1122 dma_unmap_page(tx_ring->dev,
1123 dma_unmap_addr(tx_buffer, dma),
1124 dma_unmap_len(tx_buffer, len),
1125 DMA_TO_DEVICE);
1126 dma_unmap_len_set(tx_buffer, len, 0);
1127 }
1128 }
1129
1130 /* move us one more past the eop_desc for start of next pkt */
1131 tx_buffer++;
1132 tx_desc++;
1133 i++;
1134 if (unlikely(!i)) {
1135 i -= tx_ring->count;
1136 tx_buffer = tx_ring->tx_buffer_info;
1137 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1138 }
1139
1140 /* issue prefetch for next Tx descriptor */
1141 prefetch(tx_desc);
1142
1143 /* update budget accounting */
1144 budget--;
1145 } while (likely(budget));
1146
1147 i += tx_ring->count;
1148 tx_ring->next_to_clean = i;
1149 u64_stats_update_begin(&tx_ring->syncp);
1150 tx_ring->stats.bytes += total_bytes;
1151 tx_ring->stats.packets += total_packets;
1152 u64_stats_update_end(&tx_ring->syncp);
1153 q_vector->tx.total_bytes += total_bytes;
1154 q_vector->tx.total_packets += total_packets;
1155
1156 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1157 /* schedule immediate reset if we believe we hung */
1158 struct ixgbe_hw *hw = &adapter->hw;
1159 e_err(drv, "Detected Tx Unit Hang\n"
1160 " Tx Queue <%d>\n"
1161 " TDH, TDT <%x>, <%x>\n"
1162 " next_to_use <%x>\n"
1163 " next_to_clean <%x>\n"
1164 "tx_buffer_info[next_to_clean]\n"
1165 " time_stamp <%lx>\n"
1166 " jiffies <%lx>\n",
1167 tx_ring->queue_index,
1168 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1169 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1170 tx_ring->next_to_use, i,
1171 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1172
1173 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1174
1175 e_info(probe,
1176 "tx hang %d detected on queue %d, resetting adapter\n",
1177 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1178
1179 /* schedule immediate reset if we believe we hung */
1180 ixgbe_tx_timeout_reset(adapter);
1181
1182 /* the adapter is about to reset, no point in enabling stuff */
1183 return true;
1184 }
1185
1186 netdev_tx_completed_queue(txring_txq(tx_ring),
1187 total_packets, total_bytes);
1188
1189 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1190 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1191 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1192 /* Make sure that anybody stopping the queue after this
1193 * sees the new next_to_clean.
1194 */
1195 smp_mb();
1196 if (__netif_subqueue_stopped(tx_ring->netdev,
1197 tx_ring->queue_index)
1198 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1199 netif_wake_subqueue(tx_ring->netdev,
1200 tx_ring->queue_index);
1201 ++tx_ring->tx_stats.restart_queue;
1202 }
1203 }
1204
1205 return !!budget;
1206 }
1207
1208 #ifdef CONFIG_IXGBE_DCA
1209 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1210 struct ixgbe_ring *tx_ring,
1211 int cpu)
1212 {
1213 struct ixgbe_hw *hw = &adapter->hw;
1214 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1215 u16 reg_offset;
1216
1217 switch (hw->mac.type) {
1218 case ixgbe_mac_82598EB:
1219 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1220 break;
1221 case ixgbe_mac_82599EB:
1222 case ixgbe_mac_X540:
1223 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1224 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1225 break;
1226 default:
1227 /* for unknown hardware do not write register */
1228 return;
1229 }
1230
1231 /*
1232 * We can enable relaxed ordering for reads, but not writes when
1233 * DCA is enabled. This is due to a known issue in some chipsets
1234 * which will cause the DCA tag to be cleared.
1235 */
1236 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1237 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1238 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1239
1240 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1241 }
1242
1243 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1244 struct ixgbe_ring *rx_ring,
1245 int cpu)
1246 {
1247 struct ixgbe_hw *hw = &adapter->hw;
1248 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1249 u8 reg_idx = rx_ring->reg_idx;
1250
1251
1252 switch (hw->mac.type) {
1253 case ixgbe_mac_82599EB:
1254 case ixgbe_mac_X540:
1255 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1256 break;
1257 default:
1258 break;
1259 }
1260
1261 /*
1262 * We can enable relaxed ordering for reads, but not writes when
1263 * DCA is enabled. This is due to a known issue in some chipsets
1264 * which will cause the DCA tag to be cleared.
1265 */
1266 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1267 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1268
1269 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1270 }
1271
1272 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1273 {
1274 struct ixgbe_adapter *adapter = q_vector->adapter;
1275 struct ixgbe_ring *ring;
1276 int cpu = get_cpu();
1277
1278 if (q_vector->cpu == cpu)
1279 goto out_no_update;
1280
1281 ixgbe_for_each_ring(ring, q_vector->tx)
1282 ixgbe_update_tx_dca(adapter, ring, cpu);
1283
1284 ixgbe_for_each_ring(ring, q_vector->rx)
1285 ixgbe_update_rx_dca(adapter, ring, cpu);
1286
1287 q_vector->cpu = cpu;
1288 out_no_update:
1289 put_cpu();
1290 }
1291
1292 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1293 {
1294 int i;
1295
1296 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1297 return;
1298
1299 /* always use CB2 mode, difference is masked in the CB driver */
1300 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1301
1302 for (i = 0; i < adapter->num_q_vectors; i++) {
1303 adapter->q_vector[i]->cpu = -1;
1304 ixgbe_update_dca(adapter->q_vector[i]);
1305 }
1306 }
1307
1308 static int __ixgbe_notify_dca(struct device *dev, void *data)
1309 {
1310 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1311 unsigned long event = *(unsigned long *)data;
1312
1313 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1314 return 0;
1315
1316 switch (event) {
1317 case DCA_PROVIDER_ADD:
1318 /* if we're already enabled, don't do it again */
1319 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1320 break;
1321 if (dca_add_requester(dev) == 0) {
1322 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1323 ixgbe_setup_dca(adapter);
1324 break;
1325 }
1326 /* Fall Through since DCA is disabled. */
1327 case DCA_PROVIDER_REMOVE:
1328 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1329 dca_remove_requester(dev);
1330 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1331 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1332 }
1333 break;
1334 }
1335
1336 return 0;
1337 }
1338
1339 #endif /* CONFIG_IXGBE_DCA */
1340 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1341 union ixgbe_adv_rx_desc *rx_desc,
1342 struct sk_buff *skb)
1343 {
1344 if (ring->netdev->features & NETIF_F_RXHASH)
1345 skb_set_hash(skb,
1346 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1347 PKT_HASH_TYPE_L3);
1348 }
1349
1350 #ifdef IXGBE_FCOE
1351 /**
1352 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1353 * @ring: structure containing ring specific data
1354 * @rx_desc: advanced rx descriptor
1355 *
1356 * Returns : true if it is FCoE pkt
1357 */
1358 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1359 union ixgbe_adv_rx_desc *rx_desc)
1360 {
1361 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1362
1363 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1364 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1365 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1366 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1367 }
1368
1369 #endif /* IXGBE_FCOE */
1370 /**
1371 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1372 * @ring: structure containing ring specific data
1373 * @rx_desc: current Rx descriptor being processed
1374 * @skb: skb currently being received and modified
1375 **/
1376 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1377 union ixgbe_adv_rx_desc *rx_desc,
1378 struct sk_buff *skb)
1379 {
1380 skb_checksum_none_assert(skb);
1381
1382 /* Rx csum disabled */
1383 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1384 return;
1385
1386 /* if IP and error */
1387 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1388 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1389 ring->rx_stats.csum_err++;
1390 return;
1391 }
1392
1393 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1394 return;
1395
1396 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1397 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1398
1399 /*
1400 * 82599 errata, UDP frames with a 0 checksum can be marked as
1401 * checksum errors.
1402 */
1403 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1404 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1405 return;
1406
1407 ring->rx_stats.csum_err++;
1408 return;
1409 }
1410
1411 /* It must be a TCP or UDP packet with a valid checksum */
1412 skb->ip_summed = CHECKSUM_UNNECESSARY;
1413 }
1414
1415 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1416 {
1417 rx_ring->next_to_use = val;
1418
1419 /* update next to alloc since we have filled the ring */
1420 rx_ring->next_to_alloc = val;
1421 /*
1422 * Force memory writes to complete before letting h/w
1423 * know there are new descriptors to fetch. (Only
1424 * applicable for weak-ordered memory model archs,
1425 * such as IA-64).
1426 */
1427 wmb();
1428 ixgbe_write_tail(rx_ring, val);
1429 }
1430
1431 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1432 struct ixgbe_rx_buffer *bi)
1433 {
1434 struct page *page = bi->page;
1435 dma_addr_t dma = bi->dma;
1436
1437 /* since we are recycling buffers we should seldom need to alloc */
1438 if (likely(dma))
1439 return true;
1440
1441 /* alloc new page for storage */
1442 if (likely(!page)) {
1443 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1444 bi->skb, ixgbe_rx_pg_order(rx_ring));
1445 if (unlikely(!page)) {
1446 rx_ring->rx_stats.alloc_rx_page_failed++;
1447 return false;
1448 }
1449 bi->page = page;
1450 }
1451
1452 /* map page for use */
1453 dma = dma_map_page(rx_ring->dev, page, 0,
1454 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1455
1456 /*
1457 * if mapping failed free memory back to system since
1458 * there isn't much point in holding memory we can't use
1459 */
1460 if (dma_mapping_error(rx_ring->dev, dma)) {
1461 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1462 bi->page = NULL;
1463
1464 rx_ring->rx_stats.alloc_rx_page_failed++;
1465 return false;
1466 }
1467
1468 bi->dma = dma;
1469 bi->page_offset = 0;
1470
1471 return true;
1472 }
1473
1474 /**
1475 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1476 * @rx_ring: ring to place buffers on
1477 * @cleaned_count: number of buffers to replace
1478 **/
1479 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1480 {
1481 union ixgbe_adv_rx_desc *rx_desc;
1482 struct ixgbe_rx_buffer *bi;
1483 u16 i = rx_ring->next_to_use;
1484
1485 /* nothing to do */
1486 if (!cleaned_count)
1487 return;
1488
1489 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1490 bi = &rx_ring->rx_buffer_info[i];
1491 i -= rx_ring->count;
1492
1493 do {
1494 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1495 break;
1496
1497 /*
1498 * Refresh the desc even if buffer_addrs didn't change
1499 * because each write-back erases this info.
1500 */
1501 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1502
1503 rx_desc++;
1504 bi++;
1505 i++;
1506 if (unlikely(!i)) {
1507 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1508 bi = rx_ring->rx_buffer_info;
1509 i -= rx_ring->count;
1510 }
1511
1512 /* clear the hdr_addr for the next_to_use descriptor */
1513 rx_desc->read.hdr_addr = 0;
1514
1515 cleaned_count--;
1516 } while (cleaned_count);
1517
1518 i += rx_ring->count;
1519
1520 if (rx_ring->next_to_use != i)
1521 ixgbe_release_rx_desc(rx_ring, i);
1522 }
1523
1524 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1525 struct sk_buff *skb)
1526 {
1527 u16 hdr_len = skb_headlen(skb);
1528
1529 /* set gso_size to avoid messing up TCP MSS */
1530 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1531 IXGBE_CB(skb)->append_cnt);
1532 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1533 }
1534
1535 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1536 struct sk_buff *skb)
1537 {
1538 /* if append_cnt is 0 then frame is not RSC */
1539 if (!IXGBE_CB(skb)->append_cnt)
1540 return;
1541
1542 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1543 rx_ring->rx_stats.rsc_flush++;
1544
1545 ixgbe_set_rsc_gso_size(rx_ring, skb);
1546
1547 /* gso_size is computed using append_cnt so always clear it last */
1548 IXGBE_CB(skb)->append_cnt = 0;
1549 }
1550
1551 /**
1552 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1553 * @rx_ring: rx descriptor ring packet is being transacted on
1554 * @rx_desc: pointer to the EOP Rx descriptor
1555 * @skb: pointer to current skb being populated
1556 *
1557 * This function checks the ring, descriptor, and packet information in
1558 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1559 * other fields within the skb.
1560 **/
1561 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1562 union ixgbe_adv_rx_desc *rx_desc,
1563 struct sk_buff *skb)
1564 {
1565 struct net_device *dev = rx_ring->netdev;
1566
1567 ixgbe_update_rsc_stats(rx_ring, skb);
1568
1569 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1570
1571 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1572
1573 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1574 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
1575
1576 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1577 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1578 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1579 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1580 }
1581
1582 skb_record_rx_queue(skb, rx_ring->queue_index);
1583
1584 skb->protocol = eth_type_trans(skb, dev);
1585 }
1586
1587 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1588 struct sk_buff *skb)
1589 {
1590 struct ixgbe_adapter *adapter = q_vector->adapter;
1591
1592 if (ixgbe_qv_busy_polling(q_vector))
1593 netif_receive_skb(skb);
1594 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1595 napi_gro_receive(&q_vector->napi, skb);
1596 else
1597 netif_rx(skb);
1598 }
1599
1600 /**
1601 * ixgbe_is_non_eop - process handling of non-EOP buffers
1602 * @rx_ring: Rx ring being processed
1603 * @rx_desc: Rx descriptor for current buffer
1604 * @skb: Current socket buffer containing buffer in progress
1605 *
1606 * This function updates next to clean. If the buffer is an EOP buffer
1607 * this function exits returning false, otherwise it will place the
1608 * sk_buff in the next buffer to be chained and return true indicating
1609 * that this is in fact a non-EOP buffer.
1610 **/
1611 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1612 union ixgbe_adv_rx_desc *rx_desc,
1613 struct sk_buff *skb)
1614 {
1615 u32 ntc = rx_ring->next_to_clean + 1;
1616
1617 /* fetch, update, and store next to clean */
1618 ntc = (ntc < rx_ring->count) ? ntc : 0;
1619 rx_ring->next_to_clean = ntc;
1620
1621 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1622
1623 /* update RSC append count if present */
1624 if (ring_is_rsc_enabled(rx_ring)) {
1625 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1626 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1627
1628 if (unlikely(rsc_enabled)) {
1629 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1630
1631 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1632 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1633
1634 /* update ntc based on RSC value */
1635 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1636 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1637 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1638 }
1639 }
1640
1641 /* if we are the last buffer then there is nothing else to do */
1642 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1643 return false;
1644
1645 /* place skb in next buffer to be received */
1646 rx_ring->rx_buffer_info[ntc].skb = skb;
1647 rx_ring->rx_stats.non_eop_descs++;
1648
1649 return true;
1650 }
1651
1652 /**
1653 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1654 * @rx_ring: rx descriptor ring packet is being transacted on
1655 * @skb: pointer to current skb being adjusted
1656 *
1657 * This function is an ixgbe specific version of __pskb_pull_tail. The
1658 * main difference between this version and the original function is that
1659 * this function can make several assumptions about the state of things
1660 * that allow for significant optimizations versus the standard function.
1661 * As a result we can do things like drop a frag and maintain an accurate
1662 * truesize for the skb.
1663 */
1664 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1665 struct sk_buff *skb)
1666 {
1667 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1668 unsigned char *va;
1669 unsigned int pull_len;
1670
1671 /*
1672 * it is valid to use page_address instead of kmap since we are
1673 * working with pages allocated out of the lomem pool per
1674 * alloc_page(GFP_ATOMIC)
1675 */
1676 va = skb_frag_address(frag);
1677
1678 /*
1679 * we need the header to contain the greater of either ETH_HLEN or
1680 * 60 bytes if the skb->len is less than 60 for skb_pad.
1681 */
1682 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
1683
1684 /* align pull length to size of long to optimize memcpy performance */
1685 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1686
1687 /* update all of the pointers */
1688 skb_frag_size_sub(frag, pull_len);
1689 frag->page_offset += pull_len;
1690 skb->data_len -= pull_len;
1691 skb->tail += pull_len;
1692 }
1693
1694 /**
1695 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1696 * @rx_ring: rx descriptor ring packet is being transacted on
1697 * @skb: pointer to current skb being updated
1698 *
1699 * This function provides a basic DMA sync up for the first fragment of an
1700 * skb. The reason for doing this is that the first fragment cannot be
1701 * unmapped until we have reached the end of packet descriptor for a buffer
1702 * chain.
1703 */
1704 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1705 struct sk_buff *skb)
1706 {
1707 /* if the page was released unmap it, else just sync our portion */
1708 if (unlikely(IXGBE_CB(skb)->page_released)) {
1709 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1710 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1711 IXGBE_CB(skb)->page_released = false;
1712 } else {
1713 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1714
1715 dma_sync_single_range_for_cpu(rx_ring->dev,
1716 IXGBE_CB(skb)->dma,
1717 frag->page_offset,
1718 ixgbe_rx_bufsz(rx_ring),
1719 DMA_FROM_DEVICE);
1720 }
1721 IXGBE_CB(skb)->dma = 0;
1722 }
1723
1724 /**
1725 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1726 * @rx_ring: rx descriptor ring packet is being transacted on
1727 * @rx_desc: pointer to the EOP Rx descriptor
1728 * @skb: pointer to current skb being fixed
1729 *
1730 * Check for corrupted packet headers caused by senders on the local L2
1731 * embedded NIC switch not setting up their Tx Descriptors right. These
1732 * should be very rare.
1733 *
1734 * Also address the case where we are pulling data in on pages only
1735 * and as such no data is present in the skb header.
1736 *
1737 * In addition if skb is not at least 60 bytes we need to pad it so that
1738 * it is large enough to qualify as a valid Ethernet frame.
1739 *
1740 * Returns true if an error was encountered and skb was freed.
1741 **/
1742 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1743 union ixgbe_adv_rx_desc *rx_desc,
1744 struct sk_buff *skb)
1745 {
1746 struct net_device *netdev = rx_ring->netdev;
1747
1748 /* verify that the packet does not have any known errors */
1749 if (unlikely(ixgbe_test_staterr(rx_desc,
1750 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1751 !(netdev->features & NETIF_F_RXALL))) {
1752 dev_kfree_skb_any(skb);
1753 return true;
1754 }
1755
1756 /* place header in linear portion of buffer */
1757 if (skb_is_nonlinear(skb))
1758 ixgbe_pull_tail(rx_ring, skb);
1759
1760 #ifdef IXGBE_FCOE
1761 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1762 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1763 return false;
1764
1765 #endif
1766 /* if skb_pad returns an error the skb was freed */
1767 if (unlikely(skb->len < 60)) {
1768 int pad_len = 60 - skb->len;
1769
1770 if (skb_pad(skb, pad_len))
1771 return true;
1772 __skb_put(skb, pad_len);
1773 }
1774
1775 return false;
1776 }
1777
1778 /**
1779 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1780 * @rx_ring: rx descriptor ring to store buffers on
1781 * @old_buff: donor buffer to have page reused
1782 *
1783 * Synchronizes page for reuse by the adapter
1784 **/
1785 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1786 struct ixgbe_rx_buffer *old_buff)
1787 {
1788 struct ixgbe_rx_buffer *new_buff;
1789 u16 nta = rx_ring->next_to_alloc;
1790
1791 new_buff = &rx_ring->rx_buffer_info[nta];
1792
1793 /* update, and store next to alloc */
1794 nta++;
1795 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1796
1797 /* transfer page from old buffer to new buffer */
1798 new_buff->page = old_buff->page;
1799 new_buff->dma = old_buff->dma;
1800 new_buff->page_offset = old_buff->page_offset;
1801
1802 /* sync the buffer for use by the device */
1803 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1804 new_buff->page_offset,
1805 ixgbe_rx_bufsz(rx_ring),
1806 DMA_FROM_DEVICE);
1807 }
1808
1809 /**
1810 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1811 * @rx_ring: rx descriptor ring to transact packets on
1812 * @rx_buffer: buffer containing page to add
1813 * @rx_desc: descriptor containing length of buffer written by hardware
1814 * @skb: sk_buff to place the data into
1815 *
1816 * This function will add the data contained in rx_buffer->page to the skb.
1817 * This is done either through a direct copy if the data in the buffer is
1818 * less than the skb header size, otherwise it will just attach the page as
1819 * a frag to the skb.
1820 *
1821 * The function will then update the page offset if necessary and return
1822 * true if the buffer can be reused by the adapter.
1823 **/
1824 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1825 struct ixgbe_rx_buffer *rx_buffer,
1826 union ixgbe_adv_rx_desc *rx_desc,
1827 struct sk_buff *skb)
1828 {
1829 struct page *page = rx_buffer->page;
1830 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1831 #if (PAGE_SIZE < 8192)
1832 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1833 #else
1834 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1835 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1836 ixgbe_rx_bufsz(rx_ring);
1837 #endif
1838
1839 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1840 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1841
1842 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1843
1844 /* we can reuse buffer as-is, just make sure it is local */
1845 if (likely(page_to_nid(page) == numa_node_id()))
1846 return true;
1847
1848 /* this page cannot be reused so discard it */
1849 put_page(page);
1850 return false;
1851 }
1852
1853 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1854 rx_buffer->page_offset, size, truesize);
1855
1856 /* avoid re-using remote pages */
1857 if (unlikely(page_to_nid(page) != numa_node_id()))
1858 return false;
1859
1860 #if (PAGE_SIZE < 8192)
1861 /* if we are only owner of page we can reuse it */
1862 if (unlikely(page_count(page) != 1))
1863 return false;
1864
1865 /* flip page offset to other buffer */
1866 rx_buffer->page_offset ^= truesize;
1867
1868 /*
1869 * since we are the only owner of the page and we need to
1870 * increment it, just set the value to 2 in order to avoid
1871 * an unecessary locked operation
1872 */
1873 atomic_set(&page->_count, 2);
1874 #else
1875 /* move offset up to the next cache line */
1876 rx_buffer->page_offset += truesize;
1877
1878 if (rx_buffer->page_offset > last_offset)
1879 return false;
1880
1881 /* bump ref count on page before it is given to the stack */
1882 get_page(page);
1883 #endif
1884
1885 return true;
1886 }
1887
1888 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1889 union ixgbe_adv_rx_desc *rx_desc)
1890 {
1891 struct ixgbe_rx_buffer *rx_buffer;
1892 struct sk_buff *skb;
1893 struct page *page;
1894
1895 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1896 page = rx_buffer->page;
1897 prefetchw(page);
1898
1899 skb = rx_buffer->skb;
1900
1901 if (likely(!skb)) {
1902 void *page_addr = page_address(page) +
1903 rx_buffer->page_offset;
1904
1905 /* prefetch first cache line of first page */
1906 prefetch(page_addr);
1907 #if L1_CACHE_BYTES < 128
1908 prefetch(page_addr + L1_CACHE_BYTES);
1909 #endif
1910
1911 /* allocate a skb to store the frags */
1912 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1913 IXGBE_RX_HDR_SIZE);
1914 if (unlikely(!skb)) {
1915 rx_ring->rx_stats.alloc_rx_buff_failed++;
1916 return NULL;
1917 }
1918
1919 /*
1920 * we will be copying header into skb->data in
1921 * pskb_may_pull so it is in our interest to prefetch
1922 * it now to avoid a possible cache miss
1923 */
1924 prefetchw(skb->data);
1925
1926 /*
1927 * Delay unmapping of the first packet. It carries the
1928 * header information, HW may still access the header
1929 * after the writeback. Only unmap it when EOP is
1930 * reached
1931 */
1932 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1933 goto dma_sync;
1934
1935 IXGBE_CB(skb)->dma = rx_buffer->dma;
1936 } else {
1937 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1938 ixgbe_dma_sync_frag(rx_ring, skb);
1939
1940 dma_sync:
1941 /* we are reusing so sync this buffer for CPU use */
1942 dma_sync_single_range_for_cpu(rx_ring->dev,
1943 rx_buffer->dma,
1944 rx_buffer->page_offset,
1945 ixgbe_rx_bufsz(rx_ring),
1946 DMA_FROM_DEVICE);
1947 }
1948
1949 /* pull page into skb */
1950 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1951 /* hand second half of page back to the ring */
1952 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1953 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1954 /* the page has been released from the ring */
1955 IXGBE_CB(skb)->page_released = true;
1956 } else {
1957 /* we are not reusing the buffer so unmap it */
1958 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1959 ixgbe_rx_pg_size(rx_ring),
1960 DMA_FROM_DEVICE);
1961 }
1962
1963 /* clear contents of buffer_info */
1964 rx_buffer->skb = NULL;
1965 rx_buffer->dma = 0;
1966 rx_buffer->page = NULL;
1967
1968 return skb;
1969 }
1970
1971 /**
1972 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1973 * @q_vector: structure containing interrupt and ring information
1974 * @rx_ring: rx descriptor ring to transact packets on
1975 * @budget: Total limit on number of packets to process
1976 *
1977 * This function provides a "bounce buffer" approach to Rx interrupt
1978 * processing. The advantage to this is that on systems that have
1979 * expensive overhead for IOMMU access this provides a means of avoiding
1980 * it by maintaining the mapping of the page to the syste.
1981 *
1982 * Returns amount of work completed
1983 **/
1984 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1985 struct ixgbe_ring *rx_ring,
1986 const int budget)
1987 {
1988 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1989 #ifdef IXGBE_FCOE
1990 struct ixgbe_adapter *adapter = q_vector->adapter;
1991 int ddp_bytes;
1992 unsigned int mss = 0;
1993 #endif /* IXGBE_FCOE */
1994 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1995
1996 while (likely(total_rx_packets < budget)) {
1997 union ixgbe_adv_rx_desc *rx_desc;
1998 struct sk_buff *skb;
1999
2000 /* return some buffers to hardware, one at a time is too slow */
2001 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2002 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2003 cleaned_count = 0;
2004 }
2005
2006 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2007
2008 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2009 break;
2010
2011 /*
2012 * This memory barrier is needed to keep us from reading
2013 * any other fields out of the rx_desc until we know the
2014 * RXD_STAT_DD bit is set
2015 */
2016 rmb();
2017
2018 /* retrieve a buffer from the ring */
2019 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
2020
2021 /* exit if we failed to retrieve a buffer */
2022 if (!skb)
2023 break;
2024
2025 cleaned_count++;
2026
2027 /* place incomplete frames back on ring for completion */
2028 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2029 continue;
2030
2031 /* verify the packet layout is correct */
2032 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2033 continue;
2034
2035 /* probably a little skewed due to removing CRC */
2036 total_rx_bytes += skb->len;
2037
2038 /* populate checksum, timestamp, VLAN, and protocol */
2039 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2040
2041 #ifdef IXGBE_FCOE
2042 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2043 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2044 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2045 /* include DDPed FCoE data */
2046 if (ddp_bytes > 0) {
2047 if (!mss) {
2048 mss = rx_ring->netdev->mtu -
2049 sizeof(struct fcoe_hdr) -
2050 sizeof(struct fc_frame_header) -
2051 sizeof(struct fcoe_crc_eof);
2052 if (mss > 512)
2053 mss &= ~511;
2054 }
2055 total_rx_bytes += ddp_bytes;
2056 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2057 mss);
2058 }
2059 if (!ddp_bytes) {
2060 dev_kfree_skb_any(skb);
2061 continue;
2062 }
2063 }
2064
2065 #endif /* IXGBE_FCOE */
2066 skb_mark_napi_id(skb, &q_vector->napi);
2067 ixgbe_rx_skb(q_vector, skb);
2068
2069 /* update budget accounting */
2070 total_rx_packets++;
2071 }
2072
2073 u64_stats_update_begin(&rx_ring->syncp);
2074 rx_ring->stats.packets += total_rx_packets;
2075 rx_ring->stats.bytes += total_rx_bytes;
2076 u64_stats_update_end(&rx_ring->syncp);
2077 q_vector->rx.total_packets += total_rx_packets;
2078 q_vector->rx.total_bytes += total_rx_bytes;
2079
2080 return total_rx_packets;
2081 }
2082
2083 #ifdef CONFIG_NET_RX_BUSY_POLL
2084 /* must be called with local_bh_disable()d */
2085 static int ixgbe_low_latency_recv(struct napi_struct *napi)
2086 {
2087 struct ixgbe_q_vector *q_vector =
2088 container_of(napi, struct ixgbe_q_vector, napi);
2089 struct ixgbe_adapter *adapter = q_vector->adapter;
2090 struct ixgbe_ring *ring;
2091 int found = 0;
2092
2093 if (test_bit(__IXGBE_DOWN, &adapter->state))
2094 return LL_FLUSH_FAILED;
2095
2096 if (!ixgbe_qv_lock_poll(q_vector))
2097 return LL_FLUSH_BUSY;
2098
2099 ixgbe_for_each_ring(ring, q_vector->rx) {
2100 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
2101 #ifdef BP_EXTENDED_STATS
2102 if (found)
2103 ring->stats.cleaned += found;
2104 else
2105 ring->stats.misses++;
2106 #endif
2107 if (found)
2108 break;
2109 }
2110
2111 ixgbe_qv_unlock_poll(q_vector);
2112
2113 return found;
2114 }
2115 #endif /* CONFIG_NET_RX_BUSY_POLL */
2116
2117 /**
2118 * ixgbe_configure_msix - Configure MSI-X hardware
2119 * @adapter: board private structure
2120 *
2121 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2122 * interrupts.
2123 **/
2124 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2125 {
2126 struct ixgbe_q_vector *q_vector;
2127 int v_idx;
2128 u32 mask;
2129
2130 /* Populate MSIX to EITR Select */
2131 if (adapter->num_vfs > 32) {
2132 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2133 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2134 }
2135
2136 /*
2137 * Populate the IVAR table and set the ITR values to the
2138 * corresponding register.
2139 */
2140 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2141 struct ixgbe_ring *ring;
2142 q_vector = adapter->q_vector[v_idx];
2143
2144 ixgbe_for_each_ring(ring, q_vector->rx)
2145 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2146
2147 ixgbe_for_each_ring(ring, q_vector->tx)
2148 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2149
2150 ixgbe_write_eitr(q_vector);
2151 }
2152
2153 switch (adapter->hw.mac.type) {
2154 case ixgbe_mac_82598EB:
2155 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2156 v_idx);
2157 break;
2158 case ixgbe_mac_82599EB:
2159 case ixgbe_mac_X540:
2160 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2161 break;
2162 default:
2163 break;
2164 }
2165 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2166
2167 /* set up to autoclear timer, and the vectors */
2168 mask = IXGBE_EIMS_ENABLE_MASK;
2169 mask &= ~(IXGBE_EIMS_OTHER |
2170 IXGBE_EIMS_MAILBOX |
2171 IXGBE_EIMS_LSC);
2172
2173 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2174 }
2175
2176 enum latency_range {
2177 lowest_latency = 0,
2178 low_latency = 1,
2179 bulk_latency = 2,
2180 latency_invalid = 255
2181 };
2182
2183 /**
2184 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2185 * @q_vector: structure containing interrupt and ring information
2186 * @ring_container: structure containing ring performance data
2187 *
2188 * Stores a new ITR value based on packets and byte
2189 * counts during the last interrupt. The advantage of per interrupt
2190 * computation is faster updates and more accurate ITR for the current
2191 * traffic pattern. Constants in this function were computed
2192 * based on theoretical maximum wire speed and thresholds were set based
2193 * on testing data as well as attempting to minimize response time
2194 * while increasing bulk throughput.
2195 * this functionality is controlled by the InterruptThrottleRate module
2196 * parameter (see ixgbe_param.c)
2197 **/
2198 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2199 struct ixgbe_ring_container *ring_container)
2200 {
2201 int bytes = ring_container->total_bytes;
2202 int packets = ring_container->total_packets;
2203 u32 timepassed_us;
2204 u64 bytes_perint;
2205 u8 itr_setting = ring_container->itr;
2206
2207 if (packets == 0)
2208 return;
2209
2210 /* simple throttlerate management
2211 * 0-10MB/s lowest (100000 ints/s)
2212 * 10-20MB/s low (20000 ints/s)
2213 * 20-1249MB/s bulk (8000 ints/s)
2214 */
2215 /* what was last interrupt timeslice? */
2216 timepassed_us = q_vector->itr >> 2;
2217 if (timepassed_us == 0)
2218 return;
2219
2220 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2221
2222 switch (itr_setting) {
2223 case lowest_latency:
2224 if (bytes_perint > 10)
2225 itr_setting = low_latency;
2226 break;
2227 case low_latency:
2228 if (bytes_perint > 20)
2229 itr_setting = bulk_latency;
2230 else if (bytes_perint <= 10)
2231 itr_setting = lowest_latency;
2232 break;
2233 case bulk_latency:
2234 if (bytes_perint <= 20)
2235 itr_setting = low_latency;
2236 break;
2237 }
2238
2239 /* clear work counters since we have the values we need */
2240 ring_container->total_bytes = 0;
2241 ring_container->total_packets = 0;
2242
2243 /* write updated itr to ring container */
2244 ring_container->itr = itr_setting;
2245 }
2246
2247 /**
2248 * ixgbe_write_eitr - write EITR register in hardware specific way
2249 * @q_vector: structure containing interrupt and ring information
2250 *
2251 * This function is made to be called by ethtool and by the driver
2252 * when it needs to update EITR registers at runtime. Hardware
2253 * specific quirks/differences are taken care of here.
2254 */
2255 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2256 {
2257 struct ixgbe_adapter *adapter = q_vector->adapter;
2258 struct ixgbe_hw *hw = &adapter->hw;
2259 int v_idx = q_vector->v_idx;
2260 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2261
2262 switch (adapter->hw.mac.type) {
2263 case ixgbe_mac_82598EB:
2264 /* must write high and low 16 bits to reset counter */
2265 itr_reg |= (itr_reg << 16);
2266 break;
2267 case ixgbe_mac_82599EB:
2268 case ixgbe_mac_X540:
2269 /*
2270 * set the WDIS bit to not clear the timer bits and cause an
2271 * immediate assertion of the interrupt
2272 */
2273 itr_reg |= IXGBE_EITR_CNT_WDIS;
2274 break;
2275 default:
2276 break;
2277 }
2278 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2279 }
2280
2281 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2282 {
2283 u32 new_itr = q_vector->itr;
2284 u8 current_itr;
2285
2286 ixgbe_update_itr(q_vector, &q_vector->tx);
2287 ixgbe_update_itr(q_vector, &q_vector->rx);
2288
2289 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2290
2291 switch (current_itr) {
2292 /* counts and packets in update_itr are dependent on these numbers */
2293 case lowest_latency:
2294 new_itr = IXGBE_100K_ITR;
2295 break;
2296 case low_latency:
2297 new_itr = IXGBE_20K_ITR;
2298 break;
2299 case bulk_latency:
2300 new_itr = IXGBE_8K_ITR;
2301 break;
2302 default:
2303 break;
2304 }
2305
2306 if (new_itr != q_vector->itr) {
2307 /* do an exponential smoothing */
2308 new_itr = (10 * new_itr * q_vector->itr) /
2309 ((9 * new_itr) + q_vector->itr);
2310
2311 /* save the algorithm value here */
2312 q_vector->itr = new_itr;
2313
2314 ixgbe_write_eitr(q_vector);
2315 }
2316 }
2317
2318 /**
2319 * ixgbe_check_overtemp_subtask - check for over temperature
2320 * @adapter: pointer to adapter
2321 **/
2322 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2323 {
2324 struct ixgbe_hw *hw = &adapter->hw;
2325 u32 eicr = adapter->interrupt_event;
2326
2327 if (test_bit(__IXGBE_DOWN, &adapter->state))
2328 return;
2329
2330 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2331 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2332 return;
2333
2334 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2335
2336 switch (hw->device_id) {
2337 case IXGBE_DEV_ID_82599_T3_LOM:
2338 /*
2339 * Since the warning interrupt is for both ports
2340 * we don't have to check if:
2341 * - This interrupt wasn't for our port.
2342 * - We may have missed the interrupt so always have to
2343 * check if we got a LSC
2344 */
2345 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2346 !(eicr & IXGBE_EICR_LSC))
2347 return;
2348
2349 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2350 u32 speed;
2351 bool link_up = false;
2352
2353 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2354
2355 if (link_up)
2356 return;
2357 }
2358
2359 /* Check if this is not due to overtemp */
2360 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2361 return;
2362
2363 break;
2364 default:
2365 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2366 return;
2367 break;
2368 }
2369 e_crit(drv,
2370 "Network adapter has been stopped because it has over heated. "
2371 "Restart the computer. If the problem persists, "
2372 "power off the system and replace the adapter\n");
2373
2374 adapter->interrupt_event = 0;
2375 }
2376
2377 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2378 {
2379 struct ixgbe_hw *hw = &adapter->hw;
2380
2381 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2382 (eicr & IXGBE_EICR_GPI_SDP1)) {
2383 e_crit(probe, "Fan has stopped, replace the adapter\n");
2384 /* write to clear the interrupt */
2385 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2386 }
2387 }
2388
2389 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2390 {
2391 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2392 return;
2393
2394 switch (adapter->hw.mac.type) {
2395 case ixgbe_mac_82599EB:
2396 /*
2397 * Need to check link state so complete overtemp check
2398 * on service task
2399 */
2400 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2401 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2402 adapter->interrupt_event = eicr;
2403 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2404 ixgbe_service_event_schedule(adapter);
2405 return;
2406 }
2407 return;
2408 case ixgbe_mac_X540:
2409 if (!(eicr & IXGBE_EICR_TS))
2410 return;
2411 break;
2412 default:
2413 return;
2414 }
2415
2416 e_crit(drv,
2417 "Network adapter has been stopped because it has over heated. "
2418 "Restart the computer. If the problem persists, "
2419 "power off the system and replace the adapter\n");
2420 }
2421
2422 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2423 {
2424 struct ixgbe_hw *hw = &adapter->hw;
2425
2426 if (eicr & IXGBE_EICR_GPI_SDP2) {
2427 /* Clear the interrupt */
2428 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2429 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2430 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2431 ixgbe_service_event_schedule(adapter);
2432 }
2433 }
2434
2435 if (eicr & IXGBE_EICR_GPI_SDP1) {
2436 /* Clear the interrupt */
2437 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2438 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2439 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2440 ixgbe_service_event_schedule(adapter);
2441 }
2442 }
2443 }
2444
2445 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2446 {
2447 struct ixgbe_hw *hw = &adapter->hw;
2448
2449 adapter->lsc_int++;
2450 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2451 adapter->link_check_timeout = jiffies;
2452 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2453 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2454 IXGBE_WRITE_FLUSH(hw);
2455 ixgbe_service_event_schedule(adapter);
2456 }
2457 }
2458
2459 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2460 u64 qmask)
2461 {
2462 u32 mask;
2463 struct ixgbe_hw *hw = &adapter->hw;
2464
2465 switch (hw->mac.type) {
2466 case ixgbe_mac_82598EB:
2467 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2468 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2469 break;
2470 case ixgbe_mac_82599EB:
2471 case ixgbe_mac_X540:
2472 mask = (qmask & 0xFFFFFFFF);
2473 if (mask)
2474 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2475 mask = (qmask >> 32);
2476 if (mask)
2477 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2478 break;
2479 default:
2480 break;
2481 }
2482 /* skip the flush */
2483 }
2484
2485 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2486 u64 qmask)
2487 {
2488 u32 mask;
2489 struct ixgbe_hw *hw = &adapter->hw;
2490
2491 switch (hw->mac.type) {
2492 case ixgbe_mac_82598EB:
2493 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2494 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2495 break;
2496 case ixgbe_mac_82599EB:
2497 case ixgbe_mac_X540:
2498 mask = (qmask & 0xFFFFFFFF);
2499 if (mask)
2500 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2501 mask = (qmask >> 32);
2502 if (mask)
2503 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2504 break;
2505 default:
2506 break;
2507 }
2508 /* skip the flush */
2509 }
2510
2511 /**
2512 * ixgbe_irq_enable - Enable default interrupt generation settings
2513 * @adapter: board private structure
2514 **/
2515 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2516 bool flush)
2517 {
2518 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2519
2520 /* don't reenable LSC while waiting for link */
2521 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2522 mask &= ~IXGBE_EIMS_LSC;
2523
2524 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2525 switch (adapter->hw.mac.type) {
2526 case ixgbe_mac_82599EB:
2527 mask |= IXGBE_EIMS_GPI_SDP0;
2528 break;
2529 case ixgbe_mac_X540:
2530 mask |= IXGBE_EIMS_TS;
2531 break;
2532 default:
2533 break;
2534 }
2535 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2536 mask |= IXGBE_EIMS_GPI_SDP1;
2537 switch (adapter->hw.mac.type) {
2538 case ixgbe_mac_82599EB:
2539 mask |= IXGBE_EIMS_GPI_SDP1;
2540 mask |= IXGBE_EIMS_GPI_SDP2;
2541 case ixgbe_mac_X540:
2542 mask |= IXGBE_EIMS_ECC;
2543 mask |= IXGBE_EIMS_MAILBOX;
2544 break;
2545 default:
2546 break;
2547 }
2548
2549 if (adapter->hw.mac.type == ixgbe_mac_X540)
2550 mask |= IXGBE_EIMS_TIMESYNC;
2551
2552 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2553 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2554 mask |= IXGBE_EIMS_FLOW_DIR;
2555
2556 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2557 if (queues)
2558 ixgbe_irq_enable_queues(adapter, ~0);
2559 if (flush)
2560 IXGBE_WRITE_FLUSH(&adapter->hw);
2561 }
2562
2563 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2564 {
2565 struct ixgbe_adapter *adapter = data;
2566 struct ixgbe_hw *hw = &adapter->hw;
2567 u32 eicr;
2568
2569 /*
2570 * Workaround for Silicon errata. Use clear-by-write instead
2571 * of clear-by-read. Reading with EICS will return the
2572 * interrupt causes without clearing, which later be done
2573 * with the write to EICR.
2574 */
2575 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2576
2577 /* The lower 16bits of the EICR register are for the queue interrupts
2578 * which should be masked here in order to not accidently clear them if
2579 * the bits are high when ixgbe_msix_other is called. There is a race
2580 * condition otherwise which results in possible performance loss
2581 * especially if the ixgbe_msix_other interrupt is triggering
2582 * consistently (as it would when PPS is turned on for the X540 device)
2583 */
2584 eicr &= 0xFFFF0000;
2585
2586 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2587
2588 if (eicr & IXGBE_EICR_LSC)
2589 ixgbe_check_lsc(adapter);
2590
2591 if (eicr & IXGBE_EICR_MAILBOX)
2592 ixgbe_msg_task(adapter);
2593
2594 switch (hw->mac.type) {
2595 case ixgbe_mac_82599EB:
2596 case ixgbe_mac_X540:
2597 if (eicr & IXGBE_EICR_ECC) {
2598 e_info(link, "Received ECC Err, initiating reset\n");
2599 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2600 ixgbe_service_event_schedule(adapter);
2601 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2602 }
2603 /* Handle Flow Director Full threshold interrupt */
2604 if (eicr & IXGBE_EICR_FLOW_DIR) {
2605 int reinit_count = 0;
2606 int i;
2607 for (i = 0; i < adapter->num_tx_queues; i++) {
2608 struct ixgbe_ring *ring = adapter->tx_ring[i];
2609 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2610 &ring->state))
2611 reinit_count++;
2612 }
2613 if (reinit_count) {
2614 /* no more flow director interrupts until after init */
2615 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2616 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2617 ixgbe_service_event_schedule(adapter);
2618 }
2619 }
2620 ixgbe_check_sfp_event(adapter, eicr);
2621 ixgbe_check_overtemp_event(adapter, eicr);
2622 break;
2623 default:
2624 break;
2625 }
2626
2627 ixgbe_check_fan_failure(adapter, eicr);
2628
2629 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2630 ixgbe_ptp_check_pps_event(adapter, eicr);
2631
2632 /* re-enable the original interrupt state, no lsc, no queues */
2633 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2634 ixgbe_irq_enable(adapter, false, false);
2635
2636 return IRQ_HANDLED;
2637 }
2638
2639 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2640 {
2641 struct ixgbe_q_vector *q_vector = data;
2642
2643 /* EIAM disabled interrupts (on this vector) for us */
2644
2645 if (q_vector->rx.ring || q_vector->tx.ring)
2646 napi_schedule(&q_vector->napi);
2647
2648 return IRQ_HANDLED;
2649 }
2650
2651 /**
2652 * ixgbe_poll - NAPI Rx polling callback
2653 * @napi: structure for representing this polling device
2654 * @budget: how many packets driver is allowed to clean
2655 *
2656 * This function is used for legacy and MSI, NAPI mode
2657 **/
2658 int ixgbe_poll(struct napi_struct *napi, int budget)
2659 {
2660 struct ixgbe_q_vector *q_vector =
2661 container_of(napi, struct ixgbe_q_vector, napi);
2662 struct ixgbe_adapter *adapter = q_vector->adapter;
2663 struct ixgbe_ring *ring;
2664 int per_ring_budget;
2665 bool clean_complete = true;
2666
2667 #ifdef CONFIG_IXGBE_DCA
2668 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2669 ixgbe_update_dca(q_vector);
2670 #endif
2671
2672 ixgbe_for_each_ring(ring, q_vector->tx)
2673 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2674
2675 if (!ixgbe_qv_lock_napi(q_vector))
2676 return budget;
2677
2678 /* attempt to distribute budget to each queue fairly, but don't allow
2679 * the budget to go below 1 because we'll exit polling */
2680 if (q_vector->rx.count > 1)
2681 per_ring_budget = max(budget/q_vector->rx.count, 1);
2682 else
2683 per_ring_budget = budget;
2684
2685 ixgbe_for_each_ring(ring, q_vector->rx)
2686 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2687 per_ring_budget) < per_ring_budget);
2688
2689 ixgbe_qv_unlock_napi(q_vector);
2690 /* If all work not completed, return budget and keep polling */
2691 if (!clean_complete)
2692 return budget;
2693
2694 /* all work done, exit the polling mode */
2695 napi_complete(napi);
2696 if (adapter->rx_itr_setting & 1)
2697 ixgbe_set_itr(q_vector);
2698 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2699 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2700
2701 return 0;
2702 }
2703
2704 /**
2705 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2706 * @adapter: board private structure
2707 *
2708 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2709 * interrupts from the kernel.
2710 **/
2711 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2712 {
2713 struct net_device *netdev = adapter->netdev;
2714 int vector, err;
2715 int ri = 0, ti = 0;
2716
2717 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2718 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2719 struct msix_entry *entry = &adapter->msix_entries[vector];
2720
2721 if (q_vector->tx.ring && q_vector->rx.ring) {
2722 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2723 "%s-%s-%d", netdev->name, "TxRx", ri++);
2724 ti++;
2725 } else if (q_vector->rx.ring) {
2726 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2727 "%s-%s-%d", netdev->name, "rx", ri++);
2728 } else if (q_vector->tx.ring) {
2729 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2730 "%s-%s-%d", netdev->name, "tx", ti++);
2731 } else {
2732 /* skip this unused q_vector */
2733 continue;
2734 }
2735 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2736 q_vector->name, q_vector);
2737 if (err) {
2738 e_err(probe, "request_irq failed for MSIX interrupt "
2739 "Error: %d\n", err);
2740 goto free_queue_irqs;
2741 }
2742 /* If Flow Director is enabled, set interrupt affinity */
2743 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2744 /* assign the mask for this irq */
2745 irq_set_affinity_hint(entry->vector,
2746 &q_vector->affinity_mask);
2747 }
2748 }
2749
2750 err = request_irq(adapter->msix_entries[vector].vector,
2751 ixgbe_msix_other, 0, netdev->name, adapter);
2752 if (err) {
2753 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2754 goto free_queue_irqs;
2755 }
2756
2757 return 0;
2758
2759 free_queue_irqs:
2760 while (vector) {
2761 vector--;
2762 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2763 NULL);
2764 free_irq(adapter->msix_entries[vector].vector,
2765 adapter->q_vector[vector]);
2766 }
2767 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2768 pci_disable_msix(adapter->pdev);
2769 kfree(adapter->msix_entries);
2770 adapter->msix_entries = NULL;
2771 return err;
2772 }
2773
2774 /**
2775 * ixgbe_intr - legacy mode Interrupt Handler
2776 * @irq: interrupt number
2777 * @data: pointer to a network interface device structure
2778 **/
2779 static irqreturn_t ixgbe_intr(int irq, void *data)
2780 {
2781 struct ixgbe_adapter *adapter = data;
2782 struct ixgbe_hw *hw = &adapter->hw;
2783 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2784 u32 eicr;
2785
2786 /*
2787 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2788 * before the read of EICR.
2789 */
2790 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2791
2792 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2793 * therefore no explicit interrupt disable is necessary */
2794 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2795 if (!eicr) {
2796 /*
2797 * shared interrupt alert!
2798 * make sure interrupts are enabled because the read will
2799 * have disabled interrupts due to EIAM
2800 * finish the workaround of silicon errata on 82598. Unmask
2801 * the interrupt that we masked before the EICR read.
2802 */
2803 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2804 ixgbe_irq_enable(adapter, true, true);
2805 return IRQ_NONE; /* Not our interrupt */
2806 }
2807
2808 if (eicr & IXGBE_EICR_LSC)
2809 ixgbe_check_lsc(adapter);
2810
2811 switch (hw->mac.type) {
2812 case ixgbe_mac_82599EB:
2813 ixgbe_check_sfp_event(adapter, eicr);
2814 /* Fall through */
2815 case ixgbe_mac_X540:
2816 if (eicr & IXGBE_EICR_ECC) {
2817 e_info(link, "Received ECC Err, initiating reset\n");
2818 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2819 ixgbe_service_event_schedule(adapter);
2820 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2821 }
2822 ixgbe_check_overtemp_event(adapter, eicr);
2823 break;
2824 default:
2825 break;
2826 }
2827
2828 ixgbe_check_fan_failure(adapter, eicr);
2829 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2830 ixgbe_ptp_check_pps_event(adapter, eicr);
2831
2832 /* would disable interrupts here but EIAM disabled it */
2833 napi_schedule(&q_vector->napi);
2834
2835 /*
2836 * re-enable link(maybe) and non-queue interrupts, no flush.
2837 * ixgbe_poll will re-enable the queue interrupts
2838 */
2839 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2840 ixgbe_irq_enable(adapter, false, false);
2841
2842 return IRQ_HANDLED;
2843 }
2844
2845 /**
2846 * ixgbe_request_irq - initialize interrupts
2847 * @adapter: board private structure
2848 *
2849 * Attempts to configure interrupts using the best available
2850 * capabilities of the hardware and kernel.
2851 **/
2852 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2853 {
2854 struct net_device *netdev = adapter->netdev;
2855 int err;
2856
2857 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2858 err = ixgbe_request_msix_irqs(adapter);
2859 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2860 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2861 netdev->name, adapter);
2862 else
2863 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2864 netdev->name, adapter);
2865
2866 if (err)
2867 e_err(probe, "request_irq failed, Error %d\n", err);
2868
2869 return err;
2870 }
2871
2872 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2873 {
2874 int vector;
2875
2876 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2877 free_irq(adapter->pdev->irq, adapter);
2878 return;
2879 }
2880
2881 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2882 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2883 struct msix_entry *entry = &adapter->msix_entries[vector];
2884
2885 /* free only the irqs that were actually requested */
2886 if (!q_vector->rx.ring && !q_vector->tx.ring)
2887 continue;
2888
2889 /* clear the affinity_mask in the IRQ descriptor */
2890 irq_set_affinity_hint(entry->vector, NULL);
2891
2892 free_irq(entry->vector, q_vector);
2893 }
2894
2895 free_irq(adapter->msix_entries[vector++].vector, adapter);
2896 }
2897
2898 /**
2899 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2900 * @adapter: board private structure
2901 **/
2902 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2903 {
2904 switch (adapter->hw.mac.type) {
2905 case ixgbe_mac_82598EB:
2906 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2907 break;
2908 case ixgbe_mac_82599EB:
2909 case ixgbe_mac_X540:
2910 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2911 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2912 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2913 break;
2914 default:
2915 break;
2916 }
2917 IXGBE_WRITE_FLUSH(&adapter->hw);
2918 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2919 int vector;
2920
2921 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2922 synchronize_irq(adapter->msix_entries[vector].vector);
2923
2924 synchronize_irq(adapter->msix_entries[vector++].vector);
2925 } else {
2926 synchronize_irq(adapter->pdev->irq);
2927 }
2928 }
2929
2930 /**
2931 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2932 *
2933 **/
2934 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2935 {
2936 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2937
2938 ixgbe_write_eitr(q_vector);
2939
2940 ixgbe_set_ivar(adapter, 0, 0, 0);
2941 ixgbe_set_ivar(adapter, 1, 0, 0);
2942
2943 e_info(hw, "Legacy interrupt IVAR setup done\n");
2944 }
2945
2946 /**
2947 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2948 * @adapter: board private structure
2949 * @ring: structure containing ring specific data
2950 *
2951 * Configure the Tx descriptor ring after a reset.
2952 **/
2953 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2954 struct ixgbe_ring *ring)
2955 {
2956 struct ixgbe_hw *hw = &adapter->hw;
2957 u64 tdba = ring->dma;
2958 int wait_loop = 10;
2959 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2960 u8 reg_idx = ring->reg_idx;
2961
2962 /* disable queue to avoid issues while updating state */
2963 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2964 IXGBE_WRITE_FLUSH(hw);
2965
2966 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2967 (tdba & DMA_BIT_MASK(32)));
2968 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2969 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2970 ring->count * sizeof(union ixgbe_adv_tx_desc));
2971 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2972 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2973 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
2974
2975 /*
2976 * set WTHRESH to encourage burst writeback, it should not be set
2977 * higher than 1 when:
2978 * - ITR is 0 as it could cause false TX hangs
2979 * - ITR is set to > 100k int/sec and BQL is enabled
2980 *
2981 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2982 * to or less than the number of on chip descriptors, which is
2983 * currently 40.
2984 */
2985 #if IS_ENABLED(CONFIG_BQL)
2986 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
2987 #else
2988 if (!ring->q_vector || (ring->q_vector->itr < 8))
2989 #endif
2990 txdctl |= (1 << 16); /* WTHRESH = 1 */
2991 else
2992 txdctl |= (8 << 16); /* WTHRESH = 8 */
2993
2994 /*
2995 * Setting PTHRESH to 32 both improves performance
2996 * and avoids a TX hang with DFP enabled
2997 */
2998 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2999 32; /* PTHRESH = 32 */
3000
3001 /* reinitialize flowdirector state */
3002 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3003 ring->atr_sample_rate = adapter->atr_sample_rate;
3004 ring->atr_count = 0;
3005 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3006 } else {
3007 ring->atr_sample_rate = 0;
3008 }
3009
3010 /* initialize XPS */
3011 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3012 struct ixgbe_q_vector *q_vector = ring->q_vector;
3013
3014 if (q_vector)
3015 netif_set_xps_queue(ring->netdev,
3016 &q_vector->affinity_mask,
3017 ring->queue_index);
3018 }
3019
3020 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3021
3022 /* enable queue */
3023 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3024
3025 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3026 if (hw->mac.type == ixgbe_mac_82598EB &&
3027 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3028 return;
3029
3030 /* poll to verify queue is enabled */
3031 do {
3032 usleep_range(1000, 2000);
3033 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3034 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3035 if (!wait_loop)
3036 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
3037 }
3038
3039 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3040 {
3041 struct ixgbe_hw *hw = &adapter->hw;
3042 u32 rttdcs, mtqc;
3043 u8 tcs = netdev_get_num_tc(adapter->netdev);
3044
3045 if (hw->mac.type == ixgbe_mac_82598EB)
3046 return;
3047
3048 /* disable the arbiter while setting MTQC */
3049 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3050 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3051 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3052
3053 /* set transmit pool layout */
3054 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3055 mtqc = IXGBE_MTQC_VT_ENA;
3056 if (tcs > 4)
3057 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3058 else if (tcs > 1)
3059 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3060 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3061 mtqc |= IXGBE_MTQC_32VF;
3062 else
3063 mtqc |= IXGBE_MTQC_64VF;
3064 } else {
3065 if (tcs > 4)
3066 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3067 else if (tcs > 1)
3068 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3069 else
3070 mtqc = IXGBE_MTQC_64Q_1PB;
3071 }
3072
3073 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3074
3075 /* Enable Security TX Buffer IFG for multiple pb */
3076 if (tcs) {
3077 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3078 sectx |= IXGBE_SECTX_DCB;
3079 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3080 }
3081
3082 /* re-enable the arbiter */
3083 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3084 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3085 }
3086
3087 /**
3088 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3089 * @adapter: board private structure
3090 *
3091 * Configure the Tx unit of the MAC after a reset.
3092 **/
3093 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3094 {
3095 struct ixgbe_hw *hw = &adapter->hw;
3096 u32 dmatxctl;
3097 u32 i;
3098
3099 ixgbe_setup_mtqc(adapter);
3100
3101 if (hw->mac.type != ixgbe_mac_82598EB) {
3102 /* DMATXCTL.EN must be before Tx queues are enabled */
3103 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3104 dmatxctl |= IXGBE_DMATXCTL_TE;
3105 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3106 }
3107
3108 /* Setup the HW Tx Head and Tail descriptor pointers */
3109 for (i = 0; i < adapter->num_tx_queues; i++)
3110 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3111 }
3112
3113 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3114 struct ixgbe_ring *ring)
3115 {
3116 struct ixgbe_hw *hw = &adapter->hw;
3117 u8 reg_idx = ring->reg_idx;
3118 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3119
3120 srrctl |= IXGBE_SRRCTL_DROP_EN;
3121
3122 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3123 }
3124
3125 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3126 struct ixgbe_ring *ring)
3127 {
3128 struct ixgbe_hw *hw = &adapter->hw;
3129 u8 reg_idx = ring->reg_idx;
3130 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3131
3132 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3133
3134 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3135 }
3136
3137 #ifdef CONFIG_IXGBE_DCB
3138 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3139 #else
3140 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3141 #endif
3142 {
3143 int i;
3144 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3145
3146 if (adapter->ixgbe_ieee_pfc)
3147 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3148
3149 /*
3150 * We should set the drop enable bit if:
3151 * SR-IOV is enabled
3152 * or
3153 * Number of Rx queues > 1 and flow control is disabled
3154 *
3155 * This allows us to avoid head of line blocking for security
3156 * and performance reasons.
3157 */
3158 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3159 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3160 for (i = 0; i < adapter->num_rx_queues; i++)
3161 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3162 } else {
3163 for (i = 0; i < adapter->num_rx_queues; i++)
3164 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3165 }
3166 }
3167
3168 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3169
3170 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3171 struct ixgbe_ring *rx_ring)
3172 {
3173 struct ixgbe_hw *hw = &adapter->hw;
3174 u32 srrctl;
3175 u8 reg_idx = rx_ring->reg_idx;
3176
3177 if (hw->mac.type == ixgbe_mac_82598EB) {
3178 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3179
3180 /*
3181 * if VMDq is not active we must program one srrctl register
3182 * per RSS queue since we have enabled RDRXCTL.MVMEN
3183 */
3184 reg_idx &= mask;
3185 }
3186
3187 /* configure header buffer length, needed for RSC */
3188 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3189
3190 /* configure the packet buffer length */
3191 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3192
3193 /* configure descriptor type */
3194 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3195
3196 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3197 }
3198
3199 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3200 {
3201 struct ixgbe_hw *hw = &adapter->hw;
3202 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
3203 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3204 0x6A3E67EA, 0x14364D17, 0x3BED200D};
3205 u32 mrqc = 0, reta = 0;
3206 u32 rxcsum;
3207 int i, j;
3208 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3209
3210 /*
3211 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3212 * make full use of any rings they may have. We will use the
3213 * PSRTYPE register to control how many rings we use within the PF.
3214 */
3215 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3216 rss_i = 2;
3217
3218 /* Fill out hash function seeds */
3219 for (i = 0; i < 10; i++)
3220 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3221
3222 /* Fill out redirection table */
3223 for (i = 0, j = 0; i < 128; i++, j++) {
3224 if (j == rss_i)
3225 j = 0;
3226 /* reta = 4-byte sliding window of
3227 * 0x00..(indices-1)(indices-1)00..etc. */
3228 reta = (reta << 8) | (j * 0x11);
3229 if ((i & 3) == 3)
3230 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3231 }
3232
3233 /* Disable indicating checksum in descriptor, enables RSS hash */
3234 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3235 rxcsum |= IXGBE_RXCSUM_PCSD;
3236 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3237
3238 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3239 if (adapter->ring_feature[RING_F_RSS].mask)
3240 mrqc = IXGBE_MRQC_RSSEN;
3241 } else {
3242 u8 tcs = netdev_get_num_tc(adapter->netdev);
3243
3244 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3245 if (tcs > 4)
3246 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3247 else if (tcs > 1)
3248 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3249 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3250 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3251 else
3252 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3253 } else {
3254 if (tcs > 4)
3255 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3256 else if (tcs > 1)
3257 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3258 else
3259 mrqc = IXGBE_MRQC_RSSEN;
3260 }
3261 }
3262
3263 /* Perform hash on these packet types */
3264 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3265 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3266 IXGBE_MRQC_RSS_FIELD_IPV6 |
3267 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3268
3269 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3270 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3271 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3272 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3273
3274 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3275 }
3276
3277 /**
3278 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3279 * @adapter: address of board private structure
3280 * @index: index of ring to set
3281 **/
3282 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3283 struct ixgbe_ring *ring)
3284 {
3285 struct ixgbe_hw *hw = &adapter->hw;
3286 u32 rscctrl;
3287 u8 reg_idx = ring->reg_idx;
3288
3289 if (!ring_is_rsc_enabled(ring))
3290 return;
3291
3292 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3293 rscctrl |= IXGBE_RSCCTL_RSCEN;
3294 /*
3295 * we must limit the number of descriptors so that the
3296 * total size of max desc * buf_len is not greater
3297 * than 65536
3298 */
3299 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3300 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3301 }
3302
3303 #define IXGBE_MAX_RX_DESC_POLL 10
3304 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3305 struct ixgbe_ring *ring)
3306 {
3307 struct ixgbe_hw *hw = &adapter->hw;
3308 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3309 u32 rxdctl;
3310 u8 reg_idx = ring->reg_idx;
3311
3312 if (ixgbe_removed(hw->hw_addr))
3313 return;
3314 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3315 if (hw->mac.type == ixgbe_mac_82598EB &&
3316 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3317 return;
3318
3319 do {
3320 usleep_range(1000, 2000);
3321 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3322 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3323
3324 if (!wait_loop) {
3325 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3326 "the polling period\n", reg_idx);
3327 }
3328 }
3329
3330 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3331 struct ixgbe_ring *ring)
3332 {
3333 struct ixgbe_hw *hw = &adapter->hw;
3334 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3335 u32 rxdctl;
3336 u8 reg_idx = ring->reg_idx;
3337
3338 if (ixgbe_removed(hw->hw_addr))
3339 return;
3340 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3341 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3342
3343 /* write value back with RXDCTL.ENABLE bit cleared */
3344 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3345
3346 if (hw->mac.type == ixgbe_mac_82598EB &&
3347 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3348 return;
3349
3350 /* the hardware may take up to 100us to really disable the rx queue */
3351 do {
3352 udelay(10);
3353 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3354 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3355
3356 if (!wait_loop) {
3357 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3358 "the polling period\n", reg_idx);
3359 }
3360 }
3361
3362 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3363 struct ixgbe_ring *ring)
3364 {
3365 struct ixgbe_hw *hw = &adapter->hw;
3366 u64 rdba = ring->dma;
3367 u32 rxdctl;
3368 u8 reg_idx = ring->reg_idx;
3369
3370 /* disable queue to avoid issues while updating state */
3371 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3372 ixgbe_disable_rx_queue(adapter, ring);
3373
3374 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3375 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3376 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3377 ring->count * sizeof(union ixgbe_adv_rx_desc));
3378 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3379 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3380 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
3381
3382 ixgbe_configure_srrctl(adapter, ring);
3383 ixgbe_configure_rscctl(adapter, ring);
3384
3385 if (hw->mac.type == ixgbe_mac_82598EB) {
3386 /*
3387 * enable cache line friendly hardware writes:
3388 * PTHRESH=32 descriptors (half the internal cache),
3389 * this also removes ugly rx_no_buffer_count increment
3390 * HTHRESH=4 descriptors (to minimize latency on fetch)
3391 * WTHRESH=8 burst writeback up to two cache lines
3392 */
3393 rxdctl &= ~0x3FFFFF;
3394 rxdctl |= 0x080420;
3395 }
3396
3397 /* enable receive descriptor ring */
3398 rxdctl |= IXGBE_RXDCTL_ENABLE;
3399 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3400
3401 ixgbe_rx_desc_queue_enable(adapter, ring);
3402 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3403 }
3404
3405 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3406 {
3407 struct ixgbe_hw *hw = &adapter->hw;
3408 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3409 u16 pool;
3410
3411 /* PSRTYPE must be initialized in non 82598 adapters */
3412 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3413 IXGBE_PSRTYPE_UDPHDR |
3414 IXGBE_PSRTYPE_IPV4HDR |
3415 IXGBE_PSRTYPE_L2HDR |
3416 IXGBE_PSRTYPE_IPV6HDR;
3417
3418 if (hw->mac.type == ixgbe_mac_82598EB)
3419 return;
3420
3421 if (rss_i > 3)
3422 psrtype |= 2 << 29;
3423 else if (rss_i > 1)
3424 psrtype |= 1 << 29;
3425
3426 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3427 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
3428 }
3429
3430 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3431 {
3432 struct ixgbe_hw *hw = &adapter->hw;
3433 u32 reg_offset, vf_shift;
3434 u32 gcr_ext, vmdctl;
3435 int i;
3436
3437 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3438 return;
3439
3440 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3441 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3442 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3443 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3444 vmdctl |= IXGBE_VT_CTL_REPLEN;
3445 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3446
3447 vf_shift = VMDQ_P(0) % 32;
3448 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3449
3450 /* Enable only the PF's pool for Tx/Rx */
3451 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3452 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3453 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3454 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3455 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3456 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3457
3458 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3459 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3460
3461 /*
3462 * Set up VF register offsets for selected VT Mode,
3463 * i.e. 32 or 64 VFs for SR-IOV
3464 */
3465 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3466 case IXGBE_82599_VMDQ_8Q_MASK:
3467 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3468 break;
3469 case IXGBE_82599_VMDQ_4Q_MASK:
3470 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3471 break;
3472 default:
3473 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3474 break;
3475 }
3476
3477 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3478
3479
3480 /* Enable MAC Anti-Spoofing */
3481 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3482 adapter->num_vfs);
3483 /* For VFs that have spoof checking turned off */
3484 for (i = 0; i < adapter->num_vfs; i++) {
3485 if (!adapter->vfinfo[i].spoofchk_enabled)
3486 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3487 }
3488 }
3489
3490 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3491 {
3492 struct ixgbe_hw *hw = &adapter->hw;
3493 struct net_device *netdev = adapter->netdev;
3494 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3495 struct ixgbe_ring *rx_ring;
3496 int i;
3497 u32 mhadd, hlreg0;
3498
3499 #ifdef IXGBE_FCOE
3500 /* adjust max frame to be able to do baby jumbo for FCoE */
3501 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3502 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3503 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3504
3505 #endif /* IXGBE_FCOE */
3506
3507 /* adjust max frame to be at least the size of a standard frame */
3508 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3509 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3510
3511 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3512 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3513 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3514 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3515
3516 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3517 }
3518
3519 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3520 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3521 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3522 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3523
3524 /*
3525 * Setup the HW Rx Head and Tail Descriptor Pointers and
3526 * the Base and Length of the Rx Descriptor Ring
3527 */
3528 for (i = 0; i < adapter->num_rx_queues; i++) {
3529 rx_ring = adapter->rx_ring[i];
3530 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3531 set_ring_rsc_enabled(rx_ring);
3532 else
3533 clear_ring_rsc_enabled(rx_ring);
3534 }
3535 }
3536
3537 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3538 {
3539 struct ixgbe_hw *hw = &adapter->hw;
3540 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3541
3542 switch (hw->mac.type) {
3543 case ixgbe_mac_82598EB:
3544 /*
3545 * For VMDq support of different descriptor types or
3546 * buffer sizes through the use of multiple SRRCTL
3547 * registers, RDRXCTL.MVMEN must be set to 1
3548 *
3549 * also, the manual doesn't mention it clearly but DCA hints
3550 * will only use queue 0's tags unless this bit is set. Side
3551 * effects of setting this bit are only that SRRCTL must be
3552 * fully programmed [0..15]
3553 */
3554 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3555 break;
3556 case ixgbe_mac_82599EB:
3557 case ixgbe_mac_X540:
3558 /* Disable RSC for ACK packets */
3559 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3560 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3561 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3562 /* hardware requires some bits to be set by default */
3563 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3564 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3565 break;
3566 default:
3567 /* We should do nothing since we don't know this hardware */
3568 return;
3569 }
3570
3571 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3572 }
3573
3574 /**
3575 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3576 * @adapter: board private structure
3577 *
3578 * Configure the Rx unit of the MAC after a reset.
3579 **/
3580 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3581 {
3582 struct ixgbe_hw *hw = &adapter->hw;
3583 int i;
3584 u32 rxctrl, rfctl;
3585
3586 /* disable receives while setting up the descriptors */
3587 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3588 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3589
3590 ixgbe_setup_psrtype(adapter);
3591 ixgbe_setup_rdrxctl(adapter);
3592
3593 /* RSC Setup */
3594 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3595 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3596 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3597 rfctl |= IXGBE_RFCTL_RSC_DIS;
3598 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3599
3600 /* Program registers for the distribution of queues */
3601 ixgbe_setup_mrqc(adapter);
3602
3603 /* set_rx_buffer_len must be called before ring initialization */
3604 ixgbe_set_rx_buffer_len(adapter);
3605
3606 /*
3607 * Setup the HW Rx Head and Tail Descriptor Pointers and
3608 * the Base and Length of the Rx Descriptor Ring
3609 */
3610 for (i = 0; i < adapter->num_rx_queues; i++)
3611 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3612
3613 /* disable drop enable for 82598 parts */
3614 if (hw->mac.type == ixgbe_mac_82598EB)
3615 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3616
3617 /* enable all receives */
3618 rxctrl |= IXGBE_RXCTRL_RXEN;
3619 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3620 }
3621
3622 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3623 __be16 proto, u16 vid)
3624 {
3625 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3626 struct ixgbe_hw *hw = &adapter->hw;
3627
3628 /* add VID to filter table */
3629 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3630 set_bit(vid, adapter->active_vlans);
3631
3632 return 0;
3633 }
3634
3635 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3636 __be16 proto, u16 vid)
3637 {
3638 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3639 struct ixgbe_hw *hw = &adapter->hw;
3640
3641 /* remove VID from filter table */
3642 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3643 clear_bit(vid, adapter->active_vlans);
3644
3645 return 0;
3646 }
3647
3648 /**
3649 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3650 * @adapter: driver data
3651 */
3652 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3653 {
3654 struct ixgbe_hw *hw = &adapter->hw;
3655 u32 vlnctrl;
3656 int i, j;
3657
3658 switch (hw->mac.type) {
3659 case ixgbe_mac_82598EB:
3660 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3661 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3662 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3663 break;
3664 case ixgbe_mac_82599EB:
3665 case ixgbe_mac_X540:
3666 for (i = 0; i < adapter->num_rx_queues; i++) {
3667 struct ixgbe_ring *ring = adapter->rx_ring[i];
3668
3669 if (ring->l2_accel_priv)
3670 continue;
3671 j = ring->reg_idx;
3672 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3673 vlnctrl &= ~IXGBE_RXDCTL_VME;
3674 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3675 }
3676 break;
3677 default:
3678 break;
3679 }
3680 }
3681
3682 /**
3683 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3684 * @adapter: driver data
3685 */
3686 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3687 {
3688 struct ixgbe_hw *hw = &adapter->hw;
3689 u32 vlnctrl;
3690 int i, j;
3691
3692 switch (hw->mac.type) {
3693 case ixgbe_mac_82598EB:
3694 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3695 vlnctrl |= IXGBE_VLNCTRL_VME;
3696 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3697 break;
3698 case ixgbe_mac_82599EB:
3699 case ixgbe_mac_X540:
3700 for (i = 0; i < adapter->num_rx_queues; i++) {
3701 struct ixgbe_ring *ring = adapter->rx_ring[i];
3702
3703 if (ring->l2_accel_priv)
3704 continue;
3705 j = ring->reg_idx;
3706 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3707 vlnctrl |= IXGBE_RXDCTL_VME;
3708 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3709 }
3710 break;
3711 default:
3712 break;
3713 }
3714 }
3715
3716 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3717 {
3718 u16 vid;
3719
3720 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
3721
3722 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3723 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
3724 }
3725
3726 /**
3727 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
3728 * @netdev: network interface device structure
3729 *
3730 * Writes multicast address list to the MTA hash table.
3731 * Returns: -ENOMEM on failure
3732 * 0 on no addresses written
3733 * X on writing X addresses to MTA
3734 **/
3735 static int ixgbe_write_mc_addr_list(struct net_device *netdev)
3736 {
3737 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3738 struct ixgbe_hw *hw = &adapter->hw;
3739
3740 if (!netif_running(netdev))
3741 return 0;
3742
3743 if (hw->mac.ops.update_mc_addr_list)
3744 hw->mac.ops.update_mc_addr_list(hw, netdev);
3745 else
3746 return -ENOMEM;
3747
3748 #ifdef CONFIG_PCI_IOV
3749 ixgbe_restore_vf_multicasts(adapter);
3750 #endif
3751
3752 return netdev_mc_count(netdev);
3753 }
3754
3755 #ifdef CONFIG_PCI_IOV
3756 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
3757 {
3758 struct ixgbe_hw *hw = &adapter->hw;
3759 int i;
3760 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3761 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3762 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
3763 adapter->mac_table[i].queue,
3764 IXGBE_RAH_AV);
3765 else
3766 hw->mac.ops.clear_rar(hw, i);
3767
3768 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED);
3769 }
3770 }
3771 #endif
3772
3773 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
3774 {
3775 struct ixgbe_hw *hw = &adapter->hw;
3776 int i;
3777 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3778 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
3779 if (adapter->mac_table[i].state &
3780 IXGBE_MAC_STATE_IN_USE)
3781 hw->mac.ops.set_rar(hw, i,
3782 adapter->mac_table[i].addr,
3783 adapter->mac_table[i].queue,
3784 IXGBE_RAH_AV);
3785 else
3786 hw->mac.ops.clear_rar(hw, i);
3787
3788 adapter->mac_table[i].state &=
3789 ~(IXGBE_MAC_STATE_MODIFIED);
3790 }
3791 }
3792 }
3793
3794 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
3795 {
3796 int i;
3797 struct ixgbe_hw *hw = &adapter->hw;
3798
3799 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3800 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3801 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
3802 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
3803 adapter->mac_table[i].queue = 0;
3804 }
3805 ixgbe_sync_mac_table(adapter);
3806 }
3807
3808 static int ixgbe_available_rars(struct ixgbe_adapter *adapter)
3809 {
3810 struct ixgbe_hw *hw = &adapter->hw;
3811 int i, count = 0;
3812
3813 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3814 if (adapter->mac_table[i].state == 0)
3815 count++;
3816 }
3817 return count;
3818 }
3819
3820 /* this function destroys the first RAR entry */
3821 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter,
3822 u8 *addr)
3823 {
3824 struct ixgbe_hw *hw = &adapter->hw;
3825
3826 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN);
3827 adapter->mac_table[0].queue = VMDQ_P(0);
3828 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
3829 IXGBE_MAC_STATE_IN_USE);
3830 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
3831 adapter->mac_table[0].queue,
3832 IXGBE_RAH_AV);
3833 }
3834
3835 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3836 {
3837 struct ixgbe_hw *hw = &adapter->hw;
3838 int i;
3839
3840 if (is_zero_ether_addr(addr))
3841 return -EINVAL;
3842
3843 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3844 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3845 continue;
3846 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
3847 IXGBE_MAC_STATE_IN_USE);
3848 ether_addr_copy(adapter->mac_table[i].addr, addr);
3849 adapter->mac_table[i].queue = queue;
3850 ixgbe_sync_mac_table(adapter);
3851 return i;
3852 }
3853 return -ENOMEM;
3854 }
3855
3856 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3857 {
3858 /* search table for addr, if found, set to 0 and sync */
3859 int i;
3860 struct ixgbe_hw *hw = &adapter->hw;
3861
3862 if (is_zero_ether_addr(addr))
3863 return -EINVAL;
3864
3865 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3866 if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
3867 adapter->mac_table[i].queue == queue) {
3868 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3869 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
3870 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
3871 adapter->mac_table[i].queue = 0;
3872 ixgbe_sync_mac_table(adapter);
3873 return 0;
3874 }
3875 }
3876 return -ENOMEM;
3877 }
3878 /**
3879 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3880 * @netdev: network interface device structure
3881 *
3882 * Writes unicast address list to the RAR table.
3883 * Returns: -ENOMEM on failure/insufficient address space
3884 * 0 on no addresses written
3885 * X on writing X addresses to the RAR table
3886 **/
3887 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
3888 {
3889 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3890 int count = 0;
3891
3892 /* return ENOMEM indicating insufficient memory for addresses */
3893 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
3894 return -ENOMEM;
3895
3896 if (!netdev_uc_empty(netdev)) {
3897 struct netdev_hw_addr *ha;
3898 netdev_for_each_uc_addr(ha, netdev) {
3899 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
3900 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
3901 count++;
3902 }
3903 }
3904 return count;
3905 }
3906
3907 /**
3908 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3909 * @netdev: network interface device structure
3910 *
3911 * The set_rx_method entry point is called whenever the unicast/multicast
3912 * address list or the network interface flags are updated. This routine is
3913 * responsible for configuring the hardware for proper unicast, multicast and
3914 * promiscuous mode.
3915 **/
3916 void ixgbe_set_rx_mode(struct net_device *netdev)
3917 {
3918 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3919 struct ixgbe_hw *hw = &adapter->hw;
3920 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3921 u32 vlnctrl;
3922 int count;
3923
3924 /* Check for Promiscuous and All Multicast modes */
3925 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3926 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3927
3928 /* set all bits that we expect to always be set */
3929 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3930 fctrl |= IXGBE_FCTRL_BAM;
3931 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3932 fctrl |= IXGBE_FCTRL_PMCF;
3933
3934 /* clear the bits we are changing the status of */
3935 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3936 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3937 if (netdev->flags & IFF_PROMISC) {
3938 hw->addr_ctrl.user_set_promisc = true;
3939 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3940 vmolr |= IXGBE_VMOLR_MPE;
3941 /* Only disable hardware filter vlans in promiscuous mode
3942 * if SR-IOV and VMDQ are disabled - otherwise ensure
3943 * that hardware VLAN filters remain enabled.
3944 */
3945 if (!(adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
3946 IXGBE_FLAG_SRIOV_ENABLED)))
3947 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3948 } else {
3949 if (netdev->flags & IFF_ALLMULTI) {
3950 fctrl |= IXGBE_FCTRL_MPE;
3951 vmolr |= IXGBE_VMOLR_MPE;
3952 }
3953 vlnctrl |= IXGBE_VLNCTRL_VFE;
3954 hw->addr_ctrl.user_set_promisc = false;
3955 }
3956
3957 /*
3958 * Write addresses to available RAR registers, if there is not
3959 * sufficient space to store all the addresses then enable
3960 * unicast promiscuous mode
3961 */
3962 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0));
3963 if (count < 0) {
3964 fctrl |= IXGBE_FCTRL_UPE;
3965 vmolr |= IXGBE_VMOLR_ROPE;
3966 }
3967
3968 /* Write addresses to the MTA, if the attempt fails
3969 * then we should just turn on promiscuous mode so
3970 * that we can at least receive multicast traffic
3971 */
3972 count = ixgbe_write_mc_addr_list(netdev);
3973 if (count < 0) {
3974 fctrl |= IXGBE_FCTRL_MPE;
3975 vmolr |= IXGBE_VMOLR_MPE;
3976 } else if (count) {
3977 vmolr |= IXGBE_VMOLR_ROMPE;
3978 }
3979
3980 if (hw->mac.type != ixgbe_mac_82598EB) {
3981 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
3982 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3983 IXGBE_VMOLR_ROPE);
3984 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
3985 }
3986
3987 /* This is useful for sniffing bad packets. */
3988 if (adapter->netdev->features & NETIF_F_RXALL) {
3989 /* UPE and MPE will be handled by normal PROMISC logic
3990 * in e1000e_set_rx_mode */
3991 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3992 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3993 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3994
3995 fctrl &= ~(IXGBE_FCTRL_DPF);
3996 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3997 }
3998
3999 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4000 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4001
4002 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
4003 ixgbe_vlan_strip_enable(adapter);
4004 else
4005 ixgbe_vlan_strip_disable(adapter);
4006 }
4007
4008 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4009 {
4010 int q_idx;
4011
4012 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4013 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
4014 napi_enable(&adapter->q_vector[q_idx]->napi);
4015 }
4016 }
4017
4018 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4019 {
4020 int q_idx;
4021
4022 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4023 napi_disable(&adapter->q_vector[q_idx]->napi);
4024 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
4025 pr_info("QV %d locked\n", q_idx);
4026 usleep_range(1000, 20000);
4027 }
4028 }
4029 }
4030
4031 #ifdef CONFIG_IXGBE_DCB
4032 /**
4033 * ixgbe_configure_dcb - Configure DCB hardware
4034 * @adapter: ixgbe adapter struct
4035 *
4036 * This is called by the driver on open to configure the DCB hardware.
4037 * This is also called by the gennetlink interface when reconfiguring
4038 * the DCB state.
4039 */
4040 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4041 {
4042 struct ixgbe_hw *hw = &adapter->hw;
4043 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4044
4045 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4046 if (hw->mac.type == ixgbe_mac_82598EB)
4047 netif_set_gso_max_size(adapter->netdev, 65536);
4048 return;
4049 }
4050
4051 if (hw->mac.type == ixgbe_mac_82598EB)
4052 netif_set_gso_max_size(adapter->netdev, 32768);
4053
4054 #ifdef IXGBE_FCOE
4055 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4056 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
4057 #endif
4058
4059 /* reconfigure the hardware */
4060 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
4061 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4062 DCB_TX_CONFIG);
4063 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4064 DCB_RX_CONFIG);
4065 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
4066 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4067 ixgbe_dcb_hw_ets(&adapter->hw,
4068 adapter->ixgbe_ieee_ets,
4069 max_frame);
4070 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4071 adapter->ixgbe_ieee_pfc->pfc_en,
4072 adapter->ixgbe_ieee_ets->prio_tc);
4073 }
4074
4075 /* Enable RSS Hash per TC */
4076 if (hw->mac.type != ixgbe_mac_82598EB) {
4077 u32 msb = 0;
4078 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
4079
4080 while (rss_i) {
4081 msb++;
4082 rss_i >>= 1;
4083 }
4084
4085 /* write msb to all 8 TCs in one write */
4086 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
4087 }
4088 }
4089 #endif
4090
4091 /* Additional bittime to account for IXGBE framing */
4092 #define IXGBE_ETH_FRAMING 20
4093
4094 /**
4095 * ixgbe_hpbthresh - calculate high water mark for flow control
4096 *
4097 * @adapter: board private structure to calculate for
4098 * @pb: packet buffer to calculate
4099 */
4100 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4101 {
4102 struct ixgbe_hw *hw = &adapter->hw;
4103 struct net_device *dev = adapter->netdev;
4104 int link, tc, kb, marker;
4105 u32 dv_id, rx_pba;
4106
4107 /* Calculate max LAN frame size */
4108 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4109
4110 #ifdef IXGBE_FCOE
4111 /* FCoE traffic class uses FCOE jumbo frames */
4112 if ((dev->features & NETIF_F_FCOE_MTU) &&
4113 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4114 (pb == ixgbe_fcoe_get_tc(adapter)))
4115 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4116 #endif
4117
4118 /* Calculate delay value for device */
4119 switch (hw->mac.type) {
4120 case ixgbe_mac_X540:
4121 dv_id = IXGBE_DV_X540(link, tc);
4122 break;
4123 default:
4124 dv_id = IXGBE_DV(link, tc);
4125 break;
4126 }
4127
4128 /* Loopback switch introduces additional latency */
4129 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4130 dv_id += IXGBE_B2BT(tc);
4131
4132 /* Delay value is calculated in bit times convert to KB */
4133 kb = IXGBE_BT2KB(dv_id);
4134 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4135
4136 marker = rx_pba - kb;
4137
4138 /* It is possible that the packet buffer is not large enough
4139 * to provide required headroom. In this case throw an error
4140 * to user and a do the best we can.
4141 */
4142 if (marker < 0) {
4143 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4144 "headroom to support flow control."
4145 "Decrease MTU or number of traffic classes\n", pb);
4146 marker = tc + 1;
4147 }
4148
4149 return marker;
4150 }
4151
4152 /**
4153 * ixgbe_lpbthresh - calculate low water mark for for flow control
4154 *
4155 * @adapter: board private structure to calculate for
4156 * @pb: packet buffer to calculate
4157 */
4158 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
4159 {
4160 struct ixgbe_hw *hw = &adapter->hw;
4161 struct net_device *dev = adapter->netdev;
4162 int tc;
4163 u32 dv_id;
4164
4165 /* Calculate max LAN frame size */
4166 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4167
4168 #ifdef IXGBE_FCOE
4169 /* FCoE traffic class uses FCOE jumbo frames */
4170 if ((dev->features & NETIF_F_FCOE_MTU) &&
4171 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4172 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4173 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4174 #endif
4175
4176 /* Calculate delay value for device */
4177 switch (hw->mac.type) {
4178 case ixgbe_mac_X540:
4179 dv_id = IXGBE_LOW_DV_X540(tc);
4180 break;
4181 default:
4182 dv_id = IXGBE_LOW_DV(tc);
4183 break;
4184 }
4185
4186 /* Delay value is calculated in bit times convert to KB */
4187 return IXGBE_BT2KB(dv_id);
4188 }
4189
4190 /*
4191 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4192 */
4193 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4194 {
4195 struct ixgbe_hw *hw = &adapter->hw;
4196 int num_tc = netdev_get_num_tc(adapter->netdev);
4197 int i;
4198
4199 if (!num_tc)
4200 num_tc = 1;
4201
4202 for (i = 0; i < num_tc; i++) {
4203 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4204 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
4205
4206 /* Low water marks must not be larger than high water marks */
4207 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4208 hw->fc.low_water[i] = 0;
4209 }
4210
4211 for (; i < MAX_TRAFFIC_CLASS; i++)
4212 hw->fc.high_water[i] = 0;
4213 }
4214
4215 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4216 {
4217 struct ixgbe_hw *hw = &adapter->hw;
4218 int hdrm;
4219 u8 tc = netdev_get_num_tc(adapter->netdev);
4220
4221 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4222 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4223 hdrm = 32 << adapter->fdir_pballoc;
4224 else
4225 hdrm = 0;
4226
4227 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
4228 ixgbe_pbthresh_setup(adapter);
4229 }
4230
4231 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4232 {
4233 struct ixgbe_hw *hw = &adapter->hw;
4234 struct hlist_node *node2;
4235 struct ixgbe_fdir_filter *filter;
4236
4237 spin_lock(&adapter->fdir_perfect_lock);
4238
4239 if (!hlist_empty(&adapter->fdir_filter_list))
4240 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4241
4242 hlist_for_each_entry_safe(filter, node2,
4243 &adapter->fdir_filter_list, fdir_node) {
4244 ixgbe_fdir_write_perfect_filter_82599(hw,
4245 &filter->filter,
4246 filter->sw_idx,
4247 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4248 IXGBE_FDIR_DROP_QUEUE :
4249 adapter->rx_ring[filter->action]->reg_idx);
4250 }
4251
4252 spin_unlock(&adapter->fdir_perfect_lock);
4253 }
4254
4255 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4256 struct ixgbe_adapter *adapter)
4257 {
4258 struct ixgbe_hw *hw = &adapter->hw;
4259 u32 vmolr;
4260
4261 /* No unicast promiscuous support for VMDQ devices. */
4262 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4263 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4264
4265 /* clear the affected bit */
4266 vmolr &= ~IXGBE_VMOLR_MPE;
4267
4268 if (dev->flags & IFF_ALLMULTI) {
4269 vmolr |= IXGBE_VMOLR_MPE;
4270 } else {
4271 vmolr |= IXGBE_VMOLR_ROMPE;
4272 hw->mac.ops.update_mc_addr_list(hw, dev);
4273 }
4274 ixgbe_write_uc_addr_list(adapter->netdev, pool);
4275 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4276 }
4277
4278 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4279 {
4280 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4281 int rss_i = adapter->num_rx_queues_per_pool;
4282 struct ixgbe_hw *hw = &adapter->hw;
4283 u16 pool = vadapter->pool;
4284 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4285 IXGBE_PSRTYPE_UDPHDR |
4286 IXGBE_PSRTYPE_IPV4HDR |
4287 IXGBE_PSRTYPE_L2HDR |
4288 IXGBE_PSRTYPE_IPV6HDR;
4289
4290 if (hw->mac.type == ixgbe_mac_82598EB)
4291 return;
4292
4293 if (rss_i > 3)
4294 psrtype |= 2 << 29;
4295 else if (rss_i > 1)
4296 psrtype |= 1 << 29;
4297
4298 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4299 }
4300
4301 /**
4302 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4303 * @rx_ring: ring to free buffers from
4304 **/
4305 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4306 {
4307 struct device *dev = rx_ring->dev;
4308 unsigned long size;
4309 u16 i;
4310
4311 /* ring already cleared, nothing to do */
4312 if (!rx_ring->rx_buffer_info)
4313 return;
4314
4315 /* Free all the Rx ring sk_buffs */
4316 for (i = 0; i < rx_ring->count; i++) {
4317 struct ixgbe_rx_buffer *rx_buffer;
4318
4319 rx_buffer = &rx_ring->rx_buffer_info[i];
4320 if (rx_buffer->skb) {
4321 struct sk_buff *skb = rx_buffer->skb;
4322 if (IXGBE_CB(skb)->page_released) {
4323 dma_unmap_page(dev,
4324 IXGBE_CB(skb)->dma,
4325 ixgbe_rx_bufsz(rx_ring),
4326 DMA_FROM_DEVICE);
4327 IXGBE_CB(skb)->page_released = false;
4328 }
4329 dev_kfree_skb(skb);
4330 }
4331 rx_buffer->skb = NULL;
4332 if (rx_buffer->dma)
4333 dma_unmap_page(dev, rx_buffer->dma,
4334 ixgbe_rx_pg_size(rx_ring),
4335 DMA_FROM_DEVICE);
4336 rx_buffer->dma = 0;
4337 if (rx_buffer->page)
4338 __free_pages(rx_buffer->page,
4339 ixgbe_rx_pg_order(rx_ring));
4340 rx_buffer->page = NULL;
4341 }
4342
4343 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4344 memset(rx_ring->rx_buffer_info, 0, size);
4345
4346 /* Zero out the descriptor ring */
4347 memset(rx_ring->desc, 0, rx_ring->size);
4348
4349 rx_ring->next_to_alloc = 0;
4350 rx_ring->next_to_clean = 0;
4351 rx_ring->next_to_use = 0;
4352 }
4353
4354 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4355 struct ixgbe_ring *rx_ring)
4356 {
4357 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4358 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4359
4360 /* shutdown specific queue receive and wait for dma to settle */
4361 ixgbe_disable_rx_queue(adapter, rx_ring);
4362 usleep_range(10000, 20000);
4363 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4364 ixgbe_clean_rx_ring(rx_ring);
4365 rx_ring->l2_accel_priv = NULL;
4366 }
4367
4368 static int ixgbe_fwd_ring_down(struct net_device *vdev,
4369 struct ixgbe_fwd_adapter *accel)
4370 {
4371 struct ixgbe_adapter *adapter = accel->real_adapter;
4372 unsigned int rxbase = accel->rx_base_queue;
4373 unsigned int txbase = accel->tx_base_queue;
4374 int i;
4375
4376 netif_tx_stop_all_queues(vdev);
4377
4378 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4379 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4380 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4381 }
4382
4383 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4384 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4385 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4386 }
4387
4388
4389 return 0;
4390 }
4391
4392 static int ixgbe_fwd_ring_up(struct net_device *vdev,
4393 struct ixgbe_fwd_adapter *accel)
4394 {
4395 struct ixgbe_adapter *adapter = accel->real_adapter;
4396 unsigned int rxbase, txbase, queues;
4397 int i, baseq, err = 0;
4398
4399 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4400 return 0;
4401
4402 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4403 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4404 accel->pool, adapter->num_rx_pools,
4405 baseq, baseq + adapter->num_rx_queues_per_pool,
4406 adapter->fwd_bitmask);
4407
4408 accel->netdev = vdev;
4409 accel->rx_base_queue = rxbase = baseq;
4410 accel->tx_base_queue = txbase = baseq;
4411
4412 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4413 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4414
4415 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4416 adapter->rx_ring[rxbase + i]->netdev = vdev;
4417 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4418 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4419 }
4420
4421 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4422 adapter->tx_ring[txbase + i]->netdev = vdev;
4423 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4424 }
4425
4426 queues = min_t(unsigned int,
4427 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4428 err = netif_set_real_num_tx_queues(vdev, queues);
4429 if (err)
4430 goto fwd_queue_err;
4431
4432 err = netif_set_real_num_rx_queues(vdev, queues);
4433 if (err)
4434 goto fwd_queue_err;
4435
4436 if (is_valid_ether_addr(vdev->dev_addr))
4437 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4438
4439 ixgbe_fwd_psrtype(accel);
4440 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4441 return err;
4442 fwd_queue_err:
4443 ixgbe_fwd_ring_down(vdev, accel);
4444 return err;
4445 }
4446
4447 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4448 {
4449 struct net_device *upper;
4450 struct list_head *iter;
4451 int err;
4452
4453 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4454 if (netif_is_macvlan(upper)) {
4455 struct macvlan_dev *dfwd = netdev_priv(upper);
4456 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4457
4458 if (dfwd->fwd_priv) {
4459 err = ixgbe_fwd_ring_up(upper, vadapter);
4460 if (err)
4461 continue;
4462 }
4463 }
4464 }
4465 }
4466
4467 static void ixgbe_configure(struct ixgbe_adapter *adapter)
4468 {
4469 struct ixgbe_hw *hw = &adapter->hw;
4470
4471 ixgbe_configure_pb(adapter);
4472 #ifdef CONFIG_IXGBE_DCB
4473 ixgbe_configure_dcb(adapter);
4474 #endif
4475 /*
4476 * We must restore virtualization before VLANs or else
4477 * the VLVF registers will not be populated
4478 */
4479 ixgbe_configure_virtualization(adapter);
4480
4481 ixgbe_set_rx_mode(adapter->netdev);
4482 ixgbe_restore_vlan(adapter);
4483
4484 switch (hw->mac.type) {
4485 case ixgbe_mac_82599EB:
4486 case ixgbe_mac_X540:
4487 hw->mac.ops.disable_rx_buff(hw);
4488 break;
4489 default:
4490 break;
4491 }
4492
4493 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4494 ixgbe_init_fdir_signature_82599(&adapter->hw,
4495 adapter->fdir_pballoc);
4496 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4497 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4498 adapter->fdir_pballoc);
4499 ixgbe_fdir_filter_restore(adapter);
4500 }
4501
4502 switch (hw->mac.type) {
4503 case ixgbe_mac_82599EB:
4504 case ixgbe_mac_X540:
4505 hw->mac.ops.enable_rx_buff(hw);
4506 break;
4507 default:
4508 break;
4509 }
4510
4511 #ifdef IXGBE_FCOE
4512 /* configure FCoE L2 filters, redirection table, and Rx control */
4513 ixgbe_configure_fcoe(adapter);
4514
4515 #endif /* IXGBE_FCOE */
4516 ixgbe_configure_tx(adapter);
4517 ixgbe_configure_rx(adapter);
4518 ixgbe_configure_dfwd(adapter);
4519 }
4520
4521 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4522 {
4523 switch (hw->phy.type) {
4524 case ixgbe_phy_sfp_avago:
4525 case ixgbe_phy_sfp_ftl:
4526 case ixgbe_phy_sfp_intel:
4527 case ixgbe_phy_sfp_unknown:
4528 case ixgbe_phy_sfp_passive_tyco:
4529 case ixgbe_phy_sfp_passive_unknown:
4530 case ixgbe_phy_sfp_active_unknown:
4531 case ixgbe_phy_sfp_ftl_active:
4532 case ixgbe_phy_qsfp_passive_unknown:
4533 case ixgbe_phy_qsfp_active_unknown:
4534 case ixgbe_phy_qsfp_intel:
4535 case ixgbe_phy_qsfp_unknown:
4536 /* ixgbe_phy_none is set when no SFP module is present */
4537 case ixgbe_phy_none:
4538 return true;
4539 case ixgbe_phy_nl:
4540 if (hw->mac.type == ixgbe_mac_82598EB)
4541 return true;
4542 default:
4543 return false;
4544 }
4545 }
4546
4547 /**
4548 * ixgbe_sfp_link_config - set up SFP+ link
4549 * @adapter: pointer to private adapter struct
4550 **/
4551 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4552 {
4553 /*
4554 * We are assuming the worst case scenario here, and that
4555 * is that an SFP was inserted/removed after the reset
4556 * but before SFP detection was enabled. As such the best
4557 * solution is to just start searching as soon as we start
4558 */
4559 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4560 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4561
4562 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4563 }
4564
4565 /**
4566 * ixgbe_non_sfp_link_config - set up non-SFP+ link
4567 * @hw: pointer to private hardware struct
4568 *
4569 * Returns 0 on success, negative on failure
4570 **/
4571 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4572 {
4573 u32 speed;
4574 bool autoneg, link_up = false;
4575 u32 ret = IXGBE_ERR_LINK_SETUP;
4576
4577 if (hw->mac.ops.check_link)
4578 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
4579
4580 if (ret)
4581 return ret;
4582
4583 speed = hw->phy.autoneg_advertised;
4584 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4585 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4586 &autoneg);
4587 if (ret)
4588 return ret;
4589
4590 if (hw->mac.ops.setup_link)
4591 ret = hw->mac.ops.setup_link(hw, speed, link_up);
4592
4593 return ret;
4594 }
4595
4596 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4597 {
4598 struct ixgbe_hw *hw = &adapter->hw;
4599 u32 gpie = 0;
4600
4601 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4602 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4603 IXGBE_GPIE_OCD;
4604 gpie |= IXGBE_GPIE_EIAME;
4605 /*
4606 * use EIAM to auto-mask when MSI-X interrupt is asserted
4607 * this saves a register write for every interrupt
4608 */
4609 switch (hw->mac.type) {
4610 case ixgbe_mac_82598EB:
4611 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4612 break;
4613 case ixgbe_mac_82599EB:
4614 case ixgbe_mac_X540:
4615 default:
4616 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4617 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4618 break;
4619 }
4620 } else {
4621 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4622 * specifically only auto mask tx and rx interrupts */
4623 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4624 }
4625
4626 /* XXX: to interrupt immediately for EICS writes, enable this */
4627 /* gpie |= IXGBE_GPIE_EIMEN; */
4628
4629 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4630 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4631
4632 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4633 case IXGBE_82599_VMDQ_8Q_MASK:
4634 gpie |= IXGBE_GPIE_VTMODE_16;
4635 break;
4636 case IXGBE_82599_VMDQ_4Q_MASK:
4637 gpie |= IXGBE_GPIE_VTMODE_32;
4638 break;
4639 default:
4640 gpie |= IXGBE_GPIE_VTMODE_64;
4641 break;
4642 }
4643 }
4644
4645 /* Enable Thermal over heat sensor interrupt */
4646 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4647 switch (adapter->hw.mac.type) {
4648 case ixgbe_mac_82599EB:
4649 gpie |= IXGBE_SDP0_GPIEN;
4650 break;
4651 case ixgbe_mac_X540:
4652 gpie |= IXGBE_EIMS_TS;
4653 break;
4654 default:
4655 break;
4656 }
4657 }
4658
4659 /* Enable fan failure interrupt */
4660 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4661 gpie |= IXGBE_SDP1_GPIEN;
4662
4663 if (hw->mac.type == ixgbe_mac_82599EB) {
4664 gpie |= IXGBE_SDP1_GPIEN;
4665 gpie |= IXGBE_SDP2_GPIEN;
4666 }
4667
4668 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4669 }
4670
4671 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4672 {
4673 struct ixgbe_hw *hw = &adapter->hw;
4674 int err;
4675 u32 ctrl_ext;
4676
4677 ixgbe_get_hw_control(adapter);
4678 ixgbe_setup_gpie(adapter);
4679
4680 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4681 ixgbe_configure_msix(adapter);
4682 else
4683 ixgbe_configure_msi_and_legacy(adapter);
4684
4685 /* enable the optics for 82599 SFP+ fiber */
4686 if (hw->mac.ops.enable_tx_laser)
4687 hw->mac.ops.enable_tx_laser(hw);
4688
4689 smp_mb__before_atomic();
4690 clear_bit(__IXGBE_DOWN, &adapter->state);
4691 ixgbe_napi_enable_all(adapter);
4692
4693 if (ixgbe_is_sfp(hw)) {
4694 ixgbe_sfp_link_config(adapter);
4695 } else {
4696 err = ixgbe_non_sfp_link_config(hw);
4697 if (err)
4698 e_err(probe, "link_config FAILED %d\n", err);
4699 }
4700
4701 /* clear any pending interrupts, may auto mask */
4702 IXGBE_READ_REG(hw, IXGBE_EICR);
4703 ixgbe_irq_enable(adapter, true, true);
4704
4705 /*
4706 * If this adapter has a fan, check to see if we had a failure
4707 * before we enabled the interrupt.
4708 */
4709 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4710 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4711 if (esdp & IXGBE_ESDP_SDP1)
4712 e_crit(drv, "Fan has stopped, replace the adapter\n");
4713 }
4714
4715 /* bring the link up in the watchdog, this could race with our first
4716 * link up interrupt but shouldn't be a problem */
4717 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4718 adapter->link_check_timeout = jiffies;
4719 mod_timer(&adapter->service_timer, jiffies);
4720
4721 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4722 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4723 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4724 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4725 }
4726
4727 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4728 {
4729 WARN_ON(in_interrupt());
4730 /* put off any impending NetWatchDogTimeout */
4731 adapter->netdev->trans_start = jiffies;
4732
4733 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4734 usleep_range(1000, 2000);
4735 ixgbe_down(adapter);
4736 /*
4737 * If SR-IOV enabled then wait a bit before bringing the adapter
4738 * back up to give the VFs time to respond to the reset. The
4739 * two second wait is based upon the watchdog timer cycle in
4740 * the VF driver.
4741 */
4742 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4743 msleep(2000);
4744 ixgbe_up(adapter);
4745 clear_bit(__IXGBE_RESETTING, &adapter->state);
4746 }
4747
4748 void ixgbe_up(struct ixgbe_adapter *adapter)
4749 {
4750 /* hardware has been reset, we need to reload some things */
4751 ixgbe_configure(adapter);
4752
4753 ixgbe_up_complete(adapter);
4754 }
4755
4756 void ixgbe_reset(struct ixgbe_adapter *adapter)
4757 {
4758 struct ixgbe_hw *hw = &adapter->hw;
4759 struct net_device *netdev = adapter->netdev;
4760 int err;
4761 u8 old_addr[ETH_ALEN];
4762
4763 if (ixgbe_removed(hw->hw_addr))
4764 return;
4765 /* lock SFP init bit to prevent race conditions with the watchdog */
4766 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4767 usleep_range(1000, 2000);
4768
4769 /* clear all SFP and link config related flags while holding SFP_INIT */
4770 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4771 IXGBE_FLAG2_SFP_NEEDS_RESET);
4772 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4773
4774 err = hw->mac.ops.init_hw(hw);
4775 switch (err) {
4776 case 0:
4777 case IXGBE_ERR_SFP_NOT_PRESENT:
4778 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4779 break;
4780 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4781 e_dev_err("master disable timed out\n");
4782 break;
4783 case IXGBE_ERR_EEPROM_VERSION:
4784 /* We are running on a pre-production device, log a warning */
4785 e_dev_warn("This device is a pre-production adapter/LOM. "
4786 "Please be aware there may be issues associated with "
4787 "your hardware. If you are experiencing problems "
4788 "please contact your Intel or hardware "
4789 "representative who provided you with this "
4790 "hardware.\n");
4791 break;
4792 default:
4793 e_dev_err("Hardware Error: %d\n", err);
4794 }
4795
4796 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4797 /* do not flush user set addresses */
4798 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len);
4799 ixgbe_flush_sw_mac_table(adapter);
4800 ixgbe_mac_set_default_filter(adapter, old_addr);
4801
4802 /* update SAN MAC vmdq pool selection */
4803 if (hw->mac.san_mac_rar_index)
4804 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4805
4806 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
4807 ixgbe_ptp_reset(adapter);
4808 }
4809
4810 /**
4811 * ixgbe_clean_tx_ring - Free Tx Buffers
4812 * @tx_ring: ring to be cleaned
4813 **/
4814 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4815 {
4816 struct ixgbe_tx_buffer *tx_buffer_info;
4817 unsigned long size;
4818 u16 i;
4819
4820 /* ring already cleared, nothing to do */
4821 if (!tx_ring->tx_buffer_info)
4822 return;
4823
4824 /* Free all the Tx ring sk_buffs */
4825 for (i = 0; i < tx_ring->count; i++) {
4826 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4827 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4828 }
4829
4830 netdev_tx_reset_queue(txring_txq(tx_ring));
4831
4832 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4833 memset(tx_ring->tx_buffer_info, 0, size);
4834
4835 /* Zero out the descriptor ring */
4836 memset(tx_ring->desc, 0, tx_ring->size);
4837
4838 tx_ring->next_to_use = 0;
4839 tx_ring->next_to_clean = 0;
4840 }
4841
4842 /**
4843 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4844 * @adapter: board private structure
4845 **/
4846 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4847 {
4848 int i;
4849
4850 for (i = 0; i < adapter->num_rx_queues; i++)
4851 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4852 }
4853
4854 /**
4855 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4856 * @adapter: board private structure
4857 **/
4858 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4859 {
4860 int i;
4861
4862 for (i = 0; i < adapter->num_tx_queues; i++)
4863 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4864 }
4865
4866 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4867 {
4868 struct hlist_node *node2;
4869 struct ixgbe_fdir_filter *filter;
4870
4871 spin_lock(&adapter->fdir_perfect_lock);
4872
4873 hlist_for_each_entry_safe(filter, node2,
4874 &adapter->fdir_filter_list, fdir_node) {
4875 hlist_del(&filter->fdir_node);
4876 kfree(filter);
4877 }
4878 adapter->fdir_filter_count = 0;
4879
4880 spin_unlock(&adapter->fdir_perfect_lock);
4881 }
4882
4883 void ixgbe_down(struct ixgbe_adapter *adapter)
4884 {
4885 struct net_device *netdev = adapter->netdev;
4886 struct ixgbe_hw *hw = &adapter->hw;
4887 struct net_device *upper;
4888 struct list_head *iter;
4889 u32 rxctrl;
4890 int i;
4891
4892 /* signal that we are down to the interrupt handler */
4893 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
4894 return; /* do nothing if already down */
4895
4896 /* disable receives */
4897 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4898 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4899
4900 /* disable all enabled rx queues */
4901 for (i = 0; i < adapter->num_rx_queues; i++)
4902 /* this call also flushes the previous write */
4903 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4904
4905 usleep_range(10000, 20000);
4906
4907 netif_tx_stop_all_queues(netdev);
4908
4909 /* call carrier off first to avoid false dev_watchdog timeouts */
4910 netif_carrier_off(netdev);
4911 netif_tx_disable(netdev);
4912
4913 /* disable any upper devices */
4914 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4915 if (netif_is_macvlan(upper)) {
4916 struct macvlan_dev *vlan = netdev_priv(upper);
4917
4918 if (vlan->fwd_priv) {
4919 netif_tx_stop_all_queues(upper);
4920 netif_carrier_off(upper);
4921 netif_tx_disable(upper);
4922 }
4923 }
4924 }
4925
4926 ixgbe_irq_disable(adapter);
4927
4928 ixgbe_napi_disable_all(adapter);
4929
4930 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4931 IXGBE_FLAG2_RESET_REQUESTED);
4932 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4933
4934 del_timer_sync(&adapter->service_timer);
4935
4936 if (adapter->num_vfs) {
4937 /* Clear EITR Select mapping */
4938 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4939
4940 /* Mark all the VFs as inactive */
4941 for (i = 0 ; i < adapter->num_vfs; i++)
4942 adapter->vfinfo[i].clear_to_send = false;
4943
4944 /* ping all the active vfs to let them know we are going down */
4945 ixgbe_ping_all_vfs(adapter);
4946
4947 /* Disable all VFTE/VFRE TX/RX */
4948 ixgbe_disable_tx_rx(adapter);
4949 }
4950
4951 /* disable transmits in the hardware now that interrupts are off */
4952 for (i = 0; i < adapter->num_tx_queues; i++) {
4953 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4954 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4955 }
4956
4957 /* Disable the Tx DMA engine on 82599 and X540 */
4958 switch (hw->mac.type) {
4959 case ixgbe_mac_82599EB:
4960 case ixgbe_mac_X540:
4961 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4962 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4963 ~IXGBE_DMATXCTL_TE));
4964 break;
4965 default:
4966 break;
4967 }
4968
4969 if (!pci_channel_offline(adapter->pdev))
4970 ixgbe_reset(adapter);
4971
4972 /* power down the optics for 82599 SFP+ fiber */
4973 if (hw->mac.ops.disable_tx_laser)
4974 hw->mac.ops.disable_tx_laser(hw);
4975
4976 ixgbe_clean_all_tx_rings(adapter);
4977 ixgbe_clean_all_rx_rings(adapter);
4978
4979 #ifdef CONFIG_IXGBE_DCA
4980 /* since we reset the hardware DCA settings were cleared */
4981 ixgbe_setup_dca(adapter);
4982 #endif
4983 }
4984
4985 /**
4986 * ixgbe_tx_timeout - Respond to a Tx Hang
4987 * @netdev: network interface device structure
4988 **/
4989 static void ixgbe_tx_timeout(struct net_device *netdev)
4990 {
4991 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4992
4993 /* Do the reset outside of interrupt context */
4994 ixgbe_tx_timeout_reset(adapter);
4995 }
4996
4997 /**
4998 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4999 * @adapter: board private structure to initialize
5000 *
5001 * ixgbe_sw_init initializes the Adapter private data structure.
5002 * Fields are initialized based on PCI device information and
5003 * OS network device settings (MTU size).
5004 **/
5005 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
5006 {
5007 struct ixgbe_hw *hw = &adapter->hw;
5008 struct pci_dev *pdev = adapter->pdev;
5009 unsigned int rss, fdir;
5010 u32 fwsm;
5011 #ifdef CONFIG_IXGBE_DCB
5012 int j;
5013 struct tc_configuration *tc;
5014 #endif
5015
5016 /* PCI config space info */
5017
5018 hw->vendor_id = pdev->vendor;
5019 hw->device_id = pdev->device;
5020 hw->revision_id = pdev->revision;
5021 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5022 hw->subsystem_device_id = pdev->subsystem_device;
5023
5024 /* Set common capability flags and settings */
5025 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
5026 adapter->ring_feature[RING_F_RSS].limit = rss;
5027 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5028 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5029 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5030 adapter->atr_sample_rate = 20;
5031 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5032 adapter->ring_feature[RING_F_FDIR].limit = fdir;
5033 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5034 #ifdef CONFIG_IXGBE_DCA
5035 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5036 #endif
5037 #ifdef IXGBE_FCOE
5038 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5039 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5040 #ifdef CONFIG_IXGBE_DCB
5041 /* Default traffic class to use for FCoE */
5042 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5043 #endif /* CONFIG_IXGBE_DCB */
5044 #endif /* IXGBE_FCOE */
5045
5046 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5047 hw->mac.num_rar_entries,
5048 GFP_ATOMIC);
5049
5050 /* Set MAC specific capability flags and exceptions */
5051 switch (hw->mac.type) {
5052 case ixgbe_mac_82598EB:
5053 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5054 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5055
5056 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5057 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5058
5059 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
5060 adapter->ring_feature[RING_F_FDIR].limit = 0;
5061 adapter->atr_sample_rate = 0;
5062 adapter->fdir_pballoc = 0;
5063 #ifdef IXGBE_FCOE
5064 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5065 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5066 #ifdef CONFIG_IXGBE_DCB
5067 adapter->fcoe.up = 0;
5068 #endif /* IXGBE_DCB */
5069 #endif /* IXGBE_FCOE */
5070 break;
5071 case ixgbe_mac_82599EB:
5072 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5073 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5074 break;
5075 case ixgbe_mac_X540:
5076 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
5077 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5078 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5079 break;
5080 default:
5081 break;
5082 }
5083
5084 #ifdef IXGBE_FCOE
5085 /* FCoE support exists, always init the FCoE lock */
5086 spin_lock_init(&adapter->fcoe.lock);
5087
5088 #endif
5089 /* n-tuple support exists, always init our spinlock */
5090 spin_lock_init(&adapter->fdir_perfect_lock);
5091
5092 #ifdef CONFIG_IXGBE_DCB
5093 switch (hw->mac.type) {
5094 case ixgbe_mac_X540:
5095 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5096 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5097 break;
5098 default:
5099 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5100 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5101 break;
5102 }
5103
5104 /* Configure DCB traffic classes */
5105 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5106 tc = &adapter->dcb_cfg.tc_config[j];
5107 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5108 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5109 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5110 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5111 tc->dcb_pfc = pfc_disabled;
5112 }
5113
5114 /* Initialize default user to priority mapping, UPx->TC0 */
5115 tc = &adapter->dcb_cfg.tc_config[0];
5116 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5117 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5118
5119 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5120 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5121 adapter->dcb_cfg.pfc_mode_enable = false;
5122 adapter->dcb_set_bitmap = 0x00;
5123 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5124 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5125 sizeof(adapter->temp_dcb_cfg));
5126
5127 #endif
5128
5129 /* default flow control settings */
5130 hw->fc.requested_mode = ixgbe_fc_full;
5131 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5132 ixgbe_pbthresh_setup(adapter);
5133 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5134 hw->fc.send_xon = true;
5135 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
5136
5137 #ifdef CONFIG_PCI_IOV
5138 if (max_vfs > 0)
5139 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5140
5141 /* assign number of SR-IOV VFs */
5142 if (hw->mac.type != ixgbe_mac_82598EB) {
5143 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
5144 adapter->num_vfs = 0;
5145 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5146 } else {
5147 adapter->num_vfs = max_vfs;
5148 }
5149 }
5150 #endif /* CONFIG_PCI_IOV */
5151
5152 /* enable itr by default in dynamic mode */
5153 adapter->rx_itr_setting = 1;
5154 adapter->tx_itr_setting = 1;
5155
5156 /* set default ring sizes */
5157 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5158 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5159
5160 /* set default work limits */
5161 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5162
5163 /* initialize eeprom parameters */
5164 if (ixgbe_init_eeprom_params_generic(hw)) {
5165 e_dev_err("EEPROM initialization failed\n");
5166 return -EIO;
5167 }
5168
5169 /* PF holds first pool slot */
5170 set_bit(0, &adapter->fwd_bitmask);
5171 set_bit(__IXGBE_DOWN, &adapter->state);
5172
5173 return 0;
5174 }
5175
5176 /**
5177 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5178 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5179 *
5180 * Return 0 on success, negative on failure
5181 **/
5182 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5183 {
5184 struct device *dev = tx_ring->dev;
5185 int orig_node = dev_to_node(dev);
5186 int ring_node = -1;
5187 int size;
5188
5189 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5190
5191 if (tx_ring->q_vector)
5192 ring_node = tx_ring->q_vector->numa_node;
5193
5194 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
5195 if (!tx_ring->tx_buffer_info)
5196 tx_ring->tx_buffer_info = vzalloc(size);
5197 if (!tx_ring->tx_buffer_info)
5198 goto err;
5199
5200 u64_stats_init(&tx_ring->syncp);
5201
5202 /* round up to nearest 4K */
5203 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5204 tx_ring->size = ALIGN(tx_ring->size, 4096);
5205
5206 set_dev_node(dev, ring_node);
5207 tx_ring->desc = dma_alloc_coherent(dev,
5208 tx_ring->size,
5209 &tx_ring->dma,
5210 GFP_KERNEL);
5211 set_dev_node(dev, orig_node);
5212 if (!tx_ring->desc)
5213 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5214 &tx_ring->dma, GFP_KERNEL);
5215 if (!tx_ring->desc)
5216 goto err;
5217
5218 tx_ring->next_to_use = 0;
5219 tx_ring->next_to_clean = 0;
5220 return 0;
5221
5222 err:
5223 vfree(tx_ring->tx_buffer_info);
5224 tx_ring->tx_buffer_info = NULL;
5225 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5226 return -ENOMEM;
5227 }
5228
5229 /**
5230 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5231 * @adapter: board private structure
5232 *
5233 * If this function returns with an error, then it's possible one or
5234 * more of the rings is populated (while the rest are not). It is the
5235 * callers duty to clean those orphaned rings.
5236 *
5237 * Return 0 on success, negative on failure
5238 **/
5239 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5240 {
5241 int i, err = 0;
5242
5243 for (i = 0; i < adapter->num_tx_queues; i++) {
5244 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5245 if (!err)
5246 continue;
5247
5248 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5249 goto err_setup_tx;
5250 }
5251
5252 return 0;
5253 err_setup_tx:
5254 /* rewind the index freeing the rings as we go */
5255 while (i--)
5256 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5257 return err;
5258 }
5259
5260 /**
5261 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5262 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5263 *
5264 * Returns 0 on success, negative on failure
5265 **/
5266 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5267 {
5268 struct device *dev = rx_ring->dev;
5269 int orig_node = dev_to_node(dev);
5270 int ring_node = -1;
5271 int size;
5272
5273 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5274
5275 if (rx_ring->q_vector)
5276 ring_node = rx_ring->q_vector->numa_node;
5277
5278 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
5279 if (!rx_ring->rx_buffer_info)
5280 rx_ring->rx_buffer_info = vzalloc(size);
5281 if (!rx_ring->rx_buffer_info)
5282 goto err;
5283
5284 u64_stats_init(&rx_ring->syncp);
5285
5286 /* Round up to nearest 4K */
5287 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5288 rx_ring->size = ALIGN(rx_ring->size, 4096);
5289
5290 set_dev_node(dev, ring_node);
5291 rx_ring->desc = dma_alloc_coherent(dev,
5292 rx_ring->size,
5293 &rx_ring->dma,
5294 GFP_KERNEL);
5295 set_dev_node(dev, orig_node);
5296 if (!rx_ring->desc)
5297 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5298 &rx_ring->dma, GFP_KERNEL);
5299 if (!rx_ring->desc)
5300 goto err;
5301
5302 rx_ring->next_to_clean = 0;
5303 rx_ring->next_to_use = 0;
5304
5305 return 0;
5306 err:
5307 vfree(rx_ring->rx_buffer_info);
5308 rx_ring->rx_buffer_info = NULL;
5309 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5310 return -ENOMEM;
5311 }
5312
5313 /**
5314 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5315 * @adapter: board private structure
5316 *
5317 * If this function returns with an error, then it's possible one or
5318 * more of the rings is populated (while the rest are not). It is the
5319 * callers duty to clean those orphaned rings.
5320 *
5321 * Return 0 on success, negative on failure
5322 **/
5323 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5324 {
5325 int i, err = 0;
5326
5327 for (i = 0; i < adapter->num_rx_queues; i++) {
5328 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5329 if (!err)
5330 continue;
5331
5332 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5333 goto err_setup_rx;
5334 }
5335
5336 #ifdef IXGBE_FCOE
5337 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5338 if (!err)
5339 #endif
5340 return 0;
5341 err_setup_rx:
5342 /* rewind the index freeing the rings as we go */
5343 while (i--)
5344 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5345 return err;
5346 }
5347
5348 /**
5349 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5350 * @tx_ring: Tx descriptor ring for a specific queue
5351 *
5352 * Free all transmit software resources
5353 **/
5354 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5355 {
5356 ixgbe_clean_tx_ring(tx_ring);
5357
5358 vfree(tx_ring->tx_buffer_info);
5359 tx_ring->tx_buffer_info = NULL;
5360
5361 /* if not set, then don't free */
5362 if (!tx_ring->desc)
5363 return;
5364
5365 dma_free_coherent(tx_ring->dev, tx_ring->size,
5366 tx_ring->desc, tx_ring->dma);
5367
5368 tx_ring->desc = NULL;
5369 }
5370
5371 /**
5372 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5373 * @adapter: board private structure
5374 *
5375 * Free all transmit software resources
5376 **/
5377 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5378 {
5379 int i;
5380
5381 for (i = 0; i < adapter->num_tx_queues; i++)
5382 if (adapter->tx_ring[i]->desc)
5383 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5384 }
5385
5386 /**
5387 * ixgbe_free_rx_resources - Free Rx Resources
5388 * @rx_ring: ring to clean the resources from
5389 *
5390 * Free all receive software resources
5391 **/
5392 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5393 {
5394 ixgbe_clean_rx_ring(rx_ring);
5395
5396 vfree(rx_ring->rx_buffer_info);
5397 rx_ring->rx_buffer_info = NULL;
5398
5399 /* if not set, then don't free */
5400 if (!rx_ring->desc)
5401 return;
5402
5403 dma_free_coherent(rx_ring->dev, rx_ring->size,
5404 rx_ring->desc, rx_ring->dma);
5405
5406 rx_ring->desc = NULL;
5407 }
5408
5409 /**
5410 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5411 * @adapter: board private structure
5412 *
5413 * Free all receive software resources
5414 **/
5415 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5416 {
5417 int i;
5418
5419 #ifdef IXGBE_FCOE
5420 ixgbe_free_fcoe_ddp_resources(adapter);
5421
5422 #endif
5423 for (i = 0; i < adapter->num_rx_queues; i++)
5424 if (adapter->rx_ring[i]->desc)
5425 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5426 }
5427
5428 /**
5429 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5430 * @netdev: network interface device structure
5431 * @new_mtu: new value for maximum frame size
5432 *
5433 * Returns 0 on success, negative on failure
5434 **/
5435 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5436 {
5437 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5438 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5439
5440 /* MTU < 68 is an error and causes problems on some kernels */
5441 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5442 return -EINVAL;
5443
5444 /*
5445 * For 82599EB we cannot allow legacy VFs to enable their receive
5446 * paths when MTU greater than 1500 is configured. So display a
5447 * warning that legacy VFs will be disabled.
5448 */
5449 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5450 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
5451 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
5452 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
5453
5454 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5455
5456 /* must set new MTU before calling down or up */
5457 netdev->mtu = new_mtu;
5458
5459 if (netif_running(netdev))
5460 ixgbe_reinit_locked(adapter);
5461
5462 return 0;
5463 }
5464
5465 /**
5466 * ixgbe_open - Called when a network interface is made active
5467 * @netdev: network interface device structure
5468 *
5469 * Returns 0 on success, negative value on failure
5470 *
5471 * The open entry point is called when a network interface is made
5472 * active by the system (IFF_UP). At this point all resources needed
5473 * for transmit and receive operations are allocated, the interrupt
5474 * handler is registered with the OS, the watchdog timer is started,
5475 * and the stack is notified that the interface is ready.
5476 **/
5477 static int ixgbe_open(struct net_device *netdev)
5478 {
5479 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5480 int err, queues;
5481
5482 /* disallow open during test */
5483 if (test_bit(__IXGBE_TESTING, &adapter->state))
5484 return -EBUSY;
5485
5486 netif_carrier_off(netdev);
5487
5488 /* allocate transmit descriptors */
5489 err = ixgbe_setup_all_tx_resources(adapter);
5490 if (err)
5491 goto err_setup_tx;
5492
5493 /* allocate receive descriptors */
5494 err = ixgbe_setup_all_rx_resources(adapter);
5495 if (err)
5496 goto err_setup_rx;
5497
5498 ixgbe_configure(adapter);
5499
5500 err = ixgbe_request_irq(adapter);
5501 if (err)
5502 goto err_req_irq;
5503
5504 /* Notify the stack of the actual queue counts. */
5505 if (adapter->num_rx_pools > 1)
5506 queues = adapter->num_rx_queues_per_pool;
5507 else
5508 queues = adapter->num_tx_queues;
5509
5510 err = netif_set_real_num_tx_queues(netdev, queues);
5511 if (err)
5512 goto err_set_queues;
5513
5514 if (adapter->num_rx_pools > 1 &&
5515 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5516 queues = IXGBE_MAX_L2A_QUEUES;
5517 else
5518 queues = adapter->num_rx_queues;
5519 err = netif_set_real_num_rx_queues(netdev, queues);
5520 if (err)
5521 goto err_set_queues;
5522
5523 ixgbe_ptp_init(adapter);
5524
5525 ixgbe_up_complete(adapter);
5526
5527 return 0;
5528
5529 err_set_queues:
5530 ixgbe_free_irq(adapter);
5531 err_req_irq:
5532 ixgbe_free_all_rx_resources(adapter);
5533 err_setup_rx:
5534 ixgbe_free_all_tx_resources(adapter);
5535 err_setup_tx:
5536 ixgbe_reset(adapter);
5537
5538 return err;
5539 }
5540
5541 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5542 {
5543 ixgbe_ptp_suspend(adapter);
5544
5545 ixgbe_down(adapter);
5546 ixgbe_free_irq(adapter);
5547
5548 ixgbe_free_all_tx_resources(adapter);
5549 ixgbe_free_all_rx_resources(adapter);
5550 }
5551
5552 /**
5553 * ixgbe_close - Disables a network interface
5554 * @netdev: network interface device structure
5555 *
5556 * Returns 0, this is not allowed to fail
5557 *
5558 * The close entry point is called when an interface is de-activated
5559 * by the OS. The hardware is still under the drivers control, but
5560 * needs to be disabled. A global MAC reset is issued to stop the
5561 * hardware, and all transmit and receive resources are freed.
5562 **/
5563 static int ixgbe_close(struct net_device *netdev)
5564 {
5565 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5566
5567 ixgbe_ptp_stop(adapter);
5568
5569 ixgbe_close_suspend(adapter);
5570
5571 ixgbe_fdir_filter_exit(adapter);
5572
5573 ixgbe_release_hw_control(adapter);
5574
5575 return 0;
5576 }
5577
5578 #ifdef CONFIG_PM
5579 static int ixgbe_resume(struct pci_dev *pdev)
5580 {
5581 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5582 struct net_device *netdev = adapter->netdev;
5583 u32 err;
5584
5585 adapter->hw.hw_addr = adapter->io_addr;
5586 pci_set_power_state(pdev, PCI_D0);
5587 pci_restore_state(pdev);
5588 /*
5589 * pci_restore_state clears dev->state_saved so call
5590 * pci_save_state to restore it.
5591 */
5592 pci_save_state(pdev);
5593
5594 err = pci_enable_device_mem(pdev);
5595 if (err) {
5596 e_dev_err("Cannot enable PCI device from suspend\n");
5597 return err;
5598 }
5599 smp_mb__before_atomic();
5600 clear_bit(__IXGBE_DISABLED, &adapter->state);
5601 pci_set_master(pdev);
5602
5603 pci_wake_from_d3(pdev, false);
5604
5605 ixgbe_reset(adapter);
5606
5607 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5608
5609 rtnl_lock();
5610 err = ixgbe_init_interrupt_scheme(adapter);
5611 if (!err && netif_running(netdev))
5612 err = ixgbe_open(netdev);
5613
5614 rtnl_unlock();
5615
5616 if (err)
5617 return err;
5618
5619 netif_device_attach(netdev);
5620
5621 return 0;
5622 }
5623 #endif /* CONFIG_PM */
5624
5625 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5626 {
5627 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5628 struct net_device *netdev = adapter->netdev;
5629 struct ixgbe_hw *hw = &adapter->hw;
5630 u32 ctrl, fctrl;
5631 u32 wufc = adapter->wol;
5632 #ifdef CONFIG_PM
5633 int retval = 0;
5634 #endif
5635
5636 netif_device_detach(netdev);
5637
5638 rtnl_lock();
5639 if (netif_running(netdev))
5640 ixgbe_close_suspend(adapter);
5641 rtnl_unlock();
5642
5643 ixgbe_clear_interrupt_scheme(adapter);
5644
5645 #ifdef CONFIG_PM
5646 retval = pci_save_state(pdev);
5647 if (retval)
5648 return retval;
5649
5650 #endif
5651 if (hw->mac.ops.stop_link_on_d3)
5652 hw->mac.ops.stop_link_on_d3(hw);
5653
5654 if (wufc) {
5655 ixgbe_set_rx_mode(netdev);
5656
5657 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5658 if (hw->mac.ops.enable_tx_laser)
5659 hw->mac.ops.enable_tx_laser(hw);
5660
5661 /* turn on all-multi mode if wake on multicast is enabled */
5662 if (wufc & IXGBE_WUFC_MC) {
5663 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5664 fctrl |= IXGBE_FCTRL_MPE;
5665 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5666 }
5667
5668 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5669 ctrl |= IXGBE_CTRL_GIO_DIS;
5670 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5671
5672 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5673 } else {
5674 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5675 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5676 }
5677
5678 switch (hw->mac.type) {
5679 case ixgbe_mac_82598EB:
5680 pci_wake_from_d3(pdev, false);
5681 break;
5682 case ixgbe_mac_82599EB:
5683 case ixgbe_mac_X540:
5684 pci_wake_from_d3(pdev, !!wufc);
5685 break;
5686 default:
5687 break;
5688 }
5689
5690 *enable_wake = !!wufc;
5691
5692 ixgbe_release_hw_control(adapter);
5693
5694 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
5695 pci_disable_device(pdev);
5696
5697 return 0;
5698 }
5699
5700 #ifdef CONFIG_PM
5701 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5702 {
5703 int retval;
5704 bool wake;
5705
5706 retval = __ixgbe_shutdown(pdev, &wake);
5707 if (retval)
5708 return retval;
5709
5710 if (wake) {
5711 pci_prepare_to_sleep(pdev);
5712 } else {
5713 pci_wake_from_d3(pdev, false);
5714 pci_set_power_state(pdev, PCI_D3hot);
5715 }
5716
5717 return 0;
5718 }
5719 #endif /* CONFIG_PM */
5720
5721 static void ixgbe_shutdown(struct pci_dev *pdev)
5722 {
5723 bool wake;
5724
5725 __ixgbe_shutdown(pdev, &wake);
5726
5727 if (system_state == SYSTEM_POWER_OFF) {
5728 pci_wake_from_d3(pdev, wake);
5729 pci_set_power_state(pdev, PCI_D3hot);
5730 }
5731 }
5732
5733 /**
5734 * ixgbe_update_stats - Update the board statistics counters.
5735 * @adapter: board private structure
5736 **/
5737 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5738 {
5739 struct net_device *netdev = adapter->netdev;
5740 struct ixgbe_hw *hw = &adapter->hw;
5741 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5742 u64 total_mpc = 0;
5743 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5744 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5745 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5746 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5747
5748 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5749 test_bit(__IXGBE_RESETTING, &adapter->state))
5750 return;
5751
5752 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5753 u64 rsc_count = 0;
5754 u64 rsc_flush = 0;
5755 for (i = 0; i < adapter->num_rx_queues; i++) {
5756 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5757 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5758 }
5759 adapter->rsc_total_count = rsc_count;
5760 adapter->rsc_total_flush = rsc_flush;
5761 }
5762
5763 for (i = 0; i < adapter->num_rx_queues; i++) {
5764 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5765 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5766 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5767 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5768 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5769 bytes += rx_ring->stats.bytes;
5770 packets += rx_ring->stats.packets;
5771 }
5772 adapter->non_eop_descs = non_eop_descs;
5773 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5774 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5775 adapter->hw_csum_rx_error = hw_csum_rx_error;
5776 netdev->stats.rx_bytes = bytes;
5777 netdev->stats.rx_packets = packets;
5778
5779 bytes = 0;
5780 packets = 0;
5781 /* gather some stats to the adapter struct that are per queue */
5782 for (i = 0; i < adapter->num_tx_queues; i++) {
5783 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5784 restart_queue += tx_ring->tx_stats.restart_queue;
5785 tx_busy += tx_ring->tx_stats.tx_busy;
5786 bytes += tx_ring->stats.bytes;
5787 packets += tx_ring->stats.packets;
5788 }
5789 adapter->restart_queue = restart_queue;
5790 adapter->tx_busy = tx_busy;
5791 netdev->stats.tx_bytes = bytes;
5792 netdev->stats.tx_packets = packets;
5793
5794 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5795
5796 /* 8 register reads */
5797 for (i = 0; i < 8; i++) {
5798 /* for packet buffers not used, the register should read 0 */
5799 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5800 missed_rx += mpc;
5801 hwstats->mpc[i] += mpc;
5802 total_mpc += hwstats->mpc[i];
5803 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5804 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5805 switch (hw->mac.type) {
5806 case ixgbe_mac_82598EB:
5807 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5808 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5809 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5810 hwstats->pxonrxc[i] +=
5811 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5812 break;
5813 case ixgbe_mac_82599EB:
5814 case ixgbe_mac_X540:
5815 hwstats->pxonrxc[i] +=
5816 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5817 break;
5818 default:
5819 break;
5820 }
5821 }
5822
5823 /*16 register reads */
5824 for (i = 0; i < 16; i++) {
5825 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5826 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5827 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5828 (hw->mac.type == ixgbe_mac_X540)) {
5829 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5830 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5831 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5832 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5833 }
5834 }
5835
5836 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5837 /* work around hardware counting issue */
5838 hwstats->gprc -= missed_rx;
5839
5840 ixgbe_update_xoff_received(adapter);
5841
5842 /* 82598 hardware only has a 32 bit counter in the high register */
5843 switch (hw->mac.type) {
5844 case ixgbe_mac_82598EB:
5845 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5846 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5847 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5848 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5849 break;
5850 case ixgbe_mac_X540:
5851 /* OS2BMC stats are X540 only*/
5852 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5853 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5854 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5855 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5856 case ixgbe_mac_82599EB:
5857 for (i = 0; i < 16; i++)
5858 adapter->hw_rx_no_dma_resources +=
5859 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5860 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5861 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5862 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5863 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5864 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5865 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5866 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5867 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5868 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5869 #ifdef IXGBE_FCOE
5870 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5871 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5872 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5873 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5874 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5875 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5876 /* Add up per cpu counters for total ddp aloc fail */
5877 if (adapter->fcoe.ddp_pool) {
5878 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5879 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5880 unsigned int cpu;
5881 u64 noddp = 0, noddp_ext_buff = 0;
5882 for_each_possible_cpu(cpu) {
5883 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5884 noddp += ddp_pool->noddp;
5885 noddp_ext_buff += ddp_pool->noddp_ext_buff;
5886 }
5887 hwstats->fcoe_noddp = noddp;
5888 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
5889 }
5890 #endif /* IXGBE_FCOE */
5891 break;
5892 default:
5893 break;
5894 }
5895 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5896 hwstats->bprc += bprc;
5897 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5898 if (hw->mac.type == ixgbe_mac_82598EB)
5899 hwstats->mprc -= bprc;
5900 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5901 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5902 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5903 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5904 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5905 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5906 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5907 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5908 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5909 hwstats->lxontxc += lxon;
5910 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5911 hwstats->lxofftxc += lxoff;
5912 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5913 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5914 /*
5915 * 82598 errata - tx of flow control packets is included in tx counters
5916 */
5917 xon_off_tot = lxon + lxoff;
5918 hwstats->gptc -= xon_off_tot;
5919 hwstats->mptc -= xon_off_tot;
5920 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5921 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5922 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5923 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5924 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5925 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5926 hwstats->ptc64 -= xon_off_tot;
5927 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5928 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5929 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5930 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5931 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5932 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5933
5934 /* Fill out the OS statistics structure */
5935 netdev->stats.multicast = hwstats->mprc;
5936
5937 /* Rx Errors */
5938 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5939 netdev->stats.rx_dropped = 0;
5940 netdev->stats.rx_length_errors = hwstats->rlec;
5941 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5942 netdev->stats.rx_missed_errors = total_mpc;
5943 }
5944
5945 /**
5946 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5947 * @adapter: pointer to the device adapter structure
5948 **/
5949 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5950 {
5951 struct ixgbe_hw *hw = &adapter->hw;
5952 int i;
5953
5954 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5955 return;
5956
5957 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5958
5959 /* if interface is down do nothing */
5960 if (test_bit(__IXGBE_DOWN, &adapter->state))
5961 return;
5962
5963 /* do nothing if we are not using signature filters */
5964 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5965 return;
5966
5967 adapter->fdir_overflow++;
5968
5969 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5970 for (i = 0; i < adapter->num_tx_queues; i++)
5971 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5972 &(adapter->tx_ring[i]->state));
5973 /* re-enable flow director interrupts */
5974 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5975 } else {
5976 e_err(probe, "failed to finish FDIR re-initialization, "
5977 "ignored adding FDIR ATR filters\n");
5978 }
5979 }
5980
5981 /**
5982 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5983 * @adapter: pointer to the device adapter structure
5984 *
5985 * This function serves two purposes. First it strobes the interrupt lines
5986 * in order to make certain interrupts are occurring. Secondly it sets the
5987 * bits needed to check for TX hangs. As a result we should immediately
5988 * determine if a hang has occurred.
5989 */
5990 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5991 {
5992 struct ixgbe_hw *hw = &adapter->hw;
5993 u64 eics = 0;
5994 int i;
5995
5996 /* If we're down, removing or resetting, just bail */
5997 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5998 test_bit(__IXGBE_REMOVING, &adapter->state) ||
5999 test_bit(__IXGBE_RESETTING, &adapter->state))
6000 return;
6001
6002 /* Force detection of hung controller */
6003 if (netif_carrier_ok(adapter->netdev)) {
6004 for (i = 0; i < adapter->num_tx_queues; i++)
6005 set_check_for_tx_hang(adapter->tx_ring[i]);
6006 }
6007
6008 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6009 /*
6010 * for legacy and MSI interrupts don't set any bits
6011 * that are enabled for EIAM, because this operation
6012 * would set *both* EIMS and EICS for any bit in EIAM
6013 */
6014 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6015 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
6016 } else {
6017 /* get one bit for every active tx/rx interrupt vector */
6018 for (i = 0; i < adapter->num_q_vectors; i++) {
6019 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6020 if (qv->rx.ring || qv->tx.ring)
6021 eics |= ((u64)1 << i);
6022 }
6023 }
6024
6025 /* Cause software interrupt to ensure rings are cleaned */
6026 ixgbe_irq_rearm_queues(adapter, eics);
6027
6028 }
6029
6030 /**
6031 * ixgbe_watchdog_update_link - update the link status
6032 * @adapter: pointer to the device adapter structure
6033 * @link_speed: pointer to a u32 to store the link_speed
6034 **/
6035 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
6036 {
6037 struct ixgbe_hw *hw = &adapter->hw;
6038 u32 link_speed = adapter->link_speed;
6039 bool link_up = adapter->link_up;
6040 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
6041
6042 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6043 return;
6044
6045 if (hw->mac.ops.check_link) {
6046 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6047 } else {
6048 /* always assume link is up, if no check link function */
6049 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6050 link_up = true;
6051 }
6052
6053 if (adapter->ixgbe_ieee_pfc)
6054 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6055
6056 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
6057 hw->mac.ops.fc_enable(hw);
6058 ixgbe_set_rx_drop_en(adapter);
6059 }
6060
6061 if (link_up ||
6062 time_after(jiffies, (adapter->link_check_timeout +
6063 IXGBE_TRY_LINK_TIMEOUT))) {
6064 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6065 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6066 IXGBE_WRITE_FLUSH(hw);
6067 }
6068
6069 adapter->link_up = link_up;
6070 adapter->link_speed = link_speed;
6071 }
6072
6073 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6074 {
6075 #ifdef CONFIG_IXGBE_DCB
6076 struct net_device *netdev = adapter->netdev;
6077 struct dcb_app app = {
6078 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6079 .protocol = 0,
6080 };
6081 u8 up = 0;
6082
6083 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6084 up = dcb_ieee_getapp_mask(netdev, &app);
6085
6086 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6087 #endif
6088 }
6089
6090 /**
6091 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6092 * print link up message
6093 * @adapter: pointer to the device adapter structure
6094 **/
6095 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
6096 {
6097 struct net_device *netdev = adapter->netdev;
6098 struct ixgbe_hw *hw = &adapter->hw;
6099 struct net_device *upper;
6100 struct list_head *iter;
6101 u32 link_speed = adapter->link_speed;
6102 bool flow_rx, flow_tx;
6103
6104 /* only continue if link was previously down */
6105 if (netif_carrier_ok(netdev))
6106 return;
6107
6108 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
6109
6110 switch (hw->mac.type) {
6111 case ixgbe_mac_82598EB: {
6112 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6113 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6114 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6115 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6116 }
6117 break;
6118 case ixgbe_mac_X540:
6119 case ixgbe_mac_82599EB: {
6120 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6121 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6122 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6123 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6124 }
6125 break;
6126 default:
6127 flow_tx = false;
6128 flow_rx = false;
6129 break;
6130 }
6131
6132 adapter->last_rx_ptp_check = jiffies;
6133
6134 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6135 ixgbe_ptp_start_cyclecounter(adapter);
6136
6137 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6138 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6139 "10 Gbps" :
6140 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6141 "1 Gbps" :
6142 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6143 "100 Mbps" :
6144 "unknown speed"))),
6145 ((flow_rx && flow_tx) ? "RX/TX" :
6146 (flow_rx ? "RX" :
6147 (flow_tx ? "TX" : "None"))));
6148
6149 netif_carrier_on(netdev);
6150 ixgbe_check_vf_rate_limit(adapter);
6151
6152 /* enable transmits */
6153 netif_tx_wake_all_queues(adapter->netdev);
6154
6155 /* enable any upper devices */
6156 rtnl_lock();
6157 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6158 if (netif_is_macvlan(upper)) {
6159 struct macvlan_dev *vlan = netdev_priv(upper);
6160
6161 if (vlan->fwd_priv)
6162 netif_tx_wake_all_queues(upper);
6163 }
6164 }
6165 rtnl_unlock();
6166
6167 /* update the default user priority for VFs */
6168 ixgbe_update_default_up(adapter);
6169
6170 /* ping all the active vfs to let them know link has changed */
6171 ixgbe_ping_all_vfs(adapter);
6172 }
6173
6174 /**
6175 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6176 * print link down message
6177 * @adapter: pointer to the adapter structure
6178 **/
6179 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
6180 {
6181 struct net_device *netdev = adapter->netdev;
6182 struct ixgbe_hw *hw = &adapter->hw;
6183
6184 adapter->link_up = false;
6185 adapter->link_speed = 0;
6186
6187 /* only continue if link was up previously */
6188 if (!netif_carrier_ok(netdev))
6189 return;
6190
6191 /* poll for SFP+ cable when link is down */
6192 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6193 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6194
6195 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6196 ixgbe_ptp_start_cyclecounter(adapter);
6197
6198 e_info(drv, "NIC Link is Down\n");
6199 netif_carrier_off(netdev);
6200
6201 /* ping all the active vfs to let them know link has changed */
6202 ixgbe_ping_all_vfs(adapter);
6203 }
6204
6205 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6206 {
6207 int i;
6208
6209 for (i = 0; i < adapter->num_tx_queues; i++) {
6210 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6211
6212 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6213 return true;
6214 }
6215
6216 return false;
6217 }
6218
6219 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6220 {
6221 struct ixgbe_hw *hw = &adapter->hw;
6222 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6223 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6224
6225 int i, j;
6226
6227 if (!adapter->num_vfs)
6228 return false;
6229
6230 for (i = 0; i < adapter->num_vfs; i++) {
6231 for (j = 0; j < q_per_pool; j++) {
6232 u32 h, t;
6233
6234 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6235 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6236
6237 if (h != t)
6238 return true;
6239 }
6240 }
6241
6242 return false;
6243 }
6244
6245 /**
6246 * ixgbe_watchdog_flush_tx - flush queues on link down
6247 * @adapter: pointer to the device adapter structure
6248 **/
6249 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6250 {
6251 if (!netif_carrier_ok(adapter->netdev)) {
6252 if (ixgbe_ring_tx_pending(adapter) ||
6253 ixgbe_vf_tx_pending(adapter)) {
6254 /* We've lost link, so the controller stops DMA,
6255 * but we've got queued Tx work that's never going
6256 * to get done, so reset controller to flush Tx.
6257 * (Do the reset outside of interrupt context).
6258 */
6259 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
6260 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6261 }
6262 }
6263 }
6264
6265 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6266 {
6267 u32 ssvpc;
6268
6269 /* Do not perform spoof check for 82598 or if not in IOV mode */
6270 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6271 adapter->num_vfs == 0)
6272 return;
6273
6274 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6275
6276 /*
6277 * ssvpc register is cleared on read, if zero then no
6278 * spoofed packets in the last interval.
6279 */
6280 if (!ssvpc)
6281 return;
6282
6283 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
6284 }
6285
6286 /**
6287 * ixgbe_watchdog_subtask - check and bring link up
6288 * @adapter: pointer to the device adapter structure
6289 **/
6290 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6291 {
6292 /* if interface is down, removing or resetting, do nothing */
6293 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6294 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6295 test_bit(__IXGBE_RESETTING, &adapter->state))
6296 return;
6297
6298 ixgbe_watchdog_update_link(adapter);
6299
6300 if (adapter->link_up)
6301 ixgbe_watchdog_link_is_up(adapter);
6302 else
6303 ixgbe_watchdog_link_is_down(adapter);
6304
6305 ixgbe_spoof_check(adapter);
6306 ixgbe_update_stats(adapter);
6307
6308 ixgbe_watchdog_flush_tx(adapter);
6309 }
6310
6311 /**
6312 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6313 * @adapter: the ixgbe adapter structure
6314 **/
6315 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6316 {
6317 struct ixgbe_hw *hw = &adapter->hw;
6318 s32 err;
6319
6320 /* not searching for SFP so there is nothing to do here */
6321 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6322 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6323 return;
6324
6325 /* someone else is in init, wait until next service event */
6326 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6327 return;
6328
6329 err = hw->phy.ops.identify_sfp(hw);
6330 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6331 goto sfp_out;
6332
6333 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6334 /* If no cable is present, then we need to reset
6335 * the next time we find a good cable. */
6336 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6337 }
6338
6339 /* exit on error */
6340 if (err)
6341 goto sfp_out;
6342
6343 /* exit if reset not needed */
6344 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6345 goto sfp_out;
6346
6347 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6348
6349 /*
6350 * A module may be identified correctly, but the EEPROM may not have
6351 * support for that module. setup_sfp() will fail in that case, so
6352 * we should not allow that module to load.
6353 */
6354 if (hw->mac.type == ixgbe_mac_82598EB)
6355 err = hw->phy.ops.reset(hw);
6356 else
6357 err = hw->mac.ops.setup_sfp(hw);
6358
6359 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6360 goto sfp_out;
6361
6362 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6363 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6364
6365 sfp_out:
6366 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6367
6368 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6369 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6370 e_dev_err("failed to initialize because an unsupported "
6371 "SFP+ module type was detected.\n");
6372 e_dev_err("Reload the driver after installing a "
6373 "supported module.\n");
6374 unregister_netdev(adapter->netdev);
6375 }
6376 }
6377
6378 /**
6379 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6380 * @adapter: the ixgbe adapter structure
6381 **/
6382 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6383 {
6384 struct ixgbe_hw *hw = &adapter->hw;
6385 u32 speed;
6386 bool autoneg = false;
6387
6388 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6389 return;
6390
6391 /* someone else is in init, wait until next service event */
6392 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6393 return;
6394
6395 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6396
6397 speed = hw->phy.autoneg_advertised;
6398 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
6399 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
6400
6401 /* setup the highest link when no autoneg */
6402 if (!autoneg) {
6403 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6404 speed = IXGBE_LINK_SPEED_10GB_FULL;
6405 }
6406 }
6407
6408 if (hw->mac.ops.setup_link)
6409 hw->mac.ops.setup_link(hw, speed, true);
6410
6411 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6412 adapter->link_check_timeout = jiffies;
6413 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6414 }
6415
6416 #ifdef CONFIG_PCI_IOV
6417 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6418 {
6419 int vf;
6420 struct ixgbe_hw *hw = &adapter->hw;
6421 struct net_device *netdev = adapter->netdev;
6422 u32 gpc;
6423 u32 ciaa, ciad;
6424
6425 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6426 if (gpc) /* If incrementing then no need for the check below */
6427 return;
6428 /*
6429 * Check to see if a bad DMA write target from an errant or
6430 * malicious VF has caused a PCIe error. If so then we can
6431 * issue a VFLR to the offending VF(s) and then resume without
6432 * requesting a full slot reset.
6433 */
6434
6435 for (vf = 0; vf < adapter->num_vfs; vf++) {
6436 ciaa = (vf << 16) | 0x80000000;
6437 /* 32 bit read so align, we really want status at offset 6 */
6438 ciaa |= PCI_COMMAND;
6439 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6440 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6441 ciaa &= 0x7FFFFFFF;
6442 /* disable debug mode asap after reading data */
6443 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6444 /* Get the upper 16 bits which will be the PCI status reg */
6445 ciad >>= 16;
6446 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6447 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6448 /* Issue VFLR */
6449 ciaa = (vf << 16) | 0x80000000;
6450 ciaa |= 0xA8;
6451 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6452 ciad = 0x00008000; /* VFLR */
6453 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6454 ciaa &= 0x7FFFFFFF;
6455 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6456 }
6457 }
6458 }
6459
6460 #endif
6461 /**
6462 * ixgbe_service_timer - Timer Call-back
6463 * @data: pointer to adapter cast into an unsigned long
6464 **/
6465 static void ixgbe_service_timer(unsigned long data)
6466 {
6467 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6468 unsigned long next_event_offset;
6469 bool ready = true;
6470
6471 /* poll faster when waiting for link */
6472 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6473 next_event_offset = HZ / 10;
6474 else
6475 next_event_offset = HZ * 2;
6476
6477 #ifdef CONFIG_PCI_IOV
6478 /*
6479 * don't bother with SR-IOV VF DMA hang check if there are
6480 * no VFs or the link is down
6481 */
6482 if (!adapter->num_vfs ||
6483 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6484 goto normal_timer_service;
6485
6486 /* If we have VFs allocated then we must check for DMA hangs */
6487 ixgbe_check_for_bad_vf(adapter);
6488 next_event_offset = HZ / 50;
6489 adapter->timer_event_accumulator++;
6490
6491 if (adapter->timer_event_accumulator >= 100)
6492 adapter->timer_event_accumulator = 0;
6493 else
6494 ready = false;
6495
6496 normal_timer_service:
6497 #endif
6498 /* Reset the timer */
6499 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6500
6501 if (ready)
6502 ixgbe_service_event_schedule(adapter);
6503 }
6504
6505 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6506 {
6507 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6508 return;
6509
6510 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6511
6512 /* If we're already down, removing or resetting, just bail */
6513 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6514 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6515 test_bit(__IXGBE_RESETTING, &adapter->state))
6516 return;
6517
6518 ixgbe_dump(adapter);
6519 netdev_err(adapter->netdev, "Reset adapter\n");
6520 adapter->tx_timeout_count++;
6521
6522 rtnl_lock();
6523 ixgbe_reinit_locked(adapter);
6524 rtnl_unlock();
6525 }
6526
6527 /**
6528 * ixgbe_service_task - manages and runs subtasks
6529 * @work: pointer to work_struct containing our data
6530 **/
6531 static void ixgbe_service_task(struct work_struct *work)
6532 {
6533 struct ixgbe_adapter *adapter = container_of(work,
6534 struct ixgbe_adapter,
6535 service_task);
6536 if (ixgbe_removed(adapter->hw.hw_addr)) {
6537 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6538 rtnl_lock();
6539 ixgbe_down(adapter);
6540 rtnl_unlock();
6541 }
6542 ixgbe_service_event_complete(adapter);
6543 return;
6544 }
6545 ixgbe_reset_subtask(adapter);
6546 ixgbe_sfp_detection_subtask(adapter);
6547 ixgbe_sfp_link_config_subtask(adapter);
6548 ixgbe_check_overtemp_subtask(adapter);
6549 ixgbe_watchdog_subtask(adapter);
6550 ixgbe_fdir_reinit_subtask(adapter);
6551 ixgbe_check_hang_subtask(adapter);
6552
6553 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
6554 ixgbe_ptp_overflow_check(adapter);
6555 ixgbe_ptp_rx_hang(adapter);
6556 }
6557
6558 ixgbe_service_event_complete(adapter);
6559 }
6560
6561 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6562 struct ixgbe_tx_buffer *first,
6563 u8 *hdr_len)
6564 {
6565 struct sk_buff *skb = first->skb;
6566 u32 vlan_macip_lens, type_tucmd;
6567 u32 mss_l4len_idx, l4len;
6568 int err;
6569
6570 if (skb->ip_summed != CHECKSUM_PARTIAL)
6571 return 0;
6572
6573 if (!skb_is_gso(skb))
6574 return 0;
6575
6576 err = skb_cow_head(skb, 0);
6577 if (err < 0)
6578 return err;
6579
6580 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6581 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6582
6583 if (first->protocol == htons(ETH_P_IP)) {
6584 struct iphdr *iph = ip_hdr(skb);
6585 iph->tot_len = 0;
6586 iph->check = 0;
6587 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6588 iph->daddr, 0,
6589 IPPROTO_TCP,
6590 0);
6591 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6592 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6593 IXGBE_TX_FLAGS_CSUM |
6594 IXGBE_TX_FLAGS_IPV4;
6595 } else if (skb_is_gso_v6(skb)) {
6596 ipv6_hdr(skb)->payload_len = 0;
6597 tcp_hdr(skb)->check =
6598 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6599 &ipv6_hdr(skb)->daddr,
6600 0, IPPROTO_TCP, 0);
6601 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6602 IXGBE_TX_FLAGS_CSUM;
6603 }
6604
6605 /* compute header lengths */
6606 l4len = tcp_hdrlen(skb);
6607 *hdr_len = skb_transport_offset(skb) + l4len;
6608
6609 /* update gso size and bytecount with header size */
6610 first->gso_segs = skb_shinfo(skb)->gso_segs;
6611 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6612
6613 /* mss_l4len_id: use 0 as index for TSO */
6614 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6615 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6616
6617 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6618 vlan_macip_lens = skb_network_header_len(skb);
6619 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6620 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6621
6622 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6623 mss_l4len_idx);
6624
6625 return 1;
6626 }
6627
6628 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6629 struct ixgbe_tx_buffer *first)
6630 {
6631 struct sk_buff *skb = first->skb;
6632 u32 vlan_macip_lens = 0;
6633 u32 mss_l4len_idx = 0;
6634 u32 type_tucmd = 0;
6635
6636 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6637 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6638 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6639 return;
6640 } else {
6641 u8 l4_hdr = 0;
6642 switch (first->protocol) {
6643 case htons(ETH_P_IP):
6644 vlan_macip_lens |= skb_network_header_len(skb);
6645 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6646 l4_hdr = ip_hdr(skb)->protocol;
6647 break;
6648 case htons(ETH_P_IPV6):
6649 vlan_macip_lens |= skb_network_header_len(skb);
6650 l4_hdr = ipv6_hdr(skb)->nexthdr;
6651 break;
6652 default:
6653 if (unlikely(net_ratelimit())) {
6654 dev_warn(tx_ring->dev,
6655 "partial checksum but proto=%x!\n",
6656 first->protocol);
6657 }
6658 break;
6659 }
6660
6661 switch (l4_hdr) {
6662 case IPPROTO_TCP:
6663 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6664 mss_l4len_idx = tcp_hdrlen(skb) <<
6665 IXGBE_ADVTXD_L4LEN_SHIFT;
6666 break;
6667 case IPPROTO_SCTP:
6668 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6669 mss_l4len_idx = sizeof(struct sctphdr) <<
6670 IXGBE_ADVTXD_L4LEN_SHIFT;
6671 break;
6672 case IPPROTO_UDP:
6673 mss_l4len_idx = sizeof(struct udphdr) <<
6674 IXGBE_ADVTXD_L4LEN_SHIFT;
6675 break;
6676 default:
6677 if (unlikely(net_ratelimit())) {
6678 dev_warn(tx_ring->dev,
6679 "partial checksum but l4 proto=%x!\n",
6680 l4_hdr);
6681 }
6682 break;
6683 }
6684
6685 /* update TX checksum flag */
6686 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
6687 }
6688
6689 /* vlan_macip_lens: MACLEN, VLAN tag */
6690 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6691 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6692
6693 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6694 type_tucmd, mss_l4len_idx);
6695 }
6696
6697 #define IXGBE_SET_FLAG(_input, _flag, _result) \
6698 ((_flag <= _result) ? \
6699 ((u32)(_input & _flag) * (_result / _flag)) : \
6700 ((u32)(_input & _flag) / (_flag / _result)))
6701
6702 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6703 {
6704 /* set type for advanced descriptor with frame checksum insertion */
6705 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6706 IXGBE_ADVTXD_DCMD_DEXT |
6707 IXGBE_ADVTXD_DCMD_IFCS;
6708
6709 /* set HW vlan bit if vlan is present */
6710 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6711 IXGBE_ADVTXD_DCMD_VLE);
6712
6713 /* set segmentation enable bits for TSO/FSO */
6714 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6715 IXGBE_ADVTXD_DCMD_TSE);
6716
6717 /* set timestamp bit if present */
6718 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6719 IXGBE_ADVTXD_MAC_TSTAMP);
6720
6721 /* insert frame checksum */
6722 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
6723
6724 return cmd_type;
6725 }
6726
6727 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6728 u32 tx_flags, unsigned int paylen)
6729 {
6730 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
6731
6732 /* enable L4 checksum for TSO and TX checksum offload */
6733 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6734 IXGBE_TX_FLAGS_CSUM,
6735 IXGBE_ADVTXD_POPTS_TXSM);
6736
6737 /* enble IPv4 checksum for TSO */
6738 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6739 IXGBE_TX_FLAGS_IPV4,
6740 IXGBE_ADVTXD_POPTS_IXSM);
6741
6742 /*
6743 * Check Context must be set if Tx switch is enabled, which it
6744 * always is for case where virtual functions are running
6745 */
6746 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6747 IXGBE_TX_FLAGS_CC,
6748 IXGBE_ADVTXD_CC);
6749
6750 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6751 }
6752
6753 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6754 {
6755 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6756
6757 /* Herbert's original patch had:
6758 * smp_mb__after_netif_stop_queue();
6759 * but since that doesn't exist yet, just open code it.
6760 */
6761 smp_mb();
6762
6763 /* We need to check again in a case another CPU has just
6764 * made room available.
6765 */
6766 if (likely(ixgbe_desc_unused(tx_ring) < size))
6767 return -EBUSY;
6768
6769 /* A reprieve! - use start_queue because it doesn't call schedule */
6770 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6771 ++tx_ring->tx_stats.restart_queue;
6772 return 0;
6773 }
6774
6775 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6776 {
6777 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6778 return 0;
6779
6780 return __ixgbe_maybe_stop_tx(tx_ring, size);
6781 }
6782
6783 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6784 IXGBE_TXD_CMD_RS)
6785
6786 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6787 struct ixgbe_tx_buffer *first,
6788 const u8 hdr_len)
6789 {
6790 struct sk_buff *skb = first->skb;
6791 struct ixgbe_tx_buffer *tx_buffer;
6792 union ixgbe_adv_tx_desc *tx_desc;
6793 struct skb_frag_struct *frag;
6794 dma_addr_t dma;
6795 unsigned int data_len, size;
6796 u32 tx_flags = first->tx_flags;
6797 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
6798 u16 i = tx_ring->next_to_use;
6799
6800 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6801
6802 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6803
6804 size = skb_headlen(skb);
6805 data_len = skb->data_len;
6806
6807 #ifdef IXGBE_FCOE
6808 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6809 if (data_len < sizeof(struct fcoe_crc_eof)) {
6810 size -= sizeof(struct fcoe_crc_eof) - data_len;
6811 data_len = 0;
6812 } else {
6813 data_len -= sizeof(struct fcoe_crc_eof);
6814 }
6815 }
6816
6817 #endif
6818 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6819
6820 tx_buffer = first;
6821
6822 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6823 if (dma_mapping_error(tx_ring->dev, dma))
6824 goto dma_error;
6825
6826 /* record length, and DMA address */
6827 dma_unmap_len_set(tx_buffer, len, size);
6828 dma_unmap_addr_set(tx_buffer, dma, dma);
6829
6830 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6831
6832 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6833 tx_desc->read.cmd_type_len =
6834 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
6835
6836 i++;
6837 tx_desc++;
6838 if (i == tx_ring->count) {
6839 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6840 i = 0;
6841 }
6842 tx_desc->read.olinfo_status = 0;
6843
6844 dma += IXGBE_MAX_DATA_PER_TXD;
6845 size -= IXGBE_MAX_DATA_PER_TXD;
6846
6847 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6848 }
6849
6850 if (likely(!data_len))
6851 break;
6852
6853 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6854
6855 i++;
6856 tx_desc++;
6857 if (i == tx_ring->count) {
6858 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6859 i = 0;
6860 }
6861 tx_desc->read.olinfo_status = 0;
6862
6863 #ifdef IXGBE_FCOE
6864 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6865 #else
6866 size = skb_frag_size(frag);
6867 #endif
6868 data_len -= size;
6869
6870 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6871 DMA_TO_DEVICE);
6872
6873 tx_buffer = &tx_ring->tx_buffer_info[i];
6874 }
6875
6876 /* write last descriptor with RS and EOP bits */
6877 cmd_type |= size | IXGBE_TXD_CMD;
6878 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6879
6880 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6881
6882 /* set the timestamp */
6883 first->time_stamp = jiffies;
6884
6885 /*
6886 * Force memory writes to complete before letting h/w know there
6887 * are new descriptors to fetch. (Only applicable for weak-ordered
6888 * memory model archs, such as IA-64).
6889 *
6890 * We also need this memory barrier to make certain all of the
6891 * status bits have been updated before next_to_watch is written.
6892 */
6893 wmb();
6894
6895 /* set next_to_watch value indicating a packet is present */
6896 first->next_to_watch = tx_desc;
6897
6898 i++;
6899 if (i == tx_ring->count)
6900 i = 0;
6901
6902 tx_ring->next_to_use = i;
6903
6904 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6905
6906 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
6907 /* notify HW of packet */
6908 ixgbe_write_tail(tx_ring, i);
6909 }
6910
6911 return;
6912 dma_error:
6913 dev_err(tx_ring->dev, "TX DMA map failed\n");
6914
6915 /* clear dma mappings for failed tx_buffer_info map */
6916 for (;;) {
6917 tx_buffer = &tx_ring->tx_buffer_info[i];
6918 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6919 if (tx_buffer == first)
6920 break;
6921 if (i == 0)
6922 i = tx_ring->count;
6923 i--;
6924 }
6925
6926 tx_ring->next_to_use = i;
6927 }
6928
6929 static void ixgbe_atr(struct ixgbe_ring *ring,
6930 struct ixgbe_tx_buffer *first)
6931 {
6932 struct ixgbe_q_vector *q_vector = ring->q_vector;
6933 union ixgbe_atr_hash_dword input = { .dword = 0 };
6934 union ixgbe_atr_hash_dword common = { .dword = 0 };
6935 union {
6936 unsigned char *network;
6937 struct iphdr *ipv4;
6938 struct ipv6hdr *ipv6;
6939 } hdr;
6940 struct tcphdr *th;
6941 __be16 vlan_id;
6942
6943 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6944 if (!q_vector)
6945 return;
6946
6947 /* do nothing if sampling is disabled */
6948 if (!ring->atr_sample_rate)
6949 return;
6950
6951 ring->atr_count++;
6952
6953 /* snag network header to get L4 type and address */
6954 hdr.network = skb_network_header(first->skb);
6955
6956 /* Currently only IPv4/IPv6 with TCP is supported */
6957 if ((first->protocol != htons(ETH_P_IPV6) ||
6958 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6959 (first->protocol != htons(ETH_P_IP) ||
6960 hdr.ipv4->protocol != IPPROTO_TCP))
6961 return;
6962
6963 th = tcp_hdr(first->skb);
6964
6965 /* skip this packet since it is invalid or the socket is closing */
6966 if (!th || th->fin)
6967 return;
6968
6969 /* sample on all syn packets or once every atr sample count */
6970 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6971 return;
6972
6973 /* reset sample count */
6974 ring->atr_count = 0;
6975
6976 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6977
6978 /*
6979 * src and dst are inverted, think how the receiver sees them
6980 *
6981 * The input is broken into two sections, a non-compressed section
6982 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6983 * is XORed together and stored in the compressed dword.
6984 */
6985 input.formatted.vlan_id = vlan_id;
6986
6987 /*
6988 * since src port and flex bytes occupy the same word XOR them together
6989 * and write the value to source port portion of compressed dword
6990 */
6991 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6992 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
6993 else
6994 common.port.src ^= th->dest ^ first->protocol;
6995 common.port.dst ^= th->source;
6996
6997 if (first->protocol == htons(ETH_P_IP)) {
6998 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6999 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7000 } else {
7001 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7002 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7003 hdr.ipv6->saddr.s6_addr32[1] ^
7004 hdr.ipv6->saddr.s6_addr32[2] ^
7005 hdr.ipv6->saddr.s6_addr32[3] ^
7006 hdr.ipv6->daddr.s6_addr32[0] ^
7007 hdr.ipv6->daddr.s6_addr32[1] ^
7008 hdr.ipv6->daddr.s6_addr32[2] ^
7009 hdr.ipv6->daddr.s6_addr32[3];
7010 }
7011
7012 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
7013 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7014 input, common, ring->queue_index);
7015 }
7016
7017 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
7018 void *accel_priv, select_queue_fallback_t fallback)
7019 {
7020 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7021 #ifdef IXGBE_FCOE
7022 struct ixgbe_adapter *adapter;
7023 struct ixgbe_ring_feature *f;
7024 int txq;
7025 #endif
7026
7027 if (fwd_adapter)
7028 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7029
7030 #ifdef IXGBE_FCOE
7031
7032 /*
7033 * only execute the code below if protocol is FCoE
7034 * or FIP and we have FCoE enabled on the adapter
7035 */
7036 switch (vlan_get_protocol(skb)) {
7037 case htons(ETH_P_FCOE):
7038 case htons(ETH_P_FIP):
7039 adapter = netdev_priv(dev);
7040
7041 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7042 break;
7043 default:
7044 return fallback(dev, skb);
7045 }
7046
7047 f = &adapter->ring_feature[RING_F_FCOE];
7048
7049 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7050 smp_processor_id();
7051
7052 while (txq >= f->indices)
7053 txq -= f->indices;
7054
7055 return txq + f->offset;
7056 #else
7057 return fallback(dev, skb);
7058 #endif
7059 }
7060
7061 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
7062 struct ixgbe_adapter *adapter,
7063 struct ixgbe_ring *tx_ring)
7064 {
7065 struct ixgbe_tx_buffer *first;
7066 int tso;
7067 u32 tx_flags = 0;
7068 unsigned short f;
7069 u16 count = TXD_USE_COUNT(skb_headlen(skb));
7070 __be16 protocol = skb->protocol;
7071 u8 hdr_len = 0;
7072
7073 /*
7074 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
7075 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
7076 * + 2 desc gap to keep tail from touching head,
7077 * + 1 desc for context descriptor,
7078 * otherwise try next time
7079 */
7080 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7081 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7082
7083 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7084 tx_ring->tx_stats.tx_busy++;
7085 return NETDEV_TX_BUSY;
7086 }
7087
7088 /* record the location of the first descriptor for this packet */
7089 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7090 first->skb = skb;
7091 first->bytecount = skb->len;
7092 first->gso_segs = 1;
7093
7094 /* if we have a HW VLAN tag being added default to the HW one */
7095 if (vlan_tx_tag_present(skb)) {
7096 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7097 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7098 /* else if it is a SW VLAN check the next protocol and store the tag */
7099 } else if (protocol == htons(ETH_P_8021Q)) {
7100 struct vlan_hdr *vhdr, _vhdr;
7101 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7102 if (!vhdr)
7103 goto out_drop;
7104
7105 protocol = vhdr->h_vlan_encapsulated_proto;
7106 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7107 IXGBE_TX_FLAGS_VLAN_SHIFT;
7108 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7109 }
7110
7111 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
7112 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7113 &adapter->state))) {
7114 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7115 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
7116
7117 /* schedule check for Tx timestamp */
7118 adapter->ptp_tx_skb = skb_get(skb);
7119 adapter->ptp_tx_start = jiffies;
7120 schedule_work(&adapter->ptp_tx_work);
7121 }
7122
7123 skb_tx_timestamp(skb);
7124
7125 #ifdef CONFIG_PCI_IOV
7126 /*
7127 * Use the l2switch_enable flag - would be false if the DMA
7128 * Tx switch had been disabled.
7129 */
7130 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7131 tx_flags |= IXGBE_TX_FLAGS_CC;
7132
7133 #endif
7134 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
7135 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7136 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7137 (skb->priority != TC_PRIO_CONTROL))) {
7138 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
7139 tx_flags |= (skb->priority & 0x7) <<
7140 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
7141 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7142 struct vlan_ethhdr *vhdr;
7143
7144 if (skb_cow_head(skb, 0))
7145 goto out_drop;
7146 vhdr = (struct vlan_ethhdr *)skb->data;
7147 vhdr->h_vlan_TCI = htons(tx_flags >>
7148 IXGBE_TX_FLAGS_VLAN_SHIFT);
7149 } else {
7150 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7151 }
7152 }
7153
7154 /* record initial flags and protocol */
7155 first->tx_flags = tx_flags;
7156 first->protocol = protocol;
7157
7158 #ifdef IXGBE_FCOE
7159 /* setup tx offload for FCoE */
7160 if ((protocol == htons(ETH_P_FCOE)) &&
7161 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
7162 tso = ixgbe_fso(tx_ring, first, &hdr_len);
7163 if (tso < 0)
7164 goto out_drop;
7165
7166 goto xmit_fcoe;
7167 }
7168
7169 #endif /* IXGBE_FCOE */
7170 tso = ixgbe_tso(tx_ring, first, &hdr_len);
7171 if (tso < 0)
7172 goto out_drop;
7173 else if (!tso)
7174 ixgbe_tx_csum(tx_ring, first);
7175
7176 /* add the ATR filter if ATR is on */
7177 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7178 ixgbe_atr(tx_ring, first);
7179
7180 #ifdef IXGBE_FCOE
7181 xmit_fcoe:
7182 #endif /* IXGBE_FCOE */
7183 ixgbe_tx_map(tx_ring, first, hdr_len);
7184
7185 return NETDEV_TX_OK;
7186
7187 out_drop:
7188 dev_kfree_skb_any(first->skb);
7189 first->skb = NULL;
7190
7191 return NETDEV_TX_OK;
7192 }
7193
7194 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7195 struct net_device *netdev,
7196 struct ixgbe_ring *ring)
7197 {
7198 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7199 struct ixgbe_ring *tx_ring;
7200
7201 /*
7202 * The minimum packet size for olinfo paylen is 17 so pad the skb
7203 * in order to meet this minimum size requirement.
7204 */
7205 if (unlikely(skb->len < 17)) {
7206 if (skb_pad(skb, 17 - skb->len))
7207 return NETDEV_TX_OK;
7208 skb->len = 17;
7209 skb_set_tail_pointer(skb, 17);
7210 }
7211
7212 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7213
7214 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
7215 }
7216
7217 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7218 struct net_device *netdev)
7219 {
7220 return __ixgbe_xmit_frame(skb, netdev, NULL);
7221 }
7222
7223 /**
7224 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7225 * @netdev: network interface device structure
7226 * @p: pointer to an address structure
7227 *
7228 * Returns 0 on success, negative on failure
7229 **/
7230 static int ixgbe_set_mac(struct net_device *netdev, void *p)
7231 {
7232 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7233 struct ixgbe_hw *hw = &adapter->hw;
7234 struct sockaddr *addr = p;
7235 int ret;
7236
7237 if (!is_valid_ether_addr(addr->sa_data))
7238 return -EADDRNOTAVAIL;
7239
7240 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7241 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
7242 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
7243
7244 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7245 return ret > 0 ? 0 : ret;
7246 }
7247
7248 static int
7249 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7250 {
7251 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7252 struct ixgbe_hw *hw = &adapter->hw;
7253 u16 value;
7254 int rc;
7255
7256 if (prtad != hw->phy.mdio.prtad)
7257 return -EINVAL;
7258 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7259 if (!rc)
7260 rc = value;
7261 return rc;
7262 }
7263
7264 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7265 u16 addr, u16 value)
7266 {
7267 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7268 struct ixgbe_hw *hw = &adapter->hw;
7269
7270 if (prtad != hw->phy.mdio.prtad)
7271 return -EINVAL;
7272 return hw->phy.ops.write_reg(hw, addr, devad, value);
7273 }
7274
7275 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7276 {
7277 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7278
7279 switch (cmd) {
7280 case SIOCSHWTSTAMP:
7281 return ixgbe_ptp_set_ts_config(adapter, req);
7282 case SIOCGHWTSTAMP:
7283 return ixgbe_ptp_get_ts_config(adapter, req);
7284 default:
7285 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7286 }
7287 }
7288
7289 /**
7290 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
7291 * netdev->dev_addrs
7292 * @netdev: network interface device structure
7293 *
7294 * Returns non-zero on failure
7295 **/
7296 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7297 {
7298 int err = 0;
7299 struct ixgbe_adapter *adapter = netdev_priv(dev);
7300 struct ixgbe_hw *hw = &adapter->hw;
7301
7302 if (is_valid_ether_addr(hw->mac.san_addr)) {
7303 rtnl_lock();
7304 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
7305 rtnl_unlock();
7306
7307 /* update SAN MAC vmdq pool selection */
7308 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
7309 }
7310 return err;
7311 }
7312
7313 /**
7314 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7315 * netdev->dev_addrs
7316 * @netdev: network interface device structure
7317 *
7318 * Returns non-zero on failure
7319 **/
7320 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7321 {
7322 int err = 0;
7323 struct ixgbe_adapter *adapter = netdev_priv(dev);
7324 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7325
7326 if (is_valid_ether_addr(mac->san_addr)) {
7327 rtnl_lock();
7328 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7329 rtnl_unlock();
7330 }
7331 return err;
7332 }
7333
7334 #ifdef CONFIG_NET_POLL_CONTROLLER
7335 /*
7336 * Polling 'interrupt' - used by things like netconsole to send skbs
7337 * without having to re-enable interrupts. It's not called while
7338 * the interrupt routine is executing.
7339 */
7340 static void ixgbe_netpoll(struct net_device *netdev)
7341 {
7342 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7343 int i;
7344
7345 /* if interface is down do nothing */
7346 if (test_bit(__IXGBE_DOWN, &adapter->state))
7347 return;
7348
7349 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
7350 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7351 for (i = 0; i < adapter->num_q_vectors; i++)
7352 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
7353 } else {
7354 ixgbe_intr(adapter->pdev->irq, netdev);
7355 }
7356 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7357 }
7358
7359 #endif
7360 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7361 struct rtnl_link_stats64 *stats)
7362 {
7363 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7364 int i;
7365
7366 rcu_read_lock();
7367 for (i = 0; i < adapter->num_rx_queues; i++) {
7368 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7369 u64 bytes, packets;
7370 unsigned int start;
7371
7372 if (ring) {
7373 do {
7374 start = u64_stats_fetch_begin_irq(&ring->syncp);
7375 packets = ring->stats.packets;
7376 bytes = ring->stats.bytes;
7377 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
7378 stats->rx_packets += packets;
7379 stats->rx_bytes += bytes;
7380 }
7381 }
7382
7383 for (i = 0; i < adapter->num_tx_queues; i++) {
7384 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7385 u64 bytes, packets;
7386 unsigned int start;
7387
7388 if (ring) {
7389 do {
7390 start = u64_stats_fetch_begin_irq(&ring->syncp);
7391 packets = ring->stats.packets;
7392 bytes = ring->stats.bytes;
7393 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
7394 stats->tx_packets += packets;
7395 stats->tx_bytes += bytes;
7396 }
7397 }
7398 rcu_read_unlock();
7399 /* following stats updated by ixgbe_watchdog_task() */
7400 stats->multicast = netdev->stats.multicast;
7401 stats->rx_errors = netdev->stats.rx_errors;
7402 stats->rx_length_errors = netdev->stats.rx_length_errors;
7403 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7404 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7405 return stats;
7406 }
7407
7408 #ifdef CONFIG_IXGBE_DCB
7409 /**
7410 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7411 * @adapter: pointer to ixgbe_adapter
7412 * @tc: number of traffic classes currently enabled
7413 *
7414 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7415 * 802.1Q priority maps to a packet buffer that exists.
7416 */
7417 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7418 {
7419 struct ixgbe_hw *hw = &adapter->hw;
7420 u32 reg, rsave;
7421 int i;
7422
7423 /* 82598 have a static priority to TC mapping that can not
7424 * be changed so no validation is needed.
7425 */
7426 if (hw->mac.type == ixgbe_mac_82598EB)
7427 return;
7428
7429 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7430 rsave = reg;
7431
7432 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7433 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7434
7435 /* If up2tc is out of bounds default to zero */
7436 if (up2tc > tc)
7437 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7438 }
7439
7440 if (reg != rsave)
7441 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7442
7443 return;
7444 }
7445
7446 /**
7447 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7448 * @adapter: Pointer to adapter struct
7449 *
7450 * Populate the netdev user priority to tc map
7451 */
7452 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7453 {
7454 struct net_device *dev = adapter->netdev;
7455 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7456 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7457 u8 prio;
7458
7459 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7460 u8 tc = 0;
7461
7462 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7463 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7464 else if (ets)
7465 tc = ets->prio_tc[prio];
7466
7467 netdev_set_prio_tc_map(dev, prio, tc);
7468 }
7469 }
7470
7471 #endif /* CONFIG_IXGBE_DCB */
7472 /**
7473 * ixgbe_setup_tc - configure net_device for multiple traffic classes
7474 *
7475 * @netdev: net device to configure
7476 * @tc: number of traffic classes to enable
7477 */
7478 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7479 {
7480 struct ixgbe_adapter *adapter = netdev_priv(dev);
7481 struct ixgbe_hw *hw = &adapter->hw;
7482 bool pools;
7483
7484 /* Hardware supports up to 8 traffic classes */
7485 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
7486 (hw->mac.type == ixgbe_mac_82598EB &&
7487 tc < MAX_TRAFFIC_CLASS))
7488 return -EINVAL;
7489
7490 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7491 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7492 return -EBUSY;
7493
7494 /* Hardware has to reinitialize queues and interrupts to
7495 * match packet buffer alignment. Unfortunately, the
7496 * hardware is not flexible enough to do this dynamically.
7497 */
7498 if (netif_running(dev))
7499 ixgbe_close(dev);
7500 ixgbe_clear_interrupt_scheme(adapter);
7501
7502 #ifdef CONFIG_IXGBE_DCB
7503 if (tc) {
7504 netdev_set_num_tc(dev, tc);
7505 ixgbe_set_prio_tc_map(adapter);
7506
7507 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7508
7509 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7510 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
7511 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7512 }
7513 } else {
7514 netdev_reset_tc(dev);
7515
7516 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7517 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7518
7519 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7520
7521 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7522 adapter->dcb_cfg.pfc_mode_enable = false;
7523 }
7524
7525 ixgbe_validate_rtr(adapter, tc);
7526
7527 #endif /* CONFIG_IXGBE_DCB */
7528 ixgbe_init_interrupt_scheme(adapter);
7529
7530 if (netif_running(dev))
7531 return ixgbe_open(dev);
7532
7533 return 0;
7534 }
7535
7536 #ifdef CONFIG_PCI_IOV
7537 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7538 {
7539 struct net_device *netdev = adapter->netdev;
7540
7541 rtnl_lock();
7542 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
7543 rtnl_unlock();
7544 }
7545
7546 #endif
7547 void ixgbe_do_reset(struct net_device *netdev)
7548 {
7549 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7550
7551 if (netif_running(netdev))
7552 ixgbe_reinit_locked(adapter);
7553 else
7554 ixgbe_reset(adapter);
7555 }
7556
7557 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7558 netdev_features_t features)
7559 {
7560 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7561
7562 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7563 if (!(features & NETIF_F_RXCSUM))
7564 features &= ~NETIF_F_LRO;
7565
7566 /* Turn off LRO if not RSC capable */
7567 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7568 features &= ~NETIF_F_LRO;
7569
7570 return features;
7571 }
7572
7573 static int ixgbe_set_features(struct net_device *netdev,
7574 netdev_features_t features)
7575 {
7576 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7577 netdev_features_t changed = netdev->features ^ features;
7578 bool need_reset = false;
7579
7580 /* Make sure RSC matches LRO, reset if change */
7581 if (!(features & NETIF_F_LRO)) {
7582 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7583 need_reset = true;
7584 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7585 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7586 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7587 if (adapter->rx_itr_setting == 1 ||
7588 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7589 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7590 need_reset = true;
7591 } else if ((changed ^ features) & NETIF_F_LRO) {
7592 e_info(probe, "rx-usecs set too low, "
7593 "disabling RSC\n");
7594 }
7595 }
7596
7597 /*
7598 * Check if Flow Director n-tuple support was enabled or disabled. If
7599 * the state changed, we need to reset.
7600 */
7601 switch (features & NETIF_F_NTUPLE) {
7602 case NETIF_F_NTUPLE:
7603 /* turn off ATR, enable perfect filters and reset */
7604 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7605 need_reset = true;
7606
7607 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7608 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7609 break;
7610 default:
7611 /* turn off perfect filters, enable ATR and reset */
7612 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7613 need_reset = true;
7614
7615 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7616
7617 /* We cannot enable ATR if SR-IOV is enabled */
7618 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7619 break;
7620
7621 /* We cannot enable ATR if we have 2 or more traffic classes */
7622 if (netdev_get_num_tc(netdev) > 1)
7623 break;
7624
7625 /* We cannot enable ATR if RSS is disabled */
7626 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7627 break;
7628
7629 /* A sample rate of 0 indicates ATR disabled */
7630 if (!adapter->atr_sample_rate)
7631 break;
7632
7633 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7634 break;
7635 }
7636
7637 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7638 ixgbe_vlan_strip_enable(adapter);
7639 else
7640 ixgbe_vlan_strip_disable(adapter);
7641
7642 if (changed & NETIF_F_RXALL)
7643 need_reset = true;
7644
7645 netdev->features = features;
7646 if (need_reset)
7647 ixgbe_do_reset(netdev);
7648
7649 return 0;
7650 }
7651
7652 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7653 struct net_device *dev,
7654 const unsigned char *addr,
7655 u16 flags)
7656 {
7657 /* guarantee we can provide a unique filter for the unicast address */
7658 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
7659 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev))
7660 return -ENOMEM;
7661 }
7662
7663 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
7664 }
7665
7666 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7667 struct nlmsghdr *nlh)
7668 {
7669 struct ixgbe_adapter *adapter = netdev_priv(dev);
7670 struct nlattr *attr, *br_spec;
7671 int rem;
7672
7673 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7674 return -EOPNOTSUPP;
7675
7676 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7677
7678 nla_for_each_nested(attr, br_spec, rem) {
7679 __u16 mode;
7680 u32 reg = 0;
7681
7682 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7683 continue;
7684
7685 mode = nla_get_u16(attr);
7686 if (mode == BRIDGE_MODE_VEPA) {
7687 reg = 0;
7688 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7689 } else if (mode == BRIDGE_MODE_VEB) {
7690 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7691 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7692 } else
7693 return -EINVAL;
7694
7695 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7696
7697 e_info(drv, "enabling bridge mode: %s\n",
7698 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7699 }
7700
7701 return 0;
7702 }
7703
7704 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7705 struct net_device *dev,
7706 u32 filter_mask)
7707 {
7708 struct ixgbe_adapter *adapter = netdev_priv(dev);
7709 u16 mode;
7710
7711 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7712 return 0;
7713
7714 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
7715 mode = BRIDGE_MODE_VEB;
7716 else
7717 mode = BRIDGE_MODE_VEPA;
7718
7719 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7720 }
7721
7722 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
7723 {
7724 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
7725 struct ixgbe_adapter *adapter = netdev_priv(pdev);
7726 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
7727 unsigned int limit;
7728 int pool, err;
7729
7730 /* Hardware has a limited number of available pools. Each VF, and the
7731 * PF require a pool. Check to ensure we don't attempt to use more
7732 * then the available number of pools.
7733 */
7734 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
7735 return ERR_PTR(-EINVAL);
7736
7737 #ifdef CONFIG_RPS
7738 if (vdev->num_rx_queues != vdev->num_tx_queues) {
7739 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
7740 vdev->name);
7741 return ERR_PTR(-EINVAL);
7742 }
7743 #endif
7744 /* Check for hardware restriction on number of rx/tx queues */
7745 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
7746 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
7747 netdev_info(pdev,
7748 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
7749 pdev->name);
7750 return ERR_PTR(-EINVAL);
7751 }
7752
7753 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7754 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
7755 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
7756 return ERR_PTR(-EBUSY);
7757
7758 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL);
7759 if (!fwd_adapter)
7760 return ERR_PTR(-ENOMEM);
7761
7762 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
7763 adapter->num_rx_pools++;
7764 set_bit(pool, &adapter->fwd_bitmask);
7765 limit = find_last_bit(&adapter->fwd_bitmask, 32);
7766
7767 /* Enable VMDq flag so device will be set in VM mode */
7768 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
7769 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
7770 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
7771
7772 /* Force reinit of ring allocation with VMDQ enabled */
7773 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7774 if (err)
7775 goto fwd_add_err;
7776 fwd_adapter->pool = pool;
7777 fwd_adapter->real_adapter = adapter;
7778 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
7779 if (err)
7780 goto fwd_add_err;
7781 netif_tx_start_all_queues(vdev);
7782 return fwd_adapter;
7783 fwd_add_err:
7784 /* unwind counter and free adapter struct */
7785 netdev_info(pdev,
7786 "%s: dfwd hardware acceleration failed\n", vdev->name);
7787 clear_bit(pool, &adapter->fwd_bitmask);
7788 adapter->num_rx_pools--;
7789 kfree(fwd_adapter);
7790 return ERR_PTR(err);
7791 }
7792
7793 static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
7794 {
7795 struct ixgbe_fwd_adapter *fwd_adapter = priv;
7796 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
7797 unsigned int limit;
7798
7799 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
7800 adapter->num_rx_pools--;
7801
7802 limit = find_last_bit(&adapter->fwd_bitmask, 32);
7803 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
7804 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
7805 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7806 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
7807 fwd_adapter->pool, adapter->num_rx_pools,
7808 fwd_adapter->rx_base_queue,
7809 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
7810 adapter->fwd_bitmask);
7811 kfree(fwd_adapter);
7812 }
7813
7814 static const struct net_device_ops ixgbe_netdev_ops = {
7815 .ndo_open = ixgbe_open,
7816 .ndo_stop = ixgbe_close,
7817 .ndo_start_xmit = ixgbe_xmit_frame,
7818 .ndo_select_queue = ixgbe_select_queue,
7819 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7820 .ndo_validate_addr = eth_validate_addr,
7821 .ndo_set_mac_address = ixgbe_set_mac,
7822 .ndo_change_mtu = ixgbe_change_mtu,
7823 .ndo_tx_timeout = ixgbe_tx_timeout,
7824 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7825 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7826 .ndo_do_ioctl = ixgbe_ioctl,
7827 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7828 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7829 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
7830 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7831 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7832 .ndo_get_stats64 = ixgbe_get_stats64,
7833 #ifdef CONFIG_IXGBE_DCB
7834 .ndo_setup_tc = ixgbe_setup_tc,
7835 #endif
7836 #ifdef CONFIG_NET_POLL_CONTROLLER
7837 .ndo_poll_controller = ixgbe_netpoll,
7838 #endif
7839 #ifdef CONFIG_NET_RX_BUSY_POLL
7840 .ndo_busy_poll = ixgbe_low_latency_recv,
7841 #endif
7842 #ifdef IXGBE_FCOE
7843 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7844 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7845 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7846 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7847 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7848 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7849 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7850 #endif /* IXGBE_FCOE */
7851 .ndo_set_features = ixgbe_set_features,
7852 .ndo_fix_features = ixgbe_fix_features,
7853 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7854 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7855 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
7856 .ndo_dfwd_add_station = ixgbe_fwd_add,
7857 .ndo_dfwd_del_station = ixgbe_fwd_del,
7858 };
7859
7860 /**
7861 * ixgbe_enumerate_functions - Get the number of ports this device has
7862 * @adapter: adapter structure
7863 *
7864 * This function enumerates the phsyical functions co-located on a single slot,
7865 * in order to determine how many ports a device has. This is most useful in
7866 * determining the required GT/s of PCIe bandwidth necessary for optimal
7867 * performance.
7868 **/
7869 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7870 {
7871 struct pci_dev *entry, *pdev = adapter->pdev;
7872 int physfns = 0;
7873
7874 /* Some cards can not use the generic count PCIe functions method,
7875 * because they are behind a parent switch, so we hardcode these with
7876 * the correct number of functions.
7877 */
7878 if (ixgbe_pcie_from_parent(&adapter->hw))
7879 physfns = 4;
7880
7881 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
7882 /* don't count virtual functions */
7883 if (entry->is_virtfn)
7884 continue;
7885
7886 /* When the devices on the bus don't all match our device ID,
7887 * we can't reliably determine the correct number of
7888 * functions. This can occur if a function has been direct
7889 * attached to a virtual machine using VT-d, for example. In
7890 * this case, simply return -1 to indicate this.
7891 */
7892 if ((entry->vendor != pdev->vendor) ||
7893 (entry->device != pdev->device))
7894 return -1;
7895
7896 physfns++;
7897 }
7898
7899 return physfns;
7900 }
7901
7902 /**
7903 * ixgbe_wol_supported - Check whether device supports WoL
7904 * @hw: hw specific details
7905 * @device_id: the device ID
7906 * @subdev_id: the subsystem device ID
7907 *
7908 * This function is used by probe and ethtool to determine
7909 * which devices have WoL support
7910 *
7911 **/
7912 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7913 u16 subdevice_id)
7914 {
7915 struct ixgbe_hw *hw = &adapter->hw;
7916 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7917 int is_wol_supported = 0;
7918
7919 switch (device_id) {
7920 case IXGBE_DEV_ID_82599_SFP:
7921 /* Only these subdevices could supports WOL */
7922 switch (subdevice_id) {
7923 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
7924 case IXGBE_SUBDEV_ID_82599_560FLR:
7925 /* only support first port */
7926 if (hw->bus.func != 0)
7927 break;
7928 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
7929 case IXGBE_SUBDEV_ID_82599_SFP:
7930 case IXGBE_SUBDEV_ID_82599_RNDC:
7931 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
7932 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
7933 is_wol_supported = 1;
7934 break;
7935 }
7936 break;
7937 case IXGBE_DEV_ID_82599EN_SFP:
7938 /* Only this subdevice supports WOL */
7939 switch (subdevice_id) {
7940 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
7941 is_wol_supported = 1;
7942 break;
7943 }
7944 break;
7945 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7946 /* All except this subdevice support WOL */
7947 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7948 is_wol_supported = 1;
7949 break;
7950 case IXGBE_DEV_ID_82599_KX4:
7951 is_wol_supported = 1;
7952 break;
7953 case IXGBE_DEV_ID_X540T:
7954 case IXGBE_DEV_ID_X540T1:
7955 /* check eeprom to see if enabled wol */
7956 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7957 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7958 (hw->bus.func == 0))) {
7959 is_wol_supported = 1;
7960 }
7961 break;
7962 }
7963
7964 return is_wol_supported;
7965 }
7966
7967 /**
7968 * ixgbe_probe - Device Initialization Routine
7969 * @pdev: PCI device information struct
7970 * @ent: entry in ixgbe_pci_tbl
7971 *
7972 * Returns 0 on success, negative on failure
7973 *
7974 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7975 * The OS initialization, configuring of the adapter private structure,
7976 * and a hardware reset occur.
7977 **/
7978 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7979 {
7980 struct net_device *netdev;
7981 struct ixgbe_adapter *adapter = NULL;
7982 struct ixgbe_hw *hw;
7983 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7984 static int cards_found;
7985 int i, err, pci_using_dac, expected_gts;
7986 unsigned int indices = MAX_TX_QUEUES;
7987 u8 part_str[IXGBE_PBANUM_LENGTH];
7988 #ifdef IXGBE_FCOE
7989 u16 device_caps;
7990 #endif
7991 u32 eec;
7992
7993 /* Catch broken hardware that put the wrong VF device ID in
7994 * the PCIe SR-IOV capability.
7995 */
7996 if (pdev->is_virtfn) {
7997 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7998 pci_name(pdev), pdev->vendor, pdev->device);
7999 return -EINVAL;
8000 }
8001
8002 err = pci_enable_device_mem(pdev);
8003 if (err)
8004 return err;
8005
8006 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
8007 pci_using_dac = 1;
8008 } else {
8009 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8010 if (err) {
8011 dev_err(&pdev->dev,
8012 "No usable DMA configuration, aborting\n");
8013 goto err_dma;
8014 }
8015 pci_using_dac = 0;
8016 }
8017
8018 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8019 IORESOURCE_MEM), ixgbe_driver_name);
8020 if (err) {
8021 dev_err(&pdev->dev,
8022 "pci_request_selected_regions failed 0x%x\n", err);
8023 goto err_pci_reg;
8024 }
8025
8026 pci_enable_pcie_error_reporting(pdev);
8027
8028 pci_set_master(pdev);
8029 pci_save_state(pdev);
8030
8031 if (ii->mac == ixgbe_mac_82598EB) {
8032 #ifdef CONFIG_IXGBE_DCB
8033 /* 8 TC w/ 4 queues per TC */
8034 indices = 4 * MAX_TRAFFIC_CLASS;
8035 #else
8036 indices = IXGBE_MAX_RSS_INDICES;
8037 #endif
8038 }
8039
8040 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
8041 if (!netdev) {
8042 err = -ENOMEM;
8043 goto err_alloc_etherdev;
8044 }
8045
8046 SET_NETDEV_DEV(netdev, &pdev->dev);
8047
8048 adapter = netdev_priv(netdev);
8049 pci_set_drvdata(pdev, adapter);
8050
8051 adapter->netdev = netdev;
8052 adapter->pdev = pdev;
8053 hw = &adapter->hw;
8054 hw->back = adapter;
8055 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
8056
8057 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8058 pci_resource_len(pdev, 0));
8059 adapter->io_addr = hw->hw_addr;
8060 if (!hw->hw_addr) {
8061 err = -EIO;
8062 goto err_ioremap;
8063 }
8064
8065 netdev->netdev_ops = &ixgbe_netdev_ops;
8066 ixgbe_set_ethtool_ops(netdev);
8067 netdev->watchdog_timeo = 5 * HZ;
8068 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
8069
8070 adapter->bd_number = cards_found;
8071
8072 /* Setup hw api */
8073 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
8074 hw->mac.type = ii->mac;
8075
8076 /* EEPROM */
8077 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
8078 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
8079 if (ixgbe_removed(hw->hw_addr)) {
8080 err = -EIO;
8081 goto err_ioremap;
8082 }
8083 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8084 if (!(eec & (1 << 8)))
8085 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8086
8087 /* PHY */
8088 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
8089 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
8090 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8091 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8092 hw->phy.mdio.mmds = 0;
8093 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8094 hw->phy.mdio.dev = netdev;
8095 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8096 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
8097
8098 ii->get_invariants(hw);
8099
8100 /* setup the private structure */
8101 err = ixgbe_sw_init(adapter);
8102 if (err)
8103 goto err_sw_init;
8104
8105 /* Make it possible the adapter to be woken up via WOL */
8106 switch (adapter->hw.mac.type) {
8107 case ixgbe_mac_82599EB:
8108 case ixgbe_mac_X540:
8109 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
8110 break;
8111 default:
8112 break;
8113 }
8114
8115 /*
8116 * If there is a fan on this device and it has failed log the
8117 * failure.
8118 */
8119 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8120 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8121 if (esdp & IXGBE_ESDP_SDP1)
8122 e_crit(probe, "Fan has stopped, replace the adapter\n");
8123 }
8124
8125 if (allow_unsupported_sfp)
8126 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8127
8128 /* reset_hw fills in the perm_addr as well */
8129 hw->phy.reset_if_overtemp = true;
8130 err = hw->mac.ops.reset_hw(hw);
8131 hw->phy.reset_if_overtemp = false;
8132 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
8133 hw->mac.type == ixgbe_mac_82598EB) {
8134 err = 0;
8135 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
8136 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8137 e_dev_err("Reload the driver after installing a supported module.\n");
8138 goto err_sw_init;
8139 } else if (err) {
8140 e_dev_err("HW Init failed: %d\n", err);
8141 goto err_sw_init;
8142 }
8143
8144 #ifdef CONFIG_PCI_IOV
8145 /* SR-IOV not supported on the 82598 */
8146 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8147 goto skip_sriov;
8148 /* Mailbox */
8149 ixgbe_init_mbx_params_pf(hw);
8150 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
8151 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
8152 ixgbe_enable_sriov(adapter);
8153 skip_sriov:
8154
8155 #endif
8156 netdev->features = NETIF_F_SG |
8157 NETIF_F_IP_CSUM |
8158 NETIF_F_IPV6_CSUM |
8159 NETIF_F_HW_VLAN_CTAG_TX |
8160 NETIF_F_HW_VLAN_CTAG_RX |
8161 NETIF_F_HW_VLAN_CTAG_FILTER |
8162 NETIF_F_TSO |
8163 NETIF_F_TSO6 |
8164 NETIF_F_RXHASH |
8165 NETIF_F_RXCSUM;
8166
8167 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
8168
8169 switch (adapter->hw.mac.type) {
8170 case ixgbe_mac_82599EB:
8171 case ixgbe_mac_X540:
8172 netdev->features |= NETIF_F_SCTP_CSUM;
8173 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8174 NETIF_F_NTUPLE;
8175 break;
8176 default:
8177 break;
8178 }
8179
8180 netdev->hw_features |= NETIF_F_RXALL;
8181
8182 netdev->vlan_features |= NETIF_F_TSO;
8183 netdev->vlan_features |= NETIF_F_TSO6;
8184 netdev->vlan_features |= NETIF_F_IP_CSUM;
8185 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
8186 netdev->vlan_features |= NETIF_F_SG;
8187
8188 netdev->priv_flags |= IFF_UNICAST_FLT;
8189 netdev->priv_flags |= IFF_SUPP_NOFCS;
8190
8191 #ifdef CONFIG_IXGBE_DCB
8192 netdev->dcbnl_ops = &dcbnl_ops;
8193 #endif
8194
8195 #ifdef IXGBE_FCOE
8196 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
8197 unsigned int fcoe_l;
8198
8199 if (hw->mac.ops.get_device_caps) {
8200 hw->mac.ops.get_device_caps(hw, &device_caps);
8201 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8202 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
8203 }
8204
8205
8206 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8207 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
8208
8209 netdev->features |= NETIF_F_FSO |
8210 NETIF_F_FCOE_CRC;
8211
8212 netdev->vlan_features |= NETIF_F_FSO |
8213 NETIF_F_FCOE_CRC |
8214 NETIF_F_FCOE_MTU;
8215 }
8216 #endif /* IXGBE_FCOE */
8217 if (pci_using_dac) {
8218 netdev->features |= NETIF_F_HIGHDMA;
8219 netdev->vlan_features |= NETIF_F_HIGHDMA;
8220 }
8221
8222 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8223 netdev->hw_features |= NETIF_F_LRO;
8224 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
8225 netdev->features |= NETIF_F_LRO;
8226
8227 /* make sure the EEPROM is good */
8228 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
8229 e_dev_err("The EEPROM Checksum Is Not Valid\n");
8230 err = -EIO;
8231 goto err_sw_init;
8232 }
8233
8234 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
8235
8236 if (!is_valid_ether_addr(netdev->dev_addr)) {
8237 e_dev_err("invalid MAC address\n");
8238 err = -EIO;
8239 goto err_sw_init;
8240 }
8241
8242 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr);
8243
8244 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
8245 (unsigned long) adapter);
8246
8247 if (ixgbe_removed(hw->hw_addr)) {
8248 err = -EIO;
8249 goto err_sw_init;
8250 }
8251 INIT_WORK(&adapter->service_task, ixgbe_service_task);
8252 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
8253 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
8254
8255 err = ixgbe_init_interrupt_scheme(adapter);
8256 if (err)
8257 goto err_sw_init;
8258
8259 /* WOL not supported for all devices */
8260 adapter->wol = 0;
8261 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
8262 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
8263 pdev->subsystem_device);
8264 if (hw->wol_enabled)
8265 adapter->wol = IXGBE_WUFC_MAG;
8266
8267 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8268
8269 /* save off EEPROM version number */
8270 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8271 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8272
8273 /* pick up the PCI bus settings for reporting later */
8274 hw->mac.ops.get_bus_info(hw);
8275 if (ixgbe_pcie_from_parent(hw))
8276 ixgbe_get_parent_bus_info(adapter);
8277
8278 /* calculate the expected PCIe bandwidth required for optimal
8279 * performance. Note that some older parts will never have enough
8280 * bandwidth due to being older generation PCIe parts. We clamp these
8281 * parts to ensure no warning is displayed if it can't be fixed.
8282 */
8283 switch (hw->mac.type) {
8284 case ixgbe_mac_82598EB:
8285 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8286 break;
8287 default:
8288 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8289 break;
8290 }
8291
8292 /* don't check link if we failed to enumerate functions */
8293 if (expected_gts > 0)
8294 ixgbe_check_minimum_link(adapter, expected_gts);
8295
8296 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
8297 if (err)
8298 strlcpy(part_str, "Unknown", sizeof(part_str));
8299 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8300 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8301 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
8302 part_str);
8303 else
8304 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8305 hw->mac.type, hw->phy.type, part_str);
8306
8307 e_dev_info("%pM\n", netdev->dev_addr);
8308
8309 /* reset the hardware with the new settings */
8310 err = hw->mac.ops.start_hw(hw);
8311 if (err == IXGBE_ERR_EEPROM_VERSION) {
8312 /* We are running on a pre-production device, log a warning */
8313 e_dev_warn("This device is a pre-production adapter/LOM. "
8314 "Please be aware there may be issues associated "
8315 "with your hardware. If you are experiencing "
8316 "problems please contact your Intel or hardware "
8317 "representative who provided you with this "
8318 "hardware.\n");
8319 }
8320 strcpy(netdev->name, "eth%d");
8321 err = register_netdev(netdev);
8322 if (err)
8323 goto err_register;
8324
8325 /* power down the optics for 82599 SFP+ fiber */
8326 if (hw->mac.ops.disable_tx_laser)
8327 hw->mac.ops.disable_tx_laser(hw);
8328
8329 /* carrier off reporting is important to ethtool even BEFORE open */
8330 netif_carrier_off(netdev);
8331
8332 #ifdef CONFIG_IXGBE_DCA
8333 if (dca_add_requester(&pdev->dev) == 0) {
8334 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
8335 ixgbe_setup_dca(adapter);
8336 }
8337 #endif
8338 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
8339 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
8340 for (i = 0; i < adapter->num_vfs; i++)
8341 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8342 }
8343
8344 /* firmware requires driver version to be 0xFFFFFFFF
8345 * since os does not support feature
8346 */
8347 if (hw->mac.ops.set_fw_drv_ver)
8348 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8349 0xFF);
8350
8351 /* add san mac addr to netdev */
8352 ixgbe_add_sanmac_netdev(netdev);
8353
8354 e_dev_info("%s\n", ixgbe_default_device_descr);
8355 cards_found++;
8356
8357 #ifdef CONFIG_IXGBE_HWMON
8358 if (ixgbe_sysfs_init(adapter))
8359 e_err(probe, "failed to allocate sysfs resources\n");
8360 #endif /* CONFIG_IXGBE_HWMON */
8361
8362 ixgbe_dbg_adapter_init(adapter);
8363
8364 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
8365 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
8366 hw->mac.ops.setup_link(hw,
8367 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8368 true);
8369
8370 return 0;
8371
8372 err_register:
8373 ixgbe_release_hw_control(adapter);
8374 ixgbe_clear_interrupt_scheme(adapter);
8375 err_sw_init:
8376 ixgbe_disable_sriov(adapter);
8377 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
8378 iounmap(adapter->io_addr);
8379 kfree(adapter->mac_table);
8380 err_ioremap:
8381 free_netdev(netdev);
8382 err_alloc_etherdev:
8383 pci_release_selected_regions(pdev,
8384 pci_select_bars(pdev, IORESOURCE_MEM));
8385 err_pci_reg:
8386 err_dma:
8387 if (!adapter || !test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8388 pci_disable_device(pdev);
8389 return err;
8390 }
8391
8392 /**
8393 * ixgbe_remove - Device Removal Routine
8394 * @pdev: PCI device information struct
8395 *
8396 * ixgbe_remove is called by the PCI subsystem to alert the driver
8397 * that it should release a PCI device. The could be caused by a
8398 * Hot-Plug event, or because the driver is going to be removed from
8399 * memory.
8400 **/
8401 static void ixgbe_remove(struct pci_dev *pdev)
8402 {
8403 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8404 struct net_device *netdev = adapter->netdev;
8405
8406 ixgbe_dbg_adapter_exit(adapter);
8407
8408 set_bit(__IXGBE_REMOVING, &adapter->state);
8409 cancel_work_sync(&adapter->service_task);
8410
8411
8412 #ifdef CONFIG_IXGBE_DCA
8413 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8414 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8415 dca_remove_requester(&pdev->dev);
8416 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8417 }
8418
8419 #endif
8420 #ifdef CONFIG_IXGBE_HWMON
8421 ixgbe_sysfs_exit(adapter);
8422 #endif /* CONFIG_IXGBE_HWMON */
8423
8424 /* remove the added san mac */
8425 ixgbe_del_sanmac_netdev(netdev);
8426
8427 if (netdev->reg_state == NETREG_REGISTERED)
8428 unregister_netdev(netdev);
8429
8430 #ifdef CONFIG_PCI_IOV
8431 /*
8432 * Only disable SR-IOV on unload if the user specified the now
8433 * deprecated max_vfs module parameter.
8434 */
8435 if (max_vfs)
8436 ixgbe_disable_sriov(adapter);
8437 #endif
8438 ixgbe_clear_interrupt_scheme(adapter);
8439
8440 ixgbe_release_hw_control(adapter);
8441
8442 #ifdef CONFIG_DCB
8443 kfree(adapter->ixgbe_ieee_pfc);
8444 kfree(adapter->ixgbe_ieee_ets);
8445
8446 #endif
8447 iounmap(adapter->io_addr);
8448 pci_release_selected_regions(pdev, pci_select_bars(pdev,
8449 IORESOURCE_MEM));
8450
8451 e_dev_info("complete\n");
8452
8453 kfree(adapter->mac_table);
8454 free_netdev(netdev);
8455
8456 pci_disable_pcie_error_reporting(pdev);
8457
8458 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8459 pci_disable_device(pdev);
8460 }
8461
8462 /**
8463 * ixgbe_io_error_detected - called when PCI error is detected
8464 * @pdev: Pointer to PCI device
8465 * @state: The current pci connection state
8466 *
8467 * This function is called after a PCI bus error affecting
8468 * this device has been detected.
8469 */
8470 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
8471 pci_channel_state_t state)
8472 {
8473 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8474 struct net_device *netdev = adapter->netdev;
8475
8476 #ifdef CONFIG_PCI_IOV
8477 struct ixgbe_hw *hw = &adapter->hw;
8478 struct pci_dev *bdev, *vfdev;
8479 u32 dw0, dw1, dw2, dw3;
8480 int vf, pos;
8481 u16 req_id, pf_func;
8482
8483 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8484 adapter->num_vfs == 0)
8485 goto skip_bad_vf_detection;
8486
8487 bdev = pdev->bus->self;
8488 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
8489 bdev = bdev->bus->self;
8490
8491 if (!bdev)
8492 goto skip_bad_vf_detection;
8493
8494 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8495 if (!pos)
8496 goto skip_bad_vf_detection;
8497
8498 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
8499 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
8500 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
8501 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
8502 if (ixgbe_removed(hw->hw_addr))
8503 goto skip_bad_vf_detection;
8504
8505 req_id = dw1 >> 16;
8506 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8507 if (!(req_id & 0x0080))
8508 goto skip_bad_vf_detection;
8509
8510 pf_func = req_id & 0x01;
8511 if ((pf_func & 1) == (pdev->devfn & 1)) {
8512 unsigned int device_id;
8513
8514 vf = (req_id & 0x7F) >> 1;
8515 e_dev_err("VF %d has caused a PCIe error\n", vf);
8516 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8517 "%8.8x\tdw3: %8.8x\n",
8518 dw0, dw1, dw2, dw3);
8519 switch (adapter->hw.mac.type) {
8520 case ixgbe_mac_82599EB:
8521 device_id = IXGBE_82599_VF_DEVICE_ID;
8522 break;
8523 case ixgbe_mac_X540:
8524 device_id = IXGBE_X540_VF_DEVICE_ID;
8525 break;
8526 default:
8527 device_id = 0;
8528 break;
8529 }
8530
8531 /* Find the pci device of the offending VF */
8532 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
8533 while (vfdev) {
8534 if (vfdev->devfn == (req_id & 0xFF))
8535 break;
8536 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
8537 device_id, vfdev);
8538 }
8539 /*
8540 * There's a slim chance the VF could have been hot plugged,
8541 * so if it is no longer present we don't need to issue the
8542 * VFLR. Just clean up the AER in that case.
8543 */
8544 if (vfdev) {
8545 e_dev_err("Issuing VFLR to VF %d\n", vf);
8546 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
8547 /* Free device reference count */
8548 pci_dev_put(vfdev);
8549 }
8550
8551 pci_cleanup_aer_uncorrect_error_status(pdev);
8552 }
8553
8554 /*
8555 * Even though the error may have occurred on the other port
8556 * we still need to increment the vf error reference count for
8557 * both ports because the I/O resume function will be called
8558 * for both of them.
8559 */
8560 adapter->vferr_refcount++;
8561
8562 return PCI_ERS_RESULT_RECOVERED;
8563
8564 skip_bad_vf_detection:
8565 #endif /* CONFIG_PCI_IOV */
8566 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
8567 return PCI_ERS_RESULT_DISCONNECT;
8568
8569 rtnl_lock();
8570 netif_device_detach(netdev);
8571
8572 if (state == pci_channel_io_perm_failure) {
8573 rtnl_unlock();
8574 return PCI_ERS_RESULT_DISCONNECT;
8575 }
8576
8577 if (netif_running(netdev))
8578 ixgbe_down(adapter);
8579
8580 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8581 pci_disable_device(pdev);
8582 rtnl_unlock();
8583
8584 /* Request a slot reset. */
8585 return PCI_ERS_RESULT_NEED_RESET;
8586 }
8587
8588 /**
8589 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8590 * @pdev: Pointer to PCI device
8591 *
8592 * Restart the card from scratch, as if from a cold-boot.
8593 */
8594 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8595 {
8596 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8597 pci_ers_result_t result;
8598 int err;
8599
8600 if (pci_enable_device_mem(pdev)) {
8601 e_err(probe, "Cannot re-enable PCI device after reset.\n");
8602 result = PCI_ERS_RESULT_DISCONNECT;
8603 } else {
8604 smp_mb__before_atomic();
8605 clear_bit(__IXGBE_DISABLED, &adapter->state);
8606 adapter->hw.hw_addr = adapter->io_addr;
8607 pci_set_master(pdev);
8608 pci_restore_state(pdev);
8609 pci_save_state(pdev);
8610
8611 pci_wake_from_d3(pdev, false);
8612
8613 ixgbe_reset(adapter);
8614 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
8615 result = PCI_ERS_RESULT_RECOVERED;
8616 }
8617
8618 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8619 if (err) {
8620 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8621 "failed 0x%0x\n", err);
8622 /* non-fatal, continue */
8623 }
8624
8625 return result;
8626 }
8627
8628 /**
8629 * ixgbe_io_resume - called when traffic can start flowing again.
8630 * @pdev: Pointer to PCI device
8631 *
8632 * This callback is called when the error recovery driver tells us that
8633 * its OK to resume normal operation.
8634 */
8635 static void ixgbe_io_resume(struct pci_dev *pdev)
8636 {
8637 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8638 struct net_device *netdev = adapter->netdev;
8639
8640 #ifdef CONFIG_PCI_IOV
8641 if (adapter->vferr_refcount) {
8642 e_info(drv, "Resuming after VF err\n");
8643 adapter->vferr_refcount--;
8644 return;
8645 }
8646
8647 #endif
8648 if (netif_running(netdev))
8649 ixgbe_up(adapter);
8650
8651 netif_device_attach(netdev);
8652 }
8653
8654 static const struct pci_error_handlers ixgbe_err_handler = {
8655 .error_detected = ixgbe_io_error_detected,
8656 .slot_reset = ixgbe_io_slot_reset,
8657 .resume = ixgbe_io_resume,
8658 };
8659
8660 static struct pci_driver ixgbe_driver = {
8661 .name = ixgbe_driver_name,
8662 .id_table = ixgbe_pci_tbl,
8663 .probe = ixgbe_probe,
8664 .remove = ixgbe_remove,
8665 #ifdef CONFIG_PM
8666 .suspend = ixgbe_suspend,
8667 .resume = ixgbe_resume,
8668 #endif
8669 .shutdown = ixgbe_shutdown,
8670 .sriov_configure = ixgbe_pci_sriov_configure,
8671 .err_handler = &ixgbe_err_handler
8672 };
8673
8674 /**
8675 * ixgbe_init_module - Driver Registration Routine
8676 *
8677 * ixgbe_init_module is the first routine called when the driver is
8678 * loaded. All it does is register with the PCI subsystem.
8679 **/
8680 static int __init ixgbe_init_module(void)
8681 {
8682 int ret;
8683 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
8684 pr_info("%s\n", ixgbe_copyright);
8685
8686 ixgbe_dbg_init();
8687
8688 ret = pci_register_driver(&ixgbe_driver);
8689 if (ret) {
8690 ixgbe_dbg_exit();
8691 return ret;
8692 }
8693
8694 #ifdef CONFIG_IXGBE_DCA
8695 dca_register_notify(&dca_notifier);
8696 #endif
8697
8698 return 0;
8699 }
8700
8701 module_init(ixgbe_init_module);
8702
8703 /**
8704 * ixgbe_exit_module - Driver Exit Cleanup Routine
8705 *
8706 * ixgbe_exit_module is called just before the driver is removed
8707 * from memory.
8708 **/
8709 static void __exit ixgbe_exit_module(void)
8710 {
8711 #ifdef CONFIG_IXGBE_DCA
8712 dca_unregister_notify(&dca_notifier);
8713 #endif
8714 pci_unregister_driver(&ixgbe_driver);
8715
8716 ixgbe_dbg_exit();
8717
8718 rcu_barrier(); /* Wait for completion of call_rcu()'s */
8719 }
8720
8721 #ifdef CONFIG_IXGBE_DCA
8722 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
8723 void *p)
8724 {
8725 int ret_val;
8726
8727 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
8728 __ixgbe_notify_dca);
8729
8730 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8731 }
8732
8733 #endif /* CONFIG_IXGBE_DCA */
8734
8735 module_exit(ixgbe_exit_module);
8736
8737 /* ixgbe_main.c */
Linux kernel - Deliverables
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