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[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2015 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/types.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/vmalloc.h>
34 #include <linux/string.h>
35 #include <linux/in.h>
36 #include <linux/interrupt.h>
37 #include <linux/ip.h>
38 #include <linux/tcp.h>
39 #include <linux/sctp.h>
40 #include <linux/pkt_sched.h>
41 #include <linux/ipv6.h>
42 #include <linux/slab.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/etherdevice.h>
46 #include <linux/ethtool.h>
47 #include <linux/if.h>
48 #include <linux/if_vlan.h>
49 #include <linux/if_macvlan.h>
50 #include <linux/if_bridge.h>
51 #include <linux/prefetch.h>
52 #include <scsi/fc/fc_fcoe.h>
53 #include <net/vxlan.h>
54
55 #ifdef CONFIG_OF
56 #include <linux/of_net.h>
57 #endif
58
59 #ifdef CONFIG_SPARC
60 #include <asm/idprom.h>
61 #include <asm/prom.h>
62 #endif
63
64 #include "ixgbe.h"
65 #include "ixgbe_common.h"
66 #include "ixgbe_dcb_82599.h"
67 #include "ixgbe_sriov.h"
68 #ifdef CONFIG_IXGBE_VXLAN
69 #include <net/vxlan.h>
70 #endif
71
72 char ixgbe_driver_name[] = "ixgbe";
73 static const char ixgbe_driver_string[] =
74 "Intel(R) 10 Gigabit PCI Express Network Driver";
75 #ifdef IXGBE_FCOE
76 char ixgbe_default_device_descr[] =
77 "Intel(R) 10 Gigabit Network Connection";
78 #else
79 static char ixgbe_default_device_descr[] =
80 "Intel(R) 10 Gigabit Network Connection";
81 #endif
82 #define DRV_VERSION "4.0.1-k"
83 const char ixgbe_driver_version[] = DRV_VERSION;
84 static const char ixgbe_copyright[] =
85 "Copyright (c) 1999-2015 Intel Corporation.";
86
87 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
88
89 static const struct ixgbe_info *ixgbe_info_tbl[] = {
90 [board_82598] = &ixgbe_82598_info,
91 [board_82599] = &ixgbe_82599_info,
92 [board_X540] = &ixgbe_X540_info,
93 [board_X550] = &ixgbe_X550_info,
94 [board_X550EM_x] = &ixgbe_X550EM_x_info,
95 };
96
97 /* ixgbe_pci_tbl - PCI Device ID Table
98 *
99 * Wildcard entries (PCI_ANY_ID) should come last
100 * Last entry must be all 0s
101 *
102 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
103 * Class, Class Mask, private data (not used) }
104 */
105 static const struct pci_device_id ixgbe_pci_tbl[] = {
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
140 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
141 /* required last entry */
142 {0, }
143 };
144 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
145
146 #ifdef CONFIG_IXGBE_DCA
147 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
148 void *p);
149 static struct notifier_block dca_notifier = {
150 .notifier_call = ixgbe_notify_dca,
151 .next = NULL,
152 .priority = 0
153 };
154 #endif
155
156 #ifdef CONFIG_PCI_IOV
157 static unsigned int max_vfs;
158 module_param(max_vfs, uint, 0);
159 MODULE_PARM_DESC(max_vfs,
160 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
161 #endif /* CONFIG_PCI_IOV */
162
163 static unsigned int allow_unsupported_sfp;
164 module_param(allow_unsupported_sfp, uint, 0);
165 MODULE_PARM_DESC(allow_unsupported_sfp,
166 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
167
168 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
169 static int debug = -1;
170 module_param(debug, int, 0);
171 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
172
173 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
174 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
175 MODULE_LICENSE("GPL");
176 MODULE_VERSION(DRV_VERSION);
177
178 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
179
180 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
181 u32 reg, u16 *value)
182 {
183 struct pci_dev *parent_dev;
184 struct pci_bus *parent_bus;
185
186 parent_bus = adapter->pdev->bus->parent;
187 if (!parent_bus)
188 return -1;
189
190 parent_dev = parent_bus->self;
191 if (!parent_dev)
192 return -1;
193
194 if (!pci_is_pcie(parent_dev))
195 return -1;
196
197 pcie_capability_read_word(parent_dev, reg, value);
198 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
199 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
200 return -1;
201 return 0;
202 }
203
204 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
205 {
206 struct ixgbe_hw *hw = &adapter->hw;
207 u16 link_status = 0;
208 int err;
209
210 hw->bus.type = ixgbe_bus_type_pci_express;
211
212 /* Get the negotiated link width and speed from PCI config space of the
213 * parent, as this device is behind a switch
214 */
215 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
216
217 /* assume caller will handle error case */
218 if (err)
219 return err;
220
221 hw->bus.width = ixgbe_convert_bus_width(link_status);
222 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
223
224 return 0;
225 }
226
227 /**
228 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
229 * @hw: hw specific details
230 *
231 * This function is used by probe to determine whether a device's PCI-Express
232 * bandwidth details should be gathered from the parent bus instead of from the
233 * device. Used to ensure that various locations all have the correct device ID
234 * checks.
235 */
236 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
237 {
238 switch (hw->device_id) {
239 case IXGBE_DEV_ID_82599_SFP_SF_QP:
240 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
241 return true;
242 default:
243 return false;
244 }
245 }
246
247 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
248 int expected_gts)
249 {
250 struct ixgbe_hw *hw = &adapter->hw;
251 int max_gts = 0;
252 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
253 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
254 struct pci_dev *pdev;
255
256 /* Some devices are not connected over PCIe and thus do not negotiate
257 * speed. These devices do not have valid bus info, and thus any report
258 * we generate may not be correct.
259 */
260 if (hw->bus.type == ixgbe_bus_type_internal)
261 return;
262
263 /* determine whether to use the parent device */
264 if (ixgbe_pcie_from_parent(&adapter->hw))
265 pdev = adapter->pdev->bus->parent->self;
266 else
267 pdev = adapter->pdev;
268
269 if (pcie_get_minimum_link(pdev, &speed, &width) ||
270 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
271 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
272 return;
273 }
274
275 switch (speed) {
276 case PCIE_SPEED_2_5GT:
277 /* 8b/10b encoding reduces max throughput by 20% */
278 max_gts = 2 * width;
279 break;
280 case PCIE_SPEED_5_0GT:
281 /* 8b/10b encoding reduces max throughput by 20% */
282 max_gts = 4 * width;
283 break;
284 case PCIE_SPEED_8_0GT:
285 /* 128b/130b encoding reduces throughput by less than 2% */
286 max_gts = 8 * width;
287 break;
288 default:
289 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
290 return;
291 }
292
293 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
294 max_gts);
295 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
296 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
297 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
298 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
299 "Unknown"),
300 width,
301 (speed == PCIE_SPEED_2_5GT ? "20%" :
302 speed == PCIE_SPEED_5_0GT ? "20%" :
303 speed == PCIE_SPEED_8_0GT ? "<2%" :
304 "Unknown"));
305
306 if (max_gts < expected_gts) {
307 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
308 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
309 expected_gts);
310 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
311 }
312 }
313
314 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
315 {
316 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
317 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
318 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
319 schedule_work(&adapter->service_task);
320 }
321
322 static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
323 {
324 struct ixgbe_adapter *adapter = hw->back;
325
326 if (!hw->hw_addr)
327 return;
328 hw->hw_addr = NULL;
329 e_dev_err("Adapter removed\n");
330 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
331 ixgbe_service_event_schedule(adapter);
332 }
333
334 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
335 {
336 u32 value;
337
338 /* The following check not only optimizes a bit by not
339 * performing a read on the status register when the
340 * register just read was a status register read that
341 * returned IXGBE_FAILED_READ_REG. It also blocks any
342 * potential recursion.
343 */
344 if (reg == IXGBE_STATUS) {
345 ixgbe_remove_adapter(hw);
346 return;
347 }
348 value = ixgbe_read_reg(hw, IXGBE_STATUS);
349 if (value == IXGBE_FAILED_READ_REG)
350 ixgbe_remove_adapter(hw);
351 }
352
353 /**
354 * ixgbe_read_reg - Read from device register
355 * @hw: hw specific details
356 * @reg: offset of register to read
357 *
358 * Returns : value read or IXGBE_FAILED_READ_REG if removed
359 *
360 * This function is used to read device registers. It checks for device
361 * removal by confirming any read that returns all ones by checking the
362 * status register value for all ones. This function avoids reading from
363 * the hardware if a removal was previously detected in which case it
364 * returns IXGBE_FAILED_READ_REG (all ones).
365 */
366 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
367 {
368 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
369 u32 value;
370
371 if (ixgbe_removed(reg_addr))
372 return IXGBE_FAILED_READ_REG;
373 value = readl(reg_addr + reg);
374 if (unlikely(value == IXGBE_FAILED_READ_REG))
375 ixgbe_check_remove(hw, reg);
376 return value;
377 }
378
379 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
380 {
381 u16 value;
382
383 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
384 if (value == IXGBE_FAILED_READ_CFG_WORD) {
385 ixgbe_remove_adapter(hw);
386 return true;
387 }
388 return false;
389 }
390
391 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
392 {
393 struct ixgbe_adapter *adapter = hw->back;
394 u16 value;
395
396 if (ixgbe_removed(hw->hw_addr))
397 return IXGBE_FAILED_READ_CFG_WORD;
398 pci_read_config_word(adapter->pdev, reg, &value);
399 if (value == IXGBE_FAILED_READ_CFG_WORD &&
400 ixgbe_check_cfg_remove(hw, adapter->pdev))
401 return IXGBE_FAILED_READ_CFG_WORD;
402 return value;
403 }
404
405 #ifdef CONFIG_PCI_IOV
406 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
407 {
408 struct ixgbe_adapter *adapter = hw->back;
409 u32 value;
410
411 if (ixgbe_removed(hw->hw_addr))
412 return IXGBE_FAILED_READ_CFG_DWORD;
413 pci_read_config_dword(adapter->pdev, reg, &value);
414 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
415 ixgbe_check_cfg_remove(hw, adapter->pdev))
416 return IXGBE_FAILED_READ_CFG_DWORD;
417 return value;
418 }
419 #endif /* CONFIG_PCI_IOV */
420
421 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
422 {
423 struct ixgbe_adapter *adapter = hw->back;
424
425 if (ixgbe_removed(hw->hw_addr))
426 return;
427 pci_write_config_word(adapter->pdev, reg, value);
428 }
429
430 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
431 {
432 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
433
434 /* flush memory to make sure state is correct before next watchdog */
435 smp_mb__before_atomic();
436 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
437 }
438
439 struct ixgbe_reg_info {
440 u32 ofs;
441 char *name;
442 };
443
444 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
445
446 /* General Registers */
447 {IXGBE_CTRL, "CTRL"},
448 {IXGBE_STATUS, "STATUS"},
449 {IXGBE_CTRL_EXT, "CTRL_EXT"},
450
451 /* Interrupt Registers */
452 {IXGBE_EICR, "EICR"},
453
454 /* RX Registers */
455 {IXGBE_SRRCTL(0), "SRRCTL"},
456 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
457 {IXGBE_RDLEN(0), "RDLEN"},
458 {IXGBE_RDH(0), "RDH"},
459 {IXGBE_RDT(0), "RDT"},
460 {IXGBE_RXDCTL(0), "RXDCTL"},
461 {IXGBE_RDBAL(0), "RDBAL"},
462 {IXGBE_RDBAH(0), "RDBAH"},
463
464 /* TX Registers */
465 {IXGBE_TDBAL(0), "TDBAL"},
466 {IXGBE_TDBAH(0), "TDBAH"},
467 {IXGBE_TDLEN(0), "TDLEN"},
468 {IXGBE_TDH(0), "TDH"},
469 {IXGBE_TDT(0), "TDT"},
470 {IXGBE_TXDCTL(0), "TXDCTL"},
471
472 /* List Terminator */
473 { .name = NULL }
474 };
475
476
477 /*
478 * ixgbe_regdump - register printout routine
479 */
480 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
481 {
482 int i = 0, j = 0;
483 char rname[16];
484 u32 regs[64];
485
486 switch (reginfo->ofs) {
487 case IXGBE_SRRCTL(0):
488 for (i = 0; i < 64; i++)
489 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
490 break;
491 case IXGBE_DCA_RXCTRL(0):
492 for (i = 0; i < 64; i++)
493 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
494 break;
495 case IXGBE_RDLEN(0):
496 for (i = 0; i < 64; i++)
497 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
498 break;
499 case IXGBE_RDH(0):
500 for (i = 0; i < 64; i++)
501 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
502 break;
503 case IXGBE_RDT(0):
504 for (i = 0; i < 64; i++)
505 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
506 break;
507 case IXGBE_RXDCTL(0):
508 for (i = 0; i < 64; i++)
509 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
510 break;
511 case IXGBE_RDBAL(0):
512 for (i = 0; i < 64; i++)
513 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
514 break;
515 case IXGBE_RDBAH(0):
516 for (i = 0; i < 64; i++)
517 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
518 break;
519 case IXGBE_TDBAL(0):
520 for (i = 0; i < 64; i++)
521 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
522 break;
523 case IXGBE_TDBAH(0):
524 for (i = 0; i < 64; i++)
525 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
526 break;
527 case IXGBE_TDLEN(0):
528 for (i = 0; i < 64; i++)
529 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
530 break;
531 case IXGBE_TDH(0):
532 for (i = 0; i < 64; i++)
533 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
534 break;
535 case IXGBE_TDT(0):
536 for (i = 0; i < 64; i++)
537 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
538 break;
539 case IXGBE_TXDCTL(0):
540 for (i = 0; i < 64; i++)
541 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
542 break;
543 default:
544 pr_info("%-15s %08x\n", reginfo->name,
545 IXGBE_READ_REG(hw, reginfo->ofs));
546 return;
547 }
548
549 for (i = 0; i < 8; i++) {
550 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
551 pr_err("%-15s", rname);
552 for (j = 0; j < 8; j++)
553 pr_cont(" %08x", regs[i*8+j]);
554 pr_cont("\n");
555 }
556
557 }
558
559 /*
560 * ixgbe_dump - Print registers, tx-rings and rx-rings
561 */
562 static void ixgbe_dump(struct ixgbe_adapter *adapter)
563 {
564 struct net_device *netdev = adapter->netdev;
565 struct ixgbe_hw *hw = &adapter->hw;
566 struct ixgbe_reg_info *reginfo;
567 int n = 0;
568 struct ixgbe_ring *tx_ring;
569 struct ixgbe_tx_buffer *tx_buffer;
570 union ixgbe_adv_tx_desc *tx_desc;
571 struct my_u0 { u64 a; u64 b; } *u0;
572 struct ixgbe_ring *rx_ring;
573 union ixgbe_adv_rx_desc *rx_desc;
574 struct ixgbe_rx_buffer *rx_buffer_info;
575 u32 staterr;
576 int i = 0;
577
578 if (!netif_msg_hw(adapter))
579 return;
580
581 /* Print netdevice Info */
582 if (netdev) {
583 dev_info(&adapter->pdev->dev, "Net device Info\n");
584 pr_info("Device Name state "
585 "trans_start last_rx\n");
586 pr_info("%-15s %016lX %016lX %016lX\n",
587 netdev->name,
588 netdev->state,
589 netdev->trans_start,
590 netdev->last_rx);
591 }
592
593 /* Print Registers */
594 dev_info(&adapter->pdev->dev, "Register Dump\n");
595 pr_info(" Register Name Value\n");
596 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
597 reginfo->name; reginfo++) {
598 ixgbe_regdump(hw, reginfo);
599 }
600
601 /* Print TX Ring Summary */
602 if (!netdev || !netif_running(netdev))
603 return;
604
605 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
606 pr_info(" %s %s %s %s\n",
607 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
608 "leng", "ntw", "timestamp");
609 for (n = 0; n < adapter->num_tx_queues; n++) {
610 tx_ring = adapter->tx_ring[n];
611 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
612 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
613 n, tx_ring->next_to_use, tx_ring->next_to_clean,
614 (u64)dma_unmap_addr(tx_buffer, dma),
615 dma_unmap_len(tx_buffer, len),
616 tx_buffer->next_to_watch,
617 (u64)tx_buffer->time_stamp);
618 }
619
620 /* Print TX Rings */
621 if (!netif_msg_tx_done(adapter))
622 goto rx_ring_summary;
623
624 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
625
626 /* Transmit Descriptor Formats
627 *
628 * 82598 Advanced Transmit Descriptor
629 * +--------------------------------------------------------------+
630 * 0 | Buffer Address [63:0] |
631 * +--------------------------------------------------------------+
632 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
633 * +--------------------------------------------------------------+
634 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
635 *
636 * 82598 Advanced Transmit Descriptor (Write-Back Format)
637 * +--------------------------------------------------------------+
638 * 0 | RSV [63:0] |
639 * +--------------------------------------------------------------+
640 * 8 | RSV | STA | NXTSEQ |
641 * +--------------------------------------------------------------+
642 * 63 36 35 32 31 0
643 *
644 * 82599+ Advanced Transmit Descriptor
645 * +--------------------------------------------------------------+
646 * 0 | Buffer Address [63:0] |
647 * +--------------------------------------------------------------+
648 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
649 * +--------------------------------------------------------------+
650 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
651 *
652 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
653 * +--------------------------------------------------------------+
654 * 0 | RSV [63:0] |
655 * +--------------------------------------------------------------+
656 * 8 | RSV | STA | RSV |
657 * +--------------------------------------------------------------+
658 * 63 36 35 32 31 0
659 */
660
661 for (n = 0; n < adapter->num_tx_queues; n++) {
662 tx_ring = adapter->tx_ring[n];
663 pr_info("------------------------------------\n");
664 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
665 pr_info("------------------------------------\n");
666 pr_info("%s%s %s %s %s %s\n",
667 "T [desc] [address 63:0 ] ",
668 "[PlPOIdStDDt Ln] [bi->dma ] ",
669 "leng", "ntw", "timestamp", "bi->skb");
670
671 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
672 tx_desc = IXGBE_TX_DESC(tx_ring, i);
673 tx_buffer = &tx_ring->tx_buffer_info[i];
674 u0 = (struct my_u0 *)tx_desc;
675 if (dma_unmap_len(tx_buffer, len) > 0) {
676 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
677 i,
678 le64_to_cpu(u0->a),
679 le64_to_cpu(u0->b),
680 (u64)dma_unmap_addr(tx_buffer, dma),
681 dma_unmap_len(tx_buffer, len),
682 tx_buffer->next_to_watch,
683 (u64)tx_buffer->time_stamp,
684 tx_buffer->skb);
685 if (i == tx_ring->next_to_use &&
686 i == tx_ring->next_to_clean)
687 pr_cont(" NTC/U\n");
688 else if (i == tx_ring->next_to_use)
689 pr_cont(" NTU\n");
690 else if (i == tx_ring->next_to_clean)
691 pr_cont(" NTC\n");
692 else
693 pr_cont("\n");
694
695 if (netif_msg_pktdata(adapter) &&
696 tx_buffer->skb)
697 print_hex_dump(KERN_INFO, "",
698 DUMP_PREFIX_ADDRESS, 16, 1,
699 tx_buffer->skb->data,
700 dma_unmap_len(tx_buffer, len),
701 true);
702 }
703 }
704 }
705
706 /* Print RX Rings Summary */
707 rx_ring_summary:
708 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
709 pr_info("Queue [NTU] [NTC]\n");
710 for (n = 0; n < adapter->num_rx_queues; n++) {
711 rx_ring = adapter->rx_ring[n];
712 pr_info("%5d %5X %5X\n",
713 n, rx_ring->next_to_use, rx_ring->next_to_clean);
714 }
715
716 /* Print RX Rings */
717 if (!netif_msg_rx_status(adapter))
718 return;
719
720 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
721
722 /* Receive Descriptor Formats
723 *
724 * 82598 Advanced Receive Descriptor (Read) Format
725 * 63 1 0
726 * +-----------------------------------------------------+
727 * 0 | Packet Buffer Address [63:1] |A0/NSE|
728 * +----------------------------------------------+------+
729 * 8 | Header Buffer Address [63:1] | DD |
730 * +-----------------------------------------------------+
731 *
732 *
733 * 82598 Advanced Receive Descriptor (Write-Back) Format
734 *
735 * 63 48 47 32 31 30 21 20 16 15 4 3 0
736 * +------------------------------------------------------+
737 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
738 * | Packet | IP | | | | Type | Type |
739 * | Checksum | Ident | | | | | |
740 * +------------------------------------------------------+
741 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
742 * +------------------------------------------------------+
743 * 63 48 47 32 31 20 19 0
744 *
745 * 82599+ Advanced Receive Descriptor (Read) Format
746 * 63 1 0
747 * +-----------------------------------------------------+
748 * 0 | Packet Buffer Address [63:1] |A0/NSE|
749 * +----------------------------------------------+------+
750 * 8 | Header Buffer Address [63:1] | DD |
751 * +-----------------------------------------------------+
752 *
753 *
754 * 82599+ Advanced Receive Descriptor (Write-Back) Format
755 *
756 * 63 48 47 32 31 30 21 20 17 16 4 3 0
757 * +------------------------------------------------------+
758 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
759 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
760 * |/ Flow Dir Flt ID | | | | | |
761 * +------------------------------------------------------+
762 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
763 * +------------------------------------------------------+
764 * 63 48 47 32 31 20 19 0
765 */
766
767 for (n = 0; n < adapter->num_rx_queues; n++) {
768 rx_ring = adapter->rx_ring[n];
769 pr_info("------------------------------------\n");
770 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
771 pr_info("------------------------------------\n");
772 pr_info("%s%s%s",
773 "R [desc] [ PktBuf A0] ",
774 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
775 "<-- Adv Rx Read format\n");
776 pr_info("%s%s%s",
777 "RWB[desc] [PcsmIpSHl PtRs] ",
778 "[vl er S cks ln] ---------------- [bi->skb ] ",
779 "<-- Adv Rx Write-Back format\n");
780
781 for (i = 0; i < rx_ring->count; i++) {
782 rx_buffer_info = &rx_ring->rx_buffer_info[i];
783 rx_desc = IXGBE_RX_DESC(rx_ring, i);
784 u0 = (struct my_u0 *)rx_desc;
785 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
786 if (staterr & IXGBE_RXD_STAT_DD) {
787 /* Descriptor Done */
788 pr_info("RWB[0x%03X] %016llX "
789 "%016llX ---------------- %p", i,
790 le64_to_cpu(u0->a),
791 le64_to_cpu(u0->b),
792 rx_buffer_info->skb);
793 } else {
794 pr_info("R [0x%03X] %016llX "
795 "%016llX %016llX %p", i,
796 le64_to_cpu(u0->a),
797 le64_to_cpu(u0->b),
798 (u64)rx_buffer_info->dma,
799 rx_buffer_info->skb);
800
801 if (netif_msg_pktdata(adapter) &&
802 rx_buffer_info->dma) {
803 print_hex_dump(KERN_INFO, "",
804 DUMP_PREFIX_ADDRESS, 16, 1,
805 page_address(rx_buffer_info->page) +
806 rx_buffer_info->page_offset,
807 ixgbe_rx_bufsz(rx_ring), true);
808 }
809 }
810
811 if (i == rx_ring->next_to_use)
812 pr_cont(" NTU\n");
813 else if (i == rx_ring->next_to_clean)
814 pr_cont(" NTC\n");
815 else
816 pr_cont("\n");
817
818 }
819 }
820 }
821
822 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
823 {
824 u32 ctrl_ext;
825
826 /* Let firmware take over control of h/w */
827 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
828 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
829 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
830 }
831
832 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
833 {
834 u32 ctrl_ext;
835
836 /* Let firmware know the driver has taken over */
837 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
838 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
839 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
840 }
841
842 /**
843 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
844 * @adapter: pointer to adapter struct
845 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
846 * @queue: queue to map the corresponding interrupt to
847 * @msix_vector: the vector to map to the corresponding queue
848 *
849 */
850 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
851 u8 queue, u8 msix_vector)
852 {
853 u32 ivar, index;
854 struct ixgbe_hw *hw = &adapter->hw;
855 switch (hw->mac.type) {
856 case ixgbe_mac_82598EB:
857 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
858 if (direction == -1)
859 direction = 0;
860 index = (((direction * 64) + queue) >> 2) & 0x1F;
861 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
862 ivar &= ~(0xFF << (8 * (queue & 0x3)));
863 ivar |= (msix_vector << (8 * (queue & 0x3)));
864 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
865 break;
866 case ixgbe_mac_82599EB:
867 case ixgbe_mac_X540:
868 case ixgbe_mac_X550:
869 case ixgbe_mac_X550EM_x:
870 if (direction == -1) {
871 /* other causes */
872 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
873 index = ((queue & 1) * 8);
874 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
875 ivar &= ~(0xFF << index);
876 ivar |= (msix_vector << index);
877 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
878 break;
879 } else {
880 /* tx or rx causes */
881 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
882 index = ((16 * (queue & 1)) + (8 * direction));
883 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
884 ivar &= ~(0xFF << index);
885 ivar |= (msix_vector << index);
886 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
887 break;
888 }
889 default:
890 break;
891 }
892 }
893
894 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
895 u64 qmask)
896 {
897 u32 mask;
898
899 switch (adapter->hw.mac.type) {
900 case ixgbe_mac_82598EB:
901 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
902 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
903 break;
904 case ixgbe_mac_82599EB:
905 case ixgbe_mac_X540:
906 case ixgbe_mac_X550:
907 case ixgbe_mac_X550EM_x:
908 mask = (qmask & 0xFFFFFFFF);
909 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
910 mask = (qmask >> 32);
911 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
912 break;
913 default:
914 break;
915 }
916 }
917
918 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
919 struct ixgbe_tx_buffer *tx_buffer)
920 {
921 if (tx_buffer->skb) {
922 dev_kfree_skb_any(tx_buffer->skb);
923 if (dma_unmap_len(tx_buffer, len))
924 dma_unmap_single(ring->dev,
925 dma_unmap_addr(tx_buffer, dma),
926 dma_unmap_len(tx_buffer, len),
927 DMA_TO_DEVICE);
928 } else if (dma_unmap_len(tx_buffer, len)) {
929 dma_unmap_page(ring->dev,
930 dma_unmap_addr(tx_buffer, dma),
931 dma_unmap_len(tx_buffer, len),
932 DMA_TO_DEVICE);
933 }
934 tx_buffer->next_to_watch = NULL;
935 tx_buffer->skb = NULL;
936 dma_unmap_len_set(tx_buffer, len, 0);
937 /* tx_buffer must be completely set up in the transmit path */
938 }
939
940 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
941 {
942 struct ixgbe_hw *hw = &adapter->hw;
943 struct ixgbe_hw_stats *hwstats = &adapter->stats;
944 int i;
945 u32 data;
946
947 if ((hw->fc.current_mode != ixgbe_fc_full) &&
948 (hw->fc.current_mode != ixgbe_fc_rx_pause))
949 return;
950
951 switch (hw->mac.type) {
952 case ixgbe_mac_82598EB:
953 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
954 break;
955 default:
956 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
957 }
958 hwstats->lxoffrxc += data;
959
960 /* refill credits (no tx hang) if we received xoff */
961 if (!data)
962 return;
963
964 for (i = 0; i < adapter->num_tx_queues; i++)
965 clear_bit(__IXGBE_HANG_CHECK_ARMED,
966 &adapter->tx_ring[i]->state);
967 }
968
969 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
970 {
971 struct ixgbe_hw *hw = &adapter->hw;
972 struct ixgbe_hw_stats *hwstats = &adapter->stats;
973 u32 xoff[8] = {0};
974 u8 tc;
975 int i;
976 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
977
978 if (adapter->ixgbe_ieee_pfc)
979 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
980
981 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
982 ixgbe_update_xoff_rx_lfc(adapter);
983 return;
984 }
985
986 /* update stats for each tc, only valid with PFC enabled */
987 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
988 u32 pxoffrxc;
989
990 switch (hw->mac.type) {
991 case ixgbe_mac_82598EB:
992 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
993 break;
994 default:
995 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
996 }
997 hwstats->pxoffrxc[i] += pxoffrxc;
998 /* Get the TC for given UP */
999 tc = netdev_get_prio_tc_map(adapter->netdev, i);
1000 xoff[tc] += pxoffrxc;
1001 }
1002
1003 /* disarm tx queues that have received xoff frames */
1004 for (i = 0; i < adapter->num_tx_queues; i++) {
1005 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
1006
1007 tc = tx_ring->dcb_tc;
1008 if (xoff[tc])
1009 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1010 }
1011 }
1012
1013 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
1014 {
1015 return ring->stats.packets;
1016 }
1017
1018 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1019 {
1020 struct ixgbe_adapter *adapter;
1021 struct ixgbe_hw *hw;
1022 u32 head, tail;
1023
1024 if (ring->l2_accel_priv)
1025 adapter = ring->l2_accel_priv->real_adapter;
1026 else
1027 adapter = netdev_priv(ring->netdev);
1028
1029 hw = &adapter->hw;
1030 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1031 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
1032
1033 if (head != tail)
1034 return (head < tail) ?
1035 tail - head : (tail + ring->count - head);
1036
1037 return 0;
1038 }
1039
1040 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1041 {
1042 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1043 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1044 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1045
1046 clear_check_for_tx_hang(tx_ring);
1047
1048 /*
1049 * Check for a hung queue, but be thorough. This verifies
1050 * that a transmit has been completed since the previous
1051 * check AND there is at least one packet pending. The
1052 * ARMED bit is set to indicate a potential hang. The
1053 * bit is cleared if a pause frame is received to remove
1054 * false hang detection due to PFC or 802.3x frames. By
1055 * requiring this to fail twice we avoid races with
1056 * pfc clearing the ARMED bit and conditions where we
1057 * run the check_tx_hang logic with a transmit completion
1058 * pending but without time to complete it yet.
1059 */
1060 if (tx_done_old == tx_done && tx_pending)
1061 /* make sure it is true for two checks in a row */
1062 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1063 &tx_ring->state);
1064 /* update completed stats and continue */
1065 tx_ring->tx_stats.tx_done_old = tx_done;
1066 /* reset the countdown */
1067 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1068
1069 return false;
1070 }
1071
1072 /**
1073 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1074 * @adapter: driver private struct
1075 **/
1076 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1077 {
1078
1079 /* Do the reset outside of interrupt context */
1080 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1081 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
1082 e_warn(drv, "initiating reset due to tx timeout\n");
1083 ixgbe_service_event_schedule(adapter);
1084 }
1085 }
1086
1087 /**
1088 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
1089 * @q_vector: structure containing interrupt and ring information
1090 * @tx_ring: tx ring to clean
1091 **/
1092 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
1093 struct ixgbe_ring *tx_ring)
1094 {
1095 struct ixgbe_adapter *adapter = q_vector->adapter;
1096 struct ixgbe_tx_buffer *tx_buffer;
1097 union ixgbe_adv_tx_desc *tx_desc;
1098 unsigned int total_bytes = 0, total_packets = 0;
1099 unsigned int budget = q_vector->tx.work_limit;
1100 unsigned int i = tx_ring->next_to_clean;
1101
1102 if (test_bit(__IXGBE_DOWN, &adapter->state))
1103 return true;
1104
1105 tx_buffer = &tx_ring->tx_buffer_info[i];
1106 tx_desc = IXGBE_TX_DESC(tx_ring, i);
1107 i -= tx_ring->count;
1108
1109 do {
1110 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1111
1112 /* if next_to_watch is not set then there is no work pending */
1113 if (!eop_desc)
1114 break;
1115
1116 /* prevent any other reads prior to eop_desc */
1117 read_barrier_depends();
1118
1119 /* if DD is not set pending work has not been completed */
1120 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1121 break;
1122
1123 /* clear next_to_watch to prevent false hangs */
1124 tx_buffer->next_to_watch = NULL;
1125
1126 /* update the statistics for this packet */
1127 total_bytes += tx_buffer->bytecount;
1128 total_packets += tx_buffer->gso_segs;
1129
1130 /* free the skb */
1131 dev_consume_skb_any(tx_buffer->skb);
1132
1133 /* unmap skb header data */
1134 dma_unmap_single(tx_ring->dev,
1135 dma_unmap_addr(tx_buffer, dma),
1136 dma_unmap_len(tx_buffer, len),
1137 DMA_TO_DEVICE);
1138
1139 /* clear tx_buffer data */
1140 tx_buffer->skb = NULL;
1141 dma_unmap_len_set(tx_buffer, len, 0);
1142
1143 /* unmap remaining buffers */
1144 while (tx_desc != eop_desc) {
1145 tx_buffer++;
1146 tx_desc++;
1147 i++;
1148 if (unlikely(!i)) {
1149 i -= tx_ring->count;
1150 tx_buffer = tx_ring->tx_buffer_info;
1151 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1152 }
1153
1154 /* unmap any remaining paged data */
1155 if (dma_unmap_len(tx_buffer, len)) {
1156 dma_unmap_page(tx_ring->dev,
1157 dma_unmap_addr(tx_buffer, dma),
1158 dma_unmap_len(tx_buffer, len),
1159 DMA_TO_DEVICE);
1160 dma_unmap_len_set(tx_buffer, len, 0);
1161 }
1162 }
1163
1164 /* move us one more past the eop_desc for start of next pkt */
1165 tx_buffer++;
1166 tx_desc++;
1167 i++;
1168 if (unlikely(!i)) {
1169 i -= tx_ring->count;
1170 tx_buffer = tx_ring->tx_buffer_info;
1171 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1172 }
1173
1174 /* issue prefetch for next Tx descriptor */
1175 prefetch(tx_desc);
1176
1177 /* update budget accounting */
1178 budget--;
1179 } while (likely(budget));
1180
1181 i += tx_ring->count;
1182 tx_ring->next_to_clean = i;
1183 u64_stats_update_begin(&tx_ring->syncp);
1184 tx_ring->stats.bytes += total_bytes;
1185 tx_ring->stats.packets += total_packets;
1186 u64_stats_update_end(&tx_ring->syncp);
1187 q_vector->tx.total_bytes += total_bytes;
1188 q_vector->tx.total_packets += total_packets;
1189
1190 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1191 /* schedule immediate reset if we believe we hung */
1192 struct ixgbe_hw *hw = &adapter->hw;
1193 e_err(drv, "Detected Tx Unit Hang\n"
1194 " Tx Queue <%d>\n"
1195 " TDH, TDT <%x>, <%x>\n"
1196 " next_to_use <%x>\n"
1197 " next_to_clean <%x>\n"
1198 "tx_buffer_info[next_to_clean]\n"
1199 " time_stamp <%lx>\n"
1200 " jiffies <%lx>\n",
1201 tx_ring->queue_index,
1202 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1203 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1204 tx_ring->next_to_use, i,
1205 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1206
1207 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1208
1209 e_info(probe,
1210 "tx hang %d detected on queue %d, resetting adapter\n",
1211 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1212
1213 /* schedule immediate reset if we believe we hung */
1214 ixgbe_tx_timeout_reset(adapter);
1215
1216 /* the adapter is about to reset, no point in enabling stuff */
1217 return true;
1218 }
1219
1220 netdev_tx_completed_queue(txring_txq(tx_ring),
1221 total_packets, total_bytes);
1222
1223 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1224 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1225 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1226 /* Make sure that anybody stopping the queue after this
1227 * sees the new next_to_clean.
1228 */
1229 smp_mb();
1230 if (__netif_subqueue_stopped(tx_ring->netdev,
1231 tx_ring->queue_index)
1232 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1233 netif_wake_subqueue(tx_ring->netdev,
1234 tx_ring->queue_index);
1235 ++tx_ring->tx_stats.restart_queue;
1236 }
1237 }
1238
1239 return !!budget;
1240 }
1241
1242 #ifdef CONFIG_IXGBE_DCA
1243 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1244 struct ixgbe_ring *tx_ring,
1245 int cpu)
1246 {
1247 struct ixgbe_hw *hw = &adapter->hw;
1248 u32 txctrl = 0;
1249 u16 reg_offset;
1250
1251 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1252 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1253
1254 switch (hw->mac.type) {
1255 case ixgbe_mac_82598EB:
1256 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1257 break;
1258 case ixgbe_mac_82599EB:
1259 case ixgbe_mac_X540:
1260 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1261 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1262 break;
1263 default:
1264 /* for unknown hardware do not write register */
1265 return;
1266 }
1267
1268 /*
1269 * We can enable relaxed ordering for reads, but not writes when
1270 * DCA is enabled. This is due to a known issue in some chipsets
1271 * which will cause the DCA tag to be cleared.
1272 */
1273 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1274 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1275 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1276
1277 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1278 }
1279
1280 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1281 struct ixgbe_ring *rx_ring,
1282 int cpu)
1283 {
1284 struct ixgbe_hw *hw = &adapter->hw;
1285 u32 rxctrl = 0;
1286 u8 reg_idx = rx_ring->reg_idx;
1287
1288 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1289 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1290
1291 switch (hw->mac.type) {
1292 case ixgbe_mac_82599EB:
1293 case ixgbe_mac_X540:
1294 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1295 break;
1296 default:
1297 break;
1298 }
1299
1300 /*
1301 * We can enable relaxed ordering for reads, but not writes when
1302 * DCA is enabled. This is due to a known issue in some chipsets
1303 * which will cause the DCA tag to be cleared.
1304 */
1305 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1306 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
1307 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1308
1309 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1310 }
1311
1312 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1313 {
1314 struct ixgbe_adapter *adapter = q_vector->adapter;
1315 struct ixgbe_ring *ring;
1316 int cpu = get_cpu();
1317
1318 if (q_vector->cpu == cpu)
1319 goto out_no_update;
1320
1321 ixgbe_for_each_ring(ring, q_vector->tx)
1322 ixgbe_update_tx_dca(adapter, ring, cpu);
1323
1324 ixgbe_for_each_ring(ring, q_vector->rx)
1325 ixgbe_update_rx_dca(adapter, ring, cpu);
1326
1327 q_vector->cpu = cpu;
1328 out_no_update:
1329 put_cpu();
1330 }
1331
1332 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1333 {
1334 int i;
1335
1336 /* always use CB2 mode, difference is masked in the CB driver */
1337 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1338 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1339 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1340 else
1341 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1342 IXGBE_DCA_CTRL_DCA_DISABLE);
1343
1344 for (i = 0; i < adapter->num_q_vectors; i++) {
1345 adapter->q_vector[i]->cpu = -1;
1346 ixgbe_update_dca(adapter->q_vector[i]);
1347 }
1348 }
1349
1350 static int __ixgbe_notify_dca(struct device *dev, void *data)
1351 {
1352 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1353 unsigned long event = *(unsigned long *)data;
1354
1355 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1356 return 0;
1357
1358 switch (event) {
1359 case DCA_PROVIDER_ADD:
1360 /* if we're already enabled, don't do it again */
1361 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1362 break;
1363 if (dca_add_requester(dev) == 0) {
1364 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1365 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1366 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1367 break;
1368 }
1369 /* Fall Through since DCA is disabled. */
1370 case DCA_PROVIDER_REMOVE:
1371 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1372 dca_remove_requester(dev);
1373 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1374 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1375 IXGBE_DCA_CTRL_DCA_DISABLE);
1376 }
1377 break;
1378 }
1379
1380 return 0;
1381 }
1382
1383 #endif /* CONFIG_IXGBE_DCA */
1384
1385 #define IXGBE_RSS_L4_TYPES_MASK \
1386 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1387 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1388 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1389 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1390
1391 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1392 union ixgbe_adv_rx_desc *rx_desc,
1393 struct sk_buff *skb)
1394 {
1395 u16 rss_type;
1396
1397 if (!(ring->netdev->features & NETIF_F_RXHASH))
1398 return;
1399
1400 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1401 IXGBE_RXDADV_RSSTYPE_MASK;
1402
1403 if (!rss_type)
1404 return;
1405
1406 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1407 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1408 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
1409 }
1410
1411 #ifdef IXGBE_FCOE
1412 /**
1413 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1414 * @ring: structure containing ring specific data
1415 * @rx_desc: advanced rx descriptor
1416 *
1417 * Returns : true if it is FCoE pkt
1418 */
1419 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1420 union ixgbe_adv_rx_desc *rx_desc)
1421 {
1422 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1423
1424 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1425 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1426 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1427 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1428 }
1429
1430 #endif /* IXGBE_FCOE */
1431 /**
1432 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1433 * @ring: structure containing ring specific data
1434 * @rx_desc: current Rx descriptor being processed
1435 * @skb: skb currently being received and modified
1436 **/
1437 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1438 union ixgbe_adv_rx_desc *rx_desc,
1439 struct sk_buff *skb)
1440 {
1441 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1442 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1443 bool encap_pkt = false;
1444
1445 skb_checksum_none_assert(skb);
1446
1447 /* Rx csum disabled */
1448 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1449 return;
1450
1451 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1452 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1453 encap_pkt = true;
1454 skb->encapsulation = 1;
1455 }
1456
1457 /* if IP and error */
1458 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1459 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1460 ring->rx_stats.csum_err++;
1461 return;
1462 }
1463
1464 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1465 return;
1466
1467 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1468 /*
1469 * 82599 errata, UDP frames with a 0 checksum can be marked as
1470 * checksum errors.
1471 */
1472 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1473 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1474 return;
1475
1476 ring->rx_stats.csum_err++;
1477 return;
1478 }
1479
1480 /* It must be a TCP or UDP packet with a valid checksum */
1481 skb->ip_summed = CHECKSUM_UNNECESSARY;
1482 if (encap_pkt) {
1483 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1484 return;
1485
1486 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1487 ring->rx_stats.csum_err++;
1488 return;
1489 }
1490 /* If we checked the outer header let the stack know */
1491 skb->csum_level = 1;
1492 }
1493 }
1494
1495 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1496 struct ixgbe_rx_buffer *bi)
1497 {
1498 struct page *page = bi->page;
1499 dma_addr_t dma;
1500
1501 /* since we are recycling buffers we should seldom need to alloc */
1502 if (likely(page))
1503 return true;
1504
1505 /* alloc new page for storage */
1506 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1507 if (unlikely(!page)) {
1508 rx_ring->rx_stats.alloc_rx_page_failed++;
1509 return false;
1510 }
1511
1512 /* map page for use */
1513 dma = dma_map_page(rx_ring->dev, page, 0,
1514 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1515
1516 /*
1517 * if mapping failed free memory back to system since
1518 * there isn't much point in holding memory we can't use
1519 */
1520 if (dma_mapping_error(rx_ring->dev, dma)) {
1521 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1522
1523 rx_ring->rx_stats.alloc_rx_page_failed++;
1524 return false;
1525 }
1526
1527 bi->dma = dma;
1528 bi->page = page;
1529 bi->page_offset = 0;
1530
1531 return true;
1532 }
1533
1534 /**
1535 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1536 * @rx_ring: ring to place buffers on
1537 * @cleaned_count: number of buffers to replace
1538 **/
1539 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1540 {
1541 union ixgbe_adv_rx_desc *rx_desc;
1542 struct ixgbe_rx_buffer *bi;
1543 u16 i = rx_ring->next_to_use;
1544
1545 /* nothing to do */
1546 if (!cleaned_count)
1547 return;
1548
1549 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1550 bi = &rx_ring->rx_buffer_info[i];
1551 i -= rx_ring->count;
1552
1553 do {
1554 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1555 break;
1556
1557 /*
1558 * Refresh the desc even if buffer_addrs didn't change
1559 * because each write-back erases this info.
1560 */
1561 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1562
1563 rx_desc++;
1564 bi++;
1565 i++;
1566 if (unlikely(!i)) {
1567 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1568 bi = rx_ring->rx_buffer_info;
1569 i -= rx_ring->count;
1570 }
1571
1572 /* clear the status bits for the next_to_use descriptor */
1573 rx_desc->wb.upper.status_error = 0;
1574
1575 cleaned_count--;
1576 } while (cleaned_count);
1577
1578 i += rx_ring->count;
1579
1580 if (rx_ring->next_to_use != i) {
1581 rx_ring->next_to_use = i;
1582
1583 /* update next to alloc since we have filled the ring */
1584 rx_ring->next_to_alloc = i;
1585
1586 /* Force memory writes to complete before letting h/w
1587 * know there are new descriptors to fetch. (Only
1588 * applicable for weak-ordered memory model archs,
1589 * such as IA-64).
1590 */
1591 wmb();
1592 writel(i, rx_ring->tail);
1593 }
1594 }
1595
1596 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1597 struct sk_buff *skb)
1598 {
1599 u16 hdr_len = skb_headlen(skb);
1600
1601 /* set gso_size to avoid messing up TCP MSS */
1602 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1603 IXGBE_CB(skb)->append_cnt);
1604 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1605 }
1606
1607 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1608 struct sk_buff *skb)
1609 {
1610 /* if append_cnt is 0 then frame is not RSC */
1611 if (!IXGBE_CB(skb)->append_cnt)
1612 return;
1613
1614 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1615 rx_ring->rx_stats.rsc_flush++;
1616
1617 ixgbe_set_rsc_gso_size(rx_ring, skb);
1618
1619 /* gso_size is computed using append_cnt so always clear it last */
1620 IXGBE_CB(skb)->append_cnt = 0;
1621 }
1622
1623 /**
1624 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1625 * @rx_ring: rx descriptor ring packet is being transacted on
1626 * @rx_desc: pointer to the EOP Rx descriptor
1627 * @skb: pointer to current skb being populated
1628 *
1629 * This function checks the ring, descriptor, and packet information in
1630 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1631 * other fields within the skb.
1632 **/
1633 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1634 union ixgbe_adv_rx_desc *rx_desc,
1635 struct sk_buff *skb)
1636 {
1637 struct net_device *dev = rx_ring->netdev;
1638
1639 ixgbe_update_rsc_stats(rx_ring, skb);
1640
1641 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1642
1643 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1644
1645 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1646 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
1647
1648 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1649 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1650 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1651 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1652 }
1653
1654 skb_record_rx_queue(skb, rx_ring->queue_index);
1655
1656 skb->protocol = eth_type_trans(skb, dev);
1657 }
1658
1659 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1660 struct sk_buff *skb)
1661 {
1662 if (ixgbe_qv_busy_polling(q_vector))
1663 netif_receive_skb(skb);
1664 else
1665 napi_gro_receive(&q_vector->napi, skb);
1666 }
1667
1668 /**
1669 * ixgbe_is_non_eop - process handling of non-EOP buffers
1670 * @rx_ring: Rx ring being processed
1671 * @rx_desc: Rx descriptor for current buffer
1672 * @skb: Current socket buffer containing buffer in progress
1673 *
1674 * This function updates next to clean. If the buffer is an EOP buffer
1675 * this function exits returning false, otherwise it will place the
1676 * sk_buff in the next buffer to be chained and return true indicating
1677 * that this is in fact a non-EOP buffer.
1678 **/
1679 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1680 union ixgbe_adv_rx_desc *rx_desc,
1681 struct sk_buff *skb)
1682 {
1683 u32 ntc = rx_ring->next_to_clean + 1;
1684
1685 /* fetch, update, and store next to clean */
1686 ntc = (ntc < rx_ring->count) ? ntc : 0;
1687 rx_ring->next_to_clean = ntc;
1688
1689 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1690
1691 /* update RSC append count if present */
1692 if (ring_is_rsc_enabled(rx_ring)) {
1693 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1694 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1695
1696 if (unlikely(rsc_enabled)) {
1697 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1698
1699 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1700 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1701
1702 /* update ntc based on RSC value */
1703 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1704 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1705 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1706 }
1707 }
1708
1709 /* if we are the last buffer then there is nothing else to do */
1710 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1711 return false;
1712
1713 /* place skb in next buffer to be received */
1714 rx_ring->rx_buffer_info[ntc].skb = skb;
1715 rx_ring->rx_stats.non_eop_descs++;
1716
1717 return true;
1718 }
1719
1720 /**
1721 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1722 * @rx_ring: rx descriptor ring packet is being transacted on
1723 * @skb: pointer to current skb being adjusted
1724 *
1725 * This function is an ixgbe specific version of __pskb_pull_tail. The
1726 * main difference between this version and the original function is that
1727 * this function can make several assumptions about the state of things
1728 * that allow for significant optimizations versus the standard function.
1729 * As a result we can do things like drop a frag and maintain an accurate
1730 * truesize for the skb.
1731 */
1732 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1733 struct sk_buff *skb)
1734 {
1735 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1736 unsigned char *va;
1737 unsigned int pull_len;
1738
1739 /*
1740 * it is valid to use page_address instead of kmap since we are
1741 * working with pages allocated out of the lomem pool per
1742 * alloc_page(GFP_ATOMIC)
1743 */
1744 va = skb_frag_address(frag);
1745
1746 /*
1747 * we need the header to contain the greater of either ETH_HLEN or
1748 * 60 bytes if the skb->len is less than 60 for skb_pad.
1749 */
1750 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
1751
1752 /* align pull length to size of long to optimize memcpy performance */
1753 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1754
1755 /* update all of the pointers */
1756 skb_frag_size_sub(frag, pull_len);
1757 frag->page_offset += pull_len;
1758 skb->data_len -= pull_len;
1759 skb->tail += pull_len;
1760 }
1761
1762 /**
1763 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1764 * @rx_ring: rx descriptor ring packet is being transacted on
1765 * @skb: pointer to current skb being updated
1766 *
1767 * This function provides a basic DMA sync up for the first fragment of an
1768 * skb. The reason for doing this is that the first fragment cannot be
1769 * unmapped until we have reached the end of packet descriptor for a buffer
1770 * chain.
1771 */
1772 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1773 struct sk_buff *skb)
1774 {
1775 /* if the page was released unmap it, else just sync our portion */
1776 if (unlikely(IXGBE_CB(skb)->page_released)) {
1777 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1778 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1779 IXGBE_CB(skb)->page_released = false;
1780 } else {
1781 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1782
1783 dma_sync_single_range_for_cpu(rx_ring->dev,
1784 IXGBE_CB(skb)->dma,
1785 frag->page_offset,
1786 ixgbe_rx_bufsz(rx_ring),
1787 DMA_FROM_DEVICE);
1788 }
1789 IXGBE_CB(skb)->dma = 0;
1790 }
1791
1792 /**
1793 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1794 * @rx_ring: rx descriptor ring packet is being transacted on
1795 * @rx_desc: pointer to the EOP Rx descriptor
1796 * @skb: pointer to current skb being fixed
1797 *
1798 * Check for corrupted packet headers caused by senders on the local L2
1799 * embedded NIC switch not setting up their Tx Descriptors right. These
1800 * should be very rare.
1801 *
1802 * Also address the case where we are pulling data in on pages only
1803 * and as such no data is present in the skb header.
1804 *
1805 * In addition if skb is not at least 60 bytes we need to pad it so that
1806 * it is large enough to qualify as a valid Ethernet frame.
1807 *
1808 * Returns true if an error was encountered and skb was freed.
1809 **/
1810 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1811 union ixgbe_adv_rx_desc *rx_desc,
1812 struct sk_buff *skb)
1813 {
1814 struct net_device *netdev = rx_ring->netdev;
1815
1816 /* verify that the packet does not have any known errors */
1817 if (unlikely(ixgbe_test_staterr(rx_desc,
1818 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1819 !(netdev->features & NETIF_F_RXALL))) {
1820 dev_kfree_skb_any(skb);
1821 return true;
1822 }
1823
1824 /* place header in linear portion of buffer */
1825 if (skb_is_nonlinear(skb))
1826 ixgbe_pull_tail(rx_ring, skb);
1827
1828 #ifdef IXGBE_FCOE
1829 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1830 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1831 return false;
1832
1833 #endif
1834 /* if eth_skb_pad returns an error the skb was freed */
1835 if (eth_skb_pad(skb))
1836 return true;
1837
1838 return false;
1839 }
1840
1841 /**
1842 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1843 * @rx_ring: rx descriptor ring to store buffers on
1844 * @old_buff: donor buffer to have page reused
1845 *
1846 * Synchronizes page for reuse by the adapter
1847 **/
1848 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1849 struct ixgbe_rx_buffer *old_buff)
1850 {
1851 struct ixgbe_rx_buffer *new_buff;
1852 u16 nta = rx_ring->next_to_alloc;
1853
1854 new_buff = &rx_ring->rx_buffer_info[nta];
1855
1856 /* update, and store next to alloc */
1857 nta++;
1858 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1859
1860 /* transfer page from old buffer to new buffer */
1861 *new_buff = *old_buff;
1862
1863 /* sync the buffer for use by the device */
1864 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1865 new_buff->page_offset,
1866 ixgbe_rx_bufsz(rx_ring),
1867 DMA_FROM_DEVICE);
1868 }
1869
1870 static inline bool ixgbe_page_is_reserved(struct page *page)
1871 {
1872 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
1873 }
1874
1875 /**
1876 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1877 * @rx_ring: rx descriptor ring to transact packets on
1878 * @rx_buffer: buffer containing page to add
1879 * @rx_desc: descriptor containing length of buffer written by hardware
1880 * @skb: sk_buff to place the data into
1881 *
1882 * This function will add the data contained in rx_buffer->page to the skb.
1883 * This is done either through a direct copy if the data in the buffer is
1884 * less than the skb header size, otherwise it will just attach the page as
1885 * a frag to the skb.
1886 *
1887 * The function will then update the page offset if necessary and return
1888 * true if the buffer can be reused by the adapter.
1889 **/
1890 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1891 struct ixgbe_rx_buffer *rx_buffer,
1892 union ixgbe_adv_rx_desc *rx_desc,
1893 struct sk_buff *skb)
1894 {
1895 struct page *page = rx_buffer->page;
1896 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1897 #if (PAGE_SIZE < 8192)
1898 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1899 #else
1900 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1901 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1902 ixgbe_rx_bufsz(rx_ring);
1903 #endif
1904
1905 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1906 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1907
1908 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1909
1910 /* page is not reserved, we can reuse buffer as-is */
1911 if (likely(!ixgbe_page_is_reserved(page)))
1912 return true;
1913
1914 /* this page cannot be reused so discard it */
1915 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1916 return false;
1917 }
1918
1919 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1920 rx_buffer->page_offset, size, truesize);
1921
1922 /* avoid re-using remote pages */
1923 if (unlikely(ixgbe_page_is_reserved(page)))
1924 return false;
1925
1926 #if (PAGE_SIZE < 8192)
1927 /* if we are only owner of page we can reuse it */
1928 if (unlikely(page_count(page) != 1))
1929 return false;
1930
1931 /* flip page offset to other buffer */
1932 rx_buffer->page_offset ^= truesize;
1933 #else
1934 /* move offset up to the next cache line */
1935 rx_buffer->page_offset += truesize;
1936
1937 if (rx_buffer->page_offset > last_offset)
1938 return false;
1939 #endif
1940
1941 /* Even if we own the page, we are not allowed to use atomic_set()
1942 * This would break get_page_unless_zero() users.
1943 */
1944 atomic_inc(&page->_count);
1945
1946 return true;
1947 }
1948
1949 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1950 union ixgbe_adv_rx_desc *rx_desc)
1951 {
1952 struct ixgbe_rx_buffer *rx_buffer;
1953 struct sk_buff *skb;
1954 struct page *page;
1955
1956 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1957 page = rx_buffer->page;
1958 prefetchw(page);
1959
1960 skb = rx_buffer->skb;
1961
1962 if (likely(!skb)) {
1963 void *page_addr = page_address(page) +
1964 rx_buffer->page_offset;
1965
1966 /* prefetch first cache line of first page */
1967 prefetch(page_addr);
1968 #if L1_CACHE_BYTES < 128
1969 prefetch(page_addr + L1_CACHE_BYTES);
1970 #endif
1971
1972 /* allocate a skb to store the frags */
1973 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
1974 IXGBE_RX_HDR_SIZE);
1975 if (unlikely(!skb)) {
1976 rx_ring->rx_stats.alloc_rx_buff_failed++;
1977 return NULL;
1978 }
1979
1980 /*
1981 * we will be copying header into skb->data in
1982 * pskb_may_pull so it is in our interest to prefetch
1983 * it now to avoid a possible cache miss
1984 */
1985 prefetchw(skb->data);
1986
1987 /*
1988 * Delay unmapping of the first packet. It carries the
1989 * header information, HW may still access the header
1990 * after the writeback. Only unmap it when EOP is
1991 * reached
1992 */
1993 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1994 goto dma_sync;
1995
1996 IXGBE_CB(skb)->dma = rx_buffer->dma;
1997 } else {
1998 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1999 ixgbe_dma_sync_frag(rx_ring, skb);
2000
2001 dma_sync:
2002 /* we are reusing so sync this buffer for CPU use */
2003 dma_sync_single_range_for_cpu(rx_ring->dev,
2004 rx_buffer->dma,
2005 rx_buffer->page_offset,
2006 ixgbe_rx_bufsz(rx_ring),
2007 DMA_FROM_DEVICE);
2008
2009 rx_buffer->skb = NULL;
2010 }
2011
2012 /* pull page into skb */
2013 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2014 /* hand second half of page back to the ring */
2015 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2016 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2017 /* the page has been released from the ring */
2018 IXGBE_CB(skb)->page_released = true;
2019 } else {
2020 /* we are not reusing the buffer so unmap it */
2021 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2022 ixgbe_rx_pg_size(rx_ring),
2023 DMA_FROM_DEVICE);
2024 }
2025
2026 /* clear contents of buffer_info */
2027 rx_buffer->page = NULL;
2028
2029 return skb;
2030 }
2031
2032 /**
2033 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2034 * @q_vector: structure containing interrupt and ring information
2035 * @rx_ring: rx descriptor ring to transact packets on
2036 * @budget: Total limit on number of packets to process
2037 *
2038 * This function provides a "bounce buffer" approach to Rx interrupt
2039 * processing. The advantage to this is that on systems that have
2040 * expensive overhead for IOMMU access this provides a means of avoiding
2041 * it by maintaining the mapping of the page to the syste.
2042 *
2043 * Returns amount of work completed
2044 **/
2045 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
2046 struct ixgbe_ring *rx_ring,
2047 const int budget)
2048 {
2049 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2050 #ifdef IXGBE_FCOE
2051 struct ixgbe_adapter *adapter = q_vector->adapter;
2052 int ddp_bytes;
2053 unsigned int mss = 0;
2054 #endif /* IXGBE_FCOE */
2055 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
2056
2057 while (likely(total_rx_packets < budget)) {
2058 union ixgbe_adv_rx_desc *rx_desc;
2059 struct sk_buff *skb;
2060
2061 /* return some buffers to hardware, one at a time is too slow */
2062 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2063 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2064 cleaned_count = 0;
2065 }
2066
2067 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2068
2069 if (!rx_desc->wb.upper.status_error)
2070 break;
2071
2072 /* This memory barrier is needed to keep us from reading
2073 * any other fields out of the rx_desc until we know the
2074 * descriptor has been written back
2075 */
2076 dma_rmb();
2077
2078 /* retrieve a buffer from the ring */
2079 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
2080
2081 /* exit if we failed to retrieve a buffer */
2082 if (!skb)
2083 break;
2084
2085 cleaned_count++;
2086
2087 /* place incomplete frames back on ring for completion */
2088 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2089 continue;
2090
2091 /* verify the packet layout is correct */
2092 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2093 continue;
2094
2095 /* probably a little skewed due to removing CRC */
2096 total_rx_bytes += skb->len;
2097
2098 /* populate checksum, timestamp, VLAN, and protocol */
2099 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2100
2101 #ifdef IXGBE_FCOE
2102 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2103 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2104 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2105 /* include DDPed FCoE data */
2106 if (ddp_bytes > 0) {
2107 if (!mss) {
2108 mss = rx_ring->netdev->mtu -
2109 sizeof(struct fcoe_hdr) -
2110 sizeof(struct fc_frame_header) -
2111 sizeof(struct fcoe_crc_eof);
2112 if (mss > 512)
2113 mss &= ~511;
2114 }
2115 total_rx_bytes += ddp_bytes;
2116 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2117 mss);
2118 }
2119 if (!ddp_bytes) {
2120 dev_kfree_skb_any(skb);
2121 continue;
2122 }
2123 }
2124
2125 #endif /* IXGBE_FCOE */
2126 skb_mark_napi_id(skb, &q_vector->napi);
2127 ixgbe_rx_skb(q_vector, skb);
2128
2129 /* update budget accounting */
2130 total_rx_packets++;
2131 }
2132
2133 u64_stats_update_begin(&rx_ring->syncp);
2134 rx_ring->stats.packets += total_rx_packets;
2135 rx_ring->stats.bytes += total_rx_bytes;
2136 u64_stats_update_end(&rx_ring->syncp);
2137 q_vector->rx.total_packets += total_rx_packets;
2138 q_vector->rx.total_bytes += total_rx_bytes;
2139
2140 return total_rx_packets;
2141 }
2142
2143 #ifdef CONFIG_NET_RX_BUSY_POLL
2144 /* must be called with local_bh_disable()d */
2145 static int ixgbe_low_latency_recv(struct napi_struct *napi)
2146 {
2147 struct ixgbe_q_vector *q_vector =
2148 container_of(napi, struct ixgbe_q_vector, napi);
2149 struct ixgbe_adapter *adapter = q_vector->adapter;
2150 struct ixgbe_ring *ring;
2151 int found = 0;
2152
2153 if (test_bit(__IXGBE_DOWN, &adapter->state))
2154 return LL_FLUSH_FAILED;
2155
2156 if (!ixgbe_qv_lock_poll(q_vector))
2157 return LL_FLUSH_BUSY;
2158
2159 ixgbe_for_each_ring(ring, q_vector->rx) {
2160 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
2161 #ifdef BP_EXTENDED_STATS
2162 if (found)
2163 ring->stats.cleaned += found;
2164 else
2165 ring->stats.misses++;
2166 #endif
2167 if (found)
2168 break;
2169 }
2170
2171 ixgbe_qv_unlock_poll(q_vector);
2172
2173 return found;
2174 }
2175 #endif /* CONFIG_NET_RX_BUSY_POLL */
2176
2177 /**
2178 * ixgbe_configure_msix - Configure MSI-X hardware
2179 * @adapter: board private structure
2180 *
2181 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2182 * interrupts.
2183 **/
2184 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2185 {
2186 struct ixgbe_q_vector *q_vector;
2187 int v_idx;
2188 u32 mask;
2189
2190 /* Populate MSIX to EITR Select */
2191 if (adapter->num_vfs > 32) {
2192 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2193 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2194 }
2195
2196 /*
2197 * Populate the IVAR table and set the ITR values to the
2198 * corresponding register.
2199 */
2200 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2201 struct ixgbe_ring *ring;
2202 q_vector = adapter->q_vector[v_idx];
2203
2204 ixgbe_for_each_ring(ring, q_vector->rx)
2205 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2206
2207 ixgbe_for_each_ring(ring, q_vector->tx)
2208 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2209
2210 ixgbe_write_eitr(q_vector);
2211 }
2212
2213 switch (adapter->hw.mac.type) {
2214 case ixgbe_mac_82598EB:
2215 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2216 v_idx);
2217 break;
2218 case ixgbe_mac_82599EB:
2219 case ixgbe_mac_X540:
2220 case ixgbe_mac_X550:
2221 case ixgbe_mac_X550EM_x:
2222 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2223 break;
2224 default:
2225 break;
2226 }
2227 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2228
2229 /* set up to autoclear timer, and the vectors */
2230 mask = IXGBE_EIMS_ENABLE_MASK;
2231 mask &= ~(IXGBE_EIMS_OTHER |
2232 IXGBE_EIMS_MAILBOX |
2233 IXGBE_EIMS_LSC);
2234
2235 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2236 }
2237
2238 enum latency_range {
2239 lowest_latency = 0,
2240 low_latency = 1,
2241 bulk_latency = 2,
2242 latency_invalid = 255
2243 };
2244
2245 /**
2246 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2247 * @q_vector: structure containing interrupt and ring information
2248 * @ring_container: structure containing ring performance data
2249 *
2250 * Stores a new ITR value based on packets and byte
2251 * counts during the last interrupt. The advantage of per interrupt
2252 * computation is faster updates and more accurate ITR for the current
2253 * traffic pattern. Constants in this function were computed
2254 * based on theoretical maximum wire speed and thresholds were set based
2255 * on testing data as well as attempting to minimize response time
2256 * while increasing bulk throughput.
2257 * this functionality is controlled by the InterruptThrottleRate module
2258 * parameter (see ixgbe_param.c)
2259 **/
2260 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2261 struct ixgbe_ring_container *ring_container)
2262 {
2263 int bytes = ring_container->total_bytes;
2264 int packets = ring_container->total_packets;
2265 u32 timepassed_us;
2266 u64 bytes_perint;
2267 u8 itr_setting = ring_container->itr;
2268
2269 if (packets == 0)
2270 return;
2271
2272 /* simple throttlerate management
2273 * 0-10MB/s lowest (100000 ints/s)
2274 * 10-20MB/s low (20000 ints/s)
2275 * 20-1249MB/s bulk (12000 ints/s)
2276 */
2277 /* what was last interrupt timeslice? */
2278 timepassed_us = q_vector->itr >> 2;
2279 if (timepassed_us == 0)
2280 return;
2281
2282 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2283
2284 switch (itr_setting) {
2285 case lowest_latency:
2286 if (bytes_perint > 10)
2287 itr_setting = low_latency;
2288 break;
2289 case low_latency:
2290 if (bytes_perint > 20)
2291 itr_setting = bulk_latency;
2292 else if (bytes_perint <= 10)
2293 itr_setting = lowest_latency;
2294 break;
2295 case bulk_latency:
2296 if (bytes_perint <= 20)
2297 itr_setting = low_latency;
2298 break;
2299 }
2300
2301 /* clear work counters since we have the values we need */
2302 ring_container->total_bytes = 0;
2303 ring_container->total_packets = 0;
2304
2305 /* write updated itr to ring container */
2306 ring_container->itr = itr_setting;
2307 }
2308
2309 /**
2310 * ixgbe_write_eitr - write EITR register in hardware specific way
2311 * @q_vector: structure containing interrupt and ring information
2312 *
2313 * This function is made to be called by ethtool and by the driver
2314 * when it needs to update EITR registers at runtime. Hardware
2315 * specific quirks/differences are taken care of here.
2316 */
2317 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2318 {
2319 struct ixgbe_adapter *adapter = q_vector->adapter;
2320 struct ixgbe_hw *hw = &adapter->hw;
2321 int v_idx = q_vector->v_idx;
2322 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2323
2324 switch (adapter->hw.mac.type) {
2325 case ixgbe_mac_82598EB:
2326 /* must write high and low 16 bits to reset counter */
2327 itr_reg |= (itr_reg << 16);
2328 break;
2329 case ixgbe_mac_82599EB:
2330 case ixgbe_mac_X540:
2331 case ixgbe_mac_X550:
2332 case ixgbe_mac_X550EM_x:
2333 /*
2334 * set the WDIS bit to not clear the timer bits and cause an
2335 * immediate assertion of the interrupt
2336 */
2337 itr_reg |= IXGBE_EITR_CNT_WDIS;
2338 break;
2339 default:
2340 break;
2341 }
2342 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2343 }
2344
2345 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2346 {
2347 u32 new_itr = q_vector->itr;
2348 u8 current_itr;
2349
2350 ixgbe_update_itr(q_vector, &q_vector->tx);
2351 ixgbe_update_itr(q_vector, &q_vector->rx);
2352
2353 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2354
2355 switch (current_itr) {
2356 /* counts and packets in update_itr are dependent on these numbers */
2357 case lowest_latency:
2358 new_itr = IXGBE_100K_ITR;
2359 break;
2360 case low_latency:
2361 new_itr = IXGBE_20K_ITR;
2362 break;
2363 case bulk_latency:
2364 new_itr = IXGBE_12K_ITR;
2365 break;
2366 default:
2367 break;
2368 }
2369
2370 if (new_itr != q_vector->itr) {
2371 /* do an exponential smoothing */
2372 new_itr = (10 * new_itr * q_vector->itr) /
2373 ((9 * new_itr) + q_vector->itr);
2374
2375 /* save the algorithm value here */
2376 q_vector->itr = new_itr;
2377
2378 ixgbe_write_eitr(q_vector);
2379 }
2380 }
2381
2382 /**
2383 * ixgbe_check_overtemp_subtask - check for over temperature
2384 * @adapter: pointer to adapter
2385 **/
2386 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2387 {
2388 struct ixgbe_hw *hw = &adapter->hw;
2389 u32 eicr = adapter->interrupt_event;
2390
2391 if (test_bit(__IXGBE_DOWN, &adapter->state))
2392 return;
2393
2394 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2395 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2396 return;
2397
2398 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2399
2400 switch (hw->device_id) {
2401 case IXGBE_DEV_ID_82599_T3_LOM:
2402 /*
2403 * Since the warning interrupt is for both ports
2404 * we don't have to check if:
2405 * - This interrupt wasn't for our port.
2406 * - We may have missed the interrupt so always have to
2407 * check if we got a LSC
2408 */
2409 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
2410 !(eicr & IXGBE_EICR_LSC))
2411 return;
2412
2413 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2414 u32 speed;
2415 bool link_up = false;
2416
2417 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2418
2419 if (link_up)
2420 return;
2421 }
2422
2423 /* Check if this is not due to overtemp */
2424 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2425 return;
2426
2427 break;
2428 default:
2429 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2430 return;
2431 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
2432 return;
2433 break;
2434 }
2435 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2436
2437 adapter->interrupt_event = 0;
2438 }
2439
2440 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2441 {
2442 struct ixgbe_hw *hw = &adapter->hw;
2443
2444 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2445 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2446 e_crit(probe, "Fan has stopped, replace the adapter\n");
2447 /* write to clear the interrupt */
2448 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2449 }
2450 }
2451
2452 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2453 {
2454 struct ixgbe_hw *hw = &adapter->hw;
2455
2456 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2457 return;
2458
2459 switch (adapter->hw.mac.type) {
2460 case ixgbe_mac_82599EB:
2461 /*
2462 * Need to check link state so complete overtemp check
2463 * on service task
2464 */
2465 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2466 (eicr & IXGBE_EICR_LSC)) &&
2467 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2468 adapter->interrupt_event = eicr;
2469 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2470 ixgbe_service_event_schedule(adapter);
2471 return;
2472 }
2473 return;
2474 case ixgbe_mac_X540:
2475 if (!(eicr & IXGBE_EICR_TS))
2476 return;
2477 break;
2478 default:
2479 return;
2480 }
2481
2482 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2483 }
2484
2485 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2486 {
2487 switch (hw->mac.type) {
2488 case ixgbe_mac_82598EB:
2489 if (hw->phy.type == ixgbe_phy_nl)
2490 return true;
2491 return false;
2492 case ixgbe_mac_82599EB:
2493 case ixgbe_mac_X550EM_x:
2494 switch (hw->mac.ops.get_media_type(hw)) {
2495 case ixgbe_media_type_fiber:
2496 case ixgbe_media_type_fiber_qsfp:
2497 return true;
2498 default:
2499 return false;
2500 }
2501 default:
2502 return false;
2503 }
2504 }
2505
2506 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2507 {
2508 struct ixgbe_hw *hw = &adapter->hw;
2509 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
2510
2511 if (!ixgbe_is_sfp(hw))
2512 return;
2513
2514 /* Later MAC's use different SDP */
2515 if (hw->mac.type >= ixgbe_mac_X540)
2516 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2517
2518 if (eicr & eicr_mask) {
2519 /* Clear the interrupt */
2520 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
2521 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2522 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2523 adapter->sfp_poll_time = 0;
2524 ixgbe_service_event_schedule(adapter);
2525 }
2526 }
2527
2528 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2529 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2530 /* Clear the interrupt */
2531 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2532 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2533 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2534 ixgbe_service_event_schedule(adapter);
2535 }
2536 }
2537 }
2538
2539 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2540 {
2541 struct ixgbe_hw *hw = &adapter->hw;
2542
2543 adapter->lsc_int++;
2544 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2545 adapter->link_check_timeout = jiffies;
2546 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2547 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2548 IXGBE_WRITE_FLUSH(hw);
2549 ixgbe_service_event_schedule(adapter);
2550 }
2551 }
2552
2553 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2554 u64 qmask)
2555 {
2556 u32 mask;
2557 struct ixgbe_hw *hw = &adapter->hw;
2558
2559 switch (hw->mac.type) {
2560 case ixgbe_mac_82598EB:
2561 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2562 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2563 break;
2564 case ixgbe_mac_82599EB:
2565 case ixgbe_mac_X540:
2566 case ixgbe_mac_X550:
2567 case ixgbe_mac_X550EM_x:
2568 mask = (qmask & 0xFFFFFFFF);
2569 if (mask)
2570 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2571 mask = (qmask >> 32);
2572 if (mask)
2573 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2574 break;
2575 default:
2576 break;
2577 }
2578 /* skip the flush */
2579 }
2580
2581 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2582 u64 qmask)
2583 {
2584 u32 mask;
2585 struct ixgbe_hw *hw = &adapter->hw;
2586
2587 switch (hw->mac.type) {
2588 case ixgbe_mac_82598EB:
2589 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2590 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2591 break;
2592 case ixgbe_mac_82599EB:
2593 case ixgbe_mac_X540:
2594 case ixgbe_mac_X550:
2595 case ixgbe_mac_X550EM_x:
2596 mask = (qmask & 0xFFFFFFFF);
2597 if (mask)
2598 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2599 mask = (qmask >> 32);
2600 if (mask)
2601 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2602 break;
2603 default:
2604 break;
2605 }
2606 /* skip the flush */
2607 }
2608
2609 /**
2610 * ixgbe_irq_enable - Enable default interrupt generation settings
2611 * @adapter: board private structure
2612 **/
2613 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2614 bool flush)
2615 {
2616 struct ixgbe_hw *hw = &adapter->hw;
2617 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2618
2619 /* don't reenable LSC while waiting for link */
2620 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2621 mask &= ~IXGBE_EIMS_LSC;
2622
2623 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2624 switch (adapter->hw.mac.type) {
2625 case ixgbe_mac_82599EB:
2626 mask |= IXGBE_EIMS_GPI_SDP0(hw);
2627 break;
2628 case ixgbe_mac_X540:
2629 case ixgbe_mac_X550:
2630 case ixgbe_mac_X550EM_x:
2631 mask |= IXGBE_EIMS_TS;
2632 break;
2633 default:
2634 break;
2635 }
2636 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2637 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2638 switch (adapter->hw.mac.type) {
2639 case ixgbe_mac_82599EB:
2640 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2641 mask |= IXGBE_EIMS_GPI_SDP2(hw);
2642 /* fall through */
2643 case ixgbe_mac_X540:
2644 case ixgbe_mac_X550:
2645 case ixgbe_mac_X550EM_x:
2646 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2647 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
2648 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2649 mask |= IXGBE_EICR_GPI_SDP0_X540;
2650 mask |= IXGBE_EIMS_ECC;
2651 mask |= IXGBE_EIMS_MAILBOX;
2652 break;
2653 default:
2654 break;
2655 }
2656
2657 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2658 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2659 mask |= IXGBE_EIMS_FLOW_DIR;
2660
2661 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2662 if (queues)
2663 ixgbe_irq_enable_queues(adapter, ~0);
2664 if (flush)
2665 IXGBE_WRITE_FLUSH(&adapter->hw);
2666 }
2667
2668 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2669 {
2670 struct ixgbe_adapter *adapter = data;
2671 struct ixgbe_hw *hw = &adapter->hw;
2672 u32 eicr;
2673
2674 /*
2675 * Workaround for Silicon errata. Use clear-by-write instead
2676 * of clear-by-read. Reading with EICS will return the
2677 * interrupt causes without clearing, which later be done
2678 * with the write to EICR.
2679 */
2680 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2681
2682 /* The lower 16bits of the EICR register are for the queue interrupts
2683 * which should be masked here in order to not accidentally clear them if
2684 * the bits are high when ixgbe_msix_other is called. There is a race
2685 * condition otherwise which results in possible performance loss
2686 * especially if the ixgbe_msix_other interrupt is triggering
2687 * consistently (as it would when PPS is turned on for the X540 device)
2688 */
2689 eicr &= 0xFFFF0000;
2690
2691 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2692
2693 if (eicr & IXGBE_EICR_LSC)
2694 ixgbe_check_lsc(adapter);
2695
2696 if (eicr & IXGBE_EICR_MAILBOX)
2697 ixgbe_msg_task(adapter);
2698
2699 switch (hw->mac.type) {
2700 case ixgbe_mac_82599EB:
2701 case ixgbe_mac_X540:
2702 case ixgbe_mac_X550:
2703 case ixgbe_mac_X550EM_x:
2704 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2705 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2706 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2707 ixgbe_service_event_schedule(adapter);
2708 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2709 IXGBE_EICR_GPI_SDP0_X540);
2710 }
2711 if (eicr & IXGBE_EICR_ECC) {
2712 e_info(link, "Received ECC Err, initiating reset\n");
2713 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2714 ixgbe_service_event_schedule(adapter);
2715 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2716 }
2717 /* Handle Flow Director Full threshold interrupt */
2718 if (eicr & IXGBE_EICR_FLOW_DIR) {
2719 int reinit_count = 0;
2720 int i;
2721 for (i = 0; i < adapter->num_tx_queues; i++) {
2722 struct ixgbe_ring *ring = adapter->tx_ring[i];
2723 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2724 &ring->state))
2725 reinit_count++;
2726 }
2727 if (reinit_count) {
2728 /* no more flow director interrupts until after init */
2729 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2730 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2731 ixgbe_service_event_schedule(adapter);
2732 }
2733 }
2734 ixgbe_check_sfp_event(adapter, eicr);
2735 ixgbe_check_overtemp_event(adapter, eicr);
2736 break;
2737 default:
2738 break;
2739 }
2740
2741 ixgbe_check_fan_failure(adapter, eicr);
2742
2743 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2744 ixgbe_ptp_check_pps_event(adapter, eicr);
2745
2746 /* re-enable the original interrupt state, no lsc, no queues */
2747 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2748 ixgbe_irq_enable(adapter, false, false);
2749
2750 return IRQ_HANDLED;
2751 }
2752
2753 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2754 {
2755 struct ixgbe_q_vector *q_vector = data;
2756
2757 /* EIAM disabled interrupts (on this vector) for us */
2758
2759 if (q_vector->rx.ring || q_vector->tx.ring)
2760 napi_schedule(&q_vector->napi);
2761
2762 return IRQ_HANDLED;
2763 }
2764
2765 /**
2766 * ixgbe_poll - NAPI Rx polling callback
2767 * @napi: structure for representing this polling device
2768 * @budget: how many packets driver is allowed to clean
2769 *
2770 * This function is used for legacy and MSI, NAPI mode
2771 **/
2772 int ixgbe_poll(struct napi_struct *napi, int budget)
2773 {
2774 struct ixgbe_q_vector *q_vector =
2775 container_of(napi, struct ixgbe_q_vector, napi);
2776 struct ixgbe_adapter *adapter = q_vector->adapter;
2777 struct ixgbe_ring *ring;
2778 int per_ring_budget;
2779 bool clean_complete = true;
2780
2781 #ifdef CONFIG_IXGBE_DCA
2782 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2783 ixgbe_update_dca(q_vector);
2784 #endif
2785
2786 ixgbe_for_each_ring(ring, q_vector->tx)
2787 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2788
2789 if (!ixgbe_qv_lock_napi(q_vector))
2790 return budget;
2791
2792 /* attempt to distribute budget to each queue fairly, but don't allow
2793 * the budget to go below 1 because we'll exit polling */
2794 if (q_vector->rx.count > 1)
2795 per_ring_budget = max(budget/q_vector->rx.count, 1);
2796 else
2797 per_ring_budget = budget;
2798
2799 ixgbe_for_each_ring(ring, q_vector->rx)
2800 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2801 per_ring_budget) < per_ring_budget);
2802
2803 ixgbe_qv_unlock_napi(q_vector);
2804 /* If all work not completed, return budget and keep polling */
2805 if (!clean_complete)
2806 return budget;
2807
2808 /* all work done, exit the polling mode */
2809 napi_complete(napi);
2810 if (adapter->rx_itr_setting & 1)
2811 ixgbe_set_itr(q_vector);
2812 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2813 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2814
2815 return 0;
2816 }
2817
2818 /**
2819 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2820 * @adapter: board private structure
2821 *
2822 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2823 * interrupts from the kernel.
2824 **/
2825 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2826 {
2827 struct net_device *netdev = adapter->netdev;
2828 int vector, err;
2829 int ri = 0, ti = 0;
2830
2831 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2832 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2833 struct msix_entry *entry = &adapter->msix_entries[vector];
2834
2835 if (q_vector->tx.ring && q_vector->rx.ring) {
2836 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2837 "%s-%s-%d", netdev->name, "TxRx", ri++);
2838 ti++;
2839 } else if (q_vector->rx.ring) {
2840 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2841 "%s-%s-%d", netdev->name, "rx", ri++);
2842 } else if (q_vector->tx.ring) {
2843 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2844 "%s-%s-%d", netdev->name, "tx", ti++);
2845 } else {
2846 /* skip this unused q_vector */
2847 continue;
2848 }
2849 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2850 q_vector->name, q_vector);
2851 if (err) {
2852 e_err(probe, "request_irq failed for MSIX interrupt "
2853 "Error: %d\n", err);
2854 goto free_queue_irqs;
2855 }
2856 /* If Flow Director is enabled, set interrupt affinity */
2857 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2858 /* assign the mask for this irq */
2859 irq_set_affinity_hint(entry->vector,
2860 &q_vector->affinity_mask);
2861 }
2862 }
2863
2864 err = request_irq(adapter->msix_entries[vector].vector,
2865 ixgbe_msix_other, 0, netdev->name, adapter);
2866 if (err) {
2867 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2868 goto free_queue_irqs;
2869 }
2870
2871 return 0;
2872
2873 free_queue_irqs:
2874 while (vector) {
2875 vector--;
2876 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2877 NULL);
2878 free_irq(adapter->msix_entries[vector].vector,
2879 adapter->q_vector[vector]);
2880 }
2881 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2882 pci_disable_msix(adapter->pdev);
2883 kfree(adapter->msix_entries);
2884 adapter->msix_entries = NULL;
2885 return err;
2886 }
2887
2888 /**
2889 * ixgbe_intr - legacy mode Interrupt Handler
2890 * @irq: interrupt number
2891 * @data: pointer to a network interface device structure
2892 **/
2893 static irqreturn_t ixgbe_intr(int irq, void *data)
2894 {
2895 struct ixgbe_adapter *adapter = data;
2896 struct ixgbe_hw *hw = &adapter->hw;
2897 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2898 u32 eicr;
2899
2900 /*
2901 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2902 * before the read of EICR.
2903 */
2904 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2905
2906 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2907 * therefore no explicit interrupt disable is necessary */
2908 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2909 if (!eicr) {
2910 /*
2911 * shared interrupt alert!
2912 * make sure interrupts are enabled because the read will
2913 * have disabled interrupts due to EIAM
2914 * finish the workaround of silicon errata on 82598. Unmask
2915 * the interrupt that we masked before the EICR read.
2916 */
2917 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2918 ixgbe_irq_enable(adapter, true, true);
2919 return IRQ_NONE; /* Not our interrupt */
2920 }
2921
2922 if (eicr & IXGBE_EICR_LSC)
2923 ixgbe_check_lsc(adapter);
2924
2925 switch (hw->mac.type) {
2926 case ixgbe_mac_82599EB:
2927 ixgbe_check_sfp_event(adapter, eicr);
2928 /* Fall through */
2929 case ixgbe_mac_X540:
2930 case ixgbe_mac_X550:
2931 case ixgbe_mac_X550EM_x:
2932 if (eicr & IXGBE_EICR_ECC) {
2933 e_info(link, "Received ECC Err, initiating reset\n");
2934 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2935 ixgbe_service_event_schedule(adapter);
2936 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2937 }
2938 ixgbe_check_overtemp_event(adapter, eicr);
2939 break;
2940 default:
2941 break;
2942 }
2943
2944 ixgbe_check_fan_failure(adapter, eicr);
2945 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2946 ixgbe_ptp_check_pps_event(adapter, eicr);
2947
2948 /* would disable interrupts here but EIAM disabled it */
2949 napi_schedule(&q_vector->napi);
2950
2951 /*
2952 * re-enable link(maybe) and non-queue interrupts, no flush.
2953 * ixgbe_poll will re-enable the queue interrupts
2954 */
2955 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2956 ixgbe_irq_enable(adapter, false, false);
2957
2958 return IRQ_HANDLED;
2959 }
2960
2961 /**
2962 * ixgbe_request_irq - initialize interrupts
2963 * @adapter: board private structure
2964 *
2965 * Attempts to configure interrupts using the best available
2966 * capabilities of the hardware and kernel.
2967 **/
2968 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2969 {
2970 struct net_device *netdev = adapter->netdev;
2971 int err;
2972
2973 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2974 err = ixgbe_request_msix_irqs(adapter);
2975 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2976 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2977 netdev->name, adapter);
2978 else
2979 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2980 netdev->name, adapter);
2981
2982 if (err)
2983 e_err(probe, "request_irq failed, Error %d\n", err);
2984
2985 return err;
2986 }
2987
2988 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2989 {
2990 int vector;
2991
2992 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2993 free_irq(adapter->pdev->irq, adapter);
2994 return;
2995 }
2996
2997 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2998 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2999 struct msix_entry *entry = &adapter->msix_entries[vector];
3000
3001 /* free only the irqs that were actually requested */
3002 if (!q_vector->rx.ring && !q_vector->tx.ring)
3003 continue;
3004
3005 /* clear the affinity_mask in the IRQ descriptor */
3006 irq_set_affinity_hint(entry->vector, NULL);
3007
3008 free_irq(entry->vector, q_vector);
3009 }
3010
3011 free_irq(adapter->msix_entries[vector++].vector, adapter);
3012 }
3013
3014 /**
3015 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3016 * @adapter: board private structure
3017 **/
3018 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3019 {
3020 switch (adapter->hw.mac.type) {
3021 case ixgbe_mac_82598EB:
3022 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
3023 break;
3024 case ixgbe_mac_82599EB:
3025 case ixgbe_mac_X540:
3026 case ixgbe_mac_X550:
3027 case ixgbe_mac_X550EM_x:
3028 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3029 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
3030 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
3031 break;
3032 default:
3033 break;
3034 }
3035 IXGBE_WRITE_FLUSH(&adapter->hw);
3036 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3037 int vector;
3038
3039 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3040 synchronize_irq(adapter->msix_entries[vector].vector);
3041
3042 synchronize_irq(adapter->msix_entries[vector++].vector);
3043 } else {
3044 synchronize_irq(adapter->pdev->irq);
3045 }
3046 }
3047
3048 /**
3049 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3050 *
3051 **/
3052 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3053 {
3054 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3055
3056 ixgbe_write_eitr(q_vector);
3057
3058 ixgbe_set_ivar(adapter, 0, 0, 0);
3059 ixgbe_set_ivar(adapter, 1, 0, 0);
3060
3061 e_info(hw, "Legacy interrupt IVAR setup done\n");
3062 }
3063
3064 /**
3065 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3066 * @adapter: board private structure
3067 * @ring: structure containing ring specific data
3068 *
3069 * Configure the Tx descriptor ring after a reset.
3070 **/
3071 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3072 struct ixgbe_ring *ring)
3073 {
3074 struct ixgbe_hw *hw = &adapter->hw;
3075 u64 tdba = ring->dma;
3076 int wait_loop = 10;
3077 u32 txdctl = IXGBE_TXDCTL_ENABLE;
3078 u8 reg_idx = ring->reg_idx;
3079
3080 /* disable queue to avoid issues while updating state */
3081 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
3082 IXGBE_WRITE_FLUSH(hw);
3083
3084 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
3085 (tdba & DMA_BIT_MASK(32)));
3086 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3087 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3088 ring->count * sizeof(union ixgbe_adv_tx_desc));
3089 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3090 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
3091 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
3092
3093 /*
3094 * set WTHRESH to encourage burst writeback, it should not be set
3095 * higher than 1 when:
3096 * - ITR is 0 as it could cause false TX hangs
3097 * - ITR is set to > 100k int/sec and BQL is enabled
3098 *
3099 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3100 * to or less than the number of on chip descriptors, which is
3101 * currently 40.
3102 */
3103 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3104 txdctl |= (1 << 16); /* WTHRESH = 1 */
3105 else
3106 txdctl |= (8 << 16); /* WTHRESH = 8 */
3107
3108 /*
3109 * Setting PTHRESH to 32 both improves performance
3110 * and avoids a TX hang with DFP enabled
3111 */
3112 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3113 32; /* PTHRESH = 32 */
3114
3115 /* reinitialize flowdirector state */
3116 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3117 ring->atr_sample_rate = adapter->atr_sample_rate;
3118 ring->atr_count = 0;
3119 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3120 } else {
3121 ring->atr_sample_rate = 0;
3122 }
3123
3124 /* initialize XPS */
3125 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3126 struct ixgbe_q_vector *q_vector = ring->q_vector;
3127
3128 if (q_vector)
3129 netif_set_xps_queue(ring->netdev,
3130 &q_vector->affinity_mask,
3131 ring->queue_index);
3132 }
3133
3134 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3135
3136 /* enable queue */
3137 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3138
3139 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3140 if (hw->mac.type == ixgbe_mac_82598EB &&
3141 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3142 return;
3143
3144 /* poll to verify queue is enabled */
3145 do {
3146 usleep_range(1000, 2000);
3147 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3148 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3149 if (!wait_loop)
3150 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
3151 }
3152
3153 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3154 {
3155 struct ixgbe_hw *hw = &adapter->hw;
3156 u32 rttdcs, mtqc;
3157 u8 tcs = netdev_get_num_tc(adapter->netdev);
3158
3159 if (hw->mac.type == ixgbe_mac_82598EB)
3160 return;
3161
3162 /* disable the arbiter while setting MTQC */
3163 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3164 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3165 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3166
3167 /* set transmit pool layout */
3168 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3169 mtqc = IXGBE_MTQC_VT_ENA;
3170 if (tcs > 4)
3171 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3172 else if (tcs > 1)
3173 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3174 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3175 mtqc |= IXGBE_MTQC_32VF;
3176 else
3177 mtqc |= IXGBE_MTQC_64VF;
3178 } else {
3179 if (tcs > 4)
3180 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3181 else if (tcs > 1)
3182 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3183 else
3184 mtqc = IXGBE_MTQC_64Q_1PB;
3185 }
3186
3187 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3188
3189 /* Enable Security TX Buffer IFG for multiple pb */
3190 if (tcs) {
3191 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3192 sectx |= IXGBE_SECTX_DCB;
3193 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3194 }
3195
3196 /* re-enable the arbiter */
3197 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3198 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3199 }
3200
3201 /**
3202 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3203 * @adapter: board private structure
3204 *
3205 * Configure the Tx unit of the MAC after a reset.
3206 **/
3207 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3208 {
3209 struct ixgbe_hw *hw = &adapter->hw;
3210 u32 dmatxctl;
3211 u32 i;
3212
3213 ixgbe_setup_mtqc(adapter);
3214
3215 if (hw->mac.type != ixgbe_mac_82598EB) {
3216 /* DMATXCTL.EN must be before Tx queues are enabled */
3217 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3218 dmatxctl |= IXGBE_DMATXCTL_TE;
3219 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3220 }
3221
3222 /* Setup the HW Tx Head and Tail descriptor pointers */
3223 for (i = 0; i < adapter->num_tx_queues; i++)
3224 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3225 }
3226
3227 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3228 struct ixgbe_ring *ring)
3229 {
3230 struct ixgbe_hw *hw = &adapter->hw;
3231 u8 reg_idx = ring->reg_idx;
3232 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3233
3234 srrctl |= IXGBE_SRRCTL_DROP_EN;
3235
3236 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3237 }
3238
3239 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3240 struct ixgbe_ring *ring)
3241 {
3242 struct ixgbe_hw *hw = &adapter->hw;
3243 u8 reg_idx = ring->reg_idx;
3244 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3245
3246 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3247
3248 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3249 }
3250
3251 #ifdef CONFIG_IXGBE_DCB
3252 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3253 #else
3254 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3255 #endif
3256 {
3257 int i;
3258 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3259
3260 if (adapter->ixgbe_ieee_pfc)
3261 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3262
3263 /*
3264 * We should set the drop enable bit if:
3265 * SR-IOV is enabled
3266 * or
3267 * Number of Rx queues > 1 and flow control is disabled
3268 *
3269 * This allows us to avoid head of line blocking for security
3270 * and performance reasons.
3271 */
3272 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3273 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3274 for (i = 0; i < adapter->num_rx_queues; i++)
3275 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3276 } else {
3277 for (i = 0; i < adapter->num_rx_queues; i++)
3278 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3279 }
3280 }
3281
3282 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3283
3284 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3285 struct ixgbe_ring *rx_ring)
3286 {
3287 struct ixgbe_hw *hw = &adapter->hw;
3288 u32 srrctl;
3289 u8 reg_idx = rx_ring->reg_idx;
3290
3291 if (hw->mac.type == ixgbe_mac_82598EB) {
3292 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3293
3294 /*
3295 * if VMDq is not active we must program one srrctl register
3296 * per RSS queue since we have enabled RDRXCTL.MVMEN
3297 */
3298 reg_idx &= mask;
3299 }
3300
3301 /* configure header buffer length, needed for RSC */
3302 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3303
3304 /* configure the packet buffer length */
3305 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3306
3307 /* configure descriptor type */
3308 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3309
3310 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3311 }
3312
3313 /**
3314 * Return a number of entries in the RSS indirection table
3315 *
3316 * @adapter: device handle
3317 *
3318 * - 82598/82599/X540: 128
3319 * - X550(non-SRIOV mode): 512
3320 * - X550(SRIOV mode): 64
3321 */
3322 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
3323 {
3324 if (adapter->hw.mac.type < ixgbe_mac_X550)
3325 return 128;
3326 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3327 return 64;
3328 else
3329 return 512;
3330 }
3331
3332 /**
3333 * Write the RETA table to HW
3334 *
3335 * @adapter: device handle
3336 *
3337 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3338 */
3339 void ixgbe_store_reta(struct ixgbe_adapter *adapter)
3340 {
3341 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3342 struct ixgbe_hw *hw = &adapter->hw;
3343 u32 reta = 0;
3344 u32 indices_multi;
3345 u8 *indir_tbl = adapter->rss_indir_tbl;
3346
3347 /* Fill out the redirection table as follows:
3348 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3349 * indices.
3350 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3351 * - X550: 8 bit wide entries containing 6 bit RSS index
3352 */
3353 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3354 indices_multi = 0x11;
3355 else
3356 indices_multi = 0x1;
3357
3358 /* Write redirection table to HW */
3359 for (i = 0; i < reta_entries; i++) {
3360 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
3361 if ((i & 3) == 3) {
3362 if (i < 128)
3363 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3364 else
3365 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3366 reta);
3367 reta = 0;
3368 }
3369 }
3370 }
3371
3372 /**
3373 * Write the RETA table to HW (for x550 devices in SRIOV mode)
3374 *
3375 * @adapter: device handle
3376 *
3377 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3378 */
3379 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
3380 {
3381 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3382 struct ixgbe_hw *hw = &adapter->hw;
3383 u32 vfreta = 0;
3384 unsigned int pf_pool = adapter->num_vfs;
3385
3386 /* Write redirection table to HW */
3387 for (i = 0; i < reta_entries; i++) {
3388 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3389 if ((i & 3) == 3) {
3390 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3391 vfreta);
3392 vfreta = 0;
3393 }
3394 }
3395 }
3396
3397 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3398 {
3399 struct ixgbe_hw *hw = &adapter->hw;
3400 u32 i, j;
3401 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3402 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3403
3404 /* Program table for at least 2 queues w/ SR-IOV so that VFs can
3405 * make full use of any rings they may have. We will use the
3406 * PSRTYPE register to control how many rings we use within the PF.
3407 */
3408 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3409 rss_i = 2;
3410
3411 /* Fill out hash function seeds */
3412 for (i = 0; i < 10; i++)
3413 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3414
3415 /* Fill out redirection table */
3416 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3417
3418 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3419 if (j == rss_i)
3420 j = 0;
3421
3422 adapter->rss_indir_tbl[i] = j;
3423 }
3424
3425 ixgbe_store_reta(adapter);
3426 }
3427
3428 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3429 {
3430 struct ixgbe_hw *hw = &adapter->hw;
3431 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3432 unsigned int pf_pool = adapter->num_vfs;
3433 int i, j;
3434
3435 /* Fill out hash function seeds */
3436 for (i = 0; i < 10; i++)
3437 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3438 adapter->rss_key[i]);
3439
3440 /* Fill out the redirection table */
3441 for (i = 0, j = 0; i < 64; i++, j++) {
3442 if (j == rss_i)
3443 j = 0;
3444
3445 adapter->rss_indir_tbl[i] = j;
3446 }
3447
3448 ixgbe_store_vfreta(adapter);
3449 }
3450
3451 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3452 {
3453 struct ixgbe_hw *hw = &adapter->hw;
3454 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
3455 u32 rxcsum;
3456
3457 /* Disable indicating checksum in descriptor, enables RSS hash */
3458 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3459 rxcsum |= IXGBE_RXCSUM_PCSD;
3460 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3461
3462 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3463 if (adapter->ring_feature[RING_F_RSS].mask)
3464 mrqc = IXGBE_MRQC_RSSEN;
3465 } else {
3466 u8 tcs = netdev_get_num_tc(adapter->netdev);
3467
3468 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3469 if (tcs > 4)
3470 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3471 else if (tcs > 1)
3472 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3473 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3474 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3475 else
3476 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3477 } else {
3478 if (tcs > 4)
3479 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3480 else if (tcs > 1)
3481 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3482 else
3483 mrqc = IXGBE_MRQC_RSSEN;
3484 }
3485 }
3486
3487 /* Perform hash on these packet types */
3488 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3489 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3490 IXGBE_MRQC_RSS_FIELD_IPV6 |
3491 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3492
3493 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3494 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3495 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3496 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3497
3498 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
3499 if ((hw->mac.type >= ixgbe_mac_X550) &&
3500 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3501 unsigned int pf_pool = adapter->num_vfs;
3502
3503 /* Enable VF RSS mode */
3504 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3505 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3506
3507 /* Setup RSS through the VF registers */
3508 ixgbe_setup_vfreta(adapter);
3509 vfmrqc = IXGBE_MRQC_RSSEN;
3510 vfmrqc |= rss_field;
3511 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3512 } else {
3513 ixgbe_setup_reta(adapter);
3514 mrqc |= rss_field;
3515 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3516 }
3517 }
3518
3519 /**
3520 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3521 * @adapter: address of board private structure
3522 * @index: index of ring to set
3523 **/
3524 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3525 struct ixgbe_ring *ring)
3526 {
3527 struct ixgbe_hw *hw = &adapter->hw;
3528 u32 rscctrl;
3529 u8 reg_idx = ring->reg_idx;
3530
3531 if (!ring_is_rsc_enabled(ring))
3532 return;
3533
3534 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3535 rscctrl |= IXGBE_RSCCTL_RSCEN;
3536 /*
3537 * we must limit the number of descriptors so that the
3538 * total size of max desc * buf_len is not greater
3539 * than 65536
3540 */
3541 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3542 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3543 }
3544
3545 #define IXGBE_MAX_RX_DESC_POLL 10
3546 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3547 struct ixgbe_ring *ring)
3548 {
3549 struct ixgbe_hw *hw = &adapter->hw;
3550 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3551 u32 rxdctl;
3552 u8 reg_idx = ring->reg_idx;
3553
3554 if (ixgbe_removed(hw->hw_addr))
3555 return;
3556 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3557 if (hw->mac.type == ixgbe_mac_82598EB &&
3558 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3559 return;
3560
3561 do {
3562 usleep_range(1000, 2000);
3563 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3564 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3565
3566 if (!wait_loop) {
3567 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3568 "the polling period\n", reg_idx);
3569 }
3570 }
3571
3572 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3573 struct ixgbe_ring *ring)
3574 {
3575 struct ixgbe_hw *hw = &adapter->hw;
3576 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3577 u32 rxdctl;
3578 u8 reg_idx = ring->reg_idx;
3579
3580 if (ixgbe_removed(hw->hw_addr))
3581 return;
3582 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3583 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3584
3585 /* write value back with RXDCTL.ENABLE bit cleared */
3586 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3587
3588 if (hw->mac.type == ixgbe_mac_82598EB &&
3589 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3590 return;
3591
3592 /* the hardware may take up to 100us to really disable the rx queue */
3593 do {
3594 udelay(10);
3595 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3596 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3597
3598 if (!wait_loop) {
3599 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3600 "the polling period\n", reg_idx);
3601 }
3602 }
3603
3604 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3605 struct ixgbe_ring *ring)
3606 {
3607 struct ixgbe_hw *hw = &adapter->hw;
3608 u64 rdba = ring->dma;
3609 u32 rxdctl;
3610 u8 reg_idx = ring->reg_idx;
3611
3612 /* disable queue to avoid issues while updating state */
3613 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3614 ixgbe_disable_rx_queue(adapter, ring);
3615
3616 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3617 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3618 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3619 ring->count * sizeof(union ixgbe_adv_rx_desc));
3620 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3621 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3622 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
3623
3624 ixgbe_configure_srrctl(adapter, ring);
3625 ixgbe_configure_rscctl(adapter, ring);
3626
3627 if (hw->mac.type == ixgbe_mac_82598EB) {
3628 /*
3629 * enable cache line friendly hardware writes:
3630 * PTHRESH=32 descriptors (half the internal cache),
3631 * this also removes ugly rx_no_buffer_count increment
3632 * HTHRESH=4 descriptors (to minimize latency on fetch)
3633 * WTHRESH=8 burst writeback up to two cache lines
3634 */
3635 rxdctl &= ~0x3FFFFF;
3636 rxdctl |= 0x080420;
3637 }
3638
3639 /* enable receive descriptor ring */
3640 rxdctl |= IXGBE_RXDCTL_ENABLE;
3641 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3642
3643 ixgbe_rx_desc_queue_enable(adapter, ring);
3644 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3645 }
3646
3647 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3648 {
3649 struct ixgbe_hw *hw = &adapter->hw;
3650 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3651 u16 pool;
3652
3653 /* PSRTYPE must be initialized in non 82598 adapters */
3654 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3655 IXGBE_PSRTYPE_UDPHDR |
3656 IXGBE_PSRTYPE_IPV4HDR |
3657 IXGBE_PSRTYPE_L2HDR |
3658 IXGBE_PSRTYPE_IPV6HDR;
3659
3660 if (hw->mac.type == ixgbe_mac_82598EB)
3661 return;
3662
3663 if (rss_i > 3)
3664 psrtype |= 2 << 29;
3665 else if (rss_i > 1)
3666 psrtype |= 1 << 29;
3667
3668 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3669 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
3670 }
3671
3672 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3673 {
3674 struct ixgbe_hw *hw = &adapter->hw;
3675 u32 reg_offset, vf_shift;
3676 u32 gcr_ext, vmdctl;
3677 int i;
3678
3679 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3680 return;
3681
3682 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3683 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3684 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3685 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3686 vmdctl |= IXGBE_VT_CTL_REPLEN;
3687 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3688
3689 vf_shift = VMDQ_P(0) % 32;
3690 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3691
3692 /* Enable only the PF's pool for Tx/Rx */
3693 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3694 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3695 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3696 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3697 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
3698 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3699
3700 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3701 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3702
3703 /*
3704 * Set up VF register offsets for selected VT Mode,
3705 * i.e. 32 or 64 VFs for SR-IOV
3706 */
3707 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3708 case IXGBE_82599_VMDQ_8Q_MASK:
3709 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3710 break;
3711 case IXGBE_82599_VMDQ_4Q_MASK:
3712 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3713 break;
3714 default:
3715 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3716 break;
3717 }
3718
3719 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3720
3721
3722 /* Enable MAC Anti-Spoofing */
3723 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3724 adapter->num_vfs);
3725
3726 /* Ensure LLDP is set for Ethertype Antispoofing if we will be
3727 * calling set_ethertype_anti_spoofing for each VF in loop below
3728 */
3729 if (hw->mac.ops.set_ethertype_anti_spoofing)
3730 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
3731 (IXGBE_ETQF_FILTER_EN | /* enable filter */
3732 IXGBE_ETQF_TX_ANTISPOOF | /* tx antispoof */
3733 IXGBE_ETH_P_LLDP)); /* LLDP eth type */
3734
3735 /* For VFs that have spoof checking turned off */
3736 for (i = 0; i < adapter->num_vfs; i++) {
3737 if (!adapter->vfinfo[i].spoofchk_enabled)
3738 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3739
3740 /* enable ethertype anti spoofing if hw supports it */
3741 if (hw->mac.ops.set_ethertype_anti_spoofing)
3742 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
3743
3744 /* Enable/Disable RSS query feature */
3745 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
3746 adapter->vfinfo[i].rss_query_enabled);
3747 }
3748 }
3749
3750 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3751 {
3752 struct ixgbe_hw *hw = &adapter->hw;
3753 struct net_device *netdev = adapter->netdev;
3754 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3755 struct ixgbe_ring *rx_ring;
3756 int i;
3757 u32 mhadd, hlreg0;
3758
3759 #ifdef IXGBE_FCOE
3760 /* adjust max frame to be able to do baby jumbo for FCoE */
3761 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3762 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3763 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3764
3765 #endif /* IXGBE_FCOE */
3766
3767 /* adjust max frame to be at least the size of a standard frame */
3768 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3769 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3770
3771 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3772 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3773 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3774 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3775
3776 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3777 }
3778
3779 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3780 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3781 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3782 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3783
3784 /*
3785 * Setup the HW Rx Head and Tail Descriptor Pointers and
3786 * the Base and Length of the Rx Descriptor Ring
3787 */
3788 for (i = 0; i < adapter->num_rx_queues; i++) {
3789 rx_ring = adapter->rx_ring[i];
3790 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3791 set_ring_rsc_enabled(rx_ring);
3792 else
3793 clear_ring_rsc_enabled(rx_ring);
3794 }
3795 }
3796
3797 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3798 {
3799 struct ixgbe_hw *hw = &adapter->hw;
3800 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3801
3802 switch (hw->mac.type) {
3803 case ixgbe_mac_82598EB:
3804 /*
3805 * For VMDq support of different descriptor types or
3806 * buffer sizes through the use of multiple SRRCTL
3807 * registers, RDRXCTL.MVMEN must be set to 1
3808 *
3809 * also, the manual doesn't mention it clearly but DCA hints
3810 * will only use queue 0's tags unless this bit is set. Side
3811 * effects of setting this bit are only that SRRCTL must be
3812 * fully programmed [0..15]
3813 */
3814 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3815 break;
3816 case ixgbe_mac_X550:
3817 case ixgbe_mac_X550EM_x:
3818 if (adapter->num_vfs)
3819 rdrxctl |= IXGBE_RDRXCTL_PSP;
3820 /* fall through for older HW */
3821 case ixgbe_mac_82599EB:
3822 case ixgbe_mac_X540:
3823 /* Disable RSC for ACK packets */
3824 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3825 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3826 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3827 /* hardware requires some bits to be set by default */
3828 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3829 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3830 break;
3831 default:
3832 /* We should do nothing since we don't know this hardware */
3833 return;
3834 }
3835
3836 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3837 }
3838
3839 /**
3840 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3841 * @adapter: board private structure
3842 *
3843 * Configure the Rx unit of the MAC after a reset.
3844 **/
3845 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3846 {
3847 struct ixgbe_hw *hw = &adapter->hw;
3848 int i;
3849 u32 rxctrl, rfctl;
3850
3851 /* disable receives while setting up the descriptors */
3852 hw->mac.ops.disable_rx(hw);
3853
3854 ixgbe_setup_psrtype(adapter);
3855 ixgbe_setup_rdrxctl(adapter);
3856
3857 /* RSC Setup */
3858 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3859 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3860 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3861 rfctl |= IXGBE_RFCTL_RSC_DIS;
3862 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3863
3864 /* Program registers for the distribution of queues */
3865 ixgbe_setup_mrqc(adapter);
3866
3867 /* set_rx_buffer_len must be called before ring initialization */
3868 ixgbe_set_rx_buffer_len(adapter);
3869
3870 /*
3871 * Setup the HW Rx Head and Tail Descriptor Pointers and
3872 * the Base and Length of the Rx Descriptor Ring
3873 */
3874 for (i = 0; i < adapter->num_rx_queues; i++)
3875 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3876
3877 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3878 /* disable drop enable for 82598 parts */
3879 if (hw->mac.type == ixgbe_mac_82598EB)
3880 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3881
3882 /* enable all receives */
3883 rxctrl |= IXGBE_RXCTRL_RXEN;
3884 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3885 }
3886
3887 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3888 __be16 proto, u16 vid)
3889 {
3890 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3891 struct ixgbe_hw *hw = &adapter->hw;
3892
3893 /* add VID to filter table */
3894 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3895 set_bit(vid, adapter->active_vlans);
3896
3897 return 0;
3898 }
3899
3900 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3901 __be16 proto, u16 vid)
3902 {
3903 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3904 struct ixgbe_hw *hw = &adapter->hw;
3905
3906 /* remove VID from filter table */
3907 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3908 clear_bit(vid, adapter->active_vlans);
3909
3910 return 0;
3911 }
3912
3913 /**
3914 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3915 * @adapter: driver data
3916 */
3917 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3918 {
3919 struct ixgbe_hw *hw = &adapter->hw;
3920 u32 vlnctrl;
3921 int i, j;
3922
3923 switch (hw->mac.type) {
3924 case ixgbe_mac_82598EB:
3925 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3926 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3927 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3928 break;
3929 case ixgbe_mac_82599EB:
3930 case ixgbe_mac_X540:
3931 case ixgbe_mac_X550:
3932 case ixgbe_mac_X550EM_x:
3933 for (i = 0; i < adapter->num_rx_queues; i++) {
3934 struct ixgbe_ring *ring = adapter->rx_ring[i];
3935
3936 if (ring->l2_accel_priv)
3937 continue;
3938 j = ring->reg_idx;
3939 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3940 vlnctrl &= ~IXGBE_RXDCTL_VME;
3941 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3942 }
3943 break;
3944 default:
3945 break;
3946 }
3947 }
3948
3949 /**
3950 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3951 * @adapter: driver data
3952 */
3953 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3954 {
3955 struct ixgbe_hw *hw = &adapter->hw;
3956 u32 vlnctrl;
3957 int i, j;
3958
3959 switch (hw->mac.type) {
3960 case ixgbe_mac_82598EB:
3961 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3962 vlnctrl |= IXGBE_VLNCTRL_VME;
3963 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3964 break;
3965 case ixgbe_mac_82599EB:
3966 case ixgbe_mac_X540:
3967 case ixgbe_mac_X550:
3968 case ixgbe_mac_X550EM_x:
3969 for (i = 0; i < adapter->num_rx_queues; i++) {
3970 struct ixgbe_ring *ring = adapter->rx_ring[i];
3971
3972 if (ring->l2_accel_priv)
3973 continue;
3974 j = ring->reg_idx;
3975 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3976 vlnctrl |= IXGBE_RXDCTL_VME;
3977 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3978 }
3979 break;
3980 default:
3981 break;
3982 }
3983 }
3984
3985 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3986 {
3987 u16 vid;
3988
3989 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
3990
3991 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3992 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
3993 }
3994
3995 /**
3996 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
3997 * @netdev: network interface device structure
3998 *
3999 * Writes multicast address list to the MTA hash table.
4000 * Returns: -ENOMEM on failure
4001 * 0 on no addresses written
4002 * X on writing X addresses to MTA
4003 **/
4004 static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4005 {
4006 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4007 struct ixgbe_hw *hw = &adapter->hw;
4008
4009 if (!netif_running(netdev))
4010 return 0;
4011
4012 if (hw->mac.ops.update_mc_addr_list)
4013 hw->mac.ops.update_mc_addr_list(hw, netdev);
4014 else
4015 return -ENOMEM;
4016
4017 #ifdef CONFIG_PCI_IOV
4018 ixgbe_restore_vf_multicasts(adapter);
4019 #endif
4020
4021 return netdev_mc_count(netdev);
4022 }
4023
4024 #ifdef CONFIG_PCI_IOV
4025 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4026 {
4027 struct ixgbe_hw *hw = &adapter->hw;
4028 int i;
4029 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4030 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
4031 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
4032 adapter->mac_table[i].queue,
4033 IXGBE_RAH_AV);
4034 else
4035 hw->mac.ops.clear_rar(hw, i);
4036
4037 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED);
4038 }
4039 }
4040 #endif
4041
4042 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4043 {
4044 struct ixgbe_hw *hw = &adapter->hw;
4045 int i;
4046 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4047 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
4048 if (adapter->mac_table[i].state &
4049 IXGBE_MAC_STATE_IN_USE)
4050 hw->mac.ops.set_rar(hw, i,
4051 adapter->mac_table[i].addr,
4052 adapter->mac_table[i].queue,
4053 IXGBE_RAH_AV);
4054 else
4055 hw->mac.ops.clear_rar(hw, i);
4056
4057 adapter->mac_table[i].state &=
4058 ~(IXGBE_MAC_STATE_MODIFIED);
4059 }
4060 }
4061 }
4062
4063 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4064 {
4065 int i;
4066 struct ixgbe_hw *hw = &adapter->hw;
4067
4068 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4069 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
4070 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
4071 eth_zero_addr(adapter->mac_table[i].addr);
4072 adapter->mac_table[i].queue = 0;
4073 }
4074 ixgbe_sync_mac_table(adapter);
4075 }
4076
4077 static int ixgbe_available_rars(struct ixgbe_adapter *adapter)
4078 {
4079 struct ixgbe_hw *hw = &adapter->hw;
4080 int i, count = 0;
4081
4082 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4083 if (adapter->mac_table[i].state == 0)
4084 count++;
4085 }
4086 return count;
4087 }
4088
4089 /* this function destroys the first RAR entry */
4090 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter,
4091 u8 *addr)
4092 {
4093 struct ixgbe_hw *hw = &adapter->hw;
4094
4095 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN);
4096 adapter->mac_table[0].queue = VMDQ_P(0);
4097 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
4098 IXGBE_MAC_STATE_IN_USE);
4099 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
4100 adapter->mac_table[0].queue,
4101 IXGBE_RAH_AV);
4102 }
4103
4104 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
4105 {
4106 struct ixgbe_hw *hw = &adapter->hw;
4107 int i;
4108
4109 if (is_zero_ether_addr(addr))
4110 return -EINVAL;
4111
4112 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4113 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
4114 continue;
4115 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
4116 IXGBE_MAC_STATE_IN_USE);
4117 ether_addr_copy(adapter->mac_table[i].addr, addr);
4118 adapter->mac_table[i].queue = queue;
4119 ixgbe_sync_mac_table(adapter);
4120 return i;
4121 }
4122 return -ENOMEM;
4123 }
4124
4125 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
4126 {
4127 /* search table for addr, if found, set to 0 and sync */
4128 int i;
4129 struct ixgbe_hw *hw = &adapter->hw;
4130
4131 if (is_zero_ether_addr(addr))
4132 return -EINVAL;
4133
4134 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4135 if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
4136 adapter->mac_table[i].queue == queue) {
4137 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
4138 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
4139 eth_zero_addr(adapter->mac_table[i].addr);
4140 adapter->mac_table[i].queue = 0;
4141 ixgbe_sync_mac_table(adapter);
4142 return 0;
4143 }
4144 }
4145 return -ENOMEM;
4146 }
4147 /**
4148 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4149 * @netdev: network interface device structure
4150 *
4151 * Writes unicast address list to the RAR table.
4152 * Returns: -ENOMEM on failure/insufficient address space
4153 * 0 on no addresses written
4154 * X on writing X addresses to the RAR table
4155 **/
4156 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
4157 {
4158 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4159 int count = 0;
4160
4161 /* return ENOMEM indicating insufficient memory for addresses */
4162 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
4163 return -ENOMEM;
4164
4165 if (!netdev_uc_empty(netdev)) {
4166 struct netdev_hw_addr *ha;
4167 netdev_for_each_uc_addr(ha, netdev) {
4168 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4169 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
4170 count++;
4171 }
4172 }
4173 return count;
4174 }
4175
4176 /**
4177 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
4178 * @netdev: network interface device structure
4179 *
4180 * The set_rx_method entry point is called whenever the unicast/multicast
4181 * address list or the network interface flags are updated. This routine is
4182 * responsible for configuring the hardware for proper unicast, multicast and
4183 * promiscuous mode.
4184 **/
4185 void ixgbe_set_rx_mode(struct net_device *netdev)
4186 {
4187 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4188 struct ixgbe_hw *hw = &adapter->hw;
4189 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
4190 u32 vlnctrl;
4191 int count;
4192
4193 /* Check for Promiscuous and All Multicast modes */
4194 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4195 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4196
4197 /* set all bits that we expect to always be set */
4198 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
4199 fctrl |= IXGBE_FCTRL_BAM;
4200 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4201 fctrl |= IXGBE_FCTRL_PMCF;
4202
4203 /* clear the bits we are changing the status of */
4204 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4205 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4206 if (netdev->flags & IFF_PROMISC) {
4207 hw->addr_ctrl.user_set_promisc = true;
4208 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4209 vmolr |= IXGBE_VMOLR_MPE;
4210 /* Only disable hardware filter vlans in promiscuous mode
4211 * if SR-IOV and VMDQ are disabled - otherwise ensure
4212 * that hardware VLAN filters remain enabled.
4213 */
4214 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
4215 IXGBE_FLAG_SRIOV_ENABLED))
4216 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4217 } else {
4218 if (netdev->flags & IFF_ALLMULTI) {
4219 fctrl |= IXGBE_FCTRL_MPE;
4220 vmolr |= IXGBE_VMOLR_MPE;
4221 }
4222 vlnctrl |= IXGBE_VLNCTRL_VFE;
4223 hw->addr_ctrl.user_set_promisc = false;
4224 }
4225
4226 /*
4227 * Write addresses to available RAR registers, if there is not
4228 * sufficient space to store all the addresses then enable
4229 * unicast promiscuous mode
4230 */
4231 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0));
4232 if (count < 0) {
4233 fctrl |= IXGBE_FCTRL_UPE;
4234 vmolr |= IXGBE_VMOLR_ROPE;
4235 }
4236
4237 /* Write addresses to the MTA, if the attempt fails
4238 * then we should just turn on promiscuous mode so
4239 * that we can at least receive multicast traffic
4240 */
4241 count = ixgbe_write_mc_addr_list(netdev);
4242 if (count < 0) {
4243 fctrl |= IXGBE_FCTRL_MPE;
4244 vmolr |= IXGBE_VMOLR_MPE;
4245 } else if (count) {
4246 vmolr |= IXGBE_VMOLR_ROMPE;
4247 }
4248
4249 if (hw->mac.type != ixgbe_mac_82598EB) {
4250 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
4251 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4252 IXGBE_VMOLR_ROPE);
4253 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
4254 }
4255
4256 /* This is useful for sniffing bad packets. */
4257 if (adapter->netdev->features & NETIF_F_RXALL) {
4258 /* UPE and MPE will be handled by normal PROMISC logic
4259 * in e1000e_set_rx_mode */
4260 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4261 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4262 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4263
4264 fctrl &= ~(IXGBE_FCTRL_DPF);
4265 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4266 }
4267
4268 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4269 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4270
4271 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
4272 ixgbe_vlan_strip_enable(adapter);
4273 else
4274 ixgbe_vlan_strip_disable(adapter);
4275 }
4276
4277 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4278 {
4279 int q_idx;
4280
4281 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4282 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
4283 napi_enable(&adapter->q_vector[q_idx]->napi);
4284 }
4285 }
4286
4287 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4288 {
4289 int q_idx;
4290
4291 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4292 napi_disable(&adapter->q_vector[q_idx]->napi);
4293 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
4294 pr_info("QV %d locked\n", q_idx);
4295 usleep_range(1000, 20000);
4296 }
4297 }
4298 }
4299
4300 static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter)
4301 {
4302 switch (adapter->hw.mac.type) {
4303 case ixgbe_mac_X550:
4304 case ixgbe_mac_X550EM_x:
4305 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0);
4306 #ifdef CONFIG_IXGBE_VXLAN
4307 adapter->vxlan_port = 0;
4308 #endif
4309 break;
4310 default:
4311 break;
4312 }
4313 }
4314
4315 #ifdef CONFIG_IXGBE_DCB
4316 /**
4317 * ixgbe_configure_dcb - Configure DCB hardware
4318 * @adapter: ixgbe adapter struct
4319 *
4320 * This is called by the driver on open to configure the DCB hardware.
4321 * This is also called by the gennetlink interface when reconfiguring
4322 * the DCB state.
4323 */
4324 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4325 {
4326 struct ixgbe_hw *hw = &adapter->hw;
4327 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4328
4329 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4330 if (hw->mac.type == ixgbe_mac_82598EB)
4331 netif_set_gso_max_size(adapter->netdev, 65536);
4332 return;
4333 }
4334
4335 if (hw->mac.type == ixgbe_mac_82598EB)
4336 netif_set_gso_max_size(adapter->netdev, 32768);
4337
4338 #ifdef IXGBE_FCOE
4339 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4340 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
4341 #endif
4342
4343 /* reconfigure the hardware */
4344 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
4345 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4346 DCB_TX_CONFIG);
4347 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4348 DCB_RX_CONFIG);
4349 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
4350 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4351 ixgbe_dcb_hw_ets(&adapter->hw,
4352 adapter->ixgbe_ieee_ets,
4353 max_frame);
4354 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4355 adapter->ixgbe_ieee_pfc->pfc_en,
4356 adapter->ixgbe_ieee_ets->prio_tc);
4357 }
4358
4359 /* Enable RSS Hash per TC */
4360 if (hw->mac.type != ixgbe_mac_82598EB) {
4361 u32 msb = 0;
4362 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
4363
4364 while (rss_i) {
4365 msb++;
4366 rss_i >>= 1;
4367 }
4368
4369 /* write msb to all 8 TCs in one write */
4370 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
4371 }
4372 }
4373 #endif
4374
4375 /* Additional bittime to account for IXGBE framing */
4376 #define IXGBE_ETH_FRAMING 20
4377
4378 /**
4379 * ixgbe_hpbthresh - calculate high water mark for flow control
4380 *
4381 * @adapter: board private structure to calculate for
4382 * @pb: packet buffer to calculate
4383 */
4384 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4385 {
4386 struct ixgbe_hw *hw = &adapter->hw;
4387 struct net_device *dev = adapter->netdev;
4388 int link, tc, kb, marker;
4389 u32 dv_id, rx_pba;
4390
4391 /* Calculate max LAN frame size */
4392 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4393
4394 #ifdef IXGBE_FCOE
4395 /* FCoE traffic class uses FCOE jumbo frames */
4396 if ((dev->features & NETIF_F_FCOE_MTU) &&
4397 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4398 (pb == ixgbe_fcoe_get_tc(adapter)))
4399 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4400 #endif
4401
4402 /* Calculate delay value for device */
4403 switch (hw->mac.type) {
4404 case ixgbe_mac_X540:
4405 case ixgbe_mac_X550:
4406 case ixgbe_mac_X550EM_x:
4407 dv_id = IXGBE_DV_X540(link, tc);
4408 break;
4409 default:
4410 dv_id = IXGBE_DV(link, tc);
4411 break;
4412 }
4413
4414 /* Loopback switch introduces additional latency */
4415 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4416 dv_id += IXGBE_B2BT(tc);
4417
4418 /* Delay value is calculated in bit times convert to KB */
4419 kb = IXGBE_BT2KB(dv_id);
4420 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4421
4422 marker = rx_pba - kb;
4423
4424 /* It is possible that the packet buffer is not large enough
4425 * to provide required headroom. In this case throw an error
4426 * to user and a do the best we can.
4427 */
4428 if (marker < 0) {
4429 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4430 "headroom to support flow control."
4431 "Decrease MTU or number of traffic classes\n", pb);
4432 marker = tc + 1;
4433 }
4434
4435 return marker;
4436 }
4437
4438 /**
4439 * ixgbe_lpbthresh - calculate low water mark for for flow control
4440 *
4441 * @adapter: board private structure to calculate for
4442 * @pb: packet buffer to calculate
4443 */
4444 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
4445 {
4446 struct ixgbe_hw *hw = &adapter->hw;
4447 struct net_device *dev = adapter->netdev;
4448 int tc;
4449 u32 dv_id;
4450
4451 /* Calculate max LAN frame size */
4452 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4453
4454 #ifdef IXGBE_FCOE
4455 /* FCoE traffic class uses FCOE jumbo frames */
4456 if ((dev->features & NETIF_F_FCOE_MTU) &&
4457 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4458 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4459 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4460 #endif
4461
4462 /* Calculate delay value for device */
4463 switch (hw->mac.type) {
4464 case ixgbe_mac_X540:
4465 case ixgbe_mac_X550:
4466 case ixgbe_mac_X550EM_x:
4467 dv_id = IXGBE_LOW_DV_X540(tc);
4468 break;
4469 default:
4470 dv_id = IXGBE_LOW_DV(tc);
4471 break;
4472 }
4473
4474 /* Delay value is calculated in bit times convert to KB */
4475 return IXGBE_BT2KB(dv_id);
4476 }
4477
4478 /*
4479 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4480 */
4481 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4482 {
4483 struct ixgbe_hw *hw = &adapter->hw;
4484 int num_tc = netdev_get_num_tc(adapter->netdev);
4485 int i;
4486
4487 if (!num_tc)
4488 num_tc = 1;
4489
4490 for (i = 0; i < num_tc; i++) {
4491 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4492 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
4493
4494 /* Low water marks must not be larger than high water marks */
4495 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4496 hw->fc.low_water[i] = 0;
4497 }
4498
4499 for (; i < MAX_TRAFFIC_CLASS; i++)
4500 hw->fc.high_water[i] = 0;
4501 }
4502
4503 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4504 {
4505 struct ixgbe_hw *hw = &adapter->hw;
4506 int hdrm;
4507 u8 tc = netdev_get_num_tc(adapter->netdev);
4508
4509 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4510 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4511 hdrm = 32 << adapter->fdir_pballoc;
4512 else
4513 hdrm = 0;
4514
4515 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
4516 ixgbe_pbthresh_setup(adapter);
4517 }
4518
4519 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4520 {
4521 struct ixgbe_hw *hw = &adapter->hw;
4522 struct hlist_node *node2;
4523 struct ixgbe_fdir_filter *filter;
4524
4525 spin_lock(&adapter->fdir_perfect_lock);
4526
4527 if (!hlist_empty(&adapter->fdir_filter_list))
4528 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4529
4530 hlist_for_each_entry_safe(filter, node2,
4531 &adapter->fdir_filter_list, fdir_node) {
4532 ixgbe_fdir_write_perfect_filter_82599(hw,
4533 &filter->filter,
4534 filter->sw_idx,
4535 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4536 IXGBE_FDIR_DROP_QUEUE :
4537 adapter->rx_ring[filter->action]->reg_idx);
4538 }
4539
4540 spin_unlock(&adapter->fdir_perfect_lock);
4541 }
4542
4543 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4544 struct ixgbe_adapter *adapter)
4545 {
4546 struct ixgbe_hw *hw = &adapter->hw;
4547 u32 vmolr;
4548
4549 /* No unicast promiscuous support for VMDQ devices. */
4550 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4551 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4552
4553 /* clear the affected bit */
4554 vmolr &= ~IXGBE_VMOLR_MPE;
4555
4556 if (dev->flags & IFF_ALLMULTI) {
4557 vmolr |= IXGBE_VMOLR_MPE;
4558 } else {
4559 vmolr |= IXGBE_VMOLR_ROMPE;
4560 hw->mac.ops.update_mc_addr_list(hw, dev);
4561 }
4562 ixgbe_write_uc_addr_list(adapter->netdev, pool);
4563 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4564 }
4565
4566 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4567 {
4568 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4569 int rss_i = adapter->num_rx_queues_per_pool;
4570 struct ixgbe_hw *hw = &adapter->hw;
4571 u16 pool = vadapter->pool;
4572 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4573 IXGBE_PSRTYPE_UDPHDR |
4574 IXGBE_PSRTYPE_IPV4HDR |
4575 IXGBE_PSRTYPE_L2HDR |
4576 IXGBE_PSRTYPE_IPV6HDR;
4577
4578 if (hw->mac.type == ixgbe_mac_82598EB)
4579 return;
4580
4581 if (rss_i > 3)
4582 psrtype |= 2 << 29;
4583 else if (rss_i > 1)
4584 psrtype |= 1 << 29;
4585
4586 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4587 }
4588
4589 /**
4590 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4591 * @rx_ring: ring to free buffers from
4592 **/
4593 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4594 {
4595 struct device *dev = rx_ring->dev;
4596 unsigned long size;
4597 u16 i;
4598
4599 /* ring already cleared, nothing to do */
4600 if (!rx_ring->rx_buffer_info)
4601 return;
4602
4603 /* Free all the Rx ring sk_buffs */
4604 for (i = 0; i < rx_ring->count; i++) {
4605 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
4606
4607 if (rx_buffer->skb) {
4608 struct sk_buff *skb = rx_buffer->skb;
4609 if (IXGBE_CB(skb)->page_released)
4610 dma_unmap_page(dev,
4611 IXGBE_CB(skb)->dma,
4612 ixgbe_rx_bufsz(rx_ring),
4613 DMA_FROM_DEVICE);
4614 dev_kfree_skb(skb);
4615 rx_buffer->skb = NULL;
4616 }
4617
4618 if (!rx_buffer->page)
4619 continue;
4620
4621 dma_unmap_page(dev, rx_buffer->dma,
4622 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4623 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4624
4625 rx_buffer->page = NULL;
4626 }
4627
4628 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4629 memset(rx_ring->rx_buffer_info, 0, size);
4630
4631 /* Zero out the descriptor ring */
4632 memset(rx_ring->desc, 0, rx_ring->size);
4633
4634 rx_ring->next_to_alloc = 0;
4635 rx_ring->next_to_clean = 0;
4636 rx_ring->next_to_use = 0;
4637 }
4638
4639 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4640 struct ixgbe_ring *rx_ring)
4641 {
4642 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4643 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4644
4645 /* shutdown specific queue receive and wait for dma to settle */
4646 ixgbe_disable_rx_queue(adapter, rx_ring);
4647 usleep_range(10000, 20000);
4648 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4649 ixgbe_clean_rx_ring(rx_ring);
4650 rx_ring->l2_accel_priv = NULL;
4651 }
4652
4653 static int ixgbe_fwd_ring_down(struct net_device *vdev,
4654 struct ixgbe_fwd_adapter *accel)
4655 {
4656 struct ixgbe_adapter *adapter = accel->real_adapter;
4657 unsigned int rxbase = accel->rx_base_queue;
4658 unsigned int txbase = accel->tx_base_queue;
4659 int i;
4660
4661 netif_tx_stop_all_queues(vdev);
4662
4663 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4664 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4665 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4666 }
4667
4668 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4669 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4670 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4671 }
4672
4673
4674 return 0;
4675 }
4676
4677 static int ixgbe_fwd_ring_up(struct net_device *vdev,
4678 struct ixgbe_fwd_adapter *accel)
4679 {
4680 struct ixgbe_adapter *adapter = accel->real_adapter;
4681 unsigned int rxbase, txbase, queues;
4682 int i, baseq, err = 0;
4683
4684 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4685 return 0;
4686
4687 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4688 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4689 accel->pool, adapter->num_rx_pools,
4690 baseq, baseq + adapter->num_rx_queues_per_pool,
4691 adapter->fwd_bitmask);
4692
4693 accel->netdev = vdev;
4694 accel->rx_base_queue = rxbase = baseq;
4695 accel->tx_base_queue = txbase = baseq;
4696
4697 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4698 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4699
4700 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4701 adapter->rx_ring[rxbase + i]->netdev = vdev;
4702 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4703 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4704 }
4705
4706 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4707 adapter->tx_ring[txbase + i]->netdev = vdev;
4708 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4709 }
4710
4711 queues = min_t(unsigned int,
4712 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4713 err = netif_set_real_num_tx_queues(vdev, queues);
4714 if (err)
4715 goto fwd_queue_err;
4716
4717 err = netif_set_real_num_rx_queues(vdev, queues);
4718 if (err)
4719 goto fwd_queue_err;
4720
4721 if (is_valid_ether_addr(vdev->dev_addr))
4722 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4723
4724 ixgbe_fwd_psrtype(accel);
4725 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4726 return err;
4727 fwd_queue_err:
4728 ixgbe_fwd_ring_down(vdev, accel);
4729 return err;
4730 }
4731
4732 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4733 {
4734 struct net_device *upper;
4735 struct list_head *iter;
4736 int err;
4737
4738 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4739 if (netif_is_macvlan(upper)) {
4740 struct macvlan_dev *dfwd = netdev_priv(upper);
4741 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4742
4743 if (dfwd->fwd_priv) {
4744 err = ixgbe_fwd_ring_up(upper, vadapter);
4745 if (err)
4746 continue;
4747 }
4748 }
4749 }
4750 }
4751
4752 static void ixgbe_configure(struct ixgbe_adapter *adapter)
4753 {
4754 struct ixgbe_hw *hw = &adapter->hw;
4755
4756 ixgbe_configure_pb(adapter);
4757 #ifdef CONFIG_IXGBE_DCB
4758 ixgbe_configure_dcb(adapter);
4759 #endif
4760 /*
4761 * We must restore virtualization before VLANs or else
4762 * the VLVF registers will not be populated
4763 */
4764 ixgbe_configure_virtualization(adapter);
4765
4766 ixgbe_set_rx_mode(adapter->netdev);
4767 ixgbe_restore_vlan(adapter);
4768
4769 switch (hw->mac.type) {
4770 case ixgbe_mac_82599EB:
4771 case ixgbe_mac_X540:
4772 hw->mac.ops.disable_rx_buff(hw);
4773 break;
4774 default:
4775 break;
4776 }
4777
4778 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4779 ixgbe_init_fdir_signature_82599(&adapter->hw,
4780 adapter->fdir_pballoc);
4781 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4782 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4783 adapter->fdir_pballoc);
4784 ixgbe_fdir_filter_restore(adapter);
4785 }
4786
4787 switch (hw->mac.type) {
4788 case ixgbe_mac_82599EB:
4789 case ixgbe_mac_X540:
4790 hw->mac.ops.enable_rx_buff(hw);
4791 break;
4792 default:
4793 break;
4794 }
4795
4796 #ifdef CONFIG_IXGBE_DCA
4797 /* configure DCA */
4798 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
4799 ixgbe_setup_dca(adapter);
4800 #endif /* CONFIG_IXGBE_DCA */
4801
4802 #ifdef IXGBE_FCOE
4803 /* configure FCoE L2 filters, redirection table, and Rx control */
4804 ixgbe_configure_fcoe(adapter);
4805
4806 #endif /* IXGBE_FCOE */
4807 ixgbe_configure_tx(adapter);
4808 ixgbe_configure_rx(adapter);
4809 ixgbe_configure_dfwd(adapter);
4810 }
4811
4812 /**
4813 * ixgbe_sfp_link_config - set up SFP+ link
4814 * @adapter: pointer to private adapter struct
4815 **/
4816 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4817 {
4818 /*
4819 * We are assuming the worst case scenario here, and that
4820 * is that an SFP was inserted/removed after the reset
4821 * but before SFP detection was enabled. As such the best
4822 * solution is to just start searching as soon as we start
4823 */
4824 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4825 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4826
4827 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4828 adapter->sfp_poll_time = 0;
4829 }
4830
4831 /**
4832 * ixgbe_non_sfp_link_config - set up non-SFP+ link
4833 * @hw: pointer to private hardware struct
4834 *
4835 * Returns 0 on success, negative on failure
4836 **/
4837 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4838 {
4839 u32 speed;
4840 bool autoneg, link_up = false;
4841 int ret = IXGBE_ERR_LINK_SETUP;
4842
4843 if (hw->mac.ops.check_link)
4844 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
4845
4846 if (ret)
4847 return ret;
4848
4849 speed = hw->phy.autoneg_advertised;
4850 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4851 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4852 &autoneg);
4853 if (ret)
4854 return ret;
4855
4856 if (hw->mac.ops.setup_link)
4857 ret = hw->mac.ops.setup_link(hw, speed, link_up);
4858
4859 return ret;
4860 }
4861
4862 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4863 {
4864 struct ixgbe_hw *hw = &adapter->hw;
4865 u32 gpie = 0;
4866
4867 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4868 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4869 IXGBE_GPIE_OCD;
4870 gpie |= IXGBE_GPIE_EIAME;
4871 /*
4872 * use EIAM to auto-mask when MSI-X interrupt is asserted
4873 * this saves a register write for every interrupt
4874 */
4875 switch (hw->mac.type) {
4876 case ixgbe_mac_82598EB:
4877 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4878 break;
4879 case ixgbe_mac_82599EB:
4880 case ixgbe_mac_X540:
4881 case ixgbe_mac_X550:
4882 case ixgbe_mac_X550EM_x:
4883 default:
4884 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4885 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4886 break;
4887 }
4888 } else {
4889 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4890 * specifically only auto mask tx and rx interrupts */
4891 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4892 }
4893
4894 /* XXX: to interrupt immediately for EICS writes, enable this */
4895 /* gpie |= IXGBE_GPIE_EIMEN; */
4896
4897 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4898 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4899
4900 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4901 case IXGBE_82599_VMDQ_8Q_MASK:
4902 gpie |= IXGBE_GPIE_VTMODE_16;
4903 break;
4904 case IXGBE_82599_VMDQ_4Q_MASK:
4905 gpie |= IXGBE_GPIE_VTMODE_32;
4906 break;
4907 default:
4908 gpie |= IXGBE_GPIE_VTMODE_64;
4909 break;
4910 }
4911 }
4912
4913 /* Enable Thermal over heat sensor interrupt */
4914 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4915 switch (adapter->hw.mac.type) {
4916 case ixgbe_mac_82599EB:
4917 gpie |= IXGBE_SDP0_GPIEN_8259X;
4918 break;
4919 case ixgbe_mac_X540:
4920 gpie |= IXGBE_EIMS_TS;
4921 break;
4922 default:
4923 break;
4924 }
4925 }
4926
4927 /* Enable fan failure interrupt */
4928 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4929 gpie |= IXGBE_SDP1_GPIEN(hw);
4930
4931 switch (hw->mac.type) {
4932 case ixgbe_mac_82599EB:
4933 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
4934 break;
4935 case ixgbe_mac_X550EM_x:
4936 gpie |= IXGBE_SDP0_GPIEN_X540;
4937 break;
4938 default:
4939 break;
4940 }
4941
4942 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4943 }
4944
4945 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4946 {
4947 struct ixgbe_hw *hw = &adapter->hw;
4948 int err;
4949 u32 ctrl_ext;
4950
4951 ixgbe_get_hw_control(adapter);
4952 ixgbe_setup_gpie(adapter);
4953
4954 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4955 ixgbe_configure_msix(adapter);
4956 else
4957 ixgbe_configure_msi_and_legacy(adapter);
4958
4959 /* enable the optics for 82599 SFP+ fiber */
4960 if (hw->mac.ops.enable_tx_laser)
4961 hw->mac.ops.enable_tx_laser(hw);
4962
4963 if (hw->phy.ops.set_phy_power)
4964 hw->phy.ops.set_phy_power(hw, true);
4965
4966 smp_mb__before_atomic();
4967 clear_bit(__IXGBE_DOWN, &adapter->state);
4968 ixgbe_napi_enable_all(adapter);
4969
4970 if (ixgbe_is_sfp(hw)) {
4971 ixgbe_sfp_link_config(adapter);
4972 } else {
4973 err = ixgbe_non_sfp_link_config(hw);
4974 if (err)
4975 e_err(probe, "link_config FAILED %d\n", err);
4976 }
4977
4978 /* clear any pending interrupts, may auto mask */
4979 IXGBE_READ_REG(hw, IXGBE_EICR);
4980 ixgbe_irq_enable(adapter, true, true);
4981
4982 /*
4983 * If this adapter has a fan, check to see if we had a failure
4984 * before we enabled the interrupt.
4985 */
4986 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4987 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4988 if (esdp & IXGBE_ESDP_SDP1)
4989 e_crit(drv, "Fan has stopped, replace the adapter\n");
4990 }
4991
4992 /* bring the link up in the watchdog, this could race with our first
4993 * link up interrupt but shouldn't be a problem */
4994 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4995 adapter->link_check_timeout = jiffies;
4996 mod_timer(&adapter->service_timer, jiffies);
4997
4998 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4999 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5000 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5001 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
5002 }
5003
5004 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5005 {
5006 WARN_ON(in_interrupt());
5007 /* put off any impending NetWatchDogTimeout */
5008 adapter->netdev->trans_start = jiffies;
5009
5010 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
5011 usleep_range(1000, 2000);
5012 ixgbe_down(adapter);
5013 /*
5014 * If SR-IOV enabled then wait a bit before bringing the adapter
5015 * back up to give the VFs time to respond to the reset. The
5016 * two second wait is based upon the watchdog timer cycle in
5017 * the VF driver.
5018 */
5019 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5020 msleep(2000);
5021 ixgbe_up(adapter);
5022 clear_bit(__IXGBE_RESETTING, &adapter->state);
5023 }
5024
5025 void ixgbe_up(struct ixgbe_adapter *adapter)
5026 {
5027 /* hardware has been reset, we need to reload some things */
5028 ixgbe_configure(adapter);
5029
5030 ixgbe_up_complete(adapter);
5031 }
5032
5033 void ixgbe_reset(struct ixgbe_adapter *adapter)
5034 {
5035 struct ixgbe_hw *hw = &adapter->hw;
5036 struct net_device *netdev = adapter->netdev;
5037 int err;
5038 u8 old_addr[ETH_ALEN];
5039
5040 if (ixgbe_removed(hw->hw_addr))
5041 return;
5042 /* lock SFP init bit to prevent race conditions with the watchdog */
5043 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5044 usleep_range(1000, 2000);
5045
5046 /* clear all SFP and link config related flags while holding SFP_INIT */
5047 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5048 IXGBE_FLAG2_SFP_NEEDS_RESET);
5049 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5050
5051 err = hw->mac.ops.init_hw(hw);
5052 switch (err) {
5053 case 0:
5054 case IXGBE_ERR_SFP_NOT_PRESENT:
5055 case IXGBE_ERR_SFP_NOT_SUPPORTED:
5056 break;
5057 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
5058 e_dev_err("master disable timed out\n");
5059 break;
5060 case IXGBE_ERR_EEPROM_VERSION:
5061 /* We are running on a pre-production device, log a warning */
5062 e_dev_warn("This device is a pre-production adapter/LOM. "
5063 "Please be aware there may be issues associated with "
5064 "your hardware. If you are experiencing problems "
5065 "please contact your Intel or hardware "
5066 "representative who provided you with this "
5067 "hardware.\n");
5068 break;
5069 default:
5070 e_dev_err("Hardware Error: %d\n", err);
5071 }
5072
5073 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5074 /* do not flush user set addresses */
5075 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len);
5076 ixgbe_flush_sw_mac_table(adapter);
5077 ixgbe_mac_set_default_filter(adapter, old_addr);
5078
5079 /* update SAN MAC vmdq pool selection */
5080 if (hw->mac.san_mac_rar_index)
5081 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
5082
5083 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
5084 ixgbe_ptp_reset(adapter);
5085
5086 if (hw->phy.ops.set_phy_power) {
5087 if (!netif_running(adapter->netdev) && !adapter->wol)
5088 hw->phy.ops.set_phy_power(hw, false);
5089 else
5090 hw->phy.ops.set_phy_power(hw, true);
5091 }
5092 }
5093
5094 /**
5095 * ixgbe_clean_tx_ring - Free Tx Buffers
5096 * @tx_ring: ring to be cleaned
5097 **/
5098 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
5099 {
5100 struct ixgbe_tx_buffer *tx_buffer_info;
5101 unsigned long size;
5102 u16 i;
5103
5104 /* ring already cleared, nothing to do */
5105 if (!tx_ring->tx_buffer_info)
5106 return;
5107
5108 /* Free all the Tx ring sk_buffs */
5109 for (i = 0; i < tx_ring->count; i++) {
5110 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5111 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
5112 }
5113
5114 netdev_tx_reset_queue(txring_txq(tx_ring));
5115
5116 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5117 memset(tx_ring->tx_buffer_info, 0, size);
5118
5119 /* Zero out the descriptor ring */
5120 memset(tx_ring->desc, 0, tx_ring->size);
5121
5122 tx_ring->next_to_use = 0;
5123 tx_ring->next_to_clean = 0;
5124 }
5125
5126 /**
5127 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
5128 * @adapter: board private structure
5129 **/
5130 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
5131 {
5132 int i;
5133
5134 for (i = 0; i < adapter->num_rx_queues; i++)
5135 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
5136 }
5137
5138 /**
5139 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
5140 * @adapter: board private structure
5141 **/
5142 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
5143 {
5144 int i;
5145
5146 for (i = 0; i < adapter->num_tx_queues; i++)
5147 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
5148 }
5149
5150 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5151 {
5152 struct hlist_node *node2;
5153 struct ixgbe_fdir_filter *filter;
5154
5155 spin_lock(&adapter->fdir_perfect_lock);
5156
5157 hlist_for_each_entry_safe(filter, node2,
5158 &adapter->fdir_filter_list, fdir_node) {
5159 hlist_del(&filter->fdir_node);
5160 kfree(filter);
5161 }
5162 adapter->fdir_filter_count = 0;
5163
5164 spin_unlock(&adapter->fdir_perfect_lock);
5165 }
5166
5167 void ixgbe_down(struct ixgbe_adapter *adapter)
5168 {
5169 struct net_device *netdev = adapter->netdev;
5170 struct ixgbe_hw *hw = &adapter->hw;
5171 struct net_device *upper;
5172 struct list_head *iter;
5173 int i;
5174
5175 /* signal that we are down to the interrupt handler */
5176 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5177 return; /* do nothing if already down */
5178
5179 /* disable receives */
5180 hw->mac.ops.disable_rx(hw);
5181
5182 /* disable all enabled rx queues */
5183 for (i = 0; i < adapter->num_rx_queues; i++)
5184 /* this call also flushes the previous write */
5185 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5186
5187 usleep_range(10000, 20000);
5188
5189 netif_tx_stop_all_queues(netdev);
5190
5191 /* call carrier off first to avoid false dev_watchdog timeouts */
5192 netif_carrier_off(netdev);
5193 netif_tx_disable(netdev);
5194
5195 /* disable any upper devices */
5196 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5197 if (netif_is_macvlan(upper)) {
5198 struct macvlan_dev *vlan = netdev_priv(upper);
5199
5200 if (vlan->fwd_priv) {
5201 netif_tx_stop_all_queues(upper);
5202 netif_carrier_off(upper);
5203 netif_tx_disable(upper);
5204 }
5205 }
5206 }
5207
5208 ixgbe_irq_disable(adapter);
5209
5210 ixgbe_napi_disable_all(adapter);
5211
5212 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5213 IXGBE_FLAG2_RESET_REQUESTED);
5214 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5215
5216 del_timer_sync(&adapter->service_timer);
5217
5218 if (adapter->num_vfs) {
5219 /* Clear EITR Select mapping */
5220 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
5221
5222 /* Mark all the VFs as inactive */
5223 for (i = 0 ; i < adapter->num_vfs; i++)
5224 adapter->vfinfo[i].clear_to_send = false;
5225
5226 /* ping all the active vfs to let them know we are going down */
5227 ixgbe_ping_all_vfs(adapter);
5228
5229 /* Disable all VFTE/VFRE TX/RX */
5230 ixgbe_disable_tx_rx(adapter);
5231 }
5232
5233 /* disable transmits in the hardware now that interrupts are off */
5234 for (i = 0; i < adapter->num_tx_queues; i++) {
5235 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
5236 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5237 }
5238
5239 /* Disable the Tx DMA engine on 82599 and later MAC */
5240 switch (hw->mac.type) {
5241 case ixgbe_mac_82599EB:
5242 case ixgbe_mac_X540:
5243 case ixgbe_mac_X550:
5244 case ixgbe_mac_X550EM_x:
5245 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
5246 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5247 ~IXGBE_DMATXCTL_TE));
5248 break;
5249 default:
5250 break;
5251 }
5252
5253 if (!pci_channel_offline(adapter->pdev))
5254 ixgbe_reset(adapter);
5255
5256 /* power down the optics for 82599 SFP+ fiber */
5257 if (hw->mac.ops.disable_tx_laser)
5258 hw->mac.ops.disable_tx_laser(hw);
5259
5260 ixgbe_clean_all_tx_rings(adapter);
5261 ixgbe_clean_all_rx_rings(adapter);
5262 }
5263
5264 /**
5265 * ixgbe_tx_timeout - Respond to a Tx Hang
5266 * @netdev: network interface device structure
5267 **/
5268 static void ixgbe_tx_timeout(struct net_device *netdev)
5269 {
5270 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5271
5272 /* Do the reset outside of interrupt context */
5273 ixgbe_tx_timeout_reset(adapter);
5274 }
5275
5276 /**
5277 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5278 * @adapter: board private structure to initialize
5279 *
5280 * ixgbe_sw_init initializes the Adapter private data structure.
5281 * Fields are initialized based on PCI device information and
5282 * OS network device settings (MTU size).
5283 **/
5284 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
5285 {
5286 struct ixgbe_hw *hw = &adapter->hw;
5287 struct pci_dev *pdev = adapter->pdev;
5288 unsigned int rss, fdir;
5289 u32 fwsm;
5290 #ifdef CONFIG_IXGBE_DCB
5291 int j;
5292 struct tc_configuration *tc;
5293 #endif
5294
5295 /* PCI config space info */
5296
5297 hw->vendor_id = pdev->vendor;
5298 hw->device_id = pdev->device;
5299 hw->revision_id = pdev->revision;
5300 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5301 hw->subsystem_device_id = pdev->subsystem_device;
5302
5303 /* Set common capability flags and settings */
5304 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
5305 adapter->ring_feature[RING_F_RSS].limit = rss;
5306 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5307 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5308 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5309 adapter->atr_sample_rate = 20;
5310 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5311 adapter->ring_feature[RING_F_FDIR].limit = fdir;
5312 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5313 #ifdef CONFIG_IXGBE_DCA
5314 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5315 #endif
5316 #ifdef IXGBE_FCOE
5317 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5318 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5319 #ifdef CONFIG_IXGBE_DCB
5320 /* Default traffic class to use for FCoE */
5321 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5322 #endif /* CONFIG_IXGBE_DCB */
5323 #endif /* IXGBE_FCOE */
5324
5325 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5326 hw->mac.num_rar_entries,
5327 GFP_ATOMIC);
5328
5329 /* Set MAC specific capability flags and exceptions */
5330 switch (hw->mac.type) {
5331 case ixgbe_mac_82598EB:
5332 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5333 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5334
5335 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5336 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5337
5338 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
5339 adapter->ring_feature[RING_F_FDIR].limit = 0;
5340 adapter->atr_sample_rate = 0;
5341 adapter->fdir_pballoc = 0;
5342 #ifdef IXGBE_FCOE
5343 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5344 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5345 #ifdef CONFIG_IXGBE_DCB
5346 adapter->fcoe.up = 0;
5347 #endif /* IXGBE_DCB */
5348 #endif /* IXGBE_FCOE */
5349 break;
5350 case ixgbe_mac_82599EB:
5351 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5352 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5353 break;
5354 case ixgbe_mac_X540:
5355 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
5356 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5357 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5358 break;
5359 case ixgbe_mac_X550EM_x:
5360 case ixgbe_mac_X550:
5361 #ifdef CONFIG_IXGBE_DCA
5362 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
5363 #endif
5364 #ifdef CONFIG_IXGBE_VXLAN
5365 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
5366 #endif
5367 break;
5368 default:
5369 break;
5370 }
5371
5372 #ifdef IXGBE_FCOE
5373 /* FCoE support exists, always init the FCoE lock */
5374 spin_lock_init(&adapter->fcoe.lock);
5375
5376 #endif
5377 /* n-tuple support exists, always init our spinlock */
5378 spin_lock_init(&adapter->fdir_perfect_lock);
5379
5380 #ifdef CONFIG_IXGBE_DCB
5381 switch (hw->mac.type) {
5382 case ixgbe_mac_X540:
5383 case ixgbe_mac_X550:
5384 case ixgbe_mac_X550EM_x:
5385 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5386 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5387 break;
5388 default:
5389 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5390 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5391 break;
5392 }
5393
5394 /* Configure DCB traffic classes */
5395 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5396 tc = &adapter->dcb_cfg.tc_config[j];
5397 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5398 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5399 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5400 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5401 tc->dcb_pfc = pfc_disabled;
5402 }
5403
5404 /* Initialize default user to priority mapping, UPx->TC0 */
5405 tc = &adapter->dcb_cfg.tc_config[0];
5406 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5407 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5408
5409 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5410 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5411 adapter->dcb_cfg.pfc_mode_enable = false;
5412 adapter->dcb_set_bitmap = 0x00;
5413 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5414 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5415 sizeof(adapter->temp_dcb_cfg));
5416
5417 #endif
5418
5419 /* default flow control settings */
5420 hw->fc.requested_mode = ixgbe_fc_full;
5421 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5422 ixgbe_pbthresh_setup(adapter);
5423 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5424 hw->fc.send_xon = true;
5425 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
5426
5427 #ifdef CONFIG_PCI_IOV
5428 if (max_vfs > 0)
5429 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5430
5431 /* assign number of SR-IOV VFs */
5432 if (hw->mac.type != ixgbe_mac_82598EB) {
5433 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
5434 adapter->num_vfs = 0;
5435 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5436 } else {
5437 adapter->num_vfs = max_vfs;
5438 }
5439 }
5440 #endif /* CONFIG_PCI_IOV */
5441
5442 /* enable itr by default in dynamic mode */
5443 adapter->rx_itr_setting = 1;
5444 adapter->tx_itr_setting = 1;
5445
5446 /* set default ring sizes */
5447 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5448 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5449
5450 /* set default work limits */
5451 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5452
5453 /* initialize eeprom parameters */
5454 if (ixgbe_init_eeprom_params_generic(hw)) {
5455 e_dev_err("EEPROM initialization failed\n");
5456 return -EIO;
5457 }
5458
5459 /* PF holds first pool slot */
5460 set_bit(0, &adapter->fwd_bitmask);
5461 set_bit(__IXGBE_DOWN, &adapter->state);
5462
5463 return 0;
5464 }
5465
5466 /**
5467 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5468 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5469 *
5470 * Return 0 on success, negative on failure
5471 **/
5472 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5473 {
5474 struct device *dev = tx_ring->dev;
5475 int orig_node = dev_to_node(dev);
5476 int ring_node = -1;
5477 int size;
5478
5479 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5480
5481 if (tx_ring->q_vector)
5482 ring_node = tx_ring->q_vector->numa_node;
5483
5484 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
5485 if (!tx_ring->tx_buffer_info)
5486 tx_ring->tx_buffer_info = vzalloc(size);
5487 if (!tx_ring->tx_buffer_info)
5488 goto err;
5489
5490 u64_stats_init(&tx_ring->syncp);
5491
5492 /* round up to nearest 4K */
5493 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5494 tx_ring->size = ALIGN(tx_ring->size, 4096);
5495
5496 set_dev_node(dev, ring_node);
5497 tx_ring->desc = dma_alloc_coherent(dev,
5498 tx_ring->size,
5499 &tx_ring->dma,
5500 GFP_KERNEL);
5501 set_dev_node(dev, orig_node);
5502 if (!tx_ring->desc)
5503 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5504 &tx_ring->dma, GFP_KERNEL);
5505 if (!tx_ring->desc)
5506 goto err;
5507
5508 tx_ring->next_to_use = 0;
5509 tx_ring->next_to_clean = 0;
5510 return 0;
5511
5512 err:
5513 vfree(tx_ring->tx_buffer_info);
5514 tx_ring->tx_buffer_info = NULL;
5515 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5516 return -ENOMEM;
5517 }
5518
5519 /**
5520 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5521 * @adapter: board private structure
5522 *
5523 * If this function returns with an error, then it's possible one or
5524 * more of the rings is populated (while the rest are not). It is the
5525 * callers duty to clean those orphaned rings.
5526 *
5527 * Return 0 on success, negative on failure
5528 **/
5529 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5530 {
5531 int i, err = 0;
5532
5533 for (i = 0; i < adapter->num_tx_queues; i++) {
5534 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5535 if (!err)
5536 continue;
5537
5538 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5539 goto err_setup_tx;
5540 }
5541
5542 return 0;
5543 err_setup_tx:
5544 /* rewind the index freeing the rings as we go */
5545 while (i--)
5546 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5547 return err;
5548 }
5549
5550 /**
5551 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5552 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5553 *
5554 * Returns 0 on success, negative on failure
5555 **/
5556 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5557 {
5558 struct device *dev = rx_ring->dev;
5559 int orig_node = dev_to_node(dev);
5560 int ring_node = -1;
5561 int size;
5562
5563 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5564
5565 if (rx_ring->q_vector)
5566 ring_node = rx_ring->q_vector->numa_node;
5567
5568 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
5569 if (!rx_ring->rx_buffer_info)
5570 rx_ring->rx_buffer_info = vzalloc(size);
5571 if (!rx_ring->rx_buffer_info)
5572 goto err;
5573
5574 u64_stats_init(&rx_ring->syncp);
5575
5576 /* Round up to nearest 4K */
5577 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5578 rx_ring->size = ALIGN(rx_ring->size, 4096);
5579
5580 set_dev_node(dev, ring_node);
5581 rx_ring->desc = dma_alloc_coherent(dev,
5582 rx_ring->size,
5583 &rx_ring->dma,
5584 GFP_KERNEL);
5585 set_dev_node(dev, orig_node);
5586 if (!rx_ring->desc)
5587 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5588 &rx_ring->dma, GFP_KERNEL);
5589 if (!rx_ring->desc)
5590 goto err;
5591
5592 rx_ring->next_to_clean = 0;
5593 rx_ring->next_to_use = 0;
5594
5595 return 0;
5596 err:
5597 vfree(rx_ring->rx_buffer_info);
5598 rx_ring->rx_buffer_info = NULL;
5599 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5600 return -ENOMEM;
5601 }
5602
5603 /**
5604 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5605 * @adapter: board private structure
5606 *
5607 * If this function returns with an error, then it's possible one or
5608 * more of the rings is populated (while the rest are not). It is the
5609 * callers duty to clean those orphaned rings.
5610 *
5611 * Return 0 on success, negative on failure
5612 **/
5613 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5614 {
5615 int i, err = 0;
5616
5617 for (i = 0; i < adapter->num_rx_queues; i++) {
5618 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5619 if (!err)
5620 continue;
5621
5622 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5623 goto err_setup_rx;
5624 }
5625
5626 #ifdef IXGBE_FCOE
5627 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5628 if (!err)
5629 #endif
5630 return 0;
5631 err_setup_rx:
5632 /* rewind the index freeing the rings as we go */
5633 while (i--)
5634 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5635 return err;
5636 }
5637
5638 /**
5639 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5640 * @tx_ring: Tx descriptor ring for a specific queue
5641 *
5642 * Free all transmit software resources
5643 **/
5644 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5645 {
5646 ixgbe_clean_tx_ring(tx_ring);
5647
5648 vfree(tx_ring->tx_buffer_info);
5649 tx_ring->tx_buffer_info = NULL;
5650
5651 /* if not set, then don't free */
5652 if (!tx_ring->desc)
5653 return;
5654
5655 dma_free_coherent(tx_ring->dev, tx_ring->size,
5656 tx_ring->desc, tx_ring->dma);
5657
5658 tx_ring->desc = NULL;
5659 }
5660
5661 /**
5662 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5663 * @adapter: board private structure
5664 *
5665 * Free all transmit software resources
5666 **/
5667 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5668 {
5669 int i;
5670
5671 for (i = 0; i < adapter->num_tx_queues; i++)
5672 if (adapter->tx_ring[i]->desc)
5673 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5674 }
5675
5676 /**
5677 * ixgbe_free_rx_resources - Free Rx Resources
5678 * @rx_ring: ring to clean the resources from
5679 *
5680 * Free all receive software resources
5681 **/
5682 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5683 {
5684 ixgbe_clean_rx_ring(rx_ring);
5685
5686 vfree(rx_ring->rx_buffer_info);
5687 rx_ring->rx_buffer_info = NULL;
5688
5689 /* if not set, then don't free */
5690 if (!rx_ring->desc)
5691 return;
5692
5693 dma_free_coherent(rx_ring->dev, rx_ring->size,
5694 rx_ring->desc, rx_ring->dma);
5695
5696 rx_ring->desc = NULL;
5697 }
5698
5699 /**
5700 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5701 * @adapter: board private structure
5702 *
5703 * Free all receive software resources
5704 **/
5705 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5706 {
5707 int i;
5708
5709 #ifdef IXGBE_FCOE
5710 ixgbe_free_fcoe_ddp_resources(adapter);
5711
5712 #endif
5713 for (i = 0; i < adapter->num_rx_queues; i++)
5714 if (adapter->rx_ring[i]->desc)
5715 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5716 }
5717
5718 /**
5719 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5720 * @netdev: network interface device structure
5721 * @new_mtu: new value for maximum frame size
5722 *
5723 * Returns 0 on success, negative on failure
5724 **/
5725 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5726 {
5727 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5728 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5729
5730 /* MTU < 68 is an error and causes problems on some kernels */
5731 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5732 return -EINVAL;
5733
5734 /*
5735 * For 82599EB we cannot allow legacy VFs to enable their receive
5736 * paths when MTU greater than 1500 is configured. So display a
5737 * warning that legacy VFs will be disabled.
5738 */
5739 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5740 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
5741 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
5742 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
5743
5744 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5745
5746 /* must set new MTU before calling down or up */
5747 netdev->mtu = new_mtu;
5748
5749 if (netif_running(netdev))
5750 ixgbe_reinit_locked(adapter);
5751
5752 return 0;
5753 }
5754
5755 /**
5756 * ixgbe_open - Called when a network interface is made active
5757 * @netdev: network interface device structure
5758 *
5759 * Returns 0 on success, negative value on failure
5760 *
5761 * The open entry point is called when a network interface is made
5762 * active by the system (IFF_UP). At this point all resources needed
5763 * for transmit and receive operations are allocated, the interrupt
5764 * handler is registered with the OS, the watchdog timer is started,
5765 * and the stack is notified that the interface is ready.
5766 **/
5767 static int ixgbe_open(struct net_device *netdev)
5768 {
5769 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5770 struct ixgbe_hw *hw = &adapter->hw;
5771 int err, queues;
5772
5773 /* disallow open during test */
5774 if (test_bit(__IXGBE_TESTING, &adapter->state))
5775 return -EBUSY;
5776
5777 netif_carrier_off(netdev);
5778
5779 /* allocate transmit descriptors */
5780 err = ixgbe_setup_all_tx_resources(adapter);
5781 if (err)
5782 goto err_setup_tx;
5783
5784 /* allocate receive descriptors */
5785 err = ixgbe_setup_all_rx_resources(adapter);
5786 if (err)
5787 goto err_setup_rx;
5788
5789 ixgbe_configure(adapter);
5790
5791 err = ixgbe_request_irq(adapter);
5792 if (err)
5793 goto err_req_irq;
5794
5795 /* Notify the stack of the actual queue counts. */
5796 if (adapter->num_rx_pools > 1)
5797 queues = adapter->num_rx_queues_per_pool;
5798 else
5799 queues = adapter->num_tx_queues;
5800
5801 err = netif_set_real_num_tx_queues(netdev, queues);
5802 if (err)
5803 goto err_set_queues;
5804
5805 if (adapter->num_rx_pools > 1 &&
5806 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5807 queues = IXGBE_MAX_L2A_QUEUES;
5808 else
5809 queues = adapter->num_rx_queues;
5810 err = netif_set_real_num_rx_queues(netdev, queues);
5811 if (err)
5812 goto err_set_queues;
5813
5814 ixgbe_ptp_init(adapter);
5815
5816 ixgbe_up_complete(adapter);
5817
5818 ixgbe_clear_vxlan_port(adapter);
5819 #ifdef CONFIG_IXGBE_VXLAN
5820 vxlan_get_rx_port(netdev);
5821 #endif
5822
5823 return 0;
5824
5825 err_set_queues:
5826 ixgbe_free_irq(adapter);
5827 err_req_irq:
5828 ixgbe_free_all_rx_resources(adapter);
5829 if (hw->phy.ops.set_phy_power && !adapter->wol)
5830 hw->phy.ops.set_phy_power(&adapter->hw, false);
5831 err_setup_rx:
5832 ixgbe_free_all_tx_resources(adapter);
5833 err_setup_tx:
5834 ixgbe_reset(adapter);
5835
5836 return err;
5837 }
5838
5839 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5840 {
5841 ixgbe_ptp_suspend(adapter);
5842
5843 if (adapter->hw.phy.ops.enter_lplu) {
5844 adapter->hw.phy.reset_disable = true;
5845 ixgbe_down(adapter);
5846 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
5847 adapter->hw.phy.reset_disable = false;
5848 } else {
5849 ixgbe_down(adapter);
5850 }
5851
5852 ixgbe_free_irq(adapter);
5853
5854 ixgbe_free_all_tx_resources(adapter);
5855 ixgbe_free_all_rx_resources(adapter);
5856 }
5857
5858 /**
5859 * ixgbe_close - Disables a network interface
5860 * @netdev: network interface device structure
5861 *
5862 * Returns 0, this is not allowed to fail
5863 *
5864 * The close entry point is called when an interface is de-activated
5865 * by the OS. The hardware is still under the drivers control, but
5866 * needs to be disabled. A global MAC reset is issued to stop the
5867 * hardware, and all transmit and receive resources are freed.
5868 **/
5869 static int ixgbe_close(struct net_device *netdev)
5870 {
5871 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5872
5873 ixgbe_ptp_stop(adapter);
5874
5875 ixgbe_close_suspend(adapter);
5876
5877 ixgbe_fdir_filter_exit(adapter);
5878
5879 ixgbe_release_hw_control(adapter);
5880
5881 return 0;
5882 }
5883
5884 #ifdef CONFIG_PM
5885 static int ixgbe_resume(struct pci_dev *pdev)
5886 {
5887 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5888 struct net_device *netdev = adapter->netdev;
5889 u32 err;
5890
5891 adapter->hw.hw_addr = adapter->io_addr;
5892 pci_set_power_state(pdev, PCI_D0);
5893 pci_restore_state(pdev);
5894 /*
5895 * pci_restore_state clears dev->state_saved so call
5896 * pci_save_state to restore it.
5897 */
5898 pci_save_state(pdev);
5899
5900 err = pci_enable_device_mem(pdev);
5901 if (err) {
5902 e_dev_err("Cannot enable PCI device from suspend\n");
5903 return err;
5904 }
5905 smp_mb__before_atomic();
5906 clear_bit(__IXGBE_DISABLED, &adapter->state);
5907 pci_set_master(pdev);
5908
5909 pci_wake_from_d3(pdev, false);
5910
5911 ixgbe_reset(adapter);
5912
5913 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5914
5915 rtnl_lock();
5916 err = ixgbe_init_interrupt_scheme(adapter);
5917 if (!err && netif_running(netdev))
5918 err = ixgbe_open(netdev);
5919
5920 rtnl_unlock();
5921
5922 if (err)
5923 return err;
5924
5925 netif_device_attach(netdev);
5926
5927 return 0;
5928 }
5929 #endif /* CONFIG_PM */
5930
5931 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5932 {
5933 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5934 struct net_device *netdev = adapter->netdev;
5935 struct ixgbe_hw *hw = &adapter->hw;
5936 u32 ctrl, fctrl;
5937 u32 wufc = adapter->wol;
5938 #ifdef CONFIG_PM
5939 int retval = 0;
5940 #endif
5941
5942 netif_device_detach(netdev);
5943
5944 rtnl_lock();
5945 if (netif_running(netdev))
5946 ixgbe_close_suspend(adapter);
5947 rtnl_unlock();
5948
5949 ixgbe_clear_interrupt_scheme(adapter);
5950
5951 #ifdef CONFIG_PM
5952 retval = pci_save_state(pdev);
5953 if (retval)
5954 return retval;
5955
5956 #endif
5957 if (hw->mac.ops.stop_link_on_d3)
5958 hw->mac.ops.stop_link_on_d3(hw);
5959
5960 if (wufc) {
5961 ixgbe_set_rx_mode(netdev);
5962
5963 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5964 if (hw->mac.ops.enable_tx_laser)
5965 hw->mac.ops.enable_tx_laser(hw);
5966
5967 /* turn on all-multi mode if wake on multicast is enabled */
5968 if (wufc & IXGBE_WUFC_MC) {
5969 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5970 fctrl |= IXGBE_FCTRL_MPE;
5971 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5972 }
5973
5974 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5975 ctrl |= IXGBE_CTRL_GIO_DIS;
5976 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5977
5978 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5979 } else {
5980 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5981 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5982 }
5983
5984 switch (hw->mac.type) {
5985 case ixgbe_mac_82598EB:
5986 pci_wake_from_d3(pdev, false);
5987 break;
5988 case ixgbe_mac_82599EB:
5989 case ixgbe_mac_X540:
5990 case ixgbe_mac_X550:
5991 case ixgbe_mac_X550EM_x:
5992 pci_wake_from_d3(pdev, !!wufc);
5993 break;
5994 default:
5995 break;
5996 }
5997
5998 *enable_wake = !!wufc;
5999 if (hw->phy.ops.set_phy_power && !*enable_wake)
6000 hw->phy.ops.set_phy_power(hw, false);
6001
6002 ixgbe_release_hw_control(adapter);
6003
6004 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6005 pci_disable_device(pdev);
6006
6007 return 0;
6008 }
6009
6010 #ifdef CONFIG_PM
6011 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
6012 {
6013 int retval;
6014 bool wake;
6015
6016 retval = __ixgbe_shutdown(pdev, &wake);
6017 if (retval)
6018 return retval;
6019
6020 if (wake) {
6021 pci_prepare_to_sleep(pdev);
6022 } else {
6023 pci_wake_from_d3(pdev, false);
6024 pci_set_power_state(pdev, PCI_D3hot);
6025 }
6026
6027 return 0;
6028 }
6029 #endif /* CONFIG_PM */
6030
6031 static void ixgbe_shutdown(struct pci_dev *pdev)
6032 {
6033 bool wake;
6034
6035 __ixgbe_shutdown(pdev, &wake);
6036
6037 if (system_state == SYSTEM_POWER_OFF) {
6038 pci_wake_from_d3(pdev, wake);
6039 pci_set_power_state(pdev, PCI_D3hot);
6040 }
6041 }
6042
6043 /**
6044 * ixgbe_update_stats - Update the board statistics counters.
6045 * @adapter: board private structure
6046 **/
6047 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6048 {
6049 struct net_device *netdev = adapter->netdev;
6050 struct ixgbe_hw *hw = &adapter->hw;
6051 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6052 u64 total_mpc = 0;
6053 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
6054 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6055 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
6056 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
6057
6058 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6059 test_bit(__IXGBE_RESETTING, &adapter->state))
6060 return;
6061
6062 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
6063 u64 rsc_count = 0;
6064 u64 rsc_flush = 0;
6065 for (i = 0; i < adapter->num_rx_queues; i++) {
6066 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6067 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
6068 }
6069 adapter->rsc_total_count = rsc_count;
6070 adapter->rsc_total_flush = rsc_flush;
6071 }
6072
6073 for (i = 0; i < adapter->num_rx_queues; i++) {
6074 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6075 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6076 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6077 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
6078 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
6079 bytes += rx_ring->stats.bytes;
6080 packets += rx_ring->stats.packets;
6081 }
6082 adapter->non_eop_descs = non_eop_descs;
6083 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6084 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
6085 adapter->hw_csum_rx_error = hw_csum_rx_error;
6086 netdev->stats.rx_bytes = bytes;
6087 netdev->stats.rx_packets = packets;
6088
6089 bytes = 0;
6090 packets = 0;
6091 /* gather some stats to the adapter struct that are per queue */
6092 for (i = 0; i < adapter->num_tx_queues; i++) {
6093 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6094 restart_queue += tx_ring->tx_stats.restart_queue;
6095 tx_busy += tx_ring->tx_stats.tx_busy;
6096 bytes += tx_ring->stats.bytes;
6097 packets += tx_ring->stats.packets;
6098 }
6099 adapter->restart_queue = restart_queue;
6100 adapter->tx_busy = tx_busy;
6101 netdev->stats.tx_bytes = bytes;
6102 netdev->stats.tx_packets = packets;
6103
6104 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6105
6106 /* 8 register reads */
6107 for (i = 0; i < 8; i++) {
6108 /* for packet buffers not used, the register should read 0 */
6109 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6110 missed_rx += mpc;
6111 hwstats->mpc[i] += mpc;
6112 total_mpc += hwstats->mpc[i];
6113 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6114 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6115 switch (hw->mac.type) {
6116 case ixgbe_mac_82598EB:
6117 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6118 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6119 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
6120 hwstats->pxonrxc[i] +=
6121 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
6122 break;
6123 case ixgbe_mac_82599EB:
6124 case ixgbe_mac_X540:
6125 case ixgbe_mac_X550:
6126 case ixgbe_mac_X550EM_x:
6127 hwstats->pxonrxc[i] +=
6128 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
6129 break;
6130 default:
6131 break;
6132 }
6133 }
6134
6135 /*16 register reads */
6136 for (i = 0; i < 16; i++) {
6137 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6138 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6139 if ((hw->mac.type == ixgbe_mac_82599EB) ||
6140 (hw->mac.type == ixgbe_mac_X540) ||
6141 (hw->mac.type == ixgbe_mac_X550) ||
6142 (hw->mac.type == ixgbe_mac_X550EM_x)) {
6143 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6144 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6145 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6146 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6147 }
6148 }
6149
6150 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6151 /* work around hardware counting issue */
6152 hwstats->gprc -= missed_rx;
6153
6154 ixgbe_update_xoff_received(adapter);
6155
6156 /* 82598 hardware only has a 32 bit counter in the high register */
6157 switch (hw->mac.type) {
6158 case ixgbe_mac_82598EB:
6159 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
6160 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6161 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6162 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6163 break;
6164 case ixgbe_mac_X540:
6165 case ixgbe_mac_X550:
6166 case ixgbe_mac_X550EM_x:
6167 /* OS2BMC stats are X540 and later */
6168 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6169 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6170 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6171 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6172 case ixgbe_mac_82599EB:
6173 for (i = 0; i < 16; i++)
6174 adapter->hw_rx_no_dma_resources +=
6175 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
6176 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
6177 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
6178 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
6179 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
6180 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
6181 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
6182 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
6183 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6184 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6185 #ifdef IXGBE_FCOE
6186 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6187 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6188 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6189 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6190 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6191 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6192 /* Add up per cpu counters for total ddp aloc fail */
6193 if (adapter->fcoe.ddp_pool) {
6194 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6195 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6196 unsigned int cpu;
6197 u64 noddp = 0, noddp_ext_buff = 0;
6198 for_each_possible_cpu(cpu) {
6199 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6200 noddp += ddp_pool->noddp;
6201 noddp_ext_buff += ddp_pool->noddp_ext_buff;
6202 }
6203 hwstats->fcoe_noddp = noddp;
6204 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
6205 }
6206 #endif /* IXGBE_FCOE */
6207 break;
6208 default:
6209 break;
6210 }
6211 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
6212 hwstats->bprc += bprc;
6213 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
6214 if (hw->mac.type == ixgbe_mac_82598EB)
6215 hwstats->mprc -= bprc;
6216 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6217 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6218 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6219 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6220 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6221 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6222 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6223 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6224 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
6225 hwstats->lxontxc += lxon;
6226 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
6227 hwstats->lxofftxc += lxoff;
6228 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6229 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6230 /*
6231 * 82598 errata - tx of flow control packets is included in tx counters
6232 */
6233 xon_off_tot = lxon + lxoff;
6234 hwstats->gptc -= xon_off_tot;
6235 hwstats->mptc -= xon_off_tot;
6236 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6237 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6238 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6239 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6240 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6241 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6242 hwstats->ptc64 -= xon_off_tot;
6243 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6244 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6245 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6246 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6247 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6248 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
6249
6250 /* Fill out the OS statistics structure */
6251 netdev->stats.multicast = hwstats->mprc;
6252
6253 /* Rx Errors */
6254 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
6255 netdev->stats.rx_dropped = 0;
6256 netdev->stats.rx_length_errors = hwstats->rlec;
6257 netdev->stats.rx_crc_errors = hwstats->crcerrs;
6258 netdev->stats.rx_missed_errors = total_mpc;
6259 }
6260
6261 /**
6262 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
6263 * @adapter: pointer to the device adapter structure
6264 **/
6265 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
6266 {
6267 struct ixgbe_hw *hw = &adapter->hw;
6268 int i;
6269
6270 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6271 return;
6272
6273 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
6274
6275 /* if interface is down do nothing */
6276 if (test_bit(__IXGBE_DOWN, &adapter->state))
6277 return;
6278
6279 /* do nothing if we are not using signature filters */
6280 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6281 return;
6282
6283 adapter->fdir_overflow++;
6284
6285 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6286 for (i = 0; i < adapter->num_tx_queues; i++)
6287 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
6288 &(adapter->tx_ring[i]->state));
6289 /* re-enable flow director interrupts */
6290 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
6291 } else {
6292 e_err(probe, "failed to finish FDIR re-initialization, "
6293 "ignored adding FDIR ATR filters\n");
6294 }
6295 }
6296
6297 /**
6298 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
6299 * @adapter: pointer to the device adapter structure
6300 *
6301 * This function serves two purposes. First it strobes the interrupt lines
6302 * in order to make certain interrupts are occurring. Secondly it sets the
6303 * bits needed to check for TX hangs. As a result we should immediately
6304 * determine if a hang has occurred.
6305 */
6306 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
6307 {
6308 struct ixgbe_hw *hw = &adapter->hw;
6309 u64 eics = 0;
6310 int i;
6311
6312 /* If we're down, removing or resetting, just bail */
6313 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6314 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6315 test_bit(__IXGBE_RESETTING, &adapter->state))
6316 return;
6317
6318 /* Force detection of hung controller */
6319 if (netif_carrier_ok(adapter->netdev)) {
6320 for (i = 0; i < adapter->num_tx_queues; i++)
6321 set_check_for_tx_hang(adapter->tx_ring[i]);
6322 }
6323
6324 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6325 /*
6326 * for legacy and MSI interrupts don't set any bits
6327 * that are enabled for EIAM, because this operation
6328 * would set *both* EIMS and EICS for any bit in EIAM
6329 */
6330 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6331 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
6332 } else {
6333 /* get one bit for every active tx/rx interrupt vector */
6334 for (i = 0; i < adapter->num_q_vectors; i++) {
6335 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6336 if (qv->rx.ring || qv->tx.ring)
6337 eics |= ((u64)1 << i);
6338 }
6339 }
6340
6341 /* Cause software interrupt to ensure rings are cleaned */
6342 ixgbe_irq_rearm_queues(adapter, eics);
6343 }
6344
6345 /**
6346 * ixgbe_watchdog_update_link - update the link status
6347 * @adapter: pointer to the device adapter structure
6348 * @link_speed: pointer to a u32 to store the link_speed
6349 **/
6350 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
6351 {
6352 struct ixgbe_hw *hw = &adapter->hw;
6353 u32 link_speed = adapter->link_speed;
6354 bool link_up = adapter->link_up;
6355 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
6356
6357 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6358 return;
6359
6360 if (hw->mac.ops.check_link) {
6361 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6362 } else {
6363 /* always assume link is up, if no check link function */
6364 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6365 link_up = true;
6366 }
6367
6368 if (adapter->ixgbe_ieee_pfc)
6369 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6370
6371 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
6372 hw->mac.ops.fc_enable(hw);
6373 ixgbe_set_rx_drop_en(adapter);
6374 }
6375
6376 if (link_up ||
6377 time_after(jiffies, (adapter->link_check_timeout +
6378 IXGBE_TRY_LINK_TIMEOUT))) {
6379 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6380 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6381 IXGBE_WRITE_FLUSH(hw);
6382 }
6383
6384 adapter->link_up = link_up;
6385 adapter->link_speed = link_speed;
6386 }
6387
6388 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6389 {
6390 #ifdef CONFIG_IXGBE_DCB
6391 struct net_device *netdev = adapter->netdev;
6392 struct dcb_app app = {
6393 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6394 .protocol = 0,
6395 };
6396 u8 up = 0;
6397
6398 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6399 up = dcb_ieee_getapp_mask(netdev, &app);
6400
6401 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6402 #endif
6403 }
6404
6405 /**
6406 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6407 * print link up message
6408 * @adapter: pointer to the device adapter structure
6409 **/
6410 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
6411 {
6412 struct net_device *netdev = adapter->netdev;
6413 struct ixgbe_hw *hw = &adapter->hw;
6414 struct net_device *upper;
6415 struct list_head *iter;
6416 u32 link_speed = adapter->link_speed;
6417 const char *speed_str;
6418 bool flow_rx, flow_tx;
6419
6420 /* only continue if link was previously down */
6421 if (netif_carrier_ok(netdev))
6422 return;
6423
6424 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
6425
6426 switch (hw->mac.type) {
6427 case ixgbe_mac_82598EB: {
6428 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6429 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6430 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6431 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6432 }
6433 break;
6434 case ixgbe_mac_X540:
6435 case ixgbe_mac_X550:
6436 case ixgbe_mac_X550EM_x:
6437 case ixgbe_mac_82599EB: {
6438 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6439 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6440 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6441 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6442 }
6443 break;
6444 default:
6445 flow_tx = false;
6446 flow_rx = false;
6447 break;
6448 }
6449
6450 adapter->last_rx_ptp_check = jiffies;
6451
6452 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6453 ixgbe_ptp_start_cyclecounter(adapter);
6454
6455 switch (link_speed) {
6456 case IXGBE_LINK_SPEED_10GB_FULL:
6457 speed_str = "10 Gbps";
6458 break;
6459 case IXGBE_LINK_SPEED_2_5GB_FULL:
6460 speed_str = "2.5 Gbps";
6461 break;
6462 case IXGBE_LINK_SPEED_1GB_FULL:
6463 speed_str = "1 Gbps";
6464 break;
6465 case IXGBE_LINK_SPEED_100_FULL:
6466 speed_str = "100 Mbps";
6467 break;
6468 default:
6469 speed_str = "unknown speed";
6470 break;
6471 }
6472 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
6473 ((flow_rx && flow_tx) ? "RX/TX" :
6474 (flow_rx ? "RX" :
6475 (flow_tx ? "TX" : "None"))));
6476
6477 netif_carrier_on(netdev);
6478 ixgbe_check_vf_rate_limit(adapter);
6479
6480 /* enable transmits */
6481 netif_tx_wake_all_queues(adapter->netdev);
6482
6483 /* enable any upper devices */
6484 rtnl_lock();
6485 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6486 if (netif_is_macvlan(upper)) {
6487 struct macvlan_dev *vlan = netdev_priv(upper);
6488
6489 if (vlan->fwd_priv)
6490 netif_tx_wake_all_queues(upper);
6491 }
6492 }
6493 rtnl_unlock();
6494
6495 /* update the default user priority for VFs */
6496 ixgbe_update_default_up(adapter);
6497
6498 /* ping all the active vfs to let them know link has changed */
6499 ixgbe_ping_all_vfs(adapter);
6500 }
6501
6502 /**
6503 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6504 * print link down message
6505 * @adapter: pointer to the adapter structure
6506 **/
6507 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
6508 {
6509 struct net_device *netdev = adapter->netdev;
6510 struct ixgbe_hw *hw = &adapter->hw;
6511
6512 adapter->link_up = false;
6513 adapter->link_speed = 0;
6514
6515 /* only continue if link was up previously */
6516 if (!netif_carrier_ok(netdev))
6517 return;
6518
6519 /* poll for SFP+ cable when link is down */
6520 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6521 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6522
6523 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6524 ixgbe_ptp_start_cyclecounter(adapter);
6525
6526 e_info(drv, "NIC Link is Down\n");
6527 netif_carrier_off(netdev);
6528
6529 /* ping all the active vfs to let them know link has changed */
6530 ixgbe_ping_all_vfs(adapter);
6531 }
6532
6533 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6534 {
6535 int i;
6536
6537 for (i = 0; i < adapter->num_tx_queues; i++) {
6538 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6539
6540 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6541 return true;
6542 }
6543
6544 return false;
6545 }
6546
6547 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6548 {
6549 struct ixgbe_hw *hw = &adapter->hw;
6550 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6551 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6552
6553 int i, j;
6554
6555 if (!adapter->num_vfs)
6556 return false;
6557
6558 /* resetting the PF is only needed for MAC before X550 */
6559 if (hw->mac.type >= ixgbe_mac_X550)
6560 return false;
6561
6562 for (i = 0; i < adapter->num_vfs; i++) {
6563 for (j = 0; j < q_per_pool; j++) {
6564 u32 h, t;
6565
6566 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6567 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6568
6569 if (h != t)
6570 return true;
6571 }
6572 }
6573
6574 return false;
6575 }
6576
6577 /**
6578 * ixgbe_watchdog_flush_tx - flush queues on link down
6579 * @adapter: pointer to the device adapter structure
6580 **/
6581 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6582 {
6583 if (!netif_carrier_ok(adapter->netdev)) {
6584 if (ixgbe_ring_tx_pending(adapter) ||
6585 ixgbe_vf_tx_pending(adapter)) {
6586 /* We've lost link, so the controller stops DMA,
6587 * but we've got queued Tx work that's never going
6588 * to get done, so reset controller to flush Tx.
6589 * (Do the reset outside of interrupt context).
6590 */
6591 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
6592 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6593 }
6594 }
6595 }
6596
6597 #ifdef CONFIG_PCI_IOV
6598 static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6599 struct pci_dev *vfdev)
6600 {
6601 if (!pci_wait_for_pending_transaction(vfdev))
6602 e_dev_warn("Issuing VFLR with pending transactions\n");
6603
6604 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6605 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6606
6607 msleep(100);
6608 }
6609
6610 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6611 {
6612 struct ixgbe_hw *hw = &adapter->hw;
6613 struct pci_dev *pdev = adapter->pdev;
6614 struct pci_dev *vfdev;
6615 u32 gpc;
6616 int pos;
6617 unsigned short vf_id;
6618
6619 if (!(netif_carrier_ok(adapter->netdev)))
6620 return;
6621
6622 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6623 if (gpc) /* If incrementing then no need for the check below */
6624 return;
6625 /* Check to see if a bad DMA write target from an errant or
6626 * malicious VF has caused a PCIe error. If so then we can
6627 * issue a VFLR to the offending VF(s) and then resume without
6628 * requesting a full slot reset.
6629 */
6630
6631 if (!pdev)
6632 return;
6633
6634 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
6635 if (!pos)
6636 return;
6637
6638 /* get the device ID for the VF */
6639 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &vf_id);
6640
6641 /* check status reg for all VFs owned by this PF */
6642 vfdev = pci_get_device(pdev->vendor, vf_id, NULL);
6643 while (vfdev) {
6644 if (vfdev->is_virtfn && (vfdev->physfn == pdev)) {
6645 u16 status_reg;
6646
6647 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6648 if (status_reg & PCI_STATUS_REC_MASTER_ABORT)
6649 /* issue VFLR */
6650 ixgbe_issue_vf_flr(adapter, vfdev);
6651 }
6652
6653 vfdev = pci_get_device(pdev->vendor, vf_id, vfdev);
6654 }
6655 }
6656
6657 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6658 {
6659 u32 ssvpc;
6660
6661 /* Do not perform spoof check for 82598 or if not in IOV mode */
6662 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6663 adapter->num_vfs == 0)
6664 return;
6665
6666 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6667
6668 /*
6669 * ssvpc register is cleared on read, if zero then no
6670 * spoofed packets in the last interval.
6671 */
6672 if (!ssvpc)
6673 return;
6674
6675 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
6676 }
6677 #else
6678 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
6679 {
6680 }
6681
6682 static void
6683 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
6684 {
6685 }
6686 #endif /* CONFIG_PCI_IOV */
6687
6688
6689 /**
6690 * ixgbe_watchdog_subtask - check and bring link up
6691 * @adapter: pointer to the device adapter structure
6692 **/
6693 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6694 {
6695 /* if interface is down, removing or resetting, do nothing */
6696 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6697 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6698 test_bit(__IXGBE_RESETTING, &adapter->state))
6699 return;
6700
6701 ixgbe_watchdog_update_link(adapter);
6702
6703 if (adapter->link_up)
6704 ixgbe_watchdog_link_is_up(adapter);
6705 else
6706 ixgbe_watchdog_link_is_down(adapter);
6707
6708 ixgbe_check_for_bad_vf(adapter);
6709 ixgbe_spoof_check(adapter);
6710 ixgbe_update_stats(adapter);
6711
6712 ixgbe_watchdog_flush_tx(adapter);
6713 }
6714
6715 /**
6716 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6717 * @adapter: the ixgbe adapter structure
6718 **/
6719 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6720 {
6721 struct ixgbe_hw *hw = &adapter->hw;
6722 s32 err;
6723
6724 /* not searching for SFP so there is nothing to do here */
6725 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6726 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6727 return;
6728
6729 if (adapter->sfp_poll_time &&
6730 time_after(adapter->sfp_poll_time, jiffies))
6731 return; /* If not yet time to poll for SFP */
6732
6733 /* someone else is in init, wait until next service event */
6734 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6735 return;
6736
6737 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
6738
6739 err = hw->phy.ops.identify_sfp(hw);
6740 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6741 goto sfp_out;
6742
6743 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6744 /* If no cable is present, then we need to reset
6745 * the next time we find a good cable. */
6746 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6747 }
6748
6749 /* exit on error */
6750 if (err)
6751 goto sfp_out;
6752
6753 /* exit if reset not needed */
6754 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6755 goto sfp_out;
6756
6757 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6758
6759 /*
6760 * A module may be identified correctly, but the EEPROM may not have
6761 * support for that module. setup_sfp() will fail in that case, so
6762 * we should not allow that module to load.
6763 */
6764 if (hw->mac.type == ixgbe_mac_82598EB)
6765 err = hw->phy.ops.reset(hw);
6766 else
6767 err = hw->mac.ops.setup_sfp(hw);
6768
6769 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6770 goto sfp_out;
6771
6772 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6773 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6774
6775 sfp_out:
6776 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6777
6778 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6779 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6780 e_dev_err("failed to initialize because an unsupported "
6781 "SFP+ module type was detected.\n");
6782 e_dev_err("Reload the driver after installing a "
6783 "supported module.\n");
6784 unregister_netdev(adapter->netdev);
6785 }
6786 }
6787
6788 /**
6789 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6790 * @adapter: the ixgbe adapter structure
6791 **/
6792 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6793 {
6794 struct ixgbe_hw *hw = &adapter->hw;
6795 u32 speed;
6796 bool autoneg = false;
6797
6798 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6799 return;
6800
6801 /* someone else is in init, wait until next service event */
6802 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6803 return;
6804
6805 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6806
6807 speed = hw->phy.autoneg_advertised;
6808 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
6809 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
6810
6811 /* setup the highest link when no autoneg */
6812 if (!autoneg) {
6813 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6814 speed = IXGBE_LINK_SPEED_10GB_FULL;
6815 }
6816 }
6817
6818 if (hw->mac.ops.setup_link)
6819 hw->mac.ops.setup_link(hw, speed, true);
6820
6821 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6822 adapter->link_check_timeout = jiffies;
6823 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6824 }
6825
6826 /**
6827 * ixgbe_service_timer - Timer Call-back
6828 * @data: pointer to adapter cast into an unsigned long
6829 **/
6830 static void ixgbe_service_timer(unsigned long data)
6831 {
6832 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6833 unsigned long next_event_offset;
6834
6835 /* poll faster when waiting for link */
6836 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6837 next_event_offset = HZ / 10;
6838 else
6839 next_event_offset = HZ * 2;
6840
6841 /* Reset the timer */
6842 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6843
6844 ixgbe_service_event_schedule(adapter);
6845 }
6846
6847 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
6848 {
6849 struct ixgbe_hw *hw = &adapter->hw;
6850 u32 status;
6851
6852 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
6853 return;
6854
6855 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
6856
6857 if (!hw->phy.ops.handle_lasi)
6858 return;
6859
6860 status = hw->phy.ops.handle_lasi(&adapter->hw);
6861 if (status != IXGBE_ERR_OVERTEMP)
6862 return;
6863
6864 e_crit(drv, "%s\n", ixgbe_overheat_msg);
6865 }
6866
6867 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6868 {
6869 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6870 return;
6871
6872 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6873
6874 /* If we're already down, removing or resetting, just bail */
6875 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6876 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6877 test_bit(__IXGBE_RESETTING, &adapter->state))
6878 return;
6879
6880 ixgbe_dump(adapter);
6881 netdev_err(adapter->netdev, "Reset adapter\n");
6882 adapter->tx_timeout_count++;
6883
6884 rtnl_lock();
6885 ixgbe_reinit_locked(adapter);
6886 rtnl_unlock();
6887 }
6888
6889 /**
6890 * ixgbe_service_task - manages and runs subtasks
6891 * @work: pointer to work_struct containing our data
6892 **/
6893 static void ixgbe_service_task(struct work_struct *work)
6894 {
6895 struct ixgbe_adapter *adapter = container_of(work,
6896 struct ixgbe_adapter,
6897 service_task);
6898 if (ixgbe_removed(adapter->hw.hw_addr)) {
6899 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6900 rtnl_lock();
6901 ixgbe_down(adapter);
6902 rtnl_unlock();
6903 }
6904 ixgbe_service_event_complete(adapter);
6905 return;
6906 }
6907 #ifdef CONFIG_IXGBE_VXLAN
6908 if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) {
6909 adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED;
6910 vxlan_get_rx_port(adapter->netdev);
6911 }
6912 #endif /* CONFIG_IXGBE_VXLAN */
6913 ixgbe_reset_subtask(adapter);
6914 ixgbe_phy_interrupt_subtask(adapter);
6915 ixgbe_sfp_detection_subtask(adapter);
6916 ixgbe_sfp_link_config_subtask(adapter);
6917 ixgbe_check_overtemp_subtask(adapter);
6918 ixgbe_watchdog_subtask(adapter);
6919 ixgbe_fdir_reinit_subtask(adapter);
6920 ixgbe_check_hang_subtask(adapter);
6921
6922 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
6923 ixgbe_ptp_overflow_check(adapter);
6924 ixgbe_ptp_rx_hang(adapter);
6925 }
6926
6927 ixgbe_service_event_complete(adapter);
6928 }
6929
6930 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6931 struct ixgbe_tx_buffer *first,
6932 u8 *hdr_len)
6933 {
6934 struct sk_buff *skb = first->skb;
6935 u32 vlan_macip_lens, type_tucmd;
6936 u32 mss_l4len_idx, l4len;
6937 int err;
6938
6939 if (skb->ip_summed != CHECKSUM_PARTIAL)
6940 return 0;
6941
6942 if (!skb_is_gso(skb))
6943 return 0;
6944
6945 err = skb_cow_head(skb, 0);
6946 if (err < 0)
6947 return err;
6948
6949 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6950 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6951
6952 if (first->protocol == htons(ETH_P_IP)) {
6953 struct iphdr *iph = ip_hdr(skb);
6954 iph->tot_len = 0;
6955 iph->check = 0;
6956 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6957 iph->daddr, 0,
6958 IPPROTO_TCP,
6959 0);
6960 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6961 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6962 IXGBE_TX_FLAGS_CSUM |
6963 IXGBE_TX_FLAGS_IPV4;
6964 } else if (skb_is_gso_v6(skb)) {
6965 ipv6_hdr(skb)->payload_len = 0;
6966 tcp_hdr(skb)->check =
6967 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6968 &ipv6_hdr(skb)->daddr,
6969 0, IPPROTO_TCP, 0);
6970 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6971 IXGBE_TX_FLAGS_CSUM;
6972 }
6973
6974 /* compute header lengths */
6975 l4len = tcp_hdrlen(skb);
6976 *hdr_len = skb_transport_offset(skb) + l4len;
6977
6978 /* update gso size and bytecount with header size */
6979 first->gso_segs = skb_shinfo(skb)->gso_segs;
6980 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6981
6982 /* mss_l4len_id: use 0 as index for TSO */
6983 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6984 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6985
6986 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6987 vlan_macip_lens = skb_network_header_len(skb);
6988 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6989 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6990
6991 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6992 mss_l4len_idx);
6993
6994 return 1;
6995 }
6996
6997 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6998 struct ixgbe_tx_buffer *first)
6999 {
7000 struct sk_buff *skb = first->skb;
7001 u32 vlan_macip_lens = 0;
7002 u32 mss_l4len_idx = 0;
7003 u32 type_tucmd = 0;
7004
7005 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7006 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
7007 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
7008 return;
7009 vlan_macip_lens = skb_network_offset(skb) <<
7010 IXGBE_ADVTXD_MACLEN_SHIFT;
7011 } else {
7012 u8 l4_hdr = 0;
7013 union {
7014 struct iphdr *ipv4;
7015 struct ipv6hdr *ipv6;
7016 u8 *raw;
7017 } network_hdr;
7018 union {
7019 struct tcphdr *tcphdr;
7020 u8 *raw;
7021 } transport_hdr;
7022
7023 if (skb->encapsulation) {
7024 network_hdr.raw = skb_inner_network_header(skb);
7025 transport_hdr.raw = skb_inner_transport_header(skb);
7026 vlan_macip_lens = skb_inner_network_offset(skb) <<
7027 IXGBE_ADVTXD_MACLEN_SHIFT;
7028 } else {
7029 network_hdr.raw = skb_network_header(skb);
7030 transport_hdr.raw = skb_transport_header(skb);
7031 vlan_macip_lens = skb_network_offset(skb) <<
7032 IXGBE_ADVTXD_MACLEN_SHIFT;
7033 }
7034
7035 /* use first 4 bits to determine IP version */
7036 switch (network_hdr.ipv4->version) {
7037 case IPVERSION:
7038 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
7039 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
7040 l4_hdr = network_hdr.ipv4->protocol;
7041 break;
7042 case 6:
7043 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
7044 l4_hdr = network_hdr.ipv6->nexthdr;
7045 break;
7046 default:
7047 if (unlikely(net_ratelimit())) {
7048 dev_warn(tx_ring->dev,
7049 "partial checksum but version=%d\n",
7050 network_hdr.ipv4->version);
7051 }
7052 }
7053
7054 switch (l4_hdr) {
7055 case IPPROTO_TCP:
7056 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
7057 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) <<
7058 IXGBE_ADVTXD_L4LEN_SHIFT;
7059 break;
7060 case IPPROTO_SCTP:
7061 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
7062 mss_l4len_idx = sizeof(struct sctphdr) <<
7063 IXGBE_ADVTXD_L4LEN_SHIFT;
7064 break;
7065 case IPPROTO_UDP:
7066 mss_l4len_idx = sizeof(struct udphdr) <<
7067 IXGBE_ADVTXD_L4LEN_SHIFT;
7068 break;
7069 default:
7070 if (unlikely(net_ratelimit())) {
7071 dev_warn(tx_ring->dev,
7072 "partial checksum but l4 proto=%x!\n",
7073 l4_hdr);
7074 }
7075 break;
7076 }
7077
7078 /* update TX checksum flag */
7079 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7080 }
7081
7082 /* vlan_macip_lens: MACLEN, VLAN tag */
7083 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
7084
7085 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
7086 type_tucmd, mss_l4len_idx);
7087 }
7088
7089 #define IXGBE_SET_FLAG(_input, _flag, _result) \
7090 ((_flag <= _result) ? \
7091 ((u32)(_input & _flag) * (_result / _flag)) : \
7092 ((u32)(_input & _flag) / (_flag / _result)))
7093
7094 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
7095 {
7096 /* set type for advanced descriptor with frame checksum insertion */
7097 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7098 IXGBE_ADVTXD_DCMD_DEXT |
7099 IXGBE_ADVTXD_DCMD_IFCS;
7100
7101 /* set HW vlan bit if vlan is present */
7102 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7103 IXGBE_ADVTXD_DCMD_VLE);
7104
7105 /* set segmentation enable bits for TSO/FSO */
7106 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7107 IXGBE_ADVTXD_DCMD_TSE);
7108
7109 /* set timestamp bit if present */
7110 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7111 IXGBE_ADVTXD_MAC_TSTAMP);
7112
7113 /* insert frame checksum */
7114 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
7115
7116 return cmd_type;
7117 }
7118
7119 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7120 u32 tx_flags, unsigned int paylen)
7121 {
7122 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
7123
7124 /* enable L4 checksum for TSO and TX checksum offload */
7125 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7126 IXGBE_TX_FLAGS_CSUM,
7127 IXGBE_ADVTXD_POPTS_TXSM);
7128
7129 /* enble IPv4 checksum for TSO */
7130 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7131 IXGBE_TX_FLAGS_IPV4,
7132 IXGBE_ADVTXD_POPTS_IXSM);
7133
7134 /*
7135 * Check Context must be set if Tx switch is enabled, which it
7136 * always is for case where virtual functions are running
7137 */
7138 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7139 IXGBE_TX_FLAGS_CC,
7140 IXGBE_ADVTXD_CC);
7141
7142 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
7143 }
7144
7145 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7146 {
7147 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7148
7149 /* Herbert's original patch had:
7150 * smp_mb__after_netif_stop_queue();
7151 * but since that doesn't exist yet, just open code it.
7152 */
7153 smp_mb();
7154
7155 /* We need to check again in a case another CPU has just
7156 * made room available.
7157 */
7158 if (likely(ixgbe_desc_unused(tx_ring) < size))
7159 return -EBUSY;
7160
7161 /* A reprieve! - use start_queue because it doesn't call schedule */
7162 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7163 ++tx_ring->tx_stats.restart_queue;
7164 return 0;
7165 }
7166
7167 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7168 {
7169 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7170 return 0;
7171
7172 return __ixgbe_maybe_stop_tx(tx_ring, size);
7173 }
7174
7175 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7176 IXGBE_TXD_CMD_RS)
7177
7178 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
7179 struct ixgbe_tx_buffer *first,
7180 const u8 hdr_len)
7181 {
7182 struct sk_buff *skb = first->skb;
7183 struct ixgbe_tx_buffer *tx_buffer;
7184 union ixgbe_adv_tx_desc *tx_desc;
7185 struct skb_frag_struct *frag;
7186 dma_addr_t dma;
7187 unsigned int data_len, size;
7188 u32 tx_flags = first->tx_flags;
7189 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
7190 u16 i = tx_ring->next_to_use;
7191
7192 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7193
7194 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7195
7196 size = skb_headlen(skb);
7197 data_len = skb->data_len;
7198
7199 #ifdef IXGBE_FCOE
7200 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
7201 if (data_len < sizeof(struct fcoe_crc_eof)) {
7202 size -= sizeof(struct fcoe_crc_eof) - data_len;
7203 data_len = 0;
7204 } else {
7205 data_len -= sizeof(struct fcoe_crc_eof);
7206 }
7207 }
7208
7209 #endif
7210 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
7211
7212 tx_buffer = first;
7213
7214 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7215 if (dma_mapping_error(tx_ring->dev, dma))
7216 goto dma_error;
7217
7218 /* record length, and DMA address */
7219 dma_unmap_len_set(tx_buffer, len, size);
7220 dma_unmap_addr_set(tx_buffer, dma, dma);
7221
7222 tx_desc->read.buffer_addr = cpu_to_le64(dma);
7223
7224 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
7225 tx_desc->read.cmd_type_len =
7226 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
7227
7228 i++;
7229 tx_desc++;
7230 if (i == tx_ring->count) {
7231 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7232 i = 0;
7233 }
7234 tx_desc->read.olinfo_status = 0;
7235
7236 dma += IXGBE_MAX_DATA_PER_TXD;
7237 size -= IXGBE_MAX_DATA_PER_TXD;
7238
7239 tx_desc->read.buffer_addr = cpu_to_le64(dma);
7240 }
7241
7242 if (likely(!data_len))
7243 break;
7244
7245 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
7246
7247 i++;
7248 tx_desc++;
7249 if (i == tx_ring->count) {
7250 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7251 i = 0;
7252 }
7253 tx_desc->read.olinfo_status = 0;
7254
7255 #ifdef IXGBE_FCOE
7256 size = min_t(unsigned int, data_len, skb_frag_size(frag));
7257 #else
7258 size = skb_frag_size(frag);
7259 #endif
7260 data_len -= size;
7261
7262 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7263 DMA_TO_DEVICE);
7264
7265 tx_buffer = &tx_ring->tx_buffer_info[i];
7266 }
7267
7268 /* write last descriptor with RS and EOP bits */
7269 cmd_type |= size | IXGBE_TXD_CMD;
7270 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
7271
7272 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
7273
7274 /* set the timestamp */
7275 first->time_stamp = jiffies;
7276
7277 /*
7278 * Force memory writes to complete before letting h/w know there
7279 * are new descriptors to fetch. (Only applicable for weak-ordered
7280 * memory model archs, such as IA-64).
7281 *
7282 * We also need this memory barrier to make certain all of the
7283 * status bits have been updated before next_to_watch is written.
7284 */
7285 wmb();
7286
7287 /* set next_to_watch value indicating a packet is present */
7288 first->next_to_watch = tx_desc;
7289
7290 i++;
7291 if (i == tx_ring->count)
7292 i = 0;
7293
7294 tx_ring->next_to_use = i;
7295
7296 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7297
7298 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
7299 writel(i, tx_ring->tail);
7300
7301 /* we need this if more than one processor can write to our tail
7302 * at a time, it synchronizes IO on IA64/Altix systems
7303 */
7304 mmiowb();
7305 }
7306
7307 return;
7308 dma_error:
7309 dev_err(tx_ring->dev, "TX DMA map failed\n");
7310
7311 /* clear dma mappings for failed tx_buffer_info map */
7312 for (;;) {
7313 tx_buffer = &tx_ring->tx_buffer_info[i];
7314 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7315 if (tx_buffer == first)
7316 break;
7317 if (i == 0)
7318 i = tx_ring->count;
7319 i--;
7320 }
7321
7322 tx_ring->next_to_use = i;
7323 }
7324
7325 static void ixgbe_atr(struct ixgbe_ring *ring,
7326 struct ixgbe_tx_buffer *first)
7327 {
7328 struct ixgbe_q_vector *q_vector = ring->q_vector;
7329 union ixgbe_atr_hash_dword input = { .dword = 0 };
7330 union ixgbe_atr_hash_dword common = { .dword = 0 };
7331 union {
7332 unsigned char *network;
7333 struct iphdr *ipv4;
7334 struct ipv6hdr *ipv6;
7335 } hdr;
7336 struct tcphdr *th;
7337 struct sk_buff *skb;
7338 #ifdef CONFIG_IXGBE_VXLAN
7339 u8 encap = false;
7340 #endif /* CONFIG_IXGBE_VXLAN */
7341 __be16 vlan_id;
7342
7343 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7344 if (!q_vector)
7345 return;
7346
7347 /* do nothing if sampling is disabled */
7348 if (!ring->atr_sample_rate)
7349 return;
7350
7351 ring->atr_count++;
7352
7353 /* snag network header to get L4 type and address */
7354 skb = first->skb;
7355 hdr.network = skb_network_header(skb);
7356 if (skb->encapsulation) {
7357 #ifdef CONFIG_IXGBE_VXLAN
7358 struct ixgbe_adapter *adapter = q_vector->adapter;
7359
7360 if (!adapter->vxlan_port)
7361 return;
7362 if (first->protocol != htons(ETH_P_IP) ||
7363 hdr.ipv4->version != IPVERSION ||
7364 hdr.ipv4->protocol != IPPROTO_UDP) {
7365 return;
7366 }
7367 if (ntohs(udp_hdr(skb)->dest) != adapter->vxlan_port)
7368 return;
7369 encap = true;
7370 hdr.network = skb_inner_network_header(skb);
7371 th = inner_tcp_hdr(skb);
7372 #else
7373 return;
7374 #endif /* CONFIG_IXGBE_VXLAN */
7375 } else {
7376 /* Currently only IPv4/IPv6 with TCP is supported */
7377 if ((first->protocol != htons(ETH_P_IPV6) ||
7378 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
7379 (first->protocol != htons(ETH_P_IP) ||
7380 hdr.ipv4->protocol != IPPROTO_TCP))
7381 return;
7382 th = tcp_hdr(skb);
7383 }
7384
7385 /* skip this packet since it is invalid or the socket is closing */
7386 if (!th || th->fin)
7387 return;
7388
7389 /* sample on all syn packets or once every atr sample count */
7390 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7391 return;
7392
7393 /* reset sample count */
7394 ring->atr_count = 0;
7395
7396 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
7397
7398 /*
7399 * src and dst are inverted, think how the receiver sees them
7400 *
7401 * The input is broken into two sections, a non-compressed section
7402 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7403 * is XORed together and stored in the compressed dword.
7404 */
7405 input.formatted.vlan_id = vlan_id;
7406
7407 /*
7408 * since src port and flex bytes occupy the same word XOR them together
7409 * and write the value to source port portion of compressed dword
7410 */
7411 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
7412 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
7413 else
7414 common.port.src ^= th->dest ^ first->protocol;
7415 common.port.dst ^= th->source;
7416
7417 if (first->protocol == htons(ETH_P_IP)) {
7418 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7419 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7420 } else {
7421 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7422 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7423 hdr.ipv6->saddr.s6_addr32[1] ^
7424 hdr.ipv6->saddr.s6_addr32[2] ^
7425 hdr.ipv6->saddr.s6_addr32[3] ^
7426 hdr.ipv6->daddr.s6_addr32[0] ^
7427 hdr.ipv6->daddr.s6_addr32[1] ^
7428 hdr.ipv6->daddr.s6_addr32[2] ^
7429 hdr.ipv6->daddr.s6_addr32[3];
7430 }
7431
7432 #ifdef CONFIG_IXGBE_VXLAN
7433 if (encap)
7434 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
7435 #endif /* CONFIG_IXGBE_VXLAN */
7436
7437 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
7438 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7439 input, common, ring->queue_index);
7440 }
7441
7442 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
7443 void *accel_priv, select_queue_fallback_t fallback)
7444 {
7445 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7446 #ifdef IXGBE_FCOE
7447 struct ixgbe_adapter *adapter;
7448 struct ixgbe_ring_feature *f;
7449 int txq;
7450 #endif
7451
7452 if (fwd_adapter)
7453 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7454
7455 #ifdef IXGBE_FCOE
7456
7457 /*
7458 * only execute the code below if protocol is FCoE
7459 * or FIP and we have FCoE enabled on the adapter
7460 */
7461 switch (vlan_get_protocol(skb)) {
7462 case htons(ETH_P_FCOE):
7463 case htons(ETH_P_FIP):
7464 adapter = netdev_priv(dev);
7465
7466 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7467 break;
7468 default:
7469 return fallback(dev, skb);
7470 }
7471
7472 f = &adapter->ring_feature[RING_F_FCOE];
7473
7474 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7475 smp_processor_id();
7476
7477 while (txq >= f->indices)
7478 txq -= f->indices;
7479
7480 return txq + f->offset;
7481 #else
7482 return fallback(dev, skb);
7483 #endif
7484 }
7485
7486 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
7487 struct ixgbe_adapter *adapter,
7488 struct ixgbe_ring *tx_ring)
7489 {
7490 struct ixgbe_tx_buffer *first;
7491 int tso;
7492 u32 tx_flags = 0;
7493 unsigned short f;
7494 u16 count = TXD_USE_COUNT(skb_headlen(skb));
7495 __be16 protocol = skb->protocol;
7496 u8 hdr_len = 0;
7497
7498 /*
7499 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
7500 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
7501 * + 2 desc gap to keep tail from touching head,
7502 * + 1 desc for context descriptor,
7503 * otherwise try next time
7504 */
7505 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7506 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7507
7508 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7509 tx_ring->tx_stats.tx_busy++;
7510 return NETDEV_TX_BUSY;
7511 }
7512
7513 /* record the location of the first descriptor for this packet */
7514 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7515 first->skb = skb;
7516 first->bytecount = skb->len;
7517 first->gso_segs = 1;
7518
7519 /* if we have a HW VLAN tag being added default to the HW one */
7520 if (skb_vlan_tag_present(skb)) {
7521 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7522 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7523 /* else if it is a SW VLAN check the next protocol and store the tag */
7524 } else if (protocol == htons(ETH_P_8021Q)) {
7525 struct vlan_hdr *vhdr, _vhdr;
7526 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7527 if (!vhdr)
7528 goto out_drop;
7529
7530 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7531 IXGBE_TX_FLAGS_VLAN_SHIFT;
7532 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7533 }
7534 protocol = vlan_get_protocol(skb);
7535
7536 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7537 adapter->ptp_clock &&
7538 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7539 &adapter->state)) {
7540 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7541 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
7542
7543 /* schedule check for Tx timestamp */
7544 adapter->ptp_tx_skb = skb_get(skb);
7545 adapter->ptp_tx_start = jiffies;
7546 schedule_work(&adapter->ptp_tx_work);
7547 }
7548
7549 skb_tx_timestamp(skb);
7550
7551 #ifdef CONFIG_PCI_IOV
7552 /*
7553 * Use the l2switch_enable flag - would be false if the DMA
7554 * Tx switch had been disabled.
7555 */
7556 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7557 tx_flags |= IXGBE_TX_FLAGS_CC;
7558
7559 #endif
7560 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
7561 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7562 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7563 (skb->priority != TC_PRIO_CONTROL))) {
7564 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
7565 tx_flags |= (skb->priority & 0x7) <<
7566 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
7567 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7568 struct vlan_ethhdr *vhdr;
7569
7570 if (skb_cow_head(skb, 0))
7571 goto out_drop;
7572 vhdr = (struct vlan_ethhdr *)skb->data;
7573 vhdr->h_vlan_TCI = htons(tx_flags >>
7574 IXGBE_TX_FLAGS_VLAN_SHIFT);
7575 } else {
7576 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7577 }
7578 }
7579
7580 /* record initial flags and protocol */
7581 first->tx_flags = tx_flags;
7582 first->protocol = protocol;
7583
7584 #ifdef IXGBE_FCOE
7585 /* setup tx offload for FCoE */
7586 if ((protocol == htons(ETH_P_FCOE)) &&
7587 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
7588 tso = ixgbe_fso(tx_ring, first, &hdr_len);
7589 if (tso < 0)
7590 goto out_drop;
7591
7592 goto xmit_fcoe;
7593 }
7594
7595 #endif /* IXGBE_FCOE */
7596 tso = ixgbe_tso(tx_ring, first, &hdr_len);
7597 if (tso < 0)
7598 goto out_drop;
7599 else if (!tso)
7600 ixgbe_tx_csum(tx_ring, first);
7601
7602 /* add the ATR filter if ATR is on */
7603 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7604 ixgbe_atr(tx_ring, first);
7605
7606 #ifdef IXGBE_FCOE
7607 xmit_fcoe:
7608 #endif /* IXGBE_FCOE */
7609 ixgbe_tx_map(tx_ring, first, hdr_len);
7610
7611 return NETDEV_TX_OK;
7612
7613 out_drop:
7614 dev_kfree_skb_any(first->skb);
7615 first->skb = NULL;
7616
7617 return NETDEV_TX_OK;
7618 }
7619
7620 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7621 struct net_device *netdev,
7622 struct ixgbe_ring *ring)
7623 {
7624 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7625 struct ixgbe_ring *tx_ring;
7626
7627 /*
7628 * The minimum packet size for olinfo paylen is 17 so pad the skb
7629 * in order to meet this minimum size requirement.
7630 */
7631 if (skb_put_padto(skb, 17))
7632 return NETDEV_TX_OK;
7633
7634 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7635
7636 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
7637 }
7638
7639 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7640 struct net_device *netdev)
7641 {
7642 return __ixgbe_xmit_frame(skb, netdev, NULL);
7643 }
7644
7645 /**
7646 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7647 * @netdev: network interface device structure
7648 * @p: pointer to an address structure
7649 *
7650 * Returns 0 on success, negative on failure
7651 **/
7652 static int ixgbe_set_mac(struct net_device *netdev, void *p)
7653 {
7654 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7655 struct ixgbe_hw *hw = &adapter->hw;
7656 struct sockaddr *addr = p;
7657 int ret;
7658
7659 if (!is_valid_ether_addr(addr->sa_data))
7660 return -EADDRNOTAVAIL;
7661
7662 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7663 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
7664 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
7665
7666 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7667 return ret > 0 ? 0 : ret;
7668 }
7669
7670 static int
7671 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7672 {
7673 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7674 struct ixgbe_hw *hw = &adapter->hw;
7675 u16 value;
7676 int rc;
7677
7678 if (prtad != hw->phy.mdio.prtad)
7679 return -EINVAL;
7680 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7681 if (!rc)
7682 rc = value;
7683 return rc;
7684 }
7685
7686 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7687 u16 addr, u16 value)
7688 {
7689 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7690 struct ixgbe_hw *hw = &adapter->hw;
7691
7692 if (prtad != hw->phy.mdio.prtad)
7693 return -EINVAL;
7694 return hw->phy.ops.write_reg(hw, addr, devad, value);
7695 }
7696
7697 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7698 {
7699 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7700
7701 switch (cmd) {
7702 case SIOCSHWTSTAMP:
7703 return ixgbe_ptp_set_ts_config(adapter, req);
7704 case SIOCGHWTSTAMP:
7705 return ixgbe_ptp_get_ts_config(adapter, req);
7706 default:
7707 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7708 }
7709 }
7710
7711 /**
7712 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
7713 * netdev->dev_addrs
7714 * @netdev: network interface device structure
7715 *
7716 * Returns non-zero on failure
7717 **/
7718 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7719 {
7720 int err = 0;
7721 struct ixgbe_adapter *adapter = netdev_priv(dev);
7722 struct ixgbe_hw *hw = &adapter->hw;
7723
7724 if (is_valid_ether_addr(hw->mac.san_addr)) {
7725 rtnl_lock();
7726 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
7727 rtnl_unlock();
7728
7729 /* update SAN MAC vmdq pool selection */
7730 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
7731 }
7732 return err;
7733 }
7734
7735 /**
7736 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7737 * netdev->dev_addrs
7738 * @netdev: network interface device structure
7739 *
7740 * Returns non-zero on failure
7741 **/
7742 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7743 {
7744 int err = 0;
7745 struct ixgbe_adapter *adapter = netdev_priv(dev);
7746 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7747
7748 if (is_valid_ether_addr(mac->san_addr)) {
7749 rtnl_lock();
7750 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7751 rtnl_unlock();
7752 }
7753 return err;
7754 }
7755
7756 #ifdef CONFIG_NET_POLL_CONTROLLER
7757 /*
7758 * Polling 'interrupt' - used by things like netconsole to send skbs
7759 * without having to re-enable interrupts. It's not called while
7760 * the interrupt routine is executing.
7761 */
7762 static void ixgbe_netpoll(struct net_device *netdev)
7763 {
7764 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7765 int i;
7766
7767 /* if interface is down do nothing */
7768 if (test_bit(__IXGBE_DOWN, &adapter->state))
7769 return;
7770
7771 /* loop through and schedule all active queues */
7772 for (i = 0; i < adapter->num_q_vectors; i++)
7773 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
7774 }
7775
7776 #endif
7777 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7778 struct rtnl_link_stats64 *stats)
7779 {
7780 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7781 int i;
7782
7783 rcu_read_lock();
7784 for (i = 0; i < adapter->num_rx_queues; i++) {
7785 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7786 u64 bytes, packets;
7787 unsigned int start;
7788
7789 if (ring) {
7790 do {
7791 start = u64_stats_fetch_begin_irq(&ring->syncp);
7792 packets = ring->stats.packets;
7793 bytes = ring->stats.bytes;
7794 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
7795 stats->rx_packets += packets;
7796 stats->rx_bytes += bytes;
7797 }
7798 }
7799
7800 for (i = 0; i < adapter->num_tx_queues; i++) {
7801 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7802 u64 bytes, packets;
7803 unsigned int start;
7804
7805 if (ring) {
7806 do {
7807 start = u64_stats_fetch_begin_irq(&ring->syncp);
7808 packets = ring->stats.packets;
7809 bytes = ring->stats.bytes;
7810 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
7811 stats->tx_packets += packets;
7812 stats->tx_bytes += bytes;
7813 }
7814 }
7815 rcu_read_unlock();
7816 /* following stats updated by ixgbe_watchdog_task() */
7817 stats->multicast = netdev->stats.multicast;
7818 stats->rx_errors = netdev->stats.rx_errors;
7819 stats->rx_length_errors = netdev->stats.rx_length_errors;
7820 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7821 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7822 return stats;
7823 }
7824
7825 #ifdef CONFIG_IXGBE_DCB
7826 /**
7827 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7828 * @adapter: pointer to ixgbe_adapter
7829 * @tc: number of traffic classes currently enabled
7830 *
7831 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7832 * 802.1Q priority maps to a packet buffer that exists.
7833 */
7834 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7835 {
7836 struct ixgbe_hw *hw = &adapter->hw;
7837 u32 reg, rsave;
7838 int i;
7839
7840 /* 82598 have a static priority to TC mapping that can not
7841 * be changed so no validation is needed.
7842 */
7843 if (hw->mac.type == ixgbe_mac_82598EB)
7844 return;
7845
7846 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7847 rsave = reg;
7848
7849 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7850 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7851
7852 /* If up2tc is out of bounds default to zero */
7853 if (up2tc > tc)
7854 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7855 }
7856
7857 if (reg != rsave)
7858 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7859
7860 return;
7861 }
7862
7863 /**
7864 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7865 * @adapter: Pointer to adapter struct
7866 *
7867 * Populate the netdev user priority to tc map
7868 */
7869 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7870 {
7871 struct net_device *dev = adapter->netdev;
7872 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7873 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7874 u8 prio;
7875
7876 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7877 u8 tc = 0;
7878
7879 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7880 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7881 else if (ets)
7882 tc = ets->prio_tc[prio];
7883
7884 netdev_set_prio_tc_map(dev, prio, tc);
7885 }
7886 }
7887
7888 #endif /* CONFIG_IXGBE_DCB */
7889 /**
7890 * ixgbe_setup_tc - configure net_device for multiple traffic classes
7891 *
7892 * @netdev: net device to configure
7893 * @tc: number of traffic classes to enable
7894 */
7895 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7896 {
7897 struct ixgbe_adapter *adapter = netdev_priv(dev);
7898 struct ixgbe_hw *hw = &adapter->hw;
7899 bool pools;
7900
7901 /* Hardware supports up to 8 traffic classes */
7902 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
7903 return -EINVAL;
7904
7905 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
7906 return -EINVAL;
7907
7908 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7909 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7910 return -EBUSY;
7911
7912 /* Hardware has to reinitialize queues and interrupts to
7913 * match packet buffer alignment. Unfortunately, the
7914 * hardware is not flexible enough to do this dynamically.
7915 */
7916 if (netif_running(dev))
7917 ixgbe_close(dev);
7918 ixgbe_clear_interrupt_scheme(adapter);
7919
7920 #ifdef CONFIG_IXGBE_DCB
7921 if (tc) {
7922 netdev_set_num_tc(dev, tc);
7923 ixgbe_set_prio_tc_map(adapter);
7924
7925 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7926
7927 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7928 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
7929 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7930 }
7931 } else {
7932 netdev_reset_tc(dev);
7933
7934 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7935 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7936
7937 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7938
7939 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7940 adapter->dcb_cfg.pfc_mode_enable = false;
7941 }
7942
7943 ixgbe_validate_rtr(adapter, tc);
7944
7945 #endif /* CONFIG_IXGBE_DCB */
7946 ixgbe_init_interrupt_scheme(adapter);
7947
7948 if (netif_running(dev))
7949 return ixgbe_open(dev);
7950
7951 return 0;
7952 }
7953
7954 #ifdef CONFIG_PCI_IOV
7955 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7956 {
7957 struct net_device *netdev = adapter->netdev;
7958
7959 rtnl_lock();
7960 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
7961 rtnl_unlock();
7962 }
7963
7964 #endif
7965 void ixgbe_do_reset(struct net_device *netdev)
7966 {
7967 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7968
7969 if (netif_running(netdev))
7970 ixgbe_reinit_locked(adapter);
7971 else
7972 ixgbe_reset(adapter);
7973 }
7974
7975 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7976 netdev_features_t features)
7977 {
7978 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7979
7980 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7981 if (!(features & NETIF_F_RXCSUM))
7982 features &= ~NETIF_F_LRO;
7983
7984 /* Turn off LRO if not RSC capable */
7985 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7986 features &= ~NETIF_F_LRO;
7987
7988 return features;
7989 }
7990
7991 static int ixgbe_set_features(struct net_device *netdev,
7992 netdev_features_t features)
7993 {
7994 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7995 netdev_features_t changed = netdev->features ^ features;
7996 bool need_reset = false;
7997
7998 /* Make sure RSC matches LRO, reset if change */
7999 if (!(features & NETIF_F_LRO)) {
8000 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
8001 need_reset = true;
8002 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
8003 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
8004 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
8005 if (adapter->rx_itr_setting == 1 ||
8006 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
8007 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8008 need_reset = true;
8009 } else if ((changed ^ features) & NETIF_F_LRO) {
8010 e_info(probe, "rx-usecs set too low, "
8011 "disabling RSC\n");
8012 }
8013 }
8014
8015 /*
8016 * Check if Flow Director n-tuple support was enabled or disabled. If
8017 * the state changed, we need to reset.
8018 */
8019 switch (features & NETIF_F_NTUPLE) {
8020 case NETIF_F_NTUPLE:
8021 /* turn off ATR, enable perfect filters and reset */
8022 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
8023 need_reset = true;
8024
8025 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
8026 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8027 break;
8028 default:
8029 /* turn off perfect filters, enable ATR and reset */
8030 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
8031 need_reset = true;
8032
8033 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8034
8035 /* We cannot enable ATR if SR-IOV is enabled */
8036 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
8037 break;
8038
8039 /* We cannot enable ATR if we have 2 or more traffic classes */
8040 if (netdev_get_num_tc(netdev) > 1)
8041 break;
8042
8043 /* We cannot enable ATR if RSS is disabled */
8044 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
8045 break;
8046
8047 /* A sample rate of 0 indicates ATR disabled */
8048 if (!adapter->atr_sample_rate)
8049 break;
8050
8051 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
8052 break;
8053 }
8054
8055 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8056 ixgbe_vlan_strip_enable(adapter);
8057 else
8058 ixgbe_vlan_strip_disable(adapter);
8059
8060 if (changed & NETIF_F_RXALL)
8061 need_reset = true;
8062
8063 netdev->features = features;
8064
8065 #ifdef CONFIG_IXGBE_VXLAN
8066 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
8067 if (features & NETIF_F_RXCSUM)
8068 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8069 else
8070 ixgbe_clear_vxlan_port(adapter);
8071 }
8072 #endif /* CONFIG_IXGBE_VXLAN */
8073
8074 if (need_reset)
8075 ixgbe_do_reset(netdev);
8076
8077 return 0;
8078 }
8079
8080 #ifdef CONFIG_IXGBE_VXLAN
8081 /**
8082 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up
8083 * @dev: The port's netdev
8084 * @sa_family: Socket Family that VXLAN is notifiying us about
8085 * @port: New UDP port number that VXLAN started listening to
8086 **/
8087 static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8088 __be16 port)
8089 {
8090 struct ixgbe_adapter *adapter = netdev_priv(dev);
8091 struct ixgbe_hw *hw = &adapter->hw;
8092 u16 new_port = ntohs(port);
8093
8094 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8095 return;
8096
8097 if (sa_family == AF_INET6)
8098 return;
8099
8100 if (adapter->vxlan_port == new_port)
8101 return;
8102
8103 if (adapter->vxlan_port) {
8104 netdev_info(dev,
8105 "Hit Max num of VXLAN ports, not adding port %d\n",
8106 new_port);
8107 return;
8108 }
8109
8110 adapter->vxlan_port = new_port;
8111 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, new_port);
8112 }
8113
8114 /**
8115 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away
8116 * @dev: The port's netdev
8117 * @sa_family: Socket Family that VXLAN is notifying us about
8118 * @port: UDP port number that VXLAN stopped listening to
8119 **/
8120 static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8121 __be16 port)
8122 {
8123 struct ixgbe_adapter *adapter = netdev_priv(dev);
8124 u16 new_port = ntohs(port);
8125
8126 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8127 return;
8128
8129 if (sa_family == AF_INET6)
8130 return;
8131
8132 if (adapter->vxlan_port != new_port) {
8133 netdev_info(dev, "Port %d was not found, not deleting\n",
8134 new_port);
8135 return;
8136 }
8137
8138 ixgbe_clear_vxlan_port(adapter);
8139 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8140 }
8141 #endif /* CONFIG_IXGBE_VXLAN */
8142
8143 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8144 struct net_device *dev,
8145 const unsigned char *addr, u16 vid,
8146 u16 flags)
8147 {
8148 /* guarantee we can provide a unique filter for the unicast address */
8149 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
8150 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev))
8151 return -ENOMEM;
8152 }
8153
8154 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
8155 }
8156
8157 /**
8158 * ixgbe_configure_bridge_mode - set various bridge modes
8159 * @adapter - the private structure
8160 * @mode - requested bridge mode
8161 *
8162 * Configure some settings require for various bridge modes.
8163 **/
8164 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
8165 __u16 mode)
8166 {
8167 struct ixgbe_hw *hw = &adapter->hw;
8168 unsigned int p, num_pools;
8169 u32 vmdctl;
8170
8171 switch (mode) {
8172 case BRIDGE_MODE_VEPA:
8173 /* disable Tx loopback, rely on switch hairpin mode */
8174 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
8175
8176 /* must enable Rx switching replication to allow multicast
8177 * packet reception on all VFs, and to enable source address
8178 * pruning.
8179 */
8180 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8181 vmdctl |= IXGBE_VT_CTL_REPLEN;
8182 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8183
8184 /* enable Rx source address pruning. Note, this requires
8185 * replication to be enabled or else it does nothing.
8186 */
8187 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8188 for (p = 0; p < num_pools; p++) {
8189 if (hw->mac.ops.set_source_address_pruning)
8190 hw->mac.ops.set_source_address_pruning(hw,
8191 true,
8192 p);
8193 }
8194 break;
8195 case BRIDGE_MODE_VEB:
8196 /* enable Tx loopback for internal VF/PF communication */
8197 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
8198 IXGBE_PFDTXGSWC_VT_LBEN);
8199
8200 /* disable Rx switching replication unless we have SR-IOV
8201 * virtual functions
8202 */
8203 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8204 if (!adapter->num_vfs)
8205 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
8206 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8207
8208 /* disable Rx source address pruning, since we don't expect to
8209 * be receiving external loopback of our transmitted frames.
8210 */
8211 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8212 for (p = 0; p < num_pools; p++) {
8213 if (hw->mac.ops.set_source_address_pruning)
8214 hw->mac.ops.set_source_address_pruning(hw,
8215 false,
8216 p);
8217 }
8218 break;
8219 default:
8220 return -EINVAL;
8221 }
8222
8223 adapter->bridge_mode = mode;
8224
8225 e_info(drv, "enabling bridge mode: %s\n",
8226 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
8227
8228 return 0;
8229 }
8230
8231 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
8232 struct nlmsghdr *nlh, u16 flags)
8233 {
8234 struct ixgbe_adapter *adapter = netdev_priv(dev);
8235 struct nlattr *attr, *br_spec;
8236 int rem;
8237
8238 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8239 return -EOPNOTSUPP;
8240
8241 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8242 if (!br_spec)
8243 return -EINVAL;
8244
8245 nla_for_each_nested(attr, br_spec, rem) {
8246 int status;
8247 __u16 mode;
8248
8249 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8250 continue;
8251
8252 if (nla_len(attr) < sizeof(mode))
8253 return -EINVAL;
8254
8255 mode = nla_get_u16(attr);
8256 status = ixgbe_configure_bridge_mode(adapter, mode);
8257 if (status)
8258 return status;
8259
8260 break;
8261 }
8262
8263 return 0;
8264 }
8265
8266 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8267 struct net_device *dev,
8268 u32 filter_mask, int nlflags)
8269 {
8270 struct ixgbe_adapter *adapter = netdev_priv(dev);
8271
8272 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8273 return 0;
8274
8275 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
8276 adapter->bridge_mode, 0, 0, nlflags,
8277 filter_mask, NULL);
8278 }
8279
8280 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
8281 {
8282 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
8283 struct ixgbe_adapter *adapter = netdev_priv(pdev);
8284 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
8285 unsigned int limit;
8286 int pool, err;
8287
8288 /* Hardware has a limited number of available pools. Each VF, and the
8289 * PF require a pool. Check to ensure we don't attempt to use more
8290 * then the available number of pools.
8291 */
8292 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
8293 return ERR_PTR(-EINVAL);
8294
8295 #ifdef CONFIG_RPS
8296 if (vdev->num_rx_queues != vdev->num_tx_queues) {
8297 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
8298 vdev->name);
8299 return ERR_PTR(-EINVAL);
8300 }
8301 #endif
8302 /* Check for hardware restriction on number of rx/tx queues */
8303 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
8304 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
8305 netdev_info(pdev,
8306 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
8307 pdev->name);
8308 return ERR_PTR(-EINVAL);
8309 }
8310
8311 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8312 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
8313 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
8314 return ERR_PTR(-EBUSY);
8315
8316 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL);
8317 if (!fwd_adapter)
8318 return ERR_PTR(-ENOMEM);
8319
8320 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
8321 adapter->num_rx_pools++;
8322 set_bit(pool, &adapter->fwd_bitmask);
8323 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8324
8325 /* Enable VMDq flag so device will be set in VM mode */
8326 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
8327 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
8328 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
8329
8330 /* Force reinit of ring allocation with VMDQ enabled */
8331 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8332 if (err)
8333 goto fwd_add_err;
8334 fwd_adapter->pool = pool;
8335 fwd_adapter->real_adapter = adapter;
8336 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
8337 if (err)
8338 goto fwd_add_err;
8339 netif_tx_start_all_queues(vdev);
8340 return fwd_adapter;
8341 fwd_add_err:
8342 /* unwind counter and free adapter struct */
8343 netdev_info(pdev,
8344 "%s: dfwd hardware acceleration failed\n", vdev->name);
8345 clear_bit(pool, &adapter->fwd_bitmask);
8346 adapter->num_rx_pools--;
8347 kfree(fwd_adapter);
8348 return ERR_PTR(err);
8349 }
8350
8351 static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8352 {
8353 struct ixgbe_fwd_adapter *fwd_adapter = priv;
8354 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
8355 unsigned int limit;
8356
8357 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
8358 adapter->num_rx_pools--;
8359
8360 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8361 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
8362 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
8363 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8364 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
8365 fwd_adapter->pool, adapter->num_rx_pools,
8366 fwd_adapter->rx_base_queue,
8367 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
8368 adapter->fwd_bitmask);
8369 kfree(fwd_adapter);
8370 }
8371
8372 #define IXGBE_MAX_TUNNEL_HDR_LEN 80
8373 static netdev_features_t
8374 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
8375 netdev_features_t features)
8376 {
8377 if (!skb->encapsulation)
8378 return features;
8379
8380 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) >
8381 IXGBE_MAX_TUNNEL_HDR_LEN))
8382 return features & ~NETIF_F_ALL_CSUM;
8383
8384 return features;
8385 }
8386
8387 static const struct net_device_ops ixgbe_netdev_ops = {
8388 .ndo_open = ixgbe_open,
8389 .ndo_stop = ixgbe_close,
8390 .ndo_start_xmit = ixgbe_xmit_frame,
8391 .ndo_select_queue = ixgbe_select_queue,
8392 .ndo_set_rx_mode = ixgbe_set_rx_mode,
8393 .ndo_validate_addr = eth_validate_addr,
8394 .ndo_set_mac_address = ixgbe_set_mac,
8395 .ndo_change_mtu = ixgbe_change_mtu,
8396 .ndo_tx_timeout = ixgbe_tx_timeout,
8397 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
8398 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
8399 .ndo_do_ioctl = ixgbe_ioctl,
8400 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
8401 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
8402 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
8403 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
8404 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
8405 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
8406 .ndo_get_stats64 = ixgbe_get_stats64,
8407 #ifdef CONFIG_IXGBE_DCB
8408 .ndo_setup_tc = ixgbe_setup_tc,
8409 #endif
8410 #ifdef CONFIG_NET_POLL_CONTROLLER
8411 .ndo_poll_controller = ixgbe_netpoll,
8412 #endif
8413 #ifdef CONFIG_NET_RX_BUSY_POLL
8414 .ndo_busy_poll = ixgbe_low_latency_recv,
8415 #endif
8416 #ifdef IXGBE_FCOE
8417 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
8418 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
8419 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8420 .ndo_fcoe_enable = ixgbe_fcoe_enable,
8421 .ndo_fcoe_disable = ixgbe_fcoe_disable,
8422 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
8423 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
8424 #endif /* IXGBE_FCOE */
8425 .ndo_set_features = ixgbe_set_features,
8426 .ndo_fix_features = ixgbe_fix_features,
8427 .ndo_fdb_add = ixgbe_ndo_fdb_add,
8428 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
8429 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
8430 .ndo_dfwd_add_station = ixgbe_fwd_add,
8431 .ndo_dfwd_del_station = ixgbe_fwd_del,
8432 #ifdef CONFIG_IXGBE_VXLAN
8433 .ndo_add_vxlan_port = ixgbe_add_vxlan_port,
8434 .ndo_del_vxlan_port = ixgbe_del_vxlan_port,
8435 #endif /* CONFIG_IXGBE_VXLAN */
8436 .ndo_features_check = ixgbe_features_check,
8437 };
8438
8439 /**
8440 * ixgbe_enumerate_functions - Get the number of ports this device has
8441 * @adapter: adapter structure
8442 *
8443 * This function enumerates the phsyical functions co-located on a single slot,
8444 * in order to determine how many ports a device has. This is most useful in
8445 * determining the required GT/s of PCIe bandwidth necessary for optimal
8446 * performance.
8447 **/
8448 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
8449 {
8450 struct pci_dev *entry, *pdev = adapter->pdev;
8451 int physfns = 0;
8452
8453 /* Some cards can not use the generic count PCIe functions method,
8454 * because they are behind a parent switch, so we hardcode these with
8455 * the correct number of functions.
8456 */
8457 if (ixgbe_pcie_from_parent(&adapter->hw))
8458 physfns = 4;
8459
8460 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
8461 /* don't count virtual functions */
8462 if (entry->is_virtfn)
8463 continue;
8464
8465 /* When the devices on the bus don't all match our device ID,
8466 * we can't reliably determine the correct number of
8467 * functions. This can occur if a function has been direct
8468 * attached to a virtual machine using VT-d, for example. In
8469 * this case, simply return -1 to indicate this.
8470 */
8471 if ((entry->vendor != pdev->vendor) ||
8472 (entry->device != pdev->device))
8473 return -1;
8474
8475 physfns++;
8476 }
8477
8478 return physfns;
8479 }
8480
8481 /**
8482 * ixgbe_wol_supported - Check whether device supports WoL
8483 * @hw: hw specific details
8484 * @device_id: the device ID
8485 * @subdev_id: the subsystem device ID
8486 *
8487 * This function is used by probe and ethtool to determine
8488 * which devices have WoL support
8489 *
8490 **/
8491 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8492 u16 subdevice_id)
8493 {
8494 struct ixgbe_hw *hw = &adapter->hw;
8495 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8496 int is_wol_supported = 0;
8497
8498 switch (device_id) {
8499 case IXGBE_DEV_ID_82599_SFP:
8500 /* Only these subdevices could supports WOL */
8501 switch (subdevice_id) {
8502 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8503 case IXGBE_SUBDEV_ID_82599_560FLR:
8504 /* only support first port */
8505 if (hw->bus.func != 0)
8506 break;
8507 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8508 case IXGBE_SUBDEV_ID_82599_SFP:
8509 case IXGBE_SUBDEV_ID_82599_RNDC:
8510 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
8511 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8512 is_wol_supported = 1;
8513 break;
8514 }
8515 break;
8516 case IXGBE_DEV_ID_82599EN_SFP:
8517 /* Only this subdevice supports WOL */
8518 switch (subdevice_id) {
8519 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8520 is_wol_supported = 1;
8521 break;
8522 }
8523 break;
8524 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8525 /* All except this subdevice support WOL */
8526 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8527 is_wol_supported = 1;
8528 break;
8529 case IXGBE_DEV_ID_82599_KX4:
8530 is_wol_supported = 1;
8531 break;
8532 case IXGBE_DEV_ID_X540T:
8533 case IXGBE_DEV_ID_X540T1:
8534 case IXGBE_DEV_ID_X550T:
8535 case IXGBE_DEV_ID_X550EM_X_KX4:
8536 case IXGBE_DEV_ID_X550EM_X_KR:
8537 case IXGBE_DEV_ID_X550EM_X_10G_T:
8538 /* check eeprom to see if enabled wol */
8539 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8540 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8541 (hw->bus.func == 0))) {
8542 is_wol_supported = 1;
8543 }
8544 break;
8545 }
8546
8547 return is_wol_supported;
8548 }
8549
8550 /**
8551 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM
8552 * @adapter: Pointer to adapter struct
8553 */
8554 static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter)
8555 {
8556 #ifdef CONFIG_OF
8557 struct device_node *dp = pci_device_to_OF_node(adapter->pdev);
8558 struct ixgbe_hw *hw = &adapter->hw;
8559 const unsigned char *addr;
8560
8561 addr = of_get_mac_address(dp);
8562 if (addr) {
8563 ether_addr_copy(hw->mac.perm_addr, addr);
8564 return;
8565 }
8566 #endif /* CONFIG_OF */
8567
8568 #ifdef CONFIG_SPARC
8569 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr);
8570 #endif /* CONFIG_SPARC */
8571 }
8572
8573 /**
8574 * ixgbe_probe - Device Initialization Routine
8575 * @pdev: PCI device information struct
8576 * @ent: entry in ixgbe_pci_tbl
8577 *
8578 * Returns 0 on success, negative on failure
8579 *
8580 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
8581 * The OS initialization, configuring of the adapter private structure,
8582 * and a hardware reset occur.
8583 **/
8584 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8585 {
8586 struct net_device *netdev;
8587 struct ixgbe_adapter *adapter = NULL;
8588 struct ixgbe_hw *hw;
8589 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
8590 int i, err, pci_using_dac, expected_gts;
8591 unsigned int indices = MAX_TX_QUEUES;
8592 u8 part_str[IXGBE_PBANUM_LENGTH];
8593 bool disable_dev = false;
8594 #ifdef IXGBE_FCOE
8595 u16 device_caps;
8596 #endif
8597 u32 eec;
8598
8599 /* Catch broken hardware that put the wrong VF device ID in
8600 * the PCIe SR-IOV capability.
8601 */
8602 if (pdev->is_virtfn) {
8603 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
8604 pci_name(pdev), pdev->vendor, pdev->device);
8605 return -EINVAL;
8606 }
8607
8608 err = pci_enable_device_mem(pdev);
8609 if (err)
8610 return err;
8611
8612 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
8613 pci_using_dac = 1;
8614 } else {
8615 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8616 if (err) {
8617 dev_err(&pdev->dev,
8618 "No usable DMA configuration, aborting\n");
8619 goto err_dma;
8620 }
8621 pci_using_dac = 0;
8622 }
8623
8624 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8625 IORESOURCE_MEM), ixgbe_driver_name);
8626 if (err) {
8627 dev_err(&pdev->dev,
8628 "pci_request_selected_regions failed 0x%x\n", err);
8629 goto err_pci_reg;
8630 }
8631
8632 pci_enable_pcie_error_reporting(pdev);
8633
8634 pci_set_master(pdev);
8635 pci_save_state(pdev);
8636
8637 if (ii->mac == ixgbe_mac_82598EB) {
8638 #ifdef CONFIG_IXGBE_DCB
8639 /* 8 TC w/ 4 queues per TC */
8640 indices = 4 * MAX_TRAFFIC_CLASS;
8641 #else
8642 indices = IXGBE_MAX_RSS_INDICES;
8643 #endif
8644 }
8645
8646 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
8647 if (!netdev) {
8648 err = -ENOMEM;
8649 goto err_alloc_etherdev;
8650 }
8651
8652 SET_NETDEV_DEV(netdev, &pdev->dev);
8653
8654 adapter = netdev_priv(netdev);
8655
8656 adapter->netdev = netdev;
8657 adapter->pdev = pdev;
8658 hw = &adapter->hw;
8659 hw->back = adapter;
8660 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
8661
8662 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8663 pci_resource_len(pdev, 0));
8664 adapter->io_addr = hw->hw_addr;
8665 if (!hw->hw_addr) {
8666 err = -EIO;
8667 goto err_ioremap;
8668 }
8669
8670 netdev->netdev_ops = &ixgbe_netdev_ops;
8671 ixgbe_set_ethtool_ops(netdev);
8672 netdev->watchdog_timeo = 5 * HZ;
8673 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
8674
8675 /* Setup hw api */
8676 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
8677 hw->mac.type = ii->mac;
8678 hw->mvals = ii->mvals;
8679
8680 /* EEPROM */
8681 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
8682 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
8683 if (ixgbe_removed(hw->hw_addr)) {
8684 err = -EIO;
8685 goto err_ioremap;
8686 }
8687 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8688 if (!(eec & (1 << 8)))
8689 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8690
8691 /* PHY */
8692 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
8693 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
8694 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8695 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8696 hw->phy.mdio.mmds = 0;
8697 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8698 hw->phy.mdio.dev = netdev;
8699 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8700 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
8701
8702 ii->get_invariants(hw);
8703
8704 /* setup the private structure */
8705 err = ixgbe_sw_init(adapter);
8706 if (err)
8707 goto err_sw_init;
8708
8709 /* Make it possible the adapter to be woken up via WOL */
8710 switch (adapter->hw.mac.type) {
8711 case ixgbe_mac_82599EB:
8712 case ixgbe_mac_X540:
8713 case ixgbe_mac_X550:
8714 case ixgbe_mac_X550EM_x:
8715 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
8716 break;
8717 default:
8718 break;
8719 }
8720
8721 /*
8722 * If there is a fan on this device and it has failed log the
8723 * failure.
8724 */
8725 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8726 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8727 if (esdp & IXGBE_ESDP_SDP1)
8728 e_crit(probe, "Fan has stopped, replace the adapter\n");
8729 }
8730
8731 if (allow_unsupported_sfp)
8732 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8733
8734 /* reset_hw fills in the perm_addr as well */
8735 hw->phy.reset_if_overtemp = true;
8736 err = hw->mac.ops.reset_hw(hw);
8737 hw->phy.reset_if_overtemp = false;
8738 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
8739 err = 0;
8740 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
8741 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8742 e_dev_err("Reload the driver after installing a supported module.\n");
8743 goto err_sw_init;
8744 } else if (err) {
8745 e_dev_err("HW Init failed: %d\n", err);
8746 goto err_sw_init;
8747 }
8748
8749 #ifdef CONFIG_PCI_IOV
8750 /* SR-IOV not supported on the 82598 */
8751 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8752 goto skip_sriov;
8753 /* Mailbox */
8754 ixgbe_init_mbx_params_pf(hw);
8755 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
8756 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
8757 ixgbe_enable_sriov(adapter);
8758 skip_sriov:
8759
8760 #endif
8761 netdev->features = NETIF_F_SG |
8762 NETIF_F_IP_CSUM |
8763 NETIF_F_IPV6_CSUM |
8764 NETIF_F_HW_VLAN_CTAG_TX |
8765 NETIF_F_HW_VLAN_CTAG_RX |
8766 NETIF_F_TSO |
8767 NETIF_F_TSO6 |
8768 NETIF_F_RXHASH |
8769 NETIF_F_RXCSUM;
8770
8771 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
8772
8773 switch (adapter->hw.mac.type) {
8774 case ixgbe_mac_82599EB:
8775 case ixgbe_mac_X540:
8776 case ixgbe_mac_X550:
8777 case ixgbe_mac_X550EM_x:
8778 netdev->features |= NETIF_F_SCTP_CSUM;
8779 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8780 NETIF_F_NTUPLE;
8781 break;
8782 default:
8783 break;
8784 }
8785
8786 netdev->hw_features |= NETIF_F_RXALL;
8787 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
8788
8789 netdev->vlan_features |= NETIF_F_TSO;
8790 netdev->vlan_features |= NETIF_F_TSO6;
8791 netdev->vlan_features |= NETIF_F_IP_CSUM;
8792 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
8793 netdev->vlan_features |= NETIF_F_SG;
8794
8795 netdev->hw_enc_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
8796 NETIF_F_IPV6_CSUM;
8797
8798 netdev->priv_flags |= IFF_UNICAST_FLT;
8799 netdev->priv_flags |= IFF_SUPP_NOFCS;
8800
8801 #ifdef CONFIG_IXGBE_VXLAN
8802 switch (adapter->hw.mac.type) {
8803 case ixgbe_mac_X550:
8804 case ixgbe_mac_X550EM_x:
8805 netdev->hw_enc_features |= NETIF_F_RXCSUM |
8806 NETIF_F_IP_CSUM |
8807 NETIF_F_IPV6_CSUM;
8808 break;
8809 default:
8810 break;
8811 }
8812 #endif /* CONFIG_IXGBE_VXLAN */
8813
8814 #ifdef CONFIG_IXGBE_DCB
8815 netdev->dcbnl_ops = &dcbnl_ops;
8816 #endif
8817
8818 #ifdef IXGBE_FCOE
8819 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
8820 unsigned int fcoe_l;
8821
8822 if (hw->mac.ops.get_device_caps) {
8823 hw->mac.ops.get_device_caps(hw, &device_caps);
8824 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8825 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
8826 }
8827
8828
8829 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8830 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
8831
8832 netdev->features |= NETIF_F_FSO |
8833 NETIF_F_FCOE_CRC;
8834
8835 netdev->vlan_features |= NETIF_F_FSO |
8836 NETIF_F_FCOE_CRC |
8837 NETIF_F_FCOE_MTU;
8838 }
8839 #endif /* IXGBE_FCOE */
8840 if (pci_using_dac) {
8841 netdev->features |= NETIF_F_HIGHDMA;
8842 netdev->vlan_features |= NETIF_F_HIGHDMA;
8843 }
8844
8845 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8846 netdev->hw_features |= NETIF_F_LRO;
8847 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
8848 netdev->features |= NETIF_F_LRO;
8849
8850 /* make sure the EEPROM is good */
8851 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
8852 e_dev_err("The EEPROM Checksum Is Not Valid\n");
8853 err = -EIO;
8854 goto err_sw_init;
8855 }
8856
8857 ixgbe_get_platform_mac_addr(adapter);
8858
8859 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
8860
8861 if (!is_valid_ether_addr(netdev->dev_addr)) {
8862 e_dev_err("invalid MAC address\n");
8863 err = -EIO;
8864 goto err_sw_init;
8865 }
8866
8867 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr);
8868
8869 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
8870 (unsigned long) adapter);
8871
8872 if (ixgbe_removed(hw->hw_addr)) {
8873 err = -EIO;
8874 goto err_sw_init;
8875 }
8876 INIT_WORK(&adapter->service_task, ixgbe_service_task);
8877 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
8878 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
8879
8880 err = ixgbe_init_interrupt_scheme(adapter);
8881 if (err)
8882 goto err_sw_init;
8883
8884 /* WOL not supported for all devices */
8885 adapter->wol = 0;
8886 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
8887 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
8888 pdev->subsystem_device);
8889 if (hw->wol_enabled)
8890 adapter->wol = IXGBE_WUFC_MAG;
8891
8892 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8893
8894 /* save off EEPROM version number */
8895 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8896 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8897
8898 /* pick up the PCI bus settings for reporting later */
8899 if (ixgbe_pcie_from_parent(hw))
8900 ixgbe_get_parent_bus_info(adapter);
8901 else
8902 hw->mac.ops.get_bus_info(hw);
8903
8904 /* calculate the expected PCIe bandwidth required for optimal
8905 * performance. Note that some older parts will never have enough
8906 * bandwidth due to being older generation PCIe parts. We clamp these
8907 * parts to ensure no warning is displayed if it can't be fixed.
8908 */
8909 switch (hw->mac.type) {
8910 case ixgbe_mac_82598EB:
8911 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8912 break;
8913 default:
8914 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8915 break;
8916 }
8917
8918 /* don't check link if we failed to enumerate functions */
8919 if (expected_gts > 0)
8920 ixgbe_check_minimum_link(adapter, expected_gts);
8921
8922 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
8923 if (err)
8924 strlcpy(part_str, "Unknown", sizeof(part_str));
8925 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8926 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8927 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
8928 part_str);
8929 else
8930 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8931 hw->mac.type, hw->phy.type, part_str);
8932
8933 e_dev_info("%pM\n", netdev->dev_addr);
8934
8935 /* reset the hardware with the new settings */
8936 err = hw->mac.ops.start_hw(hw);
8937 if (err == IXGBE_ERR_EEPROM_VERSION) {
8938 /* We are running on a pre-production device, log a warning */
8939 e_dev_warn("This device is a pre-production adapter/LOM. "
8940 "Please be aware there may be issues associated "
8941 "with your hardware. If you are experiencing "
8942 "problems please contact your Intel or hardware "
8943 "representative who provided you with this "
8944 "hardware.\n");
8945 }
8946 strcpy(netdev->name, "eth%d");
8947 err = register_netdev(netdev);
8948 if (err)
8949 goto err_register;
8950
8951 pci_set_drvdata(pdev, adapter);
8952
8953 /* power down the optics for 82599 SFP+ fiber */
8954 if (hw->mac.ops.disable_tx_laser)
8955 hw->mac.ops.disable_tx_laser(hw);
8956
8957 /* carrier off reporting is important to ethtool even BEFORE open */
8958 netif_carrier_off(netdev);
8959
8960 #ifdef CONFIG_IXGBE_DCA
8961 if (dca_add_requester(&pdev->dev) == 0) {
8962 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
8963 ixgbe_setup_dca(adapter);
8964 }
8965 #endif
8966 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
8967 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
8968 for (i = 0; i < adapter->num_vfs; i++)
8969 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8970 }
8971
8972 /* firmware requires driver version to be 0xFFFFFFFF
8973 * since os does not support feature
8974 */
8975 if (hw->mac.ops.set_fw_drv_ver)
8976 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8977 0xFF);
8978
8979 /* add san mac addr to netdev */
8980 ixgbe_add_sanmac_netdev(netdev);
8981
8982 e_dev_info("%s\n", ixgbe_default_device_descr);
8983
8984 #ifdef CONFIG_IXGBE_HWMON
8985 if (ixgbe_sysfs_init(adapter))
8986 e_err(probe, "failed to allocate sysfs resources\n");
8987 #endif /* CONFIG_IXGBE_HWMON */
8988
8989 ixgbe_dbg_adapter_init(adapter);
8990
8991 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
8992 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
8993 hw->mac.ops.setup_link(hw,
8994 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8995 true);
8996
8997 return 0;
8998
8999 err_register:
9000 ixgbe_release_hw_control(adapter);
9001 ixgbe_clear_interrupt_scheme(adapter);
9002 err_sw_init:
9003 ixgbe_disable_sriov(adapter);
9004 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9005 iounmap(adapter->io_addr);
9006 kfree(adapter->mac_table);
9007 err_ioremap:
9008 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9009 free_netdev(netdev);
9010 err_alloc_etherdev:
9011 pci_release_selected_regions(pdev,
9012 pci_select_bars(pdev, IORESOURCE_MEM));
9013 err_pci_reg:
9014 err_dma:
9015 if (!adapter || disable_dev)
9016 pci_disable_device(pdev);
9017 return err;
9018 }
9019
9020 /**
9021 * ixgbe_remove - Device Removal Routine
9022 * @pdev: PCI device information struct
9023 *
9024 * ixgbe_remove is called by the PCI subsystem to alert the driver
9025 * that it should release a PCI device. The could be caused by a
9026 * Hot-Plug event, or because the driver is going to be removed from
9027 * memory.
9028 **/
9029 static void ixgbe_remove(struct pci_dev *pdev)
9030 {
9031 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9032 struct net_device *netdev;
9033 bool disable_dev;
9034
9035 /* if !adapter then we already cleaned up in probe */
9036 if (!adapter)
9037 return;
9038
9039 netdev = adapter->netdev;
9040 ixgbe_dbg_adapter_exit(adapter);
9041
9042 set_bit(__IXGBE_REMOVING, &adapter->state);
9043 cancel_work_sync(&adapter->service_task);
9044
9045
9046 #ifdef CONFIG_IXGBE_DCA
9047 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
9048 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9049 dca_remove_requester(&pdev->dev);
9050 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
9051 IXGBE_DCA_CTRL_DCA_DISABLE);
9052 }
9053
9054 #endif
9055 #ifdef CONFIG_IXGBE_HWMON
9056 ixgbe_sysfs_exit(adapter);
9057 #endif /* CONFIG_IXGBE_HWMON */
9058
9059 /* remove the added san mac */
9060 ixgbe_del_sanmac_netdev(netdev);
9061
9062 #ifdef CONFIG_PCI_IOV
9063 ixgbe_disable_sriov(adapter);
9064 #endif
9065 if (netdev->reg_state == NETREG_REGISTERED)
9066 unregister_netdev(netdev);
9067
9068 ixgbe_clear_interrupt_scheme(adapter);
9069
9070 ixgbe_release_hw_control(adapter);
9071
9072 #ifdef CONFIG_DCB
9073 kfree(adapter->ixgbe_ieee_pfc);
9074 kfree(adapter->ixgbe_ieee_ets);
9075
9076 #endif
9077 iounmap(adapter->io_addr);
9078 pci_release_selected_regions(pdev, pci_select_bars(pdev,
9079 IORESOURCE_MEM));
9080
9081 e_dev_info("complete\n");
9082
9083 kfree(adapter->mac_table);
9084 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9085 free_netdev(netdev);
9086
9087 pci_disable_pcie_error_reporting(pdev);
9088
9089 if (disable_dev)
9090 pci_disable_device(pdev);
9091 }
9092
9093 /**
9094 * ixgbe_io_error_detected - called when PCI error is detected
9095 * @pdev: Pointer to PCI device
9096 * @state: The current pci connection state
9097 *
9098 * This function is called after a PCI bus error affecting
9099 * this device has been detected.
9100 */
9101 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
9102 pci_channel_state_t state)
9103 {
9104 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9105 struct net_device *netdev = adapter->netdev;
9106
9107 #ifdef CONFIG_PCI_IOV
9108 struct ixgbe_hw *hw = &adapter->hw;
9109 struct pci_dev *bdev, *vfdev;
9110 u32 dw0, dw1, dw2, dw3;
9111 int vf, pos;
9112 u16 req_id, pf_func;
9113
9114 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
9115 adapter->num_vfs == 0)
9116 goto skip_bad_vf_detection;
9117
9118 bdev = pdev->bus->self;
9119 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
9120 bdev = bdev->bus->self;
9121
9122 if (!bdev)
9123 goto skip_bad_vf_detection;
9124
9125 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
9126 if (!pos)
9127 goto skip_bad_vf_detection;
9128
9129 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
9130 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
9131 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
9132 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
9133 if (ixgbe_removed(hw->hw_addr))
9134 goto skip_bad_vf_detection;
9135
9136 req_id = dw1 >> 16;
9137 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
9138 if (!(req_id & 0x0080))
9139 goto skip_bad_vf_detection;
9140
9141 pf_func = req_id & 0x01;
9142 if ((pf_func & 1) == (pdev->devfn & 1)) {
9143 unsigned int device_id;
9144
9145 vf = (req_id & 0x7F) >> 1;
9146 e_dev_err("VF %d has caused a PCIe error\n", vf);
9147 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
9148 "%8.8x\tdw3: %8.8x\n",
9149 dw0, dw1, dw2, dw3);
9150 switch (adapter->hw.mac.type) {
9151 case ixgbe_mac_82599EB:
9152 device_id = IXGBE_82599_VF_DEVICE_ID;
9153 break;
9154 case ixgbe_mac_X540:
9155 device_id = IXGBE_X540_VF_DEVICE_ID;
9156 break;
9157 case ixgbe_mac_X550:
9158 device_id = IXGBE_DEV_ID_X550_VF;
9159 break;
9160 case ixgbe_mac_X550EM_x:
9161 device_id = IXGBE_DEV_ID_X550EM_X_VF;
9162 break;
9163 default:
9164 device_id = 0;
9165 break;
9166 }
9167
9168 /* Find the pci device of the offending VF */
9169 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
9170 while (vfdev) {
9171 if (vfdev->devfn == (req_id & 0xFF))
9172 break;
9173 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
9174 device_id, vfdev);
9175 }
9176 /*
9177 * There's a slim chance the VF could have been hot plugged,
9178 * so if it is no longer present we don't need to issue the
9179 * VFLR. Just clean up the AER in that case.
9180 */
9181 if (vfdev) {
9182 ixgbe_issue_vf_flr(adapter, vfdev);
9183 /* Free device reference count */
9184 pci_dev_put(vfdev);
9185 }
9186
9187 pci_cleanup_aer_uncorrect_error_status(pdev);
9188 }
9189
9190 /*
9191 * Even though the error may have occurred on the other port
9192 * we still need to increment the vf error reference count for
9193 * both ports because the I/O resume function will be called
9194 * for both of them.
9195 */
9196 adapter->vferr_refcount++;
9197
9198 return PCI_ERS_RESULT_RECOVERED;
9199
9200 skip_bad_vf_detection:
9201 #endif /* CONFIG_PCI_IOV */
9202 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
9203 return PCI_ERS_RESULT_DISCONNECT;
9204
9205 rtnl_lock();
9206 netif_device_detach(netdev);
9207
9208 if (state == pci_channel_io_perm_failure) {
9209 rtnl_unlock();
9210 return PCI_ERS_RESULT_DISCONNECT;
9211 }
9212
9213 if (netif_running(netdev))
9214 ixgbe_down(adapter);
9215
9216 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
9217 pci_disable_device(pdev);
9218 rtnl_unlock();
9219
9220 /* Request a slot reset. */
9221 return PCI_ERS_RESULT_NEED_RESET;
9222 }
9223
9224 /**
9225 * ixgbe_io_slot_reset - called after the pci bus has been reset.
9226 * @pdev: Pointer to PCI device
9227 *
9228 * Restart the card from scratch, as if from a cold-boot.
9229 */
9230 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
9231 {
9232 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9233 pci_ers_result_t result;
9234 int err;
9235
9236 if (pci_enable_device_mem(pdev)) {
9237 e_err(probe, "Cannot re-enable PCI device after reset.\n");
9238 result = PCI_ERS_RESULT_DISCONNECT;
9239 } else {
9240 smp_mb__before_atomic();
9241 clear_bit(__IXGBE_DISABLED, &adapter->state);
9242 adapter->hw.hw_addr = adapter->io_addr;
9243 pci_set_master(pdev);
9244 pci_restore_state(pdev);
9245 pci_save_state(pdev);
9246
9247 pci_wake_from_d3(pdev, false);
9248
9249 ixgbe_reset(adapter);
9250 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
9251 result = PCI_ERS_RESULT_RECOVERED;
9252 }
9253
9254 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9255 if (err) {
9256 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
9257 "failed 0x%0x\n", err);
9258 /* non-fatal, continue */
9259 }
9260
9261 return result;
9262 }
9263
9264 /**
9265 * ixgbe_io_resume - called when traffic can start flowing again.
9266 * @pdev: Pointer to PCI device
9267 *
9268 * This callback is called when the error recovery driver tells us that
9269 * its OK to resume normal operation.
9270 */
9271 static void ixgbe_io_resume(struct pci_dev *pdev)
9272 {
9273 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9274 struct net_device *netdev = adapter->netdev;
9275
9276 #ifdef CONFIG_PCI_IOV
9277 if (adapter->vferr_refcount) {
9278 e_info(drv, "Resuming after VF err\n");
9279 adapter->vferr_refcount--;
9280 return;
9281 }
9282
9283 #endif
9284 if (netif_running(netdev))
9285 ixgbe_up(adapter);
9286
9287 netif_device_attach(netdev);
9288 }
9289
9290 static const struct pci_error_handlers ixgbe_err_handler = {
9291 .error_detected = ixgbe_io_error_detected,
9292 .slot_reset = ixgbe_io_slot_reset,
9293 .resume = ixgbe_io_resume,
9294 };
9295
9296 static struct pci_driver ixgbe_driver = {
9297 .name = ixgbe_driver_name,
9298 .id_table = ixgbe_pci_tbl,
9299 .probe = ixgbe_probe,
9300 .remove = ixgbe_remove,
9301 #ifdef CONFIG_PM
9302 .suspend = ixgbe_suspend,
9303 .resume = ixgbe_resume,
9304 #endif
9305 .shutdown = ixgbe_shutdown,
9306 .sriov_configure = ixgbe_pci_sriov_configure,
9307 .err_handler = &ixgbe_err_handler
9308 };
9309
9310 /**
9311 * ixgbe_init_module - Driver Registration Routine
9312 *
9313 * ixgbe_init_module is the first routine called when the driver is
9314 * loaded. All it does is register with the PCI subsystem.
9315 **/
9316 static int __init ixgbe_init_module(void)
9317 {
9318 int ret;
9319 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
9320 pr_info("%s\n", ixgbe_copyright);
9321
9322 ixgbe_dbg_init();
9323
9324 ret = pci_register_driver(&ixgbe_driver);
9325 if (ret) {
9326 ixgbe_dbg_exit();
9327 return ret;
9328 }
9329
9330 #ifdef CONFIG_IXGBE_DCA
9331 dca_register_notify(&dca_notifier);
9332 #endif
9333
9334 return 0;
9335 }
9336
9337 module_init(ixgbe_init_module);
9338
9339 /**
9340 * ixgbe_exit_module - Driver Exit Cleanup Routine
9341 *
9342 * ixgbe_exit_module is called just before the driver is removed
9343 * from memory.
9344 **/
9345 static void __exit ixgbe_exit_module(void)
9346 {
9347 #ifdef CONFIG_IXGBE_DCA
9348 dca_unregister_notify(&dca_notifier);
9349 #endif
9350 pci_unregister_driver(&ixgbe_driver);
9351
9352 ixgbe_dbg_exit();
9353 }
9354
9355 #ifdef CONFIG_IXGBE_DCA
9356 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
9357 void *p)
9358 {
9359 int ret_val;
9360
9361 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
9362 __ixgbe_notify_dca);
9363
9364 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
9365 }
9366
9367 #endif /* CONFIG_IXGBE_DCA */
9368
9369 module_exit(ixgbe_exit_module);
9370
9371 /* ixgbe_main.c */
Linux kernel - Deliverables
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