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[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2015 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/types.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/vmalloc.h>
34 #include <linux/string.h>
35 #include <linux/in.h>
36 #include <linux/interrupt.h>
37 #include <linux/ip.h>
38 #include <linux/tcp.h>
39 #include <linux/sctp.h>
40 #include <linux/pkt_sched.h>
41 #include <linux/ipv6.h>
42 #include <linux/slab.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/etherdevice.h>
46 #include <linux/ethtool.h>
47 #include <linux/if.h>
48 #include <linux/if_vlan.h>
49 #include <linux/if_macvlan.h>
50 #include <linux/if_bridge.h>
51 #include <linux/prefetch.h>
52 #include <scsi/fc/fc_fcoe.h>
53 #include <net/vxlan.h>
54
55 #ifdef CONFIG_OF
56 #include <linux/of_net.h>
57 #endif
58
59 #ifdef CONFIG_SPARC
60 #include <asm/idprom.h>
61 #include <asm/prom.h>
62 #endif
63
64 #include "ixgbe.h"
65 #include "ixgbe_common.h"
66 #include "ixgbe_dcb_82599.h"
67 #include "ixgbe_sriov.h"
68
69 char ixgbe_driver_name[] = "ixgbe";
70 static const char ixgbe_driver_string[] =
71 "Intel(R) 10 Gigabit PCI Express Network Driver";
72 #ifdef IXGBE_FCOE
73 char ixgbe_default_device_descr[] =
74 "Intel(R) 10 Gigabit Network Connection";
75 #else
76 static char ixgbe_default_device_descr[] =
77 "Intel(R) 10 Gigabit Network Connection";
78 #endif
79 #define DRV_VERSION "4.2.1-k"
80 const char ixgbe_driver_version[] = DRV_VERSION;
81 static const char ixgbe_copyright[] =
82 "Copyright (c) 1999-2015 Intel Corporation.";
83
84 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
85
86 static const struct ixgbe_info *ixgbe_info_tbl[] = {
87 [board_82598] = &ixgbe_82598_info,
88 [board_82599] = &ixgbe_82599_info,
89 [board_X540] = &ixgbe_X540_info,
90 [board_X550] = &ixgbe_X550_info,
91 [board_X550EM_x] = &ixgbe_X550EM_x_info,
92 };
93
94 /* ixgbe_pci_tbl - PCI Device ID Table
95 *
96 * Wildcard entries (PCI_ANY_ID) should come last
97 * Last entry must be all 0s
98 *
99 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
100 * Class, Class Mask, private data (not used) }
101 */
102 static const struct pci_device_id ixgbe_pci_tbl[] = {
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
138 /* required last entry */
139 {0, }
140 };
141 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
142
143 #ifdef CONFIG_IXGBE_DCA
144 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
145 void *p);
146 static struct notifier_block dca_notifier = {
147 .notifier_call = ixgbe_notify_dca,
148 .next = NULL,
149 .priority = 0
150 };
151 #endif
152
153 #ifdef CONFIG_PCI_IOV
154 static unsigned int max_vfs;
155 module_param(max_vfs, uint, 0);
156 MODULE_PARM_DESC(max_vfs,
157 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
158 #endif /* CONFIG_PCI_IOV */
159
160 static unsigned int allow_unsupported_sfp;
161 module_param(allow_unsupported_sfp, uint, 0);
162 MODULE_PARM_DESC(allow_unsupported_sfp,
163 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
164
165 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
166 static int debug = -1;
167 module_param(debug, int, 0);
168 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
169
170 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
171 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
172 MODULE_LICENSE("GPL");
173 MODULE_VERSION(DRV_VERSION);
174
175 static struct workqueue_struct *ixgbe_wq;
176
177 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
178
179 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
180 u32 reg, u16 *value)
181 {
182 struct pci_dev *parent_dev;
183 struct pci_bus *parent_bus;
184
185 parent_bus = adapter->pdev->bus->parent;
186 if (!parent_bus)
187 return -1;
188
189 parent_dev = parent_bus->self;
190 if (!parent_dev)
191 return -1;
192
193 if (!pci_is_pcie(parent_dev))
194 return -1;
195
196 pcie_capability_read_word(parent_dev, reg, value);
197 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
198 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
199 return -1;
200 return 0;
201 }
202
203 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
204 {
205 struct ixgbe_hw *hw = &adapter->hw;
206 u16 link_status = 0;
207 int err;
208
209 hw->bus.type = ixgbe_bus_type_pci_express;
210
211 /* Get the negotiated link width and speed from PCI config space of the
212 * parent, as this device is behind a switch
213 */
214 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
215
216 /* assume caller will handle error case */
217 if (err)
218 return err;
219
220 hw->bus.width = ixgbe_convert_bus_width(link_status);
221 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
222
223 return 0;
224 }
225
226 /**
227 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
228 * @hw: hw specific details
229 *
230 * This function is used by probe to determine whether a device's PCI-Express
231 * bandwidth details should be gathered from the parent bus instead of from the
232 * device. Used to ensure that various locations all have the correct device ID
233 * checks.
234 */
235 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
236 {
237 switch (hw->device_id) {
238 case IXGBE_DEV_ID_82599_SFP_SF_QP:
239 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
240 return true;
241 default:
242 return false;
243 }
244 }
245
246 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
247 int expected_gts)
248 {
249 struct ixgbe_hw *hw = &adapter->hw;
250 int max_gts = 0;
251 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
252 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
253 struct pci_dev *pdev;
254
255 /* Some devices are not connected over PCIe and thus do not negotiate
256 * speed. These devices do not have valid bus info, and thus any report
257 * we generate may not be correct.
258 */
259 if (hw->bus.type == ixgbe_bus_type_internal)
260 return;
261
262 /* determine whether to use the parent device */
263 if (ixgbe_pcie_from_parent(&adapter->hw))
264 pdev = adapter->pdev->bus->parent->self;
265 else
266 pdev = adapter->pdev;
267
268 if (pcie_get_minimum_link(pdev, &speed, &width) ||
269 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
270 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
271 return;
272 }
273
274 switch (speed) {
275 case PCIE_SPEED_2_5GT:
276 /* 8b/10b encoding reduces max throughput by 20% */
277 max_gts = 2 * width;
278 break;
279 case PCIE_SPEED_5_0GT:
280 /* 8b/10b encoding reduces max throughput by 20% */
281 max_gts = 4 * width;
282 break;
283 case PCIE_SPEED_8_0GT:
284 /* 128b/130b encoding reduces throughput by less than 2% */
285 max_gts = 8 * width;
286 break;
287 default:
288 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
289 return;
290 }
291
292 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
293 max_gts);
294 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
295 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
296 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
297 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
298 "Unknown"),
299 width,
300 (speed == PCIE_SPEED_2_5GT ? "20%" :
301 speed == PCIE_SPEED_5_0GT ? "20%" :
302 speed == PCIE_SPEED_8_0GT ? "<2%" :
303 "Unknown"));
304
305 if (max_gts < expected_gts) {
306 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
307 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
308 expected_gts);
309 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
310 }
311 }
312
313 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
314 {
315 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
316 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
317 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
318 queue_work(ixgbe_wq, &adapter->service_task);
319 }
320
321 static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
322 {
323 struct ixgbe_adapter *adapter = hw->back;
324
325 if (!hw->hw_addr)
326 return;
327 hw->hw_addr = NULL;
328 e_dev_err("Adapter removed\n");
329 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
330 ixgbe_service_event_schedule(adapter);
331 }
332
333 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
334 {
335 u32 value;
336
337 /* The following check not only optimizes a bit by not
338 * performing a read on the status register when the
339 * register just read was a status register read that
340 * returned IXGBE_FAILED_READ_REG. It also blocks any
341 * potential recursion.
342 */
343 if (reg == IXGBE_STATUS) {
344 ixgbe_remove_adapter(hw);
345 return;
346 }
347 value = ixgbe_read_reg(hw, IXGBE_STATUS);
348 if (value == IXGBE_FAILED_READ_REG)
349 ixgbe_remove_adapter(hw);
350 }
351
352 /**
353 * ixgbe_read_reg - Read from device register
354 * @hw: hw specific details
355 * @reg: offset of register to read
356 *
357 * Returns : value read or IXGBE_FAILED_READ_REG if removed
358 *
359 * This function is used to read device registers. It checks for device
360 * removal by confirming any read that returns all ones by checking the
361 * status register value for all ones. This function avoids reading from
362 * the hardware if a removal was previously detected in which case it
363 * returns IXGBE_FAILED_READ_REG (all ones).
364 */
365 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
366 {
367 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
368 u32 value;
369
370 if (ixgbe_removed(reg_addr))
371 return IXGBE_FAILED_READ_REG;
372 value = readl(reg_addr + reg);
373 if (unlikely(value == IXGBE_FAILED_READ_REG))
374 ixgbe_check_remove(hw, reg);
375 return value;
376 }
377
378 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
379 {
380 u16 value;
381
382 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
383 if (value == IXGBE_FAILED_READ_CFG_WORD) {
384 ixgbe_remove_adapter(hw);
385 return true;
386 }
387 return false;
388 }
389
390 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
391 {
392 struct ixgbe_adapter *adapter = hw->back;
393 u16 value;
394
395 if (ixgbe_removed(hw->hw_addr))
396 return IXGBE_FAILED_READ_CFG_WORD;
397 pci_read_config_word(adapter->pdev, reg, &value);
398 if (value == IXGBE_FAILED_READ_CFG_WORD &&
399 ixgbe_check_cfg_remove(hw, adapter->pdev))
400 return IXGBE_FAILED_READ_CFG_WORD;
401 return value;
402 }
403
404 #ifdef CONFIG_PCI_IOV
405 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
406 {
407 struct ixgbe_adapter *adapter = hw->back;
408 u32 value;
409
410 if (ixgbe_removed(hw->hw_addr))
411 return IXGBE_FAILED_READ_CFG_DWORD;
412 pci_read_config_dword(adapter->pdev, reg, &value);
413 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
414 ixgbe_check_cfg_remove(hw, adapter->pdev))
415 return IXGBE_FAILED_READ_CFG_DWORD;
416 return value;
417 }
418 #endif /* CONFIG_PCI_IOV */
419
420 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
421 {
422 struct ixgbe_adapter *adapter = hw->back;
423
424 if (ixgbe_removed(hw->hw_addr))
425 return;
426 pci_write_config_word(adapter->pdev, reg, value);
427 }
428
429 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
430 {
431 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
432
433 /* flush memory to make sure state is correct before next watchdog */
434 smp_mb__before_atomic();
435 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
436 }
437
438 struct ixgbe_reg_info {
439 u32 ofs;
440 char *name;
441 };
442
443 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
444
445 /* General Registers */
446 {IXGBE_CTRL, "CTRL"},
447 {IXGBE_STATUS, "STATUS"},
448 {IXGBE_CTRL_EXT, "CTRL_EXT"},
449
450 /* Interrupt Registers */
451 {IXGBE_EICR, "EICR"},
452
453 /* RX Registers */
454 {IXGBE_SRRCTL(0), "SRRCTL"},
455 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
456 {IXGBE_RDLEN(0), "RDLEN"},
457 {IXGBE_RDH(0), "RDH"},
458 {IXGBE_RDT(0), "RDT"},
459 {IXGBE_RXDCTL(0), "RXDCTL"},
460 {IXGBE_RDBAL(0), "RDBAL"},
461 {IXGBE_RDBAH(0), "RDBAH"},
462
463 /* TX Registers */
464 {IXGBE_TDBAL(0), "TDBAL"},
465 {IXGBE_TDBAH(0), "TDBAH"},
466 {IXGBE_TDLEN(0), "TDLEN"},
467 {IXGBE_TDH(0), "TDH"},
468 {IXGBE_TDT(0), "TDT"},
469 {IXGBE_TXDCTL(0), "TXDCTL"},
470
471 /* List Terminator */
472 { .name = NULL }
473 };
474
475
476 /*
477 * ixgbe_regdump - register printout routine
478 */
479 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
480 {
481 int i = 0, j = 0;
482 char rname[16];
483 u32 regs[64];
484
485 switch (reginfo->ofs) {
486 case IXGBE_SRRCTL(0):
487 for (i = 0; i < 64; i++)
488 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
489 break;
490 case IXGBE_DCA_RXCTRL(0):
491 for (i = 0; i < 64; i++)
492 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
493 break;
494 case IXGBE_RDLEN(0):
495 for (i = 0; i < 64; i++)
496 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
497 break;
498 case IXGBE_RDH(0):
499 for (i = 0; i < 64; i++)
500 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
501 break;
502 case IXGBE_RDT(0):
503 for (i = 0; i < 64; i++)
504 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
505 break;
506 case IXGBE_RXDCTL(0):
507 for (i = 0; i < 64; i++)
508 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
509 break;
510 case IXGBE_RDBAL(0):
511 for (i = 0; i < 64; i++)
512 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
513 break;
514 case IXGBE_RDBAH(0):
515 for (i = 0; i < 64; i++)
516 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
517 break;
518 case IXGBE_TDBAL(0):
519 for (i = 0; i < 64; i++)
520 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
521 break;
522 case IXGBE_TDBAH(0):
523 for (i = 0; i < 64; i++)
524 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
525 break;
526 case IXGBE_TDLEN(0):
527 for (i = 0; i < 64; i++)
528 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
529 break;
530 case IXGBE_TDH(0):
531 for (i = 0; i < 64; i++)
532 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
533 break;
534 case IXGBE_TDT(0):
535 for (i = 0; i < 64; i++)
536 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
537 break;
538 case IXGBE_TXDCTL(0):
539 for (i = 0; i < 64; i++)
540 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
541 break;
542 default:
543 pr_info("%-15s %08x\n", reginfo->name,
544 IXGBE_READ_REG(hw, reginfo->ofs));
545 return;
546 }
547
548 for (i = 0; i < 8; i++) {
549 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
550 pr_err("%-15s", rname);
551 for (j = 0; j < 8; j++)
552 pr_cont(" %08x", regs[i*8+j]);
553 pr_cont("\n");
554 }
555
556 }
557
558 /*
559 * ixgbe_dump - Print registers, tx-rings and rx-rings
560 */
561 static void ixgbe_dump(struct ixgbe_adapter *adapter)
562 {
563 struct net_device *netdev = adapter->netdev;
564 struct ixgbe_hw *hw = &adapter->hw;
565 struct ixgbe_reg_info *reginfo;
566 int n = 0;
567 struct ixgbe_ring *tx_ring;
568 struct ixgbe_tx_buffer *tx_buffer;
569 union ixgbe_adv_tx_desc *tx_desc;
570 struct my_u0 { u64 a; u64 b; } *u0;
571 struct ixgbe_ring *rx_ring;
572 union ixgbe_adv_rx_desc *rx_desc;
573 struct ixgbe_rx_buffer *rx_buffer_info;
574 u32 staterr;
575 int i = 0;
576
577 if (!netif_msg_hw(adapter))
578 return;
579
580 /* Print netdevice Info */
581 if (netdev) {
582 dev_info(&adapter->pdev->dev, "Net device Info\n");
583 pr_info("Device Name state "
584 "trans_start last_rx\n");
585 pr_info("%-15s %016lX %016lX %016lX\n",
586 netdev->name,
587 netdev->state,
588 netdev->trans_start,
589 netdev->last_rx);
590 }
591
592 /* Print Registers */
593 dev_info(&adapter->pdev->dev, "Register Dump\n");
594 pr_info(" Register Name Value\n");
595 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
596 reginfo->name; reginfo++) {
597 ixgbe_regdump(hw, reginfo);
598 }
599
600 /* Print TX Ring Summary */
601 if (!netdev || !netif_running(netdev))
602 return;
603
604 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
605 pr_info(" %s %s %s %s\n",
606 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
607 "leng", "ntw", "timestamp");
608 for (n = 0; n < adapter->num_tx_queues; n++) {
609 tx_ring = adapter->tx_ring[n];
610 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
611 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
612 n, tx_ring->next_to_use, tx_ring->next_to_clean,
613 (u64)dma_unmap_addr(tx_buffer, dma),
614 dma_unmap_len(tx_buffer, len),
615 tx_buffer->next_to_watch,
616 (u64)tx_buffer->time_stamp);
617 }
618
619 /* Print TX Rings */
620 if (!netif_msg_tx_done(adapter))
621 goto rx_ring_summary;
622
623 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
624
625 /* Transmit Descriptor Formats
626 *
627 * 82598 Advanced Transmit Descriptor
628 * +--------------------------------------------------------------+
629 * 0 | Buffer Address [63:0] |
630 * +--------------------------------------------------------------+
631 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
632 * +--------------------------------------------------------------+
633 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
634 *
635 * 82598 Advanced Transmit Descriptor (Write-Back Format)
636 * +--------------------------------------------------------------+
637 * 0 | RSV [63:0] |
638 * +--------------------------------------------------------------+
639 * 8 | RSV | STA | NXTSEQ |
640 * +--------------------------------------------------------------+
641 * 63 36 35 32 31 0
642 *
643 * 82599+ Advanced Transmit Descriptor
644 * +--------------------------------------------------------------+
645 * 0 | Buffer Address [63:0] |
646 * +--------------------------------------------------------------+
647 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
648 * +--------------------------------------------------------------+
649 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
650 *
651 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
652 * +--------------------------------------------------------------+
653 * 0 | RSV [63:0] |
654 * +--------------------------------------------------------------+
655 * 8 | RSV | STA | RSV |
656 * +--------------------------------------------------------------+
657 * 63 36 35 32 31 0
658 */
659
660 for (n = 0; n < adapter->num_tx_queues; n++) {
661 tx_ring = adapter->tx_ring[n];
662 pr_info("------------------------------------\n");
663 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
664 pr_info("------------------------------------\n");
665 pr_info("%s%s %s %s %s %s\n",
666 "T [desc] [address 63:0 ] ",
667 "[PlPOIdStDDt Ln] [bi->dma ] ",
668 "leng", "ntw", "timestamp", "bi->skb");
669
670 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
671 tx_desc = IXGBE_TX_DESC(tx_ring, i);
672 tx_buffer = &tx_ring->tx_buffer_info[i];
673 u0 = (struct my_u0 *)tx_desc;
674 if (dma_unmap_len(tx_buffer, len) > 0) {
675 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
676 i,
677 le64_to_cpu(u0->a),
678 le64_to_cpu(u0->b),
679 (u64)dma_unmap_addr(tx_buffer, dma),
680 dma_unmap_len(tx_buffer, len),
681 tx_buffer->next_to_watch,
682 (u64)tx_buffer->time_stamp,
683 tx_buffer->skb);
684 if (i == tx_ring->next_to_use &&
685 i == tx_ring->next_to_clean)
686 pr_cont(" NTC/U\n");
687 else if (i == tx_ring->next_to_use)
688 pr_cont(" NTU\n");
689 else if (i == tx_ring->next_to_clean)
690 pr_cont(" NTC\n");
691 else
692 pr_cont("\n");
693
694 if (netif_msg_pktdata(adapter) &&
695 tx_buffer->skb)
696 print_hex_dump(KERN_INFO, "",
697 DUMP_PREFIX_ADDRESS, 16, 1,
698 tx_buffer->skb->data,
699 dma_unmap_len(tx_buffer, len),
700 true);
701 }
702 }
703 }
704
705 /* Print RX Rings Summary */
706 rx_ring_summary:
707 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
708 pr_info("Queue [NTU] [NTC]\n");
709 for (n = 0; n < adapter->num_rx_queues; n++) {
710 rx_ring = adapter->rx_ring[n];
711 pr_info("%5d %5X %5X\n",
712 n, rx_ring->next_to_use, rx_ring->next_to_clean);
713 }
714
715 /* Print RX Rings */
716 if (!netif_msg_rx_status(adapter))
717 return;
718
719 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
720
721 /* Receive Descriptor Formats
722 *
723 * 82598 Advanced Receive Descriptor (Read) Format
724 * 63 1 0
725 * +-----------------------------------------------------+
726 * 0 | Packet Buffer Address [63:1] |A0/NSE|
727 * +----------------------------------------------+------+
728 * 8 | Header Buffer Address [63:1] | DD |
729 * +-----------------------------------------------------+
730 *
731 *
732 * 82598 Advanced Receive Descriptor (Write-Back) Format
733 *
734 * 63 48 47 32 31 30 21 20 16 15 4 3 0
735 * +------------------------------------------------------+
736 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
737 * | Packet | IP | | | | Type | Type |
738 * | Checksum | Ident | | | | | |
739 * +------------------------------------------------------+
740 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
741 * +------------------------------------------------------+
742 * 63 48 47 32 31 20 19 0
743 *
744 * 82599+ Advanced Receive Descriptor (Read) Format
745 * 63 1 0
746 * +-----------------------------------------------------+
747 * 0 | Packet Buffer Address [63:1] |A0/NSE|
748 * +----------------------------------------------+------+
749 * 8 | Header Buffer Address [63:1] | DD |
750 * +-----------------------------------------------------+
751 *
752 *
753 * 82599+ Advanced Receive Descriptor (Write-Back) Format
754 *
755 * 63 48 47 32 31 30 21 20 17 16 4 3 0
756 * +------------------------------------------------------+
757 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
758 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
759 * |/ Flow Dir Flt ID | | | | | |
760 * +------------------------------------------------------+
761 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
762 * +------------------------------------------------------+
763 * 63 48 47 32 31 20 19 0
764 */
765
766 for (n = 0; n < adapter->num_rx_queues; n++) {
767 rx_ring = adapter->rx_ring[n];
768 pr_info("------------------------------------\n");
769 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
770 pr_info("------------------------------------\n");
771 pr_info("%s%s%s",
772 "R [desc] [ PktBuf A0] ",
773 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
774 "<-- Adv Rx Read format\n");
775 pr_info("%s%s%s",
776 "RWB[desc] [PcsmIpSHl PtRs] ",
777 "[vl er S cks ln] ---------------- [bi->skb ] ",
778 "<-- Adv Rx Write-Back format\n");
779
780 for (i = 0; i < rx_ring->count; i++) {
781 rx_buffer_info = &rx_ring->rx_buffer_info[i];
782 rx_desc = IXGBE_RX_DESC(rx_ring, i);
783 u0 = (struct my_u0 *)rx_desc;
784 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
785 if (staterr & IXGBE_RXD_STAT_DD) {
786 /* Descriptor Done */
787 pr_info("RWB[0x%03X] %016llX "
788 "%016llX ---------------- %p", i,
789 le64_to_cpu(u0->a),
790 le64_to_cpu(u0->b),
791 rx_buffer_info->skb);
792 } else {
793 pr_info("R [0x%03X] %016llX "
794 "%016llX %016llX %p", i,
795 le64_to_cpu(u0->a),
796 le64_to_cpu(u0->b),
797 (u64)rx_buffer_info->dma,
798 rx_buffer_info->skb);
799
800 if (netif_msg_pktdata(adapter) &&
801 rx_buffer_info->dma) {
802 print_hex_dump(KERN_INFO, "",
803 DUMP_PREFIX_ADDRESS, 16, 1,
804 page_address(rx_buffer_info->page) +
805 rx_buffer_info->page_offset,
806 ixgbe_rx_bufsz(rx_ring), true);
807 }
808 }
809
810 if (i == rx_ring->next_to_use)
811 pr_cont(" NTU\n");
812 else if (i == rx_ring->next_to_clean)
813 pr_cont(" NTC\n");
814 else
815 pr_cont("\n");
816
817 }
818 }
819 }
820
821 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
822 {
823 u32 ctrl_ext;
824
825 /* Let firmware take over control of h/w */
826 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
827 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
828 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
829 }
830
831 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
832 {
833 u32 ctrl_ext;
834
835 /* Let firmware know the driver has taken over */
836 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
837 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
838 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
839 }
840
841 /**
842 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
843 * @adapter: pointer to adapter struct
844 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
845 * @queue: queue to map the corresponding interrupt to
846 * @msix_vector: the vector to map to the corresponding queue
847 *
848 */
849 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
850 u8 queue, u8 msix_vector)
851 {
852 u32 ivar, index;
853 struct ixgbe_hw *hw = &adapter->hw;
854 switch (hw->mac.type) {
855 case ixgbe_mac_82598EB:
856 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
857 if (direction == -1)
858 direction = 0;
859 index = (((direction * 64) + queue) >> 2) & 0x1F;
860 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
861 ivar &= ~(0xFF << (8 * (queue & 0x3)));
862 ivar |= (msix_vector << (8 * (queue & 0x3)));
863 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
864 break;
865 case ixgbe_mac_82599EB:
866 case ixgbe_mac_X540:
867 case ixgbe_mac_X550:
868 case ixgbe_mac_X550EM_x:
869 if (direction == -1) {
870 /* other causes */
871 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
872 index = ((queue & 1) * 8);
873 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
874 ivar &= ~(0xFF << index);
875 ivar |= (msix_vector << index);
876 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
877 break;
878 } else {
879 /* tx or rx causes */
880 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
881 index = ((16 * (queue & 1)) + (8 * direction));
882 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
883 ivar &= ~(0xFF << index);
884 ivar |= (msix_vector << index);
885 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
886 break;
887 }
888 default:
889 break;
890 }
891 }
892
893 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
894 u64 qmask)
895 {
896 u32 mask;
897
898 switch (adapter->hw.mac.type) {
899 case ixgbe_mac_82598EB:
900 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
901 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
902 break;
903 case ixgbe_mac_82599EB:
904 case ixgbe_mac_X540:
905 case ixgbe_mac_X550:
906 case ixgbe_mac_X550EM_x:
907 mask = (qmask & 0xFFFFFFFF);
908 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
909 mask = (qmask >> 32);
910 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
911 break;
912 default:
913 break;
914 }
915 }
916
917 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
918 struct ixgbe_tx_buffer *tx_buffer)
919 {
920 if (tx_buffer->skb) {
921 dev_kfree_skb_any(tx_buffer->skb);
922 if (dma_unmap_len(tx_buffer, len))
923 dma_unmap_single(ring->dev,
924 dma_unmap_addr(tx_buffer, dma),
925 dma_unmap_len(tx_buffer, len),
926 DMA_TO_DEVICE);
927 } else if (dma_unmap_len(tx_buffer, len)) {
928 dma_unmap_page(ring->dev,
929 dma_unmap_addr(tx_buffer, dma),
930 dma_unmap_len(tx_buffer, len),
931 DMA_TO_DEVICE);
932 }
933 tx_buffer->next_to_watch = NULL;
934 tx_buffer->skb = NULL;
935 dma_unmap_len_set(tx_buffer, len, 0);
936 /* tx_buffer must be completely set up in the transmit path */
937 }
938
939 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
940 {
941 struct ixgbe_hw *hw = &adapter->hw;
942 struct ixgbe_hw_stats *hwstats = &adapter->stats;
943 int i;
944 u32 data;
945
946 if ((hw->fc.current_mode != ixgbe_fc_full) &&
947 (hw->fc.current_mode != ixgbe_fc_rx_pause))
948 return;
949
950 switch (hw->mac.type) {
951 case ixgbe_mac_82598EB:
952 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
953 break;
954 default:
955 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
956 }
957 hwstats->lxoffrxc += data;
958
959 /* refill credits (no tx hang) if we received xoff */
960 if (!data)
961 return;
962
963 for (i = 0; i < adapter->num_tx_queues; i++)
964 clear_bit(__IXGBE_HANG_CHECK_ARMED,
965 &adapter->tx_ring[i]->state);
966 }
967
968 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
969 {
970 struct ixgbe_hw *hw = &adapter->hw;
971 struct ixgbe_hw_stats *hwstats = &adapter->stats;
972 u32 xoff[8] = {0};
973 u8 tc;
974 int i;
975 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
976
977 if (adapter->ixgbe_ieee_pfc)
978 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
979
980 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
981 ixgbe_update_xoff_rx_lfc(adapter);
982 return;
983 }
984
985 /* update stats for each tc, only valid with PFC enabled */
986 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
987 u32 pxoffrxc;
988
989 switch (hw->mac.type) {
990 case ixgbe_mac_82598EB:
991 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
992 break;
993 default:
994 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
995 }
996 hwstats->pxoffrxc[i] += pxoffrxc;
997 /* Get the TC for given UP */
998 tc = netdev_get_prio_tc_map(adapter->netdev, i);
999 xoff[tc] += pxoffrxc;
1000 }
1001
1002 /* disarm tx queues that have received xoff frames */
1003 for (i = 0; i < adapter->num_tx_queues; i++) {
1004 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
1005
1006 tc = tx_ring->dcb_tc;
1007 if (xoff[tc])
1008 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1009 }
1010 }
1011
1012 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
1013 {
1014 return ring->stats.packets;
1015 }
1016
1017 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1018 {
1019 struct ixgbe_adapter *adapter;
1020 struct ixgbe_hw *hw;
1021 u32 head, tail;
1022
1023 if (ring->l2_accel_priv)
1024 adapter = ring->l2_accel_priv->real_adapter;
1025 else
1026 adapter = netdev_priv(ring->netdev);
1027
1028 hw = &adapter->hw;
1029 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1030 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
1031
1032 if (head != tail)
1033 return (head < tail) ?
1034 tail - head : (tail + ring->count - head);
1035
1036 return 0;
1037 }
1038
1039 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1040 {
1041 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1042 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1043 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1044
1045 clear_check_for_tx_hang(tx_ring);
1046
1047 /*
1048 * Check for a hung queue, but be thorough. This verifies
1049 * that a transmit has been completed since the previous
1050 * check AND there is at least one packet pending. The
1051 * ARMED bit is set to indicate a potential hang. The
1052 * bit is cleared if a pause frame is received to remove
1053 * false hang detection due to PFC or 802.3x frames. By
1054 * requiring this to fail twice we avoid races with
1055 * pfc clearing the ARMED bit and conditions where we
1056 * run the check_tx_hang logic with a transmit completion
1057 * pending but without time to complete it yet.
1058 */
1059 if (tx_done_old == tx_done && tx_pending)
1060 /* make sure it is true for two checks in a row */
1061 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1062 &tx_ring->state);
1063 /* update completed stats and continue */
1064 tx_ring->tx_stats.tx_done_old = tx_done;
1065 /* reset the countdown */
1066 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1067
1068 return false;
1069 }
1070
1071 /**
1072 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1073 * @adapter: driver private struct
1074 **/
1075 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1076 {
1077
1078 /* Do the reset outside of interrupt context */
1079 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1080 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
1081 e_warn(drv, "initiating reset due to tx timeout\n");
1082 ixgbe_service_event_schedule(adapter);
1083 }
1084 }
1085
1086 /**
1087 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
1088 * @q_vector: structure containing interrupt and ring information
1089 * @tx_ring: tx ring to clean
1090 **/
1091 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
1092 struct ixgbe_ring *tx_ring)
1093 {
1094 struct ixgbe_adapter *adapter = q_vector->adapter;
1095 struct ixgbe_tx_buffer *tx_buffer;
1096 union ixgbe_adv_tx_desc *tx_desc;
1097 unsigned int total_bytes = 0, total_packets = 0;
1098 unsigned int budget = q_vector->tx.work_limit;
1099 unsigned int i = tx_ring->next_to_clean;
1100
1101 if (test_bit(__IXGBE_DOWN, &adapter->state))
1102 return true;
1103
1104 tx_buffer = &tx_ring->tx_buffer_info[i];
1105 tx_desc = IXGBE_TX_DESC(tx_ring, i);
1106 i -= tx_ring->count;
1107
1108 do {
1109 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1110
1111 /* if next_to_watch is not set then there is no work pending */
1112 if (!eop_desc)
1113 break;
1114
1115 /* prevent any other reads prior to eop_desc */
1116 read_barrier_depends();
1117
1118 /* if DD is not set pending work has not been completed */
1119 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1120 break;
1121
1122 /* clear next_to_watch to prevent false hangs */
1123 tx_buffer->next_to_watch = NULL;
1124
1125 /* update the statistics for this packet */
1126 total_bytes += tx_buffer->bytecount;
1127 total_packets += tx_buffer->gso_segs;
1128
1129 /* free the skb */
1130 dev_consume_skb_any(tx_buffer->skb);
1131
1132 /* unmap skb header data */
1133 dma_unmap_single(tx_ring->dev,
1134 dma_unmap_addr(tx_buffer, dma),
1135 dma_unmap_len(tx_buffer, len),
1136 DMA_TO_DEVICE);
1137
1138 /* clear tx_buffer data */
1139 tx_buffer->skb = NULL;
1140 dma_unmap_len_set(tx_buffer, len, 0);
1141
1142 /* unmap remaining buffers */
1143 while (tx_desc != eop_desc) {
1144 tx_buffer++;
1145 tx_desc++;
1146 i++;
1147 if (unlikely(!i)) {
1148 i -= tx_ring->count;
1149 tx_buffer = tx_ring->tx_buffer_info;
1150 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1151 }
1152
1153 /* unmap any remaining paged data */
1154 if (dma_unmap_len(tx_buffer, len)) {
1155 dma_unmap_page(tx_ring->dev,
1156 dma_unmap_addr(tx_buffer, dma),
1157 dma_unmap_len(tx_buffer, len),
1158 DMA_TO_DEVICE);
1159 dma_unmap_len_set(tx_buffer, len, 0);
1160 }
1161 }
1162
1163 /* move us one more past the eop_desc for start of next pkt */
1164 tx_buffer++;
1165 tx_desc++;
1166 i++;
1167 if (unlikely(!i)) {
1168 i -= tx_ring->count;
1169 tx_buffer = tx_ring->tx_buffer_info;
1170 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1171 }
1172
1173 /* issue prefetch for next Tx descriptor */
1174 prefetch(tx_desc);
1175
1176 /* update budget accounting */
1177 budget--;
1178 } while (likely(budget));
1179
1180 i += tx_ring->count;
1181 tx_ring->next_to_clean = i;
1182 u64_stats_update_begin(&tx_ring->syncp);
1183 tx_ring->stats.bytes += total_bytes;
1184 tx_ring->stats.packets += total_packets;
1185 u64_stats_update_end(&tx_ring->syncp);
1186 q_vector->tx.total_bytes += total_bytes;
1187 q_vector->tx.total_packets += total_packets;
1188
1189 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1190 /* schedule immediate reset if we believe we hung */
1191 struct ixgbe_hw *hw = &adapter->hw;
1192 e_err(drv, "Detected Tx Unit Hang\n"
1193 " Tx Queue <%d>\n"
1194 " TDH, TDT <%x>, <%x>\n"
1195 " next_to_use <%x>\n"
1196 " next_to_clean <%x>\n"
1197 "tx_buffer_info[next_to_clean]\n"
1198 " time_stamp <%lx>\n"
1199 " jiffies <%lx>\n",
1200 tx_ring->queue_index,
1201 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1202 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1203 tx_ring->next_to_use, i,
1204 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1205
1206 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1207
1208 e_info(probe,
1209 "tx hang %d detected on queue %d, resetting adapter\n",
1210 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1211
1212 /* schedule immediate reset if we believe we hung */
1213 ixgbe_tx_timeout_reset(adapter);
1214
1215 /* the adapter is about to reset, no point in enabling stuff */
1216 return true;
1217 }
1218
1219 netdev_tx_completed_queue(txring_txq(tx_ring),
1220 total_packets, total_bytes);
1221
1222 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1223 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1224 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1225 /* Make sure that anybody stopping the queue after this
1226 * sees the new next_to_clean.
1227 */
1228 smp_mb();
1229 if (__netif_subqueue_stopped(tx_ring->netdev,
1230 tx_ring->queue_index)
1231 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1232 netif_wake_subqueue(tx_ring->netdev,
1233 tx_ring->queue_index);
1234 ++tx_ring->tx_stats.restart_queue;
1235 }
1236 }
1237
1238 return !!budget;
1239 }
1240
1241 #ifdef CONFIG_IXGBE_DCA
1242 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1243 struct ixgbe_ring *tx_ring,
1244 int cpu)
1245 {
1246 struct ixgbe_hw *hw = &adapter->hw;
1247 u32 txctrl = 0;
1248 u16 reg_offset;
1249
1250 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1251 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1252
1253 switch (hw->mac.type) {
1254 case ixgbe_mac_82598EB:
1255 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1256 break;
1257 case ixgbe_mac_82599EB:
1258 case ixgbe_mac_X540:
1259 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1260 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1261 break;
1262 default:
1263 /* for unknown hardware do not write register */
1264 return;
1265 }
1266
1267 /*
1268 * We can enable relaxed ordering for reads, but not writes when
1269 * DCA is enabled. This is due to a known issue in some chipsets
1270 * which will cause the DCA tag to be cleared.
1271 */
1272 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1273 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1274 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1275
1276 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1277 }
1278
1279 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1280 struct ixgbe_ring *rx_ring,
1281 int cpu)
1282 {
1283 struct ixgbe_hw *hw = &adapter->hw;
1284 u32 rxctrl = 0;
1285 u8 reg_idx = rx_ring->reg_idx;
1286
1287 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1288 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1289
1290 switch (hw->mac.type) {
1291 case ixgbe_mac_82599EB:
1292 case ixgbe_mac_X540:
1293 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1294 break;
1295 default:
1296 break;
1297 }
1298
1299 /*
1300 * We can enable relaxed ordering for reads, but not writes when
1301 * DCA is enabled. This is due to a known issue in some chipsets
1302 * which will cause the DCA tag to be cleared.
1303 */
1304 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1305 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
1306 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1307
1308 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1309 }
1310
1311 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1312 {
1313 struct ixgbe_adapter *adapter = q_vector->adapter;
1314 struct ixgbe_ring *ring;
1315 int cpu = get_cpu();
1316
1317 if (q_vector->cpu == cpu)
1318 goto out_no_update;
1319
1320 ixgbe_for_each_ring(ring, q_vector->tx)
1321 ixgbe_update_tx_dca(adapter, ring, cpu);
1322
1323 ixgbe_for_each_ring(ring, q_vector->rx)
1324 ixgbe_update_rx_dca(adapter, ring, cpu);
1325
1326 q_vector->cpu = cpu;
1327 out_no_update:
1328 put_cpu();
1329 }
1330
1331 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1332 {
1333 int i;
1334
1335 /* always use CB2 mode, difference is masked in the CB driver */
1336 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1337 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1338 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1339 else
1340 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1341 IXGBE_DCA_CTRL_DCA_DISABLE);
1342
1343 for (i = 0; i < adapter->num_q_vectors; i++) {
1344 adapter->q_vector[i]->cpu = -1;
1345 ixgbe_update_dca(adapter->q_vector[i]);
1346 }
1347 }
1348
1349 static int __ixgbe_notify_dca(struct device *dev, void *data)
1350 {
1351 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1352 unsigned long event = *(unsigned long *)data;
1353
1354 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1355 return 0;
1356
1357 switch (event) {
1358 case DCA_PROVIDER_ADD:
1359 /* if we're already enabled, don't do it again */
1360 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1361 break;
1362 if (dca_add_requester(dev) == 0) {
1363 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1364 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1365 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1366 break;
1367 }
1368 /* Fall Through since DCA is disabled. */
1369 case DCA_PROVIDER_REMOVE:
1370 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1371 dca_remove_requester(dev);
1372 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1373 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1374 IXGBE_DCA_CTRL_DCA_DISABLE);
1375 }
1376 break;
1377 }
1378
1379 return 0;
1380 }
1381
1382 #endif /* CONFIG_IXGBE_DCA */
1383
1384 #define IXGBE_RSS_L4_TYPES_MASK \
1385 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1386 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1387 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1388 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1389
1390 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1391 union ixgbe_adv_rx_desc *rx_desc,
1392 struct sk_buff *skb)
1393 {
1394 u16 rss_type;
1395
1396 if (!(ring->netdev->features & NETIF_F_RXHASH))
1397 return;
1398
1399 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1400 IXGBE_RXDADV_RSSTYPE_MASK;
1401
1402 if (!rss_type)
1403 return;
1404
1405 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1406 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1407 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
1408 }
1409
1410 #ifdef IXGBE_FCOE
1411 /**
1412 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1413 * @ring: structure containing ring specific data
1414 * @rx_desc: advanced rx descriptor
1415 *
1416 * Returns : true if it is FCoE pkt
1417 */
1418 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1419 union ixgbe_adv_rx_desc *rx_desc)
1420 {
1421 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1422
1423 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1424 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1425 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1426 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1427 }
1428
1429 #endif /* IXGBE_FCOE */
1430 /**
1431 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1432 * @ring: structure containing ring specific data
1433 * @rx_desc: current Rx descriptor being processed
1434 * @skb: skb currently being received and modified
1435 **/
1436 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1437 union ixgbe_adv_rx_desc *rx_desc,
1438 struct sk_buff *skb)
1439 {
1440 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1441 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1442 bool encap_pkt = false;
1443
1444 skb_checksum_none_assert(skb);
1445
1446 /* Rx csum disabled */
1447 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1448 return;
1449
1450 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1451 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1452 encap_pkt = true;
1453 skb->encapsulation = 1;
1454 }
1455
1456 /* if IP and error */
1457 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1458 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1459 ring->rx_stats.csum_err++;
1460 return;
1461 }
1462
1463 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1464 return;
1465
1466 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1467 /*
1468 * 82599 errata, UDP frames with a 0 checksum can be marked as
1469 * checksum errors.
1470 */
1471 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1472 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1473 return;
1474
1475 ring->rx_stats.csum_err++;
1476 return;
1477 }
1478
1479 /* It must be a TCP or UDP packet with a valid checksum */
1480 skb->ip_summed = CHECKSUM_UNNECESSARY;
1481 if (encap_pkt) {
1482 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1483 return;
1484
1485 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1486 ring->rx_stats.csum_err++;
1487 return;
1488 }
1489 /* If we checked the outer header let the stack know */
1490 skb->csum_level = 1;
1491 }
1492 }
1493
1494 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1495 struct ixgbe_rx_buffer *bi)
1496 {
1497 struct page *page = bi->page;
1498 dma_addr_t dma;
1499
1500 /* since we are recycling buffers we should seldom need to alloc */
1501 if (likely(page))
1502 return true;
1503
1504 /* alloc new page for storage */
1505 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1506 if (unlikely(!page)) {
1507 rx_ring->rx_stats.alloc_rx_page_failed++;
1508 return false;
1509 }
1510
1511 /* map page for use */
1512 dma = dma_map_page(rx_ring->dev, page, 0,
1513 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1514
1515 /*
1516 * if mapping failed free memory back to system since
1517 * there isn't much point in holding memory we can't use
1518 */
1519 if (dma_mapping_error(rx_ring->dev, dma)) {
1520 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1521
1522 rx_ring->rx_stats.alloc_rx_page_failed++;
1523 return false;
1524 }
1525
1526 bi->dma = dma;
1527 bi->page = page;
1528 bi->page_offset = 0;
1529
1530 return true;
1531 }
1532
1533 /**
1534 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1535 * @rx_ring: ring to place buffers on
1536 * @cleaned_count: number of buffers to replace
1537 **/
1538 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1539 {
1540 union ixgbe_adv_rx_desc *rx_desc;
1541 struct ixgbe_rx_buffer *bi;
1542 u16 i = rx_ring->next_to_use;
1543
1544 /* nothing to do */
1545 if (!cleaned_count)
1546 return;
1547
1548 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1549 bi = &rx_ring->rx_buffer_info[i];
1550 i -= rx_ring->count;
1551
1552 do {
1553 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1554 break;
1555
1556 /*
1557 * Refresh the desc even if buffer_addrs didn't change
1558 * because each write-back erases this info.
1559 */
1560 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1561
1562 rx_desc++;
1563 bi++;
1564 i++;
1565 if (unlikely(!i)) {
1566 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1567 bi = rx_ring->rx_buffer_info;
1568 i -= rx_ring->count;
1569 }
1570
1571 /* clear the status bits for the next_to_use descriptor */
1572 rx_desc->wb.upper.status_error = 0;
1573
1574 cleaned_count--;
1575 } while (cleaned_count);
1576
1577 i += rx_ring->count;
1578
1579 if (rx_ring->next_to_use != i) {
1580 rx_ring->next_to_use = i;
1581
1582 /* update next to alloc since we have filled the ring */
1583 rx_ring->next_to_alloc = i;
1584
1585 /* Force memory writes to complete before letting h/w
1586 * know there are new descriptors to fetch. (Only
1587 * applicable for weak-ordered memory model archs,
1588 * such as IA-64).
1589 */
1590 wmb();
1591 writel(i, rx_ring->tail);
1592 }
1593 }
1594
1595 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1596 struct sk_buff *skb)
1597 {
1598 u16 hdr_len = skb_headlen(skb);
1599
1600 /* set gso_size to avoid messing up TCP MSS */
1601 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1602 IXGBE_CB(skb)->append_cnt);
1603 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1604 }
1605
1606 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1607 struct sk_buff *skb)
1608 {
1609 /* if append_cnt is 0 then frame is not RSC */
1610 if (!IXGBE_CB(skb)->append_cnt)
1611 return;
1612
1613 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1614 rx_ring->rx_stats.rsc_flush++;
1615
1616 ixgbe_set_rsc_gso_size(rx_ring, skb);
1617
1618 /* gso_size is computed using append_cnt so always clear it last */
1619 IXGBE_CB(skb)->append_cnt = 0;
1620 }
1621
1622 /**
1623 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1624 * @rx_ring: rx descriptor ring packet is being transacted on
1625 * @rx_desc: pointer to the EOP Rx descriptor
1626 * @skb: pointer to current skb being populated
1627 *
1628 * This function checks the ring, descriptor, and packet information in
1629 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1630 * other fields within the skb.
1631 **/
1632 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1633 union ixgbe_adv_rx_desc *rx_desc,
1634 struct sk_buff *skb)
1635 {
1636 struct net_device *dev = rx_ring->netdev;
1637 u32 flags = rx_ring->q_vector->adapter->flags;
1638
1639 ixgbe_update_rsc_stats(rx_ring, skb);
1640
1641 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1642
1643 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1644
1645 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED))
1646 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1647
1648 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1649 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1650 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1651 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1652 }
1653
1654 skb_record_rx_queue(skb, rx_ring->queue_index);
1655
1656 skb->protocol = eth_type_trans(skb, dev);
1657 }
1658
1659 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1660 struct sk_buff *skb)
1661 {
1662 skb_mark_napi_id(skb, &q_vector->napi);
1663 if (ixgbe_qv_busy_polling(q_vector))
1664 netif_receive_skb(skb);
1665 else
1666 napi_gro_receive(&q_vector->napi, skb);
1667 }
1668
1669 /**
1670 * ixgbe_is_non_eop - process handling of non-EOP buffers
1671 * @rx_ring: Rx ring being processed
1672 * @rx_desc: Rx descriptor for current buffer
1673 * @skb: Current socket buffer containing buffer in progress
1674 *
1675 * This function updates next to clean. If the buffer is an EOP buffer
1676 * this function exits returning false, otherwise it will place the
1677 * sk_buff in the next buffer to be chained and return true indicating
1678 * that this is in fact a non-EOP buffer.
1679 **/
1680 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1681 union ixgbe_adv_rx_desc *rx_desc,
1682 struct sk_buff *skb)
1683 {
1684 u32 ntc = rx_ring->next_to_clean + 1;
1685
1686 /* fetch, update, and store next to clean */
1687 ntc = (ntc < rx_ring->count) ? ntc : 0;
1688 rx_ring->next_to_clean = ntc;
1689
1690 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1691
1692 /* update RSC append count if present */
1693 if (ring_is_rsc_enabled(rx_ring)) {
1694 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1695 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1696
1697 if (unlikely(rsc_enabled)) {
1698 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1699
1700 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1701 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1702
1703 /* update ntc based on RSC value */
1704 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1705 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1706 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1707 }
1708 }
1709
1710 /* if we are the last buffer then there is nothing else to do */
1711 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1712 return false;
1713
1714 /* place skb in next buffer to be received */
1715 rx_ring->rx_buffer_info[ntc].skb = skb;
1716 rx_ring->rx_stats.non_eop_descs++;
1717
1718 return true;
1719 }
1720
1721 /**
1722 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1723 * @rx_ring: rx descriptor ring packet is being transacted on
1724 * @skb: pointer to current skb being adjusted
1725 *
1726 * This function is an ixgbe specific version of __pskb_pull_tail. The
1727 * main difference between this version and the original function is that
1728 * this function can make several assumptions about the state of things
1729 * that allow for significant optimizations versus the standard function.
1730 * As a result we can do things like drop a frag and maintain an accurate
1731 * truesize for the skb.
1732 */
1733 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1734 struct sk_buff *skb)
1735 {
1736 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1737 unsigned char *va;
1738 unsigned int pull_len;
1739
1740 /*
1741 * it is valid to use page_address instead of kmap since we are
1742 * working with pages allocated out of the lomem pool per
1743 * alloc_page(GFP_ATOMIC)
1744 */
1745 va = skb_frag_address(frag);
1746
1747 /*
1748 * we need the header to contain the greater of either ETH_HLEN or
1749 * 60 bytes if the skb->len is less than 60 for skb_pad.
1750 */
1751 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
1752
1753 /* align pull length to size of long to optimize memcpy performance */
1754 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1755
1756 /* update all of the pointers */
1757 skb_frag_size_sub(frag, pull_len);
1758 frag->page_offset += pull_len;
1759 skb->data_len -= pull_len;
1760 skb->tail += pull_len;
1761 }
1762
1763 /**
1764 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1765 * @rx_ring: rx descriptor ring packet is being transacted on
1766 * @skb: pointer to current skb being updated
1767 *
1768 * This function provides a basic DMA sync up for the first fragment of an
1769 * skb. The reason for doing this is that the first fragment cannot be
1770 * unmapped until we have reached the end of packet descriptor for a buffer
1771 * chain.
1772 */
1773 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1774 struct sk_buff *skb)
1775 {
1776 /* if the page was released unmap it, else just sync our portion */
1777 if (unlikely(IXGBE_CB(skb)->page_released)) {
1778 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1779 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1780 IXGBE_CB(skb)->page_released = false;
1781 } else {
1782 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1783
1784 dma_sync_single_range_for_cpu(rx_ring->dev,
1785 IXGBE_CB(skb)->dma,
1786 frag->page_offset,
1787 ixgbe_rx_bufsz(rx_ring),
1788 DMA_FROM_DEVICE);
1789 }
1790 IXGBE_CB(skb)->dma = 0;
1791 }
1792
1793 /**
1794 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1795 * @rx_ring: rx descriptor ring packet is being transacted on
1796 * @rx_desc: pointer to the EOP Rx descriptor
1797 * @skb: pointer to current skb being fixed
1798 *
1799 * Check for corrupted packet headers caused by senders on the local L2
1800 * embedded NIC switch not setting up their Tx Descriptors right. These
1801 * should be very rare.
1802 *
1803 * Also address the case where we are pulling data in on pages only
1804 * and as such no data is present in the skb header.
1805 *
1806 * In addition if skb is not at least 60 bytes we need to pad it so that
1807 * it is large enough to qualify as a valid Ethernet frame.
1808 *
1809 * Returns true if an error was encountered and skb was freed.
1810 **/
1811 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1812 union ixgbe_adv_rx_desc *rx_desc,
1813 struct sk_buff *skb)
1814 {
1815 struct net_device *netdev = rx_ring->netdev;
1816
1817 /* verify that the packet does not have any known errors */
1818 if (unlikely(ixgbe_test_staterr(rx_desc,
1819 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1820 !(netdev->features & NETIF_F_RXALL))) {
1821 dev_kfree_skb_any(skb);
1822 return true;
1823 }
1824
1825 /* place header in linear portion of buffer */
1826 if (skb_is_nonlinear(skb))
1827 ixgbe_pull_tail(rx_ring, skb);
1828
1829 #ifdef IXGBE_FCOE
1830 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1831 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1832 return false;
1833
1834 #endif
1835 /* if eth_skb_pad returns an error the skb was freed */
1836 if (eth_skb_pad(skb))
1837 return true;
1838
1839 return false;
1840 }
1841
1842 /**
1843 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1844 * @rx_ring: rx descriptor ring to store buffers on
1845 * @old_buff: donor buffer to have page reused
1846 *
1847 * Synchronizes page for reuse by the adapter
1848 **/
1849 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1850 struct ixgbe_rx_buffer *old_buff)
1851 {
1852 struct ixgbe_rx_buffer *new_buff;
1853 u16 nta = rx_ring->next_to_alloc;
1854
1855 new_buff = &rx_ring->rx_buffer_info[nta];
1856
1857 /* update, and store next to alloc */
1858 nta++;
1859 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1860
1861 /* transfer page from old buffer to new buffer */
1862 *new_buff = *old_buff;
1863
1864 /* sync the buffer for use by the device */
1865 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1866 new_buff->page_offset,
1867 ixgbe_rx_bufsz(rx_ring),
1868 DMA_FROM_DEVICE);
1869 }
1870
1871 static inline bool ixgbe_page_is_reserved(struct page *page)
1872 {
1873 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
1874 }
1875
1876 /**
1877 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1878 * @rx_ring: rx descriptor ring to transact packets on
1879 * @rx_buffer: buffer containing page to add
1880 * @rx_desc: descriptor containing length of buffer written by hardware
1881 * @skb: sk_buff to place the data into
1882 *
1883 * This function will add the data contained in rx_buffer->page to the skb.
1884 * This is done either through a direct copy if the data in the buffer is
1885 * less than the skb header size, otherwise it will just attach the page as
1886 * a frag to the skb.
1887 *
1888 * The function will then update the page offset if necessary and return
1889 * true if the buffer can be reused by the adapter.
1890 **/
1891 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1892 struct ixgbe_rx_buffer *rx_buffer,
1893 union ixgbe_adv_rx_desc *rx_desc,
1894 struct sk_buff *skb)
1895 {
1896 struct page *page = rx_buffer->page;
1897 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1898 #if (PAGE_SIZE < 8192)
1899 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1900 #else
1901 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1902 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1903 ixgbe_rx_bufsz(rx_ring);
1904 #endif
1905
1906 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1907 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1908
1909 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1910
1911 /* page is not reserved, we can reuse buffer as-is */
1912 if (likely(!ixgbe_page_is_reserved(page)))
1913 return true;
1914
1915 /* this page cannot be reused so discard it */
1916 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1917 return false;
1918 }
1919
1920 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1921 rx_buffer->page_offset, size, truesize);
1922
1923 /* avoid re-using remote pages */
1924 if (unlikely(ixgbe_page_is_reserved(page)))
1925 return false;
1926
1927 #if (PAGE_SIZE < 8192)
1928 /* if we are only owner of page we can reuse it */
1929 if (unlikely(page_count(page) != 1))
1930 return false;
1931
1932 /* flip page offset to other buffer */
1933 rx_buffer->page_offset ^= truesize;
1934 #else
1935 /* move offset up to the next cache line */
1936 rx_buffer->page_offset += truesize;
1937
1938 if (rx_buffer->page_offset > last_offset)
1939 return false;
1940 #endif
1941
1942 /* Even if we own the page, we are not allowed to use atomic_set()
1943 * This would break get_page_unless_zero() users.
1944 */
1945 atomic_inc(&page->_count);
1946
1947 return true;
1948 }
1949
1950 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1951 union ixgbe_adv_rx_desc *rx_desc)
1952 {
1953 struct ixgbe_rx_buffer *rx_buffer;
1954 struct sk_buff *skb;
1955 struct page *page;
1956
1957 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1958 page = rx_buffer->page;
1959 prefetchw(page);
1960
1961 skb = rx_buffer->skb;
1962
1963 if (likely(!skb)) {
1964 void *page_addr = page_address(page) +
1965 rx_buffer->page_offset;
1966
1967 /* prefetch first cache line of first page */
1968 prefetch(page_addr);
1969 #if L1_CACHE_BYTES < 128
1970 prefetch(page_addr + L1_CACHE_BYTES);
1971 #endif
1972
1973 /* allocate a skb to store the frags */
1974 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
1975 IXGBE_RX_HDR_SIZE);
1976 if (unlikely(!skb)) {
1977 rx_ring->rx_stats.alloc_rx_buff_failed++;
1978 return NULL;
1979 }
1980
1981 /*
1982 * we will be copying header into skb->data in
1983 * pskb_may_pull so it is in our interest to prefetch
1984 * it now to avoid a possible cache miss
1985 */
1986 prefetchw(skb->data);
1987
1988 /*
1989 * Delay unmapping of the first packet. It carries the
1990 * header information, HW may still access the header
1991 * after the writeback. Only unmap it when EOP is
1992 * reached
1993 */
1994 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1995 goto dma_sync;
1996
1997 IXGBE_CB(skb)->dma = rx_buffer->dma;
1998 } else {
1999 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2000 ixgbe_dma_sync_frag(rx_ring, skb);
2001
2002 dma_sync:
2003 /* we are reusing so sync this buffer for CPU use */
2004 dma_sync_single_range_for_cpu(rx_ring->dev,
2005 rx_buffer->dma,
2006 rx_buffer->page_offset,
2007 ixgbe_rx_bufsz(rx_ring),
2008 DMA_FROM_DEVICE);
2009
2010 rx_buffer->skb = NULL;
2011 }
2012
2013 /* pull page into skb */
2014 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2015 /* hand second half of page back to the ring */
2016 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2017 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2018 /* the page has been released from the ring */
2019 IXGBE_CB(skb)->page_released = true;
2020 } else {
2021 /* we are not reusing the buffer so unmap it */
2022 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2023 ixgbe_rx_pg_size(rx_ring),
2024 DMA_FROM_DEVICE);
2025 }
2026
2027 /* clear contents of buffer_info */
2028 rx_buffer->page = NULL;
2029
2030 return skb;
2031 }
2032
2033 /**
2034 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2035 * @q_vector: structure containing interrupt and ring information
2036 * @rx_ring: rx descriptor ring to transact packets on
2037 * @budget: Total limit on number of packets to process
2038 *
2039 * This function provides a "bounce buffer" approach to Rx interrupt
2040 * processing. The advantage to this is that on systems that have
2041 * expensive overhead for IOMMU access this provides a means of avoiding
2042 * it by maintaining the mapping of the page to the syste.
2043 *
2044 * Returns amount of work completed
2045 **/
2046 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
2047 struct ixgbe_ring *rx_ring,
2048 const int budget)
2049 {
2050 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2051 #ifdef IXGBE_FCOE
2052 struct ixgbe_adapter *adapter = q_vector->adapter;
2053 int ddp_bytes;
2054 unsigned int mss = 0;
2055 #endif /* IXGBE_FCOE */
2056 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
2057
2058 while (likely(total_rx_packets < budget)) {
2059 union ixgbe_adv_rx_desc *rx_desc;
2060 struct sk_buff *skb;
2061
2062 /* return some buffers to hardware, one at a time is too slow */
2063 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2064 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2065 cleaned_count = 0;
2066 }
2067
2068 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2069
2070 if (!rx_desc->wb.upper.status_error)
2071 break;
2072
2073 /* This memory barrier is needed to keep us from reading
2074 * any other fields out of the rx_desc until we know the
2075 * descriptor has been written back
2076 */
2077 dma_rmb();
2078
2079 /* retrieve a buffer from the ring */
2080 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
2081
2082 /* exit if we failed to retrieve a buffer */
2083 if (!skb)
2084 break;
2085
2086 cleaned_count++;
2087
2088 /* place incomplete frames back on ring for completion */
2089 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2090 continue;
2091
2092 /* verify the packet layout is correct */
2093 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2094 continue;
2095
2096 /* probably a little skewed due to removing CRC */
2097 total_rx_bytes += skb->len;
2098
2099 /* populate checksum, timestamp, VLAN, and protocol */
2100 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2101
2102 #ifdef IXGBE_FCOE
2103 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2104 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2105 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2106 /* include DDPed FCoE data */
2107 if (ddp_bytes > 0) {
2108 if (!mss) {
2109 mss = rx_ring->netdev->mtu -
2110 sizeof(struct fcoe_hdr) -
2111 sizeof(struct fc_frame_header) -
2112 sizeof(struct fcoe_crc_eof);
2113 if (mss > 512)
2114 mss &= ~511;
2115 }
2116 total_rx_bytes += ddp_bytes;
2117 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2118 mss);
2119 }
2120 if (!ddp_bytes) {
2121 dev_kfree_skb_any(skb);
2122 continue;
2123 }
2124 }
2125
2126 #endif /* IXGBE_FCOE */
2127 ixgbe_rx_skb(q_vector, skb);
2128
2129 /* update budget accounting */
2130 total_rx_packets++;
2131 }
2132
2133 u64_stats_update_begin(&rx_ring->syncp);
2134 rx_ring->stats.packets += total_rx_packets;
2135 rx_ring->stats.bytes += total_rx_bytes;
2136 u64_stats_update_end(&rx_ring->syncp);
2137 q_vector->rx.total_packets += total_rx_packets;
2138 q_vector->rx.total_bytes += total_rx_bytes;
2139
2140 return total_rx_packets;
2141 }
2142
2143 #ifdef CONFIG_NET_RX_BUSY_POLL
2144 /* must be called with local_bh_disable()d */
2145 static int ixgbe_low_latency_recv(struct napi_struct *napi)
2146 {
2147 struct ixgbe_q_vector *q_vector =
2148 container_of(napi, struct ixgbe_q_vector, napi);
2149 struct ixgbe_adapter *adapter = q_vector->adapter;
2150 struct ixgbe_ring *ring;
2151 int found = 0;
2152
2153 if (test_bit(__IXGBE_DOWN, &adapter->state))
2154 return LL_FLUSH_FAILED;
2155
2156 if (!ixgbe_qv_lock_poll(q_vector))
2157 return LL_FLUSH_BUSY;
2158
2159 ixgbe_for_each_ring(ring, q_vector->rx) {
2160 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
2161 #ifdef BP_EXTENDED_STATS
2162 if (found)
2163 ring->stats.cleaned += found;
2164 else
2165 ring->stats.misses++;
2166 #endif
2167 if (found)
2168 break;
2169 }
2170
2171 ixgbe_qv_unlock_poll(q_vector);
2172
2173 return found;
2174 }
2175 #endif /* CONFIG_NET_RX_BUSY_POLL */
2176
2177 /**
2178 * ixgbe_configure_msix - Configure MSI-X hardware
2179 * @adapter: board private structure
2180 *
2181 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2182 * interrupts.
2183 **/
2184 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2185 {
2186 struct ixgbe_q_vector *q_vector;
2187 int v_idx;
2188 u32 mask;
2189
2190 /* Populate MSIX to EITR Select */
2191 if (adapter->num_vfs > 32) {
2192 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2193 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2194 }
2195
2196 /*
2197 * Populate the IVAR table and set the ITR values to the
2198 * corresponding register.
2199 */
2200 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2201 struct ixgbe_ring *ring;
2202 q_vector = adapter->q_vector[v_idx];
2203
2204 ixgbe_for_each_ring(ring, q_vector->rx)
2205 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2206
2207 ixgbe_for_each_ring(ring, q_vector->tx)
2208 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2209
2210 ixgbe_write_eitr(q_vector);
2211 }
2212
2213 switch (adapter->hw.mac.type) {
2214 case ixgbe_mac_82598EB:
2215 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2216 v_idx);
2217 break;
2218 case ixgbe_mac_82599EB:
2219 case ixgbe_mac_X540:
2220 case ixgbe_mac_X550:
2221 case ixgbe_mac_X550EM_x:
2222 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2223 break;
2224 default:
2225 break;
2226 }
2227 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2228
2229 /* set up to autoclear timer, and the vectors */
2230 mask = IXGBE_EIMS_ENABLE_MASK;
2231 mask &= ~(IXGBE_EIMS_OTHER |
2232 IXGBE_EIMS_MAILBOX |
2233 IXGBE_EIMS_LSC);
2234
2235 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2236 }
2237
2238 enum latency_range {
2239 lowest_latency = 0,
2240 low_latency = 1,
2241 bulk_latency = 2,
2242 latency_invalid = 255
2243 };
2244
2245 /**
2246 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2247 * @q_vector: structure containing interrupt and ring information
2248 * @ring_container: structure containing ring performance data
2249 *
2250 * Stores a new ITR value based on packets and byte
2251 * counts during the last interrupt. The advantage of per interrupt
2252 * computation is faster updates and more accurate ITR for the current
2253 * traffic pattern. Constants in this function were computed
2254 * based on theoretical maximum wire speed and thresholds were set based
2255 * on testing data as well as attempting to minimize response time
2256 * while increasing bulk throughput.
2257 * this functionality is controlled by the InterruptThrottleRate module
2258 * parameter (see ixgbe_param.c)
2259 **/
2260 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2261 struct ixgbe_ring_container *ring_container)
2262 {
2263 int bytes = ring_container->total_bytes;
2264 int packets = ring_container->total_packets;
2265 u32 timepassed_us;
2266 u64 bytes_perint;
2267 u8 itr_setting = ring_container->itr;
2268
2269 if (packets == 0)
2270 return;
2271
2272 /* simple throttlerate management
2273 * 0-10MB/s lowest (100000 ints/s)
2274 * 10-20MB/s low (20000 ints/s)
2275 * 20-1249MB/s bulk (12000 ints/s)
2276 */
2277 /* what was last interrupt timeslice? */
2278 timepassed_us = q_vector->itr >> 2;
2279 if (timepassed_us == 0)
2280 return;
2281
2282 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2283
2284 switch (itr_setting) {
2285 case lowest_latency:
2286 if (bytes_perint > 10)
2287 itr_setting = low_latency;
2288 break;
2289 case low_latency:
2290 if (bytes_perint > 20)
2291 itr_setting = bulk_latency;
2292 else if (bytes_perint <= 10)
2293 itr_setting = lowest_latency;
2294 break;
2295 case bulk_latency:
2296 if (bytes_perint <= 20)
2297 itr_setting = low_latency;
2298 break;
2299 }
2300
2301 /* clear work counters since we have the values we need */
2302 ring_container->total_bytes = 0;
2303 ring_container->total_packets = 0;
2304
2305 /* write updated itr to ring container */
2306 ring_container->itr = itr_setting;
2307 }
2308
2309 /**
2310 * ixgbe_write_eitr - write EITR register in hardware specific way
2311 * @q_vector: structure containing interrupt and ring information
2312 *
2313 * This function is made to be called by ethtool and by the driver
2314 * when it needs to update EITR registers at runtime. Hardware
2315 * specific quirks/differences are taken care of here.
2316 */
2317 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2318 {
2319 struct ixgbe_adapter *adapter = q_vector->adapter;
2320 struct ixgbe_hw *hw = &adapter->hw;
2321 int v_idx = q_vector->v_idx;
2322 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2323
2324 switch (adapter->hw.mac.type) {
2325 case ixgbe_mac_82598EB:
2326 /* must write high and low 16 bits to reset counter */
2327 itr_reg |= (itr_reg << 16);
2328 break;
2329 case ixgbe_mac_82599EB:
2330 case ixgbe_mac_X540:
2331 case ixgbe_mac_X550:
2332 case ixgbe_mac_X550EM_x:
2333 /*
2334 * set the WDIS bit to not clear the timer bits and cause an
2335 * immediate assertion of the interrupt
2336 */
2337 itr_reg |= IXGBE_EITR_CNT_WDIS;
2338 break;
2339 default:
2340 break;
2341 }
2342 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2343 }
2344
2345 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2346 {
2347 u32 new_itr = q_vector->itr;
2348 u8 current_itr;
2349
2350 ixgbe_update_itr(q_vector, &q_vector->tx);
2351 ixgbe_update_itr(q_vector, &q_vector->rx);
2352
2353 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2354
2355 switch (current_itr) {
2356 /* counts and packets in update_itr are dependent on these numbers */
2357 case lowest_latency:
2358 new_itr = IXGBE_100K_ITR;
2359 break;
2360 case low_latency:
2361 new_itr = IXGBE_20K_ITR;
2362 break;
2363 case bulk_latency:
2364 new_itr = IXGBE_12K_ITR;
2365 break;
2366 default:
2367 break;
2368 }
2369
2370 if (new_itr != q_vector->itr) {
2371 /* do an exponential smoothing */
2372 new_itr = (10 * new_itr * q_vector->itr) /
2373 ((9 * new_itr) + q_vector->itr);
2374
2375 /* save the algorithm value here */
2376 q_vector->itr = new_itr;
2377
2378 ixgbe_write_eitr(q_vector);
2379 }
2380 }
2381
2382 /**
2383 * ixgbe_check_overtemp_subtask - check for over temperature
2384 * @adapter: pointer to adapter
2385 **/
2386 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2387 {
2388 struct ixgbe_hw *hw = &adapter->hw;
2389 u32 eicr = adapter->interrupt_event;
2390
2391 if (test_bit(__IXGBE_DOWN, &adapter->state))
2392 return;
2393
2394 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2395 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2396 return;
2397
2398 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2399
2400 switch (hw->device_id) {
2401 case IXGBE_DEV_ID_82599_T3_LOM:
2402 /*
2403 * Since the warning interrupt is for both ports
2404 * we don't have to check if:
2405 * - This interrupt wasn't for our port.
2406 * - We may have missed the interrupt so always have to
2407 * check if we got a LSC
2408 */
2409 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
2410 !(eicr & IXGBE_EICR_LSC))
2411 return;
2412
2413 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2414 u32 speed;
2415 bool link_up = false;
2416
2417 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2418
2419 if (link_up)
2420 return;
2421 }
2422
2423 /* Check if this is not due to overtemp */
2424 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2425 return;
2426
2427 break;
2428 default:
2429 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2430 return;
2431 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
2432 return;
2433 break;
2434 }
2435 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2436
2437 adapter->interrupt_event = 0;
2438 }
2439
2440 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2441 {
2442 struct ixgbe_hw *hw = &adapter->hw;
2443
2444 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2445 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2446 e_crit(probe, "Fan has stopped, replace the adapter\n");
2447 /* write to clear the interrupt */
2448 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2449 }
2450 }
2451
2452 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2453 {
2454 struct ixgbe_hw *hw = &adapter->hw;
2455
2456 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2457 return;
2458
2459 switch (adapter->hw.mac.type) {
2460 case ixgbe_mac_82599EB:
2461 /*
2462 * Need to check link state so complete overtemp check
2463 * on service task
2464 */
2465 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2466 (eicr & IXGBE_EICR_LSC)) &&
2467 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2468 adapter->interrupt_event = eicr;
2469 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2470 ixgbe_service_event_schedule(adapter);
2471 return;
2472 }
2473 return;
2474 case ixgbe_mac_X540:
2475 if (!(eicr & IXGBE_EICR_TS))
2476 return;
2477 break;
2478 default:
2479 return;
2480 }
2481
2482 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2483 }
2484
2485 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2486 {
2487 switch (hw->mac.type) {
2488 case ixgbe_mac_82598EB:
2489 if (hw->phy.type == ixgbe_phy_nl)
2490 return true;
2491 return false;
2492 case ixgbe_mac_82599EB:
2493 case ixgbe_mac_X550EM_x:
2494 switch (hw->mac.ops.get_media_type(hw)) {
2495 case ixgbe_media_type_fiber:
2496 case ixgbe_media_type_fiber_qsfp:
2497 return true;
2498 default:
2499 return false;
2500 }
2501 default:
2502 return false;
2503 }
2504 }
2505
2506 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2507 {
2508 struct ixgbe_hw *hw = &adapter->hw;
2509 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
2510
2511 if (!ixgbe_is_sfp(hw))
2512 return;
2513
2514 /* Later MAC's use different SDP */
2515 if (hw->mac.type >= ixgbe_mac_X540)
2516 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2517
2518 if (eicr & eicr_mask) {
2519 /* Clear the interrupt */
2520 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
2521 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2522 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2523 adapter->sfp_poll_time = 0;
2524 ixgbe_service_event_schedule(adapter);
2525 }
2526 }
2527
2528 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2529 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2530 /* Clear the interrupt */
2531 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2532 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2533 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2534 ixgbe_service_event_schedule(adapter);
2535 }
2536 }
2537 }
2538
2539 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2540 {
2541 struct ixgbe_hw *hw = &adapter->hw;
2542
2543 adapter->lsc_int++;
2544 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2545 adapter->link_check_timeout = jiffies;
2546 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2547 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2548 IXGBE_WRITE_FLUSH(hw);
2549 ixgbe_service_event_schedule(adapter);
2550 }
2551 }
2552
2553 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2554 u64 qmask)
2555 {
2556 u32 mask;
2557 struct ixgbe_hw *hw = &adapter->hw;
2558
2559 switch (hw->mac.type) {
2560 case ixgbe_mac_82598EB:
2561 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2562 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2563 break;
2564 case ixgbe_mac_82599EB:
2565 case ixgbe_mac_X540:
2566 case ixgbe_mac_X550:
2567 case ixgbe_mac_X550EM_x:
2568 mask = (qmask & 0xFFFFFFFF);
2569 if (mask)
2570 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2571 mask = (qmask >> 32);
2572 if (mask)
2573 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2574 break;
2575 default:
2576 break;
2577 }
2578 /* skip the flush */
2579 }
2580
2581 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2582 u64 qmask)
2583 {
2584 u32 mask;
2585 struct ixgbe_hw *hw = &adapter->hw;
2586
2587 switch (hw->mac.type) {
2588 case ixgbe_mac_82598EB:
2589 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2590 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2591 break;
2592 case ixgbe_mac_82599EB:
2593 case ixgbe_mac_X540:
2594 case ixgbe_mac_X550:
2595 case ixgbe_mac_X550EM_x:
2596 mask = (qmask & 0xFFFFFFFF);
2597 if (mask)
2598 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2599 mask = (qmask >> 32);
2600 if (mask)
2601 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2602 break;
2603 default:
2604 break;
2605 }
2606 /* skip the flush */
2607 }
2608
2609 /**
2610 * ixgbe_irq_enable - Enable default interrupt generation settings
2611 * @adapter: board private structure
2612 **/
2613 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2614 bool flush)
2615 {
2616 struct ixgbe_hw *hw = &adapter->hw;
2617 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2618
2619 /* don't reenable LSC while waiting for link */
2620 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2621 mask &= ~IXGBE_EIMS_LSC;
2622
2623 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2624 switch (adapter->hw.mac.type) {
2625 case ixgbe_mac_82599EB:
2626 mask |= IXGBE_EIMS_GPI_SDP0(hw);
2627 break;
2628 case ixgbe_mac_X540:
2629 case ixgbe_mac_X550:
2630 case ixgbe_mac_X550EM_x:
2631 mask |= IXGBE_EIMS_TS;
2632 break;
2633 default:
2634 break;
2635 }
2636 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2637 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2638 switch (adapter->hw.mac.type) {
2639 case ixgbe_mac_82599EB:
2640 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2641 mask |= IXGBE_EIMS_GPI_SDP2(hw);
2642 /* fall through */
2643 case ixgbe_mac_X540:
2644 case ixgbe_mac_X550:
2645 case ixgbe_mac_X550EM_x:
2646 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2647 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
2648 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2649 mask |= IXGBE_EICR_GPI_SDP0_X540;
2650 mask |= IXGBE_EIMS_ECC;
2651 mask |= IXGBE_EIMS_MAILBOX;
2652 break;
2653 default:
2654 break;
2655 }
2656
2657 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2658 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2659 mask |= IXGBE_EIMS_FLOW_DIR;
2660
2661 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2662 if (queues)
2663 ixgbe_irq_enable_queues(adapter, ~0);
2664 if (flush)
2665 IXGBE_WRITE_FLUSH(&adapter->hw);
2666 }
2667
2668 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2669 {
2670 struct ixgbe_adapter *adapter = data;
2671 struct ixgbe_hw *hw = &adapter->hw;
2672 u32 eicr;
2673
2674 /*
2675 * Workaround for Silicon errata. Use clear-by-write instead
2676 * of clear-by-read. Reading with EICS will return the
2677 * interrupt causes without clearing, which later be done
2678 * with the write to EICR.
2679 */
2680 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2681
2682 /* The lower 16bits of the EICR register are for the queue interrupts
2683 * which should be masked here in order to not accidentally clear them if
2684 * the bits are high when ixgbe_msix_other is called. There is a race
2685 * condition otherwise which results in possible performance loss
2686 * especially if the ixgbe_msix_other interrupt is triggering
2687 * consistently (as it would when PPS is turned on for the X540 device)
2688 */
2689 eicr &= 0xFFFF0000;
2690
2691 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2692
2693 if (eicr & IXGBE_EICR_LSC)
2694 ixgbe_check_lsc(adapter);
2695
2696 if (eicr & IXGBE_EICR_MAILBOX)
2697 ixgbe_msg_task(adapter);
2698
2699 switch (hw->mac.type) {
2700 case ixgbe_mac_82599EB:
2701 case ixgbe_mac_X540:
2702 case ixgbe_mac_X550:
2703 case ixgbe_mac_X550EM_x:
2704 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2705 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2706 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2707 ixgbe_service_event_schedule(adapter);
2708 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2709 IXGBE_EICR_GPI_SDP0_X540);
2710 }
2711 if (eicr & IXGBE_EICR_ECC) {
2712 e_info(link, "Received ECC Err, initiating reset\n");
2713 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2714 ixgbe_service_event_schedule(adapter);
2715 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2716 }
2717 /* Handle Flow Director Full threshold interrupt */
2718 if (eicr & IXGBE_EICR_FLOW_DIR) {
2719 int reinit_count = 0;
2720 int i;
2721 for (i = 0; i < adapter->num_tx_queues; i++) {
2722 struct ixgbe_ring *ring = adapter->tx_ring[i];
2723 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2724 &ring->state))
2725 reinit_count++;
2726 }
2727 if (reinit_count) {
2728 /* no more flow director interrupts until after init */
2729 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2730 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2731 ixgbe_service_event_schedule(adapter);
2732 }
2733 }
2734 ixgbe_check_sfp_event(adapter, eicr);
2735 ixgbe_check_overtemp_event(adapter, eicr);
2736 break;
2737 default:
2738 break;
2739 }
2740
2741 ixgbe_check_fan_failure(adapter, eicr);
2742
2743 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2744 ixgbe_ptp_check_pps_event(adapter);
2745
2746 /* re-enable the original interrupt state, no lsc, no queues */
2747 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2748 ixgbe_irq_enable(adapter, false, false);
2749
2750 return IRQ_HANDLED;
2751 }
2752
2753 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2754 {
2755 struct ixgbe_q_vector *q_vector = data;
2756
2757 /* EIAM disabled interrupts (on this vector) for us */
2758
2759 if (q_vector->rx.ring || q_vector->tx.ring)
2760 napi_schedule_irqoff(&q_vector->napi);
2761
2762 return IRQ_HANDLED;
2763 }
2764
2765 /**
2766 * ixgbe_poll - NAPI Rx polling callback
2767 * @napi: structure for representing this polling device
2768 * @budget: how many packets driver is allowed to clean
2769 *
2770 * This function is used for legacy and MSI, NAPI mode
2771 **/
2772 int ixgbe_poll(struct napi_struct *napi, int budget)
2773 {
2774 struct ixgbe_q_vector *q_vector =
2775 container_of(napi, struct ixgbe_q_vector, napi);
2776 struct ixgbe_adapter *adapter = q_vector->adapter;
2777 struct ixgbe_ring *ring;
2778 int per_ring_budget, work_done = 0;
2779 bool clean_complete = true;
2780
2781 #ifdef CONFIG_IXGBE_DCA
2782 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2783 ixgbe_update_dca(q_vector);
2784 #endif
2785
2786 ixgbe_for_each_ring(ring, q_vector->tx)
2787 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2788
2789 /* Exit if we are called by netpoll or busy polling is active */
2790 if ((budget <= 0) || !ixgbe_qv_lock_napi(q_vector))
2791 return budget;
2792
2793 /* attempt to distribute budget to each queue fairly, but don't allow
2794 * the budget to go below 1 because we'll exit polling */
2795 if (q_vector->rx.count > 1)
2796 per_ring_budget = max(budget/q_vector->rx.count, 1);
2797 else
2798 per_ring_budget = budget;
2799
2800 ixgbe_for_each_ring(ring, q_vector->rx) {
2801 int cleaned = ixgbe_clean_rx_irq(q_vector, ring,
2802 per_ring_budget);
2803
2804 work_done += cleaned;
2805 clean_complete &= (cleaned < per_ring_budget);
2806 }
2807
2808 ixgbe_qv_unlock_napi(q_vector);
2809 /* If all work not completed, return budget and keep polling */
2810 if (!clean_complete)
2811 return budget;
2812
2813 /* all work done, exit the polling mode */
2814 napi_complete_done(napi, work_done);
2815 if (adapter->rx_itr_setting & 1)
2816 ixgbe_set_itr(q_vector);
2817 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2818 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2819
2820 return 0;
2821 }
2822
2823 /**
2824 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2825 * @adapter: board private structure
2826 *
2827 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2828 * interrupts from the kernel.
2829 **/
2830 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2831 {
2832 struct net_device *netdev = adapter->netdev;
2833 int vector, err;
2834 int ri = 0, ti = 0;
2835
2836 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2837 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2838 struct msix_entry *entry = &adapter->msix_entries[vector];
2839
2840 if (q_vector->tx.ring && q_vector->rx.ring) {
2841 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2842 "%s-%s-%d", netdev->name, "TxRx", ri++);
2843 ti++;
2844 } else if (q_vector->rx.ring) {
2845 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2846 "%s-%s-%d", netdev->name, "rx", ri++);
2847 } else if (q_vector->tx.ring) {
2848 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2849 "%s-%s-%d", netdev->name, "tx", ti++);
2850 } else {
2851 /* skip this unused q_vector */
2852 continue;
2853 }
2854 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2855 q_vector->name, q_vector);
2856 if (err) {
2857 e_err(probe, "request_irq failed for MSIX interrupt "
2858 "Error: %d\n", err);
2859 goto free_queue_irqs;
2860 }
2861 /* If Flow Director is enabled, set interrupt affinity */
2862 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2863 /* assign the mask for this irq */
2864 irq_set_affinity_hint(entry->vector,
2865 &q_vector->affinity_mask);
2866 }
2867 }
2868
2869 err = request_irq(adapter->msix_entries[vector].vector,
2870 ixgbe_msix_other, 0, netdev->name, adapter);
2871 if (err) {
2872 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2873 goto free_queue_irqs;
2874 }
2875
2876 return 0;
2877
2878 free_queue_irqs:
2879 while (vector) {
2880 vector--;
2881 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2882 NULL);
2883 free_irq(adapter->msix_entries[vector].vector,
2884 adapter->q_vector[vector]);
2885 }
2886 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2887 pci_disable_msix(adapter->pdev);
2888 kfree(adapter->msix_entries);
2889 adapter->msix_entries = NULL;
2890 return err;
2891 }
2892
2893 /**
2894 * ixgbe_intr - legacy mode Interrupt Handler
2895 * @irq: interrupt number
2896 * @data: pointer to a network interface device structure
2897 **/
2898 static irqreturn_t ixgbe_intr(int irq, void *data)
2899 {
2900 struct ixgbe_adapter *adapter = data;
2901 struct ixgbe_hw *hw = &adapter->hw;
2902 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2903 u32 eicr;
2904
2905 /*
2906 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2907 * before the read of EICR.
2908 */
2909 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2910
2911 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2912 * therefore no explicit interrupt disable is necessary */
2913 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2914 if (!eicr) {
2915 /*
2916 * shared interrupt alert!
2917 * make sure interrupts are enabled because the read will
2918 * have disabled interrupts due to EIAM
2919 * finish the workaround of silicon errata on 82598. Unmask
2920 * the interrupt that we masked before the EICR read.
2921 */
2922 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2923 ixgbe_irq_enable(adapter, true, true);
2924 return IRQ_NONE; /* Not our interrupt */
2925 }
2926
2927 if (eicr & IXGBE_EICR_LSC)
2928 ixgbe_check_lsc(adapter);
2929
2930 switch (hw->mac.type) {
2931 case ixgbe_mac_82599EB:
2932 ixgbe_check_sfp_event(adapter, eicr);
2933 /* Fall through */
2934 case ixgbe_mac_X540:
2935 case ixgbe_mac_X550:
2936 case ixgbe_mac_X550EM_x:
2937 if (eicr & IXGBE_EICR_ECC) {
2938 e_info(link, "Received ECC Err, initiating reset\n");
2939 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2940 ixgbe_service_event_schedule(adapter);
2941 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2942 }
2943 ixgbe_check_overtemp_event(adapter, eicr);
2944 break;
2945 default:
2946 break;
2947 }
2948
2949 ixgbe_check_fan_failure(adapter, eicr);
2950 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2951 ixgbe_ptp_check_pps_event(adapter);
2952
2953 /* would disable interrupts here but EIAM disabled it */
2954 napi_schedule_irqoff(&q_vector->napi);
2955
2956 /*
2957 * re-enable link(maybe) and non-queue interrupts, no flush.
2958 * ixgbe_poll will re-enable the queue interrupts
2959 */
2960 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2961 ixgbe_irq_enable(adapter, false, false);
2962
2963 return IRQ_HANDLED;
2964 }
2965
2966 /**
2967 * ixgbe_request_irq - initialize interrupts
2968 * @adapter: board private structure
2969 *
2970 * Attempts to configure interrupts using the best available
2971 * capabilities of the hardware and kernel.
2972 **/
2973 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2974 {
2975 struct net_device *netdev = adapter->netdev;
2976 int err;
2977
2978 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2979 err = ixgbe_request_msix_irqs(adapter);
2980 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2981 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2982 netdev->name, adapter);
2983 else
2984 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2985 netdev->name, adapter);
2986
2987 if (err)
2988 e_err(probe, "request_irq failed, Error %d\n", err);
2989
2990 return err;
2991 }
2992
2993 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2994 {
2995 int vector;
2996
2997 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2998 free_irq(adapter->pdev->irq, adapter);
2999 return;
3000 }
3001
3002 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3003 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3004 struct msix_entry *entry = &adapter->msix_entries[vector];
3005
3006 /* free only the irqs that were actually requested */
3007 if (!q_vector->rx.ring && !q_vector->tx.ring)
3008 continue;
3009
3010 /* clear the affinity_mask in the IRQ descriptor */
3011 irq_set_affinity_hint(entry->vector, NULL);
3012
3013 free_irq(entry->vector, q_vector);
3014 }
3015
3016 free_irq(adapter->msix_entries[vector++].vector, adapter);
3017 }
3018
3019 /**
3020 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3021 * @adapter: board private structure
3022 **/
3023 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3024 {
3025 switch (adapter->hw.mac.type) {
3026 case ixgbe_mac_82598EB:
3027 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
3028 break;
3029 case ixgbe_mac_82599EB:
3030 case ixgbe_mac_X540:
3031 case ixgbe_mac_X550:
3032 case ixgbe_mac_X550EM_x:
3033 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3034 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
3035 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
3036 break;
3037 default:
3038 break;
3039 }
3040 IXGBE_WRITE_FLUSH(&adapter->hw);
3041 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3042 int vector;
3043
3044 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3045 synchronize_irq(adapter->msix_entries[vector].vector);
3046
3047 synchronize_irq(adapter->msix_entries[vector++].vector);
3048 } else {
3049 synchronize_irq(adapter->pdev->irq);
3050 }
3051 }
3052
3053 /**
3054 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3055 *
3056 **/
3057 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3058 {
3059 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3060
3061 ixgbe_write_eitr(q_vector);
3062
3063 ixgbe_set_ivar(adapter, 0, 0, 0);
3064 ixgbe_set_ivar(adapter, 1, 0, 0);
3065
3066 e_info(hw, "Legacy interrupt IVAR setup done\n");
3067 }
3068
3069 /**
3070 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3071 * @adapter: board private structure
3072 * @ring: structure containing ring specific data
3073 *
3074 * Configure the Tx descriptor ring after a reset.
3075 **/
3076 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3077 struct ixgbe_ring *ring)
3078 {
3079 struct ixgbe_hw *hw = &adapter->hw;
3080 u64 tdba = ring->dma;
3081 int wait_loop = 10;
3082 u32 txdctl = IXGBE_TXDCTL_ENABLE;
3083 u8 reg_idx = ring->reg_idx;
3084
3085 /* disable queue to avoid issues while updating state */
3086 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
3087 IXGBE_WRITE_FLUSH(hw);
3088
3089 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
3090 (tdba & DMA_BIT_MASK(32)));
3091 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3092 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3093 ring->count * sizeof(union ixgbe_adv_tx_desc));
3094 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3095 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
3096 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
3097
3098 /*
3099 * set WTHRESH to encourage burst writeback, it should not be set
3100 * higher than 1 when:
3101 * - ITR is 0 as it could cause false TX hangs
3102 * - ITR is set to > 100k int/sec and BQL is enabled
3103 *
3104 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3105 * to or less than the number of on chip descriptors, which is
3106 * currently 40.
3107 */
3108 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3109 txdctl |= (1 << 16); /* WTHRESH = 1 */
3110 else
3111 txdctl |= (8 << 16); /* WTHRESH = 8 */
3112
3113 /*
3114 * Setting PTHRESH to 32 both improves performance
3115 * and avoids a TX hang with DFP enabled
3116 */
3117 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3118 32; /* PTHRESH = 32 */
3119
3120 /* reinitialize flowdirector state */
3121 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3122 ring->atr_sample_rate = adapter->atr_sample_rate;
3123 ring->atr_count = 0;
3124 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3125 } else {
3126 ring->atr_sample_rate = 0;
3127 }
3128
3129 /* initialize XPS */
3130 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3131 struct ixgbe_q_vector *q_vector = ring->q_vector;
3132
3133 if (q_vector)
3134 netif_set_xps_queue(ring->netdev,
3135 &q_vector->affinity_mask,
3136 ring->queue_index);
3137 }
3138
3139 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3140
3141 /* enable queue */
3142 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3143
3144 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3145 if (hw->mac.type == ixgbe_mac_82598EB &&
3146 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3147 return;
3148
3149 /* poll to verify queue is enabled */
3150 do {
3151 usleep_range(1000, 2000);
3152 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3153 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3154 if (!wait_loop)
3155 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
3156 }
3157
3158 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3159 {
3160 struct ixgbe_hw *hw = &adapter->hw;
3161 u32 rttdcs, mtqc;
3162 u8 tcs = netdev_get_num_tc(adapter->netdev);
3163
3164 if (hw->mac.type == ixgbe_mac_82598EB)
3165 return;
3166
3167 /* disable the arbiter while setting MTQC */
3168 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3169 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3170 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3171
3172 /* set transmit pool layout */
3173 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3174 mtqc = IXGBE_MTQC_VT_ENA;
3175 if (tcs > 4)
3176 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3177 else if (tcs > 1)
3178 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3179 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3180 mtqc |= IXGBE_MTQC_32VF;
3181 else
3182 mtqc |= IXGBE_MTQC_64VF;
3183 } else {
3184 if (tcs > 4)
3185 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3186 else if (tcs > 1)
3187 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3188 else
3189 mtqc = IXGBE_MTQC_64Q_1PB;
3190 }
3191
3192 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3193
3194 /* Enable Security TX Buffer IFG for multiple pb */
3195 if (tcs) {
3196 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3197 sectx |= IXGBE_SECTX_DCB;
3198 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3199 }
3200
3201 /* re-enable the arbiter */
3202 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3203 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3204 }
3205
3206 /**
3207 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3208 * @adapter: board private structure
3209 *
3210 * Configure the Tx unit of the MAC after a reset.
3211 **/
3212 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3213 {
3214 struct ixgbe_hw *hw = &adapter->hw;
3215 u32 dmatxctl;
3216 u32 i;
3217
3218 ixgbe_setup_mtqc(adapter);
3219
3220 if (hw->mac.type != ixgbe_mac_82598EB) {
3221 /* DMATXCTL.EN must be before Tx queues are enabled */
3222 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3223 dmatxctl |= IXGBE_DMATXCTL_TE;
3224 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3225 }
3226
3227 /* Setup the HW Tx Head and Tail descriptor pointers */
3228 for (i = 0; i < adapter->num_tx_queues; i++)
3229 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3230 }
3231
3232 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3233 struct ixgbe_ring *ring)
3234 {
3235 struct ixgbe_hw *hw = &adapter->hw;
3236 u8 reg_idx = ring->reg_idx;
3237 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3238
3239 srrctl |= IXGBE_SRRCTL_DROP_EN;
3240
3241 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3242 }
3243
3244 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3245 struct ixgbe_ring *ring)
3246 {
3247 struct ixgbe_hw *hw = &adapter->hw;
3248 u8 reg_idx = ring->reg_idx;
3249 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3250
3251 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3252
3253 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3254 }
3255
3256 #ifdef CONFIG_IXGBE_DCB
3257 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3258 #else
3259 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3260 #endif
3261 {
3262 int i;
3263 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3264
3265 if (adapter->ixgbe_ieee_pfc)
3266 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3267
3268 /*
3269 * We should set the drop enable bit if:
3270 * SR-IOV is enabled
3271 * or
3272 * Number of Rx queues > 1 and flow control is disabled
3273 *
3274 * This allows us to avoid head of line blocking for security
3275 * and performance reasons.
3276 */
3277 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3278 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3279 for (i = 0; i < adapter->num_rx_queues; i++)
3280 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3281 } else {
3282 for (i = 0; i < adapter->num_rx_queues; i++)
3283 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3284 }
3285 }
3286
3287 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3288
3289 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3290 struct ixgbe_ring *rx_ring)
3291 {
3292 struct ixgbe_hw *hw = &adapter->hw;
3293 u32 srrctl;
3294 u8 reg_idx = rx_ring->reg_idx;
3295
3296 if (hw->mac.type == ixgbe_mac_82598EB) {
3297 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3298
3299 /*
3300 * if VMDq is not active we must program one srrctl register
3301 * per RSS queue since we have enabled RDRXCTL.MVMEN
3302 */
3303 reg_idx &= mask;
3304 }
3305
3306 /* configure header buffer length, needed for RSC */
3307 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3308
3309 /* configure the packet buffer length */
3310 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3311
3312 /* configure descriptor type */
3313 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3314
3315 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3316 }
3317
3318 /**
3319 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
3320 * @adapter: device handle
3321 *
3322 * - 82598/82599/X540: 128
3323 * - X550(non-SRIOV mode): 512
3324 * - X550(SRIOV mode): 64
3325 */
3326 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
3327 {
3328 if (adapter->hw.mac.type < ixgbe_mac_X550)
3329 return 128;
3330 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3331 return 64;
3332 else
3333 return 512;
3334 }
3335
3336 /**
3337 * ixgbe_store_reta - Write the RETA table to HW
3338 * @adapter: device handle
3339 *
3340 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3341 */
3342 void ixgbe_store_reta(struct ixgbe_adapter *adapter)
3343 {
3344 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3345 struct ixgbe_hw *hw = &adapter->hw;
3346 u32 reta = 0;
3347 u32 indices_multi;
3348 u8 *indir_tbl = adapter->rss_indir_tbl;
3349
3350 /* Fill out the redirection table as follows:
3351 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3352 * indices.
3353 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3354 * - X550: 8 bit wide entries containing 6 bit RSS index
3355 */
3356 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3357 indices_multi = 0x11;
3358 else
3359 indices_multi = 0x1;
3360
3361 /* Write redirection table to HW */
3362 for (i = 0; i < reta_entries; i++) {
3363 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
3364 if ((i & 3) == 3) {
3365 if (i < 128)
3366 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3367 else
3368 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3369 reta);
3370 reta = 0;
3371 }
3372 }
3373 }
3374
3375 /**
3376 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
3377 * @adapter: device handle
3378 *
3379 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3380 */
3381 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
3382 {
3383 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3384 struct ixgbe_hw *hw = &adapter->hw;
3385 u32 vfreta = 0;
3386 unsigned int pf_pool = adapter->num_vfs;
3387
3388 /* Write redirection table to HW */
3389 for (i = 0; i < reta_entries; i++) {
3390 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3391 if ((i & 3) == 3) {
3392 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3393 vfreta);
3394 vfreta = 0;
3395 }
3396 }
3397 }
3398
3399 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3400 {
3401 struct ixgbe_hw *hw = &adapter->hw;
3402 u32 i, j;
3403 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3404 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3405
3406 /* Program table for at least 2 queues w/ SR-IOV so that VFs can
3407 * make full use of any rings they may have. We will use the
3408 * PSRTYPE register to control how many rings we use within the PF.
3409 */
3410 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3411 rss_i = 2;
3412
3413 /* Fill out hash function seeds */
3414 for (i = 0; i < 10; i++)
3415 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3416
3417 /* Fill out redirection table */
3418 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3419
3420 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3421 if (j == rss_i)
3422 j = 0;
3423
3424 adapter->rss_indir_tbl[i] = j;
3425 }
3426
3427 ixgbe_store_reta(adapter);
3428 }
3429
3430 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3431 {
3432 struct ixgbe_hw *hw = &adapter->hw;
3433 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3434 unsigned int pf_pool = adapter->num_vfs;
3435 int i, j;
3436
3437 /* Fill out hash function seeds */
3438 for (i = 0; i < 10; i++)
3439 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3440 adapter->rss_key[i]);
3441
3442 /* Fill out the redirection table */
3443 for (i = 0, j = 0; i < 64; i++, j++) {
3444 if (j == rss_i)
3445 j = 0;
3446
3447 adapter->rss_indir_tbl[i] = j;
3448 }
3449
3450 ixgbe_store_vfreta(adapter);
3451 }
3452
3453 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3454 {
3455 struct ixgbe_hw *hw = &adapter->hw;
3456 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
3457 u32 rxcsum;
3458
3459 /* Disable indicating checksum in descriptor, enables RSS hash */
3460 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3461 rxcsum |= IXGBE_RXCSUM_PCSD;
3462 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3463
3464 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3465 if (adapter->ring_feature[RING_F_RSS].mask)
3466 mrqc = IXGBE_MRQC_RSSEN;
3467 } else {
3468 u8 tcs = netdev_get_num_tc(adapter->netdev);
3469
3470 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3471 if (tcs > 4)
3472 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3473 else if (tcs > 1)
3474 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3475 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3476 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3477 else
3478 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3479 } else {
3480 if (tcs > 4)
3481 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3482 else if (tcs > 1)
3483 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3484 else
3485 mrqc = IXGBE_MRQC_RSSEN;
3486 }
3487 }
3488
3489 /* Perform hash on these packet types */
3490 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3491 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3492 IXGBE_MRQC_RSS_FIELD_IPV6 |
3493 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3494
3495 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3496 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3497 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3498 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3499
3500 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
3501 if ((hw->mac.type >= ixgbe_mac_X550) &&
3502 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3503 unsigned int pf_pool = adapter->num_vfs;
3504
3505 /* Enable VF RSS mode */
3506 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3507 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3508
3509 /* Setup RSS through the VF registers */
3510 ixgbe_setup_vfreta(adapter);
3511 vfmrqc = IXGBE_MRQC_RSSEN;
3512 vfmrqc |= rss_field;
3513 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3514 } else {
3515 ixgbe_setup_reta(adapter);
3516 mrqc |= rss_field;
3517 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3518 }
3519 }
3520
3521 /**
3522 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3523 * @adapter: address of board private structure
3524 * @index: index of ring to set
3525 **/
3526 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3527 struct ixgbe_ring *ring)
3528 {
3529 struct ixgbe_hw *hw = &adapter->hw;
3530 u32 rscctrl;
3531 u8 reg_idx = ring->reg_idx;
3532
3533 if (!ring_is_rsc_enabled(ring))
3534 return;
3535
3536 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3537 rscctrl |= IXGBE_RSCCTL_RSCEN;
3538 /*
3539 * we must limit the number of descriptors so that the
3540 * total size of max desc * buf_len is not greater
3541 * than 65536
3542 */
3543 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3544 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3545 }
3546
3547 #define IXGBE_MAX_RX_DESC_POLL 10
3548 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3549 struct ixgbe_ring *ring)
3550 {
3551 struct ixgbe_hw *hw = &adapter->hw;
3552 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3553 u32 rxdctl;
3554 u8 reg_idx = ring->reg_idx;
3555
3556 if (ixgbe_removed(hw->hw_addr))
3557 return;
3558 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3559 if (hw->mac.type == ixgbe_mac_82598EB &&
3560 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3561 return;
3562
3563 do {
3564 usleep_range(1000, 2000);
3565 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3566 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3567
3568 if (!wait_loop) {
3569 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3570 "the polling period\n", reg_idx);
3571 }
3572 }
3573
3574 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3575 struct ixgbe_ring *ring)
3576 {
3577 struct ixgbe_hw *hw = &adapter->hw;
3578 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3579 u32 rxdctl;
3580 u8 reg_idx = ring->reg_idx;
3581
3582 if (ixgbe_removed(hw->hw_addr))
3583 return;
3584 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3585 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3586
3587 /* write value back with RXDCTL.ENABLE bit cleared */
3588 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3589
3590 if (hw->mac.type == ixgbe_mac_82598EB &&
3591 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3592 return;
3593
3594 /* the hardware may take up to 100us to really disable the rx queue */
3595 do {
3596 udelay(10);
3597 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3598 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3599
3600 if (!wait_loop) {
3601 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3602 "the polling period\n", reg_idx);
3603 }
3604 }
3605
3606 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3607 struct ixgbe_ring *ring)
3608 {
3609 struct ixgbe_hw *hw = &adapter->hw;
3610 u64 rdba = ring->dma;
3611 u32 rxdctl;
3612 u8 reg_idx = ring->reg_idx;
3613
3614 /* disable queue to avoid issues while updating state */
3615 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3616 ixgbe_disable_rx_queue(adapter, ring);
3617
3618 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3619 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3620 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3621 ring->count * sizeof(union ixgbe_adv_rx_desc));
3622 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3623 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3624 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
3625
3626 ixgbe_configure_srrctl(adapter, ring);
3627 ixgbe_configure_rscctl(adapter, ring);
3628
3629 if (hw->mac.type == ixgbe_mac_82598EB) {
3630 /*
3631 * enable cache line friendly hardware writes:
3632 * PTHRESH=32 descriptors (half the internal cache),
3633 * this also removes ugly rx_no_buffer_count increment
3634 * HTHRESH=4 descriptors (to minimize latency on fetch)
3635 * WTHRESH=8 burst writeback up to two cache lines
3636 */
3637 rxdctl &= ~0x3FFFFF;
3638 rxdctl |= 0x080420;
3639 }
3640
3641 /* enable receive descriptor ring */
3642 rxdctl |= IXGBE_RXDCTL_ENABLE;
3643 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3644
3645 ixgbe_rx_desc_queue_enable(adapter, ring);
3646 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3647 }
3648
3649 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3650 {
3651 struct ixgbe_hw *hw = &adapter->hw;
3652 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3653 u16 pool;
3654
3655 /* PSRTYPE must be initialized in non 82598 adapters */
3656 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3657 IXGBE_PSRTYPE_UDPHDR |
3658 IXGBE_PSRTYPE_IPV4HDR |
3659 IXGBE_PSRTYPE_L2HDR |
3660 IXGBE_PSRTYPE_IPV6HDR;
3661
3662 if (hw->mac.type == ixgbe_mac_82598EB)
3663 return;
3664
3665 if (rss_i > 3)
3666 psrtype |= 2 << 29;
3667 else if (rss_i > 1)
3668 psrtype |= 1 << 29;
3669
3670 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3671 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
3672 }
3673
3674 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3675 {
3676 struct ixgbe_hw *hw = &adapter->hw;
3677 u32 reg_offset, vf_shift;
3678 u32 gcr_ext, vmdctl;
3679 int i;
3680
3681 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3682 return;
3683
3684 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3685 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3686 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3687 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3688 vmdctl |= IXGBE_VT_CTL_REPLEN;
3689 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3690
3691 vf_shift = VMDQ_P(0) % 32;
3692 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3693
3694 /* Enable only the PF's pool for Tx/Rx */
3695 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3696 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3697 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3698 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3699 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
3700 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3701
3702 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3703 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3704
3705 /*
3706 * Set up VF register offsets for selected VT Mode,
3707 * i.e. 32 or 64 VFs for SR-IOV
3708 */
3709 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3710 case IXGBE_82599_VMDQ_8Q_MASK:
3711 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3712 break;
3713 case IXGBE_82599_VMDQ_4Q_MASK:
3714 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3715 break;
3716 default:
3717 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3718 break;
3719 }
3720
3721 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3722
3723
3724 /* Enable MAC Anti-Spoofing */
3725 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3726 adapter->num_vfs);
3727
3728 /* Ensure LLDP and FC is set for Ethertype Antispoofing if we will be
3729 * calling set_ethertype_anti_spoofing for each VF in loop below
3730 */
3731 if (hw->mac.ops.set_ethertype_anti_spoofing) {
3732 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
3733 (IXGBE_ETQF_FILTER_EN |
3734 IXGBE_ETQF_TX_ANTISPOOF |
3735 IXGBE_ETH_P_LLDP));
3736
3737 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FC),
3738 (IXGBE_ETQF_FILTER_EN |
3739 IXGBE_ETQF_TX_ANTISPOOF |
3740 ETH_P_PAUSE));
3741 }
3742
3743 /* For VFs that have spoof checking turned off */
3744 for (i = 0; i < adapter->num_vfs; i++) {
3745 if (!adapter->vfinfo[i].spoofchk_enabled)
3746 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3747
3748 /* enable ethertype anti spoofing if hw supports it */
3749 if (hw->mac.ops.set_ethertype_anti_spoofing)
3750 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
3751
3752 /* Enable/Disable RSS query feature */
3753 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
3754 adapter->vfinfo[i].rss_query_enabled);
3755 }
3756 }
3757
3758 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3759 {
3760 struct ixgbe_hw *hw = &adapter->hw;
3761 struct net_device *netdev = adapter->netdev;
3762 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3763 struct ixgbe_ring *rx_ring;
3764 int i;
3765 u32 mhadd, hlreg0;
3766
3767 #ifdef IXGBE_FCOE
3768 /* adjust max frame to be able to do baby jumbo for FCoE */
3769 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3770 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3771 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3772
3773 #endif /* IXGBE_FCOE */
3774
3775 /* adjust max frame to be at least the size of a standard frame */
3776 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3777 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3778
3779 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3780 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3781 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3782 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3783
3784 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3785 }
3786
3787 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3788 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3789 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3790 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3791
3792 /*
3793 * Setup the HW Rx Head and Tail Descriptor Pointers and
3794 * the Base and Length of the Rx Descriptor Ring
3795 */
3796 for (i = 0; i < adapter->num_rx_queues; i++) {
3797 rx_ring = adapter->rx_ring[i];
3798 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3799 set_ring_rsc_enabled(rx_ring);
3800 else
3801 clear_ring_rsc_enabled(rx_ring);
3802 }
3803 }
3804
3805 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3806 {
3807 struct ixgbe_hw *hw = &adapter->hw;
3808 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3809
3810 switch (hw->mac.type) {
3811 case ixgbe_mac_82598EB:
3812 /*
3813 * For VMDq support of different descriptor types or
3814 * buffer sizes through the use of multiple SRRCTL
3815 * registers, RDRXCTL.MVMEN must be set to 1
3816 *
3817 * also, the manual doesn't mention it clearly but DCA hints
3818 * will only use queue 0's tags unless this bit is set. Side
3819 * effects of setting this bit are only that SRRCTL must be
3820 * fully programmed [0..15]
3821 */
3822 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3823 break;
3824 case ixgbe_mac_X550:
3825 case ixgbe_mac_X550EM_x:
3826 if (adapter->num_vfs)
3827 rdrxctl |= IXGBE_RDRXCTL_PSP;
3828 /* fall through for older HW */
3829 case ixgbe_mac_82599EB:
3830 case ixgbe_mac_X540:
3831 /* Disable RSC for ACK packets */
3832 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3833 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3834 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3835 /* hardware requires some bits to be set by default */
3836 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3837 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3838 break;
3839 default:
3840 /* We should do nothing since we don't know this hardware */
3841 return;
3842 }
3843
3844 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3845 }
3846
3847 /**
3848 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3849 * @adapter: board private structure
3850 *
3851 * Configure the Rx unit of the MAC after a reset.
3852 **/
3853 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3854 {
3855 struct ixgbe_hw *hw = &adapter->hw;
3856 int i;
3857 u32 rxctrl, rfctl;
3858
3859 /* disable receives while setting up the descriptors */
3860 hw->mac.ops.disable_rx(hw);
3861
3862 ixgbe_setup_psrtype(adapter);
3863 ixgbe_setup_rdrxctl(adapter);
3864
3865 /* RSC Setup */
3866 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3867 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3868 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3869 rfctl |= IXGBE_RFCTL_RSC_DIS;
3870 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3871
3872 /* Program registers for the distribution of queues */
3873 ixgbe_setup_mrqc(adapter);
3874
3875 /* set_rx_buffer_len must be called before ring initialization */
3876 ixgbe_set_rx_buffer_len(adapter);
3877
3878 /*
3879 * Setup the HW Rx Head and Tail Descriptor Pointers and
3880 * the Base and Length of the Rx Descriptor Ring
3881 */
3882 for (i = 0; i < adapter->num_rx_queues; i++)
3883 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3884
3885 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3886 /* disable drop enable for 82598 parts */
3887 if (hw->mac.type == ixgbe_mac_82598EB)
3888 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3889
3890 /* enable all receives */
3891 rxctrl |= IXGBE_RXCTRL_RXEN;
3892 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3893 }
3894
3895 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3896 __be16 proto, u16 vid)
3897 {
3898 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3899 struct ixgbe_hw *hw = &adapter->hw;
3900
3901 /* add VID to filter table */
3902 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3903 set_bit(vid, adapter->active_vlans);
3904
3905 return 0;
3906 }
3907
3908 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3909 __be16 proto, u16 vid)
3910 {
3911 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3912 struct ixgbe_hw *hw = &adapter->hw;
3913
3914 /* remove VID from filter table */
3915 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3916 clear_bit(vid, adapter->active_vlans);
3917
3918 return 0;
3919 }
3920
3921 /**
3922 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3923 * @adapter: driver data
3924 */
3925 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3926 {
3927 struct ixgbe_hw *hw = &adapter->hw;
3928 u32 vlnctrl;
3929 int i, j;
3930
3931 switch (hw->mac.type) {
3932 case ixgbe_mac_82598EB:
3933 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3934 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3935 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3936 break;
3937 case ixgbe_mac_82599EB:
3938 case ixgbe_mac_X540:
3939 case ixgbe_mac_X550:
3940 case ixgbe_mac_X550EM_x:
3941 for (i = 0; i < adapter->num_rx_queues; i++) {
3942 struct ixgbe_ring *ring = adapter->rx_ring[i];
3943
3944 if (ring->l2_accel_priv)
3945 continue;
3946 j = ring->reg_idx;
3947 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3948 vlnctrl &= ~IXGBE_RXDCTL_VME;
3949 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3950 }
3951 break;
3952 default:
3953 break;
3954 }
3955 }
3956
3957 /**
3958 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3959 * @adapter: driver data
3960 */
3961 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3962 {
3963 struct ixgbe_hw *hw = &adapter->hw;
3964 u32 vlnctrl;
3965 int i, j;
3966
3967 switch (hw->mac.type) {
3968 case ixgbe_mac_82598EB:
3969 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3970 vlnctrl |= IXGBE_VLNCTRL_VME;
3971 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3972 break;
3973 case ixgbe_mac_82599EB:
3974 case ixgbe_mac_X540:
3975 case ixgbe_mac_X550:
3976 case ixgbe_mac_X550EM_x:
3977 for (i = 0; i < adapter->num_rx_queues; i++) {
3978 struct ixgbe_ring *ring = adapter->rx_ring[i];
3979
3980 if (ring->l2_accel_priv)
3981 continue;
3982 j = ring->reg_idx;
3983 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3984 vlnctrl |= IXGBE_RXDCTL_VME;
3985 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3986 }
3987 break;
3988 default:
3989 break;
3990 }
3991 }
3992
3993 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3994 {
3995 u16 vid;
3996
3997 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
3998
3999 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
4000 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
4001 }
4002
4003 /**
4004 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4005 * @netdev: network interface device structure
4006 *
4007 * Writes multicast address list to the MTA hash table.
4008 * Returns: -ENOMEM on failure
4009 * 0 on no addresses written
4010 * X on writing X addresses to MTA
4011 **/
4012 static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4013 {
4014 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4015 struct ixgbe_hw *hw = &adapter->hw;
4016
4017 if (!netif_running(netdev))
4018 return 0;
4019
4020 if (hw->mac.ops.update_mc_addr_list)
4021 hw->mac.ops.update_mc_addr_list(hw, netdev);
4022 else
4023 return -ENOMEM;
4024
4025 #ifdef CONFIG_PCI_IOV
4026 ixgbe_restore_vf_multicasts(adapter);
4027 #endif
4028
4029 return netdev_mc_count(netdev);
4030 }
4031
4032 #ifdef CONFIG_PCI_IOV
4033 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4034 {
4035 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4036 struct ixgbe_hw *hw = &adapter->hw;
4037 int i;
4038
4039 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4040 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4041
4042 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4043 hw->mac.ops.set_rar(hw, i,
4044 mac_table->addr,
4045 mac_table->pool,
4046 IXGBE_RAH_AV);
4047 else
4048 hw->mac.ops.clear_rar(hw, i);
4049 }
4050 }
4051
4052 #endif
4053 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4054 {
4055 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4056 struct ixgbe_hw *hw = &adapter->hw;
4057 int i;
4058
4059 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4060 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4061 continue;
4062
4063 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4064
4065 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4066 hw->mac.ops.set_rar(hw, i,
4067 mac_table->addr,
4068 mac_table->pool,
4069 IXGBE_RAH_AV);
4070 else
4071 hw->mac.ops.clear_rar(hw, i);
4072 }
4073 }
4074
4075 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4076 {
4077 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4078 struct ixgbe_hw *hw = &adapter->hw;
4079 int i;
4080
4081 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4082 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4083 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4084 }
4085
4086 ixgbe_sync_mac_table(adapter);
4087 }
4088
4089 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
4090 {
4091 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4092 struct ixgbe_hw *hw = &adapter->hw;
4093 int i, count = 0;
4094
4095 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4096 /* do not count default RAR as available */
4097 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4098 continue;
4099
4100 /* only count unused and addresses that belong to us */
4101 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4102 if (mac_table->pool != pool)
4103 continue;
4104 }
4105
4106 count++;
4107 }
4108
4109 return count;
4110 }
4111
4112 /* this function destroys the first RAR entry */
4113 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
4114 {
4115 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4116 struct ixgbe_hw *hw = &adapter->hw;
4117
4118 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4119 mac_table->pool = VMDQ_P(0);
4120
4121 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4122
4123 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
4124 IXGBE_RAH_AV);
4125 }
4126
4127 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4128 const u8 *addr, u16 pool)
4129 {
4130 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4131 struct ixgbe_hw *hw = &adapter->hw;
4132 int i;
4133
4134 if (is_zero_ether_addr(addr))
4135 return -EINVAL;
4136
4137 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4138 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4139 continue;
4140
4141 ether_addr_copy(mac_table->addr, addr);
4142 mac_table->pool = pool;
4143
4144 mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4145 IXGBE_MAC_STATE_IN_USE;
4146
4147 ixgbe_sync_mac_table(adapter);
4148
4149 return i;
4150 }
4151
4152 return -ENOMEM;
4153 }
4154
4155 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4156 const u8 *addr, u16 pool)
4157 {
4158 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4159 struct ixgbe_hw *hw = &adapter->hw;
4160 int i;
4161
4162 if (is_zero_ether_addr(addr))
4163 return -EINVAL;
4164
4165 /* search table for addr, if found clear IN_USE flag and sync */
4166 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4167 /* we can only delete an entry if it is in use */
4168 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4169 continue;
4170 /* we only care about entries that belong to the given pool */
4171 if (mac_table->pool != pool)
4172 continue;
4173 /* we only care about a specific MAC address */
4174 if (!ether_addr_equal(addr, mac_table->addr))
4175 continue;
4176
4177 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4178 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4179
4180 ixgbe_sync_mac_table(adapter);
4181
4182 return 0;
4183 }
4184
4185 return -ENOMEM;
4186 }
4187 /**
4188 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4189 * @netdev: network interface device structure
4190 *
4191 * Writes unicast address list to the RAR table.
4192 * Returns: -ENOMEM on failure/insufficient address space
4193 * 0 on no addresses written
4194 * X on writing X addresses to the RAR table
4195 **/
4196 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
4197 {
4198 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4199 int count = 0;
4200
4201 /* return ENOMEM indicating insufficient memory for addresses */
4202 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn))
4203 return -ENOMEM;
4204
4205 if (!netdev_uc_empty(netdev)) {
4206 struct netdev_hw_addr *ha;
4207 netdev_for_each_uc_addr(ha, netdev) {
4208 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4209 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
4210 count++;
4211 }
4212 }
4213 return count;
4214 }
4215
4216 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4217 {
4218 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4219 int ret;
4220
4221 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4222
4223 return min_t(int, ret, 0);
4224 }
4225
4226 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4227 {
4228 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4229
4230 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4231
4232 return 0;
4233 }
4234
4235 /**
4236 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
4237 * @netdev: network interface device structure
4238 *
4239 * The set_rx_method entry point is called whenever the unicast/multicast
4240 * address list or the network interface flags are updated. This routine is
4241 * responsible for configuring the hardware for proper unicast, multicast and
4242 * promiscuous mode.
4243 **/
4244 void ixgbe_set_rx_mode(struct net_device *netdev)
4245 {
4246 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4247 struct ixgbe_hw *hw = &adapter->hw;
4248 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
4249 u32 vlnctrl;
4250 int count;
4251
4252 /* Check for Promiscuous and All Multicast modes */
4253 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4254 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4255
4256 /* set all bits that we expect to always be set */
4257 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
4258 fctrl |= IXGBE_FCTRL_BAM;
4259 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4260 fctrl |= IXGBE_FCTRL_PMCF;
4261
4262 /* clear the bits we are changing the status of */
4263 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4264 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4265 if (netdev->flags & IFF_PROMISC) {
4266 hw->addr_ctrl.user_set_promisc = true;
4267 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4268 vmolr |= IXGBE_VMOLR_MPE;
4269 /* Only disable hardware filter vlans in promiscuous mode
4270 * if SR-IOV and VMDQ are disabled - otherwise ensure
4271 * that hardware VLAN filters remain enabled.
4272 */
4273 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
4274 IXGBE_FLAG_SRIOV_ENABLED))
4275 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4276 } else {
4277 if (netdev->flags & IFF_ALLMULTI) {
4278 fctrl |= IXGBE_FCTRL_MPE;
4279 vmolr |= IXGBE_VMOLR_MPE;
4280 }
4281 vlnctrl |= IXGBE_VLNCTRL_VFE;
4282 hw->addr_ctrl.user_set_promisc = false;
4283 }
4284
4285 /*
4286 * Write addresses to available RAR registers, if there is not
4287 * sufficient space to store all the addresses then enable
4288 * unicast promiscuous mode
4289 */
4290 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
4291 fctrl |= IXGBE_FCTRL_UPE;
4292 vmolr |= IXGBE_VMOLR_ROPE;
4293 }
4294
4295 /* Write addresses to the MTA, if the attempt fails
4296 * then we should just turn on promiscuous mode so
4297 * that we can at least receive multicast traffic
4298 */
4299 count = ixgbe_write_mc_addr_list(netdev);
4300 if (count < 0) {
4301 fctrl |= IXGBE_FCTRL_MPE;
4302 vmolr |= IXGBE_VMOLR_MPE;
4303 } else if (count) {
4304 vmolr |= IXGBE_VMOLR_ROMPE;
4305 }
4306
4307 if (hw->mac.type != ixgbe_mac_82598EB) {
4308 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
4309 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4310 IXGBE_VMOLR_ROPE);
4311 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
4312 }
4313
4314 /* This is useful for sniffing bad packets. */
4315 if (adapter->netdev->features & NETIF_F_RXALL) {
4316 /* UPE and MPE will be handled by normal PROMISC logic
4317 * in e1000e_set_rx_mode */
4318 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4319 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4320 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4321
4322 fctrl &= ~(IXGBE_FCTRL_DPF);
4323 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4324 }
4325
4326 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4327 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4328
4329 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
4330 ixgbe_vlan_strip_enable(adapter);
4331 else
4332 ixgbe_vlan_strip_disable(adapter);
4333 }
4334
4335 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4336 {
4337 int q_idx;
4338
4339 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4340 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
4341 napi_enable(&adapter->q_vector[q_idx]->napi);
4342 }
4343 }
4344
4345 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4346 {
4347 int q_idx;
4348
4349 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4350 napi_disable(&adapter->q_vector[q_idx]->napi);
4351 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
4352 pr_info("QV %d locked\n", q_idx);
4353 usleep_range(1000, 20000);
4354 }
4355 }
4356 }
4357
4358 static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter)
4359 {
4360 switch (adapter->hw.mac.type) {
4361 case ixgbe_mac_X550:
4362 case ixgbe_mac_X550EM_x:
4363 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0);
4364 #ifdef CONFIG_IXGBE_VXLAN
4365 adapter->vxlan_port = 0;
4366 #endif
4367 break;
4368 default:
4369 break;
4370 }
4371 }
4372
4373 #ifdef CONFIG_IXGBE_DCB
4374 /**
4375 * ixgbe_configure_dcb - Configure DCB hardware
4376 * @adapter: ixgbe adapter struct
4377 *
4378 * This is called by the driver on open to configure the DCB hardware.
4379 * This is also called by the gennetlink interface when reconfiguring
4380 * the DCB state.
4381 */
4382 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4383 {
4384 struct ixgbe_hw *hw = &adapter->hw;
4385 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4386
4387 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4388 if (hw->mac.type == ixgbe_mac_82598EB)
4389 netif_set_gso_max_size(adapter->netdev, 65536);
4390 return;
4391 }
4392
4393 if (hw->mac.type == ixgbe_mac_82598EB)
4394 netif_set_gso_max_size(adapter->netdev, 32768);
4395
4396 #ifdef IXGBE_FCOE
4397 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4398 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
4399 #endif
4400
4401 /* reconfigure the hardware */
4402 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
4403 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4404 DCB_TX_CONFIG);
4405 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4406 DCB_RX_CONFIG);
4407 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
4408 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4409 ixgbe_dcb_hw_ets(&adapter->hw,
4410 adapter->ixgbe_ieee_ets,
4411 max_frame);
4412 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4413 adapter->ixgbe_ieee_pfc->pfc_en,
4414 adapter->ixgbe_ieee_ets->prio_tc);
4415 }
4416
4417 /* Enable RSS Hash per TC */
4418 if (hw->mac.type != ixgbe_mac_82598EB) {
4419 u32 msb = 0;
4420 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
4421
4422 while (rss_i) {
4423 msb++;
4424 rss_i >>= 1;
4425 }
4426
4427 /* write msb to all 8 TCs in one write */
4428 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
4429 }
4430 }
4431 #endif
4432
4433 /* Additional bittime to account for IXGBE framing */
4434 #define IXGBE_ETH_FRAMING 20
4435
4436 /**
4437 * ixgbe_hpbthresh - calculate high water mark for flow control
4438 *
4439 * @adapter: board private structure to calculate for
4440 * @pb: packet buffer to calculate
4441 */
4442 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4443 {
4444 struct ixgbe_hw *hw = &adapter->hw;
4445 struct net_device *dev = adapter->netdev;
4446 int link, tc, kb, marker;
4447 u32 dv_id, rx_pba;
4448
4449 /* Calculate max LAN frame size */
4450 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4451
4452 #ifdef IXGBE_FCOE
4453 /* FCoE traffic class uses FCOE jumbo frames */
4454 if ((dev->features & NETIF_F_FCOE_MTU) &&
4455 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4456 (pb == ixgbe_fcoe_get_tc(adapter)))
4457 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4458 #endif
4459
4460 /* Calculate delay value for device */
4461 switch (hw->mac.type) {
4462 case ixgbe_mac_X540:
4463 case ixgbe_mac_X550:
4464 case ixgbe_mac_X550EM_x:
4465 dv_id = IXGBE_DV_X540(link, tc);
4466 break;
4467 default:
4468 dv_id = IXGBE_DV(link, tc);
4469 break;
4470 }
4471
4472 /* Loopback switch introduces additional latency */
4473 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4474 dv_id += IXGBE_B2BT(tc);
4475
4476 /* Delay value is calculated in bit times convert to KB */
4477 kb = IXGBE_BT2KB(dv_id);
4478 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4479
4480 marker = rx_pba - kb;
4481
4482 /* It is possible that the packet buffer is not large enough
4483 * to provide required headroom. In this case throw an error
4484 * to user and a do the best we can.
4485 */
4486 if (marker < 0) {
4487 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4488 "headroom to support flow control."
4489 "Decrease MTU or number of traffic classes\n", pb);
4490 marker = tc + 1;
4491 }
4492
4493 return marker;
4494 }
4495
4496 /**
4497 * ixgbe_lpbthresh - calculate low water mark for for flow control
4498 *
4499 * @adapter: board private structure to calculate for
4500 * @pb: packet buffer to calculate
4501 */
4502 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
4503 {
4504 struct ixgbe_hw *hw = &adapter->hw;
4505 struct net_device *dev = adapter->netdev;
4506 int tc;
4507 u32 dv_id;
4508
4509 /* Calculate max LAN frame size */
4510 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4511
4512 #ifdef IXGBE_FCOE
4513 /* FCoE traffic class uses FCOE jumbo frames */
4514 if ((dev->features & NETIF_F_FCOE_MTU) &&
4515 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4516 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4517 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4518 #endif
4519
4520 /* Calculate delay value for device */
4521 switch (hw->mac.type) {
4522 case ixgbe_mac_X540:
4523 case ixgbe_mac_X550:
4524 case ixgbe_mac_X550EM_x:
4525 dv_id = IXGBE_LOW_DV_X540(tc);
4526 break;
4527 default:
4528 dv_id = IXGBE_LOW_DV(tc);
4529 break;
4530 }
4531
4532 /* Delay value is calculated in bit times convert to KB */
4533 return IXGBE_BT2KB(dv_id);
4534 }
4535
4536 /*
4537 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4538 */
4539 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4540 {
4541 struct ixgbe_hw *hw = &adapter->hw;
4542 int num_tc = netdev_get_num_tc(adapter->netdev);
4543 int i;
4544
4545 if (!num_tc)
4546 num_tc = 1;
4547
4548 for (i = 0; i < num_tc; i++) {
4549 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4550 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
4551
4552 /* Low water marks must not be larger than high water marks */
4553 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4554 hw->fc.low_water[i] = 0;
4555 }
4556
4557 for (; i < MAX_TRAFFIC_CLASS; i++)
4558 hw->fc.high_water[i] = 0;
4559 }
4560
4561 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4562 {
4563 struct ixgbe_hw *hw = &adapter->hw;
4564 int hdrm;
4565 u8 tc = netdev_get_num_tc(adapter->netdev);
4566
4567 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4568 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4569 hdrm = 32 << adapter->fdir_pballoc;
4570 else
4571 hdrm = 0;
4572
4573 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
4574 ixgbe_pbthresh_setup(adapter);
4575 }
4576
4577 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4578 {
4579 struct ixgbe_hw *hw = &adapter->hw;
4580 struct hlist_node *node2;
4581 struct ixgbe_fdir_filter *filter;
4582
4583 spin_lock(&adapter->fdir_perfect_lock);
4584
4585 if (!hlist_empty(&adapter->fdir_filter_list))
4586 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4587
4588 hlist_for_each_entry_safe(filter, node2,
4589 &adapter->fdir_filter_list, fdir_node) {
4590 ixgbe_fdir_write_perfect_filter_82599(hw,
4591 &filter->filter,
4592 filter->sw_idx,
4593 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4594 IXGBE_FDIR_DROP_QUEUE :
4595 adapter->rx_ring[filter->action]->reg_idx);
4596 }
4597
4598 spin_unlock(&adapter->fdir_perfect_lock);
4599 }
4600
4601 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4602 struct ixgbe_adapter *adapter)
4603 {
4604 struct ixgbe_hw *hw = &adapter->hw;
4605 u32 vmolr;
4606
4607 /* No unicast promiscuous support for VMDQ devices. */
4608 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4609 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4610
4611 /* clear the affected bit */
4612 vmolr &= ~IXGBE_VMOLR_MPE;
4613
4614 if (dev->flags & IFF_ALLMULTI) {
4615 vmolr |= IXGBE_VMOLR_MPE;
4616 } else {
4617 vmolr |= IXGBE_VMOLR_ROMPE;
4618 hw->mac.ops.update_mc_addr_list(hw, dev);
4619 }
4620 ixgbe_write_uc_addr_list(adapter->netdev, pool);
4621 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4622 }
4623
4624 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4625 {
4626 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4627 int rss_i = adapter->num_rx_queues_per_pool;
4628 struct ixgbe_hw *hw = &adapter->hw;
4629 u16 pool = vadapter->pool;
4630 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4631 IXGBE_PSRTYPE_UDPHDR |
4632 IXGBE_PSRTYPE_IPV4HDR |
4633 IXGBE_PSRTYPE_L2HDR |
4634 IXGBE_PSRTYPE_IPV6HDR;
4635
4636 if (hw->mac.type == ixgbe_mac_82598EB)
4637 return;
4638
4639 if (rss_i > 3)
4640 psrtype |= 2 << 29;
4641 else if (rss_i > 1)
4642 psrtype |= 1 << 29;
4643
4644 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4645 }
4646
4647 /**
4648 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4649 * @rx_ring: ring to free buffers from
4650 **/
4651 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4652 {
4653 struct device *dev = rx_ring->dev;
4654 unsigned long size;
4655 u16 i;
4656
4657 /* ring already cleared, nothing to do */
4658 if (!rx_ring->rx_buffer_info)
4659 return;
4660
4661 /* Free all the Rx ring sk_buffs */
4662 for (i = 0; i < rx_ring->count; i++) {
4663 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
4664
4665 if (rx_buffer->skb) {
4666 struct sk_buff *skb = rx_buffer->skb;
4667 if (IXGBE_CB(skb)->page_released)
4668 dma_unmap_page(dev,
4669 IXGBE_CB(skb)->dma,
4670 ixgbe_rx_bufsz(rx_ring),
4671 DMA_FROM_DEVICE);
4672 dev_kfree_skb(skb);
4673 rx_buffer->skb = NULL;
4674 }
4675
4676 if (!rx_buffer->page)
4677 continue;
4678
4679 dma_unmap_page(dev, rx_buffer->dma,
4680 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4681 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4682
4683 rx_buffer->page = NULL;
4684 }
4685
4686 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4687 memset(rx_ring->rx_buffer_info, 0, size);
4688
4689 /* Zero out the descriptor ring */
4690 memset(rx_ring->desc, 0, rx_ring->size);
4691
4692 rx_ring->next_to_alloc = 0;
4693 rx_ring->next_to_clean = 0;
4694 rx_ring->next_to_use = 0;
4695 }
4696
4697 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4698 struct ixgbe_ring *rx_ring)
4699 {
4700 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4701 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4702
4703 /* shutdown specific queue receive and wait for dma to settle */
4704 ixgbe_disable_rx_queue(adapter, rx_ring);
4705 usleep_range(10000, 20000);
4706 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4707 ixgbe_clean_rx_ring(rx_ring);
4708 rx_ring->l2_accel_priv = NULL;
4709 }
4710
4711 static int ixgbe_fwd_ring_down(struct net_device *vdev,
4712 struct ixgbe_fwd_adapter *accel)
4713 {
4714 struct ixgbe_adapter *adapter = accel->real_adapter;
4715 unsigned int rxbase = accel->rx_base_queue;
4716 unsigned int txbase = accel->tx_base_queue;
4717 int i;
4718
4719 netif_tx_stop_all_queues(vdev);
4720
4721 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4722 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4723 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4724 }
4725
4726 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4727 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4728 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4729 }
4730
4731
4732 return 0;
4733 }
4734
4735 static int ixgbe_fwd_ring_up(struct net_device *vdev,
4736 struct ixgbe_fwd_adapter *accel)
4737 {
4738 struct ixgbe_adapter *adapter = accel->real_adapter;
4739 unsigned int rxbase, txbase, queues;
4740 int i, baseq, err = 0;
4741
4742 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4743 return 0;
4744
4745 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4746 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4747 accel->pool, adapter->num_rx_pools,
4748 baseq, baseq + adapter->num_rx_queues_per_pool,
4749 adapter->fwd_bitmask);
4750
4751 accel->netdev = vdev;
4752 accel->rx_base_queue = rxbase = baseq;
4753 accel->tx_base_queue = txbase = baseq;
4754
4755 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4756 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4757
4758 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4759 adapter->rx_ring[rxbase + i]->netdev = vdev;
4760 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4761 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4762 }
4763
4764 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4765 adapter->tx_ring[txbase + i]->netdev = vdev;
4766 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4767 }
4768
4769 queues = min_t(unsigned int,
4770 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4771 err = netif_set_real_num_tx_queues(vdev, queues);
4772 if (err)
4773 goto fwd_queue_err;
4774
4775 err = netif_set_real_num_rx_queues(vdev, queues);
4776 if (err)
4777 goto fwd_queue_err;
4778
4779 if (is_valid_ether_addr(vdev->dev_addr))
4780 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4781
4782 ixgbe_fwd_psrtype(accel);
4783 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4784 return err;
4785 fwd_queue_err:
4786 ixgbe_fwd_ring_down(vdev, accel);
4787 return err;
4788 }
4789
4790 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4791 {
4792 struct net_device *upper;
4793 struct list_head *iter;
4794 int err;
4795
4796 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4797 if (netif_is_macvlan(upper)) {
4798 struct macvlan_dev *dfwd = netdev_priv(upper);
4799 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4800
4801 if (dfwd->fwd_priv) {
4802 err = ixgbe_fwd_ring_up(upper, vadapter);
4803 if (err)
4804 continue;
4805 }
4806 }
4807 }
4808 }
4809
4810 static void ixgbe_configure(struct ixgbe_adapter *adapter)
4811 {
4812 struct ixgbe_hw *hw = &adapter->hw;
4813
4814 ixgbe_configure_pb(adapter);
4815 #ifdef CONFIG_IXGBE_DCB
4816 ixgbe_configure_dcb(adapter);
4817 #endif
4818 /*
4819 * We must restore virtualization before VLANs or else
4820 * the VLVF registers will not be populated
4821 */
4822 ixgbe_configure_virtualization(adapter);
4823
4824 ixgbe_set_rx_mode(adapter->netdev);
4825 ixgbe_restore_vlan(adapter);
4826
4827 switch (hw->mac.type) {
4828 case ixgbe_mac_82599EB:
4829 case ixgbe_mac_X540:
4830 hw->mac.ops.disable_rx_buff(hw);
4831 break;
4832 default:
4833 break;
4834 }
4835
4836 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4837 ixgbe_init_fdir_signature_82599(&adapter->hw,
4838 adapter->fdir_pballoc);
4839 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4840 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4841 adapter->fdir_pballoc);
4842 ixgbe_fdir_filter_restore(adapter);
4843 }
4844
4845 switch (hw->mac.type) {
4846 case ixgbe_mac_82599EB:
4847 case ixgbe_mac_X540:
4848 hw->mac.ops.enable_rx_buff(hw);
4849 break;
4850 default:
4851 break;
4852 }
4853
4854 #ifdef CONFIG_IXGBE_DCA
4855 /* configure DCA */
4856 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
4857 ixgbe_setup_dca(adapter);
4858 #endif /* CONFIG_IXGBE_DCA */
4859
4860 #ifdef IXGBE_FCOE
4861 /* configure FCoE L2 filters, redirection table, and Rx control */
4862 ixgbe_configure_fcoe(adapter);
4863
4864 #endif /* IXGBE_FCOE */
4865 ixgbe_configure_tx(adapter);
4866 ixgbe_configure_rx(adapter);
4867 ixgbe_configure_dfwd(adapter);
4868 }
4869
4870 /**
4871 * ixgbe_sfp_link_config - set up SFP+ link
4872 * @adapter: pointer to private adapter struct
4873 **/
4874 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4875 {
4876 /*
4877 * We are assuming the worst case scenario here, and that
4878 * is that an SFP was inserted/removed after the reset
4879 * but before SFP detection was enabled. As such the best
4880 * solution is to just start searching as soon as we start
4881 */
4882 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4883 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4884
4885 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4886 adapter->sfp_poll_time = 0;
4887 }
4888
4889 /**
4890 * ixgbe_non_sfp_link_config - set up non-SFP+ link
4891 * @hw: pointer to private hardware struct
4892 *
4893 * Returns 0 on success, negative on failure
4894 **/
4895 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4896 {
4897 u32 speed;
4898 bool autoneg, link_up = false;
4899 int ret = IXGBE_ERR_LINK_SETUP;
4900
4901 if (hw->mac.ops.check_link)
4902 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
4903
4904 if (ret)
4905 return ret;
4906
4907 speed = hw->phy.autoneg_advertised;
4908 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4909 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4910 &autoneg);
4911 if (ret)
4912 return ret;
4913
4914 if (hw->mac.ops.setup_link)
4915 ret = hw->mac.ops.setup_link(hw, speed, link_up);
4916
4917 return ret;
4918 }
4919
4920 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4921 {
4922 struct ixgbe_hw *hw = &adapter->hw;
4923 u32 gpie = 0;
4924
4925 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4926 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4927 IXGBE_GPIE_OCD;
4928 gpie |= IXGBE_GPIE_EIAME;
4929 /*
4930 * use EIAM to auto-mask when MSI-X interrupt is asserted
4931 * this saves a register write for every interrupt
4932 */
4933 switch (hw->mac.type) {
4934 case ixgbe_mac_82598EB:
4935 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4936 break;
4937 case ixgbe_mac_82599EB:
4938 case ixgbe_mac_X540:
4939 case ixgbe_mac_X550:
4940 case ixgbe_mac_X550EM_x:
4941 default:
4942 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4943 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4944 break;
4945 }
4946 } else {
4947 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4948 * specifically only auto mask tx and rx interrupts */
4949 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4950 }
4951
4952 /* XXX: to interrupt immediately for EICS writes, enable this */
4953 /* gpie |= IXGBE_GPIE_EIMEN; */
4954
4955 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4956 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4957
4958 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4959 case IXGBE_82599_VMDQ_8Q_MASK:
4960 gpie |= IXGBE_GPIE_VTMODE_16;
4961 break;
4962 case IXGBE_82599_VMDQ_4Q_MASK:
4963 gpie |= IXGBE_GPIE_VTMODE_32;
4964 break;
4965 default:
4966 gpie |= IXGBE_GPIE_VTMODE_64;
4967 break;
4968 }
4969 }
4970
4971 /* Enable Thermal over heat sensor interrupt */
4972 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4973 switch (adapter->hw.mac.type) {
4974 case ixgbe_mac_82599EB:
4975 gpie |= IXGBE_SDP0_GPIEN_8259X;
4976 break;
4977 default:
4978 break;
4979 }
4980 }
4981
4982 /* Enable fan failure interrupt */
4983 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4984 gpie |= IXGBE_SDP1_GPIEN(hw);
4985
4986 switch (hw->mac.type) {
4987 case ixgbe_mac_82599EB:
4988 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
4989 break;
4990 case ixgbe_mac_X550EM_x:
4991 gpie |= IXGBE_SDP0_GPIEN_X540;
4992 break;
4993 default:
4994 break;
4995 }
4996
4997 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4998 }
4999
5000 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
5001 {
5002 struct ixgbe_hw *hw = &adapter->hw;
5003 int err;
5004 u32 ctrl_ext;
5005
5006 ixgbe_get_hw_control(adapter);
5007 ixgbe_setup_gpie(adapter);
5008
5009 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5010 ixgbe_configure_msix(adapter);
5011 else
5012 ixgbe_configure_msi_and_legacy(adapter);
5013
5014 /* enable the optics for 82599 SFP+ fiber */
5015 if (hw->mac.ops.enable_tx_laser)
5016 hw->mac.ops.enable_tx_laser(hw);
5017
5018 if (hw->phy.ops.set_phy_power)
5019 hw->phy.ops.set_phy_power(hw, true);
5020
5021 smp_mb__before_atomic();
5022 clear_bit(__IXGBE_DOWN, &adapter->state);
5023 ixgbe_napi_enable_all(adapter);
5024
5025 if (ixgbe_is_sfp(hw)) {
5026 ixgbe_sfp_link_config(adapter);
5027 } else {
5028 err = ixgbe_non_sfp_link_config(hw);
5029 if (err)
5030 e_err(probe, "link_config FAILED %d\n", err);
5031 }
5032
5033 /* clear any pending interrupts, may auto mask */
5034 IXGBE_READ_REG(hw, IXGBE_EICR);
5035 ixgbe_irq_enable(adapter, true, true);
5036
5037 /*
5038 * If this adapter has a fan, check to see if we had a failure
5039 * before we enabled the interrupt.
5040 */
5041 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5042 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5043 if (esdp & IXGBE_ESDP_SDP1)
5044 e_crit(drv, "Fan has stopped, replace the adapter\n");
5045 }
5046
5047 /* bring the link up in the watchdog, this could race with our first
5048 * link up interrupt but shouldn't be a problem */
5049 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5050 adapter->link_check_timeout = jiffies;
5051 mod_timer(&adapter->service_timer, jiffies);
5052
5053 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5054 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5055 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5056 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
5057 }
5058
5059 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5060 {
5061 WARN_ON(in_interrupt());
5062 /* put off any impending NetWatchDogTimeout */
5063 adapter->netdev->trans_start = jiffies;
5064
5065 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
5066 usleep_range(1000, 2000);
5067 ixgbe_down(adapter);
5068 /*
5069 * If SR-IOV enabled then wait a bit before bringing the adapter
5070 * back up to give the VFs time to respond to the reset. The
5071 * two second wait is based upon the watchdog timer cycle in
5072 * the VF driver.
5073 */
5074 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5075 msleep(2000);
5076 ixgbe_up(adapter);
5077 clear_bit(__IXGBE_RESETTING, &adapter->state);
5078 }
5079
5080 void ixgbe_up(struct ixgbe_adapter *adapter)
5081 {
5082 /* hardware has been reset, we need to reload some things */
5083 ixgbe_configure(adapter);
5084
5085 ixgbe_up_complete(adapter);
5086 }
5087
5088 void ixgbe_reset(struct ixgbe_adapter *adapter)
5089 {
5090 struct ixgbe_hw *hw = &adapter->hw;
5091 struct net_device *netdev = adapter->netdev;
5092 int err;
5093
5094 if (ixgbe_removed(hw->hw_addr))
5095 return;
5096 /* lock SFP init bit to prevent race conditions with the watchdog */
5097 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5098 usleep_range(1000, 2000);
5099
5100 /* clear all SFP and link config related flags while holding SFP_INIT */
5101 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5102 IXGBE_FLAG2_SFP_NEEDS_RESET);
5103 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5104
5105 err = hw->mac.ops.init_hw(hw);
5106 switch (err) {
5107 case 0:
5108 case IXGBE_ERR_SFP_NOT_PRESENT:
5109 case IXGBE_ERR_SFP_NOT_SUPPORTED:
5110 break;
5111 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
5112 e_dev_err("master disable timed out\n");
5113 break;
5114 case IXGBE_ERR_EEPROM_VERSION:
5115 /* We are running on a pre-production device, log a warning */
5116 e_dev_warn("This device is a pre-production adapter/LOM. "
5117 "Please be aware there may be issues associated with "
5118 "your hardware. If you are experiencing problems "
5119 "please contact your Intel or hardware "
5120 "representative who provided you with this "
5121 "hardware.\n");
5122 break;
5123 default:
5124 e_dev_err("Hardware Error: %d\n", err);
5125 }
5126
5127 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5128
5129 /* flush entries out of MAC table */
5130 ixgbe_flush_sw_mac_table(adapter);
5131 __dev_uc_unsync(netdev, NULL);
5132
5133 /* do not flush user set addresses */
5134 ixgbe_mac_set_default_filter(adapter);
5135
5136 /* update SAN MAC vmdq pool selection */
5137 if (hw->mac.san_mac_rar_index)
5138 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
5139
5140 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
5141 ixgbe_ptp_reset(adapter);
5142
5143 if (hw->phy.ops.set_phy_power) {
5144 if (!netif_running(adapter->netdev) && !adapter->wol)
5145 hw->phy.ops.set_phy_power(hw, false);
5146 else
5147 hw->phy.ops.set_phy_power(hw, true);
5148 }
5149 }
5150
5151 /**
5152 * ixgbe_clean_tx_ring - Free Tx Buffers
5153 * @tx_ring: ring to be cleaned
5154 **/
5155 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
5156 {
5157 struct ixgbe_tx_buffer *tx_buffer_info;
5158 unsigned long size;
5159 u16 i;
5160
5161 /* ring already cleared, nothing to do */
5162 if (!tx_ring->tx_buffer_info)
5163 return;
5164
5165 /* Free all the Tx ring sk_buffs */
5166 for (i = 0; i < tx_ring->count; i++) {
5167 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5168 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
5169 }
5170
5171 netdev_tx_reset_queue(txring_txq(tx_ring));
5172
5173 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5174 memset(tx_ring->tx_buffer_info, 0, size);
5175
5176 /* Zero out the descriptor ring */
5177 memset(tx_ring->desc, 0, tx_ring->size);
5178
5179 tx_ring->next_to_use = 0;
5180 tx_ring->next_to_clean = 0;
5181 }
5182
5183 /**
5184 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
5185 * @adapter: board private structure
5186 **/
5187 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
5188 {
5189 int i;
5190
5191 for (i = 0; i < adapter->num_rx_queues; i++)
5192 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
5193 }
5194
5195 /**
5196 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
5197 * @adapter: board private structure
5198 **/
5199 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
5200 {
5201 int i;
5202
5203 for (i = 0; i < adapter->num_tx_queues; i++)
5204 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
5205 }
5206
5207 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5208 {
5209 struct hlist_node *node2;
5210 struct ixgbe_fdir_filter *filter;
5211
5212 spin_lock(&adapter->fdir_perfect_lock);
5213
5214 hlist_for_each_entry_safe(filter, node2,
5215 &adapter->fdir_filter_list, fdir_node) {
5216 hlist_del(&filter->fdir_node);
5217 kfree(filter);
5218 }
5219 adapter->fdir_filter_count = 0;
5220
5221 spin_unlock(&adapter->fdir_perfect_lock);
5222 }
5223
5224 void ixgbe_down(struct ixgbe_adapter *adapter)
5225 {
5226 struct net_device *netdev = adapter->netdev;
5227 struct ixgbe_hw *hw = &adapter->hw;
5228 struct net_device *upper;
5229 struct list_head *iter;
5230 int i;
5231
5232 /* signal that we are down to the interrupt handler */
5233 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5234 return; /* do nothing if already down */
5235
5236 /* disable receives */
5237 hw->mac.ops.disable_rx(hw);
5238
5239 /* disable all enabled rx queues */
5240 for (i = 0; i < adapter->num_rx_queues; i++)
5241 /* this call also flushes the previous write */
5242 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5243
5244 usleep_range(10000, 20000);
5245
5246 netif_tx_stop_all_queues(netdev);
5247
5248 /* call carrier off first to avoid false dev_watchdog timeouts */
5249 netif_carrier_off(netdev);
5250 netif_tx_disable(netdev);
5251
5252 /* disable any upper devices */
5253 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5254 if (netif_is_macvlan(upper)) {
5255 struct macvlan_dev *vlan = netdev_priv(upper);
5256
5257 if (vlan->fwd_priv) {
5258 netif_tx_stop_all_queues(upper);
5259 netif_carrier_off(upper);
5260 netif_tx_disable(upper);
5261 }
5262 }
5263 }
5264
5265 ixgbe_irq_disable(adapter);
5266
5267 ixgbe_napi_disable_all(adapter);
5268
5269 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5270 IXGBE_FLAG2_RESET_REQUESTED);
5271 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5272
5273 del_timer_sync(&adapter->service_timer);
5274
5275 if (adapter->num_vfs) {
5276 /* Clear EITR Select mapping */
5277 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
5278
5279 /* Mark all the VFs as inactive */
5280 for (i = 0 ; i < adapter->num_vfs; i++)
5281 adapter->vfinfo[i].clear_to_send = false;
5282
5283 /* ping all the active vfs to let them know we are going down */
5284 ixgbe_ping_all_vfs(adapter);
5285
5286 /* Disable all VFTE/VFRE TX/RX */
5287 ixgbe_disable_tx_rx(adapter);
5288 }
5289
5290 /* disable transmits in the hardware now that interrupts are off */
5291 for (i = 0; i < adapter->num_tx_queues; i++) {
5292 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
5293 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5294 }
5295
5296 /* Disable the Tx DMA engine on 82599 and later MAC */
5297 switch (hw->mac.type) {
5298 case ixgbe_mac_82599EB:
5299 case ixgbe_mac_X540:
5300 case ixgbe_mac_X550:
5301 case ixgbe_mac_X550EM_x:
5302 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
5303 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5304 ~IXGBE_DMATXCTL_TE));
5305 break;
5306 default:
5307 break;
5308 }
5309
5310 if (!pci_channel_offline(adapter->pdev))
5311 ixgbe_reset(adapter);
5312
5313 /* power down the optics for 82599 SFP+ fiber */
5314 if (hw->mac.ops.disable_tx_laser)
5315 hw->mac.ops.disable_tx_laser(hw);
5316
5317 ixgbe_clean_all_tx_rings(adapter);
5318 ixgbe_clean_all_rx_rings(adapter);
5319 }
5320
5321 /**
5322 * ixgbe_tx_timeout - Respond to a Tx Hang
5323 * @netdev: network interface device structure
5324 **/
5325 static void ixgbe_tx_timeout(struct net_device *netdev)
5326 {
5327 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5328
5329 /* Do the reset outside of interrupt context */
5330 ixgbe_tx_timeout_reset(adapter);
5331 }
5332
5333 /**
5334 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5335 * @adapter: board private structure to initialize
5336 *
5337 * ixgbe_sw_init initializes the Adapter private data structure.
5338 * Fields are initialized based on PCI device information and
5339 * OS network device settings (MTU size).
5340 **/
5341 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
5342 {
5343 struct ixgbe_hw *hw = &adapter->hw;
5344 struct pci_dev *pdev = adapter->pdev;
5345 unsigned int rss, fdir;
5346 u32 fwsm;
5347 #ifdef CONFIG_IXGBE_DCB
5348 int j;
5349 struct tc_configuration *tc;
5350 #endif
5351
5352 /* PCI config space info */
5353
5354 hw->vendor_id = pdev->vendor;
5355 hw->device_id = pdev->device;
5356 hw->revision_id = pdev->revision;
5357 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5358 hw->subsystem_device_id = pdev->subsystem_device;
5359
5360 /* Set common capability flags and settings */
5361 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
5362 adapter->ring_feature[RING_F_RSS].limit = rss;
5363 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5364 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5365 adapter->atr_sample_rate = 20;
5366 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5367 adapter->ring_feature[RING_F_FDIR].limit = fdir;
5368 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5369 #ifdef CONFIG_IXGBE_DCA
5370 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5371 #endif
5372 #ifdef IXGBE_FCOE
5373 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5374 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5375 #ifdef CONFIG_IXGBE_DCB
5376 /* Default traffic class to use for FCoE */
5377 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5378 #endif /* CONFIG_IXGBE_DCB */
5379 #endif /* IXGBE_FCOE */
5380
5381 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5382 hw->mac.num_rar_entries,
5383 GFP_ATOMIC);
5384
5385 /* Set MAC specific capability flags and exceptions */
5386 switch (hw->mac.type) {
5387 case ixgbe_mac_82598EB:
5388 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5389
5390 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5391 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5392
5393 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
5394 adapter->ring_feature[RING_F_FDIR].limit = 0;
5395 adapter->atr_sample_rate = 0;
5396 adapter->fdir_pballoc = 0;
5397 #ifdef IXGBE_FCOE
5398 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5399 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5400 #ifdef CONFIG_IXGBE_DCB
5401 adapter->fcoe.up = 0;
5402 #endif /* IXGBE_DCB */
5403 #endif /* IXGBE_FCOE */
5404 break;
5405 case ixgbe_mac_82599EB:
5406 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5407 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5408 break;
5409 case ixgbe_mac_X540:
5410 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
5411 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5412 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5413 break;
5414 case ixgbe_mac_X550EM_x:
5415 case ixgbe_mac_X550:
5416 #ifdef CONFIG_IXGBE_DCA
5417 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
5418 #endif
5419 #ifdef CONFIG_IXGBE_VXLAN
5420 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
5421 #endif
5422 break;
5423 default:
5424 break;
5425 }
5426
5427 #ifdef IXGBE_FCOE
5428 /* FCoE support exists, always init the FCoE lock */
5429 spin_lock_init(&adapter->fcoe.lock);
5430
5431 #endif
5432 /* n-tuple support exists, always init our spinlock */
5433 spin_lock_init(&adapter->fdir_perfect_lock);
5434
5435 #ifdef CONFIG_IXGBE_DCB
5436 switch (hw->mac.type) {
5437 case ixgbe_mac_X540:
5438 case ixgbe_mac_X550:
5439 case ixgbe_mac_X550EM_x:
5440 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5441 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5442 break;
5443 default:
5444 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5445 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5446 break;
5447 }
5448
5449 /* Configure DCB traffic classes */
5450 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5451 tc = &adapter->dcb_cfg.tc_config[j];
5452 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5453 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5454 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5455 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5456 tc->dcb_pfc = pfc_disabled;
5457 }
5458
5459 /* Initialize default user to priority mapping, UPx->TC0 */
5460 tc = &adapter->dcb_cfg.tc_config[0];
5461 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5462 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5463
5464 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5465 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5466 adapter->dcb_cfg.pfc_mode_enable = false;
5467 adapter->dcb_set_bitmap = 0x00;
5468 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5469 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5470 sizeof(adapter->temp_dcb_cfg));
5471
5472 #endif
5473
5474 /* default flow control settings */
5475 hw->fc.requested_mode = ixgbe_fc_full;
5476 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5477 ixgbe_pbthresh_setup(adapter);
5478 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5479 hw->fc.send_xon = true;
5480 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
5481
5482 #ifdef CONFIG_PCI_IOV
5483 if (max_vfs > 0)
5484 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5485
5486 /* assign number of SR-IOV VFs */
5487 if (hw->mac.type != ixgbe_mac_82598EB) {
5488 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
5489 adapter->num_vfs = 0;
5490 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5491 } else {
5492 adapter->num_vfs = max_vfs;
5493 }
5494 }
5495 #endif /* CONFIG_PCI_IOV */
5496
5497 /* enable itr by default in dynamic mode */
5498 adapter->rx_itr_setting = 1;
5499 adapter->tx_itr_setting = 1;
5500
5501 /* set default ring sizes */
5502 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5503 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5504
5505 /* set default work limits */
5506 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5507
5508 /* initialize eeprom parameters */
5509 if (ixgbe_init_eeprom_params_generic(hw)) {
5510 e_dev_err("EEPROM initialization failed\n");
5511 return -EIO;
5512 }
5513
5514 /* PF holds first pool slot */
5515 set_bit(0, &adapter->fwd_bitmask);
5516 set_bit(__IXGBE_DOWN, &adapter->state);
5517
5518 return 0;
5519 }
5520
5521 /**
5522 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5523 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5524 *
5525 * Return 0 on success, negative on failure
5526 **/
5527 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5528 {
5529 struct device *dev = tx_ring->dev;
5530 int orig_node = dev_to_node(dev);
5531 int ring_node = -1;
5532 int size;
5533
5534 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5535
5536 if (tx_ring->q_vector)
5537 ring_node = tx_ring->q_vector->numa_node;
5538
5539 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
5540 if (!tx_ring->tx_buffer_info)
5541 tx_ring->tx_buffer_info = vzalloc(size);
5542 if (!tx_ring->tx_buffer_info)
5543 goto err;
5544
5545 u64_stats_init(&tx_ring->syncp);
5546
5547 /* round up to nearest 4K */
5548 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5549 tx_ring->size = ALIGN(tx_ring->size, 4096);
5550
5551 set_dev_node(dev, ring_node);
5552 tx_ring->desc = dma_alloc_coherent(dev,
5553 tx_ring->size,
5554 &tx_ring->dma,
5555 GFP_KERNEL);
5556 set_dev_node(dev, orig_node);
5557 if (!tx_ring->desc)
5558 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5559 &tx_ring->dma, GFP_KERNEL);
5560 if (!tx_ring->desc)
5561 goto err;
5562
5563 tx_ring->next_to_use = 0;
5564 tx_ring->next_to_clean = 0;
5565 return 0;
5566
5567 err:
5568 vfree(tx_ring->tx_buffer_info);
5569 tx_ring->tx_buffer_info = NULL;
5570 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5571 return -ENOMEM;
5572 }
5573
5574 /**
5575 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5576 * @adapter: board private structure
5577 *
5578 * If this function returns with an error, then it's possible one or
5579 * more of the rings is populated (while the rest are not). It is the
5580 * callers duty to clean those orphaned rings.
5581 *
5582 * Return 0 on success, negative on failure
5583 **/
5584 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5585 {
5586 int i, err = 0;
5587
5588 for (i = 0; i < adapter->num_tx_queues; i++) {
5589 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5590 if (!err)
5591 continue;
5592
5593 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5594 goto err_setup_tx;
5595 }
5596
5597 return 0;
5598 err_setup_tx:
5599 /* rewind the index freeing the rings as we go */
5600 while (i--)
5601 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5602 return err;
5603 }
5604
5605 /**
5606 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5607 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5608 *
5609 * Returns 0 on success, negative on failure
5610 **/
5611 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5612 {
5613 struct device *dev = rx_ring->dev;
5614 int orig_node = dev_to_node(dev);
5615 int ring_node = -1;
5616 int size;
5617
5618 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5619
5620 if (rx_ring->q_vector)
5621 ring_node = rx_ring->q_vector->numa_node;
5622
5623 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
5624 if (!rx_ring->rx_buffer_info)
5625 rx_ring->rx_buffer_info = vzalloc(size);
5626 if (!rx_ring->rx_buffer_info)
5627 goto err;
5628
5629 u64_stats_init(&rx_ring->syncp);
5630
5631 /* Round up to nearest 4K */
5632 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5633 rx_ring->size = ALIGN(rx_ring->size, 4096);
5634
5635 set_dev_node(dev, ring_node);
5636 rx_ring->desc = dma_alloc_coherent(dev,
5637 rx_ring->size,
5638 &rx_ring->dma,
5639 GFP_KERNEL);
5640 set_dev_node(dev, orig_node);
5641 if (!rx_ring->desc)
5642 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5643 &rx_ring->dma, GFP_KERNEL);
5644 if (!rx_ring->desc)
5645 goto err;
5646
5647 rx_ring->next_to_clean = 0;
5648 rx_ring->next_to_use = 0;
5649
5650 return 0;
5651 err:
5652 vfree(rx_ring->rx_buffer_info);
5653 rx_ring->rx_buffer_info = NULL;
5654 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5655 return -ENOMEM;
5656 }
5657
5658 /**
5659 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5660 * @adapter: board private structure
5661 *
5662 * If this function returns with an error, then it's possible one or
5663 * more of the rings is populated (while the rest are not). It is the
5664 * callers duty to clean those orphaned rings.
5665 *
5666 * Return 0 on success, negative on failure
5667 **/
5668 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5669 {
5670 int i, err = 0;
5671
5672 for (i = 0; i < adapter->num_rx_queues; i++) {
5673 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5674 if (!err)
5675 continue;
5676
5677 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5678 goto err_setup_rx;
5679 }
5680
5681 #ifdef IXGBE_FCOE
5682 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5683 if (!err)
5684 #endif
5685 return 0;
5686 err_setup_rx:
5687 /* rewind the index freeing the rings as we go */
5688 while (i--)
5689 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5690 return err;
5691 }
5692
5693 /**
5694 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5695 * @tx_ring: Tx descriptor ring for a specific queue
5696 *
5697 * Free all transmit software resources
5698 **/
5699 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5700 {
5701 ixgbe_clean_tx_ring(tx_ring);
5702
5703 vfree(tx_ring->tx_buffer_info);
5704 tx_ring->tx_buffer_info = NULL;
5705
5706 /* if not set, then don't free */
5707 if (!tx_ring->desc)
5708 return;
5709
5710 dma_free_coherent(tx_ring->dev, tx_ring->size,
5711 tx_ring->desc, tx_ring->dma);
5712
5713 tx_ring->desc = NULL;
5714 }
5715
5716 /**
5717 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5718 * @adapter: board private structure
5719 *
5720 * Free all transmit software resources
5721 **/
5722 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5723 {
5724 int i;
5725
5726 for (i = 0; i < adapter->num_tx_queues; i++)
5727 if (adapter->tx_ring[i]->desc)
5728 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5729 }
5730
5731 /**
5732 * ixgbe_free_rx_resources - Free Rx Resources
5733 * @rx_ring: ring to clean the resources from
5734 *
5735 * Free all receive software resources
5736 **/
5737 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5738 {
5739 ixgbe_clean_rx_ring(rx_ring);
5740
5741 vfree(rx_ring->rx_buffer_info);
5742 rx_ring->rx_buffer_info = NULL;
5743
5744 /* if not set, then don't free */
5745 if (!rx_ring->desc)
5746 return;
5747
5748 dma_free_coherent(rx_ring->dev, rx_ring->size,
5749 rx_ring->desc, rx_ring->dma);
5750
5751 rx_ring->desc = NULL;
5752 }
5753
5754 /**
5755 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5756 * @adapter: board private structure
5757 *
5758 * Free all receive software resources
5759 **/
5760 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5761 {
5762 int i;
5763
5764 #ifdef IXGBE_FCOE
5765 ixgbe_free_fcoe_ddp_resources(adapter);
5766
5767 #endif
5768 for (i = 0; i < adapter->num_rx_queues; i++)
5769 if (adapter->rx_ring[i]->desc)
5770 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5771 }
5772
5773 /**
5774 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5775 * @netdev: network interface device structure
5776 * @new_mtu: new value for maximum frame size
5777 *
5778 * Returns 0 on success, negative on failure
5779 **/
5780 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5781 {
5782 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5783 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5784
5785 /* MTU < 68 is an error and causes problems on some kernels */
5786 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5787 return -EINVAL;
5788
5789 /*
5790 * For 82599EB we cannot allow legacy VFs to enable their receive
5791 * paths when MTU greater than 1500 is configured. So display a
5792 * warning that legacy VFs will be disabled.
5793 */
5794 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5795 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
5796 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
5797 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
5798
5799 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5800
5801 /* must set new MTU before calling down or up */
5802 netdev->mtu = new_mtu;
5803
5804 if (netif_running(netdev))
5805 ixgbe_reinit_locked(adapter);
5806
5807 return 0;
5808 }
5809
5810 /**
5811 * ixgbe_open - Called when a network interface is made active
5812 * @netdev: network interface device structure
5813 *
5814 * Returns 0 on success, negative value on failure
5815 *
5816 * The open entry point is called when a network interface is made
5817 * active by the system (IFF_UP). At this point all resources needed
5818 * for transmit and receive operations are allocated, the interrupt
5819 * handler is registered with the OS, the watchdog timer is started,
5820 * and the stack is notified that the interface is ready.
5821 **/
5822 static int ixgbe_open(struct net_device *netdev)
5823 {
5824 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5825 struct ixgbe_hw *hw = &adapter->hw;
5826 int err, queues;
5827
5828 /* disallow open during test */
5829 if (test_bit(__IXGBE_TESTING, &adapter->state))
5830 return -EBUSY;
5831
5832 netif_carrier_off(netdev);
5833
5834 /* allocate transmit descriptors */
5835 err = ixgbe_setup_all_tx_resources(adapter);
5836 if (err)
5837 goto err_setup_tx;
5838
5839 /* allocate receive descriptors */
5840 err = ixgbe_setup_all_rx_resources(adapter);
5841 if (err)
5842 goto err_setup_rx;
5843
5844 ixgbe_configure(adapter);
5845
5846 err = ixgbe_request_irq(adapter);
5847 if (err)
5848 goto err_req_irq;
5849
5850 /* Notify the stack of the actual queue counts. */
5851 if (adapter->num_rx_pools > 1)
5852 queues = adapter->num_rx_queues_per_pool;
5853 else
5854 queues = adapter->num_tx_queues;
5855
5856 err = netif_set_real_num_tx_queues(netdev, queues);
5857 if (err)
5858 goto err_set_queues;
5859
5860 if (adapter->num_rx_pools > 1 &&
5861 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5862 queues = IXGBE_MAX_L2A_QUEUES;
5863 else
5864 queues = adapter->num_rx_queues;
5865 err = netif_set_real_num_rx_queues(netdev, queues);
5866 if (err)
5867 goto err_set_queues;
5868
5869 ixgbe_ptp_init(adapter);
5870
5871 ixgbe_up_complete(adapter);
5872
5873 ixgbe_clear_vxlan_port(adapter);
5874 #ifdef CONFIG_IXGBE_VXLAN
5875 vxlan_get_rx_port(netdev);
5876 #endif
5877
5878 return 0;
5879
5880 err_set_queues:
5881 ixgbe_free_irq(adapter);
5882 err_req_irq:
5883 ixgbe_free_all_rx_resources(adapter);
5884 if (hw->phy.ops.set_phy_power && !adapter->wol)
5885 hw->phy.ops.set_phy_power(&adapter->hw, false);
5886 err_setup_rx:
5887 ixgbe_free_all_tx_resources(adapter);
5888 err_setup_tx:
5889 ixgbe_reset(adapter);
5890
5891 return err;
5892 }
5893
5894 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5895 {
5896 ixgbe_ptp_suspend(adapter);
5897
5898 if (adapter->hw.phy.ops.enter_lplu) {
5899 adapter->hw.phy.reset_disable = true;
5900 ixgbe_down(adapter);
5901 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
5902 adapter->hw.phy.reset_disable = false;
5903 } else {
5904 ixgbe_down(adapter);
5905 }
5906
5907 ixgbe_free_irq(adapter);
5908
5909 ixgbe_free_all_tx_resources(adapter);
5910 ixgbe_free_all_rx_resources(adapter);
5911 }
5912
5913 /**
5914 * ixgbe_close - Disables a network interface
5915 * @netdev: network interface device structure
5916 *
5917 * Returns 0, this is not allowed to fail
5918 *
5919 * The close entry point is called when an interface is de-activated
5920 * by the OS. The hardware is still under the drivers control, but
5921 * needs to be disabled. A global MAC reset is issued to stop the
5922 * hardware, and all transmit and receive resources are freed.
5923 **/
5924 static int ixgbe_close(struct net_device *netdev)
5925 {
5926 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5927
5928 ixgbe_ptp_stop(adapter);
5929
5930 ixgbe_close_suspend(adapter);
5931
5932 ixgbe_fdir_filter_exit(adapter);
5933
5934 ixgbe_release_hw_control(adapter);
5935
5936 return 0;
5937 }
5938
5939 #ifdef CONFIG_PM
5940 static int ixgbe_resume(struct pci_dev *pdev)
5941 {
5942 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5943 struct net_device *netdev = adapter->netdev;
5944 u32 err;
5945
5946 adapter->hw.hw_addr = adapter->io_addr;
5947 pci_set_power_state(pdev, PCI_D0);
5948 pci_restore_state(pdev);
5949 /*
5950 * pci_restore_state clears dev->state_saved so call
5951 * pci_save_state to restore it.
5952 */
5953 pci_save_state(pdev);
5954
5955 err = pci_enable_device_mem(pdev);
5956 if (err) {
5957 e_dev_err("Cannot enable PCI device from suspend\n");
5958 return err;
5959 }
5960 smp_mb__before_atomic();
5961 clear_bit(__IXGBE_DISABLED, &adapter->state);
5962 pci_set_master(pdev);
5963
5964 pci_wake_from_d3(pdev, false);
5965
5966 ixgbe_reset(adapter);
5967
5968 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5969
5970 rtnl_lock();
5971 err = ixgbe_init_interrupt_scheme(adapter);
5972 if (!err && netif_running(netdev))
5973 err = ixgbe_open(netdev);
5974
5975 rtnl_unlock();
5976
5977 if (err)
5978 return err;
5979
5980 netif_device_attach(netdev);
5981
5982 return 0;
5983 }
5984 #endif /* CONFIG_PM */
5985
5986 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5987 {
5988 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5989 struct net_device *netdev = adapter->netdev;
5990 struct ixgbe_hw *hw = &adapter->hw;
5991 u32 ctrl, fctrl;
5992 u32 wufc = adapter->wol;
5993 #ifdef CONFIG_PM
5994 int retval = 0;
5995 #endif
5996
5997 netif_device_detach(netdev);
5998
5999 rtnl_lock();
6000 if (netif_running(netdev))
6001 ixgbe_close_suspend(adapter);
6002 rtnl_unlock();
6003
6004 ixgbe_clear_interrupt_scheme(adapter);
6005
6006 #ifdef CONFIG_PM
6007 retval = pci_save_state(pdev);
6008 if (retval)
6009 return retval;
6010
6011 #endif
6012 if (hw->mac.ops.stop_link_on_d3)
6013 hw->mac.ops.stop_link_on_d3(hw);
6014
6015 if (wufc) {
6016 ixgbe_set_rx_mode(netdev);
6017
6018 /* enable the optics for 82599 SFP+ fiber as we can WoL */
6019 if (hw->mac.ops.enable_tx_laser)
6020 hw->mac.ops.enable_tx_laser(hw);
6021
6022 /* turn on all-multi mode if wake on multicast is enabled */
6023 if (wufc & IXGBE_WUFC_MC) {
6024 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6025 fctrl |= IXGBE_FCTRL_MPE;
6026 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
6027 }
6028
6029 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
6030 ctrl |= IXGBE_CTRL_GIO_DIS;
6031 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
6032
6033 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
6034 } else {
6035 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
6036 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
6037 }
6038
6039 switch (hw->mac.type) {
6040 case ixgbe_mac_82598EB:
6041 pci_wake_from_d3(pdev, false);
6042 break;
6043 case ixgbe_mac_82599EB:
6044 case ixgbe_mac_X540:
6045 case ixgbe_mac_X550:
6046 case ixgbe_mac_X550EM_x:
6047 pci_wake_from_d3(pdev, !!wufc);
6048 break;
6049 default:
6050 break;
6051 }
6052
6053 *enable_wake = !!wufc;
6054 if (hw->phy.ops.set_phy_power && !*enable_wake)
6055 hw->phy.ops.set_phy_power(hw, false);
6056
6057 ixgbe_release_hw_control(adapter);
6058
6059 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6060 pci_disable_device(pdev);
6061
6062 return 0;
6063 }
6064
6065 #ifdef CONFIG_PM
6066 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
6067 {
6068 int retval;
6069 bool wake;
6070
6071 retval = __ixgbe_shutdown(pdev, &wake);
6072 if (retval)
6073 return retval;
6074
6075 if (wake) {
6076 pci_prepare_to_sleep(pdev);
6077 } else {
6078 pci_wake_from_d3(pdev, false);
6079 pci_set_power_state(pdev, PCI_D3hot);
6080 }
6081
6082 return 0;
6083 }
6084 #endif /* CONFIG_PM */
6085
6086 static void ixgbe_shutdown(struct pci_dev *pdev)
6087 {
6088 bool wake;
6089
6090 __ixgbe_shutdown(pdev, &wake);
6091
6092 if (system_state == SYSTEM_POWER_OFF) {
6093 pci_wake_from_d3(pdev, wake);
6094 pci_set_power_state(pdev, PCI_D3hot);
6095 }
6096 }
6097
6098 /**
6099 * ixgbe_update_stats - Update the board statistics counters.
6100 * @adapter: board private structure
6101 **/
6102 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6103 {
6104 struct net_device *netdev = adapter->netdev;
6105 struct ixgbe_hw *hw = &adapter->hw;
6106 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6107 u64 total_mpc = 0;
6108 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
6109 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6110 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
6111 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
6112
6113 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6114 test_bit(__IXGBE_RESETTING, &adapter->state))
6115 return;
6116
6117 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
6118 u64 rsc_count = 0;
6119 u64 rsc_flush = 0;
6120 for (i = 0; i < adapter->num_rx_queues; i++) {
6121 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6122 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
6123 }
6124 adapter->rsc_total_count = rsc_count;
6125 adapter->rsc_total_flush = rsc_flush;
6126 }
6127
6128 for (i = 0; i < adapter->num_rx_queues; i++) {
6129 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6130 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6131 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6132 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
6133 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
6134 bytes += rx_ring->stats.bytes;
6135 packets += rx_ring->stats.packets;
6136 }
6137 adapter->non_eop_descs = non_eop_descs;
6138 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6139 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
6140 adapter->hw_csum_rx_error = hw_csum_rx_error;
6141 netdev->stats.rx_bytes = bytes;
6142 netdev->stats.rx_packets = packets;
6143
6144 bytes = 0;
6145 packets = 0;
6146 /* gather some stats to the adapter struct that are per queue */
6147 for (i = 0; i < adapter->num_tx_queues; i++) {
6148 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6149 restart_queue += tx_ring->tx_stats.restart_queue;
6150 tx_busy += tx_ring->tx_stats.tx_busy;
6151 bytes += tx_ring->stats.bytes;
6152 packets += tx_ring->stats.packets;
6153 }
6154 adapter->restart_queue = restart_queue;
6155 adapter->tx_busy = tx_busy;
6156 netdev->stats.tx_bytes = bytes;
6157 netdev->stats.tx_packets = packets;
6158
6159 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6160
6161 /* 8 register reads */
6162 for (i = 0; i < 8; i++) {
6163 /* for packet buffers not used, the register should read 0 */
6164 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6165 missed_rx += mpc;
6166 hwstats->mpc[i] += mpc;
6167 total_mpc += hwstats->mpc[i];
6168 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6169 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6170 switch (hw->mac.type) {
6171 case ixgbe_mac_82598EB:
6172 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6173 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6174 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
6175 hwstats->pxonrxc[i] +=
6176 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
6177 break;
6178 case ixgbe_mac_82599EB:
6179 case ixgbe_mac_X540:
6180 case ixgbe_mac_X550:
6181 case ixgbe_mac_X550EM_x:
6182 hwstats->pxonrxc[i] +=
6183 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
6184 break;
6185 default:
6186 break;
6187 }
6188 }
6189
6190 /*16 register reads */
6191 for (i = 0; i < 16; i++) {
6192 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6193 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6194 if ((hw->mac.type == ixgbe_mac_82599EB) ||
6195 (hw->mac.type == ixgbe_mac_X540) ||
6196 (hw->mac.type == ixgbe_mac_X550) ||
6197 (hw->mac.type == ixgbe_mac_X550EM_x)) {
6198 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6199 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6200 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6201 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6202 }
6203 }
6204
6205 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6206 /* work around hardware counting issue */
6207 hwstats->gprc -= missed_rx;
6208
6209 ixgbe_update_xoff_received(adapter);
6210
6211 /* 82598 hardware only has a 32 bit counter in the high register */
6212 switch (hw->mac.type) {
6213 case ixgbe_mac_82598EB:
6214 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
6215 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6216 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6217 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6218 break;
6219 case ixgbe_mac_X540:
6220 case ixgbe_mac_X550:
6221 case ixgbe_mac_X550EM_x:
6222 /* OS2BMC stats are X540 and later */
6223 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6224 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6225 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6226 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6227 case ixgbe_mac_82599EB:
6228 for (i = 0; i < 16; i++)
6229 adapter->hw_rx_no_dma_resources +=
6230 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
6231 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
6232 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
6233 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
6234 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
6235 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
6236 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
6237 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
6238 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6239 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6240 #ifdef IXGBE_FCOE
6241 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6242 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6243 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6244 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6245 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6246 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6247 /* Add up per cpu counters for total ddp aloc fail */
6248 if (adapter->fcoe.ddp_pool) {
6249 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6250 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6251 unsigned int cpu;
6252 u64 noddp = 0, noddp_ext_buff = 0;
6253 for_each_possible_cpu(cpu) {
6254 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6255 noddp += ddp_pool->noddp;
6256 noddp_ext_buff += ddp_pool->noddp_ext_buff;
6257 }
6258 hwstats->fcoe_noddp = noddp;
6259 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
6260 }
6261 #endif /* IXGBE_FCOE */
6262 break;
6263 default:
6264 break;
6265 }
6266 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
6267 hwstats->bprc += bprc;
6268 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
6269 if (hw->mac.type == ixgbe_mac_82598EB)
6270 hwstats->mprc -= bprc;
6271 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6272 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6273 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6274 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6275 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6276 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6277 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6278 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6279 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
6280 hwstats->lxontxc += lxon;
6281 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
6282 hwstats->lxofftxc += lxoff;
6283 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6284 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6285 /*
6286 * 82598 errata - tx of flow control packets is included in tx counters
6287 */
6288 xon_off_tot = lxon + lxoff;
6289 hwstats->gptc -= xon_off_tot;
6290 hwstats->mptc -= xon_off_tot;
6291 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6292 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6293 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6294 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6295 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6296 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6297 hwstats->ptc64 -= xon_off_tot;
6298 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6299 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6300 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6301 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6302 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6303 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
6304
6305 /* Fill out the OS statistics structure */
6306 netdev->stats.multicast = hwstats->mprc;
6307
6308 /* Rx Errors */
6309 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
6310 netdev->stats.rx_dropped = 0;
6311 netdev->stats.rx_length_errors = hwstats->rlec;
6312 netdev->stats.rx_crc_errors = hwstats->crcerrs;
6313 netdev->stats.rx_missed_errors = total_mpc;
6314 }
6315
6316 /**
6317 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
6318 * @adapter: pointer to the device adapter structure
6319 **/
6320 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
6321 {
6322 struct ixgbe_hw *hw = &adapter->hw;
6323 int i;
6324
6325 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6326 return;
6327
6328 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
6329
6330 /* if interface is down do nothing */
6331 if (test_bit(__IXGBE_DOWN, &adapter->state))
6332 return;
6333
6334 /* do nothing if we are not using signature filters */
6335 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6336 return;
6337
6338 adapter->fdir_overflow++;
6339
6340 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6341 for (i = 0; i < adapter->num_tx_queues; i++)
6342 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
6343 &(adapter->tx_ring[i]->state));
6344 /* re-enable flow director interrupts */
6345 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
6346 } else {
6347 e_err(probe, "failed to finish FDIR re-initialization, "
6348 "ignored adding FDIR ATR filters\n");
6349 }
6350 }
6351
6352 /**
6353 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
6354 * @adapter: pointer to the device adapter structure
6355 *
6356 * This function serves two purposes. First it strobes the interrupt lines
6357 * in order to make certain interrupts are occurring. Secondly it sets the
6358 * bits needed to check for TX hangs. As a result we should immediately
6359 * determine if a hang has occurred.
6360 */
6361 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
6362 {
6363 struct ixgbe_hw *hw = &adapter->hw;
6364 u64 eics = 0;
6365 int i;
6366
6367 /* If we're down, removing or resetting, just bail */
6368 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6369 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6370 test_bit(__IXGBE_RESETTING, &adapter->state))
6371 return;
6372
6373 /* Force detection of hung controller */
6374 if (netif_carrier_ok(adapter->netdev)) {
6375 for (i = 0; i < adapter->num_tx_queues; i++)
6376 set_check_for_tx_hang(adapter->tx_ring[i]);
6377 }
6378
6379 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6380 /*
6381 * for legacy and MSI interrupts don't set any bits
6382 * that are enabled for EIAM, because this operation
6383 * would set *both* EIMS and EICS for any bit in EIAM
6384 */
6385 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6386 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
6387 } else {
6388 /* get one bit for every active tx/rx interrupt vector */
6389 for (i = 0; i < adapter->num_q_vectors; i++) {
6390 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6391 if (qv->rx.ring || qv->tx.ring)
6392 eics |= ((u64)1 << i);
6393 }
6394 }
6395
6396 /* Cause software interrupt to ensure rings are cleaned */
6397 ixgbe_irq_rearm_queues(adapter, eics);
6398 }
6399
6400 /**
6401 * ixgbe_watchdog_update_link - update the link status
6402 * @adapter: pointer to the device adapter structure
6403 * @link_speed: pointer to a u32 to store the link_speed
6404 **/
6405 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
6406 {
6407 struct ixgbe_hw *hw = &adapter->hw;
6408 u32 link_speed = adapter->link_speed;
6409 bool link_up = adapter->link_up;
6410 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
6411
6412 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6413 return;
6414
6415 if (hw->mac.ops.check_link) {
6416 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6417 } else {
6418 /* always assume link is up, if no check link function */
6419 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6420 link_up = true;
6421 }
6422
6423 if (adapter->ixgbe_ieee_pfc)
6424 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6425
6426 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
6427 hw->mac.ops.fc_enable(hw);
6428 ixgbe_set_rx_drop_en(adapter);
6429 }
6430
6431 if (link_up ||
6432 time_after(jiffies, (adapter->link_check_timeout +
6433 IXGBE_TRY_LINK_TIMEOUT))) {
6434 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6435 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6436 IXGBE_WRITE_FLUSH(hw);
6437 }
6438
6439 adapter->link_up = link_up;
6440 adapter->link_speed = link_speed;
6441 }
6442
6443 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6444 {
6445 #ifdef CONFIG_IXGBE_DCB
6446 struct net_device *netdev = adapter->netdev;
6447 struct dcb_app app = {
6448 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6449 .protocol = 0,
6450 };
6451 u8 up = 0;
6452
6453 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6454 up = dcb_ieee_getapp_mask(netdev, &app);
6455
6456 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6457 #endif
6458 }
6459
6460 /**
6461 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6462 * print link up message
6463 * @adapter: pointer to the device adapter structure
6464 **/
6465 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
6466 {
6467 struct net_device *netdev = adapter->netdev;
6468 struct ixgbe_hw *hw = &adapter->hw;
6469 struct net_device *upper;
6470 struct list_head *iter;
6471 u32 link_speed = adapter->link_speed;
6472 const char *speed_str;
6473 bool flow_rx, flow_tx;
6474
6475 /* only continue if link was previously down */
6476 if (netif_carrier_ok(netdev))
6477 return;
6478
6479 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
6480
6481 switch (hw->mac.type) {
6482 case ixgbe_mac_82598EB: {
6483 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6484 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6485 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6486 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6487 }
6488 break;
6489 case ixgbe_mac_X540:
6490 case ixgbe_mac_X550:
6491 case ixgbe_mac_X550EM_x:
6492 case ixgbe_mac_82599EB: {
6493 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6494 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6495 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6496 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6497 }
6498 break;
6499 default:
6500 flow_tx = false;
6501 flow_rx = false;
6502 break;
6503 }
6504
6505 adapter->last_rx_ptp_check = jiffies;
6506
6507 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6508 ixgbe_ptp_start_cyclecounter(adapter);
6509
6510 switch (link_speed) {
6511 case IXGBE_LINK_SPEED_10GB_FULL:
6512 speed_str = "10 Gbps";
6513 break;
6514 case IXGBE_LINK_SPEED_2_5GB_FULL:
6515 speed_str = "2.5 Gbps";
6516 break;
6517 case IXGBE_LINK_SPEED_1GB_FULL:
6518 speed_str = "1 Gbps";
6519 break;
6520 case IXGBE_LINK_SPEED_100_FULL:
6521 speed_str = "100 Mbps";
6522 break;
6523 default:
6524 speed_str = "unknown speed";
6525 break;
6526 }
6527 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
6528 ((flow_rx && flow_tx) ? "RX/TX" :
6529 (flow_rx ? "RX" :
6530 (flow_tx ? "TX" : "None"))));
6531
6532 netif_carrier_on(netdev);
6533 ixgbe_check_vf_rate_limit(adapter);
6534
6535 /* enable transmits */
6536 netif_tx_wake_all_queues(adapter->netdev);
6537
6538 /* enable any upper devices */
6539 rtnl_lock();
6540 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6541 if (netif_is_macvlan(upper)) {
6542 struct macvlan_dev *vlan = netdev_priv(upper);
6543
6544 if (vlan->fwd_priv)
6545 netif_tx_wake_all_queues(upper);
6546 }
6547 }
6548 rtnl_unlock();
6549
6550 /* update the default user priority for VFs */
6551 ixgbe_update_default_up(adapter);
6552
6553 /* ping all the active vfs to let them know link has changed */
6554 ixgbe_ping_all_vfs(adapter);
6555 }
6556
6557 /**
6558 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6559 * print link down message
6560 * @adapter: pointer to the adapter structure
6561 **/
6562 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
6563 {
6564 struct net_device *netdev = adapter->netdev;
6565 struct ixgbe_hw *hw = &adapter->hw;
6566
6567 adapter->link_up = false;
6568 adapter->link_speed = 0;
6569
6570 /* only continue if link was up previously */
6571 if (!netif_carrier_ok(netdev))
6572 return;
6573
6574 /* poll for SFP+ cable when link is down */
6575 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6576 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6577
6578 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6579 ixgbe_ptp_start_cyclecounter(adapter);
6580
6581 e_info(drv, "NIC Link is Down\n");
6582 netif_carrier_off(netdev);
6583
6584 /* ping all the active vfs to let them know link has changed */
6585 ixgbe_ping_all_vfs(adapter);
6586 }
6587
6588 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6589 {
6590 int i;
6591
6592 for (i = 0; i < adapter->num_tx_queues; i++) {
6593 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6594
6595 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6596 return true;
6597 }
6598
6599 return false;
6600 }
6601
6602 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6603 {
6604 struct ixgbe_hw *hw = &adapter->hw;
6605 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6606 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6607
6608 int i, j;
6609
6610 if (!adapter->num_vfs)
6611 return false;
6612
6613 /* resetting the PF is only needed for MAC before X550 */
6614 if (hw->mac.type >= ixgbe_mac_X550)
6615 return false;
6616
6617 for (i = 0; i < adapter->num_vfs; i++) {
6618 for (j = 0; j < q_per_pool; j++) {
6619 u32 h, t;
6620
6621 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6622 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6623
6624 if (h != t)
6625 return true;
6626 }
6627 }
6628
6629 return false;
6630 }
6631
6632 /**
6633 * ixgbe_watchdog_flush_tx - flush queues on link down
6634 * @adapter: pointer to the device adapter structure
6635 **/
6636 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6637 {
6638 if (!netif_carrier_ok(adapter->netdev)) {
6639 if (ixgbe_ring_tx_pending(adapter) ||
6640 ixgbe_vf_tx_pending(adapter)) {
6641 /* We've lost link, so the controller stops DMA,
6642 * but we've got queued Tx work that's never going
6643 * to get done, so reset controller to flush Tx.
6644 * (Do the reset outside of interrupt context).
6645 */
6646 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
6647 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6648 }
6649 }
6650 }
6651
6652 #ifdef CONFIG_PCI_IOV
6653 static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6654 struct pci_dev *vfdev)
6655 {
6656 if (!pci_wait_for_pending_transaction(vfdev))
6657 e_dev_warn("Issuing VFLR with pending transactions\n");
6658
6659 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6660 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6661
6662 msleep(100);
6663 }
6664
6665 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6666 {
6667 struct ixgbe_hw *hw = &adapter->hw;
6668 struct pci_dev *pdev = adapter->pdev;
6669 unsigned int vf;
6670 u32 gpc;
6671
6672 if (!(netif_carrier_ok(adapter->netdev)))
6673 return;
6674
6675 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6676 if (gpc) /* If incrementing then no need for the check below */
6677 return;
6678 /* Check to see if a bad DMA write target from an errant or
6679 * malicious VF has caused a PCIe error. If so then we can
6680 * issue a VFLR to the offending VF(s) and then resume without
6681 * requesting a full slot reset.
6682 */
6683
6684 if (!pdev)
6685 return;
6686
6687 /* check status reg for all VFs owned by this PF */
6688 for (vf = 0; vf < adapter->num_vfs; ++vf) {
6689 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev;
6690 u16 status_reg;
6691
6692 if (!vfdev)
6693 continue;
6694 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6695 if (status_reg != IXGBE_FAILED_READ_CFG_WORD &&
6696 status_reg & PCI_STATUS_REC_MASTER_ABORT)
6697 ixgbe_issue_vf_flr(adapter, vfdev);
6698 }
6699 }
6700
6701 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6702 {
6703 u32 ssvpc;
6704
6705 /* Do not perform spoof check for 82598 or if not in IOV mode */
6706 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6707 adapter->num_vfs == 0)
6708 return;
6709
6710 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6711
6712 /*
6713 * ssvpc register is cleared on read, if zero then no
6714 * spoofed packets in the last interval.
6715 */
6716 if (!ssvpc)
6717 return;
6718
6719 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
6720 }
6721 #else
6722 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
6723 {
6724 }
6725
6726 static void
6727 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
6728 {
6729 }
6730 #endif /* CONFIG_PCI_IOV */
6731
6732
6733 /**
6734 * ixgbe_watchdog_subtask - check and bring link up
6735 * @adapter: pointer to the device adapter structure
6736 **/
6737 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6738 {
6739 /* if interface is down, removing or resetting, do nothing */
6740 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6741 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6742 test_bit(__IXGBE_RESETTING, &adapter->state))
6743 return;
6744
6745 ixgbe_watchdog_update_link(adapter);
6746
6747 if (adapter->link_up)
6748 ixgbe_watchdog_link_is_up(adapter);
6749 else
6750 ixgbe_watchdog_link_is_down(adapter);
6751
6752 ixgbe_check_for_bad_vf(adapter);
6753 ixgbe_spoof_check(adapter);
6754 ixgbe_update_stats(adapter);
6755
6756 ixgbe_watchdog_flush_tx(adapter);
6757 }
6758
6759 /**
6760 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6761 * @adapter: the ixgbe adapter structure
6762 **/
6763 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6764 {
6765 struct ixgbe_hw *hw = &adapter->hw;
6766 s32 err;
6767
6768 /* not searching for SFP so there is nothing to do here */
6769 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6770 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6771 return;
6772
6773 if (adapter->sfp_poll_time &&
6774 time_after(adapter->sfp_poll_time, jiffies))
6775 return; /* If not yet time to poll for SFP */
6776
6777 /* someone else is in init, wait until next service event */
6778 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6779 return;
6780
6781 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
6782
6783 err = hw->phy.ops.identify_sfp(hw);
6784 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6785 goto sfp_out;
6786
6787 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6788 /* If no cable is present, then we need to reset
6789 * the next time we find a good cable. */
6790 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6791 }
6792
6793 /* exit on error */
6794 if (err)
6795 goto sfp_out;
6796
6797 /* exit if reset not needed */
6798 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6799 goto sfp_out;
6800
6801 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6802
6803 /*
6804 * A module may be identified correctly, but the EEPROM may not have
6805 * support for that module. setup_sfp() will fail in that case, so
6806 * we should not allow that module to load.
6807 */
6808 if (hw->mac.type == ixgbe_mac_82598EB)
6809 err = hw->phy.ops.reset(hw);
6810 else
6811 err = hw->mac.ops.setup_sfp(hw);
6812
6813 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6814 goto sfp_out;
6815
6816 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6817 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6818
6819 sfp_out:
6820 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6821
6822 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6823 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6824 e_dev_err("failed to initialize because an unsupported "
6825 "SFP+ module type was detected.\n");
6826 e_dev_err("Reload the driver after installing a "
6827 "supported module.\n");
6828 unregister_netdev(adapter->netdev);
6829 }
6830 }
6831
6832 /**
6833 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6834 * @adapter: the ixgbe adapter structure
6835 **/
6836 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6837 {
6838 struct ixgbe_hw *hw = &adapter->hw;
6839 u32 speed;
6840 bool autoneg = false;
6841
6842 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6843 return;
6844
6845 /* someone else is in init, wait until next service event */
6846 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6847 return;
6848
6849 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6850
6851 speed = hw->phy.autoneg_advertised;
6852 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
6853 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
6854
6855 /* setup the highest link when no autoneg */
6856 if (!autoneg) {
6857 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6858 speed = IXGBE_LINK_SPEED_10GB_FULL;
6859 }
6860 }
6861
6862 if (hw->mac.ops.setup_link)
6863 hw->mac.ops.setup_link(hw, speed, true);
6864
6865 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6866 adapter->link_check_timeout = jiffies;
6867 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6868 }
6869
6870 /**
6871 * ixgbe_service_timer - Timer Call-back
6872 * @data: pointer to adapter cast into an unsigned long
6873 **/
6874 static void ixgbe_service_timer(unsigned long data)
6875 {
6876 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6877 unsigned long next_event_offset;
6878
6879 /* poll faster when waiting for link */
6880 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6881 next_event_offset = HZ / 10;
6882 else
6883 next_event_offset = HZ * 2;
6884
6885 /* Reset the timer */
6886 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6887
6888 ixgbe_service_event_schedule(adapter);
6889 }
6890
6891 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
6892 {
6893 struct ixgbe_hw *hw = &adapter->hw;
6894 u32 status;
6895
6896 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
6897 return;
6898
6899 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
6900
6901 if (!hw->phy.ops.handle_lasi)
6902 return;
6903
6904 status = hw->phy.ops.handle_lasi(&adapter->hw);
6905 if (status != IXGBE_ERR_OVERTEMP)
6906 return;
6907
6908 e_crit(drv, "%s\n", ixgbe_overheat_msg);
6909 }
6910
6911 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6912 {
6913 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6914 return;
6915
6916 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6917
6918 /* If we're already down, removing or resetting, just bail */
6919 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6920 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6921 test_bit(__IXGBE_RESETTING, &adapter->state))
6922 return;
6923
6924 ixgbe_dump(adapter);
6925 netdev_err(adapter->netdev, "Reset adapter\n");
6926 adapter->tx_timeout_count++;
6927
6928 rtnl_lock();
6929 ixgbe_reinit_locked(adapter);
6930 rtnl_unlock();
6931 }
6932
6933 /**
6934 * ixgbe_service_task - manages and runs subtasks
6935 * @work: pointer to work_struct containing our data
6936 **/
6937 static void ixgbe_service_task(struct work_struct *work)
6938 {
6939 struct ixgbe_adapter *adapter = container_of(work,
6940 struct ixgbe_adapter,
6941 service_task);
6942 if (ixgbe_removed(adapter->hw.hw_addr)) {
6943 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6944 rtnl_lock();
6945 ixgbe_down(adapter);
6946 rtnl_unlock();
6947 }
6948 ixgbe_service_event_complete(adapter);
6949 return;
6950 }
6951 #ifdef CONFIG_IXGBE_VXLAN
6952 if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) {
6953 adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED;
6954 vxlan_get_rx_port(adapter->netdev);
6955 }
6956 #endif /* CONFIG_IXGBE_VXLAN */
6957 ixgbe_reset_subtask(adapter);
6958 ixgbe_phy_interrupt_subtask(adapter);
6959 ixgbe_sfp_detection_subtask(adapter);
6960 ixgbe_sfp_link_config_subtask(adapter);
6961 ixgbe_check_overtemp_subtask(adapter);
6962 ixgbe_watchdog_subtask(adapter);
6963 ixgbe_fdir_reinit_subtask(adapter);
6964 ixgbe_check_hang_subtask(adapter);
6965
6966 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
6967 ixgbe_ptp_overflow_check(adapter);
6968 ixgbe_ptp_rx_hang(adapter);
6969 }
6970
6971 ixgbe_service_event_complete(adapter);
6972 }
6973
6974 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6975 struct ixgbe_tx_buffer *first,
6976 u8 *hdr_len)
6977 {
6978 struct sk_buff *skb = first->skb;
6979 u32 vlan_macip_lens, type_tucmd;
6980 u32 mss_l4len_idx, l4len;
6981 int err;
6982
6983 if (skb->ip_summed != CHECKSUM_PARTIAL)
6984 return 0;
6985
6986 if (!skb_is_gso(skb))
6987 return 0;
6988
6989 err = skb_cow_head(skb, 0);
6990 if (err < 0)
6991 return err;
6992
6993 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6994 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6995
6996 if (first->protocol == htons(ETH_P_IP)) {
6997 struct iphdr *iph = ip_hdr(skb);
6998 iph->tot_len = 0;
6999 iph->check = 0;
7000 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7001 iph->daddr, 0,
7002 IPPROTO_TCP,
7003 0);
7004 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
7005 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7006 IXGBE_TX_FLAGS_CSUM |
7007 IXGBE_TX_FLAGS_IPV4;
7008 } else if (skb_is_gso_v6(skb)) {
7009 ipv6_hdr(skb)->payload_len = 0;
7010 tcp_hdr(skb)->check =
7011 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
7012 &ipv6_hdr(skb)->daddr,
7013 0, IPPROTO_TCP, 0);
7014 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7015 IXGBE_TX_FLAGS_CSUM;
7016 }
7017
7018 /* compute header lengths */
7019 l4len = tcp_hdrlen(skb);
7020 *hdr_len = skb_transport_offset(skb) + l4len;
7021
7022 /* update gso size and bytecount with header size */
7023 first->gso_segs = skb_shinfo(skb)->gso_segs;
7024 first->bytecount += (first->gso_segs - 1) * *hdr_len;
7025
7026 /* mss_l4len_id: use 0 as index for TSO */
7027 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
7028 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
7029
7030 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
7031 vlan_macip_lens = skb_network_header_len(skb);
7032 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
7033 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
7034
7035 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
7036 mss_l4len_idx);
7037
7038 return 1;
7039 }
7040
7041 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
7042 struct ixgbe_tx_buffer *first)
7043 {
7044 struct sk_buff *skb = first->skb;
7045 u32 vlan_macip_lens = 0;
7046 u32 mss_l4len_idx = 0;
7047 u32 type_tucmd = 0;
7048
7049 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7050 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
7051 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
7052 return;
7053 vlan_macip_lens = skb_network_offset(skb) <<
7054 IXGBE_ADVTXD_MACLEN_SHIFT;
7055 } else {
7056 u8 l4_hdr = 0;
7057 union {
7058 struct iphdr *ipv4;
7059 struct ipv6hdr *ipv6;
7060 u8 *raw;
7061 } network_hdr;
7062 union {
7063 struct tcphdr *tcphdr;
7064 u8 *raw;
7065 } transport_hdr;
7066
7067 if (skb->encapsulation) {
7068 network_hdr.raw = skb_inner_network_header(skb);
7069 transport_hdr.raw = skb_inner_transport_header(skb);
7070 vlan_macip_lens = skb_inner_network_offset(skb) <<
7071 IXGBE_ADVTXD_MACLEN_SHIFT;
7072 } else {
7073 network_hdr.raw = skb_network_header(skb);
7074 transport_hdr.raw = skb_transport_header(skb);
7075 vlan_macip_lens = skb_network_offset(skb) <<
7076 IXGBE_ADVTXD_MACLEN_SHIFT;
7077 }
7078
7079 /* use first 4 bits to determine IP version */
7080 switch (network_hdr.ipv4->version) {
7081 case IPVERSION:
7082 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
7083 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
7084 l4_hdr = network_hdr.ipv4->protocol;
7085 break;
7086 case 6:
7087 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
7088 l4_hdr = network_hdr.ipv6->nexthdr;
7089 break;
7090 default:
7091 if (unlikely(net_ratelimit())) {
7092 dev_warn(tx_ring->dev,
7093 "partial checksum but version=%d\n",
7094 network_hdr.ipv4->version);
7095 }
7096 }
7097
7098 switch (l4_hdr) {
7099 case IPPROTO_TCP:
7100 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
7101 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) <<
7102 IXGBE_ADVTXD_L4LEN_SHIFT;
7103 break;
7104 case IPPROTO_SCTP:
7105 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
7106 mss_l4len_idx = sizeof(struct sctphdr) <<
7107 IXGBE_ADVTXD_L4LEN_SHIFT;
7108 break;
7109 case IPPROTO_UDP:
7110 mss_l4len_idx = sizeof(struct udphdr) <<
7111 IXGBE_ADVTXD_L4LEN_SHIFT;
7112 break;
7113 default:
7114 if (unlikely(net_ratelimit())) {
7115 dev_warn(tx_ring->dev,
7116 "partial checksum but l4 proto=%x!\n",
7117 l4_hdr);
7118 }
7119 break;
7120 }
7121
7122 /* update TX checksum flag */
7123 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7124 }
7125
7126 /* vlan_macip_lens: MACLEN, VLAN tag */
7127 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
7128
7129 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
7130 type_tucmd, mss_l4len_idx);
7131 }
7132
7133 #define IXGBE_SET_FLAG(_input, _flag, _result) \
7134 ((_flag <= _result) ? \
7135 ((u32)(_input & _flag) * (_result / _flag)) : \
7136 ((u32)(_input & _flag) / (_flag / _result)))
7137
7138 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
7139 {
7140 /* set type for advanced descriptor with frame checksum insertion */
7141 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7142 IXGBE_ADVTXD_DCMD_DEXT |
7143 IXGBE_ADVTXD_DCMD_IFCS;
7144
7145 /* set HW vlan bit if vlan is present */
7146 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7147 IXGBE_ADVTXD_DCMD_VLE);
7148
7149 /* set segmentation enable bits for TSO/FSO */
7150 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7151 IXGBE_ADVTXD_DCMD_TSE);
7152
7153 /* set timestamp bit if present */
7154 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7155 IXGBE_ADVTXD_MAC_TSTAMP);
7156
7157 /* insert frame checksum */
7158 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
7159
7160 return cmd_type;
7161 }
7162
7163 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7164 u32 tx_flags, unsigned int paylen)
7165 {
7166 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
7167
7168 /* enable L4 checksum for TSO and TX checksum offload */
7169 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7170 IXGBE_TX_FLAGS_CSUM,
7171 IXGBE_ADVTXD_POPTS_TXSM);
7172
7173 /* enble IPv4 checksum for TSO */
7174 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7175 IXGBE_TX_FLAGS_IPV4,
7176 IXGBE_ADVTXD_POPTS_IXSM);
7177
7178 /*
7179 * Check Context must be set if Tx switch is enabled, which it
7180 * always is for case where virtual functions are running
7181 */
7182 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7183 IXGBE_TX_FLAGS_CC,
7184 IXGBE_ADVTXD_CC);
7185
7186 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
7187 }
7188
7189 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7190 {
7191 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7192
7193 /* Herbert's original patch had:
7194 * smp_mb__after_netif_stop_queue();
7195 * but since that doesn't exist yet, just open code it.
7196 */
7197 smp_mb();
7198
7199 /* We need to check again in a case another CPU has just
7200 * made room available.
7201 */
7202 if (likely(ixgbe_desc_unused(tx_ring) < size))
7203 return -EBUSY;
7204
7205 /* A reprieve! - use start_queue because it doesn't call schedule */
7206 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7207 ++tx_ring->tx_stats.restart_queue;
7208 return 0;
7209 }
7210
7211 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7212 {
7213 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7214 return 0;
7215
7216 return __ixgbe_maybe_stop_tx(tx_ring, size);
7217 }
7218
7219 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7220 IXGBE_TXD_CMD_RS)
7221
7222 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
7223 struct ixgbe_tx_buffer *first,
7224 const u8 hdr_len)
7225 {
7226 struct sk_buff *skb = first->skb;
7227 struct ixgbe_tx_buffer *tx_buffer;
7228 union ixgbe_adv_tx_desc *tx_desc;
7229 struct skb_frag_struct *frag;
7230 dma_addr_t dma;
7231 unsigned int data_len, size;
7232 u32 tx_flags = first->tx_flags;
7233 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
7234 u16 i = tx_ring->next_to_use;
7235
7236 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7237
7238 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7239
7240 size = skb_headlen(skb);
7241 data_len = skb->data_len;
7242
7243 #ifdef IXGBE_FCOE
7244 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
7245 if (data_len < sizeof(struct fcoe_crc_eof)) {
7246 size -= sizeof(struct fcoe_crc_eof) - data_len;
7247 data_len = 0;
7248 } else {
7249 data_len -= sizeof(struct fcoe_crc_eof);
7250 }
7251 }
7252
7253 #endif
7254 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
7255
7256 tx_buffer = first;
7257
7258 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7259 if (dma_mapping_error(tx_ring->dev, dma))
7260 goto dma_error;
7261
7262 /* record length, and DMA address */
7263 dma_unmap_len_set(tx_buffer, len, size);
7264 dma_unmap_addr_set(tx_buffer, dma, dma);
7265
7266 tx_desc->read.buffer_addr = cpu_to_le64(dma);
7267
7268 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
7269 tx_desc->read.cmd_type_len =
7270 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
7271
7272 i++;
7273 tx_desc++;
7274 if (i == tx_ring->count) {
7275 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7276 i = 0;
7277 }
7278 tx_desc->read.olinfo_status = 0;
7279
7280 dma += IXGBE_MAX_DATA_PER_TXD;
7281 size -= IXGBE_MAX_DATA_PER_TXD;
7282
7283 tx_desc->read.buffer_addr = cpu_to_le64(dma);
7284 }
7285
7286 if (likely(!data_len))
7287 break;
7288
7289 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
7290
7291 i++;
7292 tx_desc++;
7293 if (i == tx_ring->count) {
7294 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7295 i = 0;
7296 }
7297 tx_desc->read.olinfo_status = 0;
7298
7299 #ifdef IXGBE_FCOE
7300 size = min_t(unsigned int, data_len, skb_frag_size(frag));
7301 #else
7302 size = skb_frag_size(frag);
7303 #endif
7304 data_len -= size;
7305
7306 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7307 DMA_TO_DEVICE);
7308
7309 tx_buffer = &tx_ring->tx_buffer_info[i];
7310 }
7311
7312 /* write last descriptor with RS and EOP bits */
7313 cmd_type |= size | IXGBE_TXD_CMD;
7314 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
7315
7316 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
7317
7318 /* set the timestamp */
7319 first->time_stamp = jiffies;
7320
7321 /*
7322 * Force memory writes to complete before letting h/w know there
7323 * are new descriptors to fetch. (Only applicable for weak-ordered
7324 * memory model archs, such as IA-64).
7325 *
7326 * We also need this memory barrier to make certain all of the
7327 * status bits have been updated before next_to_watch is written.
7328 */
7329 wmb();
7330
7331 /* set next_to_watch value indicating a packet is present */
7332 first->next_to_watch = tx_desc;
7333
7334 i++;
7335 if (i == tx_ring->count)
7336 i = 0;
7337
7338 tx_ring->next_to_use = i;
7339
7340 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7341
7342 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
7343 writel(i, tx_ring->tail);
7344
7345 /* we need this if more than one processor can write to our tail
7346 * at a time, it synchronizes IO on IA64/Altix systems
7347 */
7348 mmiowb();
7349 }
7350
7351 return;
7352 dma_error:
7353 dev_err(tx_ring->dev, "TX DMA map failed\n");
7354
7355 /* clear dma mappings for failed tx_buffer_info map */
7356 for (;;) {
7357 tx_buffer = &tx_ring->tx_buffer_info[i];
7358 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7359 if (tx_buffer == first)
7360 break;
7361 if (i == 0)
7362 i = tx_ring->count;
7363 i--;
7364 }
7365
7366 tx_ring->next_to_use = i;
7367 }
7368
7369 static void ixgbe_atr(struct ixgbe_ring *ring,
7370 struct ixgbe_tx_buffer *first)
7371 {
7372 struct ixgbe_q_vector *q_vector = ring->q_vector;
7373 union ixgbe_atr_hash_dword input = { .dword = 0 };
7374 union ixgbe_atr_hash_dword common = { .dword = 0 };
7375 union {
7376 unsigned char *network;
7377 struct iphdr *ipv4;
7378 struct ipv6hdr *ipv6;
7379 } hdr;
7380 struct tcphdr *th;
7381 struct sk_buff *skb;
7382 #ifdef CONFIG_IXGBE_VXLAN
7383 u8 encap = false;
7384 #endif /* CONFIG_IXGBE_VXLAN */
7385 __be16 vlan_id;
7386
7387 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7388 if (!q_vector)
7389 return;
7390
7391 /* do nothing if sampling is disabled */
7392 if (!ring->atr_sample_rate)
7393 return;
7394
7395 ring->atr_count++;
7396
7397 /* snag network header to get L4 type and address */
7398 skb = first->skb;
7399 hdr.network = skb_network_header(skb);
7400 if (skb->encapsulation) {
7401 #ifdef CONFIG_IXGBE_VXLAN
7402 struct ixgbe_adapter *adapter = q_vector->adapter;
7403
7404 if (!adapter->vxlan_port)
7405 return;
7406 if (first->protocol != htons(ETH_P_IP) ||
7407 hdr.ipv4->version != IPVERSION ||
7408 hdr.ipv4->protocol != IPPROTO_UDP) {
7409 return;
7410 }
7411 if (ntohs(udp_hdr(skb)->dest) != adapter->vxlan_port)
7412 return;
7413 encap = true;
7414 hdr.network = skb_inner_network_header(skb);
7415 th = inner_tcp_hdr(skb);
7416 #else
7417 return;
7418 #endif /* CONFIG_IXGBE_VXLAN */
7419 } else {
7420 /* Currently only IPv4/IPv6 with TCP is supported */
7421 if ((first->protocol != htons(ETH_P_IPV6) ||
7422 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
7423 (first->protocol != htons(ETH_P_IP) ||
7424 hdr.ipv4->protocol != IPPROTO_TCP))
7425 return;
7426 th = tcp_hdr(skb);
7427 }
7428
7429 /* skip this packet since it is invalid or the socket is closing */
7430 if (!th || th->fin)
7431 return;
7432
7433 /* sample on all syn packets or once every atr sample count */
7434 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7435 return;
7436
7437 /* reset sample count */
7438 ring->atr_count = 0;
7439
7440 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
7441
7442 /*
7443 * src and dst are inverted, think how the receiver sees them
7444 *
7445 * The input is broken into two sections, a non-compressed section
7446 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7447 * is XORed together and stored in the compressed dword.
7448 */
7449 input.formatted.vlan_id = vlan_id;
7450
7451 /*
7452 * since src port and flex bytes occupy the same word XOR them together
7453 * and write the value to source port portion of compressed dword
7454 */
7455 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
7456 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
7457 else
7458 common.port.src ^= th->dest ^ first->protocol;
7459 common.port.dst ^= th->source;
7460
7461 if (first->protocol == htons(ETH_P_IP)) {
7462 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7463 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7464 } else {
7465 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7466 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7467 hdr.ipv6->saddr.s6_addr32[1] ^
7468 hdr.ipv6->saddr.s6_addr32[2] ^
7469 hdr.ipv6->saddr.s6_addr32[3] ^
7470 hdr.ipv6->daddr.s6_addr32[0] ^
7471 hdr.ipv6->daddr.s6_addr32[1] ^
7472 hdr.ipv6->daddr.s6_addr32[2] ^
7473 hdr.ipv6->daddr.s6_addr32[3];
7474 }
7475
7476 #ifdef CONFIG_IXGBE_VXLAN
7477 if (encap)
7478 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
7479 #endif /* CONFIG_IXGBE_VXLAN */
7480
7481 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
7482 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7483 input, common, ring->queue_index);
7484 }
7485
7486 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
7487 void *accel_priv, select_queue_fallback_t fallback)
7488 {
7489 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7490 #ifdef IXGBE_FCOE
7491 struct ixgbe_adapter *adapter;
7492 struct ixgbe_ring_feature *f;
7493 int txq;
7494 #endif
7495
7496 if (fwd_adapter)
7497 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7498
7499 #ifdef IXGBE_FCOE
7500
7501 /*
7502 * only execute the code below if protocol is FCoE
7503 * or FIP and we have FCoE enabled on the adapter
7504 */
7505 switch (vlan_get_protocol(skb)) {
7506 case htons(ETH_P_FCOE):
7507 case htons(ETH_P_FIP):
7508 adapter = netdev_priv(dev);
7509
7510 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7511 break;
7512 default:
7513 return fallback(dev, skb);
7514 }
7515
7516 f = &adapter->ring_feature[RING_F_FCOE];
7517
7518 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7519 smp_processor_id();
7520
7521 while (txq >= f->indices)
7522 txq -= f->indices;
7523
7524 return txq + f->offset;
7525 #else
7526 return fallback(dev, skb);
7527 #endif
7528 }
7529
7530 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
7531 struct ixgbe_adapter *adapter,
7532 struct ixgbe_ring *tx_ring)
7533 {
7534 struct ixgbe_tx_buffer *first;
7535 int tso;
7536 u32 tx_flags = 0;
7537 unsigned short f;
7538 u16 count = TXD_USE_COUNT(skb_headlen(skb));
7539 __be16 protocol = skb->protocol;
7540 u8 hdr_len = 0;
7541
7542 /*
7543 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
7544 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
7545 * + 2 desc gap to keep tail from touching head,
7546 * + 1 desc for context descriptor,
7547 * otherwise try next time
7548 */
7549 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7550 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7551
7552 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7553 tx_ring->tx_stats.tx_busy++;
7554 return NETDEV_TX_BUSY;
7555 }
7556
7557 /* record the location of the first descriptor for this packet */
7558 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7559 first->skb = skb;
7560 first->bytecount = skb->len;
7561 first->gso_segs = 1;
7562
7563 /* if we have a HW VLAN tag being added default to the HW one */
7564 if (skb_vlan_tag_present(skb)) {
7565 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7566 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7567 /* else if it is a SW VLAN check the next protocol and store the tag */
7568 } else if (protocol == htons(ETH_P_8021Q)) {
7569 struct vlan_hdr *vhdr, _vhdr;
7570 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7571 if (!vhdr)
7572 goto out_drop;
7573
7574 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7575 IXGBE_TX_FLAGS_VLAN_SHIFT;
7576 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7577 }
7578 protocol = vlan_get_protocol(skb);
7579
7580 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7581 adapter->ptp_clock &&
7582 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7583 &adapter->state)) {
7584 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7585 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
7586
7587 /* schedule check for Tx timestamp */
7588 adapter->ptp_tx_skb = skb_get(skb);
7589 adapter->ptp_tx_start = jiffies;
7590 schedule_work(&adapter->ptp_tx_work);
7591 }
7592
7593 skb_tx_timestamp(skb);
7594
7595 #ifdef CONFIG_PCI_IOV
7596 /*
7597 * Use the l2switch_enable flag - would be false if the DMA
7598 * Tx switch had been disabled.
7599 */
7600 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7601 tx_flags |= IXGBE_TX_FLAGS_CC;
7602
7603 #endif
7604 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
7605 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7606 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7607 (skb->priority != TC_PRIO_CONTROL))) {
7608 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
7609 tx_flags |= (skb->priority & 0x7) <<
7610 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
7611 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7612 struct vlan_ethhdr *vhdr;
7613
7614 if (skb_cow_head(skb, 0))
7615 goto out_drop;
7616 vhdr = (struct vlan_ethhdr *)skb->data;
7617 vhdr->h_vlan_TCI = htons(tx_flags >>
7618 IXGBE_TX_FLAGS_VLAN_SHIFT);
7619 } else {
7620 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7621 }
7622 }
7623
7624 /* record initial flags and protocol */
7625 first->tx_flags = tx_flags;
7626 first->protocol = protocol;
7627
7628 #ifdef IXGBE_FCOE
7629 /* setup tx offload for FCoE */
7630 if ((protocol == htons(ETH_P_FCOE)) &&
7631 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
7632 tso = ixgbe_fso(tx_ring, first, &hdr_len);
7633 if (tso < 0)
7634 goto out_drop;
7635
7636 goto xmit_fcoe;
7637 }
7638
7639 #endif /* IXGBE_FCOE */
7640 tso = ixgbe_tso(tx_ring, first, &hdr_len);
7641 if (tso < 0)
7642 goto out_drop;
7643 else if (!tso)
7644 ixgbe_tx_csum(tx_ring, first);
7645
7646 /* add the ATR filter if ATR is on */
7647 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7648 ixgbe_atr(tx_ring, first);
7649
7650 #ifdef IXGBE_FCOE
7651 xmit_fcoe:
7652 #endif /* IXGBE_FCOE */
7653 ixgbe_tx_map(tx_ring, first, hdr_len);
7654
7655 return NETDEV_TX_OK;
7656
7657 out_drop:
7658 dev_kfree_skb_any(first->skb);
7659 first->skb = NULL;
7660
7661 return NETDEV_TX_OK;
7662 }
7663
7664 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7665 struct net_device *netdev,
7666 struct ixgbe_ring *ring)
7667 {
7668 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7669 struct ixgbe_ring *tx_ring;
7670
7671 /*
7672 * The minimum packet size for olinfo paylen is 17 so pad the skb
7673 * in order to meet this minimum size requirement.
7674 */
7675 if (skb_put_padto(skb, 17))
7676 return NETDEV_TX_OK;
7677
7678 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7679
7680 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
7681 }
7682
7683 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7684 struct net_device *netdev)
7685 {
7686 return __ixgbe_xmit_frame(skb, netdev, NULL);
7687 }
7688
7689 /**
7690 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7691 * @netdev: network interface device structure
7692 * @p: pointer to an address structure
7693 *
7694 * Returns 0 on success, negative on failure
7695 **/
7696 static int ixgbe_set_mac(struct net_device *netdev, void *p)
7697 {
7698 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7699 struct ixgbe_hw *hw = &adapter->hw;
7700 struct sockaddr *addr = p;
7701
7702 if (!is_valid_ether_addr(addr->sa_data))
7703 return -EADDRNOTAVAIL;
7704
7705 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
7706 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
7707
7708 ixgbe_mac_set_default_filter(adapter);
7709
7710 return 0;
7711 }
7712
7713 static int
7714 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7715 {
7716 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7717 struct ixgbe_hw *hw = &adapter->hw;
7718 u16 value;
7719 int rc;
7720
7721 if (prtad != hw->phy.mdio.prtad)
7722 return -EINVAL;
7723 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7724 if (!rc)
7725 rc = value;
7726 return rc;
7727 }
7728
7729 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7730 u16 addr, u16 value)
7731 {
7732 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7733 struct ixgbe_hw *hw = &adapter->hw;
7734
7735 if (prtad != hw->phy.mdio.prtad)
7736 return -EINVAL;
7737 return hw->phy.ops.write_reg(hw, addr, devad, value);
7738 }
7739
7740 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7741 {
7742 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7743
7744 switch (cmd) {
7745 case SIOCSHWTSTAMP:
7746 return ixgbe_ptp_set_ts_config(adapter, req);
7747 case SIOCGHWTSTAMP:
7748 return ixgbe_ptp_get_ts_config(adapter, req);
7749 default:
7750 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7751 }
7752 }
7753
7754 /**
7755 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
7756 * netdev->dev_addrs
7757 * @netdev: network interface device structure
7758 *
7759 * Returns non-zero on failure
7760 **/
7761 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7762 {
7763 int err = 0;
7764 struct ixgbe_adapter *adapter = netdev_priv(dev);
7765 struct ixgbe_hw *hw = &adapter->hw;
7766
7767 if (is_valid_ether_addr(hw->mac.san_addr)) {
7768 rtnl_lock();
7769 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
7770 rtnl_unlock();
7771
7772 /* update SAN MAC vmdq pool selection */
7773 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
7774 }
7775 return err;
7776 }
7777
7778 /**
7779 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7780 * netdev->dev_addrs
7781 * @netdev: network interface device structure
7782 *
7783 * Returns non-zero on failure
7784 **/
7785 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7786 {
7787 int err = 0;
7788 struct ixgbe_adapter *adapter = netdev_priv(dev);
7789 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7790
7791 if (is_valid_ether_addr(mac->san_addr)) {
7792 rtnl_lock();
7793 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7794 rtnl_unlock();
7795 }
7796 return err;
7797 }
7798
7799 #ifdef CONFIG_NET_POLL_CONTROLLER
7800 /*
7801 * Polling 'interrupt' - used by things like netconsole to send skbs
7802 * without having to re-enable interrupts. It's not called while
7803 * the interrupt routine is executing.
7804 */
7805 static void ixgbe_netpoll(struct net_device *netdev)
7806 {
7807 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7808 int i;
7809
7810 /* if interface is down do nothing */
7811 if (test_bit(__IXGBE_DOWN, &adapter->state))
7812 return;
7813
7814 /* loop through and schedule all active queues */
7815 for (i = 0; i < adapter->num_q_vectors; i++)
7816 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
7817 }
7818
7819 #endif
7820 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7821 struct rtnl_link_stats64 *stats)
7822 {
7823 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7824 int i;
7825
7826 rcu_read_lock();
7827 for (i = 0; i < adapter->num_rx_queues; i++) {
7828 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7829 u64 bytes, packets;
7830 unsigned int start;
7831
7832 if (ring) {
7833 do {
7834 start = u64_stats_fetch_begin_irq(&ring->syncp);
7835 packets = ring->stats.packets;
7836 bytes = ring->stats.bytes;
7837 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
7838 stats->rx_packets += packets;
7839 stats->rx_bytes += bytes;
7840 }
7841 }
7842
7843 for (i = 0; i < adapter->num_tx_queues; i++) {
7844 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7845 u64 bytes, packets;
7846 unsigned int start;
7847
7848 if (ring) {
7849 do {
7850 start = u64_stats_fetch_begin_irq(&ring->syncp);
7851 packets = ring->stats.packets;
7852 bytes = ring->stats.bytes;
7853 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
7854 stats->tx_packets += packets;
7855 stats->tx_bytes += bytes;
7856 }
7857 }
7858 rcu_read_unlock();
7859 /* following stats updated by ixgbe_watchdog_task() */
7860 stats->multicast = netdev->stats.multicast;
7861 stats->rx_errors = netdev->stats.rx_errors;
7862 stats->rx_length_errors = netdev->stats.rx_length_errors;
7863 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7864 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7865 return stats;
7866 }
7867
7868 #ifdef CONFIG_IXGBE_DCB
7869 /**
7870 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7871 * @adapter: pointer to ixgbe_adapter
7872 * @tc: number of traffic classes currently enabled
7873 *
7874 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7875 * 802.1Q priority maps to a packet buffer that exists.
7876 */
7877 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7878 {
7879 struct ixgbe_hw *hw = &adapter->hw;
7880 u32 reg, rsave;
7881 int i;
7882
7883 /* 82598 have a static priority to TC mapping that can not
7884 * be changed so no validation is needed.
7885 */
7886 if (hw->mac.type == ixgbe_mac_82598EB)
7887 return;
7888
7889 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7890 rsave = reg;
7891
7892 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7893 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7894
7895 /* If up2tc is out of bounds default to zero */
7896 if (up2tc > tc)
7897 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7898 }
7899
7900 if (reg != rsave)
7901 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7902
7903 return;
7904 }
7905
7906 /**
7907 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7908 * @adapter: Pointer to adapter struct
7909 *
7910 * Populate the netdev user priority to tc map
7911 */
7912 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7913 {
7914 struct net_device *dev = adapter->netdev;
7915 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7916 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7917 u8 prio;
7918
7919 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7920 u8 tc = 0;
7921
7922 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7923 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7924 else if (ets)
7925 tc = ets->prio_tc[prio];
7926
7927 netdev_set_prio_tc_map(dev, prio, tc);
7928 }
7929 }
7930
7931 #endif /* CONFIG_IXGBE_DCB */
7932 /**
7933 * ixgbe_setup_tc - configure net_device for multiple traffic classes
7934 *
7935 * @netdev: net device to configure
7936 * @tc: number of traffic classes to enable
7937 */
7938 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7939 {
7940 struct ixgbe_adapter *adapter = netdev_priv(dev);
7941 struct ixgbe_hw *hw = &adapter->hw;
7942 bool pools;
7943
7944 /* Hardware supports up to 8 traffic classes */
7945 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
7946 return -EINVAL;
7947
7948 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
7949 return -EINVAL;
7950
7951 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7952 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7953 return -EBUSY;
7954
7955 /* Hardware has to reinitialize queues and interrupts to
7956 * match packet buffer alignment. Unfortunately, the
7957 * hardware is not flexible enough to do this dynamically.
7958 */
7959 if (netif_running(dev))
7960 ixgbe_close(dev);
7961 ixgbe_clear_interrupt_scheme(adapter);
7962
7963 #ifdef CONFIG_IXGBE_DCB
7964 if (tc) {
7965 netdev_set_num_tc(dev, tc);
7966 ixgbe_set_prio_tc_map(adapter);
7967
7968 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7969
7970 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7971 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
7972 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7973 }
7974 } else {
7975 netdev_reset_tc(dev);
7976
7977 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7978 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7979
7980 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7981
7982 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7983 adapter->dcb_cfg.pfc_mode_enable = false;
7984 }
7985
7986 ixgbe_validate_rtr(adapter, tc);
7987
7988 #endif /* CONFIG_IXGBE_DCB */
7989 ixgbe_init_interrupt_scheme(adapter);
7990
7991 if (netif_running(dev))
7992 return ixgbe_open(dev);
7993
7994 return 0;
7995 }
7996
7997 #ifdef CONFIG_PCI_IOV
7998 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7999 {
8000 struct net_device *netdev = adapter->netdev;
8001
8002 rtnl_lock();
8003 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
8004 rtnl_unlock();
8005 }
8006
8007 #endif
8008 void ixgbe_do_reset(struct net_device *netdev)
8009 {
8010 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8011
8012 if (netif_running(netdev))
8013 ixgbe_reinit_locked(adapter);
8014 else
8015 ixgbe_reset(adapter);
8016 }
8017
8018 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
8019 netdev_features_t features)
8020 {
8021 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8022
8023 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
8024 if (!(features & NETIF_F_RXCSUM))
8025 features &= ~NETIF_F_LRO;
8026
8027 /* Turn off LRO if not RSC capable */
8028 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
8029 features &= ~NETIF_F_LRO;
8030
8031 return features;
8032 }
8033
8034 static int ixgbe_set_features(struct net_device *netdev,
8035 netdev_features_t features)
8036 {
8037 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8038 netdev_features_t changed = netdev->features ^ features;
8039 bool need_reset = false;
8040
8041 /* Make sure RSC matches LRO, reset if change */
8042 if (!(features & NETIF_F_LRO)) {
8043 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
8044 need_reset = true;
8045 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
8046 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
8047 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
8048 if (adapter->rx_itr_setting == 1 ||
8049 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
8050 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8051 need_reset = true;
8052 } else if ((changed ^ features) & NETIF_F_LRO) {
8053 e_info(probe, "rx-usecs set too low, "
8054 "disabling RSC\n");
8055 }
8056 }
8057
8058 /*
8059 * Check if Flow Director n-tuple support was enabled or disabled. If
8060 * the state changed, we need to reset.
8061 */
8062 switch (features & NETIF_F_NTUPLE) {
8063 case NETIF_F_NTUPLE:
8064 /* turn off ATR, enable perfect filters and reset */
8065 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
8066 need_reset = true;
8067
8068 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
8069 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8070 break;
8071 default:
8072 /* turn off perfect filters, enable ATR and reset */
8073 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
8074 need_reset = true;
8075
8076 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8077
8078 /* We cannot enable ATR if SR-IOV is enabled */
8079 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
8080 break;
8081
8082 /* We cannot enable ATR if we have 2 or more traffic classes */
8083 if (netdev_get_num_tc(netdev) > 1)
8084 break;
8085
8086 /* We cannot enable ATR if RSS is disabled */
8087 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
8088 break;
8089
8090 /* A sample rate of 0 indicates ATR disabled */
8091 if (!adapter->atr_sample_rate)
8092 break;
8093
8094 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
8095 break;
8096 }
8097
8098 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8099 ixgbe_vlan_strip_enable(adapter);
8100 else
8101 ixgbe_vlan_strip_disable(adapter);
8102
8103 if (changed & NETIF_F_RXALL)
8104 need_reset = true;
8105
8106 netdev->features = features;
8107
8108 #ifdef CONFIG_IXGBE_VXLAN
8109 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
8110 if (features & NETIF_F_RXCSUM)
8111 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8112 else
8113 ixgbe_clear_vxlan_port(adapter);
8114 }
8115 #endif /* CONFIG_IXGBE_VXLAN */
8116
8117 if (need_reset)
8118 ixgbe_do_reset(netdev);
8119
8120 return 0;
8121 }
8122
8123 #ifdef CONFIG_IXGBE_VXLAN
8124 /**
8125 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up
8126 * @dev: The port's netdev
8127 * @sa_family: Socket Family that VXLAN is notifiying us about
8128 * @port: New UDP port number that VXLAN started listening to
8129 **/
8130 static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8131 __be16 port)
8132 {
8133 struct ixgbe_adapter *adapter = netdev_priv(dev);
8134 struct ixgbe_hw *hw = &adapter->hw;
8135 u16 new_port = ntohs(port);
8136
8137 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8138 return;
8139
8140 if (sa_family == AF_INET6)
8141 return;
8142
8143 if (adapter->vxlan_port == new_port)
8144 return;
8145
8146 if (adapter->vxlan_port) {
8147 netdev_info(dev,
8148 "Hit Max num of VXLAN ports, not adding port %d\n",
8149 new_port);
8150 return;
8151 }
8152
8153 adapter->vxlan_port = new_port;
8154 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, new_port);
8155 }
8156
8157 /**
8158 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away
8159 * @dev: The port's netdev
8160 * @sa_family: Socket Family that VXLAN is notifying us about
8161 * @port: UDP port number that VXLAN stopped listening to
8162 **/
8163 static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8164 __be16 port)
8165 {
8166 struct ixgbe_adapter *adapter = netdev_priv(dev);
8167 u16 new_port = ntohs(port);
8168
8169 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8170 return;
8171
8172 if (sa_family == AF_INET6)
8173 return;
8174
8175 if (adapter->vxlan_port != new_port) {
8176 netdev_info(dev, "Port %d was not found, not deleting\n",
8177 new_port);
8178 return;
8179 }
8180
8181 ixgbe_clear_vxlan_port(adapter);
8182 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8183 }
8184 #endif /* CONFIG_IXGBE_VXLAN */
8185
8186 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8187 struct net_device *dev,
8188 const unsigned char *addr, u16 vid,
8189 u16 flags)
8190 {
8191 /* guarantee we can provide a unique filter for the unicast address */
8192 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
8193 struct ixgbe_adapter *adapter = netdev_priv(dev);
8194 u16 pool = VMDQ_P(0);
8195
8196 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool))
8197 return -ENOMEM;
8198 }
8199
8200 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
8201 }
8202
8203 /**
8204 * ixgbe_configure_bridge_mode - set various bridge modes
8205 * @adapter - the private structure
8206 * @mode - requested bridge mode
8207 *
8208 * Configure some settings require for various bridge modes.
8209 **/
8210 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
8211 __u16 mode)
8212 {
8213 struct ixgbe_hw *hw = &adapter->hw;
8214 unsigned int p, num_pools;
8215 u32 vmdctl;
8216
8217 switch (mode) {
8218 case BRIDGE_MODE_VEPA:
8219 /* disable Tx loopback, rely on switch hairpin mode */
8220 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
8221
8222 /* must enable Rx switching replication to allow multicast
8223 * packet reception on all VFs, and to enable source address
8224 * pruning.
8225 */
8226 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8227 vmdctl |= IXGBE_VT_CTL_REPLEN;
8228 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8229
8230 /* enable Rx source address pruning. Note, this requires
8231 * replication to be enabled or else it does nothing.
8232 */
8233 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8234 for (p = 0; p < num_pools; p++) {
8235 if (hw->mac.ops.set_source_address_pruning)
8236 hw->mac.ops.set_source_address_pruning(hw,
8237 true,
8238 p);
8239 }
8240 break;
8241 case BRIDGE_MODE_VEB:
8242 /* enable Tx loopback for internal VF/PF communication */
8243 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
8244 IXGBE_PFDTXGSWC_VT_LBEN);
8245
8246 /* disable Rx switching replication unless we have SR-IOV
8247 * virtual functions
8248 */
8249 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8250 if (!adapter->num_vfs)
8251 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
8252 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8253
8254 /* disable Rx source address pruning, since we don't expect to
8255 * be receiving external loopback of our transmitted frames.
8256 */
8257 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8258 for (p = 0; p < num_pools; p++) {
8259 if (hw->mac.ops.set_source_address_pruning)
8260 hw->mac.ops.set_source_address_pruning(hw,
8261 false,
8262 p);
8263 }
8264 break;
8265 default:
8266 return -EINVAL;
8267 }
8268
8269 adapter->bridge_mode = mode;
8270
8271 e_info(drv, "enabling bridge mode: %s\n",
8272 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
8273
8274 return 0;
8275 }
8276
8277 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
8278 struct nlmsghdr *nlh, u16 flags)
8279 {
8280 struct ixgbe_adapter *adapter = netdev_priv(dev);
8281 struct nlattr *attr, *br_spec;
8282 int rem;
8283
8284 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8285 return -EOPNOTSUPP;
8286
8287 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8288 if (!br_spec)
8289 return -EINVAL;
8290
8291 nla_for_each_nested(attr, br_spec, rem) {
8292 int status;
8293 __u16 mode;
8294
8295 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8296 continue;
8297
8298 if (nla_len(attr) < sizeof(mode))
8299 return -EINVAL;
8300
8301 mode = nla_get_u16(attr);
8302 status = ixgbe_configure_bridge_mode(adapter, mode);
8303 if (status)
8304 return status;
8305
8306 break;
8307 }
8308
8309 return 0;
8310 }
8311
8312 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8313 struct net_device *dev,
8314 u32 filter_mask, int nlflags)
8315 {
8316 struct ixgbe_adapter *adapter = netdev_priv(dev);
8317
8318 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8319 return 0;
8320
8321 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
8322 adapter->bridge_mode, 0, 0, nlflags,
8323 filter_mask, NULL);
8324 }
8325
8326 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
8327 {
8328 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
8329 struct ixgbe_adapter *adapter = netdev_priv(pdev);
8330 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
8331 unsigned int limit;
8332 int pool, err;
8333
8334 /* Hardware has a limited number of available pools. Each VF, and the
8335 * PF require a pool. Check to ensure we don't attempt to use more
8336 * then the available number of pools.
8337 */
8338 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
8339 return ERR_PTR(-EINVAL);
8340
8341 #ifdef CONFIG_RPS
8342 if (vdev->num_rx_queues != vdev->num_tx_queues) {
8343 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
8344 vdev->name);
8345 return ERR_PTR(-EINVAL);
8346 }
8347 #endif
8348 /* Check for hardware restriction on number of rx/tx queues */
8349 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
8350 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
8351 netdev_info(pdev,
8352 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
8353 pdev->name);
8354 return ERR_PTR(-EINVAL);
8355 }
8356
8357 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8358 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
8359 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
8360 return ERR_PTR(-EBUSY);
8361
8362 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL);
8363 if (!fwd_adapter)
8364 return ERR_PTR(-ENOMEM);
8365
8366 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
8367 adapter->num_rx_pools++;
8368 set_bit(pool, &adapter->fwd_bitmask);
8369 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8370
8371 /* Enable VMDq flag so device will be set in VM mode */
8372 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
8373 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
8374 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
8375
8376 /* Force reinit of ring allocation with VMDQ enabled */
8377 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8378 if (err)
8379 goto fwd_add_err;
8380 fwd_adapter->pool = pool;
8381 fwd_adapter->real_adapter = adapter;
8382 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
8383 if (err)
8384 goto fwd_add_err;
8385 netif_tx_start_all_queues(vdev);
8386 return fwd_adapter;
8387 fwd_add_err:
8388 /* unwind counter and free adapter struct */
8389 netdev_info(pdev,
8390 "%s: dfwd hardware acceleration failed\n", vdev->name);
8391 clear_bit(pool, &adapter->fwd_bitmask);
8392 adapter->num_rx_pools--;
8393 kfree(fwd_adapter);
8394 return ERR_PTR(err);
8395 }
8396
8397 static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8398 {
8399 struct ixgbe_fwd_adapter *fwd_adapter = priv;
8400 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
8401 unsigned int limit;
8402
8403 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
8404 adapter->num_rx_pools--;
8405
8406 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8407 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
8408 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
8409 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8410 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
8411 fwd_adapter->pool, adapter->num_rx_pools,
8412 fwd_adapter->rx_base_queue,
8413 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
8414 adapter->fwd_bitmask);
8415 kfree(fwd_adapter);
8416 }
8417
8418 #define IXGBE_MAX_TUNNEL_HDR_LEN 80
8419 static netdev_features_t
8420 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
8421 netdev_features_t features)
8422 {
8423 if (!skb->encapsulation)
8424 return features;
8425
8426 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) >
8427 IXGBE_MAX_TUNNEL_HDR_LEN))
8428 return features & ~NETIF_F_ALL_CSUM;
8429
8430 return features;
8431 }
8432
8433 static const struct net_device_ops ixgbe_netdev_ops = {
8434 .ndo_open = ixgbe_open,
8435 .ndo_stop = ixgbe_close,
8436 .ndo_start_xmit = ixgbe_xmit_frame,
8437 .ndo_select_queue = ixgbe_select_queue,
8438 .ndo_set_rx_mode = ixgbe_set_rx_mode,
8439 .ndo_validate_addr = eth_validate_addr,
8440 .ndo_set_mac_address = ixgbe_set_mac,
8441 .ndo_change_mtu = ixgbe_change_mtu,
8442 .ndo_tx_timeout = ixgbe_tx_timeout,
8443 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
8444 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
8445 .ndo_do_ioctl = ixgbe_ioctl,
8446 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
8447 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
8448 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
8449 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
8450 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
8451 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
8452 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
8453 .ndo_get_stats64 = ixgbe_get_stats64,
8454 #ifdef CONFIG_IXGBE_DCB
8455 .ndo_setup_tc = ixgbe_setup_tc,
8456 #endif
8457 #ifdef CONFIG_NET_POLL_CONTROLLER
8458 .ndo_poll_controller = ixgbe_netpoll,
8459 #endif
8460 #ifdef CONFIG_NET_RX_BUSY_POLL
8461 .ndo_busy_poll = ixgbe_low_latency_recv,
8462 #endif
8463 #ifdef IXGBE_FCOE
8464 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
8465 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
8466 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8467 .ndo_fcoe_enable = ixgbe_fcoe_enable,
8468 .ndo_fcoe_disable = ixgbe_fcoe_disable,
8469 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
8470 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
8471 #endif /* IXGBE_FCOE */
8472 .ndo_set_features = ixgbe_set_features,
8473 .ndo_fix_features = ixgbe_fix_features,
8474 .ndo_fdb_add = ixgbe_ndo_fdb_add,
8475 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
8476 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
8477 .ndo_dfwd_add_station = ixgbe_fwd_add,
8478 .ndo_dfwd_del_station = ixgbe_fwd_del,
8479 #ifdef CONFIG_IXGBE_VXLAN
8480 .ndo_add_vxlan_port = ixgbe_add_vxlan_port,
8481 .ndo_del_vxlan_port = ixgbe_del_vxlan_port,
8482 #endif /* CONFIG_IXGBE_VXLAN */
8483 .ndo_features_check = ixgbe_features_check,
8484 };
8485
8486 /**
8487 * ixgbe_enumerate_functions - Get the number of ports this device has
8488 * @adapter: adapter structure
8489 *
8490 * This function enumerates the phsyical functions co-located on a single slot,
8491 * in order to determine how many ports a device has. This is most useful in
8492 * determining the required GT/s of PCIe bandwidth necessary for optimal
8493 * performance.
8494 **/
8495 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
8496 {
8497 struct pci_dev *entry, *pdev = adapter->pdev;
8498 int physfns = 0;
8499
8500 /* Some cards can not use the generic count PCIe functions method,
8501 * because they are behind a parent switch, so we hardcode these with
8502 * the correct number of functions.
8503 */
8504 if (ixgbe_pcie_from_parent(&adapter->hw))
8505 physfns = 4;
8506
8507 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
8508 /* don't count virtual functions */
8509 if (entry->is_virtfn)
8510 continue;
8511
8512 /* When the devices on the bus don't all match our device ID,
8513 * we can't reliably determine the correct number of
8514 * functions. This can occur if a function has been direct
8515 * attached to a virtual machine using VT-d, for example. In
8516 * this case, simply return -1 to indicate this.
8517 */
8518 if ((entry->vendor != pdev->vendor) ||
8519 (entry->device != pdev->device))
8520 return -1;
8521
8522 physfns++;
8523 }
8524
8525 return physfns;
8526 }
8527
8528 /**
8529 * ixgbe_wol_supported - Check whether device supports WoL
8530 * @hw: hw specific details
8531 * @device_id: the device ID
8532 * @subdev_id: the subsystem device ID
8533 *
8534 * This function is used by probe and ethtool to determine
8535 * which devices have WoL support
8536 *
8537 **/
8538 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8539 u16 subdevice_id)
8540 {
8541 struct ixgbe_hw *hw = &adapter->hw;
8542 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8543 int is_wol_supported = 0;
8544
8545 switch (device_id) {
8546 case IXGBE_DEV_ID_82599_SFP:
8547 /* Only these subdevices could supports WOL */
8548 switch (subdevice_id) {
8549 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8550 case IXGBE_SUBDEV_ID_82599_560FLR:
8551 /* only support first port */
8552 if (hw->bus.func != 0)
8553 break;
8554 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8555 case IXGBE_SUBDEV_ID_82599_SFP:
8556 case IXGBE_SUBDEV_ID_82599_RNDC:
8557 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
8558 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8559 is_wol_supported = 1;
8560 break;
8561 }
8562 break;
8563 case IXGBE_DEV_ID_82599EN_SFP:
8564 /* Only this subdevice supports WOL */
8565 switch (subdevice_id) {
8566 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8567 is_wol_supported = 1;
8568 break;
8569 }
8570 break;
8571 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8572 /* All except this subdevice support WOL */
8573 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8574 is_wol_supported = 1;
8575 break;
8576 case IXGBE_DEV_ID_82599_KX4:
8577 is_wol_supported = 1;
8578 break;
8579 case IXGBE_DEV_ID_X540T:
8580 case IXGBE_DEV_ID_X540T1:
8581 case IXGBE_DEV_ID_X550T:
8582 case IXGBE_DEV_ID_X550EM_X_KX4:
8583 case IXGBE_DEV_ID_X550EM_X_KR:
8584 case IXGBE_DEV_ID_X550EM_X_10G_T:
8585 /* check eeprom to see if enabled wol */
8586 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8587 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8588 (hw->bus.func == 0))) {
8589 is_wol_supported = 1;
8590 }
8591 break;
8592 }
8593
8594 return is_wol_supported;
8595 }
8596
8597 /**
8598 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM
8599 * @adapter: Pointer to adapter struct
8600 */
8601 static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter)
8602 {
8603 #ifdef CONFIG_OF
8604 struct device_node *dp = pci_device_to_OF_node(adapter->pdev);
8605 struct ixgbe_hw *hw = &adapter->hw;
8606 const unsigned char *addr;
8607
8608 addr = of_get_mac_address(dp);
8609 if (addr) {
8610 ether_addr_copy(hw->mac.perm_addr, addr);
8611 return;
8612 }
8613 #endif /* CONFIG_OF */
8614
8615 #ifdef CONFIG_SPARC
8616 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr);
8617 #endif /* CONFIG_SPARC */
8618 }
8619
8620 /**
8621 * ixgbe_probe - Device Initialization Routine
8622 * @pdev: PCI device information struct
8623 * @ent: entry in ixgbe_pci_tbl
8624 *
8625 * Returns 0 on success, negative on failure
8626 *
8627 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
8628 * The OS initialization, configuring of the adapter private structure,
8629 * and a hardware reset occur.
8630 **/
8631 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8632 {
8633 struct net_device *netdev;
8634 struct ixgbe_adapter *adapter = NULL;
8635 struct ixgbe_hw *hw;
8636 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
8637 int i, err, pci_using_dac, expected_gts;
8638 unsigned int indices = MAX_TX_QUEUES;
8639 u8 part_str[IXGBE_PBANUM_LENGTH];
8640 bool disable_dev = false;
8641 #ifdef IXGBE_FCOE
8642 u16 device_caps;
8643 #endif
8644 u32 eec;
8645
8646 /* Catch broken hardware that put the wrong VF device ID in
8647 * the PCIe SR-IOV capability.
8648 */
8649 if (pdev->is_virtfn) {
8650 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
8651 pci_name(pdev), pdev->vendor, pdev->device);
8652 return -EINVAL;
8653 }
8654
8655 err = pci_enable_device_mem(pdev);
8656 if (err)
8657 return err;
8658
8659 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
8660 pci_using_dac = 1;
8661 } else {
8662 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8663 if (err) {
8664 dev_err(&pdev->dev,
8665 "No usable DMA configuration, aborting\n");
8666 goto err_dma;
8667 }
8668 pci_using_dac = 0;
8669 }
8670
8671 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8672 IORESOURCE_MEM), ixgbe_driver_name);
8673 if (err) {
8674 dev_err(&pdev->dev,
8675 "pci_request_selected_regions failed 0x%x\n", err);
8676 goto err_pci_reg;
8677 }
8678
8679 pci_enable_pcie_error_reporting(pdev);
8680
8681 pci_set_master(pdev);
8682 pci_save_state(pdev);
8683
8684 if (ii->mac == ixgbe_mac_82598EB) {
8685 #ifdef CONFIG_IXGBE_DCB
8686 /* 8 TC w/ 4 queues per TC */
8687 indices = 4 * MAX_TRAFFIC_CLASS;
8688 #else
8689 indices = IXGBE_MAX_RSS_INDICES;
8690 #endif
8691 }
8692
8693 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
8694 if (!netdev) {
8695 err = -ENOMEM;
8696 goto err_alloc_etherdev;
8697 }
8698
8699 SET_NETDEV_DEV(netdev, &pdev->dev);
8700
8701 adapter = netdev_priv(netdev);
8702
8703 adapter->netdev = netdev;
8704 adapter->pdev = pdev;
8705 hw = &adapter->hw;
8706 hw->back = adapter;
8707 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
8708
8709 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8710 pci_resource_len(pdev, 0));
8711 adapter->io_addr = hw->hw_addr;
8712 if (!hw->hw_addr) {
8713 err = -EIO;
8714 goto err_ioremap;
8715 }
8716
8717 netdev->netdev_ops = &ixgbe_netdev_ops;
8718 ixgbe_set_ethtool_ops(netdev);
8719 netdev->watchdog_timeo = 5 * HZ;
8720 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
8721
8722 /* Setup hw api */
8723 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
8724 hw->mac.type = ii->mac;
8725 hw->mvals = ii->mvals;
8726
8727 /* EEPROM */
8728 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
8729 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
8730 if (ixgbe_removed(hw->hw_addr)) {
8731 err = -EIO;
8732 goto err_ioremap;
8733 }
8734 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8735 if (!(eec & (1 << 8)))
8736 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8737
8738 /* PHY */
8739 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
8740 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
8741 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8742 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8743 hw->phy.mdio.mmds = 0;
8744 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8745 hw->phy.mdio.dev = netdev;
8746 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8747 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
8748
8749 ii->get_invariants(hw);
8750
8751 /* setup the private structure */
8752 err = ixgbe_sw_init(adapter);
8753 if (err)
8754 goto err_sw_init;
8755
8756 /* Make it possible the adapter to be woken up via WOL */
8757 switch (adapter->hw.mac.type) {
8758 case ixgbe_mac_82599EB:
8759 case ixgbe_mac_X540:
8760 case ixgbe_mac_X550:
8761 case ixgbe_mac_X550EM_x:
8762 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
8763 break;
8764 default:
8765 break;
8766 }
8767
8768 /*
8769 * If there is a fan on this device and it has failed log the
8770 * failure.
8771 */
8772 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8773 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8774 if (esdp & IXGBE_ESDP_SDP1)
8775 e_crit(probe, "Fan has stopped, replace the adapter\n");
8776 }
8777
8778 if (allow_unsupported_sfp)
8779 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8780
8781 /* reset_hw fills in the perm_addr as well */
8782 hw->phy.reset_if_overtemp = true;
8783 err = hw->mac.ops.reset_hw(hw);
8784 hw->phy.reset_if_overtemp = false;
8785 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
8786 err = 0;
8787 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
8788 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8789 e_dev_err("Reload the driver after installing a supported module.\n");
8790 goto err_sw_init;
8791 } else if (err) {
8792 e_dev_err("HW Init failed: %d\n", err);
8793 goto err_sw_init;
8794 }
8795
8796 #ifdef CONFIG_PCI_IOV
8797 /* SR-IOV not supported on the 82598 */
8798 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8799 goto skip_sriov;
8800 /* Mailbox */
8801 ixgbe_init_mbx_params_pf(hw);
8802 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
8803 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
8804 ixgbe_enable_sriov(adapter);
8805 skip_sriov:
8806
8807 #endif
8808 netdev->features = NETIF_F_SG |
8809 NETIF_F_IP_CSUM |
8810 NETIF_F_IPV6_CSUM |
8811 NETIF_F_HW_VLAN_CTAG_TX |
8812 NETIF_F_HW_VLAN_CTAG_RX |
8813 NETIF_F_TSO |
8814 NETIF_F_TSO6 |
8815 NETIF_F_RXHASH |
8816 NETIF_F_RXCSUM;
8817
8818 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
8819
8820 switch (adapter->hw.mac.type) {
8821 case ixgbe_mac_82599EB:
8822 case ixgbe_mac_X540:
8823 case ixgbe_mac_X550:
8824 case ixgbe_mac_X550EM_x:
8825 netdev->features |= NETIF_F_SCTP_CSUM;
8826 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8827 NETIF_F_NTUPLE;
8828 break;
8829 default:
8830 break;
8831 }
8832
8833 netdev->hw_features |= NETIF_F_RXALL;
8834 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
8835
8836 netdev->vlan_features |= NETIF_F_TSO;
8837 netdev->vlan_features |= NETIF_F_TSO6;
8838 netdev->vlan_features |= NETIF_F_IP_CSUM;
8839 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
8840 netdev->vlan_features |= NETIF_F_SG;
8841
8842 netdev->hw_enc_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
8843 NETIF_F_IPV6_CSUM;
8844
8845 netdev->priv_flags |= IFF_UNICAST_FLT;
8846 netdev->priv_flags |= IFF_SUPP_NOFCS;
8847
8848 #ifdef CONFIG_IXGBE_VXLAN
8849 switch (adapter->hw.mac.type) {
8850 case ixgbe_mac_X550:
8851 case ixgbe_mac_X550EM_x:
8852 netdev->hw_enc_features |= NETIF_F_RXCSUM |
8853 NETIF_F_IP_CSUM |
8854 NETIF_F_IPV6_CSUM;
8855 break;
8856 default:
8857 break;
8858 }
8859 #endif /* CONFIG_IXGBE_VXLAN */
8860
8861 #ifdef CONFIG_IXGBE_DCB
8862 netdev->dcbnl_ops = &dcbnl_ops;
8863 #endif
8864
8865 #ifdef IXGBE_FCOE
8866 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
8867 unsigned int fcoe_l;
8868
8869 if (hw->mac.ops.get_device_caps) {
8870 hw->mac.ops.get_device_caps(hw, &device_caps);
8871 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8872 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
8873 }
8874
8875
8876 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8877 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
8878
8879 netdev->features |= NETIF_F_FSO |
8880 NETIF_F_FCOE_CRC;
8881
8882 netdev->vlan_features |= NETIF_F_FSO |
8883 NETIF_F_FCOE_CRC |
8884 NETIF_F_FCOE_MTU;
8885 }
8886 #endif /* IXGBE_FCOE */
8887 if (pci_using_dac) {
8888 netdev->features |= NETIF_F_HIGHDMA;
8889 netdev->vlan_features |= NETIF_F_HIGHDMA;
8890 }
8891
8892 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8893 netdev->hw_features |= NETIF_F_LRO;
8894 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
8895 netdev->features |= NETIF_F_LRO;
8896
8897 /* make sure the EEPROM is good */
8898 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
8899 e_dev_err("The EEPROM Checksum Is Not Valid\n");
8900 err = -EIO;
8901 goto err_sw_init;
8902 }
8903
8904 ixgbe_get_platform_mac_addr(adapter);
8905
8906 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
8907
8908 if (!is_valid_ether_addr(netdev->dev_addr)) {
8909 e_dev_err("invalid MAC address\n");
8910 err = -EIO;
8911 goto err_sw_init;
8912 }
8913
8914 ixgbe_mac_set_default_filter(adapter);
8915
8916 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
8917 (unsigned long) adapter);
8918
8919 if (ixgbe_removed(hw->hw_addr)) {
8920 err = -EIO;
8921 goto err_sw_init;
8922 }
8923 INIT_WORK(&adapter->service_task, ixgbe_service_task);
8924 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
8925 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
8926
8927 err = ixgbe_init_interrupt_scheme(adapter);
8928 if (err)
8929 goto err_sw_init;
8930
8931 /* WOL not supported for all devices */
8932 adapter->wol = 0;
8933 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
8934 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
8935 pdev->subsystem_device);
8936 if (hw->wol_enabled)
8937 adapter->wol = IXGBE_WUFC_MAG;
8938
8939 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8940
8941 /* save off EEPROM version number */
8942 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8943 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8944
8945 /* pick up the PCI bus settings for reporting later */
8946 if (ixgbe_pcie_from_parent(hw))
8947 ixgbe_get_parent_bus_info(adapter);
8948 else
8949 hw->mac.ops.get_bus_info(hw);
8950
8951 /* calculate the expected PCIe bandwidth required for optimal
8952 * performance. Note that some older parts will never have enough
8953 * bandwidth due to being older generation PCIe parts. We clamp these
8954 * parts to ensure no warning is displayed if it can't be fixed.
8955 */
8956 switch (hw->mac.type) {
8957 case ixgbe_mac_82598EB:
8958 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8959 break;
8960 default:
8961 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8962 break;
8963 }
8964
8965 /* don't check link if we failed to enumerate functions */
8966 if (expected_gts > 0)
8967 ixgbe_check_minimum_link(adapter, expected_gts);
8968
8969 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
8970 if (err)
8971 strlcpy(part_str, "Unknown", sizeof(part_str));
8972 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8973 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8974 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
8975 part_str);
8976 else
8977 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8978 hw->mac.type, hw->phy.type, part_str);
8979
8980 e_dev_info("%pM\n", netdev->dev_addr);
8981
8982 /* reset the hardware with the new settings */
8983 err = hw->mac.ops.start_hw(hw);
8984 if (err == IXGBE_ERR_EEPROM_VERSION) {
8985 /* We are running on a pre-production device, log a warning */
8986 e_dev_warn("This device is a pre-production adapter/LOM. "
8987 "Please be aware there may be issues associated "
8988 "with your hardware. If you are experiencing "
8989 "problems please contact your Intel or hardware "
8990 "representative who provided you with this "
8991 "hardware.\n");
8992 }
8993 strcpy(netdev->name, "eth%d");
8994 err = register_netdev(netdev);
8995 if (err)
8996 goto err_register;
8997
8998 pci_set_drvdata(pdev, adapter);
8999
9000 /* power down the optics for 82599 SFP+ fiber */
9001 if (hw->mac.ops.disable_tx_laser)
9002 hw->mac.ops.disable_tx_laser(hw);
9003
9004 /* carrier off reporting is important to ethtool even BEFORE open */
9005 netif_carrier_off(netdev);
9006
9007 #ifdef CONFIG_IXGBE_DCA
9008 if (dca_add_requester(&pdev->dev) == 0) {
9009 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
9010 ixgbe_setup_dca(adapter);
9011 }
9012 #endif
9013 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
9014 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
9015 for (i = 0; i < adapter->num_vfs; i++)
9016 ixgbe_vf_configuration(pdev, (i | 0x10000000));
9017 }
9018
9019 /* firmware requires driver version to be 0xFFFFFFFF
9020 * since os does not support feature
9021 */
9022 if (hw->mac.ops.set_fw_drv_ver)
9023 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
9024 0xFF);
9025
9026 /* add san mac addr to netdev */
9027 ixgbe_add_sanmac_netdev(netdev);
9028
9029 e_dev_info("%s\n", ixgbe_default_device_descr);
9030
9031 #ifdef CONFIG_IXGBE_HWMON
9032 if (ixgbe_sysfs_init(adapter))
9033 e_err(probe, "failed to allocate sysfs resources\n");
9034 #endif /* CONFIG_IXGBE_HWMON */
9035
9036 ixgbe_dbg_adapter_init(adapter);
9037
9038 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
9039 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
9040 hw->mac.ops.setup_link(hw,
9041 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
9042 true);
9043
9044 return 0;
9045
9046 err_register:
9047 ixgbe_release_hw_control(adapter);
9048 ixgbe_clear_interrupt_scheme(adapter);
9049 err_sw_init:
9050 ixgbe_disable_sriov(adapter);
9051 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9052 iounmap(adapter->io_addr);
9053 kfree(adapter->mac_table);
9054 err_ioremap:
9055 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9056 free_netdev(netdev);
9057 err_alloc_etherdev:
9058 pci_release_selected_regions(pdev,
9059 pci_select_bars(pdev, IORESOURCE_MEM));
9060 err_pci_reg:
9061 err_dma:
9062 if (!adapter || disable_dev)
9063 pci_disable_device(pdev);
9064 return err;
9065 }
9066
9067 /**
9068 * ixgbe_remove - Device Removal Routine
9069 * @pdev: PCI device information struct
9070 *
9071 * ixgbe_remove is called by the PCI subsystem to alert the driver
9072 * that it should release a PCI device. The could be caused by a
9073 * Hot-Plug event, or because the driver is going to be removed from
9074 * memory.
9075 **/
9076 static void ixgbe_remove(struct pci_dev *pdev)
9077 {
9078 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9079 struct net_device *netdev;
9080 bool disable_dev;
9081
9082 /* if !adapter then we already cleaned up in probe */
9083 if (!adapter)
9084 return;
9085
9086 netdev = adapter->netdev;
9087 ixgbe_dbg_adapter_exit(adapter);
9088
9089 set_bit(__IXGBE_REMOVING, &adapter->state);
9090 cancel_work_sync(&adapter->service_task);
9091
9092
9093 #ifdef CONFIG_IXGBE_DCA
9094 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
9095 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9096 dca_remove_requester(&pdev->dev);
9097 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
9098 IXGBE_DCA_CTRL_DCA_DISABLE);
9099 }
9100
9101 #endif
9102 #ifdef CONFIG_IXGBE_HWMON
9103 ixgbe_sysfs_exit(adapter);
9104 #endif /* CONFIG_IXGBE_HWMON */
9105
9106 /* remove the added san mac */
9107 ixgbe_del_sanmac_netdev(netdev);
9108
9109 #ifdef CONFIG_PCI_IOV
9110 ixgbe_disable_sriov(adapter);
9111 #endif
9112 if (netdev->reg_state == NETREG_REGISTERED)
9113 unregister_netdev(netdev);
9114
9115 ixgbe_clear_interrupt_scheme(adapter);
9116
9117 ixgbe_release_hw_control(adapter);
9118
9119 #ifdef CONFIG_DCB
9120 kfree(adapter->ixgbe_ieee_pfc);
9121 kfree(adapter->ixgbe_ieee_ets);
9122
9123 #endif
9124 iounmap(adapter->io_addr);
9125 pci_release_selected_regions(pdev, pci_select_bars(pdev,
9126 IORESOURCE_MEM));
9127
9128 e_dev_info("complete\n");
9129
9130 kfree(adapter->mac_table);
9131 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9132 free_netdev(netdev);
9133
9134 pci_disable_pcie_error_reporting(pdev);
9135
9136 if (disable_dev)
9137 pci_disable_device(pdev);
9138 }
9139
9140 /**
9141 * ixgbe_io_error_detected - called when PCI error is detected
9142 * @pdev: Pointer to PCI device
9143 * @state: The current pci connection state
9144 *
9145 * This function is called after a PCI bus error affecting
9146 * this device has been detected.
9147 */
9148 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
9149 pci_channel_state_t state)
9150 {
9151 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9152 struct net_device *netdev = adapter->netdev;
9153
9154 #ifdef CONFIG_PCI_IOV
9155 struct ixgbe_hw *hw = &adapter->hw;
9156 struct pci_dev *bdev, *vfdev;
9157 u32 dw0, dw1, dw2, dw3;
9158 int vf, pos;
9159 u16 req_id, pf_func;
9160
9161 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
9162 adapter->num_vfs == 0)
9163 goto skip_bad_vf_detection;
9164
9165 bdev = pdev->bus->self;
9166 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
9167 bdev = bdev->bus->self;
9168
9169 if (!bdev)
9170 goto skip_bad_vf_detection;
9171
9172 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
9173 if (!pos)
9174 goto skip_bad_vf_detection;
9175
9176 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
9177 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
9178 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
9179 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
9180 if (ixgbe_removed(hw->hw_addr))
9181 goto skip_bad_vf_detection;
9182
9183 req_id = dw1 >> 16;
9184 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
9185 if (!(req_id & 0x0080))
9186 goto skip_bad_vf_detection;
9187
9188 pf_func = req_id & 0x01;
9189 if ((pf_func & 1) == (pdev->devfn & 1)) {
9190 unsigned int device_id;
9191
9192 vf = (req_id & 0x7F) >> 1;
9193 e_dev_err("VF %d has caused a PCIe error\n", vf);
9194 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
9195 "%8.8x\tdw3: %8.8x\n",
9196 dw0, dw1, dw2, dw3);
9197 switch (adapter->hw.mac.type) {
9198 case ixgbe_mac_82599EB:
9199 device_id = IXGBE_82599_VF_DEVICE_ID;
9200 break;
9201 case ixgbe_mac_X540:
9202 device_id = IXGBE_X540_VF_DEVICE_ID;
9203 break;
9204 case ixgbe_mac_X550:
9205 device_id = IXGBE_DEV_ID_X550_VF;
9206 break;
9207 case ixgbe_mac_X550EM_x:
9208 device_id = IXGBE_DEV_ID_X550EM_X_VF;
9209 break;
9210 default:
9211 device_id = 0;
9212 break;
9213 }
9214
9215 /* Find the pci device of the offending VF */
9216 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
9217 while (vfdev) {
9218 if (vfdev->devfn == (req_id & 0xFF))
9219 break;
9220 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
9221 device_id, vfdev);
9222 }
9223 /*
9224 * There's a slim chance the VF could have been hot plugged,
9225 * so if it is no longer present we don't need to issue the
9226 * VFLR. Just clean up the AER in that case.
9227 */
9228 if (vfdev) {
9229 ixgbe_issue_vf_flr(adapter, vfdev);
9230 /* Free device reference count */
9231 pci_dev_put(vfdev);
9232 }
9233
9234 pci_cleanup_aer_uncorrect_error_status(pdev);
9235 }
9236
9237 /*
9238 * Even though the error may have occurred on the other port
9239 * we still need to increment the vf error reference count for
9240 * both ports because the I/O resume function will be called
9241 * for both of them.
9242 */
9243 adapter->vferr_refcount++;
9244
9245 return PCI_ERS_RESULT_RECOVERED;
9246
9247 skip_bad_vf_detection:
9248 #endif /* CONFIG_PCI_IOV */
9249 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
9250 return PCI_ERS_RESULT_DISCONNECT;
9251
9252 rtnl_lock();
9253 netif_device_detach(netdev);
9254
9255 if (state == pci_channel_io_perm_failure) {
9256 rtnl_unlock();
9257 return PCI_ERS_RESULT_DISCONNECT;
9258 }
9259
9260 if (netif_running(netdev))
9261 ixgbe_down(adapter);
9262
9263 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
9264 pci_disable_device(pdev);
9265 rtnl_unlock();
9266
9267 /* Request a slot reset. */
9268 return PCI_ERS_RESULT_NEED_RESET;
9269 }
9270
9271 /**
9272 * ixgbe_io_slot_reset - called after the pci bus has been reset.
9273 * @pdev: Pointer to PCI device
9274 *
9275 * Restart the card from scratch, as if from a cold-boot.
9276 */
9277 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
9278 {
9279 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9280 pci_ers_result_t result;
9281 int err;
9282
9283 if (pci_enable_device_mem(pdev)) {
9284 e_err(probe, "Cannot re-enable PCI device after reset.\n");
9285 result = PCI_ERS_RESULT_DISCONNECT;
9286 } else {
9287 smp_mb__before_atomic();
9288 clear_bit(__IXGBE_DISABLED, &adapter->state);
9289 adapter->hw.hw_addr = adapter->io_addr;
9290 pci_set_master(pdev);
9291 pci_restore_state(pdev);
9292 pci_save_state(pdev);
9293
9294 pci_wake_from_d3(pdev, false);
9295
9296 ixgbe_reset(adapter);
9297 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
9298 result = PCI_ERS_RESULT_RECOVERED;
9299 }
9300
9301 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9302 if (err) {
9303 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
9304 "failed 0x%0x\n", err);
9305 /* non-fatal, continue */
9306 }
9307
9308 return result;
9309 }
9310
9311 /**
9312 * ixgbe_io_resume - called when traffic can start flowing again.
9313 * @pdev: Pointer to PCI device
9314 *
9315 * This callback is called when the error recovery driver tells us that
9316 * its OK to resume normal operation.
9317 */
9318 static void ixgbe_io_resume(struct pci_dev *pdev)
9319 {
9320 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9321 struct net_device *netdev = adapter->netdev;
9322
9323 #ifdef CONFIG_PCI_IOV
9324 if (adapter->vferr_refcount) {
9325 e_info(drv, "Resuming after VF err\n");
9326 adapter->vferr_refcount--;
9327 return;
9328 }
9329
9330 #endif
9331 if (netif_running(netdev))
9332 ixgbe_up(adapter);
9333
9334 netif_device_attach(netdev);
9335 }
9336
9337 static const struct pci_error_handlers ixgbe_err_handler = {
9338 .error_detected = ixgbe_io_error_detected,
9339 .slot_reset = ixgbe_io_slot_reset,
9340 .resume = ixgbe_io_resume,
9341 };
9342
9343 static struct pci_driver ixgbe_driver = {
9344 .name = ixgbe_driver_name,
9345 .id_table = ixgbe_pci_tbl,
9346 .probe = ixgbe_probe,
9347 .remove = ixgbe_remove,
9348 #ifdef CONFIG_PM
9349 .suspend = ixgbe_suspend,
9350 .resume = ixgbe_resume,
9351 #endif
9352 .shutdown = ixgbe_shutdown,
9353 .sriov_configure = ixgbe_pci_sriov_configure,
9354 .err_handler = &ixgbe_err_handler
9355 };
9356
9357 /**
9358 * ixgbe_init_module - Driver Registration Routine
9359 *
9360 * ixgbe_init_module is the first routine called when the driver is
9361 * loaded. All it does is register with the PCI subsystem.
9362 **/
9363 static int __init ixgbe_init_module(void)
9364 {
9365 int ret;
9366 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
9367 pr_info("%s\n", ixgbe_copyright);
9368
9369 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
9370 if (!ixgbe_wq) {
9371 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
9372 return -ENOMEM;
9373 }
9374
9375 ixgbe_dbg_init();
9376
9377 ret = pci_register_driver(&ixgbe_driver);
9378 if (ret) {
9379 ixgbe_dbg_exit();
9380 return ret;
9381 }
9382
9383 #ifdef CONFIG_IXGBE_DCA
9384 dca_register_notify(&dca_notifier);
9385 #endif
9386
9387 return 0;
9388 }
9389
9390 module_init(ixgbe_init_module);
9391
9392 /**
9393 * ixgbe_exit_module - Driver Exit Cleanup Routine
9394 *
9395 * ixgbe_exit_module is called just before the driver is removed
9396 * from memory.
9397 **/
9398 static void __exit ixgbe_exit_module(void)
9399 {
9400 #ifdef CONFIG_IXGBE_DCA
9401 dca_unregister_notify(&dca_notifier);
9402 #endif
9403 pci_unregister_driver(&ixgbe_driver);
9404
9405 ixgbe_dbg_exit();
9406 if (ixgbe_wq) {
9407 destroy_workqueue(ixgbe_wq);
9408 ixgbe_wq = NULL;
9409 }
9410 }
9411
9412 #ifdef CONFIG_IXGBE_DCA
9413 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
9414 void *p)
9415 {
9416 int ret_val;
9417
9418 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
9419 __ixgbe_notify_dca);
9420
9421 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
9422 }
9423
9424 #endif /* CONFIG_IXGBE_DCA */
9425
9426 module_exit(ixgbe_exit_module);
9427
9428 /* ixgbe_main.c */
Linux kernel - Deliverables
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