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[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/if_bridge.h>
48 #include <linux/prefetch.h>
49 #include <scsi/fc/fc_fcoe.h>
50
51 #include "ixgbe.h"
52 #include "ixgbe_common.h"
53 #include "ixgbe_dcb_82599.h"
54 #include "ixgbe_sriov.h"
55
56 char ixgbe_driver_name[] = "ixgbe";
57 static const char ixgbe_driver_string[] =
58 "Intel(R) 10 Gigabit PCI Express Network Driver";
59 #ifdef IXGBE_FCOE
60 char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
62 #else
63 static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
65 #endif
66 #define DRV_VERSION "3.15.1-k"
67 const char ixgbe_driver_version[] = DRV_VERSION;
68 static const char ixgbe_copyright[] =
69 "Copyright (c) 1999-2013 Intel Corporation.";
70
71 static const struct ixgbe_info *ixgbe_info_tbl[] = {
72 [board_82598] = &ixgbe_82598_info,
73 [board_82599] = &ixgbe_82599_info,
74 [board_X540] = &ixgbe_X540_info,
75 };
76
77 /* ixgbe_pci_tbl - PCI Device ID Table
78 *
79 * Wildcard entries (PCI_ANY_ID) should come last
80 * Last entry must be all 0s
81 *
82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
83 * Class, Class Mask, private data (not used) }
84 */
85 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
116 /* required last entry */
117 {0, }
118 };
119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
120
121 #ifdef CONFIG_IXGBE_DCA
122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
123 void *p);
124 static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
126 .next = NULL,
127 .priority = 0
128 };
129 #endif
130
131 #ifdef CONFIG_PCI_IOV
132 static unsigned int max_vfs;
133 module_param(max_vfs, uint, 0);
134 MODULE_PARM_DESC(max_vfs,
135 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
136 #endif /* CONFIG_PCI_IOV */
137
138 static unsigned int allow_unsupported_sfp;
139 module_param(allow_unsupported_sfp, uint, 0);
140 MODULE_PARM_DESC(allow_unsupported_sfp,
141 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
142
143 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
144 static int debug = -1;
145 module_param(debug, int, 0);
146 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
147
148 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
149 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
150 MODULE_LICENSE("GPL");
151 MODULE_VERSION(DRV_VERSION);
152
153 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
154 u32 reg, u16 *value)
155 {
156 struct pci_dev *parent_dev;
157 struct pci_bus *parent_bus;
158
159 parent_bus = adapter->pdev->bus->parent;
160 if (!parent_bus)
161 return -1;
162
163 parent_dev = parent_bus->self;
164 if (!parent_dev)
165 return -1;
166
167 if (!pci_is_pcie(parent_dev))
168 return -1;
169
170 pcie_capability_read_word(parent_dev, reg, value);
171 return 0;
172 }
173
174 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
175 {
176 struct ixgbe_hw *hw = &adapter->hw;
177 u16 link_status = 0;
178 int err;
179
180 hw->bus.type = ixgbe_bus_type_pci_express;
181
182 /* Get the negotiated link width and speed from PCI config space of the
183 * parent, as this device is behind a switch
184 */
185 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
186
187 /* assume caller will handle error case */
188 if (err)
189 return err;
190
191 hw->bus.width = ixgbe_convert_bus_width(link_status);
192 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
193
194 return 0;
195 }
196
197 /**
198 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
199 * @hw: hw specific details
200 *
201 * This function is used by probe to determine whether a device's PCI-Express
202 * bandwidth details should be gathered from the parent bus instead of from the
203 * device. Used to ensure that various locations all have the correct device ID
204 * checks.
205 */
206 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
207 {
208 switch (hw->device_id) {
209 case IXGBE_DEV_ID_82599_SFP_SF_QP:
210 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
211 return true;
212 default:
213 return false;
214 }
215 }
216
217 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
218 int expected_gts)
219 {
220 int max_gts = 0;
221 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
222 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
223 struct pci_dev *pdev;
224
225 /* determine whether to use the the parent device
226 */
227 if (ixgbe_pcie_from_parent(&adapter->hw))
228 pdev = adapter->pdev->bus->parent->self;
229 else
230 pdev = adapter->pdev;
231
232 if (pcie_get_minimum_link(pdev, &speed, &width) ||
233 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
234 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
235 return;
236 }
237
238 switch (speed) {
239 case PCIE_SPEED_2_5GT:
240 /* 8b/10b encoding reduces max throughput by 20% */
241 max_gts = 2 * width;
242 break;
243 case PCIE_SPEED_5_0GT:
244 /* 8b/10b encoding reduces max throughput by 20% */
245 max_gts = 4 * width;
246 break;
247 case PCIE_SPEED_8_0GT:
248 /* 128b/130b encoding reduces throughput by less than 2% */
249 max_gts = 8 * width;
250 break;
251 default:
252 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
253 return;
254 }
255
256 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
257 max_gts);
258 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
259 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
260 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
261 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
262 "Unknown"),
263 width,
264 (speed == PCIE_SPEED_2_5GT ? "20%" :
265 speed == PCIE_SPEED_5_0GT ? "20%" :
266 speed == PCIE_SPEED_8_0GT ? "<2%" :
267 "Unknown"));
268
269 if (max_gts < expected_gts) {
270 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
271 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
272 expected_gts);
273 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
274 }
275 }
276
277 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
278 {
279 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
280 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
281 schedule_work(&adapter->service_task);
282 }
283
284 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
285 {
286 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
287
288 /* flush memory to make sure state is correct before next watchdog */
289 smp_mb__before_clear_bit();
290 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
291 }
292
293 struct ixgbe_reg_info {
294 u32 ofs;
295 char *name;
296 };
297
298 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
299
300 /* General Registers */
301 {IXGBE_CTRL, "CTRL"},
302 {IXGBE_STATUS, "STATUS"},
303 {IXGBE_CTRL_EXT, "CTRL_EXT"},
304
305 /* Interrupt Registers */
306 {IXGBE_EICR, "EICR"},
307
308 /* RX Registers */
309 {IXGBE_SRRCTL(0), "SRRCTL"},
310 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
311 {IXGBE_RDLEN(0), "RDLEN"},
312 {IXGBE_RDH(0), "RDH"},
313 {IXGBE_RDT(0), "RDT"},
314 {IXGBE_RXDCTL(0), "RXDCTL"},
315 {IXGBE_RDBAL(0), "RDBAL"},
316 {IXGBE_RDBAH(0), "RDBAH"},
317
318 /* TX Registers */
319 {IXGBE_TDBAL(0), "TDBAL"},
320 {IXGBE_TDBAH(0), "TDBAH"},
321 {IXGBE_TDLEN(0), "TDLEN"},
322 {IXGBE_TDH(0), "TDH"},
323 {IXGBE_TDT(0), "TDT"},
324 {IXGBE_TXDCTL(0), "TXDCTL"},
325
326 /* List Terminator */
327 {}
328 };
329
330
331 /*
332 * ixgbe_regdump - register printout routine
333 */
334 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
335 {
336 int i = 0, j = 0;
337 char rname[16];
338 u32 regs[64];
339
340 switch (reginfo->ofs) {
341 case IXGBE_SRRCTL(0):
342 for (i = 0; i < 64; i++)
343 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
344 break;
345 case IXGBE_DCA_RXCTRL(0):
346 for (i = 0; i < 64; i++)
347 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
348 break;
349 case IXGBE_RDLEN(0):
350 for (i = 0; i < 64; i++)
351 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
352 break;
353 case IXGBE_RDH(0):
354 for (i = 0; i < 64; i++)
355 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
356 break;
357 case IXGBE_RDT(0):
358 for (i = 0; i < 64; i++)
359 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
360 break;
361 case IXGBE_RXDCTL(0):
362 for (i = 0; i < 64; i++)
363 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
364 break;
365 case IXGBE_RDBAL(0):
366 for (i = 0; i < 64; i++)
367 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
368 break;
369 case IXGBE_RDBAH(0):
370 for (i = 0; i < 64; i++)
371 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
372 break;
373 case IXGBE_TDBAL(0):
374 for (i = 0; i < 64; i++)
375 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
376 break;
377 case IXGBE_TDBAH(0):
378 for (i = 0; i < 64; i++)
379 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
380 break;
381 case IXGBE_TDLEN(0):
382 for (i = 0; i < 64; i++)
383 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
384 break;
385 case IXGBE_TDH(0):
386 for (i = 0; i < 64; i++)
387 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
388 break;
389 case IXGBE_TDT(0):
390 for (i = 0; i < 64; i++)
391 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
392 break;
393 case IXGBE_TXDCTL(0):
394 for (i = 0; i < 64; i++)
395 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
396 break;
397 default:
398 pr_info("%-15s %08x\n", reginfo->name,
399 IXGBE_READ_REG(hw, reginfo->ofs));
400 return;
401 }
402
403 for (i = 0; i < 8; i++) {
404 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
405 pr_err("%-15s", rname);
406 for (j = 0; j < 8; j++)
407 pr_cont(" %08x", regs[i*8+j]);
408 pr_cont("\n");
409 }
410
411 }
412
413 /*
414 * ixgbe_dump - Print registers, tx-rings and rx-rings
415 */
416 static void ixgbe_dump(struct ixgbe_adapter *adapter)
417 {
418 struct net_device *netdev = adapter->netdev;
419 struct ixgbe_hw *hw = &adapter->hw;
420 struct ixgbe_reg_info *reginfo;
421 int n = 0;
422 struct ixgbe_ring *tx_ring;
423 struct ixgbe_tx_buffer *tx_buffer;
424 union ixgbe_adv_tx_desc *tx_desc;
425 struct my_u0 { u64 a; u64 b; } *u0;
426 struct ixgbe_ring *rx_ring;
427 union ixgbe_adv_rx_desc *rx_desc;
428 struct ixgbe_rx_buffer *rx_buffer_info;
429 u32 staterr;
430 int i = 0;
431
432 if (!netif_msg_hw(adapter))
433 return;
434
435 /* Print netdevice Info */
436 if (netdev) {
437 dev_info(&adapter->pdev->dev, "Net device Info\n");
438 pr_info("Device Name state "
439 "trans_start last_rx\n");
440 pr_info("%-15s %016lX %016lX %016lX\n",
441 netdev->name,
442 netdev->state,
443 netdev->trans_start,
444 netdev->last_rx);
445 }
446
447 /* Print Registers */
448 dev_info(&adapter->pdev->dev, "Register Dump\n");
449 pr_info(" Register Name Value\n");
450 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
451 reginfo->name; reginfo++) {
452 ixgbe_regdump(hw, reginfo);
453 }
454
455 /* Print TX Ring Summary */
456 if (!netdev || !netif_running(netdev))
457 goto exit;
458
459 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
460 pr_info(" %s %s %s %s\n",
461 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
462 "leng", "ntw", "timestamp");
463 for (n = 0; n < adapter->num_tx_queues; n++) {
464 tx_ring = adapter->tx_ring[n];
465 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
466 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
467 n, tx_ring->next_to_use, tx_ring->next_to_clean,
468 (u64)dma_unmap_addr(tx_buffer, dma),
469 dma_unmap_len(tx_buffer, len),
470 tx_buffer->next_to_watch,
471 (u64)tx_buffer->time_stamp);
472 }
473
474 /* Print TX Rings */
475 if (!netif_msg_tx_done(adapter))
476 goto rx_ring_summary;
477
478 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
479
480 /* Transmit Descriptor Formats
481 *
482 * 82598 Advanced Transmit Descriptor
483 * +--------------------------------------------------------------+
484 * 0 | Buffer Address [63:0] |
485 * +--------------------------------------------------------------+
486 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
487 * +--------------------------------------------------------------+
488 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
489 *
490 * 82598 Advanced Transmit Descriptor (Write-Back Format)
491 * +--------------------------------------------------------------+
492 * 0 | RSV [63:0] |
493 * +--------------------------------------------------------------+
494 * 8 | RSV | STA | NXTSEQ |
495 * +--------------------------------------------------------------+
496 * 63 36 35 32 31 0
497 *
498 * 82599+ Advanced Transmit Descriptor
499 * +--------------------------------------------------------------+
500 * 0 | Buffer Address [63:0] |
501 * +--------------------------------------------------------------+
502 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
503 * +--------------------------------------------------------------+
504 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
505 *
506 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
507 * +--------------------------------------------------------------+
508 * 0 | RSV [63:0] |
509 * +--------------------------------------------------------------+
510 * 8 | RSV | STA | RSV |
511 * +--------------------------------------------------------------+
512 * 63 36 35 32 31 0
513 */
514
515 for (n = 0; n < adapter->num_tx_queues; n++) {
516 tx_ring = adapter->tx_ring[n];
517 pr_info("------------------------------------\n");
518 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
519 pr_info("------------------------------------\n");
520 pr_info("%s%s %s %s %s %s\n",
521 "T [desc] [address 63:0 ] ",
522 "[PlPOIdStDDt Ln] [bi->dma ] ",
523 "leng", "ntw", "timestamp", "bi->skb");
524
525 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
526 tx_desc = IXGBE_TX_DESC(tx_ring, i);
527 tx_buffer = &tx_ring->tx_buffer_info[i];
528 u0 = (struct my_u0 *)tx_desc;
529 if (dma_unmap_len(tx_buffer, len) > 0) {
530 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
531 i,
532 le64_to_cpu(u0->a),
533 le64_to_cpu(u0->b),
534 (u64)dma_unmap_addr(tx_buffer, dma),
535 dma_unmap_len(tx_buffer, len),
536 tx_buffer->next_to_watch,
537 (u64)tx_buffer->time_stamp,
538 tx_buffer->skb);
539 if (i == tx_ring->next_to_use &&
540 i == tx_ring->next_to_clean)
541 pr_cont(" NTC/U\n");
542 else if (i == tx_ring->next_to_use)
543 pr_cont(" NTU\n");
544 else if (i == tx_ring->next_to_clean)
545 pr_cont(" NTC\n");
546 else
547 pr_cont("\n");
548
549 if (netif_msg_pktdata(adapter) &&
550 tx_buffer->skb)
551 print_hex_dump(KERN_INFO, "",
552 DUMP_PREFIX_ADDRESS, 16, 1,
553 tx_buffer->skb->data,
554 dma_unmap_len(tx_buffer, len),
555 true);
556 }
557 }
558 }
559
560 /* Print RX Rings Summary */
561 rx_ring_summary:
562 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
563 pr_info("Queue [NTU] [NTC]\n");
564 for (n = 0; n < adapter->num_rx_queues; n++) {
565 rx_ring = adapter->rx_ring[n];
566 pr_info("%5d %5X %5X\n",
567 n, rx_ring->next_to_use, rx_ring->next_to_clean);
568 }
569
570 /* Print RX Rings */
571 if (!netif_msg_rx_status(adapter))
572 goto exit;
573
574 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
575
576 /* Receive Descriptor Formats
577 *
578 * 82598 Advanced Receive Descriptor (Read) Format
579 * 63 1 0
580 * +-----------------------------------------------------+
581 * 0 | Packet Buffer Address [63:1] |A0/NSE|
582 * +----------------------------------------------+------+
583 * 8 | Header Buffer Address [63:1] | DD |
584 * +-----------------------------------------------------+
585 *
586 *
587 * 82598 Advanced Receive Descriptor (Write-Back) Format
588 *
589 * 63 48 47 32 31 30 21 20 16 15 4 3 0
590 * +------------------------------------------------------+
591 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
592 * | Packet | IP | | | | Type | Type |
593 * | Checksum | Ident | | | | | |
594 * +------------------------------------------------------+
595 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
596 * +------------------------------------------------------+
597 * 63 48 47 32 31 20 19 0
598 *
599 * 82599+ Advanced Receive Descriptor (Read) Format
600 * 63 1 0
601 * +-----------------------------------------------------+
602 * 0 | Packet Buffer Address [63:1] |A0/NSE|
603 * +----------------------------------------------+------+
604 * 8 | Header Buffer Address [63:1] | DD |
605 * +-----------------------------------------------------+
606 *
607 *
608 * 82599+ Advanced Receive Descriptor (Write-Back) Format
609 *
610 * 63 48 47 32 31 30 21 20 17 16 4 3 0
611 * +------------------------------------------------------+
612 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
613 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
614 * |/ Flow Dir Flt ID | | | | | |
615 * +------------------------------------------------------+
616 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
617 * +------------------------------------------------------+
618 * 63 48 47 32 31 20 19 0
619 */
620
621 for (n = 0; n < adapter->num_rx_queues; n++) {
622 rx_ring = adapter->rx_ring[n];
623 pr_info("------------------------------------\n");
624 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
625 pr_info("------------------------------------\n");
626 pr_info("%s%s%s",
627 "R [desc] [ PktBuf A0] ",
628 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
629 "<-- Adv Rx Read format\n");
630 pr_info("%s%s%s",
631 "RWB[desc] [PcsmIpSHl PtRs] ",
632 "[vl er S cks ln] ---------------- [bi->skb ] ",
633 "<-- Adv Rx Write-Back format\n");
634
635 for (i = 0; i < rx_ring->count; i++) {
636 rx_buffer_info = &rx_ring->rx_buffer_info[i];
637 rx_desc = IXGBE_RX_DESC(rx_ring, i);
638 u0 = (struct my_u0 *)rx_desc;
639 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
640 if (staterr & IXGBE_RXD_STAT_DD) {
641 /* Descriptor Done */
642 pr_info("RWB[0x%03X] %016llX "
643 "%016llX ---------------- %p", i,
644 le64_to_cpu(u0->a),
645 le64_to_cpu(u0->b),
646 rx_buffer_info->skb);
647 } else {
648 pr_info("R [0x%03X] %016llX "
649 "%016llX %016llX %p", i,
650 le64_to_cpu(u0->a),
651 le64_to_cpu(u0->b),
652 (u64)rx_buffer_info->dma,
653 rx_buffer_info->skb);
654
655 if (netif_msg_pktdata(adapter) &&
656 rx_buffer_info->dma) {
657 print_hex_dump(KERN_INFO, "",
658 DUMP_PREFIX_ADDRESS, 16, 1,
659 page_address(rx_buffer_info->page) +
660 rx_buffer_info->page_offset,
661 ixgbe_rx_bufsz(rx_ring), true);
662 }
663 }
664
665 if (i == rx_ring->next_to_use)
666 pr_cont(" NTU\n");
667 else if (i == rx_ring->next_to_clean)
668 pr_cont(" NTC\n");
669 else
670 pr_cont("\n");
671
672 }
673 }
674
675 exit:
676 return;
677 }
678
679 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
680 {
681 u32 ctrl_ext;
682
683 /* Let firmware take over control of h/w */
684 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
685 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
686 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
687 }
688
689 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
690 {
691 u32 ctrl_ext;
692
693 /* Let firmware know the driver has taken over */
694 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
695 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
696 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
697 }
698
699 /**
700 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
701 * @adapter: pointer to adapter struct
702 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
703 * @queue: queue to map the corresponding interrupt to
704 * @msix_vector: the vector to map to the corresponding queue
705 *
706 */
707 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
708 u8 queue, u8 msix_vector)
709 {
710 u32 ivar, index;
711 struct ixgbe_hw *hw = &adapter->hw;
712 switch (hw->mac.type) {
713 case ixgbe_mac_82598EB:
714 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
715 if (direction == -1)
716 direction = 0;
717 index = (((direction * 64) + queue) >> 2) & 0x1F;
718 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
719 ivar &= ~(0xFF << (8 * (queue & 0x3)));
720 ivar |= (msix_vector << (8 * (queue & 0x3)));
721 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
722 break;
723 case ixgbe_mac_82599EB:
724 case ixgbe_mac_X540:
725 if (direction == -1) {
726 /* other causes */
727 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
728 index = ((queue & 1) * 8);
729 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
730 ivar &= ~(0xFF << index);
731 ivar |= (msix_vector << index);
732 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
733 break;
734 } else {
735 /* tx or rx causes */
736 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
737 index = ((16 * (queue & 1)) + (8 * direction));
738 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
739 ivar &= ~(0xFF << index);
740 ivar |= (msix_vector << index);
741 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
742 break;
743 }
744 default:
745 break;
746 }
747 }
748
749 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
750 u64 qmask)
751 {
752 u32 mask;
753
754 switch (adapter->hw.mac.type) {
755 case ixgbe_mac_82598EB:
756 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
757 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
758 break;
759 case ixgbe_mac_82599EB:
760 case ixgbe_mac_X540:
761 mask = (qmask & 0xFFFFFFFF);
762 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
763 mask = (qmask >> 32);
764 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
765 break;
766 default:
767 break;
768 }
769 }
770
771 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
772 struct ixgbe_tx_buffer *tx_buffer)
773 {
774 if (tx_buffer->skb) {
775 dev_kfree_skb_any(tx_buffer->skb);
776 if (dma_unmap_len(tx_buffer, len))
777 dma_unmap_single(ring->dev,
778 dma_unmap_addr(tx_buffer, dma),
779 dma_unmap_len(tx_buffer, len),
780 DMA_TO_DEVICE);
781 } else if (dma_unmap_len(tx_buffer, len)) {
782 dma_unmap_page(ring->dev,
783 dma_unmap_addr(tx_buffer, dma),
784 dma_unmap_len(tx_buffer, len),
785 DMA_TO_DEVICE);
786 }
787 tx_buffer->next_to_watch = NULL;
788 tx_buffer->skb = NULL;
789 dma_unmap_len_set(tx_buffer, len, 0);
790 /* tx_buffer must be completely set up in the transmit path */
791 }
792
793 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
794 {
795 struct ixgbe_hw *hw = &adapter->hw;
796 struct ixgbe_hw_stats *hwstats = &adapter->stats;
797 int i;
798 u32 data;
799
800 if ((hw->fc.current_mode != ixgbe_fc_full) &&
801 (hw->fc.current_mode != ixgbe_fc_rx_pause))
802 return;
803
804 switch (hw->mac.type) {
805 case ixgbe_mac_82598EB:
806 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
807 break;
808 default:
809 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
810 }
811 hwstats->lxoffrxc += data;
812
813 /* refill credits (no tx hang) if we received xoff */
814 if (!data)
815 return;
816
817 for (i = 0; i < adapter->num_tx_queues; i++)
818 clear_bit(__IXGBE_HANG_CHECK_ARMED,
819 &adapter->tx_ring[i]->state);
820 }
821
822 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
823 {
824 struct ixgbe_hw *hw = &adapter->hw;
825 struct ixgbe_hw_stats *hwstats = &adapter->stats;
826 u32 xoff[8] = {0};
827 u8 tc;
828 int i;
829 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
830
831 if (adapter->ixgbe_ieee_pfc)
832 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
833
834 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
835 ixgbe_update_xoff_rx_lfc(adapter);
836 return;
837 }
838
839 /* update stats for each tc, only valid with PFC enabled */
840 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
841 u32 pxoffrxc;
842
843 switch (hw->mac.type) {
844 case ixgbe_mac_82598EB:
845 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
846 break;
847 default:
848 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
849 }
850 hwstats->pxoffrxc[i] += pxoffrxc;
851 /* Get the TC for given UP */
852 tc = netdev_get_prio_tc_map(adapter->netdev, i);
853 xoff[tc] += pxoffrxc;
854 }
855
856 /* disarm tx queues that have received xoff frames */
857 for (i = 0; i < adapter->num_tx_queues; i++) {
858 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
859
860 tc = tx_ring->dcb_tc;
861 if (xoff[tc])
862 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
863 }
864 }
865
866 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
867 {
868 return ring->stats.packets;
869 }
870
871 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
872 {
873 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
874 struct ixgbe_hw *hw = &adapter->hw;
875
876 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
877 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
878
879 if (head != tail)
880 return (head < tail) ?
881 tail - head : (tail + ring->count - head);
882
883 return 0;
884 }
885
886 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
887 {
888 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
889 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
890 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
891 bool ret = false;
892
893 clear_check_for_tx_hang(tx_ring);
894
895 /*
896 * Check for a hung queue, but be thorough. This verifies
897 * that a transmit has been completed since the previous
898 * check AND there is at least one packet pending. The
899 * ARMED bit is set to indicate a potential hang. The
900 * bit is cleared if a pause frame is received to remove
901 * false hang detection due to PFC or 802.3x frames. By
902 * requiring this to fail twice we avoid races with
903 * pfc clearing the ARMED bit and conditions where we
904 * run the check_tx_hang logic with a transmit completion
905 * pending but without time to complete it yet.
906 */
907 if ((tx_done_old == tx_done) && tx_pending) {
908 /* make sure it is true for two checks in a row */
909 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
910 &tx_ring->state);
911 } else {
912 /* update completed stats and continue */
913 tx_ring->tx_stats.tx_done_old = tx_done;
914 /* reset the countdown */
915 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
916 }
917
918 return ret;
919 }
920
921 /**
922 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
923 * @adapter: driver private struct
924 **/
925 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
926 {
927
928 /* Do the reset outside of interrupt context */
929 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
930 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
931 e_warn(drv, "initiating reset due to tx timeout\n");
932 ixgbe_service_event_schedule(adapter);
933 }
934 }
935
936 /**
937 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
938 * @q_vector: structure containing interrupt and ring information
939 * @tx_ring: tx ring to clean
940 **/
941 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
942 struct ixgbe_ring *tx_ring)
943 {
944 struct ixgbe_adapter *adapter = q_vector->adapter;
945 struct ixgbe_tx_buffer *tx_buffer;
946 union ixgbe_adv_tx_desc *tx_desc;
947 unsigned int total_bytes = 0, total_packets = 0;
948 unsigned int budget = q_vector->tx.work_limit;
949 unsigned int i = tx_ring->next_to_clean;
950
951 if (test_bit(__IXGBE_DOWN, &adapter->state))
952 return true;
953
954 tx_buffer = &tx_ring->tx_buffer_info[i];
955 tx_desc = IXGBE_TX_DESC(tx_ring, i);
956 i -= tx_ring->count;
957
958 do {
959 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
960
961 /* if next_to_watch is not set then there is no work pending */
962 if (!eop_desc)
963 break;
964
965 /* prevent any other reads prior to eop_desc */
966 read_barrier_depends();
967
968 /* if DD is not set pending work has not been completed */
969 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
970 break;
971
972 /* clear next_to_watch to prevent false hangs */
973 tx_buffer->next_to_watch = NULL;
974
975 /* update the statistics for this packet */
976 total_bytes += tx_buffer->bytecount;
977 total_packets += tx_buffer->gso_segs;
978
979 /* free the skb */
980 dev_kfree_skb_any(tx_buffer->skb);
981
982 /* unmap skb header data */
983 dma_unmap_single(tx_ring->dev,
984 dma_unmap_addr(tx_buffer, dma),
985 dma_unmap_len(tx_buffer, len),
986 DMA_TO_DEVICE);
987
988 /* clear tx_buffer data */
989 tx_buffer->skb = NULL;
990 dma_unmap_len_set(tx_buffer, len, 0);
991
992 /* unmap remaining buffers */
993 while (tx_desc != eop_desc) {
994 tx_buffer++;
995 tx_desc++;
996 i++;
997 if (unlikely(!i)) {
998 i -= tx_ring->count;
999 tx_buffer = tx_ring->tx_buffer_info;
1000 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1001 }
1002
1003 /* unmap any remaining paged data */
1004 if (dma_unmap_len(tx_buffer, len)) {
1005 dma_unmap_page(tx_ring->dev,
1006 dma_unmap_addr(tx_buffer, dma),
1007 dma_unmap_len(tx_buffer, len),
1008 DMA_TO_DEVICE);
1009 dma_unmap_len_set(tx_buffer, len, 0);
1010 }
1011 }
1012
1013 /* move us one more past the eop_desc for start of next pkt */
1014 tx_buffer++;
1015 tx_desc++;
1016 i++;
1017 if (unlikely(!i)) {
1018 i -= tx_ring->count;
1019 tx_buffer = tx_ring->tx_buffer_info;
1020 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1021 }
1022
1023 /* issue prefetch for next Tx descriptor */
1024 prefetch(tx_desc);
1025
1026 /* update budget accounting */
1027 budget--;
1028 } while (likely(budget));
1029
1030 i += tx_ring->count;
1031 tx_ring->next_to_clean = i;
1032 u64_stats_update_begin(&tx_ring->syncp);
1033 tx_ring->stats.bytes += total_bytes;
1034 tx_ring->stats.packets += total_packets;
1035 u64_stats_update_end(&tx_ring->syncp);
1036 q_vector->tx.total_bytes += total_bytes;
1037 q_vector->tx.total_packets += total_packets;
1038
1039 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1040 /* schedule immediate reset if we believe we hung */
1041 struct ixgbe_hw *hw = &adapter->hw;
1042 e_err(drv, "Detected Tx Unit Hang\n"
1043 " Tx Queue <%d>\n"
1044 " TDH, TDT <%x>, <%x>\n"
1045 " next_to_use <%x>\n"
1046 " next_to_clean <%x>\n"
1047 "tx_buffer_info[next_to_clean]\n"
1048 " time_stamp <%lx>\n"
1049 " jiffies <%lx>\n",
1050 tx_ring->queue_index,
1051 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1052 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1053 tx_ring->next_to_use, i,
1054 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1055
1056 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1057
1058 e_info(probe,
1059 "tx hang %d detected on queue %d, resetting adapter\n",
1060 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1061
1062 /* schedule immediate reset if we believe we hung */
1063 ixgbe_tx_timeout_reset(adapter);
1064
1065 /* the adapter is about to reset, no point in enabling stuff */
1066 return true;
1067 }
1068
1069 netdev_tx_completed_queue(txring_txq(tx_ring),
1070 total_packets, total_bytes);
1071
1072 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1073 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1074 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1075 /* Make sure that anybody stopping the queue after this
1076 * sees the new next_to_clean.
1077 */
1078 smp_mb();
1079 if (__netif_subqueue_stopped(tx_ring->netdev,
1080 tx_ring->queue_index)
1081 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1082 netif_wake_subqueue(tx_ring->netdev,
1083 tx_ring->queue_index);
1084 ++tx_ring->tx_stats.restart_queue;
1085 }
1086 }
1087
1088 return !!budget;
1089 }
1090
1091 #ifdef CONFIG_IXGBE_DCA
1092 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1093 struct ixgbe_ring *tx_ring,
1094 int cpu)
1095 {
1096 struct ixgbe_hw *hw = &adapter->hw;
1097 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1098 u16 reg_offset;
1099
1100 switch (hw->mac.type) {
1101 case ixgbe_mac_82598EB:
1102 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1103 break;
1104 case ixgbe_mac_82599EB:
1105 case ixgbe_mac_X540:
1106 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1107 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1108 break;
1109 default:
1110 /* for unknown hardware do not write register */
1111 return;
1112 }
1113
1114 /*
1115 * We can enable relaxed ordering for reads, but not writes when
1116 * DCA is enabled. This is due to a known issue in some chipsets
1117 * which will cause the DCA tag to be cleared.
1118 */
1119 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1120 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1121 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1122
1123 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1124 }
1125
1126 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1127 struct ixgbe_ring *rx_ring,
1128 int cpu)
1129 {
1130 struct ixgbe_hw *hw = &adapter->hw;
1131 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1132 u8 reg_idx = rx_ring->reg_idx;
1133
1134
1135 switch (hw->mac.type) {
1136 case ixgbe_mac_82599EB:
1137 case ixgbe_mac_X540:
1138 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1139 break;
1140 default:
1141 break;
1142 }
1143
1144 /*
1145 * We can enable relaxed ordering for reads, but not writes when
1146 * DCA is enabled. This is due to a known issue in some chipsets
1147 * which will cause the DCA tag to be cleared.
1148 */
1149 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1150 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1151
1152 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1153 }
1154
1155 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1156 {
1157 struct ixgbe_adapter *adapter = q_vector->adapter;
1158 struct ixgbe_ring *ring;
1159 int cpu = get_cpu();
1160
1161 if (q_vector->cpu == cpu)
1162 goto out_no_update;
1163
1164 ixgbe_for_each_ring(ring, q_vector->tx)
1165 ixgbe_update_tx_dca(adapter, ring, cpu);
1166
1167 ixgbe_for_each_ring(ring, q_vector->rx)
1168 ixgbe_update_rx_dca(adapter, ring, cpu);
1169
1170 q_vector->cpu = cpu;
1171 out_no_update:
1172 put_cpu();
1173 }
1174
1175 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1176 {
1177 int i;
1178
1179 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1180 return;
1181
1182 /* always use CB2 mode, difference is masked in the CB driver */
1183 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1184
1185 for (i = 0; i < adapter->num_q_vectors; i++) {
1186 adapter->q_vector[i]->cpu = -1;
1187 ixgbe_update_dca(adapter->q_vector[i]);
1188 }
1189 }
1190
1191 static int __ixgbe_notify_dca(struct device *dev, void *data)
1192 {
1193 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1194 unsigned long event = *(unsigned long *)data;
1195
1196 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1197 return 0;
1198
1199 switch (event) {
1200 case DCA_PROVIDER_ADD:
1201 /* if we're already enabled, don't do it again */
1202 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1203 break;
1204 if (dca_add_requester(dev) == 0) {
1205 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1206 ixgbe_setup_dca(adapter);
1207 break;
1208 }
1209 /* Fall Through since DCA is disabled. */
1210 case DCA_PROVIDER_REMOVE:
1211 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1212 dca_remove_requester(dev);
1213 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1214 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1215 }
1216 break;
1217 }
1218
1219 return 0;
1220 }
1221
1222 #endif /* CONFIG_IXGBE_DCA */
1223 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1224 union ixgbe_adv_rx_desc *rx_desc,
1225 struct sk_buff *skb)
1226 {
1227 if (ring->netdev->features & NETIF_F_RXHASH)
1228 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1229 }
1230
1231 #ifdef IXGBE_FCOE
1232 /**
1233 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1234 * @ring: structure containing ring specific data
1235 * @rx_desc: advanced rx descriptor
1236 *
1237 * Returns : true if it is FCoE pkt
1238 */
1239 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1240 union ixgbe_adv_rx_desc *rx_desc)
1241 {
1242 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1243
1244 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1245 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1246 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1247 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1248 }
1249
1250 #endif /* IXGBE_FCOE */
1251 /**
1252 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1253 * @ring: structure containing ring specific data
1254 * @rx_desc: current Rx descriptor being processed
1255 * @skb: skb currently being received and modified
1256 **/
1257 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1258 union ixgbe_adv_rx_desc *rx_desc,
1259 struct sk_buff *skb)
1260 {
1261 skb_checksum_none_assert(skb);
1262
1263 /* Rx csum disabled */
1264 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1265 return;
1266
1267 /* if IP and error */
1268 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1269 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1270 ring->rx_stats.csum_err++;
1271 return;
1272 }
1273
1274 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1275 return;
1276
1277 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1278 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1279
1280 /*
1281 * 82599 errata, UDP frames with a 0 checksum can be marked as
1282 * checksum errors.
1283 */
1284 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1285 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1286 return;
1287
1288 ring->rx_stats.csum_err++;
1289 return;
1290 }
1291
1292 /* It must be a TCP or UDP packet with a valid checksum */
1293 skb->ip_summed = CHECKSUM_UNNECESSARY;
1294 }
1295
1296 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1297 {
1298 rx_ring->next_to_use = val;
1299
1300 /* update next to alloc since we have filled the ring */
1301 rx_ring->next_to_alloc = val;
1302 /*
1303 * Force memory writes to complete before letting h/w
1304 * know there are new descriptors to fetch. (Only
1305 * applicable for weak-ordered memory model archs,
1306 * such as IA-64).
1307 */
1308 wmb();
1309 writel(val, rx_ring->tail);
1310 }
1311
1312 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1313 struct ixgbe_rx_buffer *bi)
1314 {
1315 struct page *page = bi->page;
1316 dma_addr_t dma = bi->dma;
1317
1318 /* since we are recycling buffers we should seldom need to alloc */
1319 if (likely(dma))
1320 return true;
1321
1322 /* alloc new page for storage */
1323 if (likely(!page)) {
1324 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1325 bi->skb, ixgbe_rx_pg_order(rx_ring));
1326 if (unlikely(!page)) {
1327 rx_ring->rx_stats.alloc_rx_page_failed++;
1328 return false;
1329 }
1330 bi->page = page;
1331 }
1332
1333 /* map page for use */
1334 dma = dma_map_page(rx_ring->dev, page, 0,
1335 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1336
1337 /*
1338 * if mapping failed free memory back to system since
1339 * there isn't much point in holding memory we can't use
1340 */
1341 if (dma_mapping_error(rx_ring->dev, dma)) {
1342 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1343 bi->page = NULL;
1344
1345 rx_ring->rx_stats.alloc_rx_page_failed++;
1346 return false;
1347 }
1348
1349 bi->dma = dma;
1350 bi->page_offset = 0;
1351
1352 return true;
1353 }
1354
1355 /**
1356 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1357 * @rx_ring: ring to place buffers on
1358 * @cleaned_count: number of buffers to replace
1359 **/
1360 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1361 {
1362 union ixgbe_adv_rx_desc *rx_desc;
1363 struct ixgbe_rx_buffer *bi;
1364 u16 i = rx_ring->next_to_use;
1365
1366 /* nothing to do */
1367 if (!cleaned_count)
1368 return;
1369
1370 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1371 bi = &rx_ring->rx_buffer_info[i];
1372 i -= rx_ring->count;
1373
1374 do {
1375 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1376 break;
1377
1378 /*
1379 * Refresh the desc even if buffer_addrs didn't change
1380 * because each write-back erases this info.
1381 */
1382 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1383
1384 rx_desc++;
1385 bi++;
1386 i++;
1387 if (unlikely(!i)) {
1388 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1389 bi = rx_ring->rx_buffer_info;
1390 i -= rx_ring->count;
1391 }
1392
1393 /* clear the hdr_addr for the next_to_use descriptor */
1394 rx_desc->read.hdr_addr = 0;
1395
1396 cleaned_count--;
1397 } while (cleaned_count);
1398
1399 i += rx_ring->count;
1400
1401 if (rx_ring->next_to_use != i)
1402 ixgbe_release_rx_desc(rx_ring, i);
1403 }
1404
1405 /**
1406 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1407 * @data: pointer to the start of the headers
1408 * @max_len: total length of section to find headers in
1409 *
1410 * This function is meant to determine the length of headers that will
1411 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1412 * motivation of doing this is to only perform one pull for IPv4 TCP
1413 * packets so that we can do basic things like calculating the gso_size
1414 * based on the average data per packet.
1415 **/
1416 static unsigned int ixgbe_get_headlen(unsigned char *data,
1417 unsigned int max_len)
1418 {
1419 union {
1420 unsigned char *network;
1421 /* l2 headers */
1422 struct ethhdr *eth;
1423 struct vlan_hdr *vlan;
1424 /* l3 headers */
1425 struct iphdr *ipv4;
1426 struct ipv6hdr *ipv6;
1427 } hdr;
1428 __be16 protocol;
1429 u8 nexthdr = 0; /* default to not TCP */
1430 u8 hlen;
1431
1432 /* this should never happen, but better safe than sorry */
1433 if (max_len < ETH_HLEN)
1434 return max_len;
1435
1436 /* initialize network frame pointer */
1437 hdr.network = data;
1438
1439 /* set first protocol and move network header forward */
1440 protocol = hdr.eth->h_proto;
1441 hdr.network += ETH_HLEN;
1442
1443 /* handle any vlan tag if present */
1444 if (protocol == __constant_htons(ETH_P_8021Q)) {
1445 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1446 return max_len;
1447
1448 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1449 hdr.network += VLAN_HLEN;
1450 }
1451
1452 /* handle L3 protocols */
1453 if (protocol == __constant_htons(ETH_P_IP)) {
1454 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1455 return max_len;
1456
1457 /* access ihl as a u8 to avoid unaligned access on ia64 */
1458 hlen = (hdr.network[0] & 0x0F) << 2;
1459
1460 /* verify hlen meets minimum size requirements */
1461 if (hlen < sizeof(struct iphdr))
1462 return hdr.network - data;
1463
1464 /* record next protocol if header is present */
1465 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
1466 nexthdr = hdr.ipv4->protocol;
1467 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1468 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1469 return max_len;
1470
1471 /* record next protocol */
1472 nexthdr = hdr.ipv6->nexthdr;
1473 hlen = sizeof(struct ipv6hdr);
1474 #ifdef IXGBE_FCOE
1475 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1476 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1477 return max_len;
1478 hlen = FCOE_HEADER_LEN;
1479 #endif
1480 } else {
1481 return hdr.network - data;
1482 }
1483
1484 /* relocate pointer to start of L4 header */
1485 hdr.network += hlen;
1486
1487 /* finally sort out TCP/UDP */
1488 if (nexthdr == IPPROTO_TCP) {
1489 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1490 return max_len;
1491
1492 /* access doff as a u8 to avoid unaligned access on ia64 */
1493 hlen = (hdr.network[12] & 0xF0) >> 2;
1494
1495 /* verify hlen meets minimum size requirements */
1496 if (hlen < sizeof(struct tcphdr))
1497 return hdr.network - data;
1498
1499 hdr.network += hlen;
1500 } else if (nexthdr == IPPROTO_UDP) {
1501 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1502 return max_len;
1503
1504 hdr.network += sizeof(struct udphdr);
1505 }
1506
1507 /*
1508 * If everything has gone correctly hdr.network should be the
1509 * data section of the packet and will be the end of the header.
1510 * If not then it probably represents the end of the last recognized
1511 * header.
1512 */
1513 if ((hdr.network - data) < max_len)
1514 return hdr.network - data;
1515 else
1516 return max_len;
1517 }
1518
1519 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1520 struct sk_buff *skb)
1521 {
1522 u16 hdr_len = skb_headlen(skb);
1523
1524 /* set gso_size to avoid messing up TCP MSS */
1525 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1526 IXGBE_CB(skb)->append_cnt);
1527 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1528 }
1529
1530 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1531 struct sk_buff *skb)
1532 {
1533 /* if append_cnt is 0 then frame is not RSC */
1534 if (!IXGBE_CB(skb)->append_cnt)
1535 return;
1536
1537 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1538 rx_ring->rx_stats.rsc_flush++;
1539
1540 ixgbe_set_rsc_gso_size(rx_ring, skb);
1541
1542 /* gso_size is computed using append_cnt so always clear it last */
1543 IXGBE_CB(skb)->append_cnt = 0;
1544 }
1545
1546 /**
1547 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1548 * @rx_ring: rx descriptor ring packet is being transacted on
1549 * @rx_desc: pointer to the EOP Rx descriptor
1550 * @skb: pointer to current skb being populated
1551 *
1552 * This function checks the ring, descriptor, and packet information in
1553 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1554 * other fields within the skb.
1555 **/
1556 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1557 union ixgbe_adv_rx_desc *rx_desc,
1558 struct sk_buff *skb)
1559 {
1560 struct net_device *dev = rx_ring->netdev;
1561
1562 ixgbe_update_rsc_stats(rx_ring, skb);
1563
1564 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1565
1566 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1567
1568 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1569
1570 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1571 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1572 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1573 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1574 }
1575
1576 skb_record_rx_queue(skb, rx_ring->queue_index);
1577
1578 skb->protocol = eth_type_trans(skb, dev);
1579 }
1580
1581 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1582 struct sk_buff *skb)
1583 {
1584 struct ixgbe_adapter *adapter = q_vector->adapter;
1585
1586 if (ixgbe_qv_busy_polling(q_vector))
1587 netif_receive_skb(skb);
1588 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1589 napi_gro_receive(&q_vector->napi, skb);
1590 else
1591 netif_rx(skb);
1592 }
1593
1594 /**
1595 * ixgbe_is_non_eop - process handling of non-EOP buffers
1596 * @rx_ring: Rx ring being processed
1597 * @rx_desc: Rx descriptor for current buffer
1598 * @skb: Current socket buffer containing buffer in progress
1599 *
1600 * This function updates next to clean. If the buffer is an EOP buffer
1601 * this function exits returning false, otherwise it will place the
1602 * sk_buff in the next buffer to be chained and return true indicating
1603 * that this is in fact a non-EOP buffer.
1604 **/
1605 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1606 union ixgbe_adv_rx_desc *rx_desc,
1607 struct sk_buff *skb)
1608 {
1609 u32 ntc = rx_ring->next_to_clean + 1;
1610
1611 /* fetch, update, and store next to clean */
1612 ntc = (ntc < rx_ring->count) ? ntc : 0;
1613 rx_ring->next_to_clean = ntc;
1614
1615 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1616
1617 /* update RSC append count if present */
1618 if (ring_is_rsc_enabled(rx_ring)) {
1619 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1620 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1621
1622 if (unlikely(rsc_enabled)) {
1623 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1624
1625 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1626 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1627
1628 /* update ntc based on RSC value */
1629 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1630 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1631 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1632 }
1633 }
1634
1635 /* if we are the last buffer then there is nothing else to do */
1636 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1637 return false;
1638
1639 /* place skb in next buffer to be received */
1640 rx_ring->rx_buffer_info[ntc].skb = skb;
1641 rx_ring->rx_stats.non_eop_descs++;
1642
1643 return true;
1644 }
1645
1646 /**
1647 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1648 * @rx_ring: rx descriptor ring packet is being transacted on
1649 * @skb: pointer to current skb being adjusted
1650 *
1651 * This function is an ixgbe specific version of __pskb_pull_tail. The
1652 * main difference between this version and the original function is that
1653 * this function can make several assumptions about the state of things
1654 * that allow for significant optimizations versus the standard function.
1655 * As a result we can do things like drop a frag and maintain an accurate
1656 * truesize for the skb.
1657 */
1658 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1659 struct sk_buff *skb)
1660 {
1661 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1662 unsigned char *va;
1663 unsigned int pull_len;
1664
1665 /*
1666 * it is valid to use page_address instead of kmap since we are
1667 * working with pages allocated out of the lomem pool per
1668 * alloc_page(GFP_ATOMIC)
1669 */
1670 va = skb_frag_address(frag);
1671
1672 /*
1673 * we need the header to contain the greater of either ETH_HLEN or
1674 * 60 bytes if the skb->len is less than 60 for skb_pad.
1675 */
1676 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
1677
1678 /* align pull length to size of long to optimize memcpy performance */
1679 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1680
1681 /* update all of the pointers */
1682 skb_frag_size_sub(frag, pull_len);
1683 frag->page_offset += pull_len;
1684 skb->data_len -= pull_len;
1685 skb->tail += pull_len;
1686 }
1687
1688 /**
1689 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1690 * @rx_ring: rx descriptor ring packet is being transacted on
1691 * @skb: pointer to current skb being updated
1692 *
1693 * This function provides a basic DMA sync up for the first fragment of an
1694 * skb. The reason for doing this is that the first fragment cannot be
1695 * unmapped until we have reached the end of packet descriptor for a buffer
1696 * chain.
1697 */
1698 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1699 struct sk_buff *skb)
1700 {
1701 /* if the page was released unmap it, else just sync our portion */
1702 if (unlikely(IXGBE_CB(skb)->page_released)) {
1703 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1704 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1705 IXGBE_CB(skb)->page_released = false;
1706 } else {
1707 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1708
1709 dma_sync_single_range_for_cpu(rx_ring->dev,
1710 IXGBE_CB(skb)->dma,
1711 frag->page_offset,
1712 ixgbe_rx_bufsz(rx_ring),
1713 DMA_FROM_DEVICE);
1714 }
1715 IXGBE_CB(skb)->dma = 0;
1716 }
1717
1718 /**
1719 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1720 * @rx_ring: rx descriptor ring packet is being transacted on
1721 * @rx_desc: pointer to the EOP Rx descriptor
1722 * @skb: pointer to current skb being fixed
1723 *
1724 * Check for corrupted packet headers caused by senders on the local L2
1725 * embedded NIC switch not setting up their Tx Descriptors right. These
1726 * should be very rare.
1727 *
1728 * Also address the case where we are pulling data in on pages only
1729 * and as such no data is present in the skb header.
1730 *
1731 * In addition if skb is not at least 60 bytes we need to pad it so that
1732 * it is large enough to qualify as a valid Ethernet frame.
1733 *
1734 * Returns true if an error was encountered and skb was freed.
1735 **/
1736 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1737 union ixgbe_adv_rx_desc *rx_desc,
1738 struct sk_buff *skb)
1739 {
1740 struct net_device *netdev = rx_ring->netdev;
1741
1742 /* verify that the packet does not have any known errors */
1743 if (unlikely(ixgbe_test_staterr(rx_desc,
1744 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1745 !(netdev->features & NETIF_F_RXALL))) {
1746 dev_kfree_skb_any(skb);
1747 return true;
1748 }
1749
1750 /* place header in linear portion of buffer */
1751 if (skb_is_nonlinear(skb))
1752 ixgbe_pull_tail(rx_ring, skb);
1753
1754 #ifdef IXGBE_FCOE
1755 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1756 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1757 return false;
1758
1759 #endif
1760 /* if skb_pad returns an error the skb was freed */
1761 if (unlikely(skb->len < 60)) {
1762 int pad_len = 60 - skb->len;
1763
1764 if (skb_pad(skb, pad_len))
1765 return true;
1766 __skb_put(skb, pad_len);
1767 }
1768
1769 return false;
1770 }
1771
1772 /**
1773 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1774 * @rx_ring: rx descriptor ring to store buffers on
1775 * @old_buff: donor buffer to have page reused
1776 *
1777 * Synchronizes page for reuse by the adapter
1778 **/
1779 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1780 struct ixgbe_rx_buffer *old_buff)
1781 {
1782 struct ixgbe_rx_buffer *new_buff;
1783 u16 nta = rx_ring->next_to_alloc;
1784
1785 new_buff = &rx_ring->rx_buffer_info[nta];
1786
1787 /* update, and store next to alloc */
1788 nta++;
1789 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1790
1791 /* transfer page from old buffer to new buffer */
1792 new_buff->page = old_buff->page;
1793 new_buff->dma = old_buff->dma;
1794 new_buff->page_offset = old_buff->page_offset;
1795
1796 /* sync the buffer for use by the device */
1797 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1798 new_buff->page_offset,
1799 ixgbe_rx_bufsz(rx_ring),
1800 DMA_FROM_DEVICE);
1801 }
1802
1803 /**
1804 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1805 * @rx_ring: rx descriptor ring to transact packets on
1806 * @rx_buffer: buffer containing page to add
1807 * @rx_desc: descriptor containing length of buffer written by hardware
1808 * @skb: sk_buff to place the data into
1809 *
1810 * This function will add the data contained in rx_buffer->page to the skb.
1811 * This is done either through a direct copy if the data in the buffer is
1812 * less than the skb header size, otherwise it will just attach the page as
1813 * a frag to the skb.
1814 *
1815 * The function will then update the page offset if necessary and return
1816 * true if the buffer can be reused by the adapter.
1817 **/
1818 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1819 struct ixgbe_rx_buffer *rx_buffer,
1820 union ixgbe_adv_rx_desc *rx_desc,
1821 struct sk_buff *skb)
1822 {
1823 struct page *page = rx_buffer->page;
1824 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1825 #if (PAGE_SIZE < 8192)
1826 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1827 #else
1828 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1829 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1830 ixgbe_rx_bufsz(rx_ring);
1831 #endif
1832
1833 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1834 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1835
1836 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1837
1838 /* we can reuse buffer as-is, just make sure it is local */
1839 if (likely(page_to_nid(page) == numa_node_id()))
1840 return true;
1841
1842 /* this page cannot be reused so discard it */
1843 put_page(page);
1844 return false;
1845 }
1846
1847 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1848 rx_buffer->page_offset, size, truesize);
1849
1850 /* avoid re-using remote pages */
1851 if (unlikely(page_to_nid(page) != numa_node_id()))
1852 return false;
1853
1854 #if (PAGE_SIZE < 8192)
1855 /* if we are only owner of page we can reuse it */
1856 if (unlikely(page_count(page) != 1))
1857 return false;
1858
1859 /* flip page offset to other buffer */
1860 rx_buffer->page_offset ^= truesize;
1861
1862 /*
1863 * since we are the only owner of the page and we need to
1864 * increment it, just set the value to 2 in order to avoid
1865 * an unecessary locked operation
1866 */
1867 atomic_set(&page->_count, 2);
1868 #else
1869 /* move offset up to the next cache line */
1870 rx_buffer->page_offset += truesize;
1871
1872 if (rx_buffer->page_offset > last_offset)
1873 return false;
1874
1875 /* bump ref count on page before it is given to the stack */
1876 get_page(page);
1877 #endif
1878
1879 return true;
1880 }
1881
1882 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1883 union ixgbe_adv_rx_desc *rx_desc)
1884 {
1885 struct ixgbe_rx_buffer *rx_buffer;
1886 struct sk_buff *skb;
1887 struct page *page;
1888
1889 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1890 page = rx_buffer->page;
1891 prefetchw(page);
1892
1893 skb = rx_buffer->skb;
1894
1895 if (likely(!skb)) {
1896 void *page_addr = page_address(page) +
1897 rx_buffer->page_offset;
1898
1899 /* prefetch first cache line of first page */
1900 prefetch(page_addr);
1901 #if L1_CACHE_BYTES < 128
1902 prefetch(page_addr + L1_CACHE_BYTES);
1903 #endif
1904
1905 /* allocate a skb to store the frags */
1906 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1907 IXGBE_RX_HDR_SIZE);
1908 if (unlikely(!skb)) {
1909 rx_ring->rx_stats.alloc_rx_buff_failed++;
1910 return NULL;
1911 }
1912
1913 /*
1914 * we will be copying header into skb->data in
1915 * pskb_may_pull so it is in our interest to prefetch
1916 * it now to avoid a possible cache miss
1917 */
1918 prefetchw(skb->data);
1919
1920 /*
1921 * Delay unmapping of the first packet. It carries the
1922 * header information, HW may still access the header
1923 * after the writeback. Only unmap it when EOP is
1924 * reached
1925 */
1926 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1927 goto dma_sync;
1928
1929 IXGBE_CB(skb)->dma = rx_buffer->dma;
1930 } else {
1931 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1932 ixgbe_dma_sync_frag(rx_ring, skb);
1933
1934 dma_sync:
1935 /* we are reusing so sync this buffer for CPU use */
1936 dma_sync_single_range_for_cpu(rx_ring->dev,
1937 rx_buffer->dma,
1938 rx_buffer->page_offset,
1939 ixgbe_rx_bufsz(rx_ring),
1940 DMA_FROM_DEVICE);
1941 }
1942
1943 /* pull page into skb */
1944 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1945 /* hand second half of page back to the ring */
1946 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1947 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1948 /* the page has been released from the ring */
1949 IXGBE_CB(skb)->page_released = true;
1950 } else {
1951 /* we are not reusing the buffer so unmap it */
1952 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1953 ixgbe_rx_pg_size(rx_ring),
1954 DMA_FROM_DEVICE);
1955 }
1956
1957 /* clear contents of buffer_info */
1958 rx_buffer->skb = NULL;
1959 rx_buffer->dma = 0;
1960 rx_buffer->page = NULL;
1961
1962 return skb;
1963 }
1964
1965 /**
1966 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1967 * @q_vector: structure containing interrupt and ring information
1968 * @rx_ring: rx descriptor ring to transact packets on
1969 * @budget: Total limit on number of packets to process
1970 *
1971 * This function provides a "bounce buffer" approach to Rx interrupt
1972 * processing. The advantage to this is that on systems that have
1973 * expensive overhead for IOMMU access this provides a means of avoiding
1974 * it by maintaining the mapping of the page to the syste.
1975 *
1976 * Returns amount of work completed
1977 **/
1978 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1979 struct ixgbe_ring *rx_ring,
1980 const int budget)
1981 {
1982 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1983 #ifdef IXGBE_FCOE
1984 struct ixgbe_adapter *adapter = q_vector->adapter;
1985 int ddp_bytes;
1986 unsigned int mss = 0;
1987 #endif /* IXGBE_FCOE */
1988 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1989
1990 do {
1991 union ixgbe_adv_rx_desc *rx_desc;
1992 struct sk_buff *skb;
1993
1994 /* return some buffers to hardware, one at a time is too slow */
1995 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1996 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1997 cleaned_count = 0;
1998 }
1999
2000 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2001
2002 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2003 break;
2004
2005 /*
2006 * This memory barrier is needed to keep us from reading
2007 * any other fields out of the rx_desc until we know the
2008 * RXD_STAT_DD bit is set
2009 */
2010 rmb();
2011
2012 /* retrieve a buffer from the ring */
2013 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
2014
2015 /* exit if we failed to retrieve a buffer */
2016 if (!skb)
2017 break;
2018
2019 cleaned_count++;
2020
2021 /* place incomplete frames back on ring for completion */
2022 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2023 continue;
2024
2025 /* verify the packet layout is correct */
2026 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2027 continue;
2028
2029 /* probably a little skewed due to removing CRC */
2030 total_rx_bytes += skb->len;
2031
2032 /* populate checksum, timestamp, VLAN, and protocol */
2033 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2034
2035 #ifdef IXGBE_FCOE
2036 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2037 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2038 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2039 /* include DDPed FCoE data */
2040 if (ddp_bytes > 0) {
2041 if (!mss) {
2042 mss = rx_ring->netdev->mtu -
2043 sizeof(struct fcoe_hdr) -
2044 sizeof(struct fc_frame_header) -
2045 sizeof(struct fcoe_crc_eof);
2046 if (mss > 512)
2047 mss &= ~511;
2048 }
2049 total_rx_bytes += ddp_bytes;
2050 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2051 mss);
2052 }
2053 if (!ddp_bytes) {
2054 dev_kfree_skb_any(skb);
2055 continue;
2056 }
2057 }
2058
2059 #endif /* IXGBE_FCOE */
2060 skb_mark_napi_id(skb, &q_vector->napi);
2061 ixgbe_rx_skb(q_vector, skb);
2062
2063 /* update budget accounting */
2064 total_rx_packets++;
2065 } while (likely(total_rx_packets < budget));
2066
2067 u64_stats_update_begin(&rx_ring->syncp);
2068 rx_ring->stats.packets += total_rx_packets;
2069 rx_ring->stats.bytes += total_rx_bytes;
2070 u64_stats_update_end(&rx_ring->syncp);
2071 q_vector->rx.total_packets += total_rx_packets;
2072 q_vector->rx.total_bytes += total_rx_bytes;
2073
2074 if (cleaned_count)
2075 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2076
2077 return total_rx_packets;
2078 }
2079
2080 #ifdef CONFIG_NET_RX_BUSY_POLL
2081 /* must be called with local_bh_disable()d */
2082 static int ixgbe_low_latency_recv(struct napi_struct *napi)
2083 {
2084 struct ixgbe_q_vector *q_vector =
2085 container_of(napi, struct ixgbe_q_vector, napi);
2086 struct ixgbe_adapter *adapter = q_vector->adapter;
2087 struct ixgbe_ring *ring;
2088 int found = 0;
2089
2090 if (test_bit(__IXGBE_DOWN, &adapter->state))
2091 return LL_FLUSH_FAILED;
2092
2093 if (!ixgbe_qv_lock_poll(q_vector))
2094 return LL_FLUSH_BUSY;
2095
2096 ixgbe_for_each_ring(ring, q_vector->rx) {
2097 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
2098 #ifdef BP_EXTENDED_STATS
2099 if (found)
2100 ring->stats.cleaned += found;
2101 else
2102 ring->stats.misses++;
2103 #endif
2104 if (found)
2105 break;
2106 }
2107
2108 ixgbe_qv_unlock_poll(q_vector);
2109
2110 return found;
2111 }
2112 #endif /* CONFIG_NET_RX_BUSY_POLL */
2113
2114 /**
2115 * ixgbe_configure_msix - Configure MSI-X hardware
2116 * @adapter: board private structure
2117 *
2118 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2119 * interrupts.
2120 **/
2121 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2122 {
2123 struct ixgbe_q_vector *q_vector;
2124 int v_idx;
2125 u32 mask;
2126
2127 /* Populate MSIX to EITR Select */
2128 if (adapter->num_vfs > 32) {
2129 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2130 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2131 }
2132
2133 /*
2134 * Populate the IVAR table and set the ITR values to the
2135 * corresponding register.
2136 */
2137 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2138 struct ixgbe_ring *ring;
2139 q_vector = adapter->q_vector[v_idx];
2140
2141 ixgbe_for_each_ring(ring, q_vector->rx)
2142 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2143
2144 ixgbe_for_each_ring(ring, q_vector->tx)
2145 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2146
2147 ixgbe_write_eitr(q_vector);
2148 }
2149
2150 switch (adapter->hw.mac.type) {
2151 case ixgbe_mac_82598EB:
2152 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2153 v_idx);
2154 break;
2155 case ixgbe_mac_82599EB:
2156 case ixgbe_mac_X540:
2157 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2158 break;
2159 default:
2160 break;
2161 }
2162 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2163
2164 /* set up to autoclear timer, and the vectors */
2165 mask = IXGBE_EIMS_ENABLE_MASK;
2166 mask &= ~(IXGBE_EIMS_OTHER |
2167 IXGBE_EIMS_MAILBOX |
2168 IXGBE_EIMS_LSC);
2169
2170 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2171 }
2172
2173 enum latency_range {
2174 lowest_latency = 0,
2175 low_latency = 1,
2176 bulk_latency = 2,
2177 latency_invalid = 255
2178 };
2179
2180 /**
2181 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2182 * @q_vector: structure containing interrupt and ring information
2183 * @ring_container: structure containing ring performance data
2184 *
2185 * Stores a new ITR value based on packets and byte
2186 * counts during the last interrupt. The advantage of per interrupt
2187 * computation is faster updates and more accurate ITR for the current
2188 * traffic pattern. Constants in this function were computed
2189 * based on theoretical maximum wire speed and thresholds were set based
2190 * on testing data as well as attempting to minimize response time
2191 * while increasing bulk throughput.
2192 * this functionality is controlled by the InterruptThrottleRate module
2193 * parameter (see ixgbe_param.c)
2194 **/
2195 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2196 struct ixgbe_ring_container *ring_container)
2197 {
2198 int bytes = ring_container->total_bytes;
2199 int packets = ring_container->total_packets;
2200 u32 timepassed_us;
2201 u64 bytes_perint;
2202 u8 itr_setting = ring_container->itr;
2203
2204 if (packets == 0)
2205 return;
2206
2207 /* simple throttlerate management
2208 * 0-10MB/s lowest (100000 ints/s)
2209 * 10-20MB/s low (20000 ints/s)
2210 * 20-1249MB/s bulk (8000 ints/s)
2211 */
2212 /* what was last interrupt timeslice? */
2213 timepassed_us = q_vector->itr >> 2;
2214 if (timepassed_us == 0)
2215 return;
2216
2217 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2218
2219 switch (itr_setting) {
2220 case lowest_latency:
2221 if (bytes_perint > 10)
2222 itr_setting = low_latency;
2223 break;
2224 case low_latency:
2225 if (bytes_perint > 20)
2226 itr_setting = bulk_latency;
2227 else if (bytes_perint <= 10)
2228 itr_setting = lowest_latency;
2229 break;
2230 case bulk_latency:
2231 if (bytes_perint <= 20)
2232 itr_setting = low_latency;
2233 break;
2234 }
2235
2236 /* clear work counters since we have the values we need */
2237 ring_container->total_bytes = 0;
2238 ring_container->total_packets = 0;
2239
2240 /* write updated itr to ring container */
2241 ring_container->itr = itr_setting;
2242 }
2243
2244 /**
2245 * ixgbe_write_eitr - write EITR register in hardware specific way
2246 * @q_vector: structure containing interrupt and ring information
2247 *
2248 * This function is made to be called by ethtool and by the driver
2249 * when it needs to update EITR registers at runtime. Hardware
2250 * specific quirks/differences are taken care of here.
2251 */
2252 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2253 {
2254 struct ixgbe_adapter *adapter = q_vector->adapter;
2255 struct ixgbe_hw *hw = &adapter->hw;
2256 int v_idx = q_vector->v_idx;
2257 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2258
2259 switch (adapter->hw.mac.type) {
2260 case ixgbe_mac_82598EB:
2261 /* must write high and low 16 bits to reset counter */
2262 itr_reg |= (itr_reg << 16);
2263 break;
2264 case ixgbe_mac_82599EB:
2265 case ixgbe_mac_X540:
2266 /*
2267 * set the WDIS bit to not clear the timer bits and cause an
2268 * immediate assertion of the interrupt
2269 */
2270 itr_reg |= IXGBE_EITR_CNT_WDIS;
2271 break;
2272 default:
2273 break;
2274 }
2275 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2276 }
2277
2278 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2279 {
2280 u32 new_itr = q_vector->itr;
2281 u8 current_itr;
2282
2283 ixgbe_update_itr(q_vector, &q_vector->tx);
2284 ixgbe_update_itr(q_vector, &q_vector->rx);
2285
2286 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2287
2288 switch (current_itr) {
2289 /* counts and packets in update_itr are dependent on these numbers */
2290 case lowest_latency:
2291 new_itr = IXGBE_100K_ITR;
2292 break;
2293 case low_latency:
2294 new_itr = IXGBE_20K_ITR;
2295 break;
2296 case bulk_latency:
2297 new_itr = IXGBE_8K_ITR;
2298 break;
2299 default:
2300 break;
2301 }
2302
2303 if (new_itr != q_vector->itr) {
2304 /* do an exponential smoothing */
2305 new_itr = (10 * new_itr * q_vector->itr) /
2306 ((9 * new_itr) + q_vector->itr);
2307
2308 /* save the algorithm value here */
2309 q_vector->itr = new_itr;
2310
2311 ixgbe_write_eitr(q_vector);
2312 }
2313 }
2314
2315 /**
2316 * ixgbe_check_overtemp_subtask - check for over temperature
2317 * @adapter: pointer to adapter
2318 **/
2319 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2320 {
2321 struct ixgbe_hw *hw = &adapter->hw;
2322 u32 eicr = adapter->interrupt_event;
2323
2324 if (test_bit(__IXGBE_DOWN, &adapter->state))
2325 return;
2326
2327 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2328 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2329 return;
2330
2331 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2332
2333 switch (hw->device_id) {
2334 case IXGBE_DEV_ID_82599_T3_LOM:
2335 /*
2336 * Since the warning interrupt is for both ports
2337 * we don't have to check if:
2338 * - This interrupt wasn't for our port.
2339 * - We may have missed the interrupt so always have to
2340 * check if we got a LSC
2341 */
2342 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2343 !(eicr & IXGBE_EICR_LSC))
2344 return;
2345
2346 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2347 u32 speed;
2348 bool link_up = false;
2349
2350 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2351
2352 if (link_up)
2353 return;
2354 }
2355
2356 /* Check if this is not due to overtemp */
2357 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2358 return;
2359
2360 break;
2361 default:
2362 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2363 return;
2364 break;
2365 }
2366 e_crit(drv,
2367 "Network adapter has been stopped because it has over heated. "
2368 "Restart the computer. If the problem persists, "
2369 "power off the system and replace the adapter\n");
2370
2371 adapter->interrupt_event = 0;
2372 }
2373
2374 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2375 {
2376 struct ixgbe_hw *hw = &adapter->hw;
2377
2378 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2379 (eicr & IXGBE_EICR_GPI_SDP1)) {
2380 e_crit(probe, "Fan has stopped, replace the adapter\n");
2381 /* write to clear the interrupt */
2382 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2383 }
2384 }
2385
2386 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2387 {
2388 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2389 return;
2390
2391 switch (adapter->hw.mac.type) {
2392 case ixgbe_mac_82599EB:
2393 /*
2394 * Need to check link state so complete overtemp check
2395 * on service task
2396 */
2397 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2398 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2399 adapter->interrupt_event = eicr;
2400 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2401 ixgbe_service_event_schedule(adapter);
2402 return;
2403 }
2404 return;
2405 case ixgbe_mac_X540:
2406 if (!(eicr & IXGBE_EICR_TS))
2407 return;
2408 break;
2409 default:
2410 return;
2411 }
2412
2413 e_crit(drv,
2414 "Network adapter has been stopped because it has over heated. "
2415 "Restart the computer. If the problem persists, "
2416 "power off the system and replace the adapter\n");
2417 }
2418
2419 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2420 {
2421 struct ixgbe_hw *hw = &adapter->hw;
2422
2423 if (eicr & IXGBE_EICR_GPI_SDP2) {
2424 /* Clear the interrupt */
2425 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2426 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2427 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2428 ixgbe_service_event_schedule(adapter);
2429 }
2430 }
2431
2432 if (eicr & IXGBE_EICR_GPI_SDP1) {
2433 /* Clear the interrupt */
2434 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2435 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2436 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2437 ixgbe_service_event_schedule(adapter);
2438 }
2439 }
2440 }
2441
2442 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2443 {
2444 struct ixgbe_hw *hw = &adapter->hw;
2445
2446 adapter->lsc_int++;
2447 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2448 adapter->link_check_timeout = jiffies;
2449 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2450 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2451 IXGBE_WRITE_FLUSH(hw);
2452 ixgbe_service_event_schedule(adapter);
2453 }
2454 }
2455
2456 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2457 u64 qmask)
2458 {
2459 u32 mask;
2460 struct ixgbe_hw *hw = &adapter->hw;
2461
2462 switch (hw->mac.type) {
2463 case ixgbe_mac_82598EB:
2464 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2465 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2466 break;
2467 case ixgbe_mac_82599EB:
2468 case ixgbe_mac_X540:
2469 mask = (qmask & 0xFFFFFFFF);
2470 if (mask)
2471 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2472 mask = (qmask >> 32);
2473 if (mask)
2474 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2475 break;
2476 default:
2477 break;
2478 }
2479 /* skip the flush */
2480 }
2481
2482 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2483 u64 qmask)
2484 {
2485 u32 mask;
2486 struct ixgbe_hw *hw = &adapter->hw;
2487
2488 switch (hw->mac.type) {
2489 case ixgbe_mac_82598EB:
2490 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2491 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2492 break;
2493 case ixgbe_mac_82599EB:
2494 case ixgbe_mac_X540:
2495 mask = (qmask & 0xFFFFFFFF);
2496 if (mask)
2497 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2498 mask = (qmask >> 32);
2499 if (mask)
2500 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2501 break;
2502 default:
2503 break;
2504 }
2505 /* skip the flush */
2506 }
2507
2508 /**
2509 * ixgbe_irq_enable - Enable default interrupt generation settings
2510 * @adapter: board private structure
2511 **/
2512 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2513 bool flush)
2514 {
2515 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2516
2517 /* don't reenable LSC while waiting for link */
2518 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2519 mask &= ~IXGBE_EIMS_LSC;
2520
2521 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2522 switch (adapter->hw.mac.type) {
2523 case ixgbe_mac_82599EB:
2524 mask |= IXGBE_EIMS_GPI_SDP0;
2525 break;
2526 case ixgbe_mac_X540:
2527 mask |= IXGBE_EIMS_TS;
2528 break;
2529 default:
2530 break;
2531 }
2532 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2533 mask |= IXGBE_EIMS_GPI_SDP1;
2534 switch (adapter->hw.mac.type) {
2535 case ixgbe_mac_82599EB:
2536 mask |= IXGBE_EIMS_GPI_SDP1;
2537 mask |= IXGBE_EIMS_GPI_SDP2;
2538 case ixgbe_mac_X540:
2539 mask |= IXGBE_EIMS_ECC;
2540 mask |= IXGBE_EIMS_MAILBOX;
2541 break;
2542 default:
2543 break;
2544 }
2545
2546 if (adapter->hw.mac.type == ixgbe_mac_X540)
2547 mask |= IXGBE_EIMS_TIMESYNC;
2548
2549 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2550 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2551 mask |= IXGBE_EIMS_FLOW_DIR;
2552
2553 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2554 if (queues)
2555 ixgbe_irq_enable_queues(adapter, ~0);
2556 if (flush)
2557 IXGBE_WRITE_FLUSH(&adapter->hw);
2558 }
2559
2560 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2561 {
2562 struct ixgbe_adapter *adapter = data;
2563 struct ixgbe_hw *hw = &adapter->hw;
2564 u32 eicr;
2565
2566 /*
2567 * Workaround for Silicon errata. Use clear-by-write instead
2568 * of clear-by-read. Reading with EICS will return the
2569 * interrupt causes without clearing, which later be done
2570 * with the write to EICR.
2571 */
2572 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2573
2574 /* The lower 16bits of the EICR register are for the queue interrupts
2575 * which should be masked here in order to not accidently clear them if
2576 * the bits are high when ixgbe_msix_other is called. There is a race
2577 * condition otherwise which results in possible performance loss
2578 * especially if the ixgbe_msix_other interrupt is triggering
2579 * consistently (as it would when PPS is turned on for the X540 device)
2580 */
2581 eicr &= 0xFFFF0000;
2582
2583 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2584
2585 if (eicr & IXGBE_EICR_LSC)
2586 ixgbe_check_lsc(adapter);
2587
2588 if (eicr & IXGBE_EICR_MAILBOX)
2589 ixgbe_msg_task(adapter);
2590
2591 switch (hw->mac.type) {
2592 case ixgbe_mac_82599EB:
2593 case ixgbe_mac_X540:
2594 if (eicr & IXGBE_EICR_ECC)
2595 e_info(link, "Received unrecoverable ECC Err, please "
2596 "reboot\n");
2597 /* Handle Flow Director Full threshold interrupt */
2598 if (eicr & IXGBE_EICR_FLOW_DIR) {
2599 int reinit_count = 0;
2600 int i;
2601 for (i = 0; i < adapter->num_tx_queues; i++) {
2602 struct ixgbe_ring *ring = adapter->tx_ring[i];
2603 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2604 &ring->state))
2605 reinit_count++;
2606 }
2607 if (reinit_count) {
2608 /* no more flow director interrupts until after init */
2609 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2610 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2611 ixgbe_service_event_schedule(adapter);
2612 }
2613 }
2614 ixgbe_check_sfp_event(adapter, eicr);
2615 ixgbe_check_overtemp_event(adapter, eicr);
2616 break;
2617 default:
2618 break;
2619 }
2620
2621 ixgbe_check_fan_failure(adapter, eicr);
2622
2623 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2624 ixgbe_ptp_check_pps_event(adapter, eicr);
2625
2626 /* re-enable the original interrupt state, no lsc, no queues */
2627 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2628 ixgbe_irq_enable(adapter, false, false);
2629
2630 return IRQ_HANDLED;
2631 }
2632
2633 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2634 {
2635 struct ixgbe_q_vector *q_vector = data;
2636
2637 /* EIAM disabled interrupts (on this vector) for us */
2638
2639 if (q_vector->rx.ring || q_vector->tx.ring)
2640 napi_schedule(&q_vector->napi);
2641
2642 return IRQ_HANDLED;
2643 }
2644
2645 /**
2646 * ixgbe_poll - NAPI Rx polling callback
2647 * @napi: structure for representing this polling device
2648 * @budget: how many packets driver is allowed to clean
2649 *
2650 * This function is used for legacy and MSI, NAPI mode
2651 **/
2652 int ixgbe_poll(struct napi_struct *napi, int budget)
2653 {
2654 struct ixgbe_q_vector *q_vector =
2655 container_of(napi, struct ixgbe_q_vector, napi);
2656 struct ixgbe_adapter *adapter = q_vector->adapter;
2657 struct ixgbe_ring *ring;
2658 int per_ring_budget;
2659 bool clean_complete = true;
2660
2661 #ifdef CONFIG_IXGBE_DCA
2662 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2663 ixgbe_update_dca(q_vector);
2664 #endif
2665
2666 ixgbe_for_each_ring(ring, q_vector->tx)
2667 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2668
2669 if (!ixgbe_qv_lock_napi(q_vector))
2670 return budget;
2671
2672 /* attempt to distribute budget to each queue fairly, but don't allow
2673 * the budget to go below 1 because we'll exit polling */
2674 if (q_vector->rx.count > 1)
2675 per_ring_budget = max(budget/q_vector->rx.count, 1);
2676 else
2677 per_ring_budget = budget;
2678
2679 ixgbe_for_each_ring(ring, q_vector->rx)
2680 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2681 per_ring_budget) < per_ring_budget);
2682
2683 ixgbe_qv_unlock_napi(q_vector);
2684 /* If all work not completed, return budget and keep polling */
2685 if (!clean_complete)
2686 return budget;
2687
2688 /* all work done, exit the polling mode */
2689 napi_complete(napi);
2690 if (adapter->rx_itr_setting & 1)
2691 ixgbe_set_itr(q_vector);
2692 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2693 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2694
2695 return 0;
2696 }
2697
2698 /**
2699 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2700 * @adapter: board private structure
2701 *
2702 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2703 * interrupts from the kernel.
2704 **/
2705 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2706 {
2707 struct net_device *netdev = adapter->netdev;
2708 int vector, err;
2709 int ri = 0, ti = 0;
2710
2711 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2712 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2713 struct msix_entry *entry = &adapter->msix_entries[vector];
2714
2715 if (q_vector->tx.ring && q_vector->rx.ring) {
2716 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2717 "%s-%s-%d", netdev->name, "TxRx", ri++);
2718 ti++;
2719 } else if (q_vector->rx.ring) {
2720 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2721 "%s-%s-%d", netdev->name, "rx", ri++);
2722 } else if (q_vector->tx.ring) {
2723 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2724 "%s-%s-%d", netdev->name, "tx", ti++);
2725 } else {
2726 /* skip this unused q_vector */
2727 continue;
2728 }
2729 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2730 q_vector->name, q_vector);
2731 if (err) {
2732 e_err(probe, "request_irq failed for MSIX interrupt "
2733 "Error: %d\n", err);
2734 goto free_queue_irqs;
2735 }
2736 /* If Flow Director is enabled, set interrupt affinity */
2737 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2738 /* assign the mask for this irq */
2739 irq_set_affinity_hint(entry->vector,
2740 &q_vector->affinity_mask);
2741 }
2742 }
2743
2744 err = request_irq(adapter->msix_entries[vector].vector,
2745 ixgbe_msix_other, 0, netdev->name, adapter);
2746 if (err) {
2747 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2748 goto free_queue_irqs;
2749 }
2750
2751 return 0;
2752
2753 free_queue_irqs:
2754 while (vector) {
2755 vector--;
2756 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2757 NULL);
2758 free_irq(adapter->msix_entries[vector].vector,
2759 adapter->q_vector[vector]);
2760 }
2761 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2762 pci_disable_msix(adapter->pdev);
2763 kfree(adapter->msix_entries);
2764 adapter->msix_entries = NULL;
2765 return err;
2766 }
2767
2768 /**
2769 * ixgbe_intr - legacy mode Interrupt Handler
2770 * @irq: interrupt number
2771 * @data: pointer to a network interface device structure
2772 **/
2773 static irqreturn_t ixgbe_intr(int irq, void *data)
2774 {
2775 struct ixgbe_adapter *adapter = data;
2776 struct ixgbe_hw *hw = &adapter->hw;
2777 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2778 u32 eicr;
2779
2780 /*
2781 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2782 * before the read of EICR.
2783 */
2784 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2785
2786 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2787 * therefore no explicit interrupt disable is necessary */
2788 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2789 if (!eicr) {
2790 /*
2791 * shared interrupt alert!
2792 * make sure interrupts are enabled because the read will
2793 * have disabled interrupts due to EIAM
2794 * finish the workaround of silicon errata on 82598. Unmask
2795 * the interrupt that we masked before the EICR read.
2796 */
2797 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2798 ixgbe_irq_enable(adapter, true, true);
2799 return IRQ_NONE; /* Not our interrupt */
2800 }
2801
2802 if (eicr & IXGBE_EICR_LSC)
2803 ixgbe_check_lsc(adapter);
2804
2805 switch (hw->mac.type) {
2806 case ixgbe_mac_82599EB:
2807 ixgbe_check_sfp_event(adapter, eicr);
2808 /* Fall through */
2809 case ixgbe_mac_X540:
2810 if (eicr & IXGBE_EICR_ECC)
2811 e_info(link, "Received unrecoverable ECC err, please "
2812 "reboot\n");
2813 ixgbe_check_overtemp_event(adapter, eicr);
2814 break;
2815 default:
2816 break;
2817 }
2818
2819 ixgbe_check_fan_failure(adapter, eicr);
2820 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2821 ixgbe_ptp_check_pps_event(adapter, eicr);
2822
2823 /* would disable interrupts here but EIAM disabled it */
2824 napi_schedule(&q_vector->napi);
2825
2826 /*
2827 * re-enable link(maybe) and non-queue interrupts, no flush.
2828 * ixgbe_poll will re-enable the queue interrupts
2829 */
2830 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2831 ixgbe_irq_enable(adapter, false, false);
2832
2833 return IRQ_HANDLED;
2834 }
2835
2836 /**
2837 * ixgbe_request_irq - initialize interrupts
2838 * @adapter: board private structure
2839 *
2840 * Attempts to configure interrupts using the best available
2841 * capabilities of the hardware and kernel.
2842 **/
2843 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2844 {
2845 struct net_device *netdev = adapter->netdev;
2846 int err;
2847
2848 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2849 err = ixgbe_request_msix_irqs(adapter);
2850 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2851 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2852 netdev->name, adapter);
2853 else
2854 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2855 netdev->name, adapter);
2856
2857 if (err)
2858 e_err(probe, "request_irq failed, Error %d\n", err);
2859
2860 return err;
2861 }
2862
2863 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2864 {
2865 int vector;
2866
2867 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2868 free_irq(adapter->pdev->irq, adapter);
2869 return;
2870 }
2871
2872 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2873 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2874 struct msix_entry *entry = &adapter->msix_entries[vector];
2875
2876 /* free only the irqs that were actually requested */
2877 if (!q_vector->rx.ring && !q_vector->tx.ring)
2878 continue;
2879
2880 /* clear the affinity_mask in the IRQ descriptor */
2881 irq_set_affinity_hint(entry->vector, NULL);
2882
2883 free_irq(entry->vector, q_vector);
2884 }
2885
2886 free_irq(adapter->msix_entries[vector++].vector, adapter);
2887 }
2888
2889 /**
2890 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2891 * @adapter: board private structure
2892 **/
2893 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2894 {
2895 switch (adapter->hw.mac.type) {
2896 case ixgbe_mac_82598EB:
2897 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2898 break;
2899 case ixgbe_mac_82599EB:
2900 case ixgbe_mac_X540:
2901 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2902 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2903 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2904 break;
2905 default:
2906 break;
2907 }
2908 IXGBE_WRITE_FLUSH(&adapter->hw);
2909 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2910 int vector;
2911
2912 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2913 synchronize_irq(adapter->msix_entries[vector].vector);
2914
2915 synchronize_irq(adapter->msix_entries[vector++].vector);
2916 } else {
2917 synchronize_irq(adapter->pdev->irq);
2918 }
2919 }
2920
2921 /**
2922 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2923 *
2924 **/
2925 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2926 {
2927 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2928
2929 ixgbe_write_eitr(q_vector);
2930
2931 ixgbe_set_ivar(adapter, 0, 0, 0);
2932 ixgbe_set_ivar(adapter, 1, 0, 0);
2933
2934 e_info(hw, "Legacy interrupt IVAR setup done\n");
2935 }
2936
2937 /**
2938 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2939 * @adapter: board private structure
2940 * @ring: structure containing ring specific data
2941 *
2942 * Configure the Tx descriptor ring after a reset.
2943 **/
2944 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2945 struct ixgbe_ring *ring)
2946 {
2947 struct ixgbe_hw *hw = &adapter->hw;
2948 u64 tdba = ring->dma;
2949 int wait_loop = 10;
2950 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2951 u8 reg_idx = ring->reg_idx;
2952
2953 /* disable queue to avoid issues while updating state */
2954 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2955 IXGBE_WRITE_FLUSH(hw);
2956
2957 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2958 (tdba & DMA_BIT_MASK(32)));
2959 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2960 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2961 ring->count * sizeof(union ixgbe_adv_tx_desc));
2962 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2963 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2964 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2965
2966 /*
2967 * set WTHRESH to encourage burst writeback, it should not be set
2968 * higher than 1 when:
2969 * - ITR is 0 as it could cause false TX hangs
2970 * - ITR is set to > 100k int/sec and BQL is enabled
2971 *
2972 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2973 * to or less than the number of on chip descriptors, which is
2974 * currently 40.
2975 */
2976 #if IS_ENABLED(CONFIG_BQL)
2977 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
2978 #else
2979 if (!ring->q_vector || (ring->q_vector->itr < 8))
2980 #endif
2981 txdctl |= (1 << 16); /* WTHRESH = 1 */
2982 else
2983 txdctl |= (8 << 16); /* WTHRESH = 8 */
2984
2985 /*
2986 * Setting PTHRESH to 32 both improves performance
2987 * and avoids a TX hang with DFP enabled
2988 */
2989 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2990 32; /* PTHRESH = 32 */
2991
2992 /* reinitialize flowdirector state */
2993 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2994 ring->atr_sample_rate = adapter->atr_sample_rate;
2995 ring->atr_count = 0;
2996 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2997 } else {
2998 ring->atr_sample_rate = 0;
2999 }
3000
3001 /* initialize XPS */
3002 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3003 struct ixgbe_q_vector *q_vector = ring->q_vector;
3004
3005 if (q_vector)
3006 netif_set_xps_queue(adapter->netdev,
3007 &q_vector->affinity_mask,
3008 ring->queue_index);
3009 }
3010
3011 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3012
3013 /* enable queue */
3014 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3015
3016 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3017 if (hw->mac.type == ixgbe_mac_82598EB &&
3018 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3019 return;
3020
3021 /* poll to verify queue is enabled */
3022 do {
3023 usleep_range(1000, 2000);
3024 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3025 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3026 if (!wait_loop)
3027 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
3028 }
3029
3030 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3031 {
3032 struct ixgbe_hw *hw = &adapter->hw;
3033 u32 rttdcs, mtqc;
3034 u8 tcs = netdev_get_num_tc(adapter->netdev);
3035
3036 if (hw->mac.type == ixgbe_mac_82598EB)
3037 return;
3038
3039 /* disable the arbiter while setting MTQC */
3040 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3041 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3042 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3043
3044 /* set transmit pool layout */
3045 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3046 mtqc = IXGBE_MTQC_VT_ENA;
3047 if (tcs > 4)
3048 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3049 else if (tcs > 1)
3050 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3051 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3052 mtqc |= IXGBE_MTQC_32VF;
3053 else
3054 mtqc |= IXGBE_MTQC_64VF;
3055 } else {
3056 if (tcs > 4)
3057 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3058 else if (tcs > 1)
3059 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3060 else
3061 mtqc = IXGBE_MTQC_64Q_1PB;
3062 }
3063
3064 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3065
3066 /* Enable Security TX Buffer IFG for multiple pb */
3067 if (tcs) {
3068 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3069 sectx |= IXGBE_SECTX_DCB;
3070 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3071 }
3072
3073 /* re-enable the arbiter */
3074 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3075 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3076 }
3077
3078 /**
3079 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3080 * @adapter: board private structure
3081 *
3082 * Configure the Tx unit of the MAC after a reset.
3083 **/
3084 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3085 {
3086 struct ixgbe_hw *hw = &adapter->hw;
3087 u32 dmatxctl;
3088 u32 i;
3089
3090 ixgbe_setup_mtqc(adapter);
3091
3092 if (hw->mac.type != ixgbe_mac_82598EB) {
3093 /* DMATXCTL.EN must be before Tx queues are enabled */
3094 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3095 dmatxctl |= IXGBE_DMATXCTL_TE;
3096 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3097 }
3098
3099 /* Setup the HW Tx Head and Tail descriptor pointers */
3100 for (i = 0; i < adapter->num_tx_queues; i++)
3101 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3102 }
3103
3104 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3105 struct ixgbe_ring *ring)
3106 {
3107 struct ixgbe_hw *hw = &adapter->hw;
3108 u8 reg_idx = ring->reg_idx;
3109 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3110
3111 srrctl |= IXGBE_SRRCTL_DROP_EN;
3112
3113 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3114 }
3115
3116 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3117 struct ixgbe_ring *ring)
3118 {
3119 struct ixgbe_hw *hw = &adapter->hw;
3120 u8 reg_idx = ring->reg_idx;
3121 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3122
3123 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3124
3125 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3126 }
3127
3128 #ifdef CONFIG_IXGBE_DCB
3129 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3130 #else
3131 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3132 #endif
3133 {
3134 int i;
3135 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3136
3137 if (adapter->ixgbe_ieee_pfc)
3138 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3139
3140 /*
3141 * We should set the drop enable bit if:
3142 * SR-IOV is enabled
3143 * or
3144 * Number of Rx queues > 1 and flow control is disabled
3145 *
3146 * This allows us to avoid head of line blocking for security
3147 * and performance reasons.
3148 */
3149 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3150 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3151 for (i = 0; i < adapter->num_rx_queues; i++)
3152 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3153 } else {
3154 for (i = 0; i < adapter->num_rx_queues; i++)
3155 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3156 }
3157 }
3158
3159 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3160
3161 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3162 struct ixgbe_ring *rx_ring)
3163 {
3164 struct ixgbe_hw *hw = &adapter->hw;
3165 u32 srrctl;
3166 u8 reg_idx = rx_ring->reg_idx;
3167
3168 if (hw->mac.type == ixgbe_mac_82598EB) {
3169 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3170
3171 /*
3172 * if VMDq is not active we must program one srrctl register
3173 * per RSS queue since we have enabled RDRXCTL.MVMEN
3174 */
3175 reg_idx &= mask;
3176 }
3177
3178 /* configure header buffer length, needed for RSC */
3179 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3180
3181 /* configure the packet buffer length */
3182 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3183
3184 /* configure descriptor type */
3185 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3186
3187 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3188 }
3189
3190 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3191 {
3192 struct ixgbe_hw *hw = &adapter->hw;
3193 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
3194 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3195 0x6A3E67EA, 0x14364D17, 0x3BED200D};
3196 u32 mrqc = 0, reta = 0;
3197 u32 rxcsum;
3198 int i, j;
3199 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3200
3201 /*
3202 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3203 * make full use of any rings they may have. We will use the
3204 * PSRTYPE register to control how many rings we use within the PF.
3205 */
3206 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3207 rss_i = 2;
3208
3209 /* Fill out hash function seeds */
3210 for (i = 0; i < 10; i++)
3211 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3212
3213 /* Fill out redirection table */
3214 for (i = 0, j = 0; i < 128; i++, j++) {
3215 if (j == rss_i)
3216 j = 0;
3217 /* reta = 4-byte sliding window of
3218 * 0x00..(indices-1)(indices-1)00..etc. */
3219 reta = (reta << 8) | (j * 0x11);
3220 if ((i & 3) == 3)
3221 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3222 }
3223
3224 /* Disable indicating checksum in descriptor, enables RSS hash */
3225 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3226 rxcsum |= IXGBE_RXCSUM_PCSD;
3227 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3228
3229 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3230 if (adapter->ring_feature[RING_F_RSS].mask)
3231 mrqc = IXGBE_MRQC_RSSEN;
3232 } else {
3233 u8 tcs = netdev_get_num_tc(adapter->netdev);
3234
3235 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3236 if (tcs > 4)
3237 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3238 else if (tcs > 1)
3239 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3240 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3241 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3242 else
3243 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3244 } else {
3245 if (tcs > 4)
3246 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3247 else if (tcs > 1)
3248 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3249 else
3250 mrqc = IXGBE_MRQC_RSSEN;
3251 }
3252 }
3253
3254 /* Perform hash on these packet types */
3255 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3256 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3257 IXGBE_MRQC_RSS_FIELD_IPV6 |
3258 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3259
3260 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3261 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3262 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3263 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3264
3265 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3266 }
3267
3268 /**
3269 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3270 * @adapter: address of board private structure
3271 * @index: index of ring to set
3272 **/
3273 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3274 struct ixgbe_ring *ring)
3275 {
3276 struct ixgbe_hw *hw = &adapter->hw;
3277 u32 rscctrl;
3278 u8 reg_idx = ring->reg_idx;
3279
3280 if (!ring_is_rsc_enabled(ring))
3281 return;
3282
3283 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3284 rscctrl |= IXGBE_RSCCTL_RSCEN;
3285 /*
3286 * we must limit the number of descriptors so that the
3287 * total size of max desc * buf_len is not greater
3288 * than 65536
3289 */
3290 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3291 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3292 }
3293
3294 #define IXGBE_MAX_RX_DESC_POLL 10
3295 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3296 struct ixgbe_ring *ring)
3297 {
3298 struct ixgbe_hw *hw = &adapter->hw;
3299 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3300 u32 rxdctl;
3301 u8 reg_idx = ring->reg_idx;
3302
3303 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3304 if (hw->mac.type == ixgbe_mac_82598EB &&
3305 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3306 return;
3307
3308 do {
3309 usleep_range(1000, 2000);
3310 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3311 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3312
3313 if (!wait_loop) {
3314 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3315 "the polling period\n", reg_idx);
3316 }
3317 }
3318
3319 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3320 struct ixgbe_ring *ring)
3321 {
3322 struct ixgbe_hw *hw = &adapter->hw;
3323 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3324 u32 rxdctl;
3325 u8 reg_idx = ring->reg_idx;
3326
3327 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3328 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3329
3330 /* write value back with RXDCTL.ENABLE bit cleared */
3331 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3332
3333 if (hw->mac.type == ixgbe_mac_82598EB &&
3334 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3335 return;
3336
3337 /* the hardware may take up to 100us to really disable the rx queue */
3338 do {
3339 udelay(10);
3340 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3341 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3342
3343 if (!wait_loop) {
3344 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3345 "the polling period\n", reg_idx);
3346 }
3347 }
3348
3349 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3350 struct ixgbe_ring *ring)
3351 {
3352 struct ixgbe_hw *hw = &adapter->hw;
3353 u64 rdba = ring->dma;
3354 u32 rxdctl;
3355 u8 reg_idx = ring->reg_idx;
3356
3357 /* disable queue to avoid issues while updating state */
3358 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3359 ixgbe_disable_rx_queue(adapter, ring);
3360
3361 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3362 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3363 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3364 ring->count * sizeof(union ixgbe_adv_rx_desc));
3365 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3366 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3367 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3368
3369 ixgbe_configure_srrctl(adapter, ring);
3370 ixgbe_configure_rscctl(adapter, ring);
3371
3372 if (hw->mac.type == ixgbe_mac_82598EB) {
3373 /*
3374 * enable cache line friendly hardware writes:
3375 * PTHRESH=32 descriptors (half the internal cache),
3376 * this also removes ugly rx_no_buffer_count increment
3377 * HTHRESH=4 descriptors (to minimize latency on fetch)
3378 * WTHRESH=8 burst writeback up to two cache lines
3379 */
3380 rxdctl &= ~0x3FFFFF;
3381 rxdctl |= 0x080420;
3382 }
3383
3384 /* enable receive descriptor ring */
3385 rxdctl |= IXGBE_RXDCTL_ENABLE;
3386 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3387
3388 ixgbe_rx_desc_queue_enable(adapter, ring);
3389 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3390 }
3391
3392 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3393 {
3394 struct ixgbe_hw *hw = &adapter->hw;
3395 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3396 int p;
3397
3398 /* PSRTYPE must be initialized in non 82598 adapters */
3399 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3400 IXGBE_PSRTYPE_UDPHDR |
3401 IXGBE_PSRTYPE_IPV4HDR |
3402 IXGBE_PSRTYPE_L2HDR |
3403 IXGBE_PSRTYPE_IPV6HDR;
3404
3405 if (hw->mac.type == ixgbe_mac_82598EB)
3406 return;
3407
3408 if (rss_i > 3)
3409 psrtype |= 2 << 29;
3410 else if (rss_i > 1)
3411 psrtype |= 1 << 29;
3412
3413 for (p = 0; p < adapter->num_rx_pools; p++)
3414 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
3415 psrtype);
3416 }
3417
3418 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3419 {
3420 struct ixgbe_hw *hw = &adapter->hw;
3421 u32 reg_offset, vf_shift;
3422 u32 gcr_ext, vmdctl;
3423 int i;
3424
3425 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3426 return;
3427
3428 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3429 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3430 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3431 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3432 vmdctl |= IXGBE_VT_CTL_REPLEN;
3433 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3434
3435 vf_shift = VMDQ_P(0) % 32;
3436 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3437
3438 /* Enable only the PF's pool for Tx/Rx */
3439 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3440 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3441 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3442 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3443 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3444 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3445
3446 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3447 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3448
3449 /*
3450 * Set up VF register offsets for selected VT Mode,
3451 * i.e. 32 or 64 VFs for SR-IOV
3452 */
3453 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3454 case IXGBE_82599_VMDQ_8Q_MASK:
3455 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3456 break;
3457 case IXGBE_82599_VMDQ_4Q_MASK:
3458 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3459 break;
3460 default:
3461 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3462 break;
3463 }
3464
3465 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3466
3467
3468 /* Enable MAC Anti-Spoofing */
3469 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3470 adapter->num_vfs);
3471 /* For VFs that have spoof checking turned off */
3472 for (i = 0; i < adapter->num_vfs; i++) {
3473 if (!adapter->vfinfo[i].spoofchk_enabled)
3474 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3475 }
3476 }
3477
3478 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3479 {
3480 struct ixgbe_hw *hw = &adapter->hw;
3481 struct net_device *netdev = adapter->netdev;
3482 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3483 struct ixgbe_ring *rx_ring;
3484 int i;
3485 u32 mhadd, hlreg0;
3486
3487 #ifdef IXGBE_FCOE
3488 /* adjust max frame to be able to do baby jumbo for FCoE */
3489 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3490 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3491 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3492
3493 #endif /* IXGBE_FCOE */
3494
3495 /* adjust max frame to be at least the size of a standard frame */
3496 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3497 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3498
3499 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3500 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3501 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3502 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3503
3504 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3505 }
3506
3507 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3508 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3509 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3510 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3511
3512 /*
3513 * Setup the HW Rx Head and Tail Descriptor Pointers and
3514 * the Base and Length of the Rx Descriptor Ring
3515 */
3516 for (i = 0; i < adapter->num_rx_queues; i++) {
3517 rx_ring = adapter->rx_ring[i];
3518 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3519 set_ring_rsc_enabled(rx_ring);
3520 else
3521 clear_ring_rsc_enabled(rx_ring);
3522 }
3523 }
3524
3525 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3526 {
3527 struct ixgbe_hw *hw = &adapter->hw;
3528 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3529
3530 switch (hw->mac.type) {
3531 case ixgbe_mac_82598EB:
3532 /*
3533 * For VMDq support of different descriptor types or
3534 * buffer sizes through the use of multiple SRRCTL
3535 * registers, RDRXCTL.MVMEN must be set to 1
3536 *
3537 * also, the manual doesn't mention it clearly but DCA hints
3538 * will only use queue 0's tags unless this bit is set. Side
3539 * effects of setting this bit are only that SRRCTL must be
3540 * fully programmed [0..15]
3541 */
3542 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3543 break;
3544 case ixgbe_mac_82599EB:
3545 case ixgbe_mac_X540:
3546 /* Disable RSC for ACK packets */
3547 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3548 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3549 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3550 /* hardware requires some bits to be set by default */
3551 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3552 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3553 break;
3554 default:
3555 /* We should do nothing since we don't know this hardware */
3556 return;
3557 }
3558
3559 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3560 }
3561
3562 /**
3563 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3564 * @adapter: board private structure
3565 *
3566 * Configure the Rx unit of the MAC after a reset.
3567 **/
3568 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3569 {
3570 struct ixgbe_hw *hw = &adapter->hw;
3571 int i;
3572 u32 rxctrl, rfctl;
3573
3574 /* disable receives while setting up the descriptors */
3575 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3576 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3577
3578 ixgbe_setup_psrtype(adapter);
3579 ixgbe_setup_rdrxctl(adapter);
3580
3581 /* RSC Setup */
3582 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3583 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3584 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3585 rfctl |= IXGBE_RFCTL_RSC_DIS;
3586 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3587
3588 /* Program registers for the distribution of queues */
3589 ixgbe_setup_mrqc(adapter);
3590
3591 /* set_rx_buffer_len must be called before ring initialization */
3592 ixgbe_set_rx_buffer_len(adapter);
3593
3594 /*
3595 * Setup the HW Rx Head and Tail Descriptor Pointers and
3596 * the Base and Length of the Rx Descriptor Ring
3597 */
3598 for (i = 0; i < adapter->num_rx_queues; i++)
3599 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3600
3601 /* disable drop enable for 82598 parts */
3602 if (hw->mac.type == ixgbe_mac_82598EB)
3603 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3604
3605 /* enable all receives */
3606 rxctrl |= IXGBE_RXCTRL_RXEN;
3607 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3608 }
3609
3610 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3611 __be16 proto, u16 vid)
3612 {
3613 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3614 struct ixgbe_hw *hw = &adapter->hw;
3615
3616 /* add VID to filter table */
3617 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3618 set_bit(vid, adapter->active_vlans);
3619
3620 return 0;
3621 }
3622
3623 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3624 __be16 proto, u16 vid)
3625 {
3626 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3627 struct ixgbe_hw *hw = &adapter->hw;
3628
3629 /* remove VID from filter table */
3630 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3631 clear_bit(vid, adapter->active_vlans);
3632
3633 return 0;
3634 }
3635
3636 /**
3637 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3638 * @adapter: driver data
3639 */
3640 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3641 {
3642 struct ixgbe_hw *hw = &adapter->hw;
3643 u32 vlnctrl;
3644
3645 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3646 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3647 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3648 }
3649
3650 /**
3651 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3652 * @adapter: driver data
3653 */
3654 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3655 {
3656 struct ixgbe_hw *hw = &adapter->hw;
3657 u32 vlnctrl;
3658
3659 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3660 vlnctrl |= IXGBE_VLNCTRL_VFE;
3661 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3662 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3663 }
3664
3665 /**
3666 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3667 * @adapter: driver data
3668 */
3669 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3670 {
3671 struct ixgbe_hw *hw = &adapter->hw;
3672 u32 vlnctrl;
3673 int i, j;
3674
3675 switch (hw->mac.type) {
3676 case ixgbe_mac_82598EB:
3677 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3678 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3679 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3680 break;
3681 case ixgbe_mac_82599EB:
3682 case ixgbe_mac_X540:
3683 for (i = 0; i < adapter->num_rx_queues; i++) {
3684 j = adapter->rx_ring[i]->reg_idx;
3685 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3686 vlnctrl &= ~IXGBE_RXDCTL_VME;
3687 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3688 }
3689 break;
3690 default:
3691 break;
3692 }
3693 }
3694
3695 /**
3696 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3697 * @adapter: driver data
3698 */
3699 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3700 {
3701 struct ixgbe_hw *hw = &adapter->hw;
3702 u32 vlnctrl;
3703 int i, j;
3704
3705 switch (hw->mac.type) {
3706 case ixgbe_mac_82598EB:
3707 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3708 vlnctrl |= IXGBE_VLNCTRL_VME;
3709 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3710 break;
3711 case ixgbe_mac_82599EB:
3712 case ixgbe_mac_X540:
3713 for (i = 0; i < adapter->num_rx_queues; i++) {
3714 j = adapter->rx_ring[i]->reg_idx;
3715 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3716 vlnctrl |= IXGBE_RXDCTL_VME;
3717 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3718 }
3719 break;
3720 default:
3721 break;
3722 }
3723 }
3724
3725 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3726 {
3727 u16 vid;
3728
3729 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
3730
3731 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3732 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
3733 }
3734
3735 /**
3736 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3737 * @netdev: network interface device structure
3738 *
3739 * Writes unicast address list to the RAR table.
3740 * Returns: -ENOMEM on failure/insufficient address space
3741 * 0 on no addresses written
3742 * X on writing X addresses to the RAR table
3743 **/
3744 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3745 {
3746 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3747 struct ixgbe_hw *hw = &adapter->hw;
3748 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
3749 int count = 0;
3750
3751 /* In SR-IOV mode significantly less RAR entries are available */
3752 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3753 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3754
3755 /* return ENOMEM indicating insufficient memory for addresses */
3756 if (netdev_uc_count(netdev) > rar_entries)
3757 return -ENOMEM;
3758
3759 if (!netdev_uc_empty(netdev)) {
3760 struct netdev_hw_addr *ha;
3761 /* return error if we do not support writing to RAR table */
3762 if (!hw->mac.ops.set_rar)
3763 return -ENOMEM;
3764
3765 netdev_for_each_uc_addr(ha, netdev) {
3766 if (!rar_entries)
3767 break;
3768 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3769 VMDQ_P(0), IXGBE_RAH_AV);
3770 count++;
3771 }
3772 }
3773 /* write the addresses in reverse order to avoid write combining */
3774 for (; rar_entries > 0 ; rar_entries--)
3775 hw->mac.ops.clear_rar(hw, rar_entries);
3776
3777 return count;
3778 }
3779
3780 /**
3781 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3782 * @netdev: network interface device structure
3783 *
3784 * The set_rx_method entry point is called whenever the unicast/multicast
3785 * address list or the network interface flags are updated. This routine is
3786 * responsible for configuring the hardware for proper unicast, multicast and
3787 * promiscuous mode.
3788 **/
3789 void ixgbe_set_rx_mode(struct net_device *netdev)
3790 {
3791 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3792 struct ixgbe_hw *hw = &adapter->hw;
3793 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3794 int count;
3795
3796 /* Check for Promiscuous and All Multicast modes */
3797
3798 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3799
3800 /* set all bits that we expect to always be set */
3801 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3802 fctrl |= IXGBE_FCTRL_BAM;
3803 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3804 fctrl |= IXGBE_FCTRL_PMCF;
3805
3806 /* clear the bits we are changing the status of */
3807 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3808
3809 if (netdev->flags & IFF_PROMISC) {
3810 hw->addr_ctrl.user_set_promisc = true;
3811 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3812 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3813 /* Only disable hardware filter vlans in promiscuous mode
3814 * if SR-IOV and VMDQ are disabled - otherwise ensure
3815 * that hardware VLAN filters remain enabled.
3816 */
3817 if (!(adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
3818 IXGBE_FLAG_SRIOV_ENABLED)))
3819 ixgbe_vlan_filter_disable(adapter);
3820 else
3821 ixgbe_vlan_filter_enable(adapter);
3822 } else {
3823 if (netdev->flags & IFF_ALLMULTI) {
3824 fctrl |= IXGBE_FCTRL_MPE;
3825 vmolr |= IXGBE_VMOLR_MPE;
3826 } else {
3827 /*
3828 * Write addresses to the MTA, if the attempt fails
3829 * then we should just turn on promiscuous mode so
3830 * that we can at least receive multicast traffic
3831 */
3832 hw->mac.ops.update_mc_addr_list(hw, netdev);
3833 vmolr |= IXGBE_VMOLR_ROMPE;
3834 }
3835 ixgbe_vlan_filter_enable(adapter);
3836 hw->addr_ctrl.user_set_promisc = false;
3837 }
3838
3839 /*
3840 * Write addresses to available RAR registers, if there is not
3841 * sufficient space to store all the addresses then enable
3842 * unicast promiscuous mode
3843 */
3844 count = ixgbe_write_uc_addr_list(netdev);
3845 if (count < 0) {
3846 fctrl |= IXGBE_FCTRL_UPE;
3847 vmolr |= IXGBE_VMOLR_ROPE;
3848 }
3849
3850 if (adapter->num_vfs)
3851 ixgbe_restore_vf_multicasts(adapter);
3852
3853 if (hw->mac.type != ixgbe_mac_82598EB) {
3854 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
3855 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3856 IXGBE_VMOLR_ROPE);
3857 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
3858 }
3859
3860 /* This is useful for sniffing bad packets. */
3861 if (adapter->netdev->features & NETIF_F_RXALL) {
3862 /* UPE and MPE will be handled by normal PROMISC logic
3863 * in e1000e_set_rx_mode */
3864 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3865 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3866 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3867
3868 fctrl &= ~(IXGBE_FCTRL_DPF);
3869 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3870 }
3871
3872 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3873
3874 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3875 ixgbe_vlan_strip_enable(adapter);
3876 else
3877 ixgbe_vlan_strip_disable(adapter);
3878 }
3879
3880 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3881 {
3882 int q_idx;
3883
3884 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
3885 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
3886 napi_enable(&adapter->q_vector[q_idx]->napi);
3887 }
3888 }
3889
3890 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3891 {
3892 int q_idx;
3893
3894 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
3895 napi_disable(&adapter->q_vector[q_idx]->napi);
3896 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
3897 pr_info("QV %d locked\n", q_idx);
3898 usleep_range(1000, 20000);
3899 }
3900 }
3901 }
3902
3903 #ifdef CONFIG_IXGBE_DCB
3904 /**
3905 * ixgbe_configure_dcb - Configure DCB hardware
3906 * @adapter: ixgbe adapter struct
3907 *
3908 * This is called by the driver on open to configure the DCB hardware.
3909 * This is also called by the gennetlink interface when reconfiguring
3910 * the DCB state.
3911 */
3912 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3913 {
3914 struct ixgbe_hw *hw = &adapter->hw;
3915 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3916
3917 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3918 if (hw->mac.type == ixgbe_mac_82598EB)
3919 netif_set_gso_max_size(adapter->netdev, 65536);
3920 return;
3921 }
3922
3923 if (hw->mac.type == ixgbe_mac_82598EB)
3924 netif_set_gso_max_size(adapter->netdev, 32768);
3925
3926 #ifdef IXGBE_FCOE
3927 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3928 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3929 #endif
3930
3931 /* reconfigure the hardware */
3932 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3933 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3934 DCB_TX_CONFIG);
3935 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3936 DCB_RX_CONFIG);
3937 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3938 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3939 ixgbe_dcb_hw_ets(&adapter->hw,
3940 adapter->ixgbe_ieee_ets,
3941 max_frame);
3942 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3943 adapter->ixgbe_ieee_pfc->pfc_en,
3944 adapter->ixgbe_ieee_ets->prio_tc);
3945 }
3946
3947 /* Enable RSS Hash per TC */
3948 if (hw->mac.type != ixgbe_mac_82598EB) {
3949 u32 msb = 0;
3950 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
3951
3952 while (rss_i) {
3953 msb++;
3954 rss_i >>= 1;
3955 }
3956
3957 /* write msb to all 8 TCs in one write */
3958 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
3959 }
3960 }
3961 #endif
3962
3963 /* Additional bittime to account for IXGBE framing */
3964 #define IXGBE_ETH_FRAMING 20
3965
3966 /**
3967 * ixgbe_hpbthresh - calculate high water mark for flow control
3968 *
3969 * @adapter: board private structure to calculate for
3970 * @pb: packet buffer to calculate
3971 */
3972 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3973 {
3974 struct ixgbe_hw *hw = &adapter->hw;
3975 struct net_device *dev = adapter->netdev;
3976 int link, tc, kb, marker;
3977 u32 dv_id, rx_pba;
3978
3979 /* Calculate max LAN frame size */
3980 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3981
3982 #ifdef IXGBE_FCOE
3983 /* FCoE traffic class uses FCOE jumbo frames */
3984 if ((dev->features & NETIF_F_FCOE_MTU) &&
3985 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3986 (pb == ixgbe_fcoe_get_tc(adapter)))
3987 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3988
3989 #endif
3990 /* Calculate delay value for device */
3991 switch (hw->mac.type) {
3992 case ixgbe_mac_X540:
3993 dv_id = IXGBE_DV_X540(link, tc);
3994 break;
3995 default:
3996 dv_id = IXGBE_DV(link, tc);
3997 break;
3998 }
3999
4000 /* Loopback switch introduces additional latency */
4001 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4002 dv_id += IXGBE_B2BT(tc);
4003
4004 /* Delay value is calculated in bit times convert to KB */
4005 kb = IXGBE_BT2KB(dv_id);
4006 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4007
4008 marker = rx_pba - kb;
4009
4010 /* It is possible that the packet buffer is not large enough
4011 * to provide required headroom. In this case throw an error
4012 * to user and a do the best we can.
4013 */
4014 if (marker < 0) {
4015 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4016 "headroom to support flow control."
4017 "Decrease MTU or number of traffic classes\n", pb);
4018 marker = tc + 1;
4019 }
4020
4021 return marker;
4022 }
4023
4024 /**
4025 * ixgbe_lpbthresh - calculate low water mark for for flow control
4026 *
4027 * @adapter: board private structure to calculate for
4028 * @pb: packet buffer to calculate
4029 */
4030 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
4031 {
4032 struct ixgbe_hw *hw = &adapter->hw;
4033 struct net_device *dev = adapter->netdev;
4034 int tc;
4035 u32 dv_id;
4036
4037 /* Calculate max LAN frame size */
4038 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4039
4040 /* Calculate delay value for device */
4041 switch (hw->mac.type) {
4042 case ixgbe_mac_X540:
4043 dv_id = IXGBE_LOW_DV_X540(tc);
4044 break;
4045 default:
4046 dv_id = IXGBE_LOW_DV(tc);
4047 break;
4048 }
4049
4050 /* Delay value is calculated in bit times convert to KB */
4051 return IXGBE_BT2KB(dv_id);
4052 }
4053
4054 /*
4055 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4056 */
4057 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4058 {
4059 struct ixgbe_hw *hw = &adapter->hw;
4060 int num_tc = netdev_get_num_tc(adapter->netdev);
4061 int i;
4062
4063 if (!num_tc)
4064 num_tc = 1;
4065
4066 hw->fc.low_water = ixgbe_lpbthresh(adapter);
4067
4068 for (i = 0; i < num_tc; i++) {
4069 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4070
4071 /* Low water marks must not be larger than high water marks */
4072 if (hw->fc.low_water > hw->fc.high_water[i])
4073 hw->fc.low_water = 0;
4074 }
4075 }
4076
4077 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4078 {
4079 struct ixgbe_hw *hw = &adapter->hw;
4080 int hdrm;
4081 u8 tc = netdev_get_num_tc(adapter->netdev);
4082
4083 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4084 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4085 hdrm = 32 << adapter->fdir_pballoc;
4086 else
4087 hdrm = 0;
4088
4089 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
4090 ixgbe_pbthresh_setup(adapter);
4091 }
4092
4093 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4094 {
4095 struct ixgbe_hw *hw = &adapter->hw;
4096 struct hlist_node *node2;
4097 struct ixgbe_fdir_filter *filter;
4098
4099 spin_lock(&adapter->fdir_perfect_lock);
4100
4101 if (!hlist_empty(&adapter->fdir_filter_list))
4102 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4103
4104 hlist_for_each_entry_safe(filter, node2,
4105 &adapter->fdir_filter_list, fdir_node) {
4106 ixgbe_fdir_write_perfect_filter_82599(hw,
4107 &filter->filter,
4108 filter->sw_idx,
4109 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4110 IXGBE_FDIR_DROP_QUEUE :
4111 adapter->rx_ring[filter->action]->reg_idx);
4112 }
4113
4114 spin_unlock(&adapter->fdir_perfect_lock);
4115 }
4116
4117 static void ixgbe_configure(struct ixgbe_adapter *adapter)
4118 {
4119 struct ixgbe_hw *hw = &adapter->hw;
4120
4121 ixgbe_configure_pb(adapter);
4122 #ifdef CONFIG_IXGBE_DCB
4123 ixgbe_configure_dcb(adapter);
4124 #endif
4125 /*
4126 * We must restore virtualization before VLANs or else
4127 * the VLVF registers will not be populated
4128 */
4129 ixgbe_configure_virtualization(adapter);
4130
4131 ixgbe_set_rx_mode(adapter->netdev);
4132 ixgbe_restore_vlan(adapter);
4133
4134 switch (hw->mac.type) {
4135 case ixgbe_mac_82599EB:
4136 case ixgbe_mac_X540:
4137 hw->mac.ops.disable_rx_buff(hw);
4138 break;
4139 default:
4140 break;
4141 }
4142
4143 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4144 ixgbe_init_fdir_signature_82599(&adapter->hw,
4145 adapter->fdir_pballoc);
4146 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4147 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4148 adapter->fdir_pballoc);
4149 ixgbe_fdir_filter_restore(adapter);
4150 }
4151
4152 switch (hw->mac.type) {
4153 case ixgbe_mac_82599EB:
4154 case ixgbe_mac_X540:
4155 hw->mac.ops.enable_rx_buff(hw);
4156 break;
4157 default:
4158 break;
4159 }
4160
4161 #ifdef IXGBE_FCOE
4162 /* configure FCoE L2 filters, redirection table, and Rx control */
4163 ixgbe_configure_fcoe(adapter);
4164
4165 #endif /* IXGBE_FCOE */
4166 ixgbe_configure_tx(adapter);
4167 ixgbe_configure_rx(adapter);
4168 }
4169
4170 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4171 {
4172 switch (hw->phy.type) {
4173 case ixgbe_phy_sfp_avago:
4174 case ixgbe_phy_sfp_ftl:
4175 case ixgbe_phy_sfp_intel:
4176 case ixgbe_phy_sfp_unknown:
4177 case ixgbe_phy_sfp_passive_tyco:
4178 case ixgbe_phy_sfp_passive_unknown:
4179 case ixgbe_phy_sfp_active_unknown:
4180 case ixgbe_phy_sfp_ftl_active:
4181 case ixgbe_phy_qsfp_passive_unknown:
4182 case ixgbe_phy_qsfp_active_unknown:
4183 case ixgbe_phy_qsfp_intel:
4184 case ixgbe_phy_qsfp_unknown:
4185 return true;
4186 case ixgbe_phy_nl:
4187 if (hw->mac.type == ixgbe_mac_82598EB)
4188 return true;
4189 default:
4190 return false;
4191 }
4192 }
4193
4194 /**
4195 * ixgbe_sfp_link_config - set up SFP+ link
4196 * @adapter: pointer to private adapter struct
4197 **/
4198 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4199 {
4200 /*
4201 * We are assuming the worst case scenario here, and that
4202 * is that an SFP was inserted/removed after the reset
4203 * but before SFP detection was enabled. As such the best
4204 * solution is to just start searching as soon as we start
4205 */
4206 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4207 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4208
4209 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4210 }
4211
4212 /**
4213 * ixgbe_non_sfp_link_config - set up non-SFP+ link
4214 * @hw: pointer to private hardware struct
4215 *
4216 * Returns 0 on success, negative on failure
4217 **/
4218 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4219 {
4220 u32 speed;
4221 bool autoneg, link_up = false;
4222 u32 ret = IXGBE_ERR_LINK_SETUP;
4223
4224 if (hw->mac.ops.check_link)
4225 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
4226
4227 if (ret)
4228 goto link_cfg_out;
4229
4230 speed = hw->phy.autoneg_advertised;
4231 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4232 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4233 &autoneg);
4234 if (ret)
4235 goto link_cfg_out;
4236
4237 if (hw->mac.ops.setup_link)
4238 ret = hw->mac.ops.setup_link(hw, speed, link_up);
4239 link_cfg_out:
4240 return ret;
4241 }
4242
4243 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4244 {
4245 struct ixgbe_hw *hw = &adapter->hw;
4246 u32 gpie = 0;
4247
4248 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4249 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4250 IXGBE_GPIE_OCD;
4251 gpie |= IXGBE_GPIE_EIAME;
4252 /*
4253 * use EIAM to auto-mask when MSI-X interrupt is asserted
4254 * this saves a register write for every interrupt
4255 */
4256 switch (hw->mac.type) {
4257 case ixgbe_mac_82598EB:
4258 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4259 break;
4260 case ixgbe_mac_82599EB:
4261 case ixgbe_mac_X540:
4262 default:
4263 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4264 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4265 break;
4266 }
4267 } else {
4268 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4269 * specifically only auto mask tx and rx interrupts */
4270 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4271 }
4272
4273 /* XXX: to interrupt immediately for EICS writes, enable this */
4274 /* gpie |= IXGBE_GPIE_EIMEN; */
4275
4276 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4277 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4278
4279 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4280 case IXGBE_82599_VMDQ_8Q_MASK:
4281 gpie |= IXGBE_GPIE_VTMODE_16;
4282 break;
4283 case IXGBE_82599_VMDQ_4Q_MASK:
4284 gpie |= IXGBE_GPIE_VTMODE_32;
4285 break;
4286 default:
4287 gpie |= IXGBE_GPIE_VTMODE_64;
4288 break;
4289 }
4290 }
4291
4292 /* Enable Thermal over heat sensor interrupt */
4293 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4294 switch (adapter->hw.mac.type) {
4295 case ixgbe_mac_82599EB:
4296 gpie |= IXGBE_SDP0_GPIEN;
4297 break;
4298 case ixgbe_mac_X540:
4299 gpie |= IXGBE_EIMS_TS;
4300 break;
4301 default:
4302 break;
4303 }
4304 }
4305
4306 /* Enable fan failure interrupt */
4307 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4308 gpie |= IXGBE_SDP1_GPIEN;
4309
4310 if (hw->mac.type == ixgbe_mac_82599EB) {
4311 gpie |= IXGBE_SDP1_GPIEN;
4312 gpie |= IXGBE_SDP2_GPIEN;
4313 }
4314
4315 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4316 }
4317
4318 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4319 {
4320 struct ixgbe_hw *hw = &adapter->hw;
4321 int err;
4322 u32 ctrl_ext;
4323
4324 ixgbe_get_hw_control(adapter);
4325 ixgbe_setup_gpie(adapter);
4326
4327 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4328 ixgbe_configure_msix(adapter);
4329 else
4330 ixgbe_configure_msi_and_legacy(adapter);
4331
4332 /* enable the optics for 82599 SFP+ fiber */
4333 if (hw->mac.ops.enable_tx_laser)
4334 hw->mac.ops.enable_tx_laser(hw);
4335
4336 clear_bit(__IXGBE_DOWN, &adapter->state);
4337 ixgbe_napi_enable_all(adapter);
4338
4339 if (ixgbe_is_sfp(hw)) {
4340 ixgbe_sfp_link_config(adapter);
4341 } else {
4342 err = ixgbe_non_sfp_link_config(hw);
4343 if (err)
4344 e_err(probe, "link_config FAILED %d\n", err);
4345 }
4346
4347 /* clear any pending interrupts, may auto mask */
4348 IXGBE_READ_REG(hw, IXGBE_EICR);
4349 ixgbe_irq_enable(adapter, true, true);
4350
4351 /*
4352 * If this adapter has a fan, check to see if we had a failure
4353 * before we enabled the interrupt.
4354 */
4355 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4356 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4357 if (esdp & IXGBE_ESDP_SDP1)
4358 e_crit(drv, "Fan has stopped, replace the adapter\n");
4359 }
4360
4361 /* enable transmits */
4362 netif_tx_start_all_queues(adapter->netdev);
4363
4364 /* bring the link up in the watchdog, this could race with our first
4365 * link up interrupt but shouldn't be a problem */
4366 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4367 adapter->link_check_timeout = jiffies;
4368 mod_timer(&adapter->service_timer, jiffies);
4369
4370 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4371 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4372 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4373 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4374 }
4375
4376 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4377 {
4378 WARN_ON(in_interrupt());
4379 /* put off any impending NetWatchDogTimeout */
4380 adapter->netdev->trans_start = jiffies;
4381
4382 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4383 usleep_range(1000, 2000);
4384 ixgbe_down(adapter);
4385 /*
4386 * If SR-IOV enabled then wait a bit before bringing the adapter
4387 * back up to give the VFs time to respond to the reset. The
4388 * two second wait is based upon the watchdog timer cycle in
4389 * the VF driver.
4390 */
4391 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4392 msleep(2000);
4393 ixgbe_up(adapter);
4394 clear_bit(__IXGBE_RESETTING, &adapter->state);
4395 }
4396
4397 void ixgbe_up(struct ixgbe_adapter *adapter)
4398 {
4399 /* hardware has been reset, we need to reload some things */
4400 ixgbe_configure(adapter);
4401
4402 ixgbe_up_complete(adapter);
4403 }
4404
4405 void ixgbe_reset(struct ixgbe_adapter *adapter)
4406 {
4407 struct ixgbe_hw *hw = &adapter->hw;
4408 int err;
4409
4410 /* lock SFP init bit to prevent race conditions with the watchdog */
4411 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4412 usleep_range(1000, 2000);
4413
4414 /* clear all SFP and link config related flags while holding SFP_INIT */
4415 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4416 IXGBE_FLAG2_SFP_NEEDS_RESET);
4417 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4418
4419 err = hw->mac.ops.init_hw(hw);
4420 switch (err) {
4421 case 0:
4422 case IXGBE_ERR_SFP_NOT_PRESENT:
4423 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4424 break;
4425 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4426 e_dev_err("master disable timed out\n");
4427 break;
4428 case IXGBE_ERR_EEPROM_VERSION:
4429 /* We are running on a pre-production device, log a warning */
4430 e_dev_warn("This device is a pre-production adapter/LOM. "
4431 "Please be aware there may be issues associated with "
4432 "your hardware. If you are experiencing problems "
4433 "please contact your Intel or hardware "
4434 "representative who provided you with this "
4435 "hardware.\n");
4436 break;
4437 default:
4438 e_dev_err("Hardware Error: %d\n", err);
4439 }
4440
4441 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4442
4443 /* reprogram the RAR[0] in case user changed it. */
4444 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
4445
4446 /* update SAN MAC vmdq pool selection */
4447 if (hw->mac.san_mac_rar_index)
4448 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4449
4450 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
4451 ixgbe_ptp_reset(adapter);
4452 }
4453
4454 /**
4455 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4456 * @rx_ring: ring to free buffers from
4457 **/
4458 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4459 {
4460 struct device *dev = rx_ring->dev;
4461 unsigned long size;
4462 u16 i;
4463
4464 /* ring already cleared, nothing to do */
4465 if (!rx_ring->rx_buffer_info)
4466 return;
4467
4468 /* Free all the Rx ring sk_buffs */
4469 for (i = 0; i < rx_ring->count; i++) {
4470 struct ixgbe_rx_buffer *rx_buffer;
4471
4472 rx_buffer = &rx_ring->rx_buffer_info[i];
4473 if (rx_buffer->skb) {
4474 struct sk_buff *skb = rx_buffer->skb;
4475 if (IXGBE_CB(skb)->page_released) {
4476 dma_unmap_page(dev,
4477 IXGBE_CB(skb)->dma,
4478 ixgbe_rx_bufsz(rx_ring),
4479 DMA_FROM_DEVICE);
4480 IXGBE_CB(skb)->page_released = false;
4481 }
4482 dev_kfree_skb(skb);
4483 }
4484 rx_buffer->skb = NULL;
4485 if (rx_buffer->dma)
4486 dma_unmap_page(dev, rx_buffer->dma,
4487 ixgbe_rx_pg_size(rx_ring),
4488 DMA_FROM_DEVICE);
4489 rx_buffer->dma = 0;
4490 if (rx_buffer->page)
4491 __free_pages(rx_buffer->page,
4492 ixgbe_rx_pg_order(rx_ring));
4493 rx_buffer->page = NULL;
4494 }
4495
4496 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4497 memset(rx_ring->rx_buffer_info, 0, size);
4498
4499 /* Zero out the descriptor ring */
4500 memset(rx_ring->desc, 0, rx_ring->size);
4501
4502 rx_ring->next_to_alloc = 0;
4503 rx_ring->next_to_clean = 0;
4504 rx_ring->next_to_use = 0;
4505 }
4506
4507 /**
4508 * ixgbe_clean_tx_ring - Free Tx Buffers
4509 * @tx_ring: ring to be cleaned
4510 **/
4511 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4512 {
4513 struct ixgbe_tx_buffer *tx_buffer_info;
4514 unsigned long size;
4515 u16 i;
4516
4517 /* ring already cleared, nothing to do */
4518 if (!tx_ring->tx_buffer_info)
4519 return;
4520
4521 /* Free all the Tx ring sk_buffs */
4522 for (i = 0; i < tx_ring->count; i++) {
4523 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4524 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4525 }
4526
4527 netdev_tx_reset_queue(txring_txq(tx_ring));
4528
4529 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4530 memset(tx_ring->tx_buffer_info, 0, size);
4531
4532 /* Zero out the descriptor ring */
4533 memset(tx_ring->desc, 0, tx_ring->size);
4534
4535 tx_ring->next_to_use = 0;
4536 tx_ring->next_to_clean = 0;
4537 }
4538
4539 /**
4540 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4541 * @adapter: board private structure
4542 **/
4543 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4544 {
4545 int i;
4546
4547 for (i = 0; i < adapter->num_rx_queues; i++)
4548 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4549 }
4550
4551 /**
4552 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4553 * @adapter: board private structure
4554 **/
4555 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4556 {
4557 int i;
4558
4559 for (i = 0; i < adapter->num_tx_queues; i++)
4560 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4561 }
4562
4563 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4564 {
4565 struct hlist_node *node2;
4566 struct ixgbe_fdir_filter *filter;
4567
4568 spin_lock(&adapter->fdir_perfect_lock);
4569
4570 hlist_for_each_entry_safe(filter, node2,
4571 &adapter->fdir_filter_list, fdir_node) {
4572 hlist_del(&filter->fdir_node);
4573 kfree(filter);
4574 }
4575 adapter->fdir_filter_count = 0;
4576
4577 spin_unlock(&adapter->fdir_perfect_lock);
4578 }
4579
4580 void ixgbe_down(struct ixgbe_adapter *adapter)
4581 {
4582 struct net_device *netdev = adapter->netdev;
4583 struct ixgbe_hw *hw = &adapter->hw;
4584 u32 rxctrl;
4585 int i;
4586
4587 /* signal that we are down to the interrupt handler */
4588 set_bit(__IXGBE_DOWN, &adapter->state);
4589
4590 /* disable receives */
4591 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4592 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4593
4594 /* disable all enabled rx queues */
4595 for (i = 0; i < adapter->num_rx_queues; i++)
4596 /* this call also flushes the previous write */
4597 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4598
4599 usleep_range(10000, 20000);
4600
4601 netif_tx_stop_all_queues(netdev);
4602
4603 /* call carrier off first to avoid false dev_watchdog timeouts */
4604 netif_carrier_off(netdev);
4605 netif_tx_disable(netdev);
4606
4607 ixgbe_irq_disable(adapter);
4608
4609 ixgbe_napi_disable_all(adapter);
4610
4611 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4612 IXGBE_FLAG2_RESET_REQUESTED);
4613 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4614
4615 del_timer_sync(&adapter->service_timer);
4616
4617 if (adapter->num_vfs) {
4618 /* Clear EITR Select mapping */
4619 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4620
4621 /* Mark all the VFs as inactive */
4622 for (i = 0 ; i < adapter->num_vfs; i++)
4623 adapter->vfinfo[i].clear_to_send = false;
4624
4625 /* ping all the active vfs to let them know we are going down */
4626 ixgbe_ping_all_vfs(adapter);
4627
4628 /* Disable all VFTE/VFRE TX/RX */
4629 ixgbe_disable_tx_rx(adapter);
4630 }
4631
4632 /* disable transmits in the hardware now that interrupts are off */
4633 for (i = 0; i < adapter->num_tx_queues; i++) {
4634 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4635 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4636 }
4637
4638 /* Disable the Tx DMA engine on 82599 and X540 */
4639 switch (hw->mac.type) {
4640 case ixgbe_mac_82599EB:
4641 case ixgbe_mac_X540:
4642 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4643 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4644 ~IXGBE_DMATXCTL_TE));
4645 break;
4646 default:
4647 break;
4648 }
4649
4650 if (!pci_channel_offline(adapter->pdev))
4651 ixgbe_reset(adapter);
4652
4653 /* power down the optics for 82599 SFP+ fiber */
4654 if (hw->mac.ops.disable_tx_laser)
4655 hw->mac.ops.disable_tx_laser(hw);
4656
4657 ixgbe_clean_all_tx_rings(adapter);
4658 ixgbe_clean_all_rx_rings(adapter);
4659
4660 #ifdef CONFIG_IXGBE_DCA
4661 /* since we reset the hardware DCA settings were cleared */
4662 ixgbe_setup_dca(adapter);
4663 #endif
4664 }
4665
4666 /**
4667 * ixgbe_tx_timeout - Respond to a Tx Hang
4668 * @netdev: network interface device structure
4669 **/
4670 static void ixgbe_tx_timeout(struct net_device *netdev)
4671 {
4672 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4673
4674 /* Do the reset outside of interrupt context */
4675 ixgbe_tx_timeout_reset(adapter);
4676 }
4677
4678 /**
4679 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4680 * @adapter: board private structure to initialize
4681 *
4682 * ixgbe_sw_init initializes the Adapter private data structure.
4683 * Fields are initialized based on PCI device information and
4684 * OS network device settings (MTU size).
4685 **/
4686 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
4687 {
4688 struct ixgbe_hw *hw = &adapter->hw;
4689 struct pci_dev *pdev = adapter->pdev;
4690 unsigned int rss, fdir;
4691 u32 fwsm;
4692 #ifdef CONFIG_IXGBE_DCB
4693 int j;
4694 struct tc_configuration *tc;
4695 #endif
4696
4697 /* PCI config space info */
4698
4699 hw->vendor_id = pdev->vendor;
4700 hw->device_id = pdev->device;
4701 hw->revision_id = pdev->revision;
4702 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4703 hw->subsystem_device_id = pdev->subsystem_device;
4704
4705 /* Set common capability flags and settings */
4706 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4707 adapter->ring_feature[RING_F_RSS].limit = rss;
4708 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4709 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4710 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
4711 adapter->atr_sample_rate = 20;
4712 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
4713 adapter->ring_feature[RING_F_FDIR].limit = fdir;
4714 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4715 #ifdef CONFIG_IXGBE_DCA
4716 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
4717 #endif
4718 #ifdef IXGBE_FCOE
4719 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4720 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4721 #ifdef CONFIG_IXGBE_DCB
4722 /* Default traffic class to use for FCoE */
4723 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4724 #endif /* CONFIG_IXGBE_DCB */
4725 #endif /* IXGBE_FCOE */
4726
4727 /* Set MAC specific capability flags and exceptions */
4728 switch (hw->mac.type) {
4729 case ixgbe_mac_82598EB:
4730 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
4731 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
4732
4733 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4734 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4735
4736 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
4737 adapter->ring_feature[RING_F_FDIR].limit = 0;
4738 adapter->atr_sample_rate = 0;
4739 adapter->fdir_pballoc = 0;
4740 #ifdef IXGBE_FCOE
4741 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
4742 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4743 #ifdef CONFIG_IXGBE_DCB
4744 adapter->fcoe.up = 0;
4745 #endif /* IXGBE_DCB */
4746 #endif /* IXGBE_FCOE */
4747 break;
4748 case ixgbe_mac_82599EB:
4749 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4750 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4751 break;
4752 case ixgbe_mac_X540:
4753 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4754 if (fwsm & IXGBE_FWSM_TS_ENABLED)
4755 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4756 break;
4757 default:
4758 break;
4759 }
4760
4761 #ifdef IXGBE_FCOE
4762 /* FCoE support exists, always init the FCoE lock */
4763 spin_lock_init(&adapter->fcoe.lock);
4764
4765 #endif
4766 /* n-tuple support exists, always init our spinlock */
4767 spin_lock_init(&adapter->fdir_perfect_lock);
4768
4769 #ifdef CONFIG_IXGBE_DCB
4770 switch (hw->mac.type) {
4771 case ixgbe_mac_X540:
4772 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4773 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4774 break;
4775 default:
4776 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4777 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4778 break;
4779 }
4780
4781 /* Configure DCB traffic classes */
4782 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4783 tc = &adapter->dcb_cfg.tc_config[j];
4784 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4785 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4786 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4787 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4788 tc->dcb_pfc = pfc_disabled;
4789 }
4790
4791 /* Initialize default user to priority mapping, UPx->TC0 */
4792 tc = &adapter->dcb_cfg.tc_config[0];
4793 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4794 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4795
4796 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4797 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4798 adapter->dcb_cfg.pfc_mode_enable = false;
4799 adapter->dcb_set_bitmap = 0x00;
4800 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4801 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4802 sizeof(adapter->temp_dcb_cfg));
4803
4804 #endif
4805
4806 /* default flow control settings */
4807 hw->fc.requested_mode = ixgbe_fc_full;
4808 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4809 ixgbe_pbthresh_setup(adapter);
4810 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4811 hw->fc.send_xon = true;
4812 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
4813
4814 #ifdef CONFIG_PCI_IOV
4815 /* assign number of SR-IOV VFs */
4816 if (hw->mac.type != ixgbe_mac_82598EB)
4817 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4818
4819 #endif
4820 /* enable itr by default in dynamic mode */
4821 adapter->rx_itr_setting = 1;
4822 adapter->tx_itr_setting = 1;
4823
4824 /* set default ring sizes */
4825 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4826 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4827
4828 /* set default work limits */
4829 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4830
4831 /* initialize eeprom parameters */
4832 if (ixgbe_init_eeprom_params_generic(hw)) {
4833 e_dev_err("EEPROM initialization failed\n");
4834 return -EIO;
4835 }
4836
4837 set_bit(__IXGBE_DOWN, &adapter->state);
4838
4839 return 0;
4840 }
4841
4842 /**
4843 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4844 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4845 *
4846 * Return 0 on success, negative on failure
4847 **/
4848 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4849 {
4850 struct device *dev = tx_ring->dev;
4851 int orig_node = dev_to_node(dev);
4852 int numa_node = -1;
4853 int size;
4854
4855 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4856
4857 if (tx_ring->q_vector)
4858 numa_node = tx_ring->q_vector->numa_node;
4859
4860 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4861 if (!tx_ring->tx_buffer_info)
4862 tx_ring->tx_buffer_info = vzalloc(size);
4863 if (!tx_ring->tx_buffer_info)
4864 goto err;
4865
4866 /* round up to nearest 4K */
4867 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4868 tx_ring->size = ALIGN(tx_ring->size, 4096);
4869
4870 set_dev_node(dev, numa_node);
4871 tx_ring->desc = dma_alloc_coherent(dev,
4872 tx_ring->size,
4873 &tx_ring->dma,
4874 GFP_KERNEL);
4875 set_dev_node(dev, orig_node);
4876 if (!tx_ring->desc)
4877 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4878 &tx_ring->dma, GFP_KERNEL);
4879 if (!tx_ring->desc)
4880 goto err;
4881
4882 tx_ring->next_to_use = 0;
4883 tx_ring->next_to_clean = 0;
4884 return 0;
4885
4886 err:
4887 vfree(tx_ring->tx_buffer_info);
4888 tx_ring->tx_buffer_info = NULL;
4889 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4890 return -ENOMEM;
4891 }
4892
4893 /**
4894 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4895 * @adapter: board private structure
4896 *
4897 * If this function returns with an error, then it's possible one or
4898 * more of the rings is populated (while the rest are not). It is the
4899 * callers duty to clean those orphaned rings.
4900 *
4901 * Return 0 on success, negative on failure
4902 **/
4903 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4904 {
4905 int i, err = 0;
4906
4907 for (i = 0; i < adapter->num_tx_queues; i++) {
4908 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4909 if (!err)
4910 continue;
4911
4912 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4913 goto err_setup_tx;
4914 }
4915
4916 return 0;
4917 err_setup_tx:
4918 /* rewind the index freeing the rings as we go */
4919 while (i--)
4920 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4921 return err;
4922 }
4923
4924 /**
4925 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4926 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4927 *
4928 * Returns 0 on success, negative on failure
4929 **/
4930 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4931 {
4932 struct device *dev = rx_ring->dev;
4933 int orig_node = dev_to_node(dev);
4934 int numa_node = -1;
4935 int size;
4936
4937 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4938
4939 if (rx_ring->q_vector)
4940 numa_node = rx_ring->q_vector->numa_node;
4941
4942 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4943 if (!rx_ring->rx_buffer_info)
4944 rx_ring->rx_buffer_info = vzalloc(size);
4945 if (!rx_ring->rx_buffer_info)
4946 goto err;
4947
4948 /* Round up to nearest 4K */
4949 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4950 rx_ring->size = ALIGN(rx_ring->size, 4096);
4951
4952 set_dev_node(dev, numa_node);
4953 rx_ring->desc = dma_alloc_coherent(dev,
4954 rx_ring->size,
4955 &rx_ring->dma,
4956 GFP_KERNEL);
4957 set_dev_node(dev, orig_node);
4958 if (!rx_ring->desc)
4959 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4960 &rx_ring->dma, GFP_KERNEL);
4961 if (!rx_ring->desc)
4962 goto err;
4963
4964 rx_ring->next_to_clean = 0;
4965 rx_ring->next_to_use = 0;
4966
4967 return 0;
4968 err:
4969 vfree(rx_ring->rx_buffer_info);
4970 rx_ring->rx_buffer_info = NULL;
4971 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4972 return -ENOMEM;
4973 }
4974
4975 /**
4976 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4977 * @adapter: board private structure
4978 *
4979 * If this function returns with an error, then it's possible one or
4980 * more of the rings is populated (while the rest are not). It is the
4981 * callers duty to clean those orphaned rings.
4982 *
4983 * Return 0 on success, negative on failure
4984 **/
4985 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4986 {
4987 int i, err = 0;
4988
4989 for (i = 0; i < adapter->num_rx_queues; i++) {
4990 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4991 if (!err)
4992 continue;
4993
4994 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4995 goto err_setup_rx;
4996 }
4997
4998 #ifdef IXGBE_FCOE
4999 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5000 if (!err)
5001 #endif
5002 return 0;
5003 err_setup_rx:
5004 /* rewind the index freeing the rings as we go */
5005 while (i--)
5006 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5007 return err;
5008 }
5009
5010 /**
5011 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5012 * @tx_ring: Tx descriptor ring for a specific queue
5013 *
5014 * Free all transmit software resources
5015 **/
5016 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5017 {
5018 ixgbe_clean_tx_ring(tx_ring);
5019
5020 vfree(tx_ring->tx_buffer_info);
5021 tx_ring->tx_buffer_info = NULL;
5022
5023 /* if not set, then don't free */
5024 if (!tx_ring->desc)
5025 return;
5026
5027 dma_free_coherent(tx_ring->dev, tx_ring->size,
5028 tx_ring->desc, tx_ring->dma);
5029
5030 tx_ring->desc = NULL;
5031 }
5032
5033 /**
5034 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5035 * @adapter: board private structure
5036 *
5037 * Free all transmit software resources
5038 **/
5039 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5040 {
5041 int i;
5042
5043 for (i = 0; i < adapter->num_tx_queues; i++)
5044 if (adapter->tx_ring[i]->desc)
5045 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5046 }
5047
5048 /**
5049 * ixgbe_free_rx_resources - Free Rx Resources
5050 * @rx_ring: ring to clean the resources from
5051 *
5052 * Free all receive software resources
5053 **/
5054 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5055 {
5056 ixgbe_clean_rx_ring(rx_ring);
5057
5058 vfree(rx_ring->rx_buffer_info);
5059 rx_ring->rx_buffer_info = NULL;
5060
5061 /* if not set, then don't free */
5062 if (!rx_ring->desc)
5063 return;
5064
5065 dma_free_coherent(rx_ring->dev, rx_ring->size,
5066 rx_ring->desc, rx_ring->dma);
5067
5068 rx_ring->desc = NULL;
5069 }
5070
5071 /**
5072 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5073 * @adapter: board private structure
5074 *
5075 * Free all receive software resources
5076 **/
5077 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5078 {
5079 int i;
5080
5081 #ifdef IXGBE_FCOE
5082 ixgbe_free_fcoe_ddp_resources(adapter);
5083
5084 #endif
5085 for (i = 0; i < adapter->num_rx_queues; i++)
5086 if (adapter->rx_ring[i]->desc)
5087 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5088 }
5089
5090 /**
5091 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5092 * @netdev: network interface device structure
5093 * @new_mtu: new value for maximum frame size
5094 *
5095 * Returns 0 on success, negative on failure
5096 **/
5097 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5098 {
5099 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5100 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5101
5102 /* MTU < 68 is an error and causes problems on some kernels */
5103 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5104 return -EINVAL;
5105
5106 /*
5107 * For 82599EB we cannot allow legacy VFs to enable their receive
5108 * paths when MTU greater than 1500 is configured. So display a
5109 * warning that legacy VFs will be disabled.
5110 */
5111 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5112 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
5113 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
5114 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
5115
5116 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5117
5118 /* must set new MTU before calling down or up */
5119 netdev->mtu = new_mtu;
5120
5121 if (netif_running(netdev))
5122 ixgbe_reinit_locked(adapter);
5123
5124 return 0;
5125 }
5126
5127 /**
5128 * ixgbe_open - Called when a network interface is made active
5129 * @netdev: network interface device structure
5130 *
5131 * Returns 0 on success, negative value on failure
5132 *
5133 * The open entry point is called when a network interface is made
5134 * active by the system (IFF_UP). At this point all resources needed
5135 * for transmit and receive operations are allocated, the interrupt
5136 * handler is registered with the OS, the watchdog timer is started,
5137 * and the stack is notified that the interface is ready.
5138 **/
5139 static int ixgbe_open(struct net_device *netdev)
5140 {
5141 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5142 int err;
5143
5144 /* disallow open during test */
5145 if (test_bit(__IXGBE_TESTING, &adapter->state))
5146 return -EBUSY;
5147
5148 netif_carrier_off(netdev);
5149
5150 /* allocate transmit descriptors */
5151 err = ixgbe_setup_all_tx_resources(adapter);
5152 if (err)
5153 goto err_setup_tx;
5154
5155 /* allocate receive descriptors */
5156 err = ixgbe_setup_all_rx_resources(adapter);
5157 if (err)
5158 goto err_setup_rx;
5159
5160 ixgbe_configure(adapter);
5161
5162 err = ixgbe_request_irq(adapter);
5163 if (err)
5164 goto err_req_irq;
5165
5166 /* Notify the stack of the actual queue counts. */
5167 err = netif_set_real_num_tx_queues(netdev,
5168 adapter->num_rx_pools > 1 ? 1 :
5169 adapter->num_tx_queues);
5170 if (err)
5171 goto err_set_queues;
5172
5173
5174 err = netif_set_real_num_rx_queues(netdev,
5175 adapter->num_rx_pools > 1 ? 1 :
5176 adapter->num_rx_queues);
5177 if (err)
5178 goto err_set_queues;
5179
5180 ixgbe_ptp_init(adapter);
5181
5182 ixgbe_up_complete(adapter);
5183
5184 return 0;
5185
5186 err_set_queues:
5187 ixgbe_free_irq(adapter);
5188 err_req_irq:
5189 ixgbe_free_all_rx_resources(adapter);
5190 err_setup_rx:
5191 ixgbe_free_all_tx_resources(adapter);
5192 err_setup_tx:
5193 ixgbe_reset(adapter);
5194
5195 return err;
5196 }
5197
5198 /**
5199 * ixgbe_close - Disables a network interface
5200 * @netdev: network interface device structure
5201 *
5202 * Returns 0, this is not allowed to fail
5203 *
5204 * The close entry point is called when an interface is de-activated
5205 * by the OS. The hardware is still under the drivers control, but
5206 * needs to be disabled. A global MAC reset is issued to stop the
5207 * hardware, and all transmit and receive resources are freed.
5208 **/
5209 static int ixgbe_close(struct net_device *netdev)
5210 {
5211 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5212
5213 ixgbe_ptp_stop(adapter);
5214
5215 ixgbe_down(adapter);
5216 ixgbe_free_irq(adapter);
5217
5218 ixgbe_fdir_filter_exit(adapter);
5219
5220 ixgbe_free_all_tx_resources(adapter);
5221 ixgbe_free_all_rx_resources(adapter);
5222
5223 ixgbe_release_hw_control(adapter);
5224
5225 return 0;
5226 }
5227
5228 #ifdef CONFIG_PM
5229 static int ixgbe_resume(struct pci_dev *pdev)
5230 {
5231 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5232 struct net_device *netdev = adapter->netdev;
5233 u32 err;
5234
5235 pci_set_power_state(pdev, PCI_D0);
5236 pci_restore_state(pdev);
5237 /*
5238 * pci_restore_state clears dev->state_saved so call
5239 * pci_save_state to restore it.
5240 */
5241 pci_save_state(pdev);
5242
5243 err = pci_enable_device_mem(pdev);
5244 if (err) {
5245 e_dev_err("Cannot enable PCI device from suspend\n");
5246 return err;
5247 }
5248 pci_set_master(pdev);
5249
5250 pci_wake_from_d3(pdev, false);
5251
5252 ixgbe_reset(adapter);
5253
5254 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5255
5256 rtnl_lock();
5257 err = ixgbe_init_interrupt_scheme(adapter);
5258 if (!err && netif_running(netdev))
5259 err = ixgbe_open(netdev);
5260
5261 rtnl_unlock();
5262
5263 if (err)
5264 return err;
5265
5266 netif_device_attach(netdev);
5267
5268 return 0;
5269 }
5270 #endif /* CONFIG_PM */
5271
5272 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5273 {
5274 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5275 struct net_device *netdev = adapter->netdev;
5276 struct ixgbe_hw *hw = &adapter->hw;
5277 u32 ctrl, fctrl;
5278 u32 wufc = adapter->wol;
5279 #ifdef CONFIG_PM
5280 int retval = 0;
5281 #endif
5282
5283 netif_device_detach(netdev);
5284
5285 rtnl_lock();
5286 if (netif_running(netdev)) {
5287 ixgbe_down(adapter);
5288 ixgbe_free_irq(adapter);
5289 ixgbe_free_all_tx_resources(adapter);
5290 ixgbe_free_all_rx_resources(adapter);
5291 }
5292 rtnl_unlock();
5293
5294 ixgbe_clear_interrupt_scheme(adapter);
5295
5296 #ifdef CONFIG_PM
5297 retval = pci_save_state(pdev);
5298 if (retval)
5299 return retval;
5300
5301 #endif
5302 if (hw->mac.ops.stop_link_on_d3)
5303 hw->mac.ops.stop_link_on_d3(hw);
5304
5305 if (wufc) {
5306 ixgbe_set_rx_mode(netdev);
5307
5308 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5309 if (hw->mac.ops.enable_tx_laser)
5310 hw->mac.ops.enable_tx_laser(hw);
5311
5312 /* turn on all-multi mode if wake on multicast is enabled */
5313 if (wufc & IXGBE_WUFC_MC) {
5314 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5315 fctrl |= IXGBE_FCTRL_MPE;
5316 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5317 }
5318
5319 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5320 ctrl |= IXGBE_CTRL_GIO_DIS;
5321 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5322
5323 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5324 } else {
5325 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5326 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5327 }
5328
5329 switch (hw->mac.type) {
5330 case ixgbe_mac_82598EB:
5331 pci_wake_from_d3(pdev, false);
5332 break;
5333 case ixgbe_mac_82599EB:
5334 case ixgbe_mac_X540:
5335 pci_wake_from_d3(pdev, !!wufc);
5336 break;
5337 default:
5338 break;
5339 }
5340
5341 *enable_wake = !!wufc;
5342
5343 ixgbe_release_hw_control(adapter);
5344
5345 pci_disable_device(pdev);
5346
5347 return 0;
5348 }
5349
5350 #ifdef CONFIG_PM
5351 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5352 {
5353 int retval;
5354 bool wake;
5355
5356 retval = __ixgbe_shutdown(pdev, &wake);
5357 if (retval)
5358 return retval;
5359
5360 if (wake) {
5361 pci_prepare_to_sleep(pdev);
5362 } else {
5363 pci_wake_from_d3(pdev, false);
5364 pci_set_power_state(pdev, PCI_D3hot);
5365 }
5366
5367 return 0;
5368 }
5369 #endif /* CONFIG_PM */
5370
5371 static void ixgbe_shutdown(struct pci_dev *pdev)
5372 {
5373 bool wake;
5374
5375 __ixgbe_shutdown(pdev, &wake);
5376
5377 if (system_state == SYSTEM_POWER_OFF) {
5378 pci_wake_from_d3(pdev, wake);
5379 pci_set_power_state(pdev, PCI_D3hot);
5380 }
5381 }
5382
5383 /**
5384 * ixgbe_update_stats - Update the board statistics counters.
5385 * @adapter: board private structure
5386 **/
5387 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5388 {
5389 struct net_device *netdev = adapter->netdev;
5390 struct ixgbe_hw *hw = &adapter->hw;
5391 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5392 u64 total_mpc = 0;
5393 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5394 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5395 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5396 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5397
5398 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5399 test_bit(__IXGBE_RESETTING, &adapter->state))
5400 return;
5401
5402 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5403 u64 rsc_count = 0;
5404 u64 rsc_flush = 0;
5405 for (i = 0; i < adapter->num_rx_queues; i++) {
5406 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5407 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5408 }
5409 adapter->rsc_total_count = rsc_count;
5410 adapter->rsc_total_flush = rsc_flush;
5411 }
5412
5413 for (i = 0; i < adapter->num_rx_queues; i++) {
5414 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5415 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5416 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5417 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5418 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5419 bytes += rx_ring->stats.bytes;
5420 packets += rx_ring->stats.packets;
5421 }
5422 adapter->non_eop_descs = non_eop_descs;
5423 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5424 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5425 adapter->hw_csum_rx_error = hw_csum_rx_error;
5426 netdev->stats.rx_bytes = bytes;
5427 netdev->stats.rx_packets = packets;
5428
5429 bytes = 0;
5430 packets = 0;
5431 /* gather some stats to the adapter struct that are per queue */
5432 for (i = 0; i < adapter->num_tx_queues; i++) {
5433 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5434 restart_queue += tx_ring->tx_stats.restart_queue;
5435 tx_busy += tx_ring->tx_stats.tx_busy;
5436 bytes += tx_ring->stats.bytes;
5437 packets += tx_ring->stats.packets;
5438 }
5439 adapter->restart_queue = restart_queue;
5440 adapter->tx_busy = tx_busy;
5441 netdev->stats.tx_bytes = bytes;
5442 netdev->stats.tx_packets = packets;
5443
5444 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5445
5446 /* 8 register reads */
5447 for (i = 0; i < 8; i++) {
5448 /* for packet buffers not used, the register should read 0 */
5449 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5450 missed_rx += mpc;
5451 hwstats->mpc[i] += mpc;
5452 total_mpc += hwstats->mpc[i];
5453 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5454 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5455 switch (hw->mac.type) {
5456 case ixgbe_mac_82598EB:
5457 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5458 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5459 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5460 hwstats->pxonrxc[i] +=
5461 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5462 break;
5463 case ixgbe_mac_82599EB:
5464 case ixgbe_mac_X540:
5465 hwstats->pxonrxc[i] +=
5466 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5467 break;
5468 default:
5469 break;
5470 }
5471 }
5472
5473 /*16 register reads */
5474 for (i = 0; i < 16; i++) {
5475 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5476 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5477 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5478 (hw->mac.type == ixgbe_mac_X540)) {
5479 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5480 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5481 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5482 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5483 }
5484 }
5485
5486 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5487 /* work around hardware counting issue */
5488 hwstats->gprc -= missed_rx;
5489
5490 ixgbe_update_xoff_received(adapter);
5491
5492 /* 82598 hardware only has a 32 bit counter in the high register */
5493 switch (hw->mac.type) {
5494 case ixgbe_mac_82598EB:
5495 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5496 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5497 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5498 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5499 break;
5500 case ixgbe_mac_X540:
5501 /* OS2BMC stats are X540 only*/
5502 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5503 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5504 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5505 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5506 case ixgbe_mac_82599EB:
5507 for (i = 0; i < 16; i++)
5508 adapter->hw_rx_no_dma_resources +=
5509 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5510 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5511 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5512 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5513 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5514 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5515 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5516 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5517 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5518 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5519 #ifdef IXGBE_FCOE
5520 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5521 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5522 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5523 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5524 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5525 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5526 /* Add up per cpu counters for total ddp aloc fail */
5527 if (adapter->fcoe.ddp_pool) {
5528 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5529 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5530 unsigned int cpu;
5531 u64 noddp = 0, noddp_ext_buff = 0;
5532 for_each_possible_cpu(cpu) {
5533 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5534 noddp += ddp_pool->noddp;
5535 noddp_ext_buff += ddp_pool->noddp_ext_buff;
5536 }
5537 hwstats->fcoe_noddp = noddp;
5538 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
5539 }
5540 #endif /* IXGBE_FCOE */
5541 break;
5542 default:
5543 break;
5544 }
5545 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5546 hwstats->bprc += bprc;
5547 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5548 if (hw->mac.type == ixgbe_mac_82598EB)
5549 hwstats->mprc -= bprc;
5550 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5551 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5552 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5553 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5554 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5555 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5556 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5557 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5558 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5559 hwstats->lxontxc += lxon;
5560 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5561 hwstats->lxofftxc += lxoff;
5562 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5563 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5564 /*
5565 * 82598 errata - tx of flow control packets is included in tx counters
5566 */
5567 xon_off_tot = lxon + lxoff;
5568 hwstats->gptc -= xon_off_tot;
5569 hwstats->mptc -= xon_off_tot;
5570 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5571 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5572 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5573 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5574 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5575 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5576 hwstats->ptc64 -= xon_off_tot;
5577 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5578 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5579 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5580 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5581 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5582 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5583
5584 /* Fill out the OS statistics structure */
5585 netdev->stats.multicast = hwstats->mprc;
5586
5587 /* Rx Errors */
5588 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5589 netdev->stats.rx_dropped = 0;
5590 netdev->stats.rx_length_errors = hwstats->rlec;
5591 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5592 netdev->stats.rx_missed_errors = total_mpc;
5593 }
5594
5595 /**
5596 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5597 * @adapter: pointer to the device adapter structure
5598 **/
5599 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5600 {
5601 struct ixgbe_hw *hw = &adapter->hw;
5602 int i;
5603
5604 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5605 return;
5606
5607 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5608
5609 /* if interface is down do nothing */
5610 if (test_bit(__IXGBE_DOWN, &adapter->state))
5611 return;
5612
5613 /* do nothing if we are not using signature filters */
5614 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5615 return;
5616
5617 adapter->fdir_overflow++;
5618
5619 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5620 for (i = 0; i < adapter->num_tx_queues; i++)
5621 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5622 &(adapter->tx_ring[i]->state));
5623 /* re-enable flow director interrupts */
5624 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5625 } else {
5626 e_err(probe, "failed to finish FDIR re-initialization, "
5627 "ignored adding FDIR ATR filters\n");
5628 }
5629 }
5630
5631 /**
5632 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5633 * @adapter: pointer to the device adapter structure
5634 *
5635 * This function serves two purposes. First it strobes the interrupt lines
5636 * in order to make certain interrupts are occurring. Secondly it sets the
5637 * bits needed to check for TX hangs. As a result we should immediately
5638 * determine if a hang has occurred.
5639 */
5640 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5641 {
5642 struct ixgbe_hw *hw = &adapter->hw;
5643 u64 eics = 0;
5644 int i;
5645
5646 /* If we're down or resetting, just bail */
5647 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5648 test_bit(__IXGBE_RESETTING, &adapter->state))
5649 return;
5650
5651 /* Force detection of hung controller */
5652 if (netif_carrier_ok(adapter->netdev)) {
5653 for (i = 0; i < adapter->num_tx_queues; i++)
5654 set_check_for_tx_hang(adapter->tx_ring[i]);
5655 }
5656
5657 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5658 /*
5659 * for legacy and MSI interrupts don't set any bits
5660 * that are enabled for EIAM, because this operation
5661 * would set *both* EIMS and EICS for any bit in EIAM
5662 */
5663 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5664 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5665 } else {
5666 /* get one bit for every active tx/rx interrupt vector */
5667 for (i = 0; i < adapter->num_q_vectors; i++) {
5668 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5669 if (qv->rx.ring || qv->tx.ring)
5670 eics |= ((u64)1 << i);
5671 }
5672 }
5673
5674 /* Cause software interrupt to ensure rings are cleaned */
5675 ixgbe_irq_rearm_queues(adapter, eics);
5676
5677 }
5678
5679 /**
5680 * ixgbe_watchdog_update_link - update the link status
5681 * @adapter: pointer to the device adapter structure
5682 * @link_speed: pointer to a u32 to store the link_speed
5683 **/
5684 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5685 {
5686 struct ixgbe_hw *hw = &adapter->hw;
5687 u32 link_speed = adapter->link_speed;
5688 bool link_up = adapter->link_up;
5689 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
5690
5691 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5692 return;
5693
5694 if (hw->mac.ops.check_link) {
5695 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5696 } else {
5697 /* always assume link is up, if no check link function */
5698 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5699 link_up = true;
5700 }
5701
5702 if (adapter->ixgbe_ieee_pfc)
5703 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5704
5705 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
5706 hw->mac.ops.fc_enable(hw);
5707 ixgbe_set_rx_drop_en(adapter);
5708 }
5709
5710 if (link_up ||
5711 time_after(jiffies, (adapter->link_check_timeout +
5712 IXGBE_TRY_LINK_TIMEOUT))) {
5713 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5714 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5715 IXGBE_WRITE_FLUSH(hw);
5716 }
5717
5718 adapter->link_up = link_up;
5719 adapter->link_speed = link_speed;
5720 }
5721
5722 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5723 {
5724 #ifdef CONFIG_IXGBE_DCB
5725 struct net_device *netdev = adapter->netdev;
5726 struct dcb_app app = {
5727 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5728 .protocol = 0,
5729 };
5730 u8 up = 0;
5731
5732 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5733 up = dcb_ieee_getapp_mask(netdev, &app);
5734
5735 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5736 #endif
5737 }
5738
5739 /**
5740 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5741 * print link up message
5742 * @adapter: pointer to the device adapter structure
5743 **/
5744 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5745 {
5746 struct net_device *netdev = adapter->netdev;
5747 struct ixgbe_hw *hw = &adapter->hw;
5748 u32 link_speed = adapter->link_speed;
5749 bool flow_rx, flow_tx;
5750
5751 /* only continue if link was previously down */
5752 if (netif_carrier_ok(netdev))
5753 return;
5754
5755 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5756
5757 switch (hw->mac.type) {
5758 case ixgbe_mac_82598EB: {
5759 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5760 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5761 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5762 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5763 }
5764 break;
5765 case ixgbe_mac_X540:
5766 case ixgbe_mac_82599EB: {
5767 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5768 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5769 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5770 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5771 }
5772 break;
5773 default:
5774 flow_tx = false;
5775 flow_rx = false;
5776 break;
5777 }
5778
5779 adapter->last_rx_ptp_check = jiffies;
5780
5781 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
5782 ixgbe_ptp_start_cyclecounter(adapter);
5783
5784 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5785 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5786 "10 Gbps" :
5787 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5788 "1 Gbps" :
5789 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5790 "100 Mbps" :
5791 "unknown speed"))),
5792 ((flow_rx && flow_tx) ? "RX/TX" :
5793 (flow_rx ? "RX" :
5794 (flow_tx ? "TX" : "None"))));
5795
5796 netif_carrier_on(netdev);
5797 ixgbe_check_vf_rate_limit(adapter);
5798
5799 /* update the default user priority for VFs */
5800 ixgbe_update_default_up(adapter);
5801
5802 /* ping all the active vfs to let them know link has changed */
5803 ixgbe_ping_all_vfs(adapter);
5804 }
5805
5806 /**
5807 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5808 * print link down message
5809 * @adapter: pointer to the adapter structure
5810 **/
5811 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5812 {
5813 struct net_device *netdev = adapter->netdev;
5814 struct ixgbe_hw *hw = &adapter->hw;
5815
5816 adapter->link_up = false;
5817 adapter->link_speed = 0;
5818
5819 /* only continue if link was up previously */
5820 if (!netif_carrier_ok(netdev))
5821 return;
5822
5823 /* poll for SFP+ cable when link is down */
5824 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5825 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5826
5827 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
5828 ixgbe_ptp_start_cyclecounter(adapter);
5829
5830 e_info(drv, "NIC Link is Down\n");
5831 netif_carrier_off(netdev);
5832
5833 /* ping all the active vfs to let them know link has changed */
5834 ixgbe_ping_all_vfs(adapter);
5835 }
5836
5837 /**
5838 * ixgbe_watchdog_flush_tx - flush queues on link down
5839 * @adapter: pointer to the device adapter structure
5840 **/
5841 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5842 {
5843 int i;
5844 int some_tx_pending = 0;
5845
5846 if (!netif_carrier_ok(adapter->netdev)) {
5847 for (i = 0; i < adapter->num_tx_queues; i++) {
5848 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5849 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5850 some_tx_pending = 1;
5851 break;
5852 }
5853 }
5854
5855 if (some_tx_pending) {
5856 /* We've lost link, so the controller stops DMA,
5857 * but we've got queued Tx work that's never going
5858 * to get done, so reset controller to flush Tx.
5859 * (Do the reset outside of interrupt context).
5860 */
5861 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
5862 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5863 }
5864 }
5865 }
5866
5867 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5868 {
5869 u32 ssvpc;
5870
5871 /* Do not perform spoof check for 82598 or if not in IOV mode */
5872 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5873 adapter->num_vfs == 0)
5874 return;
5875
5876 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5877
5878 /*
5879 * ssvpc register is cleared on read, if zero then no
5880 * spoofed packets in the last interval.
5881 */
5882 if (!ssvpc)
5883 return;
5884
5885 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
5886 }
5887
5888 /**
5889 * ixgbe_watchdog_subtask - check and bring link up
5890 * @adapter: pointer to the device adapter structure
5891 **/
5892 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5893 {
5894 /* if interface is down do nothing */
5895 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5896 test_bit(__IXGBE_RESETTING, &adapter->state))
5897 return;
5898
5899 ixgbe_watchdog_update_link(adapter);
5900
5901 if (adapter->link_up)
5902 ixgbe_watchdog_link_is_up(adapter);
5903 else
5904 ixgbe_watchdog_link_is_down(adapter);
5905
5906 ixgbe_spoof_check(adapter);
5907 ixgbe_update_stats(adapter);
5908
5909 ixgbe_watchdog_flush_tx(adapter);
5910 }
5911
5912 /**
5913 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5914 * @adapter: the ixgbe adapter structure
5915 **/
5916 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5917 {
5918 struct ixgbe_hw *hw = &adapter->hw;
5919 s32 err;
5920
5921 /* not searching for SFP so there is nothing to do here */
5922 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5923 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5924 return;
5925
5926 /* someone else is in init, wait until next service event */
5927 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5928 return;
5929
5930 err = hw->phy.ops.identify_sfp(hw);
5931 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5932 goto sfp_out;
5933
5934 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5935 /* If no cable is present, then we need to reset
5936 * the next time we find a good cable. */
5937 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5938 }
5939
5940 /* exit on error */
5941 if (err)
5942 goto sfp_out;
5943
5944 /* exit if reset not needed */
5945 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5946 goto sfp_out;
5947
5948 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5949
5950 /*
5951 * A module may be identified correctly, but the EEPROM may not have
5952 * support for that module. setup_sfp() will fail in that case, so
5953 * we should not allow that module to load.
5954 */
5955 if (hw->mac.type == ixgbe_mac_82598EB)
5956 err = hw->phy.ops.reset(hw);
5957 else
5958 err = hw->mac.ops.setup_sfp(hw);
5959
5960 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5961 goto sfp_out;
5962
5963 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5964 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5965
5966 sfp_out:
5967 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5968
5969 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5970 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5971 e_dev_err("failed to initialize because an unsupported "
5972 "SFP+ module type was detected.\n");
5973 e_dev_err("Reload the driver after installing a "
5974 "supported module.\n");
5975 unregister_netdev(adapter->netdev);
5976 }
5977 }
5978
5979 /**
5980 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5981 * @adapter: the ixgbe adapter structure
5982 **/
5983 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5984 {
5985 struct ixgbe_hw *hw = &adapter->hw;
5986 u32 speed;
5987 bool autoneg = false;
5988
5989 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5990 return;
5991
5992 /* someone else is in init, wait until next service event */
5993 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5994 return;
5995
5996 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5997
5998 speed = hw->phy.autoneg_advertised;
5999 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
6000 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
6001
6002 /* setup the highest link when no autoneg */
6003 if (!autoneg) {
6004 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6005 speed = IXGBE_LINK_SPEED_10GB_FULL;
6006 }
6007 }
6008
6009 if (hw->mac.ops.setup_link)
6010 hw->mac.ops.setup_link(hw, speed, true);
6011
6012 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6013 adapter->link_check_timeout = jiffies;
6014 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6015 }
6016
6017 #ifdef CONFIG_PCI_IOV
6018 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6019 {
6020 int vf;
6021 struct ixgbe_hw *hw = &adapter->hw;
6022 struct net_device *netdev = adapter->netdev;
6023 u32 gpc;
6024 u32 ciaa, ciad;
6025
6026 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6027 if (gpc) /* If incrementing then no need for the check below */
6028 return;
6029 /*
6030 * Check to see if a bad DMA write target from an errant or
6031 * malicious VF has caused a PCIe error. If so then we can
6032 * issue a VFLR to the offending VF(s) and then resume without
6033 * requesting a full slot reset.
6034 */
6035
6036 for (vf = 0; vf < adapter->num_vfs; vf++) {
6037 ciaa = (vf << 16) | 0x80000000;
6038 /* 32 bit read so align, we really want status at offset 6 */
6039 ciaa |= PCI_COMMAND;
6040 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6041 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6042 ciaa &= 0x7FFFFFFF;
6043 /* disable debug mode asap after reading data */
6044 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6045 /* Get the upper 16 bits which will be the PCI status reg */
6046 ciad >>= 16;
6047 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6048 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6049 /* Issue VFLR */
6050 ciaa = (vf << 16) | 0x80000000;
6051 ciaa |= 0xA8;
6052 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6053 ciad = 0x00008000; /* VFLR */
6054 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6055 ciaa &= 0x7FFFFFFF;
6056 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6057 }
6058 }
6059 }
6060
6061 #endif
6062 /**
6063 * ixgbe_service_timer - Timer Call-back
6064 * @data: pointer to adapter cast into an unsigned long
6065 **/
6066 static void ixgbe_service_timer(unsigned long data)
6067 {
6068 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6069 unsigned long next_event_offset;
6070 bool ready = true;
6071
6072 /* poll faster when waiting for link */
6073 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6074 next_event_offset = HZ / 10;
6075 else
6076 next_event_offset = HZ * 2;
6077
6078 #ifdef CONFIG_PCI_IOV
6079 /*
6080 * don't bother with SR-IOV VF DMA hang check if there are
6081 * no VFs or the link is down
6082 */
6083 if (!adapter->num_vfs ||
6084 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6085 goto normal_timer_service;
6086
6087 /* If we have VFs allocated then we must check for DMA hangs */
6088 ixgbe_check_for_bad_vf(adapter);
6089 next_event_offset = HZ / 50;
6090 adapter->timer_event_accumulator++;
6091
6092 if (adapter->timer_event_accumulator >= 100)
6093 adapter->timer_event_accumulator = 0;
6094 else
6095 ready = false;
6096
6097 normal_timer_service:
6098 #endif
6099 /* Reset the timer */
6100 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6101
6102 if (ready)
6103 ixgbe_service_event_schedule(adapter);
6104 }
6105
6106 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6107 {
6108 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6109 return;
6110
6111 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6112
6113 /* If we're already down or resetting, just bail */
6114 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6115 test_bit(__IXGBE_RESETTING, &adapter->state))
6116 return;
6117
6118 ixgbe_dump(adapter);
6119 netdev_err(adapter->netdev, "Reset adapter\n");
6120 adapter->tx_timeout_count++;
6121
6122 ixgbe_reinit_locked(adapter);
6123 }
6124
6125 /**
6126 * ixgbe_service_task - manages and runs subtasks
6127 * @work: pointer to work_struct containing our data
6128 **/
6129 static void ixgbe_service_task(struct work_struct *work)
6130 {
6131 struct ixgbe_adapter *adapter = container_of(work,
6132 struct ixgbe_adapter,
6133 service_task);
6134 ixgbe_reset_subtask(adapter);
6135 ixgbe_sfp_detection_subtask(adapter);
6136 ixgbe_sfp_link_config_subtask(adapter);
6137 ixgbe_check_overtemp_subtask(adapter);
6138 ixgbe_watchdog_subtask(adapter);
6139 ixgbe_fdir_reinit_subtask(adapter);
6140 ixgbe_check_hang_subtask(adapter);
6141
6142 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
6143 ixgbe_ptp_overflow_check(adapter);
6144 ixgbe_ptp_rx_hang(adapter);
6145 }
6146
6147 ixgbe_service_event_complete(adapter);
6148 }
6149
6150 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6151 struct ixgbe_tx_buffer *first,
6152 u8 *hdr_len)
6153 {
6154 struct sk_buff *skb = first->skb;
6155 u32 vlan_macip_lens, type_tucmd;
6156 u32 mss_l4len_idx, l4len;
6157
6158 if (skb->ip_summed != CHECKSUM_PARTIAL)
6159 return 0;
6160
6161 if (!skb_is_gso(skb))
6162 return 0;
6163
6164 if (skb_header_cloned(skb)) {
6165 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6166 if (err)
6167 return err;
6168 }
6169
6170 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6171 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6172
6173 if (first->protocol == __constant_htons(ETH_P_IP)) {
6174 struct iphdr *iph = ip_hdr(skb);
6175 iph->tot_len = 0;
6176 iph->check = 0;
6177 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6178 iph->daddr, 0,
6179 IPPROTO_TCP,
6180 0);
6181 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6182 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6183 IXGBE_TX_FLAGS_CSUM |
6184 IXGBE_TX_FLAGS_IPV4;
6185 } else if (skb_is_gso_v6(skb)) {
6186 ipv6_hdr(skb)->payload_len = 0;
6187 tcp_hdr(skb)->check =
6188 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6189 &ipv6_hdr(skb)->daddr,
6190 0, IPPROTO_TCP, 0);
6191 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6192 IXGBE_TX_FLAGS_CSUM;
6193 }
6194
6195 /* compute header lengths */
6196 l4len = tcp_hdrlen(skb);
6197 *hdr_len = skb_transport_offset(skb) + l4len;
6198
6199 /* update gso size and bytecount with header size */
6200 first->gso_segs = skb_shinfo(skb)->gso_segs;
6201 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6202
6203 /* mss_l4len_id: use 0 as index for TSO */
6204 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6205 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6206
6207 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6208 vlan_macip_lens = skb_network_header_len(skb);
6209 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6210 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6211
6212 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6213 mss_l4len_idx);
6214
6215 return 1;
6216 }
6217
6218 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6219 struct ixgbe_tx_buffer *first)
6220 {
6221 struct sk_buff *skb = first->skb;
6222 u32 vlan_macip_lens = 0;
6223 u32 mss_l4len_idx = 0;
6224 u32 type_tucmd = 0;
6225
6226 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6227 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6228 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6229 return;
6230 } else {
6231 u8 l4_hdr = 0;
6232 switch (first->protocol) {
6233 case __constant_htons(ETH_P_IP):
6234 vlan_macip_lens |= skb_network_header_len(skb);
6235 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6236 l4_hdr = ip_hdr(skb)->protocol;
6237 break;
6238 case __constant_htons(ETH_P_IPV6):
6239 vlan_macip_lens |= skb_network_header_len(skb);
6240 l4_hdr = ipv6_hdr(skb)->nexthdr;
6241 break;
6242 default:
6243 if (unlikely(net_ratelimit())) {
6244 dev_warn(tx_ring->dev,
6245 "partial checksum but proto=%x!\n",
6246 first->protocol);
6247 }
6248 break;
6249 }
6250
6251 switch (l4_hdr) {
6252 case IPPROTO_TCP:
6253 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6254 mss_l4len_idx = tcp_hdrlen(skb) <<
6255 IXGBE_ADVTXD_L4LEN_SHIFT;
6256 break;
6257 case IPPROTO_SCTP:
6258 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6259 mss_l4len_idx = sizeof(struct sctphdr) <<
6260 IXGBE_ADVTXD_L4LEN_SHIFT;
6261 break;
6262 case IPPROTO_UDP:
6263 mss_l4len_idx = sizeof(struct udphdr) <<
6264 IXGBE_ADVTXD_L4LEN_SHIFT;
6265 break;
6266 default:
6267 if (unlikely(net_ratelimit())) {
6268 dev_warn(tx_ring->dev,
6269 "partial checksum but l4 proto=%x!\n",
6270 l4_hdr);
6271 }
6272 break;
6273 }
6274
6275 /* update TX checksum flag */
6276 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
6277 }
6278
6279 /* vlan_macip_lens: MACLEN, VLAN tag */
6280 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6281 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6282
6283 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6284 type_tucmd, mss_l4len_idx);
6285 }
6286
6287 #define IXGBE_SET_FLAG(_input, _flag, _result) \
6288 ((_flag <= _result) ? \
6289 ((u32)(_input & _flag) * (_result / _flag)) : \
6290 ((u32)(_input & _flag) / (_flag / _result)))
6291
6292 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6293 {
6294 /* set type for advanced descriptor with frame checksum insertion */
6295 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6296 IXGBE_ADVTXD_DCMD_DEXT |
6297 IXGBE_ADVTXD_DCMD_IFCS;
6298
6299 /* set HW vlan bit if vlan is present */
6300 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6301 IXGBE_ADVTXD_DCMD_VLE);
6302
6303 /* set segmentation enable bits for TSO/FSO */
6304 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6305 IXGBE_ADVTXD_DCMD_TSE);
6306
6307 /* set timestamp bit if present */
6308 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6309 IXGBE_ADVTXD_MAC_TSTAMP);
6310
6311 /* insert frame checksum */
6312 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
6313
6314 return cmd_type;
6315 }
6316
6317 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6318 u32 tx_flags, unsigned int paylen)
6319 {
6320 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
6321
6322 /* enable L4 checksum for TSO and TX checksum offload */
6323 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6324 IXGBE_TX_FLAGS_CSUM,
6325 IXGBE_ADVTXD_POPTS_TXSM);
6326
6327 /* enble IPv4 checksum for TSO */
6328 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6329 IXGBE_TX_FLAGS_IPV4,
6330 IXGBE_ADVTXD_POPTS_IXSM);
6331
6332 /*
6333 * Check Context must be set if Tx switch is enabled, which it
6334 * always is for case where virtual functions are running
6335 */
6336 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6337 IXGBE_TX_FLAGS_CC,
6338 IXGBE_ADVTXD_CC);
6339
6340 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6341 }
6342
6343 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6344 IXGBE_TXD_CMD_RS)
6345
6346 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6347 struct ixgbe_tx_buffer *first,
6348 const u8 hdr_len)
6349 {
6350 struct sk_buff *skb = first->skb;
6351 struct ixgbe_tx_buffer *tx_buffer;
6352 union ixgbe_adv_tx_desc *tx_desc;
6353 struct skb_frag_struct *frag;
6354 dma_addr_t dma;
6355 unsigned int data_len, size;
6356 u32 tx_flags = first->tx_flags;
6357 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
6358 u16 i = tx_ring->next_to_use;
6359
6360 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6361
6362 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6363
6364 size = skb_headlen(skb);
6365 data_len = skb->data_len;
6366
6367 #ifdef IXGBE_FCOE
6368 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6369 if (data_len < sizeof(struct fcoe_crc_eof)) {
6370 size -= sizeof(struct fcoe_crc_eof) - data_len;
6371 data_len = 0;
6372 } else {
6373 data_len -= sizeof(struct fcoe_crc_eof);
6374 }
6375 }
6376
6377 #endif
6378 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6379
6380 tx_buffer = first;
6381
6382 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6383 if (dma_mapping_error(tx_ring->dev, dma))
6384 goto dma_error;
6385
6386 /* record length, and DMA address */
6387 dma_unmap_len_set(tx_buffer, len, size);
6388 dma_unmap_addr_set(tx_buffer, dma, dma);
6389
6390 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6391
6392 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6393 tx_desc->read.cmd_type_len =
6394 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
6395
6396 i++;
6397 tx_desc++;
6398 if (i == tx_ring->count) {
6399 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6400 i = 0;
6401 }
6402 tx_desc->read.olinfo_status = 0;
6403
6404 dma += IXGBE_MAX_DATA_PER_TXD;
6405 size -= IXGBE_MAX_DATA_PER_TXD;
6406
6407 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6408 }
6409
6410 if (likely(!data_len))
6411 break;
6412
6413 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6414
6415 i++;
6416 tx_desc++;
6417 if (i == tx_ring->count) {
6418 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6419 i = 0;
6420 }
6421 tx_desc->read.olinfo_status = 0;
6422
6423 #ifdef IXGBE_FCOE
6424 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6425 #else
6426 size = skb_frag_size(frag);
6427 #endif
6428 data_len -= size;
6429
6430 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6431 DMA_TO_DEVICE);
6432
6433 tx_buffer = &tx_ring->tx_buffer_info[i];
6434 }
6435
6436 /* write last descriptor with RS and EOP bits */
6437 cmd_type |= size | IXGBE_TXD_CMD;
6438 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6439
6440 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6441
6442 /* set the timestamp */
6443 first->time_stamp = jiffies;
6444
6445 /*
6446 * Force memory writes to complete before letting h/w know there
6447 * are new descriptors to fetch. (Only applicable for weak-ordered
6448 * memory model archs, such as IA-64).
6449 *
6450 * We also need this memory barrier to make certain all of the
6451 * status bits have been updated before next_to_watch is written.
6452 */
6453 wmb();
6454
6455 /* set next_to_watch value indicating a packet is present */
6456 first->next_to_watch = tx_desc;
6457
6458 i++;
6459 if (i == tx_ring->count)
6460 i = 0;
6461
6462 tx_ring->next_to_use = i;
6463
6464 /* notify HW of packet */
6465 writel(i, tx_ring->tail);
6466
6467 return;
6468 dma_error:
6469 dev_err(tx_ring->dev, "TX DMA map failed\n");
6470
6471 /* clear dma mappings for failed tx_buffer_info map */
6472 for (;;) {
6473 tx_buffer = &tx_ring->tx_buffer_info[i];
6474 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6475 if (tx_buffer == first)
6476 break;
6477 if (i == 0)
6478 i = tx_ring->count;
6479 i--;
6480 }
6481
6482 tx_ring->next_to_use = i;
6483 }
6484
6485 static void ixgbe_atr(struct ixgbe_ring *ring,
6486 struct ixgbe_tx_buffer *first)
6487 {
6488 struct ixgbe_q_vector *q_vector = ring->q_vector;
6489 union ixgbe_atr_hash_dword input = { .dword = 0 };
6490 union ixgbe_atr_hash_dword common = { .dword = 0 };
6491 union {
6492 unsigned char *network;
6493 struct iphdr *ipv4;
6494 struct ipv6hdr *ipv6;
6495 } hdr;
6496 struct tcphdr *th;
6497 __be16 vlan_id;
6498
6499 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6500 if (!q_vector)
6501 return;
6502
6503 /* do nothing if sampling is disabled */
6504 if (!ring->atr_sample_rate)
6505 return;
6506
6507 ring->atr_count++;
6508
6509 /* snag network header to get L4 type and address */
6510 hdr.network = skb_network_header(first->skb);
6511
6512 /* Currently only IPv4/IPv6 with TCP is supported */
6513 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6514 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6515 (first->protocol != __constant_htons(ETH_P_IP) ||
6516 hdr.ipv4->protocol != IPPROTO_TCP))
6517 return;
6518
6519 th = tcp_hdr(first->skb);
6520
6521 /* skip this packet since it is invalid or the socket is closing */
6522 if (!th || th->fin)
6523 return;
6524
6525 /* sample on all syn packets or once every atr sample count */
6526 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6527 return;
6528
6529 /* reset sample count */
6530 ring->atr_count = 0;
6531
6532 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6533
6534 /*
6535 * src and dst are inverted, think how the receiver sees them
6536 *
6537 * The input is broken into two sections, a non-compressed section
6538 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6539 * is XORed together and stored in the compressed dword.
6540 */
6541 input.formatted.vlan_id = vlan_id;
6542
6543 /*
6544 * since src port and flex bytes occupy the same word XOR them together
6545 * and write the value to source port portion of compressed dword
6546 */
6547 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6548 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6549 else
6550 common.port.src ^= th->dest ^ first->protocol;
6551 common.port.dst ^= th->source;
6552
6553 if (first->protocol == __constant_htons(ETH_P_IP)) {
6554 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6555 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6556 } else {
6557 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6558 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6559 hdr.ipv6->saddr.s6_addr32[1] ^
6560 hdr.ipv6->saddr.s6_addr32[2] ^
6561 hdr.ipv6->saddr.s6_addr32[3] ^
6562 hdr.ipv6->daddr.s6_addr32[0] ^
6563 hdr.ipv6->daddr.s6_addr32[1] ^
6564 hdr.ipv6->daddr.s6_addr32[2] ^
6565 hdr.ipv6->daddr.s6_addr32[3];
6566 }
6567
6568 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6569 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6570 input, common, ring->queue_index);
6571 }
6572
6573 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6574 {
6575 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6576 /* Herbert's original patch had:
6577 * smp_mb__after_netif_stop_queue();
6578 * but since that doesn't exist yet, just open code it. */
6579 smp_mb();
6580
6581 /* We need to check again in a case another CPU has just
6582 * made room available. */
6583 if (likely(ixgbe_desc_unused(tx_ring) < size))
6584 return -EBUSY;
6585
6586 /* A reprieve! - use start_queue because it doesn't call schedule */
6587 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6588 ++tx_ring->tx_stats.restart_queue;
6589 return 0;
6590 }
6591
6592 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6593 {
6594 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6595 return 0;
6596 return __ixgbe_maybe_stop_tx(tx_ring, size);
6597 }
6598
6599 #ifdef IXGBE_FCOE
6600 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6601 {
6602 struct ixgbe_adapter *adapter;
6603 struct ixgbe_ring_feature *f;
6604 int txq;
6605
6606 /*
6607 * only execute the code below if protocol is FCoE
6608 * or FIP and we have FCoE enabled on the adapter
6609 */
6610 switch (vlan_get_protocol(skb)) {
6611 case __constant_htons(ETH_P_FCOE):
6612 case __constant_htons(ETH_P_FIP):
6613 adapter = netdev_priv(dev);
6614
6615 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6616 break;
6617 default:
6618 return __netdev_pick_tx(dev, skb);
6619 }
6620
6621 f = &adapter->ring_feature[RING_F_FCOE];
6622
6623 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6624 smp_processor_id();
6625
6626 while (txq >= f->indices)
6627 txq -= f->indices;
6628
6629 return txq + f->offset;
6630 }
6631
6632 #endif
6633 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6634 struct ixgbe_adapter *adapter,
6635 struct ixgbe_ring *tx_ring)
6636 {
6637 struct ixgbe_tx_buffer *first;
6638 int tso;
6639 u32 tx_flags = 0;
6640 unsigned short f;
6641 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6642 __be16 protocol = skb->protocol;
6643 u8 hdr_len = 0;
6644
6645 /*
6646 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6647 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6648 * + 2 desc gap to keep tail from touching head,
6649 * + 1 desc for context descriptor,
6650 * otherwise try next time
6651 */
6652 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6653 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6654
6655 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6656 tx_ring->tx_stats.tx_busy++;
6657 return NETDEV_TX_BUSY;
6658 }
6659
6660 /* record the location of the first descriptor for this packet */
6661 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6662 first->skb = skb;
6663 first->bytecount = skb->len;
6664 first->gso_segs = 1;
6665
6666 /* if we have a HW VLAN tag being added default to the HW one */
6667 if (vlan_tx_tag_present(skb)) {
6668 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6669 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6670 /* else if it is a SW VLAN check the next protocol and store the tag */
6671 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6672 struct vlan_hdr *vhdr, _vhdr;
6673 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6674 if (!vhdr)
6675 goto out_drop;
6676
6677 protocol = vhdr->h_vlan_encapsulated_proto;
6678 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6679 IXGBE_TX_FLAGS_VLAN_SHIFT;
6680 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6681 }
6682
6683 skb_tx_timestamp(skb);
6684
6685 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6686 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6687 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6688
6689 /* schedule check for Tx timestamp */
6690 adapter->ptp_tx_skb = skb_get(skb);
6691 adapter->ptp_tx_start = jiffies;
6692 schedule_work(&adapter->ptp_tx_work);
6693 }
6694
6695 #ifdef CONFIG_PCI_IOV
6696 /*
6697 * Use the l2switch_enable flag - would be false if the DMA
6698 * Tx switch had been disabled.
6699 */
6700 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6701 tx_flags |= IXGBE_TX_FLAGS_CC;
6702
6703 #endif
6704 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6705 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6706 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6707 (skb->priority != TC_PRIO_CONTROL))) {
6708 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6709 tx_flags |= (skb->priority & 0x7) <<
6710 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6711 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6712 struct vlan_ethhdr *vhdr;
6713 if (skb_header_cloned(skb) &&
6714 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6715 goto out_drop;
6716 vhdr = (struct vlan_ethhdr *)skb->data;
6717 vhdr->h_vlan_TCI = htons(tx_flags >>
6718 IXGBE_TX_FLAGS_VLAN_SHIFT);
6719 } else {
6720 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6721 }
6722 }
6723
6724 /* record initial flags and protocol */
6725 first->tx_flags = tx_flags;
6726 first->protocol = protocol;
6727
6728 #ifdef IXGBE_FCOE
6729 /* setup tx offload for FCoE */
6730 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6731 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
6732 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6733 if (tso < 0)
6734 goto out_drop;
6735
6736 goto xmit_fcoe;
6737 }
6738
6739 #endif /* IXGBE_FCOE */
6740 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6741 if (tso < 0)
6742 goto out_drop;
6743 else if (!tso)
6744 ixgbe_tx_csum(tx_ring, first);
6745
6746 /* add the ATR filter if ATR is on */
6747 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6748 ixgbe_atr(tx_ring, first);
6749
6750 #ifdef IXGBE_FCOE
6751 xmit_fcoe:
6752 #endif /* IXGBE_FCOE */
6753 ixgbe_tx_map(tx_ring, first, hdr_len);
6754
6755 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6756
6757 return NETDEV_TX_OK;
6758
6759 out_drop:
6760 dev_kfree_skb_any(first->skb);
6761 first->skb = NULL;
6762
6763 return NETDEV_TX_OK;
6764 }
6765
6766 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6767 struct net_device *netdev)
6768 {
6769 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6770 struct ixgbe_ring *tx_ring;
6771
6772 /*
6773 * The minimum packet size for olinfo paylen is 17 so pad the skb
6774 * in order to meet this minimum size requirement.
6775 */
6776 if (unlikely(skb->len < 17)) {
6777 if (skb_pad(skb, 17 - skb->len))
6778 return NETDEV_TX_OK;
6779 skb->len = 17;
6780 skb_set_tail_pointer(skb, 17);
6781 }
6782
6783 tx_ring = adapter->tx_ring[skb->queue_mapping];
6784 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6785 }
6786
6787 /**
6788 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6789 * @netdev: network interface device structure
6790 * @p: pointer to an address structure
6791 *
6792 * Returns 0 on success, negative on failure
6793 **/
6794 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6795 {
6796 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6797 struct ixgbe_hw *hw = &adapter->hw;
6798 struct sockaddr *addr = p;
6799
6800 if (!is_valid_ether_addr(addr->sa_data))
6801 return -EADDRNOTAVAIL;
6802
6803 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6804 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6805
6806 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
6807
6808 return 0;
6809 }
6810
6811 static int
6812 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6813 {
6814 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6815 struct ixgbe_hw *hw = &adapter->hw;
6816 u16 value;
6817 int rc;
6818
6819 if (prtad != hw->phy.mdio.prtad)
6820 return -EINVAL;
6821 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6822 if (!rc)
6823 rc = value;
6824 return rc;
6825 }
6826
6827 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6828 u16 addr, u16 value)
6829 {
6830 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6831 struct ixgbe_hw *hw = &adapter->hw;
6832
6833 if (prtad != hw->phy.mdio.prtad)
6834 return -EINVAL;
6835 return hw->phy.ops.write_reg(hw, addr, devad, value);
6836 }
6837
6838 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6839 {
6840 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6841
6842 switch (cmd) {
6843 case SIOCSHWTSTAMP:
6844 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6845 default:
6846 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6847 }
6848 }
6849
6850 /**
6851 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6852 * netdev->dev_addrs
6853 * @netdev: network interface device structure
6854 *
6855 * Returns non-zero on failure
6856 **/
6857 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6858 {
6859 int err = 0;
6860 struct ixgbe_adapter *adapter = netdev_priv(dev);
6861 struct ixgbe_hw *hw = &adapter->hw;
6862
6863 if (is_valid_ether_addr(hw->mac.san_addr)) {
6864 rtnl_lock();
6865 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
6866 rtnl_unlock();
6867
6868 /* update SAN MAC vmdq pool selection */
6869 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
6870 }
6871 return err;
6872 }
6873
6874 /**
6875 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6876 * netdev->dev_addrs
6877 * @netdev: network interface device structure
6878 *
6879 * Returns non-zero on failure
6880 **/
6881 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6882 {
6883 int err = 0;
6884 struct ixgbe_adapter *adapter = netdev_priv(dev);
6885 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6886
6887 if (is_valid_ether_addr(mac->san_addr)) {
6888 rtnl_lock();
6889 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6890 rtnl_unlock();
6891 }
6892 return err;
6893 }
6894
6895 #ifdef CONFIG_NET_POLL_CONTROLLER
6896 /*
6897 * Polling 'interrupt' - used by things like netconsole to send skbs
6898 * without having to re-enable interrupts. It's not called while
6899 * the interrupt routine is executing.
6900 */
6901 static void ixgbe_netpoll(struct net_device *netdev)
6902 {
6903 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6904 int i;
6905
6906 /* if interface is down do nothing */
6907 if (test_bit(__IXGBE_DOWN, &adapter->state))
6908 return;
6909
6910 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6911 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6912 for (i = 0; i < adapter->num_q_vectors; i++)
6913 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
6914 } else {
6915 ixgbe_intr(adapter->pdev->irq, netdev);
6916 }
6917 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6918 }
6919
6920 #endif
6921 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6922 struct rtnl_link_stats64 *stats)
6923 {
6924 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6925 int i;
6926
6927 rcu_read_lock();
6928 for (i = 0; i < adapter->num_rx_queues; i++) {
6929 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6930 u64 bytes, packets;
6931 unsigned int start;
6932
6933 if (ring) {
6934 do {
6935 start = u64_stats_fetch_begin_bh(&ring->syncp);
6936 packets = ring->stats.packets;
6937 bytes = ring->stats.bytes;
6938 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6939 stats->rx_packets += packets;
6940 stats->rx_bytes += bytes;
6941 }
6942 }
6943
6944 for (i = 0; i < adapter->num_tx_queues; i++) {
6945 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6946 u64 bytes, packets;
6947 unsigned int start;
6948
6949 if (ring) {
6950 do {
6951 start = u64_stats_fetch_begin_bh(&ring->syncp);
6952 packets = ring->stats.packets;
6953 bytes = ring->stats.bytes;
6954 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6955 stats->tx_packets += packets;
6956 stats->tx_bytes += bytes;
6957 }
6958 }
6959 rcu_read_unlock();
6960 /* following stats updated by ixgbe_watchdog_task() */
6961 stats->multicast = netdev->stats.multicast;
6962 stats->rx_errors = netdev->stats.rx_errors;
6963 stats->rx_length_errors = netdev->stats.rx_length_errors;
6964 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6965 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6966 return stats;
6967 }
6968
6969 #ifdef CONFIG_IXGBE_DCB
6970 /**
6971 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6972 * @adapter: pointer to ixgbe_adapter
6973 * @tc: number of traffic classes currently enabled
6974 *
6975 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6976 * 802.1Q priority maps to a packet buffer that exists.
6977 */
6978 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6979 {
6980 struct ixgbe_hw *hw = &adapter->hw;
6981 u32 reg, rsave;
6982 int i;
6983
6984 /* 82598 have a static priority to TC mapping that can not
6985 * be changed so no validation is needed.
6986 */
6987 if (hw->mac.type == ixgbe_mac_82598EB)
6988 return;
6989
6990 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6991 rsave = reg;
6992
6993 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6994 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6995
6996 /* If up2tc is out of bounds default to zero */
6997 if (up2tc > tc)
6998 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6999 }
7000
7001 if (reg != rsave)
7002 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7003
7004 return;
7005 }
7006
7007 /**
7008 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7009 * @adapter: Pointer to adapter struct
7010 *
7011 * Populate the netdev user priority to tc map
7012 */
7013 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7014 {
7015 struct net_device *dev = adapter->netdev;
7016 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7017 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7018 u8 prio;
7019
7020 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7021 u8 tc = 0;
7022
7023 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7024 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7025 else if (ets)
7026 tc = ets->prio_tc[prio];
7027
7028 netdev_set_prio_tc_map(dev, prio, tc);
7029 }
7030 }
7031
7032 #endif /* CONFIG_IXGBE_DCB */
7033 /**
7034 * ixgbe_setup_tc - configure net_device for multiple traffic classes
7035 *
7036 * @netdev: net device to configure
7037 * @tc: number of traffic classes to enable
7038 */
7039 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7040 {
7041 struct ixgbe_adapter *adapter = netdev_priv(dev);
7042 struct ixgbe_hw *hw = &adapter->hw;
7043
7044 /* Hardware supports up to 8 traffic classes */
7045 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
7046 (hw->mac.type == ixgbe_mac_82598EB &&
7047 tc < MAX_TRAFFIC_CLASS))
7048 return -EINVAL;
7049
7050 /* Hardware has to reinitialize queues and interrupts to
7051 * match packet buffer alignment. Unfortunately, the
7052 * hardware is not flexible enough to do this dynamically.
7053 */
7054 if (netif_running(dev))
7055 ixgbe_close(dev);
7056 ixgbe_clear_interrupt_scheme(adapter);
7057
7058 #ifdef CONFIG_IXGBE_DCB
7059 if (tc) {
7060 netdev_set_num_tc(dev, tc);
7061 ixgbe_set_prio_tc_map(adapter);
7062
7063 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7064
7065 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7066 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
7067 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7068 }
7069 } else {
7070 netdev_reset_tc(dev);
7071
7072 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7073 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7074
7075 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7076
7077 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7078 adapter->dcb_cfg.pfc_mode_enable = false;
7079 }
7080
7081 ixgbe_validate_rtr(adapter, tc);
7082
7083 #endif /* CONFIG_IXGBE_DCB */
7084 ixgbe_init_interrupt_scheme(adapter);
7085
7086 if (netif_running(dev))
7087 return ixgbe_open(dev);
7088
7089 return 0;
7090 }
7091
7092 #ifdef CONFIG_PCI_IOV
7093 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7094 {
7095 struct net_device *netdev = adapter->netdev;
7096
7097 rtnl_lock();
7098 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
7099 rtnl_unlock();
7100 }
7101
7102 #endif
7103 void ixgbe_do_reset(struct net_device *netdev)
7104 {
7105 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7106
7107 if (netif_running(netdev))
7108 ixgbe_reinit_locked(adapter);
7109 else
7110 ixgbe_reset(adapter);
7111 }
7112
7113 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7114 netdev_features_t features)
7115 {
7116 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7117
7118 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7119 if (!(features & NETIF_F_RXCSUM))
7120 features &= ~NETIF_F_LRO;
7121
7122 /* Turn off LRO if not RSC capable */
7123 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7124 features &= ~NETIF_F_LRO;
7125
7126 return features;
7127 }
7128
7129 static int ixgbe_set_features(struct net_device *netdev,
7130 netdev_features_t features)
7131 {
7132 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7133 netdev_features_t changed = netdev->features ^ features;
7134 bool need_reset = false;
7135
7136 /* Make sure RSC matches LRO, reset if change */
7137 if (!(features & NETIF_F_LRO)) {
7138 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7139 need_reset = true;
7140 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7141 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7142 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7143 if (adapter->rx_itr_setting == 1 ||
7144 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7145 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7146 need_reset = true;
7147 } else if ((changed ^ features) & NETIF_F_LRO) {
7148 e_info(probe, "rx-usecs set too low, "
7149 "disabling RSC\n");
7150 }
7151 }
7152
7153 /*
7154 * Check if Flow Director n-tuple support was enabled or disabled. If
7155 * the state changed, we need to reset.
7156 */
7157 switch (features & NETIF_F_NTUPLE) {
7158 case NETIF_F_NTUPLE:
7159 /* turn off ATR, enable perfect filters and reset */
7160 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7161 need_reset = true;
7162
7163 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7164 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7165 break;
7166 default:
7167 /* turn off perfect filters, enable ATR and reset */
7168 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7169 need_reset = true;
7170
7171 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7172
7173 /* We cannot enable ATR if SR-IOV is enabled */
7174 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7175 break;
7176
7177 /* We cannot enable ATR if we have 2 or more traffic classes */
7178 if (netdev_get_num_tc(netdev) > 1)
7179 break;
7180
7181 /* We cannot enable ATR if RSS is disabled */
7182 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7183 break;
7184
7185 /* A sample rate of 0 indicates ATR disabled */
7186 if (!adapter->atr_sample_rate)
7187 break;
7188
7189 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7190 break;
7191 }
7192
7193 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7194 ixgbe_vlan_strip_enable(adapter);
7195 else
7196 ixgbe_vlan_strip_disable(adapter);
7197
7198 if (changed & NETIF_F_RXALL)
7199 need_reset = true;
7200
7201 netdev->features = features;
7202 if (need_reset)
7203 ixgbe_do_reset(netdev);
7204
7205 return 0;
7206 }
7207
7208 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7209 struct net_device *dev,
7210 const unsigned char *addr,
7211 u16 flags)
7212 {
7213 struct ixgbe_adapter *adapter = netdev_priv(dev);
7214 int err;
7215
7216 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7217 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
7218
7219 /* Hardware does not support aging addresses so if a
7220 * ndm_state is given only allow permanent addresses
7221 */
7222 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7223 pr_info("%s: FDB only supports static addresses\n",
7224 ixgbe_driver_name);
7225 return -EINVAL;
7226 }
7227
7228 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
7229 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7230
7231 if (netdev_uc_count(dev) < rar_uc_entries)
7232 err = dev_uc_add_excl(dev, addr);
7233 else
7234 err = -ENOMEM;
7235 } else if (is_multicast_ether_addr(addr)) {
7236 err = dev_mc_add_excl(dev, addr);
7237 } else {
7238 err = -EINVAL;
7239 }
7240
7241 /* Only return duplicate errors if NLM_F_EXCL is set */
7242 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7243 err = 0;
7244
7245 return err;
7246 }
7247
7248 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7249 struct nlmsghdr *nlh)
7250 {
7251 struct ixgbe_adapter *adapter = netdev_priv(dev);
7252 struct nlattr *attr, *br_spec;
7253 int rem;
7254
7255 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7256 return -EOPNOTSUPP;
7257
7258 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7259
7260 nla_for_each_nested(attr, br_spec, rem) {
7261 __u16 mode;
7262 u32 reg = 0;
7263
7264 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7265 continue;
7266
7267 mode = nla_get_u16(attr);
7268 if (mode == BRIDGE_MODE_VEPA) {
7269 reg = 0;
7270 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7271 } else if (mode == BRIDGE_MODE_VEB) {
7272 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7273 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7274 } else
7275 return -EINVAL;
7276
7277 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7278
7279 e_info(drv, "enabling bridge mode: %s\n",
7280 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7281 }
7282
7283 return 0;
7284 }
7285
7286 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7287 struct net_device *dev,
7288 u32 filter_mask)
7289 {
7290 struct ixgbe_adapter *adapter = netdev_priv(dev);
7291 u16 mode;
7292
7293 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7294 return 0;
7295
7296 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
7297 mode = BRIDGE_MODE_VEB;
7298 else
7299 mode = BRIDGE_MODE_VEPA;
7300
7301 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7302 }
7303
7304 static const struct net_device_ops ixgbe_netdev_ops = {
7305 .ndo_open = ixgbe_open,
7306 .ndo_stop = ixgbe_close,
7307 .ndo_start_xmit = ixgbe_xmit_frame,
7308 #ifdef IXGBE_FCOE
7309 .ndo_select_queue = ixgbe_select_queue,
7310 #endif
7311 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7312 .ndo_validate_addr = eth_validate_addr,
7313 .ndo_set_mac_address = ixgbe_set_mac,
7314 .ndo_change_mtu = ixgbe_change_mtu,
7315 .ndo_tx_timeout = ixgbe_tx_timeout,
7316 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7317 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7318 .ndo_do_ioctl = ixgbe_ioctl,
7319 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7320 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7321 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7322 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7323 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7324 .ndo_get_stats64 = ixgbe_get_stats64,
7325 #ifdef CONFIG_IXGBE_DCB
7326 .ndo_setup_tc = ixgbe_setup_tc,
7327 #endif
7328 #ifdef CONFIG_NET_POLL_CONTROLLER
7329 .ndo_poll_controller = ixgbe_netpoll,
7330 #endif
7331 #ifdef CONFIG_NET_RX_BUSY_POLL
7332 .ndo_busy_poll = ixgbe_low_latency_recv,
7333 #endif
7334 #ifdef IXGBE_FCOE
7335 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7336 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7337 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7338 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7339 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7340 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7341 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7342 #endif /* IXGBE_FCOE */
7343 .ndo_set_features = ixgbe_set_features,
7344 .ndo_fix_features = ixgbe_fix_features,
7345 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7346 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7347 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
7348 };
7349
7350 /**
7351 * ixgbe_enumerate_functions - Get the number of ports this device has
7352 * @adapter: adapter structure
7353 *
7354 * This function enumerates the phsyical functions co-located on a single slot,
7355 * in order to determine how many ports a device has. This is most useful in
7356 * determining the required GT/s of PCIe bandwidth necessary for optimal
7357 * performance.
7358 **/
7359 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7360 {
7361 struct list_head *entry;
7362 int physfns = 0;
7363
7364 /* Some cards can not use the generic count PCIe functions method,
7365 * because they are behind a parent switch, so we hardcode these with
7366 * the correct number of functions.
7367 */
7368 if (ixgbe_pcie_from_parent(&adapter->hw)) {
7369 physfns = 4;
7370 } else {
7371 list_for_each(entry, &adapter->pdev->bus_list) {
7372 struct pci_dev *pdev =
7373 list_entry(entry, struct pci_dev, bus_list);
7374 /* don't count virtual functions */
7375 if (!pdev->is_virtfn)
7376 physfns++;
7377 }
7378 }
7379
7380 return physfns;
7381 }
7382
7383 /**
7384 * ixgbe_wol_supported - Check whether device supports WoL
7385 * @hw: hw specific details
7386 * @device_id: the device ID
7387 * @subdev_id: the subsystem device ID
7388 *
7389 * This function is used by probe and ethtool to determine
7390 * which devices have WoL support
7391 *
7392 **/
7393 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7394 u16 subdevice_id)
7395 {
7396 struct ixgbe_hw *hw = &adapter->hw;
7397 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7398 int is_wol_supported = 0;
7399
7400 switch (device_id) {
7401 case IXGBE_DEV_ID_82599_SFP:
7402 /* Only these subdevices could supports WOL */
7403 switch (subdevice_id) {
7404 case IXGBE_SUBDEV_ID_82599_560FLR:
7405 /* only support first port */
7406 if (hw->bus.func != 0)
7407 break;
7408 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
7409 case IXGBE_SUBDEV_ID_82599_SFP:
7410 case IXGBE_SUBDEV_ID_82599_RNDC:
7411 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
7412 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
7413 is_wol_supported = 1;
7414 break;
7415 }
7416 break;
7417 case IXGBE_DEV_ID_82599EN_SFP:
7418 /* Only this subdevice supports WOL */
7419 switch (subdevice_id) {
7420 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
7421 is_wol_supported = 1;
7422 break;
7423 }
7424 break;
7425 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7426 /* All except this subdevice support WOL */
7427 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7428 is_wol_supported = 1;
7429 break;
7430 case IXGBE_DEV_ID_82599_KX4:
7431 is_wol_supported = 1;
7432 break;
7433 case IXGBE_DEV_ID_X540T:
7434 case IXGBE_DEV_ID_X540T1:
7435 /* check eeprom to see if enabled wol */
7436 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7437 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7438 (hw->bus.func == 0))) {
7439 is_wol_supported = 1;
7440 }
7441 break;
7442 }
7443
7444 return is_wol_supported;
7445 }
7446
7447 /**
7448 * ixgbe_probe - Device Initialization Routine
7449 * @pdev: PCI device information struct
7450 * @ent: entry in ixgbe_pci_tbl
7451 *
7452 * Returns 0 on success, negative on failure
7453 *
7454 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7455 * The OS initialization, configuring of the adapter private structure,
7456 * and a hardware reset occur.
7457 **/
7458 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7459 {
7460 struct net_device *netdev;
7461 struct ixgbe_adapter *adapter = NULL;
7462 struct ixgbe_hw *hw;
7463 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7464 static int cards_found;
7465 int i, err, pci_using_dac, expected_gts;
7466 unsigned int indices = MAX_TX_QUEUES;
7467 u8 part_str[IXGBE_PBANUM_LENGTH];
7468 #ifdef IXGBE_FCOE
7469 u16 device_caps;
7470 #endif
7471 u32 eec;
7472
7473 /* Catch broken hardware that put the wrong VF device ID in
7474 * the PCIe SR-IOV capability.
7475 */
7476 if (pdev->is_virtfn) {
7477 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7478 pci_name(pdev), pdev->vendor, pdev->device);
7479 return -EINVAL;
7480 }
7481
7482 err = pci_enable_device_mem(pdev);
7483 if (err)
7484 return err;
7485
7486 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7487 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7488 pci_using_dac = 1;
7489 } else {
7490 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7491 if (err) {
7492 err = dma_set_coherent_mask(&pdev->dev,
7493 DMA_BIT_MASK(32));
7494 if (err) {
7495 dev_err(&pdev->dev,
7496 "No usable DMA configuration, aborting\n");
7497 goto err_dma;
7498 }
7499 }
7500 pci_using_dac = 0;
7501 }
7502
7503 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7504 IORESOURCE_MEM), ixgbe_driver_name);
7505 if (err) {
7506 dev_err(&pdev->dev,
7507 "pci_request_selected_regions failed 0x%x\n", err);
7508 goto err_pci_reg;
7509 }
7510
7511 pci_enable_pcie_error_reporting(pdev);
7512
7513 pci_set_master(pdev);
7514 pci_save_state(pdev);
7515
7516 if (ii->mac == ixgbe_mac_82598EB) {
7517 #ifdef CONFIG_IXGBE_DCB
7518 /* 8 TC w/ 4 queues per TC */
7519 indices = 4 * MAX_TRAFFIC_CLASS;
7520 #else
7521 indices = IXGBE_MAX_RSS_INDICES;
7522 #endif
7523 }
7524
7525 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7526 if (!netdev) {
7527 err = -ENOMEM;
7528 goto err_alloc_etherdev;
7529 }
7530
7531 SET_NETDEV_DEV(netdev, &pdev->dev);
7532
7533 adapter = netdev_priv(netdev);
7534 pci_set_drvdata(pdev, adapter);
7535
7536 adapter->netdev = netdev;
7537 adapter->pdev = pdev;
7538 hw = &adapter->hw;
7539 hw->back = adapter;
7540 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7541
7542 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7543 pci_resource_len(pdev, 0));
7544 if (!hw->hw_addr) {
7545 err = -EIO;
7546 goto err_ioremap;
7547 }
7548
7549 netdev->netdev_ops = &ixgbe_netdev_ops;
7550 ixgbe_set_ethtool_ops(netdev);
7551 netdev->watchdog_timeo = 5 * HZ;
7552 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7553
7554 adapter->bd_number = cards_found;
7555
7556 /* Setup hw api */
7557 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7558 hw->mac.type = ii->mac;
7559
7560 /* EEPROM */
7561 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7562 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7563 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7564 if (!(eec & (1 << 8)))
7565 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7566
7567 /* PHY */
7568 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7569 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7570 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7571 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7572 hw->phy.mdio.mmds = 0;
7573 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7574 hw->phy.mdio.dev = netdev;
7575 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7576 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7577
7578 ii->get_invariants(hw);
7579
7580 /* setup the private structure */
7581 err = ixgbe_sw_init(adapter);
7582 if (err)
7583 goto err_sw_init;
7584
7585 /* Cache if MNG FW is up so we don't have to read the REG later */
7586 if (hw->mac.ops.mng_fw_enabled)
7587 hw->mng_fw_enabled = hw->mac.ops.mng_fw_enabled(hw);
7588
7589 /* Make it possible the adapter to be woken up via WOL */
7590 switch (adapter->hw.mac.type) {
7591 case ixgbe_mac_82599EB:
7592 case ixgbe_mac_X540:
7593 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7594 break;
7595 default:
7596 break;
7597 }
7598
7599 /*
7600 * If there is a fan on this device and it has failed log the
7601 * failure.
7602 */
7603 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7604 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7605 if (esdp & IXGBE_ESDP_SDP1)
7606 e_crit(probe, "Fan has stopped, replace the adapter\n");
7607 }
7608
7609 if (allow_unsupported_sfp)
7610 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7611
7612 /* reset_hw fills in the perm_addr as well */
7613 hw->phy.reset_if_overtemp = true;
7614 err = hw->mac.ops.reset_hw(hw);
7615 hw->phy.reset_if_overtemp = false;
7616 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7617 hw->mac.type == ixgbe_mac_82598EB) {
7618 err = 0;
7619 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7620 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
7621 e_dev_err("Reload the driver after installing a supported module.\n");
7622 goto err_sw_init;
7623 } else if (err) {
7624 e_dev_err("HW Init failed: %d\n", err);
7625 goto err_sw_init;
7626 }
7627
7628 #ifdef CONFIG_PCI_IOV
7629 /* SR-IOV not supported on the 82598 */
7630 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7631 goto skip_sriov;
7632 /* Mailbox */
7633 ixgbe_init_mbx_params_pf(hw);
7634 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
7635 ixgbe_enable_sriov(adapter);
7636 pci_sriov_set_totalvfs(pdev, 63);
7637 skip_sriov:
7638
7639 #endif
7640 netdev->features = NETIF_F_SG |
7641 NETIF_F_IP_CSUM |
7642 NETIF_F_IPV6_CSUM |
7643 NETIF_F_HW_VLAN_CTAG_TX |
7644 NETIF_F_HW_VLAN_CTAG_RX |
7645 NETIF_F_HW_VLAN_CTAG_FILTER |
7646 NETIF_F_TSO |
7647 NETIF_F_TSO6 |
7648 NETIF_F_RXHASH |
7649 NETIF_F_RXCSUM;
7650
7651 netdev->hw_features = netdev->features;
7652
7653 switch (adapter->hw.mac.type) {
7654 case ixgbe_mac_82599EB:
7655 case ixgbe_mac_X540:
7656 netdev->features |= NETIF_F_SCTP_CSUM;
7657 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7658 NETIF_F_NTUPLE;
7659 break;
7660 default:
7661 break;
7662 }
7663
7664 netdev->hw_features |= NETIF_F_RXALL;
7665
7666 netdev->vlan_features |= NETIF_F_TSO;
7667 netdev->vlan_features |= NETIF_F_TSO6;
7668 netdev->vlan_features |= NETIF_F_IP_CSUM;
7669 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7670 netdev->vlan_features |= NETIF_F_SG;
7671
7672 netdev->priv_flags |= IFF_UNICAST_FLT;
7673 netdev->priv_flags |= IFF_SUPP_NOFCS;
7674
7675 #ifdef CONFIG_IXGBE_DCB
7676 netdev->dcbnl_ops = &dcbnl_ops;
7677 #endif
7678
7679 #ifdef IXGBE_FCOE
7680 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7681 unsigned int fcoe_l;
7682
7683 if (hw->mac.ops.get_device_caps) {
7684 hw->mac.ops.get_device_caps(hw, &device_caps);
7685 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7686 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7687 }
7688
7689
7690 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
7691 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7692
7693 netdev->features |= NETIF_F_FSO |
7694 NETIF_F_FCOE_CRC;
7695
7696 netdev->vlan_features |= NETIF_F_FSO |
7697 NETIF_F_FCOE_CRC |
7698 NETIF_F_FCOE_MTU;
7699 }
7700 #endif /* IXGBE_FCOE */
7701 if (pci_using_dac) {
7702 netdev->features |= NETIF_F_HIGHDMA;
7703 netdev->vlan_features |= NETIF_F_HIGHDMA;
7704 }
7705
7706 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7707 netdev->hw_features |= NETIF_F_LRO;
7708 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7709 netdev->features |= NETIF_F_LRO;
7710
7711 /* make sure the EEPROM is good */
7712 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7713 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7714 err = -EIO;
7715 goto err_sw_init;
7716 }
7717
7718 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7719
7720 if (!is_valid_ether_addr(netdev->dev_addr)) {
7721 e_dev_err("invalid MAC address\n");
7722 err = -EIO;
7723 goto err_sw_init;
7724 }
7725
7726 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7727 (unsigned long) adapter);
7728
7729 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7730 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7731
7732 err = ixgbe_init_interrupt_scheme(adapter);
7733 if (err)
7734 goto err_sw_init;
7735
7736 /* WOL not supported for all devices */
7737 adapter->wol = 0;
7738 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7739 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
7740 pdev->subsystem_device);
7741 if (hw->wol_enabled)
7742 adapter->wol = IXGBE_WUFC_MAG;
7743
7744 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7745
7746 /* save off EEPROM version number */
7747 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7748 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7749
7750 /* pick up the PCI bus settings for reporting later */
7751 hw->mac.ops.get_bus_info(hw);
7752 if (ixgbe_pcie_from_parent(hw))
7753 ixgbe_get_parent_bus_info(adapter);
7754
7755 /* calculate the expected PCIe bandwidth required for optimal
7756 * performance. Note that some older parts will never have enough
7757 * bandwidth due to being older generation PCIe parts. We clamp these
7758 * parts to ensure no warning is displayed if it can't be fixed.
7759 */
7760 switch (hw->mac.type) {
7761 case ixgbe_mac_82598EB:
7762 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
7763 break;
7764 default:
7765 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
7766 break;
7767 }
7768 ixgbe_check_minimum_link(adapter, expected_gts);
7769
7770 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7771 if (err)
7772 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7773 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7774 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7775 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7776 part_str);
7777 else
7778 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7779 hw->mac.type, hw->phy.type, part_str);
7780
7781 e_dev_info("%pM\n", netdev->dev_addr);
7782
7783 /* reset the hardware with the new settings */
7784 err = hw->mac.ops.start_hw(hw);
7785 if (err == IXGBE_ERR_EEPROM_VERSION) {
7786 /* We are running on a pre-production device, log a warning */
7787 e_dev_warn("This device is a pre-production adapter/LOM. "
7788 "Please be aware there may be issues associated "
7789 "with your hardware. If you are experiencing "
7790 "problems please contact your Intel or hardware "
7791 "representative who provided you with this "
7792 "hardware.\n");
7793 }
7794 strcpy(netdev->name, "eth%d");
7795 err = register_netdev(netdev);
7796 if (err)
7797 goto err_register;
7798
7799 /* power down the optics for 82599 SFP+ fiber */
7800 if (hw->mac.ops.disable_tx_laser)
7801 hw->mac.ops.disable_tx_laser(hw);
7802
7803 /* carrier off reporting is important to ethtool even BEFORE open */
7804 netif_carrier_off(netdev);
7805
7806 #ifdef CONFIG_IXGBE_DCA
7807 if (dca_add_requester(&pdev->dev) == 0) {
7808 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7809 ixgbe_setup_dca(adapter);
7810 }
7811 #endif
7812 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7813 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7814 for (i = 0; i < adapter->num_vfs; i++)
7815 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7816 }
7817
7818 /* firmware requires driver version to be 0xFFFFFFFF
7819 * since os does not support feature
7820 */
7821 if (hw->mac.ops.set_fw_drv_ver)
7822 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7823 0xFF);
7824
7825 /* add san mac addr to netdev */
7826 ixgbe_add_sanmac_netdev(netdev);
7827
7828 e_dev_info("%s\n", ixgbe_default_device_descr);
7829 cards_found++;
7830
7831 #ifdef CONFIG_IXGBE_HWMON
7832 if (ixgbe_sysfs_init(adapter))
7833 e_err(probe, "failed to allocate sysfs resources\n");
7834 #endif /* CONFIG_IXGBE_HWMON */
7835
7836 ixgbe_dbg_adapter_init(adapter);
7837
7838 /* Need link setup for MNG FW, else wait for IXGBE_UP */
7839 if (hw->mng_fw_enabled && hw->mac.ops.setup_link)
7840 hw->mac.ops.setup_link(hw,
7841 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
7842 true);
7843
7844 return 0;
7845
7846 err_register:
7847 ixgbe_release_hw_control(adapter);
7848 ixgbe_clear_interrupt_scheme(adapter);
7849 err_sw_init:
7850 ixgbe_disable_sriov(adapter);
7851 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7852 iounmap(hw->hw_addr);
7853 err_ioremap:
7854 free_netdev(netdev);
7855 err_alloc_etherdev:
7856 pci_release_selected_regions(pdev,
7857 pci_select_bars(pdev, IORESOURCE_MEM));
7858 err_pci_reg:
7859 err_dma:
7860 pci_disable_device(pdev);
7861 return err;
7862 }
7863
7864 /**
7865 * ixgbe_remove - Device Removal Routine
7866 * @pdev: PCI device information struct
7867 *
7868 * ixgbe_remove is called by the PCI subsystem to alert the driver
7869 * that it should release a PCI device. The could be caused by a
7870 * Hot-Plug event, or because the driver is going to be removed from
7871 * memory.
7872 **/
7873 static void ixgbe_remove(struct pci_dev *pdev)
7874 {
7875 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7876 struct net_device *netdev = adapter->netdev;
7877
7878 ixgbe_dbg_adapter_exit(adapter);
7879
7880 set_bit(__IXGBE_DOWN, &adapter->state);
7881 cancel_work_sync(&adapter->service_task);
7882
7883
7884 #ifdef CONFIG_IXGBE_DCA
7885 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7886 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7887 dca_remove_requester(&pdev->dev);
7888 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7889 }
7890
7891 #endif
7892 #ifdef CONFIG_IXGBE_HWMON
7893 ixgbe_sysfs_exit(adapter);
7894 #endif /* CONFIG_IXGBE_HWMON */
7895
7896 /* remove the added san mac */
7897 ixgbe_del_sanmac_netdev(netdev);
7898
7899 if (netdev->reg_state == NETREG_REGISTERED)
7900 unregister_netdev(netdev);
7901
7902 #ifdef CONFIG_PCI_IOV
7903 /*
7904 * Only disable SR-IOV on unload if the user specified the now
7905 * deprecated max_vfs module parameter.
7906 */
7907 if (max_vfs)
7908 ixgbe_disable_sriov(adapter);
7909 #endif
7910 ixgbe_clear_interrupt_scheme(adapter);
7911
7912 ixgbe_release_hw_control(adapter);
7913
7914 #ifdef CONFIG_DCB
7915 kfree(adapter->ixgbe_ieee_pfc);
7916 kfree(adapter->ixgbe_ieee_ets);
7917
7918 #endif
7919 iounmap(adapter->hw.hw_addr);
7920 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7921 IORESOURCE_MEM));
7922
7923 e_dev_info("complete\n");
7924
7925 free_netdev(netdev);
7926
7927 pci_disable_pcie_error_reporting(pdev);
7928
7929 pci_disable_device(pdev);
7930 }
7931
7932 /**
7933 * ixgbe_io_error_detected - called when PCI error is detected
7934 * @pdev: Pointer to PCI device
7935 * @state: The current pci connection state
7936 *
7937 * This function is called after a PCI bus error affecting
7938 * this device has been detected.
7939 */
7940 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7941 pci_channel_state_t state)
7942 {
7943 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7944 struct net_device *netdev = adapter->netdev;
7945
7946 #ifdef CONFIG_PCI_IOV
7947 struct pci_dev *bdev, *vfdev;
7948 u32 dw0, dw1, dw2, dw3;
7949 int vf, pos;
7950 u16 req_id, pf_func;
7951
7952 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7953 adapter->num_vfs == 0)
7954 goto skip_bad_vf_detection;
7955
7956 bdev = pdev->bus->self;
7957 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
7958 bdev = bdev->bus->self;
7959
7960 if (!bdev)
7961 goto skip_bad_vf_detection;
7962
7963 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7964 if (!pos)
7965 goto skip_bad_vf_detection;
7966
7967 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7968 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7969 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7970 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7971
7972 req_id = dw1 >> 16;
7973 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7974 if (!(req_id & 0x0080))
7975 goto skip_bad_vf_detection;
7976
7977 pf_func = req_id & 0x01;
7978 if ((pf_func & 1) == (pdev->devfn & 1)) {
7979 unsigned int device_id;
7980
7981 vf = (req_id & 0x7F) >> 1;
7982 e_dev_err("VF %d has caused a PCIe error\n", vf);
7983 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7984 "%8.8x\tdw3: %8.8x\n",
7985 dw0, dw1, dw2, dw3);
7986 switch (adapter->hw.mac.type) {
7987 case ixgbe_mac_82599EB:
7988 device_id = IXGBE_82599_VF_DEVICE_ID;
7989 break;
7990 case ixgbe_mac_X540:
7991 device_id = IXGBE_X540_VF_DEVICE_ID;
7992 break;
7993 default:
7994 device_id = 0;
7995 break;
7996 }
7997
7998 /* Find the pci device of the offending VF */
7999 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
8000 while (vfdev) {
8001 if (vfdev->devfn == (req_id & 0xFF))
8002 break;
8003 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
8004 device_id, vfdev);
8005 }
8006 /*
8007 * There's a slim chance the VF could have been hot plugged,
8008 * so if it is no longer present we don't need to issue the
8009 * VFLR. Just clean up the AER in that case.
8010 */
8011 if (vfdev) {
8012 e_dev_err("Issuing VFLR to VF %d\n", vf);
8013 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
8014 /* Free device reference count */
8015 pci_dev_put(vfdev);
8016 }
8017
8018 pci_cleanup_aer_uncorrect_error_status(pdev);
8019 }
8020
8021 /*
8022 * Even though the error may have occurred on the other port
8023 * we still need to increment the vf error reference count for
8024 * both ports because the I/O resume function will be called
8025 * for both of them.
8026 */
8027 adapter->vferr_refcount++;
8028
8029 return PCI_ERS_RESULT_RECOVERED;
8030
8031 skip_bad_vf_detection:
8032 #endif /* CONFIG_PCI_IOV */
8033 netif_device_detach(netdev);
8034
8035 if (state == pci_channel_io_perm_failure)
8036 return PCI_ERS_RESULT_DISCONNECT;
8037
8038 if (netif_running(netdev))
8039 ixgbe_down(adapter);
8040 pci_disable_device(pdev);
8041
8042 /* Request a slot reset. */
8043 return PCI_ERS_RESULT_NEED_RESET;
8044 }
8045
8046 /**
8047 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8048 * @pdev: Pointer to PCI device
8049 *
8050 * Restart the card from scratch, as if from a cold-boot.
8051 */
8052 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8053 {
8054 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8055 pci_ers_result_t result;
8056 int err;
8057
8058 if (pci_enable_device_mem(pdev)) {
8059 e_err(probe, "Cannot re-enable PCI device after reset.\n");
8060 result = PCI_ERS_RESULT_DISCONNECT;
8061 } else {
8062 pci_set_master(pdev);
8063 pci_restore_state(pdev);
8064 pci_save_state(pdev);
8065
8066 pci_wake_from_d3(pdev, false);
8067
8068 ixgbe_reset(adapter);
8069 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
8070 result = PCI_ERS_RESULT_RECOVERED;
8071 }
8072
8073 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8074 if (err) {
8075 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8076 "failed 0x%0x\n", err);
8077 /* non-fatal, continue */
8078 }
8079
8080 return result;
8081 }
8082
8083 /**
8084 * ixgbe_io_resume - called when traffic can start flowing again.
8085 * @pdev: Pointer to PCI device
8086 *
8087 * This callback is called when the error recovery driver tells us that
8088 * its OK to resume normal operation.
8089 */
8090 static void ixgbe_io_resume(struct pci_dev *pdev)
8091 {
8092 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8093 struct net_device *netdev = adapter->netdev;
8094
8095 #ifdef CONFIG_PCI_IOV
8096 if (adapter->vferr_refcount) {
8097 e_info(drv, "Resuming after VF err\n");
8098 adapter->vferr_refcount--;
8099 return;
8100 }
8101
8102 #endif
8103 if (netif_running(netdev))
8104 ixgbe_up(adapter);
8105
8106 netif_device_attach(netdev);
8107 }
8108
8109 static const struct pci_error_handlers ixgbe_err_handler = {
8110 .error_detected = ixgbe_io_error_detected,
8111 .slot_reset = ixgbe_io_slot_reset,
8112 .resume = ixgbe_io_resume,
8113 };
8114
8115 static struct pci_driver ixgbe_driver = {
8116 .name = ixgbe_driver_name,
8117 .id_table = ixgbe_pci_tbl,
8118 .probe = ixgbe_probe,
8119 .remove = ixgbe_remove,
8120 #ifdef CONFIG_PM
8121 .suspend = ixgbe_suspend,
8122 .resume = ixgbe_resume,
8123 #endif
8124 .shutdown = ixgbe_shutdown,
8125 .sriov_configure = ixgbe_pci_sriov_configure,
8126 .err_handler = &ixgbe_err_handler
8127 };
8128
8129 /**
8130 * ixgbe_init_module - Driver Registration Routine
8131 *
8132 * ixgbe_init_module is the first routine called when the driver is
8133 * loaded. All it does is register with the PCI subsystem.
8134 **/
8135 static int __init ixgbe_init_module(void)
8136 {
8137 int ret;
8138 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
8139 pr_info("%s\n", ixgbe_copyright);
8140
8141 ixgbe_dbg_init();
8142
8143 ret = pci_register_driver(&ixgbe_driver);
8144 if (ret) {
8145 ixgbe_dbg_exit();
8146 return ret;
8147 }
8148
8149 #ifdef CONFIG_IXGBE_DCA
8150 dca_register_notify(&dca_notifier);
8151 #endif
8152
8153 return 0;
8154 }
8155
8156 module_init(ixgbe_init_module);
8157
8158 /**
8159 * ixgbe_exit_module - Driver Exit Cleanup Routine
8160 *
8161 * ixgbe_exit_module is called just before the driver is removed
8162 * from memory.
8163 **/
8164 static void __exit ixgbe_exit_module(void)
8165 {
8166 #ifdef CONFIG_IXGBE_DCA
8167 dca_unregister_notify(&dca_notifier);
8168 #endif
8169 pci_unregister_driver(&ixgbe_driver);
8170
8171 ixgbe_dbg_exit();
8172
8173 rcu_barrier(); /* Wait for completion of call_rcu()'s */
8174 }
8175
8176 #ifdef CONFIG_IXGBE_DCA
8177 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
8178 void *p)
8179 {
8180 int ret_val;
8181
8182 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
8183 __ixgbe_notify_dca);
8184
8185 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8186 }
8187
8188 #endif /* CONFIG_IXGBE_DCA */
8189
8190 module_exit(ixgbe_exit_module);
8191
8192 /* ixgbe_main.c */
Linux kernel - Deliverables
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