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ixgbe: update {P}FC thresholds to account for X540 and loopback
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/prefetch.h>
48 #include <scsi/fc/fc_fcoe.h>
49
50 #include "ixgbe.h"
51 #include "ixgbe_common.h"
52 #include "ixgbe_dcb_82599.h"
53 #include "ixgbe_sriov.h"
54
55 char ixgbe_driver_name[] = "ixgbe";
56 static const char ixgbe_driver_string[] =
57 "Intel(R) 10 Gigabit PCI Express Network Driver";
58 #define MAJ 3
59 #define MIN 4
60 #define BUILD 8
61 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
62 __stringify(BUILD) "-k"
63 const char ixgbe_driver_version[] = DRV_VERSION;
64 static const char ixgbe_copyright[] =
65 "Copyright (c) 1999-2011 Intel Corporation.";
66
67 static const struct ixgbe_info *ixgbe_info_tbl[] = {
68 [board_82598] = &ixgbe_82598_info,
69 [board_82599] = &ixgbe_82599_info,
70 [board_X540] = &ixgbe_X540_info,
71 };
72
73 /* ixgbe_pci_tbl - PCI Device ID Table
74 *
75 * Wildcard entries (PCI_ANY_ID) should come last
76 * Last entry must be all 0s
77 *
78 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
79 * Class, Class Mask, private data (not used) }
80 */
81 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
108 /* required last entry */
109 {0, }
110 };
111 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
112
113 #ifdef CONFIG_IXGBE_DCA
114 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
115 void *p);
116 static struct notifier_block dca_notifier = {
117 .notifier_call = ixgbe_notify_dca,
118 .next = NULL,
119 .priority = 0
120 };
121 #endif
122
123 #ifdef CONFIG_PCI_IOV
124 static unsigned int max_vfs;
125 module_param(max_vfs, uint, 0);
126 MODULE_PARM_DESC(max_vfs,
127 "Maximum number of virtual functions to allocate per physical function");
128 #endif /* CONFIG_PCI_IOV */
129
130 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
131 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
132 MODULE_LICENSE("GPL");
133 MODULE_VERSION(DRV_VERSION);
134
135 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
136
137 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
138 {
139 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
140 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
141 schedule_work(&adapter->service_task);
142 }
143
144 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
145 {
146 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
147
148 /* flush memory to make sure state is correct before next watchog */
149 smp_mb__before_clear_bit();
150 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
151 }
152
153 struct ixgbe_reg_info {
154 u32 ofs;
155 char *name;
156 };
157
158 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
159
160 /* General Registers */
161 {IXGBE_CTRL, "CTRL"},
162 {IXGBE_STATUS, "STATUS"},
163 {IXGBE_CTRL_EXT, "CTRL_EXT"},
164
165 /* Interrupt Registers */
166 {IXGBE_EICR, "EICR"},
167
168 /* RX Registers */
169 {IXGBE_SRRCTL(0), "SRRCTL"},
170 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
171 {IXGBE_RDLEN(0), "RDLEN"},
172 {IXGBE_RDH(0), "RDH"},
173 {IXGBE_RDT(0), "RDT"},
174 {IXGBE_RXDCTL(0), "RXDCTL"},
175 {IXGBE_RDBAL(0), "RDBAL"},
176 {IXGBE_RDBAH(0), "RDBAH"},
177
178 /* TX Registers */
179 {IXGBE_TDBAL(0), "TDBAL"},
180 {IXGBE_TDBAH(0), "TDBAH"},
181 {IXGBE_TDLEN(0), "TDLEN"},
182 {IXGBE_TDH(0), "TDH"},
183 {IXGBE_TDT(0), "TDT"},
184 {IXGBE_TXDCTL(0), "TXDCTL"},
185
186 /* List Terminator */
187 {}
188 };
189
190
191 /*
192 * ixgbe_regdump - register printout routine
193 */
194 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
195 {
196 int i = 0, j = 0;
197 char rname[16];
198 u32 regs[64];
199
200 switch (reginfo->ofs) {
201 case IXGBE_SRRCTL(0):
202 for (i = 0; i < 64; i++)
203 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
204 break;
205 case IXGBE_DCA_RXCTRL(0):
206 for (i = 0; i < 64; i++)
207 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
208 break;
209 case IXGBE_RDLEN(0):
210 for (i = 0; i < 64; i++)
211 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
212 break;
213 case IXGBE_RDH(0):
214 for (i = 0; i < 64; i++)
215 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
216 break;
217 case IXGBE_RDT(0):
218 for (i = 0; i < 64; i++)
219 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
220 break;
221 case IXGBE_RXDCTL(0):
222 for (i = 0; i < 64; i++)
223 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
224 break;
225 case IXGBE_RDBAL(0):
226 for (i = 0; i < 64; i++)
227 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
228 break;
229 case IXGBE_RDBAH(0):
230 for (i = 0; i < 64; i++)
231 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
232 break;
233 case IXGBE_TDBAL(0):
234 for (i = 0; i < 64; i++)
235 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
236 break;
237 case IXGBE_TDBAH(0):
238 for (i = 0; i < 64; i++)
239 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
240 break;
241 case IXGBE_TDLEN(0):
242 for (i = 0; i < 64; i++)
243 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
244 break;
245 case IXGBE_TDH(0):
246 for (i = 0; i < 64; i++)
247 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
248 break;
249 case IXGBE_TDT(0):
250 for (i = 0; i < 64; i++)
251 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
252 break;
253 case IXGBE_TXDCTL(0):
254 for (i = 0; i < 64; i++)
255 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
256 break;
257 default:
258 pr_info("%-15s %08x\n", reginfo->name,
259 IXGBE_READ_REG(hw, reginfo->ofs));
260 return;
261 }
262
263 for (i = 0; i < 8; i++) {
264 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
265 pr_err("%-15s", rname);
266 for (j = 0; j < 8; j++)
267 pr_cont(" %08x", regs[i*8+j]);
268 pr_cont("\n");
269 }
270
271 }
272
273 /*
274 * ixgbe_dump - Print registers, tx-rings and rx-rings
275 */
276 static void ixgbe_dump(struct ixgbe_adapter *adapter)
277 {
278 struct net_device *netdev = adapter->netdev;
279 struct ixgbe_hw *hw = &adapter->hw;
280 struct ixgbe_reg_info *reginfo;
281 int n = 0;
282 struct ixgbe_ring *tx_ring;
283 struct ixgbe_tx_buffer *tx_buffer_info;
284 union ixgbe_adv_tx_desc *tx_desc;
285 struct my_u0 { u64 a; u64 b; } *u0;
286 struct ixgbe_ring *rx_ring;
287 union ixgbe_adv_rx_desc *rx_desc;
288 struct ixgbe_rx_buffer *rx_buffer_info;
289 u32 staterr;
290 int i = 0;
291
292 if (!netif_msg_hw(adapter))
293 return;
294
295 /* Print netdevice Info */
296 if (netdev) {
297 dev_info(&adapter->pdev->dev, "Net device Info\n");
298 pr_info("Device Name state "
299 "trans_start last_rx\n");
300 pr_info("%-15s %016lX %016lX %016lX\n",
301 netdev->name,
302 netdev->state,
303 netdev->trans_start,
304 netdev->last_rx);
305 }
306
307 /* Print Registers */
308 dev_info(&adapter->pdev->dev, "Register Dump\n");
309 pr_info(" Register Name Value\n");
310 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
311 reginfo->name; reginfo++) {
312 ixgbe_regdump(hw, reginfo);
313 }
314
315 /* Print TX Ring Summary */
316 if (!netdev || !netif_running(netdev))
317 goto exit;
318
319 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
320 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
321 for (n = 0; n < adapter->num_tx_queues; n++) {
322 tx_ring = adapter->tx_ring[n];
323 tx_buffer_info =
324 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
325 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
326 n, tx_ring->next_to_use, tx_ring->next_to_clean,
327 (u64)tx_buffer_info->dma,
328 tx_buffer_info->length,
329 tx_buffer_info->next_to_watch,
330 (u64)tx_buffer_info->time_stamp);
331 }
332
333 /* Print TX Rings */
334 if (!netif_msg_tx_done(adapter))
335 goto rx_ring_summary;
336
337 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
338
339 /* Transmit Descriptor Formats
340 *
341 * Advanced Transmit Descriptor
342 * +--------------------------------------------------------------+
343 * 0 | Buffer Address [63:0] |
344 * +--------------------------------------------------------------+
345 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
346 * +--------------------------------------------------------------+
347 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
348 */
349
350 for (n = 0; n < adapter->num_tx_queues; n++) {
351 tx_ring = adapter->tx_ring[n];
352 pr_info("------------------------------------\n");
353 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
354 pr_info("------------------------------------\n");
355 pr_info("T [desc] [address 63:0 ] "
356 "[PlPOIdStDDt Ln] [bi->dma ] "
357 "leng ntw timestamp bi->skb\n");
358
359 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
360 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
361 tx_buffer_info = &tx_ring->tx_buffer_info[i];
362 u0 = (struct my_u0 *)tx_desc;
363 pr_info("T [0x%03X] %016llX %016llX %016llX"
364 " %04X %p %016llX %p", i,
365 le64_to_cpu(u0->a),
366 le64_to_cpu(u0->b),
367 (u64)tx_buffer_info->dma,
368 tx_buffer_info->length,
369 tx_buffer_info->next_to_watch,
370 (u64)tx_buffer_info->time_stamp,
371 tx_buffer_info->skb);
372 if (i == tx_ring->next_to_use &&
373 i == tx_ring->next_to_clean)
374 pr_cont(" NTC/U\n");
375 else if (i == tx_ring->next_to_use)
376 pr_cont(" NTU\n");
377 else if (i == tx_ring->next_to_clean)
378 pr_cont(" NTC\n");
379 else
380 pr_cont("\n");
381
382 if (netif_msg_pktdata(adapter) &&
383 tx_buffer_info->dma != 0)
384 print_hex_dump(KERN_INFO, "",
385 DUMP_PREFIX_ADDRESS, 16, 1,
386 phys_to_virt(tx_buffer_info->dma),
387 tx_buffer_info->length, true);
388 }
389 }
390
391 /* Print RX Rings Summary */
392 rx_ring_summary:
393 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
394 pr_info("Queue [NTU] [NTC]\n");
395 for (n = 0; n < adapter->num_rx_queues; n++) {
396 rx_ring = adapter->rx_ring[n];
397 pr_info("%5d %5X %5X\n",
398 n, rx_ring->next_to_use, rx_ring->next_to_clean);
399 }
400
401 /* Print RX Rings */
402 if (!netif_msg_rx_status(adapter))
403 goto exit;
404
405 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
406
407 /* Advanced Receive Descriptor (Read) Format
408 * 63 1 0
409 * +-----------------------------------------------------+
410 * 0 | Packet Buffer Address [63:1] |A0/NSE|
411 * +----------------------------------------------+------+
412 * 8 | Header Buffer Address [63:1] | DD |
413 * +-----------------------------------------------------+
414 *
415 *
416 * Advanced Receive Descriptor (Write-Back) Format
417 *
418 * 63 48 47 32 31 30 21 20 16 15 4 3 0
419 * +------------------------------------------------------+
420 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
421 * | Checksum Ident | | | | Type | Type |
422 * +------------------------------------------------------+
423 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
424 * +------------------------------------------------------+
425 * 63 48 47 32 31 20 19 0
426 */
427 for (n = 0; n < adapter->num_rx_queues; n++) {
428 rx_ring = adapter->rx_ring[n];
429 pr_info("------------------------------------\n");
430 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
431 pr_info("------------------------------------\n");
432 pr_info("R [desc] [ PktBuf A0] "
433 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
434 "<-- Adv Rx Read format\n");
435 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
436 "[vl er S cks ln] ---------------- [bi->skb] "
437 "<-- Adv Rx Write-Back format\n");
438
439 for (i = 0; i < rx_ring->count; i++) {
440 rx_buffer_info = &rx_ring->rx_buffer_info[i];
441 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
442 u0 = (struct my_u0 *)rx_desc;
443 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
444 if (staterr & IXGBE_RXD_STAT_DD) {
445 /* Descriptor Done */
446 pr_info("RWB[0x%03X] %016llX "
447 "%016llX ---------------- %p", i,
448 le64_to_cpu(u0->a),
449 le64_to_cpu(u0->b),
450 rx_buffer_info->skb);
451 } else {
452 pr_info("R [0x%03X] %016llX "
453 "%016llX %016llX %p", i,
454 le64_to_cpu(u0->a),
455 le64_to_cpu(u0->b),
456 (u64)rx_buffer_info->dma,
457 rx_buffer_info->skb);
458
459 if (netif_msg_pktdata(adapter)) {
460 print_hex_dump(KERN_INFO, "",
461 DUMP_PREFIX_ADDRESS, 16, 1,
462 phys_to_virt(rx_buffer_info->dma),
463 rx_ring->rx_buf_len, true);
464
465 if (rx_ring->rx_buf_len
466 < IXGBE_RXBUFFER_2K)
467 print_hex_dump(KERN_INFO, "",
468 DUMP_PREFIX_ADDRESS, 16, 1,
469 phys_to_virt(
470 rx_buffer_info->page_dma +
471 rx_buffer_info->page_offset
472 ),
473 PAGE_SIZE/2, true);
474 }
475 }
476
477 if (i == rx_ring->next_to_use)
478 pr_cont(" NTU\n");
479 else if (i == rx_ring->next_to_clean)
480 pr_cont(" NTC\n");
481 else
482 pr_cont("\n");
483
484 }
485 }
486
487 exit:
488 return;
489 }
490
491 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
492 {
493 u32 ctrl_ext;
494
495 /* Let firmware take over control of h/w */
496 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
497 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
498 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
499 }
500
501 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
502 {
503 u32 ctrl_ext;
504
505 /* Let firmware know the driver has taken over */
506 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
507 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
508 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
509 }
510
511 /*
512 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
513 * @adapter: pointer to adapter struct
514 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
515 * @queue: queue to map the corresponding interrupt to
516 * @msix_vector: the vector to map to the corresponding queue
517 *
518 */
519 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
520 u8 queue, u8 msix_vector)
521 {
522 u32 ivar, index;
523 struct ixgbe_hw *hw = &adapter->hw;
524 switch (hw->mac.type) {
525 case ixgbe_mac_82598EB:
526 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
527 if (direction == -1)
528 direction = 0;
529 index = (((direction * 64) + queue) >> 2) & 0x1F;
530 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
531 ivar &= ~(0xFF << (8 * (queue & 0x3)));
532 ivar |= (msix_vector << (8 * (queue & 0x3)));
533 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
534 break;
535 case ixgbe_mac_82599EB:
536 case ixgbe_mac_X540:
537 if (direction == -1) {
538 /* other causes */
539 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
540 index = ((queue & 1) * 8);
541 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
542 ivar &= ~(0xFF << index);
543 ivar |= (msix_vector << index);
544 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
545 break;
546 } else {
547 /* tx or rx causes */
548 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
549 index = ((16 * (queue & 1)) + (8 * direction));
550 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
551 ivar &= ~(0xFF << index);
552 ivar |= (msix_vector << index);
553 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
554 break;
555 }
556 default:
557 break;
558 }
559 }
560
561 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
562 u64 qmask)
563 {
564 u32 mask;
565
566 switch (adapter->hw.mac.type) {
567 case ixgbe_mac_82598EB:
568 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
569 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
570 break;
571 case ixgbe_mac_82599EB:
572 case ixgbe_mac_X540:
573 mask = (qmask & 0xFFFFFFFF);
574 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
575 mask = (qmask >> 32);
576 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
577 break;
578 default:
579 break;
580 }
581 }
582
583 static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
584 struct ixgbe_tx_buffer *tx_buffer)
585 {
586 if (tx_buffer->dma) {
587 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
588 dma_unmap_page(ring->dev,
589 tx_buffer->dma,
590 tx_buffer->length,
591 DMA_TO_DEVICE);
592 else
593 dma_unmap_single(ring->dev,
594 tx_buffer->dma,
595 tx_buffer->length,
596 DMA_TO_DEVICE);
597 }
598 tx_buffer->dma = 0;
599 }
600
601 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
602 struct ixgbe_tx_buffer *tx_buffer_info)
603 {
604 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
605 if (tx_buffer_info->skb)
606 dev_kfree_skb_any(tx_buffer_info->skb);
607 tx_buffer_info->skb = NULL;
608 /* tx_buffer_info must be completely set up in the transmit path */
609 }
610
611 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
612 {
613 struct ixgbe_hw *hw = &adapter->hw;
614 struct ixgbe_hw_stats *hwstats = &adapter->stats;
615 u32 data = 0;
616 u32 xoff[8] = {0};
617 int i;
618
619 if ((hw->fc.current_mode == ixgbe_fc_full) ||
620 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
621 switch (hw->mac.type) {
622 case ixgbe_mac_82598EB:
623 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
624 break;
625 default:
626 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
627 }
628 hwstats->lxoffrxc += data;
629
630 /* refill credits (no tx hang) if we received xoff */
631 if (!data)
632 return;
633
634 for (i = 0; i < adapter->num_tx_queues; i++)
635 clear_bit(__IXGBE_HANG_CHECK_ARMED,
636 &adapter->tx_ring[i]->state);
637 return;
638 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
639 return;
640
641 /* update stats for each tc, only valid with PFC enabled */
642 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
643 switch (hw->mac.type) {
644 case ixgbe_mac_82598EB:
645 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
646 break;
647 default:
648 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
649 }
650 hwstats->pxoffrxc[i] += xoff[i];
651 }
652
653 /* disarm tx queues that have received xoff frames */
654 for (i = 0; i < adapter->num_tx_queues; i++) {
655 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
656 u8 tc = tx_ring->dcb_tc;
657
658 if (xoff[tc])
659 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
660 }
661 }
662
663 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
664 {
665 return ring->tx_stats.completed;
666 }
667
668 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
669 {
670 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
671 struct ixgbe_hw *hw = &adapter->hw;
672
673 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
674 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
675
676 if (head != tail)
677 return (head < tail) ?
678 tail - head : (tail + ring->count - head);
679
680 return 0;
681 }
682
683 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
684 {
685 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
686 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
687 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
688 bool ret = false;
689
690 clear_check_for_tx_hang(tx_ring);
691
692 /*
693 * Check for a hung queue, but be thorough. This verifies
694 * that a transmit has been completed since the previous
695 * check AND there is at least one packet pending. The
696 * ARMED bit is set to indicate a potential hang. The
697 * bit is cleared if a pause frame is received to remove
698 * false hang detection due to PFC or 802.3x frames. By
699 * requiring this to fail twice we avoid races with
700 * pfc clearing the ARMED bit and conditions where we
701 * run the check_tx_hang logic with a transmit completion
702 * pending but without time to complete it yet.
703 */
704 if ((tx_done_old == tx_done) && tx_pending) {
705 /* make sure it is true for two checks in a row */
706 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
707 &tx_ring->state);
708 } else {
709 /* update completed stats and continue */
710 tx_ring->tx_stats.tx_done_old = tx_done;
711 /* reset the countdown */
712 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
713 }
714
715 return ret;
716 }
717
718 /**
719 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
720 * @adapter: driver private struct
721 **/
722 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
723 {
724
725 /* Do the reset outside of interrupt context */
726 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
727 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
728 ixgbe_service_event_schedule(adapter);
729 }
730 }
731
732 /**
733 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
734 * @q_vector: structure containing interrupt and ring information
735 * @tx_ring: tx ring to clean
736 **/
737 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
738 struct ixgbe_ring *tx_ring)
739 {
740 struct ixgbe_adapter *adapter = q_vector->adapter;
741 struct ixgbe_tx_buffer *tx_buffer;
742 union ixgbe_adv_tx_desc *tx_desc;
743 unsigned int total_bytes = 0, total_packets = 0;
744 unsigned int budget = q_vector->tx.work_limit;
745 u16 i = tx_ring->next_to_clean;
746
747 tx_buffer = &tx_ring->tx_buffer_info[i];
748 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
749
750 for (; budget; budget--) {
751 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
752
753 /* if next_to_watch is not set then there is no work pending */
754 if (!eop_desc)
755 break;
756
757 /* if DD is not set pending work has not been completed */
758 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
759 break;
760
761 /* count the packet as being completed */
762 tx_ring->tx_stats.completed++;
763
764 /* clear next_to_watch to prevent false hangs */
765 tx_buffer->next_to_watch = NULL;
766
767 /* prevent any other reads prior to eop_desc being verified */
768 rmb();
769
770 do {
771 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
772 tx_desc->wb.status = 0;
773 if (likely(tx_desc == eop_desc)) {
774 eop_desc = NULL;
775 dev_kfree_skb_any(tx_buffer->skb);
776 tx_buffer->skb = NULL;
777
778 total_bytes += tx_buffer->bytecount;
779 total_packets += tx_buffer->gso_segs;
780 }
781
782 tx_buffer++;
783 tx_desc++;
784 i++;
785 if (unlikely(i == tx_ring->count)) {
786 i = 0;
787
788 tx_buffer = tx_ring->tx_buffer_info;
789 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
790 }
791
792 } while (eop_desc);
793 }
794
795 tx_ring->next_to_clean = i;
796 u64_stats_update_begin(&tx_ring->syncp);
797 tx_ring->stats.bytes += total_bytes;
798 tx_ring->stats.packets += total_packets;
799 u64_stats_update_end(&tx_ring->syncp);
800 q_vector->tx.total_bytes += total_bytes;
801 q_vector->tx.total_packets += total_packets;
802
803 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
804 /* schedule immediate reset if we believe we hung */
805 struct ixgbe_hw *hw = &adapter->hw;
806 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
807 e_err(drv, "Detected Tx Unit Hang\n"
808 " Tx Queue <%d>\n"
809 " TDH, TDT <%x>, <%x>\n"
810 " next_to_use <%x>\n"
811 " next_to_clean <%x>\n"
812 "tx_buffer_info[next_to_clean]\n"
813 " time_stamp <%lx>\n"
814 " jiffies <%lx>\n",
815 tx_ring->queue_index,
816 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
817 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
818 tx_ring->next_to_use, i,
819 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
820
821 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
822
823 e_info(probe,
824 "tx hang %d detected on queue %d, resetting adapter\n",
825 adapter->tx_timeout_count + 1, tx_ring->queue_index);
826
827 /* schedule immediate reset if we believe we hung */
828 ixgbe_tx_timeout_reset(adapter);
829
830 /* the adapter is about to reset, no point in enabling stuff */
831 return true;
832 }
833
834 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
835 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
836 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
837 /* Make sure that anybody stopping the queue after this
838 * sees the new next_to_clean.
839 */
840 smp_mb();
841 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
842 !test_bit(__IXGBE_DOWN, &adapter->state)) {
843 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
844 ++tx_ring->tx_stats.restart_queue;
845 }
846 }
847
848 return !!budget;
849 }
850
851 #ifdef CONFIG_IXGBE_DCA
852 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
853 struct ixgbe_ring *rx_ring,
854 int cpu)
855 {
856 struct ixgbe_hw *hw = &adapter->hw;
857 u32 rxctrl;
858 u8 reg_idx = rx_ring->reg_idx;
859
860 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
861 switch (hw->mac.type) {
862 case ixgbe_mac_82598EB:
863 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
864 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
865 break;
866 case ixgbe_mac_82599EB:
867 case ixgbe_mac_X540:
868 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
869 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
870 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
871 break;
872 default:
873 break;
874 }
875 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
876 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
877 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
878 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
879 }
880
881 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
882 struct ixgbe_ring *tx_ring,
883 int cpu)
884 {
885 struct ixgbe_hw *hw = &adapter->hw;
886 u32 txctrl;
887 u8 reg_idx = tx_ring->reg_idx;
888
889 switch (hw->mac.type) {
890 case ixgbe_mac_82598EB:
891 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
892 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
893 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
894 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
895 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
896 break;
897 case ixgbe_mac_82599EB:
898 case ixgbe_mac_X540:
899 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
900 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
901 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
902 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
903 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
904 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
905 break;
906 default:
907 break;
908 }
909 }
910
911 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
912 {
913 struct ixgbe_adapter *adapter = q_vector->adapter;
914 struct ixgbe_ring *ring;
915 int cpu = get_cpu();
916
917 if (q_vector->cpu == cpu)
918 goto out_no_update;
919
920 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
921 ixgbe_update_tx_dca(adapter, ring, cpu);
922
923 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
924 ixgbe_update_rx_dca(adapter, ring, cpu);
925
926 q_vector->cpu = cpu;
927 out_no_update:
928 put_cpu();
929 }
930
931 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
932 {
933 int num_q_vectors;
934 int i;
935
936 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
937 return;
938
939 /* always use CB2 mode, difference is masked in the CB driver */
940 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
941
942 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
943 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
944 else
945 num_q_vectors = 1;
946
947 for (i = 0; i < num_q_vectors; i++) {
948 adapter->q_vector[i]->cpu = -1;
949 ixgbe_update_dca(adapter->q_vector[i]);
950 }
951 }
952
953 static int __ixgbe_notify_dca(struct device *dev, void *data)
954 {
955 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
956 unsigned long event = *(unsigned long *)data;
957
958 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
959 return 0;
960
961 switch (event) {
962 case DCA_PROVIDER_ADD:
963 /* if we're already enabled, don't do it again */
964 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
965 break;
966 if (dca_add_requester(dev) == 0) {
967 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
968 ixgbe_setup_dca(adapter);
969 break;
970 }
971 /* Fall Through since DCA is disabled. */
972 case DCA_PROVIDER_REMOVE:
973 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
974 dca_remove_requester(dev);
975 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
976 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
977 }
978 break;
979 }
980
981 return 0;
982 }
983 #endif /* CONFIG_IXGBE_DCA */
984
985 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
986 struct sk_buff *skb)
987 {
988 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
989 }
990
991 /**
992 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
993 * @adapter: address of board private structure
994 * @rx_desc: advanced rx descriptor
995 *
996 * Returns : true if it is FCoE pkt
997 */
998 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
999 union ixgbe_adv_rx_desc *rx_desc)
1000 {
1001 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1002
1003 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1004 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1005 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1006 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1007 }
1008
1009 /**
1010 * ixgbe_receive_skb - Send a completed packet up the stack
1011 * @adapter: board private structure
1012 * @skb: packet to send up
1013 * @status: hardware indication of status of receive
1014 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1015 * @rx_desc: rx descriptor
1016 **/
1017 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1018 struct sk_buff *skb, u8 status,
1019 struct ixgbe_ring *ring,
1020 union ixgbe_adv_rx_desc *rx_desc)
1021 {
1022 struct ixgbe_adapter *adapter = q_vector->adapter;
1023 struct napi_struct *napi = &q_vector->napi;
1024 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1025 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1026
1027 if (is_vlan && (tag & VLAN_VID_MASK))
1028 __vlan_hwaccel_put_tag(skb, tag);
1029
1030 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1031 napi_gro_receive(napi, skb);
1032 else
1033 netif_rx(skb);
1034 }
1035
1036 /**
1037 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1038 * @adapter: address of board private structure
1039 * @status_err: hardware indication of status of receive
1040 * @skb: skb currently being received and modified
1041 * @status_err: status error value of last descriptor in packet
1042 **/
1043 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1044 union ixgbe_adv_rx_desc *rx_desc,
1045 struct sk_buff *skb,
1046 u32 status_err)
1047 {
1048 skb->ip_summed = CHECKSUM_NONE;
1049
1050 /* Rx csum disabled */
1051 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1052 return;
1053
1054 /* if IP and error */
1055 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1056 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1057 adapter->hw_csum_rx_error++;
1058 return;
1059 }
1060
1061 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1062 return;
1063
1064 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1065 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1066
1067 /*
1068 * 82599 errata, UDP frames with a 0 checksum can be marked as
1069 * checksum errors.
1070 */
1071 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1072 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1073 return;
1074
1075 adapter->hw_csum_rx_error++;
1076 return;
1077 }
1078
1079 /* It must be a TCP or UDP packet with a valid checksum */
1080 skb->ip_summed = CHECKSUM_UNNECESSARY;
1081 }
1082
1083 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1084 {
1085 /*
1086 * Force memory writes to complete before letting h/w
1087 * know there are new descriptors to fetch. (Only
1088 * applicable for weak-ordered memory model archs,
1089 * such as IA-64).
1090 */
1091 wmb();
1092 writel(val, rx_ring->tail);
1093 }
1094
1095 /**
1096 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1097 * @rx_ring: ring to place buffers on
1098 * @cleaned_count: number of buffers to replace
1099 **/
1100 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1101 {
1102 union ixgbe_adv_rx_desc *rx_desc;
1103 struct ixgbe_rx_buffer *bi;
1104 struct sk_buff *skb;
1105 u16 i = rx_ring->next_to_use;
1106
1107 /* do nothing if no valid netdev defined */
1108 if (!rx_ring->netdev)
1109 return;
1110
1111 while (cleaned_count--) {
1112 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1113 bi = &rx_ring->rx_buffer_info[i];
1114 skb = bi->skb;
1115
1116 if (!skb) {
1117 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1118 rx_ring->rx_buf_len);
1119 if (!skb) {
1120 rx_ring->rx_stats.alloc_rx_buff_failed++;
1121 goto no_buffers;
1122 }
1123 /* initialize queue mapping */
1124 skb_record_rx_queue(skb, rx_ring->queue_index);
1125 bi->skb = skb;
1126 }
1127
1128 if (!bi->dma) {
1129 bi->dma = dma_map_single(rx_ring->dev,
1130 skb->data,
1131 rx_ring->rx_buf_len,
1132 DMA_FROM_DEVICE);
1133 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1134 rx_ring->rx_stats.alloc_rx_buff_failed++;
1135 bi->dma = 0;
1136 goto no_buffers;
1137 }
1138 }
1139
1140 if (ring_is_ps_enabled(rx_ring)) {
1141 if (!bi->page) {
1142 bi->page = netdev_alloc_page(rx_ring->netdev);
1143 if (!bi->page) {
1144 rx_ring->rx_stats.alloc_rx_page_failed++;
1145 goto no_buffers;
1146 }
1147 }
1148
1149 if (!bi->page_dma) {
1150 /* use a half page if we're re-using */
1151 bi->page_offset ^= PAGE_SIZE / 2;
1152 bi->page_dma = dma_map_page(rx_ring->dev,
1153 bi->page,
1154 bi->page_offset,
1155 PAGE_SIZE / 2,
1156 DMA_FROM_DEVICE);
1157 if (dma_mapping_error(rx_ring->dev,
1158 bi->page_dma)) {
1159 rx_ring->rx_stats.alloc_rx_page_failed++;
1160 bi->page_dma = 0;
1161 goto no_buffers;
1162 }
1163 }
1164
1165 /* Refresh the desc even if buffer_addrs didn't change
1166 * because each write-back erases this info. */
1167 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1168 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1169 } else {
1170 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1171 rx_desc->read.hdr_addr = 0;
1172 }
1173
1174 i++;
1175 if (i == rx_ring->count)
1176 i = 0;
1177 }
1178
1179 no_buffers:
1180 if (rx_ring->next_to_use != i) {
1181 rx_ring->next_to_use = i;
1182 ixgbe_release_rx_desc(rx_ring, i);
1183 }
1184 }
1185
1186 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1187 {
1188 /* HW will not DMA in data larger than the given buffer, even if it
1189 * parses the (NFS, of course) header to be larger. In that case, it
1190 * fills the header buffer and spills the rest into the page.
1191 */
1192 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1193 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1194 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1195 if (hlen > IXGBE_RX_HDR_SIZE)
1196 hlen = IXGBE_RX_HDR_SIZE;
1197 return hlen;
1198 }
1199
1200 /**
1201 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1202 * @skb: pointer to the last skb in the rsc queue
1203 *
1204 * This function changes a queue full of hw rsc buffers into a completed
1205 * packet. It uses the ->prev pointers to find the first packet and then
1206 * turns it into the frag list owner.
1207 **/
1208 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1209 {
1210 unsigned int frag_list_size = 0;
1211 unsigned int skb_cnt = 1;
1212
1213 while (skb->prev) {
1214 struct sk_buff *prev = skb->prev;
1215 frag_list_size += skb->len;
1216 skb->prev = NULL;
1217 skb = prev;
1218 skb_cnt++;
1219 }
1220
1221 skb_shinfo(skb)->frag_list = skb->next;
1222 skb->next = NULL;
1223 skb->len += frag_list_size;
1224 skb->data_len += frag_list_size;
1225 skb->truesize += frag_list_size;
1226 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1227
1228 return skb;
1229 }
1230
1231 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1232 {
1233 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1234 IXGBE_RXDADV_RSCCNT_MASK);
1235 }
1236
1237 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1238 struct ixgbe_ring *rx_ring,
1239 int budget)
1240 {
1241 struct ixgbe_adapter *adapter = q_vector->adapter;
1242 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1243 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1244 struct sk_buff *skb;
1245 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1246 const int current_node = numa_node_id();
1247 #ifdef IXGBE_FCOE
1248 int ddp_bytes = 0;
1249 #endif /* IXGBE_FCOE */
1250 u32 staterr;
1251 u16 i;
1252 u16 cleaned_count = 0;
1253 bool pkt_is_rsc = false;
1254
1255 i = rx_ring->next_to_clean;
1256 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1257 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1258
1259 while (staterr & IXGBE_RXD_STAT_DD) {
1260 u32 upper_len = 0;
1261
1262 rmb(); /* read descriptor and rx_buffer_info after status DD */
1263
1264 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1265
1266 skb = rx_buffer_info->skb;
1267 rx_buffer_info->skb = NULL;
1268 prefetch(skb->data);
1269
1270 if (ring_is_rsc_enabled(rx_ring))
1271 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1272
1273 /* linear means we are building an skb from multiple pages */
1274 if (!skb_is_nonlinear(skb)) {
1275 u16 hlen;
1276 if (pkt_is_rsc &&
1277 !(staterr & IXGBE_RXD_STAT_EOP) &&
1278 !skb->prev) {
1279 /*
1280 * When HWRSC is enabled, delay unmapping
1281 * of the first packet. It carries the
1282 * header information, HW may still
1283 * access the header after the writeback.
1284 * Only unmap it when EOP is reached
1285 */
1286 IXGBE_RSC_CB(skb)->delay_unmap = true;
1287 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1288 } else {
1289 dma_unmap_single(rx_ring->dev,
1290 rx_buffer_info->dma,
1291 rx_ring->rx_buf_len,
1292 DMA_FROM_DEVICE);
1293 }
1294 rx_buffer_info->dma = 0;
1295
1296 if (ring_is_ps_enabled(rx_ring)) {
1297 hlen = ixgbe_get_hlen(rx_desc);
1298 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1299 } else {
1300 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1301 }
1302
1303 skb_put(skb, hlen);
1304 } else {
1305 /* assume packet split since header is unmapped */
1306 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1307 }
1308
1309 if (upper_len) {
1310 dma_unmap_page(rx_ring->dev,
1311 rx_buffer_info->page_dma,
1312 PAGE_SIZE / 2,
1313 DMA_FROM_DEVICE);
1314 rx_buffer_info->page_dma = 0;
1315 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1316 rx_buffer_info->page,
1317 rx_buffer_info->page_offset,
1318 upper_len);
1319
1320 if ((page_count(rx_buffer_info->page) == 1) &&
1321 (page_to_nid(rx_buffer_info->page) == current_node))
1322 get_page(rx_buffer_info->page);
1323 else
1324 rx_buffer_info->page = NULL;
1325
1326 skb->len += upper_len;
1327 skb->data_len += upper_len;
1328 skb->truesize += upper_len;
1329 }
1330
1331 i++;
1332 if (i == rx_ring->count)
1333 i = 0;
1334
1335 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1336 prefetch(next_rxd);
1337 cleaned_count++;
1338
1339 if (pkt_is_rsc) {
1340 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1341 IXGBE_RXDADV_NEXTP_SHIFT;
1342 next_buffer = &rx_ring->rx_buffer_info[nextp];
1343 } else {
1344 next_buffer = &rx_ring->rx_buffer_info[i];
1345 }
1346
1347 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1348 if (ring_is_ps_enabled(rx_ring)) {
1349 rx_buffer_info->skb = next_buffer->skb;
1350 rx_buffer_info->dma = next_buffer->dma;
1351 next_buffer->skb = skb;
1352 next_buffer->dma = 0;
1353 } else {
1354 skb->next = next_buffer->skb;
1355 skb->next->prev = skb;
1356 }
1357 rx_ring->rx_stats.non_eop_descs++;
1358 goto next_desc;
1359 }
1360
1361 if (skb->prev) {
1362 skb = ixgbe_transform_rsc_queue(skb);
1363 /* if we got here without RSC the packet is invalid */
1364 if (!pkt_is_rsc) {
1365 __pskb_trim(skb, 0);
1366 rx_buffer_info->skb = skb;
1367 goto next_desc;
1368 }
1369 }
1370
1371 if (ring_is_rsc_enabled(rx_ring)) {
1372 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1373 dma_unmap_single(rx_ring->dev,
1374 IXGBE_RSC_CB(skb)->dma,
1375 rx_ring->rx_buf_len,
1376 DMA_FROM_DEVICE);
1377 IXGBE_RSC_CB(skb)->dma = 0;
1378 IXGBE_RSC_CB(skb)->delay_unmap = false;
1379 }
1380 }
1381 if (pkt_is_rsc) {
1382 if (ring_is_ps_enabled(rx_ring))
1383 rx_ring->rx_stats.rsc_count +=
1384 skb_shinfo(skb)->nr_frags;
1385 else
1386 rx_ring->rx_stats.rsc_count +=
1387 IXGBE_RSC_CB(skb)->skb_cnt;
1388 rx_ring->rx_stats.rsc_flush++;
1389 }
1390
1391 /* ERR_MASK will only have valid bits if EOP set */
1392 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1393 dev_kfree_skb_any(skb);
1394 goto next_desc;
1395 }
1396
1397 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
1398 if (adapter->netdev->features & NETIF_F_RXHASH)
1399 ixgbe_rx_hash(rx_desc, skb);
1400
1401 /* probably a little skewed due to removing CRC */
1402 total_rx_bytes += skb->len;
1403 total_rx_packets++;
1404
1405 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1406 #ifdef IXGBE_FCOE
1407 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1408 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1409 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1410 staterr);
1411 if (!ddp_bytes) {
1412 dev_kfree_skb_any(skb);
1413 goto next_desc;
1414 }
1415 }
1416 #endif /* IXGBE_FCOE */
1417 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1418
1419 budget--;
1420 next_desc:
1421 rx_desc->wb.upper.status_error = 0;
1422
1423 if (!budget)
1424 break;
1425
1426 /* return some buffers to hardware, one at a time is too slow */
1427 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1428 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1429 cleaned_count = 0;
1430 }
1431
1432 /* use prefetched values */
1433 rx_desc = next_rxd;
1434 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1435 }
1436
1437 rx_ring->next_to_clean = i;
1438 cleaned_count = ixgbe_desc_unused(rx_ring);
1439
1440 if (cleaned_count)
1441 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1442
1443 #ifdef IXGBE_FCOE
1444 /* include DDPed FCoE data */
1445 if (ddp_bytes > 0) {
1446 unsigned int mss;
1447
1448 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1449 sizeof(struct fc_frame_header) -
1450 sizeof(struct fcoe_crc_eof);
1451 if (mss > 512)
1452 mss &= ~511;
1453 total_rx_bytes += ddp_bytes;
1454 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1455 }
1456 #endif /* IXGBE_FCOE */
1457
1458 u64_stats_update_begin(&rx_ring->syncp);
1459 rx_ring->stats.packets += total_rx_packets;
1460 rx_ring->stats.bytes += total_rx_bytes;
1461 u64_stats_update_end(&rx_ring->syncp);
1462 q_vector->rx.total_packets += total_rx_packets;
1463 q_vector->rx.total_bytes += total_rx_bytes;
1464
1465 return !!budget;
1466 }
1467
1468 /**
1469 * ixgbe_configure_msix - Configure MSI-X hardware
1470 * @adapter: board private structure
1471 *
1472 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1473 * interrupts.
1474 **/
1475 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1476 {
1477 struct ixgbe_q_vector *q_vector;
1478 int q_vectors, v_idx;
1479 u32 mask;
1480
1481 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1482
1483 /* Populate MSIX to EITR Select */
1484 if (adapter->num_vfs > 32) {
1485 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1486 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1487 }
1488
1489 /*
1490 * Populate the IVAR table and set the ITR values to the
1491 * corresponding register.
1492 */
1493 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1494 struct ixgbe_ring *ring;
1495 q_vector = adapter->q_vector[v_idx];
1496
1497 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1498 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1499
1500 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1501 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1502
1503 if (q_vector->tx.ring && !q_vector->rx.ring) {
1504 /* tx only vector */
1505 if (adapter->tx_itr_setting == 1)
1506 q_vector->itr = IXGBE_10K_ITR;
1507 else
1508 q_vector->itr = adapter->tx_itr_setting;
1509 } else {
1510 /* rx or rx/tx vector */
1511 if (adapter->rx_itr_setting == 1)
1512 q_vector->itr = IXGBE_20K_ITR;
1513 else
1514 q_vector->itr = adapter->rx_itr_setting;
1515 }
1516
1517 ixgbe_write_eitr(q_vector);
1518 }
1519
1520 switch (adapter->hw.mac.type) {
1521 case ixgbe_mac_82598EB:
1522 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1523 v_idx);
1524 break;
1525 case ixgbe_mac_82599EB:
1526 case ixgbe_mac_X540:
1527 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1528 break;
1529 default:
1530 break;
1531 }
1532 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1533
1534 /* set up to autoclear timer, and the vectors */
1535 mask = IXGBE_EIMS_ENABLE_MASK;
1536 mask &= ~(IXGBE_EIMS_OTHER |
1537 IXGBE_EIMS_MAILBOX |
1538 IXGBE_EIMS_LSC);
1539
1540 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1541 }
1542
1543 enum latency_range {
1544 lowest_latency = 0,
1545 low_latency = 1,
1546 bulk_latency = 2,
1547 latency_invalid = 255
1548 };
1549
1550 /**
1551 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1552 * @q_vector: structure containing interrupt and ring information
1553 * @ring_container: structure containing ring performance data
1554 *
1555 * Stores a new ITR value based on packets and byte
1556 * counts during the last interrupt. The advantage of per interrupt
1557 * computation is faster updates and more accurate ITR for the current
1558 * traffic pattern. Constants in this function were computed
1559 * based on theoretical maximum wire speed and thresholds were set based
1560 * on testing data as well as attempting to minimize response time
1561 * while increasing bulk throughput.
1562 * this functionality is controlled by the InterruptThrottleRate module
1563 * parameter (see ixgbe_param.c)
1564 **/
1565 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1566 struct ixgbe_ring_container *ring_container)
1567 {
1568 u64 bytes_perint;
1569 struct ixgbe_adapter *adapter = q_vector->adapter;
1570 int bytes = ring_container->total_bytes;
1571 int packets = ring_container->total_packets;
1572 u32 timepassed_us;
1573 u8 itr_setting = ring_container->itr;
1574
1575 if (packets == 0)
1576 return;
1577
1578 /* simple throttlerate management
1579 * 0-20MB/s lowest (100000 ints/s)
1580 * 20-100MB/s low (20000 ints/s)
1581 * 100-1249MB/s bulk (8000 ints/s)
1582 */
1583 /* what was last interrupt timeslice? */
1584 timepassed_us = q_vector->itr >> 2;
1585 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1586
1587 switch (itr_setting) {
1588 case lowest_latency:
1589 if (bytes_perint > adapter->eitr_low)
1590 itr_setting = low_latency;
1591 break;
1592 case low_latency:
1593 if (bytes_perint > adapter->eitr_high)
1594 itr_setting = bulk_latency;
1595 else if (bytes_perint <= adapter->eitr_low)
1596 itr_setting = lowest_latency;
1597 break;
1598 case bulk_latency:
1599 if (bytes_perint <= adapter->eitr_high)
1600 itr_setting = low_latency;
1601 break;
1602 }
1603
1604 /* clear work counters since we have the values we need */
1605 ring_container->total_bytes = 0;
1606 ring_container->total_packets = 0;
1607
1608 /* write updated itr to ring container */
1609 ring_container->itr = itr_setting;
1610 }
1611
1612 /**
1613 * ixgbe_write_eitr - write EITR register in hardware specific way
1614 * @q_vector: structure containing interrupt and ring information
1615 *
1616 * This function is made to be called by ethtool and by the driver
1617 * when it needs to update EITR registers at runtime. Hardware
1618 * specific quirks/differences are taken care of here.
1619 */
1620 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1621 {
1622 struct ixgbe_adapter *adapter = q_vector->adapter;
1623 struct ixgbe_hw *hw = &adapter->hw;
1624 int v_idx = q_vector->v_idx;
1625 u32 itr_reg = q_vector->itr;
1626
1627 switch (adapter->hw.mac.type) {
1628 case ixgbe_mac_82598EB:
1629 /* must write high and low 16 bits to reset counter */
1630 itr_reg |= (itr_reg << 16);
1631 break;
1632 case ixgbe_mac_82599EB:
1633 case ixgbe_mac_X540:
1634 /*
1635 * set the WDIS bit to not clear the timer bits and cause an
1636 * immediate assertion of the interrupt
1637 */
1638 itr_reg |= IXGBE_EITR_CNT_WDIS;
1639 break;
1640 default:
1641 break;
1642 }
1643 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1644 }
1645
1646 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1647 {
1648 u32 new_itr = q_vector->itr;
1649 u8 current_itr;
1650
1651 ixgbe_update_itr(q_vector, &q_vector->tx);
1652 ixgbe_update_itr(q_vector, &q_vector->rx);
1653
1654 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1655
1656 switch (current_itr) {
1657 /* counts and packets in update_itr are dependent on these numbers */
1658 case lowest_latency:
1659 new_itr = IXGBE_100K_ITR;
1660 break;
1661 case low_latency:
1662 new_itr = IXGBE_20K_ITR;
1663 break;
1664 case bulk_latency:
1665 new_itr = IXGBE_8K_ITR;
1666 break;
1667 default:
1668 break;
1669 }
1670
1671 if (new_itr != q_vector->itr) {
1672 /* do an exponential smoothing */
1673 new_itr = (10 * new_itr * q_vector->itr) /
1674 ((9 * new_itr) + q_vector->itr);
1675
1676 /* save the algorithm value here */
1677 q_vector->itr = new_itr & IXGBE_MAX_EITR;
1678
1679 ixgbe_write_eitr(q_vector);
1680 }
1681 }
1682
1683 /**
1684 * ixgbe_check_overtemp_subtask - check for over tempurature
1685 * @adapter: pointer to adapter
1686 **/
1687 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1688 {
1689 struct ixgbe_hw *hw = &adapter->hw;
1690 u32 eicr = adapter->interrupt_event;
1691
1692 if (test_bit(__IXGBE_DOWN, &adapter->state))
1693 return;
1694
1695 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1696 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1697 return;
1698
1699 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1700
1701 switch (hw->device_id) {
1702 case IXGBE_DEV_ID_82599_T3_LOM:
1703 /*
1704 * Since the warning interrupt is for both ports
1705 * we don't have to check if:
1706 * - This interrupt wasn't for our port.
1707 * - We may have missed the interrupt so always have to
1708 * check if we got a LSC
1709 */
1710 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1711 !(eicr & IXGBE_EICR_LSC))
1712 return;
1713
1714 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1715 u32 autoneg;
1716 bool link_up = false;
1717
1718 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1719
1720 if (link_up)
1721 return;
1722 }
1723
1724 /* Check if this is not due to overtemp */
1725 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1726 return;
1727
1728 break;
1729 default:
1730 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1731 return;
1732 break;
1733 }
1734 e_crit(drv,
1735 "Network adapter has been stopped because it has over heated. "
1736 "Restart the computer. If the problem persists, "
1737 "power off the system and replace the adapter\n");
1738
1739 adapter->interrupt_event = 0;
1740 }
1741
1742 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1743 {
1744 struct ixgbe_hw *hw = &adapter->hw;
1745
1746 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1747 (eicr & IXGBE_EICR_GPI_SDP1)) {
1748 e_crit(probe, "Fan has stopped, replace the adapter\n");
1749 /* write to clear the interrupt */
1750 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1751 }
1752 }
1753
1754 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1755 {
1756 struct ixgbe_hw *hw = &adapter->hw;
1757
1758 if (eicr & IXGBE_EICR_GPI_SDP2) {
1759 /* Clear the interrupt */
1760 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1761 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1762 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1763 ixgbe_service_event_schedule(adapter);
1764 }
1765 }
1766
1767 if (eicr & IXGBE_EICR_GPI_SDP1) {
1768 /* Clear the interrupt */
1769 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1770 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1771 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1772 ixgbe_service_event_schedule(adapter);
1773 }
1774 }
1775 }
1776
1777 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1778 {
1779 struct ixgbe_hw *hw = &adapter->hw;
1780
1781 adapter->lsc_int++;
1782 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1783 adapter->link_check_timeout = jiffies;
1784 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1785 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1786 IXGBE_WRITE_FLUSH(hw);
1787 ixgbe_service_event_schedule(adapter);
1788 }
1789 }
1790
1791 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1792 u64 qmask)
1793 {
1794 u32 mask;
1795 struct ixgbe_hw *hw = &adapter->hw;
1796
1797 switch (hw->mac.type) {
1798 case ixgbe_mac_82598EB:
1799 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1800 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1801 break;
1802 case ixgbe_mac_82599EB:
1803 case ixgbe_mac_X540:
1804 mask = (qmask & 0xFFFFFFFF);
1805 if (mask)
1806 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1807 mask = (qmask >> 32);
1808 if (mask)
1809 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1810 break;
1811 default:
1812 break;
1813 }
1814 /* skip the flush */
1815 }
1816
1817 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1818 u64 qmask)
1819 {
1820 u32 mask;
1821 struct ixgbe_hw *hw = &adapter->hw;
1822
1823 switch (hw->mac.type) {
1824 case ixgbe_mac_82598EB:
1825 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1826 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1827 break;
1828 case ixgbe_mac_82599EB:
1829 case ixgbe_mac_X540:
1830 mask = (qmask & 0xFFFFFFFF);
1831 if (mask)
1832 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1833 mask = (qmask >> 32);
1834 if (mask)
1835 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1836 break;
1837 default:
1838 break;
1839 }
1840 /* skip the flush */
1841 }
1842
1843 /**
1844 * ixgbe_irq_enable - Enable default interrupt generation settings
1845 * @adapter: board private structure
1846 **/
1847 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
1848 bool flush)
1849 {
1850 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1851
1852 /* don't reenable LSC while waiting for link */
1853 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
1854 mask &= ~IXGBE_EIMS_LSC;
1855
1856 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
1857 mask |= IXGBE_EIMS_GPI_SDP0;
1858 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1859 mask |= IXGBE_EIMS_GPI_SDP1;
1860 switch (adapter->hw.mac.type) {
1861 case ixgbe_mac_82599EB:
1862 mask |= IXGBE_EIMS_GPI_SDP1;
1863 mask |= IXGBE_EIMS_GPI_SDP2;
1864 case ixgbe_mac_X540:
1865 mask |= IXGBE_EIMS_ECC;
1866 mask |= IXGBE_EIMS_MAILBOX;
1867 break;
1868 default:
1869 break;
1870 }
1871 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
1872 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
1873 mask |= IXGBE_EIMS_FLOW_DIR;
1874
1875 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1876 if (queues)
1877 ixgbe_irq_enable_queues(adapter, ~0);
1878 if (flush)
1879 IXGBE_WRITE_FLUSH(&adapter->hw);
1880 }
1881
1882 static irqreturn_t ixgbe_msix_other(int irq, void *data)
1883 {
1884 struct ixgbe_adapter *adapter = data;
1885 struct ixgbe_hw *hw = &adapter->hw;
1886 u32 eicr;
1887
1888 /*
1889 * Workaround for Silicon errata. Use clear-by-write instead
1890 * of clear-by-read. Reading with EICS will return the
1891 * interrupt causes without clearing, which later be done
1892 * with the write to EICR.
1893 */
1894 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1895 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1896
1897 if (eicr & IXGBE_EICR_LSC)
1898 ixgbe_check_lsc(adapter);
1899
1900 if (eicr & IXGBE_EICR_MAILBOX)
1901 ixgbe_msg_task(adapter);
1902
1903 switch (hw->mac.type) {
1904 case ixgbe_mac_82599EB:
1905 case ixgbe_mac_X540:
1906 if (eicr & IXGBE_EICR_ECC)
1907 e_info(link, "Received unrecoverable ECC Err, please "
1908 "reboot\n");
1909 /* Handle Flow Director Full threshold interrupt */
1910 if (eicr & IXGBE_EICR_FLOW_DIR) {
1911 int reinit_count = 0;
1912 int i;
1913 for (i = 0; i < adapter->num_tx_queues; i++) {
1914 struct ixgbe_ring *ring = adapter->tx_ring[i];
1915 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1916 &ring->state))
1917 reinit_count++;
1918 }
1919 if (reinit_count) {
1920 /* no more flow director interrupts until after init */
1921 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1922 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1923 ixgbe_service_event_schedule(adapter);
1924 }
1925 }
1926 ixgbe_check_sfp_event(adapter, eicr);
1927 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1928 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1929 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1930 adapter->interrupt_event = eicr;
1931 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1932 ixgbe_service_event_schedule(adapter);
1933 }
1934 }
1935 break;
1936 default:
1937 break;
1938 }
1939
1940 ixgbe_check_fan_failure(adapter, eicr);
1941
1942 /* re-enable the original interrupt state, no lsc, no queues */
1943 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1944 ixgbe_irq_enable(adapter, false, false);
1945
1946 return IRQ_HANDLED;
1947 }
1948
1949 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
1950 {
1951 struct ixgbe_q_vector *q_vector = data;
1952
1953 /* EIAM disabled interrupts (on this vector) for us */
1954
1955 if (q_vector->rx.ring || q_vector->tx.ring)
1956 napi_schedule(&q_vector->napi);
1957
1958 return IRQ_HANDLED;
1959 }
1960
1961 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1962 int r_idx)
1963 {
1964 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1965 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
1966
1967 rx_ring->q_vector = q_vector;
1968 rx_ring->next = q_vector->rx.ring;
1969 q_vector->rx.ring = rx_ring;
1970 q_vector->rx.count++;
1971 }
1972
1973 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1974 int t_idx)
1975 {
1976 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1977 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
1978
1979 tx_ring->q_vector = q_vector;
1980 tx_ring->next = q_vector->tx.ring;
1981 q_vector->tx.ring = tx_ring;
1982 q_vector->tx.count++;
1983 q_vector->tx.work_limit = a->tx_work_limit;
1984 }
1985
1986 /**
1987 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1988 * @adapter: board private structure to initialize
1989 *
1990 * This function maps descriptor rings to the queue-specific vectors
1991 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1992 * one vector per ring/queue, but on a constrained vector budget, we
1993 * group the rings as "efficiently" as possible. You would add new
1994 * mapping configurations in here.
1995 **/
1996 static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
1997 {
1998 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1999 int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2000 int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
2001 int v_start = 0;
2002
2003 /* only one q_vector if MSI-X is disabled. */
2004 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2005 q_vectors = 1;
2006
2007 /*
2008 * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2009 * group them so there are multiple queues per vector.
2010 *
2011 * Re-adjusting *qpv takes care of the remainder.
2012 */
2013 for (; v_start < q_vectors && rxr_remaining; v_start++) {
2014 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2015 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
2016 map_vector_to_rxq(adapter, v_start, rxr_idx);
2017 }
2018
2019 /*
2020 * If there are not enough q_vectors for each ring to have it's own
2021 * vector then we must pair up Rx/Tx on a each vector
2022 */
2023 if ((v_start + txr_remaining) > q_vectors)
2024 v_start = 0;
2025
2026 for (; v_start < q_vectors && txr_remaining; v_start++) {
2027 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2028 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2029 map_vector_to_txq(adapter, v_start, txr_idx);
2030 }
2031 }
2032
2033 /**
2034 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2035 * @adapter: board private structure
2036 *
2037 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2038 * interrupts from the kernel.
2039 **/
2040 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2041 {
2042 struct net_device *netdev = adapter->netdev;
2043 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2044 int vector, err;
2045 int ri = 0, ti = 0;
2046
2047 for (vector = 0; vector < q_vectors; vector++) {
2048 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2049 struct msix_entry *entry = &adapter->msix_entries[vector];
2050
2051 if (q_vector->tx.ring && q_vector->rx.ring) {
2052 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2053 "%s-%s-%d", netdev->name, "TxRx", ri++);
2054 ti++;
2055 } else if (q_vector->rx.ring) {
2056 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2057 "%s-%s-%d", netdev->name, "rx", ri++);
2058 } else if (q_vector->tx.ring) {
2059 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2060 "%s-%s-%d", netdev->name, "tx", ti++);
2061 } else {
2062 /* skip this unused q_vector */
2063 continue;
2064 }
2065 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2066 q_vector->name, q_vector);
2067 if (err) {
2068 e_err(probe, "request_irq failed for MSIX interrupt "
2069 "Error: %d\n", err);
2070 goto free_queue_irqs;
2071 }
2072 /* If Flow Director is enabled, set interrupt affinity */
2073 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2074 /* assign the mask for this irq */
2075 irq_set_affinity_hint(entry->vector,
2076 q_vector->affinity_mask);
2077 }
2078 }
2079
2080 err = request_irq(adapter->msix_entries[vector].vector,
2081 ixgbe_msix_other, 0, netdev->name, adapter);
2082 if (err) {
2083 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2084 goto free_queue_irqs;
2085 }
2086
2087 return 0;
2088
2089 free_queue_irqs:
2090 while (vector) {
2091 vector--;
2092 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2093 NULL);
2094 free_irq(adapter->msix_entries[vector].vector,
2095 adapter->q_vector[vector]);
2096 }
2097 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2098 pci_disable_msix(adapter->pdev);
2099 kfree(adapter->msix_entries);
2100 adapter->msix_entries = NULL;
2101 return err;
2102 }
2103
2104 /**
2105 * ixgbe_intr - legacy mode Interrupt Handler
2106 * @irq: interrupt number
2107 * @data: pointer to a network interface device structure
2108 **/
2109 static irqreturn_t ixgbe_intr(int irq, void *data)
2110 {
2111 struct ixgbe_adapter *adapter = data;
2112 struct ixgbe_hw *hw = &adapter->hw;
2113 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2114 u32 eicr;
2115
2116 /*
2117 * Workaround for silicon errata on 82598. Mask the interrupts
2118 * before the read of EICR.
2119 */
2120 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2121
2122 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2123 * therefore no explict interrupt disable is necessary */
2124 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2125 if (!eicr) {
2126 /*
2127 * shared interrupt alert!
2128 * make sure interrupts are enabled because the read will
2129 * have disabled interrupts due to EIAM
2130 * finish the workaround of silicon errata on 82598. Unmask
2131 * the interrupt that we masked before the EICR read.
2132 */
2133 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2134 ixgbe_irq_enable(adapter, true, true);
2135 return IRQ_NONE; /* Not our interrupt */
2136 }
2137
2138 if (eicr & IXGBE_EICR_LSC)
2139 ixgbe_check_lsc(adapter);
2140
2141 switch (hw->mac.type) {
2142 case ixgbe_mac_82599EB:
2143 ixgbe_check_sfp_event(adapter, eicr);
2144 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2145 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2146 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2147 adapter->interrupt_event = eicr;
2148 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2149 ixgbe_service_event_schedule(adapter);
2150 }
2151 }
2152 break;
2153 default:
2154 break;
2155 }
2156
2157 ixgbe_check_fan_failure(adapter, eicr);
2158
2159 if (napi_schedule_prep(&(q_vector->napi))) {
2160 /* would disable interrupts here but EIAM disabled it */
2161 __napi_schedule(&(q_vector->napi));
2162 }
2163
2164 /*
2165 * re-enable link(maybe) and non-queue interrupts, no flush.
2166 * ixgbe_poll will re-enable the queue interrupts
2167 */
2168
2169 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2170 ixgbe_irq_enable(adapter, false, false);
2171
2172 return IRQ_HANDLED;
2173 }
2174
2175 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2176 {
2177 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2178 int i;
2179
2180 /* legacy and MSI only use one vector */
2181 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2182 q_vectors = 1;
2183
2184 for (i = 0; i < adapter->num_rx_queues; i++) {
2185 adapter->rx_ring[i]->q_vector = NULL;
2186 adapter->rx_ring[i]->next = NULL;
2187 }
2188 for (i = 0; i < adapter->num_tx_queues; i++) {
2189 adapter->tx_ring[i]->q_vector = NULL;
2190 adapter->tx_ring[i]->next = NULL;
2191 }
2192
2193 for (i = 0; i < q_vectors; i++) {
2194 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2195 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2196 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
2197 }
2198 }
2199
2200 /**
2201 * ixgbe_request_irq - initialize interrupts
2202 * @adapter: board private structure
2203 *
2204 * Attempts to configure interrupts using the best available
2205 * capabilities of the hardware and kernel.
2206 **/
2207 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2208 {
2209 struct net_device *netdev = adapter->netdev;
2210 int err;
2211
2212 /* map all of the rings to the q_vectors */
2213 ixgbe_map_rings_to_vectors(adapter);
2214
2215 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2216 err = ixgbe_request_msix_irqs(adapter);
2217 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2218 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2219 netdev->name, adapter);
2220 else
2221 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2222 netdev->name, adapter);
2223
2224 if (err) {
2225 e_err(probe, "request_irq failed, Error %d\n", err);
2226
2227 /* place q_vectors and rings back into a known good state */
2228 ixgbe_reset_q_vectors(adapter);
2229 }
2230
2231 return err;
2232 }
2233
2234 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2235 {
2236 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2237 int i, q_vectors;
2238
2239 q_vectors = adapter->num_msix_vectors;
2240 i = q_vectors - 1;
2241 free_irq(adapter->msix_entries[i].vector, adapter);
2242 i--;
2243
2244 for (; i >= 0; i--) {
2245 /* free only the irqs that were actually requested */
2246 if (!adapter->q_vector[i]->rx.ring &&
2247 !adapter->q_vector[i]->tx.ring)
2248 continue;
2249
2250 /* clear the affinity_mask in the IRQ descriptor */
2251 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2252 NULL);
2253
2254 free_irq(adapter->msix_entries[i].vector,
2255 adapter->q_vector[i]);
2256 }
2257 } else {
2258 free_irq(adapter->pdev->irq, adapter);
2259 }
2260
2261 /* clear q_vector state information */
2262 ixgbe_reset_q_vectors(adapter);
2263 }
2264
2265 /**
2266 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2267 * @adapter: board private structure
2268 **/
2269 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2270 {
2271 switch (adapter->hw.mac.type) {
2272 case ixgbe_mac_82598EB:
2273 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2274 break;
2275 case ixgbe_mac_82599EB:
2276 case ixgbe_mac_X540:
2277 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2278 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2279 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2280 break;
2281 default:
2282 break;
2283 }
2284 IXGBE_WRITE_FLUSH(&adapter->hw);
2285 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2286 int i;
2287 for (i = 0; i < adapter->num_msix_vectors; i++)
2288 synchronize_irq(adapter->msix_entries[i].vector);
2289 } else {
2290 synchronize_irq(adapter->pdev->irq);
2291 }
2292 }
2293
2294 /**
2295 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2296 *
2297 **/
2298 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2299 {
2300 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2301
2302 /* rx/tx vector */
2303 if (adapter->rx_itr_setting == 1)
2304 q_vector->itr = IXGBE_20K_ITR;
2305 else
2306 q_vector->itr = adapter->rx_itr_setting;
2307
2308 ixgbe_write_eitr(q_vector);
2309
2310 ixgbe_set_ivar(adapter, 0, 0, 0);
2311 ixgbe_set_ivar(adapter, 1, 0, 0);
2312
2313 e_info(hw, "Legacy interrupt IVAR setup done\n");
2314 }
2315
2316 /**
2317 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2318 * @adapter: board private structure
2319 * @ring: structure containing ring specific data
2320 *
2321 * Configure the Tx descriptor ring after a reset.
2322 **/
2323 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2324 struct ixgbe_ring *ring)
2325 {
2326 struct ixgbe_hw *hw = &adapter->hw;
2327 u64 tdba = ring->dma;
2328 int wait_loop = 10;
2329 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2330 u8 reg_idx = ring->reg_idx;
2331
2332 /* disable queue to avoid issues while updating state */
2333 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2334 IXGBE_WRITE_FLUSH(hw);
2335
2336 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2337 (tdba & DMA_BIT_MASK(32)));
2338 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2339 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2340 ring->count * sizeof(union ixgbe_adv_tx_desc));
2341 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2342 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2343 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2344
2345 /*
2346 * set WTHRESH to encourage burst writeback, it should not be set
2347 * higher than 1 when ITR is 0 as it could cause false TX hangs
2348 *
2349 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2350 * to or less than the number of on chip descriptors, which is
2351 * currently 40.
2352 */
2353 if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
2354 txdctl |= (1 << 16); /* WTHRESH = 1 */
2355 else
2356 txdctl |= (8 << 16); /* WTHRESH = 8 */
2357
2358 /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2359 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2360 32; /* PTHRESH = 32 */
2361
2362 /* reinitialize flowdirector state */
2363 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2364 adapter->atr_sample_rate) {
2365 ring->atr_sample_rate = adapter->atr_sample_rate;
2366 ring->atr_count = 0;
2367 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2368 } else {
2369 ring->atr_sample_rate = 0;
2370 }
2371
2372 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2373
2374 /* enable queue */
2375 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2376
2377 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2378 if (hw->mac.type == ixgbe_mac_82598EB &&
2379 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2380 return;
2381
2382 /* poll to verify queue is enabled */
2383 do {
2384 usleep_range(1000, 2000);
2385 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2386 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2387 if (!wait_loop)
2388 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2389 }
2390
2391 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2392 {
2393 struct ixgbe_hw *hw = &adapter->hw;
2394 u32 rttdcs;
2395 u32 reg;
2396 u8 tcs = netdev_get_num_tc(adapter->netdev);
2397
2398 if (hw->mac.type == ixgbe_mac_82598EB)
2399 return;
2400
2401 /* disable the arbiter while setting MTQC */
2402 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2403 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2404 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2405
2406 /* set transmit pool layout */
2407 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2408 case (IXGBE_FLAG_SRIOV_ENABLED):
2409 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2410 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2411 break;
2412 default:
2413 if (!tcs)
2414 reg = IXGBE_MTQC_64Q_1PB;
2415 else if (tcs <= 4)
2416 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2417 else
2418 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2419
2420 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2421
2422 /* Enable Security TX Buffer IFG for multiple pb */
2423 if (tcs) {
2424 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2425 reg |= IXGBE_SECTX_DCB;
2426 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2427 }
2428 break;
2429 }
2430
2431 /* re-enable the arbiter */
2432 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2433 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2434 }
2435
2436 /**
2437 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2438 * @adapter: board private structure
2439 *
2440 * Configure the Tx unit of the MAC after a reset.
2441 **/
2442 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2443 {
2444 struct ixgbe_hw *hw = &adapter->hw;
2445 u32 dmatxctl;
2446 u32 i;
2447
2448 ixgbe_setup_mtqc(adapter);
2449
2450 if (hw->mac.type != ixgbe_mac_82598EB) {
2451 /* DMATXCTL.EN must be before Tx queues are enabled */
2452 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2453 dmatxctl |= IXGBE_DMATXCTL_TE;
2454 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2455 }
2456
2457 /* Setup the HW Tx Head and Tail descriptor pointers */
2458 for (i = 0; i < adapter->num_tx_queues; i++)
2459 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2460 }
2461
2462 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2463
2464 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2465 struct ixgbe_ring *rx_ring)
2466 {
2467 u32 srrctl;
2468 u8 reg_idx = rx_ring->reg_idx;
2469
2470 switch (adapter->hw.mac.type) {
2471 case ixgbe_mac_82598EB: {
2472 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2473 const int mask = feature[RING_F_RSS].mask;
2474 reg_idx = reg_idx & mask;
2475 }
2476 break;
2477 case ixgbe_mac_82599EB:
2478 case ixgbe_mac_X540:
2479 default:
2480 break;
2481 }
2482
2483 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2484
2485 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2486 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2487 if (adapter->num_vfs)
2488 srrctl |= IXGBE_SRRCTL_DROP_EN;
2489
2490 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2491 IXGBE_SRRCTL_BSIZEHDR_MASK;
2492
2493 if (ring_is_ps_enabled(rx_ring)) {
2494 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2495 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2496 #else
2497 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2498 #endif
2499 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2500 } else {
2501 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2502 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2503 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2504 }
2505
2506 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2507 }
2508
2509 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2510 {
2511 struct ixgbe_hw *hw = &adapter->hw;
2512 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2513 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2514 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2515 u32 mrqc = 0, reta = 0;
2516 u32 rxcsum;
2517 int i, j;
2518 u8 tcs = netdev_get_num_tc(adapter->netdev);
2519 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2520
2521 if (tcs)
2522 maxq = min(maxq, adapter->num_tx_queues / tcs);
2523
2524 /* Fill out hash function seeds */
2525 for (i = 0; i < 10; i++)
2526 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2527
2528 /* Fill out redirection table */
2529 for (i = 0, j = 0; i < 128; i++, j++) {
2530 if (j == maxq)
2531 j = 0;
2532 /* reta = 4-byte sliding window of
2533 * 0x00..(indices-1)(indices-1)00..etc. */
2534 reta = (reta << 8) | (j * 0x11);
2535 if ((i & 3) == 3)
2536 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2537 }
2538
2539 /* Disable indicating checksum in descriptor, enables RSS hash */
2540 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2541 rxcsum |= IXGBE_RXCSUM_PCSD;
2542 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2543
2544 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2545 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2546 mrqc = IXGBE_MRQC_RSSEN;
2547 } else {
2548 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2549 | IXGBE_FLAG_SRIOV_ENABLED);
2550
2551 switch (mask) {
2552 case (IXGBE_FLAG_RSS_ENABLED):
2553 if (!tcs)
2554 mrqc = IXGBE_MRQC_RSSEN;
2555 else if (tcs <= 4)
2556 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2557 else
2558 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2559 break;
2560 case (IXGBE_FLAG_SRIOV_ENABLED):
2561 mrqc = IXGBE_MRQC_VMDQEN;
2562 break;
2563 default:
2564 break;
2565 }
2566 }
2567
2568 /* Perform hash on these packet types */
2569 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2570 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2571 | IXGBE_MRQC_RSS_FIELD_IPV6
2572 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2573
2574 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2575 }
2576
2577 /**
2578 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2579 * @adapter: address of board private structure
2580 * @index: index of ring to set
2581 **/
2582 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2583 struct ixgbe_ring *ring)
2584 {
2585 struct ixgbe_hw *hw = &adapter->hw;
2586 u32 rscctrl;
2587 int rx_buf_len;
2588 u8 reg_idx = ring->reg_idx;
2589
2590 if (!ring_is_rsc_enabled(ring))
2591 return;
2592
2593 rx_buf_len = ring->rx_buf_len;
2594 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2595 rscctrl |= IXGBE_RSCCTL_RSCEN;
2596 /*
2597 * we must limit the number of descriptors so that the
2598 * total size of max desc * buf_len is not greater
2599 * than 65535
2600 */
2601 if (ring_is_ps_enabled(ring)) {
2602 #if (MAX_SKB_FRAGS > 16)
2603 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2604 #elif (MAX_SKB_FRAGS > 8)
2605 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2606 #elif (MAX_SKB_FRAGS > 4)
2607 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2608 #else
2609 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2610 #endif
2611 } else {
2612 if (rx_buf_len < IXGBE_RXBUFFER_4K)
2613 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2614 else if (rx_buf_len < IXGBE_RXBUFFER_8K)
2615 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2616 else
2617 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2618 }
2619 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2620 }
2621
2622 /**
2623 * ixgbe_set_uta - Set unicast filter table address
2624 * @adapter: board private structure
2625 *
2626 * The unicast table address is a register array of 32-bit registers.
2627 * The table is meant to be used in a way similar to how the MTA is used
2628 * however due to certain limitations in the hardware it is necessary to
2629 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2630 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2631 **/
2632 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2633 {
2634 struct ixgbe_hw *hw = &adapter->hw;
2635 int i;
2636
2637 /* The UTA table only exists on 82599 hardware and newer */
2638 if (hw->mac.type < ixgbe_mac_82599EB)
2639 return;
2640
2641 /* we only need to do this if VMDq is enabled */
2642 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2643 return;
2644
2645 for (i = 0; i < 128; i++)
2646 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2647 }
2648
2649 #define IXGBE_MAX_RX_DESC_POLL 10
2650 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2651 struct ixgbe_ring *ring)
2652 {
2653 struct ixgbe_hw *hw = &adapter->hw;
2654 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2655 u32 rxdctl;
2656 u8 reg_idx = ring->reg_idx;
2657
2658 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2659 if (hw->mac.type == ixgbe_mac_82598EB &&
2660 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2661 return;
2662
2663 do {
2664 usleep_range(1000, 2000);
2665 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2666 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2667
2668 if (!wait_loop) {
2669 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2670 "the polling period\n", reg_idx);
2671 }
2672 }
2673
2674 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2675 struct ixgbe_ring *ring)
2676 {
2677 struct ixgbe_hw *hw = &adapter->hw;
2678 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2679 u32 rxdctl;
2680 u8 reg_idx = ring->reg_idx;
2681
2682 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2683 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2684
2685 /* write value back with RXDCTL.ENABLE bit cleared */
2686 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2687
2688 if (hw->mac.type == ixgbe_mac_82598EB &&
2689 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2690 return;
2691
2692 /* the hardware may take up to 100us to really disable the rx queue */
2693 do {
2694 udelay(10);
2695 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2696 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2697
2698 if (!wait_loop) {
2699 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2700 "the polling period\n", reg_idx);
2701 }
2702 }
2703
2704 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2705 struct ixgbe_ring *ring)
2706 {
2707 struct ixgbe_hw *hw = &adapter->hw;
2708 u64 rdba = ring->dma;
2709 u32 rxdctl;
2710 u8 reg_idx = ring->reg_idx;
2711
2712 /* disable queue to avoid issues while updating state */
2713 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2714 ixgbe_disable_rx_queue(adapter, ring);
2715
2716 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2717 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2718 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2719 ring->count * sizeof(union ixgbe_adv_rx_desc));
2720 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2721 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2722 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2723
2724 ixgbe_configure_srrctl(adapter, ring);
2725 ixgbe_configure_rscctl(adapter, ring);
2726
2727 /* If operating in IOV mode set RLPML for X540 */
2728 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2729 hw->mac.type == ixgbe_mac_X540) {
2730 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2731 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2732 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2733 }
2734
2735 if (hw->mac.type == ixgbe_mac_82598EB) {
2736 /*
2737 * enable cache line friendly hardware writes:
2738 * PTHRESH=32 descriptors (half the internal cache),
2739 * this also removes ugly rx_no_buffer_count increment
2740 * HTHRESH=4 descriptors (to minimize latency on fetch)
2741 * WTHRESH=8 burst writeback up to two cache lines
2742 */
2743 rxdctl &= ~0x3FFFFF;
2744 rxdctl |= 0x080420;
2745 }
2746
2747 /* enable receive descriptor ring */
2748 rxdctl |= IXGBE_RXDCTL_ENABLE;
2749 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2750
2751 ixgbe_rx_desc_queue_enable(adapter, ring);
2752 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
2753 }
2754
2755 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2756 {
2757 struct ixgbe_hw *hw = &adapter->hw;
2758 int p;
2759
2760 /* PSRTYPE must be initialized in non 82598 adapters */
2761 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2762 IXGBE_PSRTYPE_UDPHDR |
2763 IXGBE_PSRTYPE_IPV4HDR |
2764 IXGBE_PSRTYPE_L2HDR |
2765 IXGBE_PSRTYPE_IPV6HDR;
2766
2767 if (hw->mac.type == ixgbe_mac_82598EB)
2768 return;
2769
2770 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2771 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2772
2773 for (p = 0; p < adapter->num_rx_pools; p++)
2774 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2775 psrtype);
2776 }
2777
2778 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2779 {
2780 struct ixgbe_hw *hw = &adapter->hw;
2781 u32 gcr_ext;
2782 u32 vt_reg_bits;
2783 u32 reg_offset, vf_shift;
2784 u32 vmdctl;
2785
2786 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2787 return;
2788
2789 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2790 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2791 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2792 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2793
2794 vf_shift = adapter->num_vfs % 32;
2795 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2796
2797 /* Enable only the PF's pool for Tx/Rx */
2798 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2799 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2800 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2801 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2802 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2803
2804 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2805 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2806
2807 /*
2808 * Set up VF register offsets for selected VT Mode,
2809 * i.e. 32 or 64 VFs for SR-IOV
2810 */
2811 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2812 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2813 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2814 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2815
2816 /* enable Tx loopback for VF/PF communication */
2817 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2818 /* Enable MAC Anti-Spoofing */
2819 hw->mac.ops.set_mac_anti_spoofing(hw,
2820 (adapter->antispoofing_enabled =
2821 (adapter->num_vfs != 0)),
2822 adapter->num_vfs);
2823 }
2824
2825 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2826 {
2827 struct ixgbe_hw *hw = &adapter->hw;
2828 struct net_device *netdev = adapter->netdev;
2829 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2830 int rx_buf_len;
2831 struct ixgbe_ring *rx_ring;
2832 int i;
2833 u32 mhadd, hlreg0;
2834
2835 /* Decide whether to use packet split mode or not */
2836 /* On by default */
2837 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2838
2839 /* Do not use packet split if we're in SR-IOV Mode */
2840 if (adapter->num_vfs)
2841 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2842
2843 /* Disable packet split due to 82599 erratum #45 */
2844 if (hw->mac.type == ixgbe_mac_82599EB)
2845 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2846
2847 #ifdef IXGBE_FCOE
2848 /* adjust max frame to be able to do baby jumbo for FCoE */
2849 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2850 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2851 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2852
2853 #endif /* IXGBE_FCOE */
2854 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2855 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2856 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2857 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2858
2859 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2860 }
2861
2862 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
2863 max_frame += VLAN_HLEN;
2864
2865 /* Set the RX buffer length according to the mode */
2866 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2867 rx_buf_len = IXGBE_RX_HDR_SIZE;
2868 } else {
2869 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2870 (netdev->mtu <= ETH_DATA_LEN))
2871 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2872 /*
2873 * Make best use of allocation by using all but 1K of a
2874 * power of 2 allocation that will be used for skb->head.
2875 */
2876 else if (max_frame <= IXGBE_RXBUFFER_3K)
2877 rx_buf_len = IXGBE_RXBUFFER_3K;
2878 else if (max_frame <= IXGBE_RXBUFFER_7K)
2879 rx_buf_len = IXGBE_RXBUFFER_7K;
2880 else if (max_frame <= IXGBE_RXBUFFER_15K)
2881 rx_buf_len = IXGBE_RXBUFFER_15K;
2882 else
2883 rx_buf_len = IXGBE_MAX_RXBUFFER;
2884 }
2885
2886 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2887 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2888 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2889 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2890
2891 /*
2892 * Setup the HW Rx Head and Tail Descriptor Pointers and
2893 * the Base and Length of the Rx Descriptor Ring
2894 */
2895 for (i = 0; i < adapter->num_rx_queues; i++) {
2896 rx_ring = adapter->rx_ring[i];
2897 rx_ring->rx_buf_len = rx_buf_len;
2898
2899 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2900 set_ring_ps_enabled(rx_ring);
2901 else
2902 clear_ring_ps_enabled(rx_ring);
2903
2904 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2905 set_ring_rsc_enabled(rx_ring);
2906 else
2907 clear_ring_rsc_enabled(rx_ring);
2908
2909 #ifdef IXGBE_FCOE
2910 if (netdev->features & NETIF_F_FCOE_MTU) {
2911 struct ixgbe_ring_feature *f;
2912 f = &adapter->ring_feature[RING_F_FCOE];
2913 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2914 clear_ring_ps_enabled(rx_ring);
2915 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2916 rx_ring->rx_buf_len =
2917 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2918 } else if (!ring_is_rsc_enabled(rx_ring) &&
2919 !ring_is_ps_enabled(rx_ring)) {
2920 rx_ring->rx_buf_len =
2921 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2922 }
2923 }
2924 #endif /* IXGBE_FCOE */
2925 }
2926 }
2927
2928 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2929 {
2930 struct ixgbe_hw *hw = &adapter->hw;
2931 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2932
2933 switch (hw->mac.type) {
2934 case ixgbe_mac_82598EB:
2935 /*
2936 * For VMDq support of different descriptor types or
2937 * buffer sizes through the use of multiple SRRCTL
2938 * registers, RDRXCTL.MVMEN must be set to 1
2939 *
2940 * also, the manual doesn't mention it clearly but DCA hints
2941 * will only use queue 0's tags unless this bit is set. Side
2942 * effects of setting this bit are only that SRRCTL must be
2943 * fully programmed [0..15]
2944 */
2945 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2946 break;
2947 case ixgbe_mac_82599EB:
2948 case ixgbe_mac_X540:
2949 /* Disable RSC for ACK packets */
2950 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2951 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2952 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2953 /* hardware requires some bits to be set by default */
2954 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2955 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2956 break;
2957 default:
2958 /* We should do nothing since we don't know this hardware */
2959 return;
2960 }
2961
2962 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2963 }
2964
2965 /**
2966 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2967 * @adapter: board private structure
2968 *
2969 * Configure the Rx unit of the MAC after a reset.
2970 **/
2971 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2972 {
2973 struct ixgbe_hw *hw = &adapter->hw;
2974 int i;
2975 u32 rxctrl;
2976
2977 /* disable receives while setting up the descriptors */
2978 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2979 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2980
2981 ixgbe_setup_psrtype(adapter);
2982 ixgbe_setup_rdrxctl(adapter);
2983
2984 /* Program registers for the distribution of queues */
2985 ixgbe_setup_mrqc(adapter);
2986
2987 ixgbe_set_uta(adapter);
2988
2989 /* set_rx_buffer_len must be called before ring initialization */
2990 ixgbe_set_rx_buffer_len(adapter);
2991
2992 /*
2993 * Setup the HW Rx Head and Tail Descriptor Pointers and
2994 * the Base and Length of the Rx Descriptor Ring
2995 */
2996 for (i = 0; i < adapter->num_rx_queues; i++)
2997 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
2998
2999 /* disable drop enable for 82598 parts */
3000 if (hw->mac.type == ixgbe_mac_82598EB)
3001 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3002
3003 /* enable all receives */
3004 rxctrl |= IXGBE_RXCTRL_RXEN;
3005 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3006 }
3007
3008 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3009 {
3010 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3011 struct ixgbe_hw *hw = &adapter->hw;
3012 int pool_ndx = adapter->num_vfs;
3013
3014 /* add VID to filter table */
3015 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3016 set_bit(vid, adapter->active_vlans);
3017 }
3018
3019 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3020 {
3021 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3022 struct ixgbe_hw *hw = &adapter->hw;
3023 int pool_ndx = adapter->num_vfs;
3024
3025 /* remove VID from filter table */
3026 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3027 clear_bit(vid, adapter->active_vlans);
3028 }
3029
3030 /**
3031 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3032 * @adapter: driver data
3033 */
3034 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3035 {
3036 struct ixgbe_hw *hw = &adapter->hw;
3037 u32 vlnctrl;
3038
3039 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3040 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3041 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3042 }
3043
3044 /**
3045 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3046 * @adapter: driver data
3047 */
3048 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3049 {
3050 struct ixgbe_hw *hw = &adapter->hw;
3051 u32 vlnctrl;
3052
3053 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3054 vlnctrl |= IXGBE_VLNCTRL_VFE;
3055 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3056 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3057 }
3058
3059 /**
3060 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3061 * @adapter: driver data
3062 */
3063 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3064 {
3065 struct ixgbe_hw *hw = &adapter->hw;
3066 u32 vlnctrl;
3067 int i, j;
3068
3069 switch (hw->mac.type) {
3070 case ixgbe_mac_82598EB:
3071 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3072 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3073 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3074 break;
3075 case ixgbe_mac_82599EB:
3076 case ixgbe_mac_X540:
3077 for (i = 0; i < adapter->num_rx_queues; i++) {
3078 j = adapter->rx_ring[i]->reg_idx;
3079 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3080 vlnctrl &= ~IXGBE_RXDCTL_VME;
3081 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3082 }
3083 break;
3084 default:
3085 break;
3086 }
3087 }
3088
3089 /**
3090 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3091 * @adapter: driver data
3092 */
3093 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3094 {
3095 struct ixgbe_hw *hw = &adapter->hw;
3096 u32 vlnctrl;
3097 int i, j;
3098
3099 switch (hw->mac.type) {
3100 case ixgbe_mac_82598EB:
3101 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3102 vlnctrl |= IXGBE_VLNCTRL_VME;
3103 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3104 break;
3105 case ixgbe_mac_82599EB:
3106 case ixgbe_mac_X540:
3107 for (i = 0; i < adapter->num_rx_queues; i++) {
3108 j = adapter->rx_ring[i]->reg_idx;
3109 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3110 vlnctrl |= IXGBE_RXDCTL_VME;
3111 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3112 }
3113 break;
3114 default:
3115 break;
3116 }
3117 }
3118
3119 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3120 {
3121 u16 vid;
3122
3123 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3124
3125 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3126 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3127 }
3128
3129 /**
3130 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3131 * @netdev: network interface device structure
3132 *
3133 * Writes unicast address list to the RAR table.
3134 * Returns: -ENOMEM on failure/insufficient address space
3135 * 0 on no addresses written
3136 * X on writing X addresses to the RAR table
3137 **/
3138 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3139 {
3140 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3141 struct ixgbe_hw *hw = &adapter->hw;
3142 unsigned int vfn = adapter->num_vfs;
3143 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3144 int count = 0;
3145
3146 /* return ENOMEM indicating insufficient memory for addresses */
3147 if (netdev_uc_count(netdev) > rar_entries)
3148 return -ENOMEM;
3149
3150 if (!netdev_uc_empty(netdev) && rar_entries) {
3151 struct netdev_hw_addr *ha;
3152 /* return error if we do not support writing to RAR table */
3153 if (!hw->mac.ops.set_rar)
3154 return -ENOMEM;
3155
3156 netdev_for_each_uc_addr(ha, netdev) {
3157 if (!rar_entries)
3158 break;
3159 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3160 vfn, IXGBE_RAH_AV);
3161 count++;
3162 }
3163 }
3164 /* write the addresses in reverse order to avoid write combining */
3165 for (; rar_entries > 0 ; rar_entries--)
3166 hw->mac.ops.clear_rar(hw, rar_entries);
3167
3168 return count;
3169 }
3170
3171 /**
3172 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3173 * @netdev: network interface device structure
3174 *
3175 * The set_rx_method entry point is called whenever the unicast/multicast
3176 * address list or the network interface flags are updated. This routine is
3177 * responsible for configuring the hardware for proper unicast, multicast and
3178 * promiscuous mode.
3179 **/
3180 void ixgbe_set_rx_mode(struct net_device *netdev)
3181 {
3182 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3183 struct ixgbe_hw *hw = &adapter->hw;
3184 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3185 int count;
3186
3187 /* Check for Promiscuous and All Multicast modes */
3188
3189 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3190
3191 /* set all bits that we expect to always be set */
3192 fctrl |= IXGBE_FCTRL_BAM;
3193 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3194 fctrl |= IXGBE_FCTRL_PMCF;
3195
3196 /* clear the bits we are changing the status of */
3197 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3198
3199 if (netdev->flags & IFF_PROMISC) {
3200 hw->addr_ctrl.user_set_promisc = true;
3201 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3202 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3203 /* don't hardware filter vlans in promisc mode */
3204 ixgbe_vlan_filter_disable(adapter);
3205 } else {
3206 if (netdev->flags & IFF_ALLMULTI) {
3207 fctrl |= IXGBE_FCTRL_MPE;
3208 vmolr |= IXGBE_VMOLR_MPE;
3209 } else {
3210 /*
3211 * Write addresses to the MTA, if the attempt fails
3212 * then we should just turn on promiscuous mode so
3213 * that we can at least receive multicast traffic
3214 */
3215 hw->mac.ops.update_mc_addr_list(hw, netdev);
3216 vmolr |= IXGBE_VMOLR_ROMPE;
3217 }
3218 ixgbe_vlan_filter_enable(adapter);
3219 hw->addr_ctrl.user_set_promisc = false;
3220 /*
3221 * Write addresses to available RAR registers, if there is not
3222 * sufficient space to store all the addresses then enable
3223 * unicast promiscuous mode
3224 */
3225 count = ixgbe_write_uc_addr_list(netdev);
3226 if (count < 0) {
3227 fctrl |= IXGBE_FCTRL_UPE;
3228 vmolr |= IXGBE_VMOLR_ROPE;
3229 }
3230 }
3231
3232 if (adapter->num_vfs) {
3233 ixgbe_restore_vf_multicasts(adapter);
3234 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3235 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3236 IXGBE_VMOLR_ROPE);
3237 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3238 }
3239
3240 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3241
3242 if (netdev->features & NETIF_F_HW_VLAN_RX)
3243 ixgbe_vlan_strip_enable(adapter);
3244 else
3245 ixgbe_vlan_strip_disable(adapter);
3246 }
3247
3248 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3249 {
3250 int q_idx;
3251 struct ixgbe_q_vector *q_vector;
3252 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3253
3254 /* legacy and MSI only use one vector */
3255 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3256 q_vectors = 1;
3257
3258 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3259 q_vector = adapter->q_vector[q_idx];
3260 napi_enable(&q_vector->napi);
3261 }
3262 }
3263
3264 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3265 {
3266 int q_idx;
3267 struct ixgbe_q_vector *q_vector;
3268 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3269
3270 /* legacy and MSI only use one vector */
3271 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3272 q_vectors = 1;
3273
3274 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3275 q_vector = adapter->q_vector[q_idx];
3276 napi_disable(&q_vector->napi);
3277 }
3278 }
3279
3280 #ifdef CONFIG_IXGBE_DCB
3281 /*
3282 * ixgbe_configure_dcb - Configure DCB hardware
3283 * @adapter: ixgbe adapter struct
3284 *
3285 * This is called by the driver on open to configure the DCB hardware.
3286 * This is also called by the gennetlink interface when reconfiguring
3287 * the DCB state.
3288 */
3289 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3290 {
3291 struct ixgbe_hw *hw = &adapter->hw;
3292 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3293
3294 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3295 if (hw->mac.type == ixgbe_mac_82598EB)
3296 netif_set_gso_max_size(adapter->netdev, 65536);
3297 return;
3298 }
3299
3300 if (hw->mac.type == ixgbe_mac_82598EB)
3301 netif_set_gso_max_size(adapter->netdev, 32768);
3302
3303
3304 /* Enable VLAN tag insert/strip */
3305 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3306
3307 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3308
3309 /* reconfigure the hardware */
3310 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3311 #ifdef IXGBE_FCOE
3312 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3313 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3314 #endif
3315 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3316 DCB_TX_CONFIG);
3317 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3318 DCB_RX_CONFIG);
3319 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3320 } else {
3321 struct net_device *dev = adapter->netdev;
3322
3323 if (adapter->ixgbe_ieee_ets) {
3324 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
3325 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3326
3327 ixgbe_dcb_hw_ets(&adapter->hw, ets, max_frame);
3328 }
3329
3330 if (adapter->ixgbe_ieee_pfc) {
3331 struct ieee_pfc *pfc = adapter->ixgbe_ieee_pfc;
3332
3333 ixgbe_dcb_hw_pfc_config(&adapter->hw, pfc->pfc_en);
3334 }
3335 }
3336
3337 /* Enable RSS Hash per TC */
3338 if (hw->mac.type != ixgbe_mac_82598EB) {
3339 int i;
3340 u32 reg = 0;
3341
3342 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3343 u8 msb = 0;
3344 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3345
3346 while (cnt >>= 1)
3347 msb++;
3348
3349 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3350 }
3351 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3352 }
3353 }
3354 #endif
3355
3356 /* Additional bittime to account for IXGBE framing */
3357 #define IXGBE_ETH_FRAMING 20
3358
3359 /*
3360 * ixgbe_hpbthresh - calculate high water mark for flow control
3361 *
3362 * @adapter: board private structure to calculate for
3363 * @pb - packet buffer to calculate
3364 */
3365 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3366 {
3367 struct ixgbe_hw *hw = &adapter->hw;
3368 struct net_device *dev = adapter->netdev;
3369 int link, tc, kb, marker;
3370 u32 dv_id, rx_pba;
3371
3372 /* Calculate max LAN frame size */
3373 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3374
3375 #ifdef IXGBE_FCOE
3376 /* FCoE traffic class uses FCOE jumbo frames */
3377 if (dev->features & NETIF_F_FCOE_MTU) {
3378 int fcoe_pb = 0;
3379
3380 #ifdef CONFIG_IXGBE_DCB
3381 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3382
3383 #endif
3384 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3385 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3386 }
3387 #endif
3388
3389 /* Calculate delay value for device */
3390 switch (hw->mac.type) {
3391 case ixgbe_mac_X540:
3392 dv_id = IXGBE_DV_X540(link, tc);
3393 break;
3394 default:
3395 dv_id = IXGBE_DV(link, tc);
3396 break;
3397 }
3398
3399 /* Loopback switch introduces additional latency */
3400 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3401 dv_id += IXGBE_B2BT(tc);
3402
3403 /* Delay value is calculated in bit times convert to KB */
3404 kb = IXGBE_BT2KB(dv_id);
3405 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3406
3407 marker = rx_pba - kb;
3408
3409 /* It is possible that the packet buffer is not large enough
3410 * to provide required headroom. In this case throw an error
3411 * to user and a do the best we can.
3412 */
3413 if (marker < 0) {
3414 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3415 "headroom to support flow control."
3416 "Decrease MTU or number of traffic classes\n", pb);
3417 marker = tc + 1;
3418 }
3419
3420 return marker;
3421 }
3422
3423 /*
3424 * ixgbe_lpbthresh - calculate low water mark for for flow control
3425 *
3426 * @adapter: board private structure to calculate for
3427 * @pb - packet buffer to calculate
3428 */
3429 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3430 {
3431 struct ixgbe_hw *hw = &adapter->hw;
3432 struct net_device *dev = adapter->netdev;
3433 int tc;
3434 u32 dv_id;
3435
3436 /* Calculate max LAN frame size */
3437 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3438
3439 /* Calculate delay value for device */
3440 switch (hw->mac.type) {
3441 case ixgbe_mac_X540:
3442 dv_id = IXGBE_LOW_DV_X540(tc);
3443 break;
3444 default:
3445 dv_id = IXGBE_LOW_DV(tc);
3446 break;
3447 }
3448
3449 /* Delay value is calculated in bit times convert to KB */
3450 return IXGBE_BT2KB(dv_id);
3451 }
3452
3453 /*
3454 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3455 */
3456 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3457 {
3458 struct ixgbe_hw *hw = &adapter->hw;
3459 int num_tc = netdev_get_num_tc(adapter->netdev);
3460 int i;
3461
3462 if (!num_tc)
3463 num_tc = 1;
3464
3465 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3466
3467 for (i = 0; i < num_tc; i++) {
3468 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3469
3470 /* Low water marks must not be larger than high water marks */
3471 if (hw->fc.low_water > hw->fc.high_water[i])
3472 hw->fc.low_water = 0;
3473 }
3474 }
3475
3476 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3477 {
3478 struct ixgbe_hw *hw = &adapter->hw;
3479 int hdrm;
3480 u8 tc = netdev_get_num_tc(adapter->netdev);
3481
3482 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3483 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3484 hdrm = 32 << adapter->fdir_pballoc;
3485 else
3486 hdrm = 0;
3487
3488 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3489 ixgbe_pbthresh_setup(adapter);
3490 }
3491
3492 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3493 {
3494 struct ixgbe_hw *hw = &adapter->hw;
3495 struct hlist_node *node, *node2;
3496 struct ixgbe_fdir_filter *filter;
3497
3498 spin_lock(&adapter->fdir_perfect_lock);
3499
3500 if (!hlist_empty(&adapter->fdir_filter_list))
3501 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3502
3503 hlist_for_each_entry_safe(filter, node, node2,
3504 &adapter->fdir_filter_list, fdir_node) {
3505 ixgbe_fdir_write_perfect_filter_82599(hw,
3506 &filter->filter,
3507 filter->sw_idx,
3508 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3509 IXGBE_FDIR_DROP_QUEUE :
3510 adapter->rx_ring[filter->action]->reg_idx);
3511 }
3512
3513 spin_unlock(&adapter->fdir_perfect_lock);
3514 }
3515
3516 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3517 {
3518 ixgbe_configure_pb(adapter);
3519 #ifdef CONFIG_IXGBE_DCB
3520 ixgbe_configure_dcb(adapter);
3521 #endif
3522
3523 ixgbe_set_rx_mode(adapter->netdev);
3524 ixgbe_restore_vlan(adapter);
3525
3526 #ifdef IXGBE_FCOE
3527 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3528 ixgbe_configure_fcoe(adapter);
3529
3530 #endif /* IXGBE_FCOE */
3531 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3532 ixgbe_init_fdir_signature_82599(&adapter->hw,
3533 adapter->fdir_pballoc);
3534 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3535 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3536 adapter->fdir_pballoc);
3537 ixgbe_fdir_filter_restore(adapter);
3538 }
3539
3540 ixgbe_configure_virtualization(adapter);
3541
3542 ixgbe_configure_tx(adapter);
3543 ixgbe_configure_rx(adapter);
3544 }
3545
3546 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3547 {
3548 switch (hw->phy.type) {
3549 case ixgbe_phy_sfp_avago:
3550 case ixgbe_phy_sfp_ftl:
3551 case ixgbe_phy_sfp_intel:
3552 case ixgbe_phy_sfp_unknown:
3553 case ixgbe_phy_sfp_passive_tyco:
3554 case ixgbe_phy_sfp_passive_unknown:
3555 case ixgbe_phy_sfp_active_unknown:
3556 case ixgbe_phy_sfp_ftl_active:
3557 return true;
3558 case ixgbe_phy_nl:
3559 if (hw->mac.type == ixgbe_mac_82598EB)
3560 return true;
3561 default:
3562 return false;
3563 }
3564 }
3565
3566 /**
3567 * ixgbe_sfp_link_config - set up SFP+ link
3568 * @adapter: pointer to private adapter struct
3569 **/
3570 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3571 {
3572 /*
3573 * We are assuming the worst case scenerio here, and that
3574 * is that an SFP was inserted/removed after the reset
3575 * but before SFP detection was enabled. As such the best
3576 * solution is to just start searching as soon as we start
3577 */
3578 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3579 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3580
3581 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3582 }
3583
3584 /**
3585 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3586 * @hw: pointer to private hardware struct
3587 *
3588 * Returns 0 on success, negative on failure
3589 **/
3590 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3591 {
3592 u32 autoneg;
3593 bool negotiation, link_up = false;
3594 u32 ret = IXGBE_ERR_LINK_SETUP;
3595
3596 if (hw->mac.ops.check_link)
3597 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3598
3599 if (ret)
3600 goto link_cfg_out;
3601
3602 autoneg = hw->phy.autoneg_advertised;
3603 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3604 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3605 &negotiation);
3606 if (ret)
3607 goto link_cfg_out;
3608
3609 if (hw->mac.ops.setup_link)
3610 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3611 link_cfg_out:
3612 return ret;
3613 }
3614
3615 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3616 {
3617 struct ixgbe_hw *hw = &adapter->hw;
3618 u32 gpie = 0;
3619
3620 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3621 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3622 IXGBE_GPIE_OCD;
3623 gpie |= IXGBE_GPIE_EIAME;
3624 /*
3625 * use EIAM to auto-mask when MSI-X interrupt is asserted
3626 * this saves a register write for every interrupt
3627 */
3628 switch (hw->mac.type) {
3629 case ixgbe_mac_82598EB:
3630 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3631 break;
3632 case ixgbe_mac_82599EB:
3633 case ixgbe_mac_X540:
3634 default:
3635 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3636 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3637 break;
3638 }
3639 } else {
3640 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3641 * specifically only auto mask tx and rx interrupts */
3642 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3643 }
3644
3645 /* XXX: to interrupt immediately for EICS writes, enable this */
3646 /* gpie |= IXGBE_GPIE_EIMEN; */
3647
3648 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3649 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3650 gpie |= IXGBE_GPIE_VTMODE_64;
3651 }
3652
3653 /* Enable Thermal over heat sensor interrupt */
3654 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3655 gpie |= IXGBE_SDP0_GPIEN;
3656
3657 /* Enable fan failure interrupt */
3658 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3659 gpie |= IXGBE_SDP1_GPIEN;
3660
3661 if (hw->mac.type == ixgbe_mac_82599EB) {
3662 gpie |= IXGBE_SDP1_GPIEN;
3663 gpie |= IXGBE_SDP2_GPIEN;
3664 }
3665
3666 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3667 }
3668
3669 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
3670 {
3671 struct ixgbe_hw *hw = &adapter->hw;
3672 int err;
3673 u32 ctrl_ext;
3674
3675 ixgbe_get_hw_control(adapter);
3676 ixgbe_setup_gpie(adapter);
3677
3678 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3679 ixgbe_configure_msix(adapter);
3680 else
3681 ixgbe_configure_msi_and_legacy(adapter);
3682
3683 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3684 if (hw->mac.ops.enable_tx_laser &&
3685 ((hw->phy.multispeed_fiber) ||
3686 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3687 (hw->mac.type == ixgbe_mac_82599EB))))
3688 hw->mac.ops.enable_tx_laser(hw);
3689
3690 clear_bit(__IXGBE_DOWN, &adapter->state);
3691 ixgbe_napi_enable_all(adapter);
3692
3693 if (ixgbe_is_sfp(hw)) {
3694 ixgbe_sfp_link_config(adapter);
3695 } else {
3696 err = ixgbe_non_sfp_link_config(hw);
3697 if (err)
3698 e_err(probe, "link_config FAILED %d\n", err);
3699 }
3700
3701 /* clear any pending interrupts, may auto mask */
3702 IXGBE_READ_REG(hw, IXGBE_EICR);
3703 ixgbe_irq_enable(adapter, true, true);
3704
3705 /*
3706 * If this adapter has a fan, check to see if we had a failure
3707 * before we enabled the interrupt.
3708 */
3709 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3710 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3711 if (esdp & IXGBE_ESDP_SDP1)
3712 e_crit(drv, "Fan has stopped, replace the adapter\n");
3713 }
3714
3715 /* enable transmits */
3716 netif_tx_start_all_queues(adapter->netdev);
3717
3718 /* bring the link up in the watchdog, this could race with our first
3719 * link up interrupt but shouldn't be a problem */
3720 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3721 adapter->link_check_timeout = jiffies;
3722 mod_timer(&adapter->service_timer, jiffies);
3723
3724 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3725 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3726 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3727 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3728 }
3729
3730 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3731 {
3732 WARN_ON(in_interrupt());
3733 /* put off any impending NetWatchDogTimeout */
3734 adapter->netdev->trans_start = jiffies;
3735
3736 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3737 usleep_range(1000, 2000);
3738 ixgbe_down(adapter);
3739 /*
3740 * If SR-IOV enabled then wait a bit before bringing the adapter
3741 * back up to give the VFs time to respond to the reset. The
3742 * two second wait is based upon the watchdog timer cycle in
3743 * the VF driver.
3744 */
3745 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3746 msleep(2000);
3747 ixgbe_up(adapter);
3748 clear_bit(__IXGBE_RESETTING, &adapter->state);
3749 }
3750
3751 void ixgbe_up(struct ixgbe_adapter *adapter)
3752 {
3753 /* hardware has been reset, we need to reload some things */
3754 ixgbe_configure(adapter);
3755
3756 ixgbe_up_complete(adapter);
3757 }
3758
3759 void ixgbe_reset(struct ixgbe_adapter *adapter)
3760 {
3761 struct ixgbe_hw *hw = &adapter->hw;
3762 int err;
3763
3764 /* lock SFP init bit to prevent race conditions with the watchdog */
3765 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3766 usleep_range(1000, 2000);
3767
3768 /* clear all SFP and link config related flags while holding SFP_INIT */
3769 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3770 IXGBE_FLAG2_SFP_NEEDS_RESET);
3771 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3772
3773 err = hw->mac.ops.init_hw(hw);
3774 switch (err) {
3775 case 0:
3776 case IXGBE_ERR_SFP_NOT_PRESENT:
3777 case IXGBE_ERR_SFP_NOT_SUPPORTED:
3778 break;
3779 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3780 e_dev_err("master disable timed out\n");
3781 break;
3782 case IXGBE_ERR_EEPROM_VERSION:
3783 /* We are running on a pre-production device, log a warning */
3784 e_dev_warn("This device is a pre-production adapter/LOM. "
3785 "Please be aware there may be issuesassociated with "
3786 "your hardware. If you are experiencing problems "
3787 "please contact your Intel or hardware "
3788 "representative who provided you with this "
3789 "hardware.\n");
3790 break;
3791 default:
3792 e_dev_err("Hardware Error: %d\n", err);
3793 }
3794
3795 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3796
3797 /* reprogram the RAR[0] in case user changed it. */
3798 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3799 IXGBE_RAH_AV);
3800 }
3801
3802 /**
3803 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3804 * @rx_ring: ring to free buffers from
3805 **/
3806 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3807 {
3808 struct device *dev = rx_ring->dev;
3809 unsigned long size;
3810 u16 i;
3811
3812 /* ring already cleared, nothing to do */
3813 if (!rx_ring->rx_buffer_info)
3814 return;
3815
3816 /* Free all the Rx ring sk_buffs */
3817 for (i = 0; i < rx_ring->count; i++) {
3818 struct ixgbe_rx_buffer *rx_buffer_info;
3819
3820 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3821 if (rx_buffer_info->dma) {
3822 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3823 rx_ring->rx_buf_len,
3824 DMA_FROM_DEVICE);
3825 rx_buffer_info->dma = 0;
3826 }
3827 if (rx_buffer_info->skb) {
3828 struct sk_buff *skb = rx_buffer_info->skb;
3829 rx_buffer_info->skb = NULL;
3830 do {
3831 struct sk_buff *this = skb;
3832 if (IXGBE_RSC_CB(this)->delay_unmap) {
3833 dma_unmap_single(dev,
3834 IXGBE_RSC_CB(this)->dma,
3835 rx_ring->rx_buf_len,
3836 DMA_FROM_DEVICE);
3837 IXGBE_RSC_CB(this)->dma = 0;
3838 IXGBE_RSC_CB(skb)->delay_unmap = false;
3839 }
3840 skb = skb->prev;
3841 dev_kfree_skb(this);
3842 } while (skb);
3843 }
3844 if (!rx_buffer_info->page)
3845 continue;
3846 if (rx_buffer_info->page_dma) {
3847 dma_unmap_page(dev, rx_buffer_info->page_dma,
3848 PAGE_SIZE / 2, DMA_FROM_DEVICE);
3849 rx_buffer_info->page_dma = 0;
3850 }
3851 put_page(rx_buffer_info->page);
3852 rx_buffer_info->page = NULL;
3853 rx_buffer_info->page_offset = 0;
3854 }
3855
3856 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3857 memset(rx_ring->rx_buffer_info, 0, size);
3858
3859 /* Zero out the descriptor ring */
3860 memset(rx_ring->desc, 0, rx_ring->size);
3861
3862 rx_ring->next_to_clean = 0;
3863 rx_ring->next_to_use = 0;
3864 }
3865
3866 /**
3867 * ixgbe_clean_tx_ring - Free Tx Buffers
3868 * @tx_ring: ring to be cleaned
3869 **/
3870 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3871 {
3872 struct ixgbe_tx_buffer *tx_buffer_info;
3873 unsigned long size;
3874 u16 i;
3875
3876 /* ring already cleared, nothing to do */
3877 if (!tx_ring->tx_buffer_info)
3878 return;
3879
3880 /* Free all the Tx ring sk_buffs */
3881 for (i = 0; i < tx_ring->count; i++) {
3882 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3883 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3884 }
3885
3886 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3887 memset(tx_ring->tx_buffer_info, 0, size);
3888
3889 /* Zero out the descriptor ring */
3890 memset(tx_ring->desc, 0, tx_ring->size);
3891
3892 tx_ring->next_to_use = 0;
3893 tx_ring->next_to_clean = 0;
3894 }
3895
3896 /**
3897 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3898 * @adapter: board private structure
3899 **/
3900 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3901 {
3902 int i;
3903
3904 for (i = 0; i < adapter->num_rx_queues; i++)
3905 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3906 }
3907
3908 /**
3909 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3910 * @adapter: board private structure
3911 **/
3912 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3913 {
3914 int i;
3915
3916 for (i = 0; i < adapter->num_tx_queues; i++)
3917 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3918 }
3919
3920 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
3921 {
3922 struct hlist_node *node, *node2;
3923 struct ixgbe_fdir_filter *filter;
3924
3925 spin_lock(&adapter->fdir_perfect_lock);
3926
3927 hlist_for_each_entry_safe(filter, node, node2,
3928 &adapter->fdir_filter_list, fdir_node) {
3929 hlist_del(&filter->fdir_node);
3930 kfree(filter);
3931 }
3932 adapter->fdir_filter_count = 0;
3933
3934 spin_unlock(&adapter->fdir_perfect_lock);
3935 }
3936
3937 void ixgbe_down(struct ixgbe_adapter *adapter)
3938 {
3939 struct net_device *netdev = adapter->netdev;
3940 struct ixgbe_hw *hw = &adapter->hw;
3941 u32 rxctrl;
3942 int i;
3943
3944 /* signal that we are down to the interrupt handler */
3945 set_bit(__IXGBE_DOWN, &adapter->state);
3946
3947 /* disable receives */
3948 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3949 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3950
3951 /* disable all enabled rx queues */
3952 for (i = 0; i < adapter->num_rx_queues; i++)
3953 /* this call also flushes the previous write */
3954 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
3955
3956 usleep_range(10000, 20000);
3957
3958 netif_tx_stop_all_queues(netdev);
3959
3960 /* call carrier off first to avoid false dev_watchdog timeouts */
3961 netif_carrier_off(netdev);
3962 netif_tx_disable(netdev);
3963
3964 ixgbe_irq_disable(adapter);
3965
3966 ixgbe_napi_disable_all(adapter);
3967
3968 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
3969 IXGBE_FLAG2_RESET_REQUESTED);
3970 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3971
3972 del_timer_sync(&adapter->service_timer);
3973
3974 if (adapter->num_vfs) {
3975 /* Clear EITR Select mapping */
3976 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
3977
3978 /* Mark all the VFs as inactive */
3979 for (i = 0 ; i < adapter->num_vfs; i++)
3980 adapter->vfinfo[i].clear_to_send = 0;
3981
3982 /* ping all the active vfs to let them know we are going down */
3983 ixgbe_ping_all_vfs(adapter);
3984
3985 /* Disable all VFTE/VFRE TX/RX */
3986 ixgbe_disable_tx_rx(adapter);
3987 }
3988
3989 /* disable transmits in the hardware now that interrupts are off */
3990 for (i = 0; i < adapter->num_tx_queues; i++) {
3991 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
3992 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
3993 }
3994
3995 /* Disable the Tx DMA engine on 82599 and X540 */
3996 switch (hw->mac.type) {
3997 case ixgbe_mac_82599EB:
3998 case ixgbe_mac_X540:
3999 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4000 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4001 ~IXGBE_DMATXCTL_TE));
4002 break;
4003 default:
4004 break;
4005 }
4006
4007 if (!pci_channel_offline(adapter->pdev))
4008 ixgbe_reset(adapter);
4009
4010 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4011 if (hw->mac.ops.disable_tx_laser &&
4012 ((hw->phy.multispeed_fiber) ||
4013 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4014 (hw->mac.type == ixgbe_mac_82599EB))))
4015 hw->mac.ops.disable_tx_laser(hw);
4016
4017 ixgbe_clean_all_tx_rings(adapter);
4018 ixgbe_clean_all_rx_rings(adapter);
4019
4020 #ifdef CONFIG_IXGBE_DCA
4021 /* since we reset the hardware DCA settings were cleared */
4022 ixgbe_setup_dca(adapter);
4023 #endif
4024 }
4025
4026 /**
4027 * ixgbe_poll - NAPI Rx polling callback
4028 * @napi: structure for representing this polling device
4029 * @budget: how many packets driver is allowed to clean
4030 *
4031 * This function is used for legacy and MSI, NAPI mode
4032 **/
4033 static int ixgbe_poll(struct napi_struct *napi, int budget)
4034 {
4035 struct ixgbe_q_vector *q_vector =
4036 container_of(napi, struct ixgbe_q_vector, napi);
4037 struct ixgbe_adapter *adapter = q_vector->adapter;
4038 struct ixgbe_ring *ring;
4039 int per_ring_budget;
4040 bool clean_complete = true;
4041
4042 #ifdef CONFIG_IXGBE_DCA
4043 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4044 ixgbe_update_dca(q_vector);
4045 #endif
4046
4047 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
4048 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
4049
4050 /* attempt to distribute budget to each queue fairly, but don't allow
4051 * the budget to go below 1 because we'll exit polling */
4052 if (q_vector->rx.count > 1)
4053 per_ring_budget = max(budget/q_vector->rx.count, 1);
4054 else
4055 per_ring_budget = budget;
4056
4057 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
4058 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
4059 per_ring_budget);
4060
4061 /* If all work not completed, return budget and keep polling */
4062 if (!clean_complete)
4063 return budget;
4064
4065 /* all work done, exit the polling mode */
4066 napi_complete(napi);
4067 if (adapter->rx_itr_setting & 1)
4068 ixgbe_set_itr(q_vector);
4069 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4070 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4071
4072 return 0;
4073 }
4074
4075 /**
4076 * ixgbe_tx_timeout - Respond to a Tx Hang
4077 * @netdev: network interface device structure
4078 **/
4079 static void ixgbe_tx_timeout(struct net_device *netdev)
4080 {
4081 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4082
4083 /* Do the reset outside of interrupt context */
4084 ixgbe_tx_timeout_reset(adapter);
4085 }
4086
4087 /**
4088 * ixgbe_set_rss_queues: Allocate queues for RSS
4089 * @adapter: board private structure to initialize
4090 *
4091 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4092 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4093 *
4094 **/
4095 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4096 {
4097 bool ret = false;
4098 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4099
4100 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4101 f->mask = 0xF;
4102 adapter->num_rx_queues = f->indices;
4103 adapter->num_tx_queues = f->indices;
4104 ret = true;
4105 } else {
4106 ret = false;
4107 }
4108
4109 return ret;
4110 }
4111
4112 /**
4113 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4114 * @adapter: board private structure to initialize
4115 *
4116 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4117 * to the original CPU that initiated the Tx session. This runs in addition
4118 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4119 * Rx load across CPUs using RSS.
4120 *
4121 **/
4122 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4123 {
4124 bool ret = false;
4125 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4126
4127 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4128 f_fdir->mask = 0;
4129
4130 /* Flow Director must have RSS enabled */
4131 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4132 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4133 adapter->num_tx_queues = f_fdir->indices;
4134 adapter->num_rx_queues = f_fdir->indices;
4135 ret = true;
4136 } else {
4137 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4138 }
4139 return ret;
4140 }
4141
4142 #ifdef IXGBE_FCOE
4143 /**
4144 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4145 * @adapter: board private structure to initialize
4146 *
4147 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4148 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4149 * rx queues out of the max number of rx queues, instead, it is used as the
4150 * index of the first rx queue used by FCoE.
4151 *
4152 **/
4153 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4154 {
4155 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4156
4157 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4158 return false;
4159
4160 f->indices = min((int)num_online_cpus(), f->indices);
4161
4162 adapter->num_rx_queues = 1;
4163 adapter->num_tx_queues = 1;
4164
4165 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4166 e_info(probe, "FCoE enabled with RSS\n");
4167 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4168 ixgbe_set_fdir_queues(adapter);
4169 else
4170 ixgbe_set_rss_queues(adapter);
4171 }
4172
4173 /* adding FCoE rx rings to the end */
4174 f->mask = adapter->num_rx_queues;
4175 adapter->num_rx_queues += f->indices;
4176 adapter->num_tx_queues += f->indices;
4177
4178 return true;
4179 }
4180 #endif /* IXGBE_FCOE */
4181
4182 /* Artificial max queue cap per traffic class in DCB mode */
4183 #define DCB_QUEUE_CAP 8
4184
4185 #ifdef CONFIG_IXGBE_DCB
4186 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4187 {
4188 int per_tc_q, q, i, offset = 0;
4189 struct net_device *dev = adapter->netdev;
4190 int tcs = netdev_get_num_tc(dev);
4191
4192 if (!tcs)
4193 return false;
4194
4195 /* Map queue offset and counts onto allocated tx queues */
4196 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4197 q = min((int)num_online_cpus(), per_tc_q);
4198
4199 for (i = 0; i < tcs; i++) {
4200 netdev_set_prio_tc_map(dev, i, i);
4201 netdev_set_tc_queue(dev, i, q, offset);
4202 offset += q;
4203 }
4204
4205 adapter->num_tx_queues = q * tcs;
4206 adapter->num_rx_queues = q * tcs;
4207
4208 #ifdef IXGBE_FCOE
4209 /* FCoE enabled queues require special configuration indexed
4210 * by feature specific indices and mask. Here we map FCoE
4211 * indices onto the DCB queue pairs allowing FCoE to own
4212 * configuration later.
4213 */
4214 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4215 int tc;
4216 struct ixgbe_ring_feature *f =
4217 &adapter->ring_feature[RING_F_FCOE];
4218
4219 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4220 f->indices = dev->tc_to_txq[tc].count;
4221 f->mask = dev->tc_to_txq[tc].offset;
4222 }
4223 #endif
4224
4225 return true;
4226 }
4227 #endif
4228
4229 /**
4230 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4231 * @adapter: board private structure to initialize
4232 *
4233 * IOV doesn't actually use anything, so just NAK the
4234 * request for now and let the other queue routines
4235 * figure out what to do.
4236 */
4237 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4238 {
4239 return false;
4240 }
4241
4242 /*
4243 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4244 * @adapter: board private structure to initialize
4245 *
4246 * This is the top level queue allocation routine. The order here is very
4247 * important, starting with the "most" number of features turned on at once,
4248 * and ending with the smallest set of features. This way large combinations
4249 * can be allocated if they're turned on, and smaller combinations are the
4250 * fallthrough conditions.
4251 *
4252 **/
4253 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4254 {
4255 /* Start with base case */
4256 adapter->num_rx_queues = 1;
4257 adapter->num_tx_queues = 1;
4258 adapter->num_rx_pools = adapter->num_rx_queues;
4259 adapter->num_rx_queues_per_pool = 1;
4260
4261 if (ixgbe_set_sriov_queues(adapter))
4262 goto done;
4263
4264 #ifdef CONFIG_IXGBE_DCB
4265 if (ixgbe_set_dcb_queues(adapter))
4266 goto done;
4267
4268 #endif
4269 #ifdef IXGBE_FCOE
4270 if (ixgbe_set_fcoe_queues(adapter))
4271 goto done;
4272
4273 #endif /* IXGBE_FCOE */
4274 if (ixgbe_set_fdir_queues(adapter))
4275 goto done;
4276
4277 if (ixgbe_set_rss_queues(adapter))
4278 goto done;
4279
4280 /* fallback to base case */
4281 adapter->num_rx_queues = 1;
4282 adapter->num_tx_queues = 1;
4283
4284 done:
4285 /* Notify the stack of the (possibly) reduced queue counts. */
4286 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4287 return netif_set_real_num_rx_queues(adapter->netdev,
4288 adapter->num_rx_queues);
4289 }
4290
4291 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4292 int vectors)
4293 {
4294 int err, vector_threshold;
4295
4296 /* We'll want at least 3 (vector_threshold):
4297 * 1) TxQ[0] Cleanup
4298 * 2) RxQ[0] Cleanup
4299 * 3) Other (Link Status Change, etc.)
4300 * 4) TCP Timer (optional)
4301 */
4302 vector_threshold = MIN_MSIX_COUNT;
4303
4304 /* The more we get, the more we will assign to Tx/Rx Cleanup
4305 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4306 * Right now, we simply care about how many we'll get; we'll
4307 * set them up later while requesting irq's.
4308 */
4309 while (vectors >= vector_threshold) {
4310 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4311 vectors);
4312 if (!err) /* Success in acquiring all requested vectors. */
4313 break;
4314 else if (err < 0)
4315 vectors = 0; /* Nasty failure, quit now */
4316 else /* err == number of vectors we should try again with */
4317 vectors = err;
4318 }
4319
4320 if (vectors < vector_threshold) {
4321 /* Can't allocate enough MSI-X interrupts? Oh well.
4322 * This just means we'll go with either a single MSI
4323 * vector or fall back to legacy interrupts.
4324 */
4325 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4326 "Unable to allocate MSI-X interrupts\n");
4327 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4328 kfree(adapter->msix_entries);
4329 adapter->msix_entries = NULL;
4330 } else {
4331 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4332 /*
4333 * Adjust for only the vectors we'll use, which is minimum
4334 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4335 * vectors we were allocated.
4336 */
4337 adapter->num_msix_vectors = min(vectors,
4338 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4339 }
4340 }
4341
4342 /**
4343 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4344 * @adapter: board private structure to initialize
4345 *
4346 * Cache the descriptor ring offsets for RSS to the assigned rings.
4347 *
4348 **/
4349 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4350 {
4351 int i;
4352
4353 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4354 return false;
4355
4356 for (i = 0; i < adapter->num_rx_queues; i++)
4357 adapter->rx_ring[i]->reg_idx = i;
4358 for (i = 0; i < adapter->num_tx_queues; i++)
4359 adapter->tx_ring[i]->reg_idx = i;
4360
4361 return true;
4362 }
4363
4364 #ifdef CONFIG_IXGBE_DCB
4365
4366 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4367 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4368 unsigned int *tx, unsigned int *rx)
4369 {
4370 struct net_device *dev = adapter->netdev;
4371 struct ixgbe_hw *hw = &adapter->hw;
4372 u8 num_tcs = netdev_get_num_tc(dev);
4373
4374 *tx = 0;
4375 *rx = 0;
4376
4377 switch (hw->mac.type) {
4378 case ixgbe_mac_82598EB:
4379 *tx = tc << 2;
4380 *rx = tc << 3;
4381 break;
4382 case ixgbe_mac_82599EB:
4383 case ixgbe_mac_X540:
4384 if (num_tcs > 4) {
4385 if (tc < 3) {
4386 *tx = tc << 5;
4387 *rx = tc << 4;
4388 } else if (tc < 5) {
4389 *tx = ((tc + 2) << 4);
4390 *rx = tc << 4;
4391 } else if (tc < num_tcs) {
4392 *tx = ((tc + 8) << 3);
4393 *rx = tc << 4;
4394 }
4395 } else {
4396 *rx = tc << 5;
4397 switch (tc) {
4398 case 0:
4399 *tx = 0;
4400 break;
4401 case 1:
4402 *tx = 64;
4403 break;
4404 case 2:
4405 *tx = 96;
4406 break;
4407 case 3:
4408 *tx = 112;
4409 break;
4410 default:
4411 break;
4412 }
4413 }
4414 break;
4415 default:
4416 break;
4417 }
4418 }
4419
4420 /**
4421 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4422 * @adapter: board private structure to initialize
4423 *
4424 * Cache the descriptor ring offsets for DCB to the assigned rings.
4425 *
4426 **/
4427 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4428 {
4429 struct net_device *dev = adapter->netdev;
4430 int i, j, k;
4431 u8 num_tcs = netdev_get_num_tc(dev);
4432
4433 if (!num_tcs)
4434 return false;
4435
4436 for (i = 0, k = 0; i < num_tcs; i++) {
4437 unsigned int tx_s, rx_s;
4438 u16 count = dev->tc_to_txq[i].count;
4439
4440 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4441 for (j = 0; j < count; j++, k++) {
4442 adapter->tx_ring[k]->reg_idx = tx_s + j;
4443 adapter->rx_ring[k]->reg_idx = rx_s + j;
4444 adapter->tx_ring[k]->dcb_tc = i;
4445 adapter->rx_ring[k]->dcb_tc = i;
4446 }
4447 }
4448
4449 return true;
4450 }
4451 #endif
4452
4453 /**
4454 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4455 * @adapter: board private structure to initialize
4456 *
4457 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4458 *
4459 **/
4460 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4461 {
4462 int i;
4463 bool ret = false;
4464
4465 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4466 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4467 for (i = 0; i < adapter->num_rx_queues; i++)
4468 adapter->rx_ring[i]->reg_idx = i;
4469 for (i = 0; i < adapter->num_tx_queues; i++)
4470 adapter->tx_ring[i]->reg_idx = i;
4471 ret = true;
4472 }
4473
4474 return ret;
4475 }
4476
4477 #ifdef IXGBE_FCOE
4478 /**
4479 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4480 * @adapter: board private structure to initialize
4481 *
4482 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4483 *
4484 */
4485 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4486 {
4487 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4488 int i;
4489 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4490
4491 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4492 return false;
4493
4494 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4495 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4496 ixgbe_cache_ring_fdir(adapter);
4497 else
4498 ixgbe_cache_ring_rss(adapter);
4499
4500 fcoe_rx_i = f->mask;
4501 fcoe_tx_i = f->mask;
4502 }
4503 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4504 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4505 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4506 }
4507 return true;
4508 }
4509
4510 #endif /* IXGBE_FCOE */
4511 /**
4512 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4513 * @adapter: board private structure to initialize
4514 *
4515 * SR-IOV doesn't use any descriptor rings but changes the default if
4516 * no other mapping is used.
4517 *
4518 */
4519 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4520 {
4521 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4522 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4523 if (adapter->num_vfs)
4524 return true;
4525 else
4526 return false;
4527 }
4528
4529 /**
4530 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4531 * @adapter: board private structure to initialize
4532 *
4533 * Once we know the feature-set enabled for the device, we'll cache
4534 * the register offset the descriptor ring is assigned to.
4535 *
4536 * Note, the order the various feature calls is important. It must start with
4537 * the "most" features enabled at the same time, then trickle down to the
4538 * least amount of features turned on at once.
4539 **/
4540 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4541 {
4542 /* start with default case */
4543 adapter->rx_ring[0]->reg_idx = 0;
4544 adapter->tx_ring[0]->reg_idx = 0;
4545
4546 if (ixgbe_cache_ring_sriov(adapter))
4547 return;
4548
4549 #ifdef CONFIG_IXGBE_DCB
4550 if (ixgbe_cache_ring_dcb(adapter))
4551 return;
4552 #endif
4553
4554 #ifdef IXGBE_FCOE
4555 if (ixgbe_cache_ring_fcoe(adapter))
4556 return;
4557 #endif /* IXGBE_FCOE */
4558
4559 if (ixgbe_cache_ring_fdir(adapter))
4560 return;
4561
4562 if (ixgbe_cache_ring_rss(adapter))
4563 return;
4564 }
4565
4566 /**
4567 * ixgbe_alloc_queues - Allocate memory for all rings
4568 * @adapter: board private structure to initialize
4569 *
4570 * We allocate one ring per queue at run-time since we don't know the
4571 * number of queues at compile-time. The polling_netdev array is
4572 * intended for Multiqueue, but should work fine with a single queue.
4573 **/
4574 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4575 {
4576 int rx = 0, tx = 0, nid = adapter->node;
4577
4578 if (nid < 0 || !node_online(nid))
4579 nid = first_online_node;
4580
4581 for (; tx < adapter->num_tx_queues; tx++) {
4582 struct ixgbe_ring *ring;
4583
4584 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4585 if (!ring)
4586 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4587 if (!ring)
4588 goto err_allocation;
4589 ring->count = adapter->tx_ring_count;
4590 ring->queue_index = tx;
4591 ring->numa_node = nid;
4592 ring->dev = &adapter->pdev->dev;
4593 ring->netdev = adapter->netdev;
4594
4595 adapter->tx_ring[tx] = ring;
4596 }
4597
4598 for (; rx < adapter->num_rx_queues; rx++) {
4599 struct ixgbe_ring *ring;
4600
4601 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4602 if (!ring)
4603 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4604 if (!ring)
4605 goto err_allocation;
4606 ring->count = adapter->rx_ring_count;
4607 ring->queue_index = rx;
4608 ring->numa_node = nid;
4609 ring->dev = &adapter->pdev->dev;
4610 ring->netdev = adapter->netdev;
4611
4612 adapter->rx_ring[rx] = ring;
4613 }
4614
4615 ixgbe_cache_ring_register(adapter);
4616
4617 return 0;
4618
4619 err_allocation:
4620 while (tx)
4621 kfree(adapter->tx_ring[--tx]);
4622
4623 while (rx)
4624 kfree(adapter->rx_ring[--rx]);
4625 return -ENOMEM;
4626 }
4627
4628 /**
4629 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4630 * @adapter: board private structure to initialize
4631 *
4632 * Attempt to configure the interrupts using the best available
4633 * capabilities of the hardware and the kernel.
4634 **/
4635 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4636 {
4637 struct ixgbe_hw *hw = &adapter->hw;
4638 int err = 0;
4639 int vector, v_budget;
4640
4641 /*
4642 * It's easy to be greedy for MSI-X vectors, but it really
4643 * doesn't do us much good if we have a lot more vectors
4644 * than CPU's. So let's be conservative and only ask for
4645 * (roughly) the same number of vectors as there are CPU's.
4646 */
4647 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4648 (int)num_online_cpus()) + NON_Q_VECTORS;
4649
4650 /*
4651 * At the same time, hardware can only support a maximum of
4652 * hw.mac->max_msix_vectors vectors. With features
4653 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4654 * descriptor queues supported by our device. Thus, we cap it off in
4655 * those rare cases where the cpu count also exceeds our vector limit.
4656 */
4657 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4658
4659 /* A failure in MSI-X entry allocation isn't fatal, but it does
4660 * mean we disable MSI-X capabilities of the adapter. */
4661 adapter->msix_entries = kcalloc(v_budget,
4662 sizeof(struct msix_entry), GFP_KERNEL);
4663 if (adapter->msix_entries) {
4664 for (vector = 0; vector < v_budget; vector++)
4665 adapter->msix_entries[vector].entry = vector;
4666
4667 ixgbe_acquire_msix_vectors(adapter, v_budget);
4668
4669 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4670 goto out;
4671 }
4672
4673 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4674 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4675 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4676 e_err(probe,
4677 "ATR is not supported while multiple "
4678 "queues are disabled. Disabling Flow Director\n");
4679 }
4680 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4681 adapter->atr_sample_rate = 0;
4682 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4683 ixgbe_disable_sriov(adapter);
4684
4685 err = ixgbe_set_num_queues(adapter);
4686 if (err)
4687 return err;
4688
4689 err = pci_enable_msi(adapter->pdev);
4690 if (!err) {
4691 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4692 } else {
4693 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4694 "Unable to allocate MSI interrupt, "
4695 "falling back to legacy. Error: %d\n", err);
4696 /* reset err */
4697 err = 0;
4698 }
4699
4700 out:
4701 return err;
4702 }
4703
4704 /**
4705 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4706 * @adapter: board private structure to initialize
4707 *
4708 * We allocate one q_vector per queue interrupt. If allocation fails we
4709 * return -ENOMEM.
4710 **/
4711 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4712 {
4713 int v_idx, num_q_vectors;
4714 struct ixgbe_q_vector *q_vector;
4715
4716 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4717 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4718 else
4719 num_q_vectors = 1;
4720
4721 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4722 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4723 GFP_KERNEL, adapter->node);
4724 if (!q_vector)
4725 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4726 GFP_KERNEL);
4727 if (!q_vector)
4728 goto err_out;
4729
4730 q_vector->adapter = adapter;
4731 q_vector->v_idx = v_idx;
4732
4733 /* Allocate the affinity_hint cpumask, configure the mask */
4734 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4735 goto err_out;
4736 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4737 netif_napi_add(adapter->netdev, &q_vector->napi,
4738 ixgbe_poll, 64);
4739 adapter->q_vector[v_idx] = q_vector;
4740 }
4741
4742 return 0;
4743
4744 err_out:
4745 while (v_idx) {
4746 v_idx--;
4747 q_vector = adapter->q_vector[v_idx];
4748 netif_napi_del(&q_vector->napi);
4749 free_cpumask_var(q_vector->affinity_mask);
4750 kfree(q_vector);
4751 adapter->q_vector[v_idx] = NULL;
4752 }
4753 return -ENOMEM;
4754 }
4755
4756 /**
4757 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4758 * @adapter: board private structure to initialize
4759 *
4760 * This function frees the memory allocated to the q_vectors. In addition if
4761 * NAPI is enabled it will delete any references to the NAPI struct prior
4762 * to freeing the q_vector.
4763 **/
4764 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4765 {
4766 int v_idx, num_q_vectors;
4767
4768 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4769 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4770 else
4771 num_q_vectors = 1;
4772
4773 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4774 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4775 adapter->q_vector[v_idx] = NULL;
4776 netif_napi_del(&q_vector->napi);
4777 free_cpumask_var(q_vector->affinity_mask);
4778 kfree(q_vector);
4779 }
4780 }
4781
4782 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4783 {
4784 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4785 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4786 pci_disable_msix(adapter->pdev);
4787 kfree(adapter->msix_entries);
4788 adapter->msix_entries = NULL;
4789 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4790 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4791 pci_disable_msi(adapter->pdev);
4792 }
4793 }
4794
4795 /**
4796 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4797 * @adapter: board private structure to initialize
4798 *
4799 * We determine which interrupt scheme to use based on...
4800 * - Kernel support (MSI, MSI-X)
4801 * - which can be user-defined (via MODULE_PARAM)
4802 * - Hardware queue count (num_*_queues)
4803 * - defined by miscellaneous hardware support/features (RSS, etc.)
4804 **/
4805 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4806 {
4807 int err;
4808
4809 /* Number of supported queues */
4810 err = ixgbe_set_num_queues(adapter);
4811 if (err)
4812 return err;
4813
4814 err = ixgbe_set_interrupt_capability(adapter);
4815 if (err) {
4816 e_dev_err("Unable to setup interrupt capabilities\n");
4817 goto err_set_interrupt;
4818 }
4819
4820 err = ixgbe_alloc_q_vectors(adapter);
4821 if (err) {
4822 e_dev_err("Unable to allocate memory for queue vectors\n");
4823 goto err_alloc_q_vectors;
4824 }
4825
4826 err = ixgbe_alloc_queues(adapter);
4827 if (err) {
4828 e_dev_err("Unable to allocate memory for queues\n");
4829 goto err_alloc_queues;
4830 }
4831
4832 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4833 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4834 adapter->num_rx_queues, adapter->num_tx_queues);
4835
4836 set_bit(__IXGBE_DOWN, &adapter->state);
4837
4838 return 0;
4839
4840 err_alloc_queues:
4841 ixgbe_free_q_vectors(adapter);
4842 err_alloc_q_vectors:
4843 ixgbe_reset_interrupt_capability(adapter);
4844 err_set_interrupt:
4845 return err;
4846 }
4847
4848 /**
4849 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4850 * @adapter: board private structure to clear interrupt scheme on
4851 *
4852 * We go through and clear interrupt specific resources and reset the structure
4853 * to pre-load conditions
4854 **/
4855 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4856 {
4857 int i;
4858
4859 for (i = 0; i < adapter->num_tx_queues; i++) {
4860 kfree(adapter->tx_ring[i]);
4861 adapter->tx_ring[i] = NULL;
4862 }
4863 for (i = 0; i < adapter->num_rx_queues; i++) {
4864 struct ixgbe_ring *ring = adapter->rx_ring[i];
4865
4866 /* ixgbe_get_stats64() might access this ring, we must wait
4867 * a grace period before freeing it.
4868 */
4869 kfree_rcu(ring, rcu);
4870 adapter->rx_ring[i] = NULL;
4871 }
4872
4873 adapter->num_tx_queues = 0;
4874 adapter->num_rx_queues = 0;
4875
4876 ixgbe_free_q_vectors(adapter);
4877 ixgbe_reset_interrupt_capability(adapter);
4878 }
4879
4880 /**
4881 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4882 * @adapter: board private structure to initialize
4883 *
4884 * ixgbe_sw_init initializes the Adapter private data structure.
4885 * Fields are initialized based on PCI device information and
4886 * OS network device settings (MTU size).
4887 **/
4888 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4889 {
4890 struct ixgbe_hw *hw = &adapter->hw;
4891 struct pci_dev *pdev = adapter->pdev;
4892 unsigned int rss;
4893 #ifdef CONFIG_IXGBE_DCB
4894 int j;
4895 struct tc_configuration *tc;
4896 #endif
4897
4898 /* PCI config space info */
4899
4900 hw->vendor_id = pdev->vendor;
4901 hw->device_id = pdev->device;
4902 hw->revision_id = pdev->revision;
4903 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4904 hw->subsystem_device_id = pdev->subsystem_device;
4905
4906 /* Set capability flags */
4907 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4908 adapter->ring_feature[RING_F_RSS].indices = rss;
4909 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4910 switch (hw->mac.type) {
4911 case ixgbe_mac_82598EB:
4912 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4913 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4914 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4915 break;
4916 case ixgbe_mac_82599EB:
4917 case ixgbe_mac_X540:
4918 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4919 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4920 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4921 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4922 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4923 /* Flow Director hash filters enabled */
4924 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4925 adapter->atr_sample_rate = 20;
4926 adapter->ring_feature[RING_F_FDIR].indices =
4927 IXGBE_MAX_FDIR_INDICES;
4928 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4929 #ifdef IXGBE_FCOE
4930 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4931 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4932 adapter->ring_feature[RING_F_FCOE].indices = 0;
4933 #ifdef CONFIG_IXGBE_DCB
4934 /* Default traffic class to use for FCoE */
4935 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4936 #endif
4937 #endif /* IXGBE_FCOE */
4938 break;
4939 default:
4940 break;
4941 }
4942
4943 /* n-tuple support exists, always init our spinlock */
4944 spin_lock_init(&adapter->fdir_perfect_lock);
4945
4946 #ifdef CONFIG_IXGBE_DCB
4947 /* Configure DCB traffic classes */
4948 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4949 tc = &adapter->dcb_cfg.tc_config[j];
4950 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4951 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4952 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4953 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4954 tc->dcb_pfc = pfc_disabled;
4955 }
4956 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4957 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4958 adapter->dcb_cfg.pfc_mode_enable = false;
4959 adapter->dcb_set_bitmap = 0x00;
4960 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4961 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4962 MAX_TRAFFIC_CLASS);
4963
4964 #endif
4965
4966 /* default flow control settings */
4967 hw->fc.requested_mode = ixgbe_fc_full;
4968 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4969 #ifdef CONFIG_DCB
4970 adapter->last_lfc_mode = hw->fc.current_mode;
4971 #endif
4972 ixgbe_pbthresh_setup(adapter);
4973 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4974 hw->fc.send_xon = true;
4975 hw->fc.disable_fc_autoneg = false;
4976
4977 /* enable itr by default in dynamic mode */
4978 adapter->rx_itr_setting = 1;
4979 adapter->tx_itr_setting = 1;
4980
4981 /* set defaults for eitr in MegaBytes */
4982 adapter->eitr_low = 10;
4983 adapter->eitr_high = 20;
4984
4985 /* set default ring sizes */
4986 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4987 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4988
4989 /* set default work limits */
4990 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4991
4992 /* initialize eeprom parameters */
4993 if (ixgbe_init_eeprom_params_generic(hw)) {
4994 e_dev_err("EEPROM initialization failed\n");
4995 return -EIO;
4996 }
4997
4998 /* enable rx csum by default */
4999 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5000
5001 /* get assigned NUMA node */
5002 adapter->node = dev_to_node(&pdev->dev);
5003
5004 set_bit(__IXGBE_DOWN, &adapter->state);
5005
5006 return 0;
5007 }
5008
5009 /**
5010 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5011 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5012 *
5013 * Return 0 on success, negative on failure
5014 **/
5015 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5016 {
5017 struct device *dev = tx_ring->dev;
5018 int size;
5019
5020 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5021 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5022 if (!tx_ring->tx_buffer_info)
5023 tx_ring->tx_buffer_info = vzalloc(size);
5024 if (!tx_ring->tx_buffer_info)
5025 goto err;
5026
5027 /* round up to nearest 4K */
5028 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5029 tx_ring->size = ALIGN(tx_ring->size, 4096);
5030
5031 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5032 &tx_ring->dma, GFP_KERNEL);
5033 if (!tx_ring->desc)
5034 goto err;
5035
5036 tx_ring->next_to_use = 0;
5037 tx_ring->next_to_clean = 0;
5038 return 0;
5039
5040 err:
5041 vfree(tx_ring->tx_buffer_info);
5042 tx_ring->tx_buffer_info = NULL;
5043 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5044 return -ENOMEM;
5045 }
5046
5047 /**
5048 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5049 * @adapter: board private structure
5050 *
5051 * If this function returns with an error, then it's possible one or
5052 * more of the rings is populated (while the rest are not). It is the
5053 * callers duty to clean those orphaned rings.
5054 *
5055 * Return 0 on success, negative on failure
5056 **/
5057 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5058 {
5059 int i, err = 0;
5060
5061 for (i = 0; i < adapter->num_tx_queues; i++) {
5062 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5063 if (!err)
5064 continue;
5065 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5066 break;
5067 }
5068
5069 return err;
5070 }
5071
5072 /**
5073 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5074 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5075 *
5076 * Returns 0 on success, negative on failure
5077 **/
5078 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5079 {
5080 struct device *dev = rx_ring->dev;
5081 int size;
5082
5083 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5084 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5085 if (!rx_ring->rx_buffer_info)
5086 rx_ring->rx_buffer_info = vzalloc(size);
5087 if (!rx_ring->rx_buffer_info)
5088 goto err;
5089
5090 /* Round up to nearest 4K */
5091 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5092 rx_ring->size = ALIGN(rx_ring->size, 4096);
5093
5094 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5095 &rx_ring->dma, GFP_KERNEL);
5096
5097 if (!rx_ring->desc)
5098 goto err;
5099
5100 rx_ring->next_to_clean = 0;
5101 rx_ring->next_to_use = 0;
5102
5103 return 0;
5104 err:
5105 vfree(rx_ring->rx_buffer_info);
5106 rx_ring->rx_buffer_info = NULL;
5107 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5108 return -ENOMEM;
5109 }
5110
5111 /**
5112 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5113 * @adapter: board private structure
5114 *
5115 * If this function returns with an error, then it's possible one or
5116 * more of the rings is populated (while the rest are not). It is the
5117 * callers duty to clean those orphaned rings.
5118 *
5119 * Return 0 on success, negative on failure
5120 **/
5121 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5122 {
5123 int i, err = 0;
5124
5125 for (i = 0; i < adapter->num_rx_queues; i++) {
5126 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5127 if (!err)
5128 continue;
5129 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5130 break;
5131 }
5132
5133 return err;
5134 }
5135
5136 /**
5137 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5138 * @tx_ring: Tx descriptor ring for a specific queue
5139 *
5140 * Free all transmit software resources
5141 **/
5142 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5143 {
5144 ixgbe_clean_tx_ring(tx_ring);
5145
5146 vfree(tx_ring->tx_buffer_info);
5147 tx_ring->tx_buffer_info = NULL;
5148
5149 /* if not set, then don't free */
5150 if (!tx_ring->desc)
5151 return;
5152
5153 dma_free_coherent(tx_ring->dev, tx_ring->size,
5154 tx_ring->desc, tx_ring->dma);
5155
5156 tx_ring->desc = NULL;
5157 }
5158
5159 /**
5160 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5161 * @adapter: board private structure
5162 *
5163 * Free all transmit software resources
5164 **/
5165 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5166 {
5167 int i;
5168
5169 for (i = 0; i < adapter->num_tx_queues; i++)
5170 if (adapter->tx_ring[i]->desc)
5171 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5172 }
5173
5174 /**
5175 * ixgbe_free_rx_resources - Free Rx Resources
5176 * @rx_ring: ring to clean the resources from
5177 *
5178 * Free all receive software resources
5179 **/
5180 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5181 {
5182 ixgbe_clean_rx_ring(rx_ring);
5183
5184 vfree(rx_ring->rx_buffer_info);
5185 rx_ring->rx_buffer_info = NULL;
5186
5187 /* if not set, then don't free */
5188 if (!rx_ring->desc)
5189 return;
5190
5191 dma_free_coherent(rx_ring->dev, rx_ring->size,
5192 rx_ring->desc, rx_ring->dma);
5193
5194 rx_ring->desc = NULL;
5195 }
5196
5197 /**
5198 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5199 * @adapter: board private structure
5200 *
5201 * Free all receive software resources
5202 **/
5203 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5204 {
5205 int i;
5206
5207 for (i = 0; i < adapter->num_rx_queues; i++)
5208 if (adapter->rx_ring[i]->desc)
5209 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5210 }
5211
5212 /**
5213 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5214 * @netdev: network interface device structure
5215 * @new_mtu: new value for maximum frame size
5216 *
5217 * Returns 0 on success, negative on failure
5218 **/
5219 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5220 {
5221 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5222 struct ixgbe_hw *hw = &adapter->hw;
5223 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5224
5225 /* MTU < 68 is an error and causes problems on some kernels */
5226 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5227 hw->mac.type != ixgbe_mac_X540) {
5228 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5229 return -EINVAL;
5230 } else {
5231 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5232 return -EINVAL;
5233 }
5234
5235 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5236 /* must set new MTU before calling down or up */
5237 netdev->mtu = new_mtu;
5238
5239 if (netif_running(netdev))
5240 ixgbe_reinit_locked(adapter);
5241
5242 return 0;
5243 }
5244
5245 /**
5246 * ixgbe_open - Called when a network interface is made active
5247 * @netdev: network interface device structure
5248 *
5249 * Returns 0 on success, negative value on failure
5250 *
5251 * The open entry point is called when a network interface is made
5252 * active by the system (IFF_UP). At this point all resources needed
5253 * for transmit and receive operations are allocated, the interrupt
5254 * handler is registered with the OS, the watchdog timer is started,
5255 * and the stack is notified that the interface is ready.
5256 **/
5257 static int ixgbe_open(struct net_device *netdev)
5258 {
5259 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5260 int err;
5261
5262 /* disallow open during test */
5263 if (test_bit(__IXGBE_TESTING, &adapter->state))
5264 return -EBUSY;
5265
5266 netif_carrier_off(netdev);
5267
5268 /* allocate transmit descriptors */
5269 err = ixgbe_setup_all_tx_resources(adapter);
5270 if (err)
5271 goto err_setup_tx;
5272
5273 /* allocate receive descriptors */
5274 err = ixgbe_setup_all_rx_resources(adapter);
5275 if (err)
5276 goto err_setup_rx;
5277
5278 ixgbe_configure(adapter);
5279
5280 err = ixgbe_request_irq(adapter);
5281 if (err)
5282 goto err_req_irq;
5283
5284 ixgbe_up_complete(adapter);
5285
5286 return 0;
5287
5288 err_req_irq:
5289 err_setup_rx:
5290 ixgbe_free_all_rx_resources(adapter);
5291 err_setup_tx:
5292 ixgbe_free_all_tx_resources(adapter);
5293 ixgbe_reset(adapter);
5294
5295 return err;
5296 }
5297
5298 /**
5299 * ixgbe_close - Disables a network interface
5300 * @netdev: network interface device structure
5301 *
5302 * Returns 0, this is not allowed to fail
5303 *
5304 * The close entry point is called when an interface is de-activated
5305 * by the OS. The hardware is still under the drivers control, but
5306 * needs to be disabled. A global MAC reset is issued to stop the
5307 * hardware, and all transmit and receive resources are freed.
5308 **/
5309 static int ixgbe_close(struct net_device *netdev)
5310 {
5311 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5312
5313 ixgbe_down(adapter);
5314 ixgbe_free_irq(adapter);
5315
5316 ixgbe_fdir_filter_exit(adapter);
5317
5318 ixgbe_free_all_tx_resources(adapter);
5319 ixgbe_free_all_rx_resources(adapter);
5320
5321 ixgbe_release_hw_control(adapter);
5322
5323 return 0;
5324 }
5325
5326 #ifdef CONFIG_PM
5327 static int ixgbe_resume(struct pci_dev *pdev)
5328 {
5329 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5330 struct net_device *netdev = adapter->netdev;
5331 u32 err;
5332
5333 pci_set_power_state(pdev, PCI_D0);
5334 pci_restore_state(pdev);
5335 /*
5336 * pci_restore_state clears dev->state_saved so call
5337 * pci_save_state to restore it.
5338 */
5339 pci_save_state(pdev);
5340
5341 err = pci_enable_device_mem(pdev);
5342 if (err) {
5343 e_dev_err("Cannot enable PCI device from suspend\n");
5344 return err;
5345 }
5346 pci_set_master(pdev);
5347
5348 pci_wake_from_d3(pdev, false);
5349
5350 err = ixgbe_init_interrupt_scheme(adapter);
5351 if (err) {
5352 e_dev_err("Cannot initialize interrupts for device\n");
5353 return err;
5354 }
5355
5356 ixgbe_reset(adapter);
5357
5358 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5359
5360 if (netif_running(netdev)) {
5361 err = ixgbe_open(netdev);
5362 if (err)
5363 return err;
5364 }
5365
5366 netif_device_attach(netdev);
5367
5368 return 0;
5369 }
5370 #endif /* CONFIG_PM */
5371
5372 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5373 {
5374 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5375 struct net_device *netdev = adapter->netdev;
5376 struct ixgbe_hw *hw = &adapter->hw;
5377 u32 ctrl, fctrl;
5378 u32 wufc = adapter->wol;
5379 #ifdef CONFIG_PM
5380 int retval = 0;
5381 #endif
5382
5383 netif_device_detach(netdev);
5384
5385 if (netif_running(netdev)) {
5386 ixgbe_down(adapter);
5387 ixgbe_free_irq(adapter);
5388 ixgbe_free_all_tx_resources(adapter);
5389 ixgbe_free_all_rx_resources(adapter);
5390 }
5391
5392 ixgbe_clear_interrupt_scheme(adapter);
5393 #ifdef CONFIG_DCB
5394 kfree(adapter->ixgbe_ieee_pfc);
5395 kfree(adapter->ixgbe_ieee_ets);
5396 #endif
5397
5398 #ifdef CONFIG_PM
5399 retval = pci_save_state(pdev);
5400 if (retval)
5401 return retval;
5402
5403 #endif
5404 if (wufc) {
5405 ixgbe_set_rx_mode(netdev);
5406
5407 /* turn on all-multi mode if wake on multicast is enabled */
5408 if (wufc & IXGBE_WUFC_MC) {
5409 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5410 fctrl |= IXGBE_FCTRL_MPE;
5411 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5412 }
5413
5414 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5415 ctrl |= IXGBE_CTRL_GIO_DIS;
5416 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5417
5418 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5419 } else {
5420 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5421 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5422 }
5423
5424 switch (hw->mac.type) {
5425 case ixgbe_mac_82598EB:
5426 pci_wake_from_d3(pdev, false);
5427 break;
5428 case ixgbe_mac_82599EB:
5429 case ixgbe_mac_X540:
5430 pci_wake_from_d3(pdev, !!wufc);
5431 break;
5432 default:
5433 break;
5434 }
5435
5436 *enable_wake = !!wufc;
5437
5438 ixgbe_release_hw_control(adapter);
5439
5440 pci_disable_device(pdev);
5441
5442 return 0;
5443 }
5444
5445 #ifdef CONFIG_PM
5446 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5447 {
5448 int retval;
5449 bool wake;
5450
5451 retval = __ixgbe_shutdown(pdev, &wake);
5452 if (retval)
5453 return retval;
5454
5455 if (wake) {
5456 pci_prepare_to_sleep(pdev);
5457 } else {
5458 pci_wake_from_d3(pdev, false);
5459 pci_set_power_state(pdev, PCI_D3hot);
5460 }
5461
5462 return 0;
5463 }
5464 #endif /* CONFIG_PM */
5465
5466 static void ixgbe_shutdown(struct pci_dev *pdev)
5467 {
5468 bool wake;
5469
5470 __ixgbe_shutdown(pdev, &wake);
5471
5472 if (system_state == SYSTEM_POWER_OFF) {
5473 pci_wake_from_d3(pdev, wake);
5474 pci_set_power_state(pdev, PCI_D3hot);
5475 }
5476 }
5477
5478 /**
5479 * ixgbe_update_stats - Update the board statistics counters.
5480 * @adapter: board private structure
5481 **/
5482 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5483 {
5484 struct net_device *netdev = adapter->netdev;
5485 struct ixgbe_hw *hw = &adapter->hw;
5486 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5487 u64 total_mpc = 0;
5488 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5489 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5490 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5491 u64 bytes = 0, packets = 0;
5492
5493 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5494 test_bit(__IXGBE_RESETTING, &adapter->state))
5495 return;
5496
5497 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5498 u64 rsc_count = 0;
5499 u64 rsc_flush = 0;
5500 for (i = 0; i < 16; i++)
5501 adapter->hw_rx_no_dma_resources +=
5502 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5503 for (i = 0; i < adapter->num_rx_queues; i++) {
5504 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5505 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5506 }
5507 adapter->rsc_total_count = rsc_count;
5508 adapter->rsc_total_flush = rsc_flush;
5509 }
5510
5511 for (i = 0; i < adapter->num_rx_queues; i++) {
5512 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5513 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5514 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5515 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5516 bytes += rx_ring->stats.bytes;
5517 packets += rx_ring->stats.packets;
5518 }
5519 adapter->non_eop_descs = non_eop_descs;
5520 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5521 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5522 netdev->stats.rx_bytes = bytes;
5523 netdev->stats.rx_packets = packets;
5524
5525 bytes = 0;
5526 packets = 0;
5527 /* gather some stats to the adapter struct that are per queue */
5528 for (i = 0; i < adapter->num_tx_queues; i++) {
5529 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5530 restart_queue += tx_ring->tx_stats.restart_queue;
5531 tx_busy += tx_ring->tx_stats.tx_busy;
5532 bytes += tx_ring->stats.bytes;
5533 packets += tx_ring->stats.packets;
5534 }
5535 adapter->restart_queue = restart_queue;
5536 adapter->tx_busy = tx_busy;
5537 netdev->stats.tx_bytes = bytes;
5538 netdev->stats.tx_packets = packets;
5539
5540 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5541
5542 /* 8 register reads */
5543 for (i = 0; i < 8; i++) {
5544 /* for packet buffers not used, the register should read 0 */
5545 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5546 missed_rx += mpc;
5547 hwstats->mpc[i] += mpc;
5548 total_mpc += hwstats->mpc[i];
5549 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5550 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5551 switch (hw->mac.type) {
5552 case ixgbe_mac_82598EB:
5553 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5554 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5555 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5556 hwstats->pxonrxc[i] +=
5557 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5558 break;
5559 case ixgbe_mac_82599EB:
5560 case ixgbe_mac_X540:
5561 hwstats->pxonrxc[i] +=
5562 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5563 break;
5564 default:
5565 break;
5566 }
5567 }
5568
5569 /*16 register reads */
5570 for (i = 0; i < 16; i++) {
5571 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5572 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5573 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5574 (hw->mac.type == ixgbe_mac_X540)) {
5575 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5576 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5577 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5578 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5579 }
5580 }
5581
5582 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5583 /* work around hardware counting issue */
5584 hwstats->gprc -= missed_rx;
5585
5586 ixgbe_update_xoff_received(adapter);
5587
5588 /* 82598 hardware only has a 32 bit counter in the high register */
5589 switch (hw->mac.type) {
5590 case ixgbe_mac_82598EB:
5591 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5592 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5593 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5594 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5595 break;
5596 case ixgbe_mac_X540:
5597 /* OS2BMC stats are X540 only*/
5598 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5599 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5600 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5601 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5602 case ixgbe_mac_82599EB:
5603 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5604 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5605 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5606 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5607 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5608 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5609 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5610 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5611 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5612 #ifdef IXGBE_FCOE
5613 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5614 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5615 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5616 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5617 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5618 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5619 #endif /* IXGBE_FCOE */
5620 break;
5621 default:
5622 break;
5623 }
5624 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5625 hwstats->bprc += bprc;
5626 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5627 if (hw->mac.type == ixgbe_mac_82598EB)
5628 hwstats->mprc -= bprc;
5629 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5630 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5631 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5632 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5633 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5634 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5635 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5636 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5637 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5638 hwstats->lxontxc += lxon;
5639 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5640 hwstats->lxofftxc += lxoff;
5641 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5642 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5643 /*
5644 * 82598 errata - tx of flow control packets is included in tx counters
5645 */
5646 xon_off_tot = lxon + lxoff;
5647 hwstats->gptc -= xon_off_tot;
5648 hwstats->mptc -= xon_off_tot;
5649 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5650 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5651 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5652 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5653 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5654 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5655 hwstats->ptc64 -= xon_off_tot;
5656 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5657 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5658 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5659 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5660 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5661 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5662
5663 /* Fill out the OS statistics structure */
5664 netdev->stats.multicast = hwstats->mprc;
5665
5666 /* Rx Errors */
5667 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5668 netdev->stats.rx_dropped = 0;
5669 netdev->stats.rx_length_errors = hwstats->rlec;
5670 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5671 netdev->stats.rx_missed_errors = total_mpc;
5672 }
5673
5674 /**
5675 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5676 * @adapter - pointer to the device adapter structure
5677 **/
5678 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5679 {
5680 struct ixgbe_hw *hw = &adapter->hw;
5681 int i;
5682
5683 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5684 return;
5685
5686 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5687
5688 /* if interface is down do nothing */
5689 if (test_bit(__IXGBE_DOWN, &adapter->state))
5690 return;
5691
5692 /* do nothing if we are not using signature filters */
5693 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5694 return;
5695
5696 adapter->fdir_overflow++;
5697
5698 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5699 for (i = 0; i < adapter->num_tx_queues; i++)
5700 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5701 &(adapter->tx_ring[i]->state));
5702 /* re-enable flow director interrupts */
5703 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5704 } else {
5705 e_err(probe, "failed to finish FDIR re-initialization, "
5706 "ignored adding FDIR ATR filters\n");
5707 }
5708 }
5709
5710 /**
5711 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5712 * @adapter - pointer to the device adapter structure
5713 *
5714 * This function serves two purposes. First it strobes the interrupt lines
5715 * in order to make certain interrupts are occuring. Secondly it sets the
5716 * bits needed to check for TX hangs. As a result we should immediately
5717 * determine if a hang has occured.
5718 */
5719 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5720 {
5721 struct ixgbe_hw *hw = &adapter->hw;
5722 u64 eics = 0;
5723 int i;
5724
5725 /* If we're down or resetting, just bail */
5726 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5727 test_bit(__IXGBE_RESETTING, &adapter->state))
5728 return;
5729
5730 /* Force detection of hung controller */
5731 if (netif_carrier_ok(adapter->netdev)) {
5732 for (i = 0; i < adapter->num_tx_queues; i++)
5733 set_check_for_tx_hang(adapter->tx_ring[i]);
5734 }
5735
5736 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5737 /*
5738 * for legacy and MSI interrupts don't set any bits
5739 * that are enabled for EIAM, because this operation
5740 * would set *both* EIMS and EICS for any bit in EIAM
5741 */
5742 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5743 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5744 } else {
5745 /* get one bit for every active tx/rx interrupt vector */
5746 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5747 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5748 if (qv->rx.ring || qv->tx.ring)
5749 eics |= ((u64)1 << i);
5750 }
5751 }
5752
5753 /* Cause software interrupt to ensure rings are cleaned */
5754 ixgbe_irq_rearm_queues(adapter, eics);
5755
5756 }
5757
5758 /**
5759 * ixgbe_watchdog_update_link - update the link status
5760 * @adapter - pointer to the device adapter structure
5761 * @link_speed - pointer to a u32 to store the link_speed
5762 **/
5763 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5764 {
5765 struct ixgbe_hw *hw = &adapter->hw;
5766 u32 link_speed = adapter->link_speed;
5767 bool link_up = adapter->link_up;
5768 int i;
5769
5770 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5771 return;
5772
5773 if (hw->mac.ops.check_link) {
5774 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5775 } else {
5776 /* always assume link is up, if no check link function */
5777 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5778 link_up = true;
5779 }
5780 if (link_up) {
5781 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5782 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5783 hw->mac.ops.fc_enable(hw, i);
5784 } else {
5785 hw->mac.ops.fc_enable(hw, 0);
5786 }
5787 }
5788
5789 if (link_up ||
5790 time_after(jiffies, (adapter->link_check_timeout +
5791 IXGBE_TRY_LINK_TIMEOUT))) {
5792 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5793 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5794 IXGBE_WRITE_FLUSH(hw);
5795 }
5796
5797 adapter->link_up = link_up;
5798 adapter->link_speed = link_speed;
5799 }
5800
5801 /**
5802 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5803 * print link up message
5804 * @adapter - pointer to the device adapter structure
5805 **/
5806 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5807 {
5808 struct net_device *netdev = adapter->netdev;
5809 struct ixgbe_hw *hw = &adapter->hw;
5810 u32 link_speed = adapter->link_speed;
5811 bool flow_rx, flow_tx;
5812
5813 /* only continue if link was previously down */
5814 if (netif_carrier_ok(netdev))
5815 return;
5816
5817 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5818
5819 switch (hw->mac.type) {
5820 case ixgbe_mac_82598EB: {
5821 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5822 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5823 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5824 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5825 }
5826 break;
5827 case ixgbe_mac_X540:
5828 case ixgbe_mac_82599EB: {
5829 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5830 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5831 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5832 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5833 }
5834 break;
5835 default:
5836 flow_tx = false;
5837 flow_rx = false;
5838 break;
5839 }
5840 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5841 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5842 "10 Gbps" :
5843 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5844 "1 Gbps" :
5845 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5846 "100 Mbps" :
5847 "unknown speed"))),
5848 ((flow_rx && flow_tx) ? "RX/TX" :
5849 (flow_rx ? "RX" :
5850 (flow_tx ? "TX" : "None"))));
5851
5852 netif_carrier_on(netdev);
5853 ixgbe_check_vf_rate_limit(adapter);
5854 }
5855
5856 /**
5857 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5858 * print link down message
5859 * @adapter - pointer to the adapter structure
5860 **/
5861 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
5862 {
5863 struct net_device *netdev = adapter->netdev;
5864 struct ixgbe_hw *hw = &adapter->hw;
5865
5866 adapter->link_up = false;
5867 adapter->link_speed = 0;
5868
5869 /* only continue if link was up previously */
5870 if (!netif_carrier_ok(netdev))
5871 return;
5872
5873 /* poll for SFP+ cable when link is down */
5874 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5875 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5876
5877 e_info(drv, "NIC Link is Down\n");
5878 netif_carrier_off(netdev);
5879 }
5880
5881 /**
5882 * ixgbe_watchdog_flush_tx - flush queues on link down
5883 * @adapter - pointer to the device adapter structure
5884 **/
5885 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5886 {
5887 int i;
5888 int some_tx_pending = 0;
5889
5890 if (!netif_carrier_ok(adapter->netdev)) {
5891 for (i = 0; i < adapter->num_tx_queues; i++) {
5892 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5893 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5894 some_tx_pending = 1;
5895 break;
5896 }
5897 }
5898
5899 if (some_tx_pending) {
5900 /* We've lost link, so the controller stops DMA,
5901 * but we've got queued Tx work that's never going
5902 * to get done, so reset controller to flush Tx.
5903 * (Do the reset outside of interrupt context).
5904 */
5905 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5906 }
5907 }
5908 }
5909
5910 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5911 {
5912 u32 ssvpc;
5913
5914 /* Do not perform spoof check for 82598 */
5915 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5916 return;
5917
5918 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5919
5920 /*
5921 * ssvpc register is cleared on read, if zero then no
5922 * spoofed packets in the last interval.
5923 */
5924 if (!ssvpc)
5925 return;
5926
5927 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5928 }
5929
5930 /**
5931 * ixgbe_watchdog_subtask - check and bring link up
5932 * @adapter - pointer to the device adapter structure
5933 **/
5934 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5935 {
5936 /* if interface is down do nothing */
5937 if (test_bit(__IXGBE_DOWN, &adapter->state))
5938 return;
5939
5940 ixgbe_watchdog_update_link(adapter);
5941
5942 if (adapter->link_up)
5943 ixgbe_watchdog_link_is_up(adapter);
5944 else
5945 ixgbe_watchdog_link_is_down(adapter);
5946
5947 ixgbe_spoof_check(adapter);
5948 ixgbe_update_stats(adapter);
5949
5950 ixgbe_watchdog_flush_tx(adapter);
5951 }
5952
5953 /**
5954 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5955 * @adapter - the ixgbe adapter structure
5956 **/
5957 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5958 {
5959 struct ixgbe_hw *hw = &adapter->hw;
5960 s32 err;
5961
5962 /* not searching for SFP so there is nothing to do here */
5963 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5964 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5965 return;
5966
5967 /* someone else is in init, wait until next service event */
5968 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5969 return;
5970
5971 err = hw->phy.ops.identify_sfp(hw);
5972 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5973 goto sfp_out;
5974
5975 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5976 /* If no cable is present, then we need to reset
5977 * the next time we find a good cable. */
5978 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5979 }
5980
5981 /* exit on error */
5982 if (err)
5983 goto sfp_out;
5984
5985 /* exit if reset not needed */
5986 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5987 goto sfp_out;
5988
5989 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5990
5991 /*
5992 * A module may be identified correctly, but the EEPROM may not have
5993 * support for that module. setup_sfp() will fail in that case, so
5994 * we should not allow that module to load.
5995 */
5996 if (hw->mac.type == ixgbe_mac_82598EB)
5997 err = hw->phy.ops.reset(hw);
5998 else
5999 err = hw->mac.ops.setup_sfp(hw);
6000
6001 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6002 goto sfp_out;
6003
6004 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6005 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6006
6007 sfp_out:
6008 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6009
6010 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6011 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6012 e_dev_err("failed to initialize because an unsupported "
6013 "SFP+ module type was detected.\n");
6014 e_dev_err("Reload the driver after installing a "
6015 "supported module.\n");
6016 unregister_netdev(adapter->netdev);
6017 }
6018 }
6019
6020 /**
6021 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6022 * @adapter - the ixgbe adapter structure
6023 **/
6024 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6025 {
6026 struct ixgbe_hw *hw = &adapter->hw;
6027 u32 autoneg;
6028 bool negotiation;
6029
6030 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6031 return;
6032
6033 /* someone else is in init, wait until next service event */
6034 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6035 return;
6036
6037 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6038
6039 autoneg = hw->phy.autoneg_advertised;
6040 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6041 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6042 hw->mac.autotry_restart = false;
6043 if (hw->mac.ops.setup_link)
6044 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6045
6046 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6047 adapter->link_check_timeout = jiffies;
6048 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6049 }
6050
6051 /**
6052 * ixgbe_service_timer - Timer Call-back
6053 * @data: pointer to adapter cast into an unsigned long
6054 **/
6055 static void ixgbe_service_timer(unsigned long data)
6056 {
6057 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6058 unsigned long next_event_offset;
6059
6060 /* poll faster when waiting for link */
6061 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6062 next_event_offset = HZ / 10;
6063 else
6064 next_event_offset = HZ * 2;
6065
6066 /* Reset the timer */
6067 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6068
6069 ixgbe_service_event_schedule(adapter);
6070 }
6071
6072 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6073 {
6074 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6075 return;
6076
6077 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6078
6079 /* If we're already down or resetting, just bail */
6080 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6081 test_bit(__IXGBE_RESETTING, &adapter->state))
6082 return;
6083
6084 ixgbe_dump(adapter);
6085 netdev_err(adapter->netdev, "Reset adapter\n");
6086 adapter->tx_timeout_count++;
6087
6088 ixgbe_reinit_locked(adapter);
6089 }
6090
6091 /**
6092 * ixgbe_service_task - manages and runs subtasks
6093 * @work: pointer to work_struct containing our data
6094 **/
6095 static void ixgbe_service_task(struct work_struct *work)
6096 {
6097 struct ixgbe_adapter *adapter = container_of(work,
6098 struct ixgbe_adapter,
6099 service_task);
6100
6101 ixgbe_reset_subtask(adapter);
6102 ixgbe_sfp_detection_subtask(adapter);
6103 ixgbe_sfp_link_config_subtask(adapter);
6104 ixgbe_check_overtemp_subtask(adapter);
6105 ixgbe_watchdog_subtask(adapter);
6106 ixgbe_fdir_reinit_subtask(adapter);
6107 ixgbe_check_hang_subtask(adapter);
6108
6109 ixgbe_service_event_complete(adapter);
6110 }
6111
6112 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6113 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6114 {
6115 struct ixgbe_adv_tx_context_desc *context_desc;
6116 u16 i = tx_ring->next_to_use;
6117
6118 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6119
6120 i++;
6121 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6122
6123 /* set bits to identify this as an advanced context descriptor */
6124 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6125
6126 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6127 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6128 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6129 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6130 }
6131
6132 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6133 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6134 {
6135 int err;
6136 u32 vlan_macip_lens, type_tucmd;
6137 u32 mss_l4len_idx, l4len;
6138
6139 if (!skb_is_gso(skb))
6140 return 0;
6141
6142 if (skb_header_cloned(skb)) {
6143 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6144 if (err)
6145 return err;
6146 }
6147
6148 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6149 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6150
6151 if (protocol == __constant_htons(ETH_P_IP)) {
6152 struct iphdr *iph = ip_hdr(skb);
6153 iph->tot_len = 0;
6154 iph->check = 0;
6155 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6156 iph->daddr, 0,
6157 IPPROTO_TCP,
6158 0);
6159 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6160 } else if (skb_is_gso_v6(skb)) {
6161 ipv6_hdr(skb)->payload_len = 0;
6162 tcp_hdr(skb)->check =
6163 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6164 &ipv6_hdr(skb)->daddr,
6165 0, IPPROTO_TCP, 0);
6166 }
6167
6168 l4len = tcp_hdrlen(skb);
6169 *hdr_len = skb_transport_offset(skb) + l4len;
6170
6171 /* mss_l4len_id: use 1 as index for TSO */
6172 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6173 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6174 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6175
6176 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6177 vlan_macip_lens = skb_network_header_len(skb);
6178 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6179 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6180
6181 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6182 mss_l4len_idx);
6183
6184 return 1;
6185 }
6186
6187 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6188 struct sk_buff *skb, u32 tx_flags,
6189 __be16 protocol)
6190 {
6191 u32 vlan_macip_lens = 0;
6192 u32 mss_l4len_idx = 0;
6193 u32 type_tucmd = 0;
6194
6195 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6196 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6197 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
6198 return false;
6199 } else {
6200 u8 l4_hdr = 0;
6201 switch (protocol) {
6202 case __constant_htons(ETH_P_IP):
6203 vlan_macip_lens |= skb_network_header_len(skb);
6204 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6205 l4_hdr = ip_hdr(skb)->protocol;
6206 break;
6207 case __constant_htons(ETH_P_IPV6):
6208 vlan_macip_lens |= skb_network_header_len(skb);
6209 l4_hdr = ipv6_hdr(skb)->nexthdr;
6210 break;
6211 default:
6212 if (unlikely(net_ratelimit())) {
6213 dev_warn(tx_ring->dev,
6214 "partial checksum but proto=%x!\n",
6215 skb->protocol);
6216 }
6217 break;
6218 }
6219
6220 switch (l4_hdr) {
6221 case IPPROTO_TCP:
6222 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6223 mss_l4len_idx = tcp_hdrlen(skb) <<
6224 IXGBE_ADVTXD_L4LEN_SHIFT;
6225 break;
6226 case IPPROTO_SCTP:
6227 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6228 mss_l4len_idx = sizeof(struct sctphdr) <<
6229 IXGBE_ADVTXD_L4LEN_SHIFT;
6230 break;
6231 case IPPROTO_UDP:
6232 mss_l4len_idx = sizeof(struct udphdr) <<
6233 IXGBE_ADVTXD_L4LEN_SHIFT;
6234 break;
6235 default:
6236 if (unlikely(net_ratelimit())) {
6237 dev_warn(tx_ring->dev,
6238 "partial checksum but l4 proto=%x!\n",
6239 skb->protocol);
6240 }
6241 break;
6242 }
6243 }
6244
6245 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6246 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6247
6248 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6249 type_tucmd, mss_l4len_idx);
6250
6251 return (skb->ip_summed == CHECKSUM_PARTIAL);
6252 }
6253
6254 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6255 {
6256 /* set type for advanced descriptor with frame checksum insertion */
6257 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6258 IXGBE_ADVTXD_DCMD_IFCS |
6259 IXGBE_ADVTXD_DCMD_DEXT);
6260
6261 /* set HW vlan bit if vlan is present */
6262 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6263 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6264
6265 /* set segmentation enable bits for TSO/FSO */
6266 #ifdef IXGBE_FCOE
6267 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6268 #else
6269 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6270 #endif
6271 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6272
6273 return cmd_type;
6274 }
6275
6276 static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6277 {
6278 __le32 olinfo_status =
6279 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6280
6281 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6282 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6283 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6284 /* enble IPv4 checksum for TSO */
6285 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6286 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6287 }
6288
6289 /* enable L4 checksum for TSO and TX checksum offload */
6290 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6291 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6292
6293 #ifdef IXGBE_FCOE
6294 /* use index 1 context for FCOE/FSO */
6295 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6296 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6297 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6298
6299 #endif
6300 /*
6301 * Check Context must be set if Tx switch is enabled, which it
6302 * always is for case where virtual functions are running
6303 */
6304 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6305 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6306
6307 return olinfo_status;
6308 }
6309
6310 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6311 IXGBE_TXD_CMD_RS)
6312
6313 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6314 struct sk_buff *skb,
6315 struct ixgbe_tx_buffer *first,
6316 u32 tx_flags,
6317 const u8 hdr_len)
6318 {
6319 struct device *dev = tx_ring->dev;
6320 struct ixgbe_tx_buffer *tx_buffer_info;
6321 union ixgbe_adv_tx_desc *tx_desc;
6322 dma_addr_t dma;
6323 __le32 cmd_type, olinfo_status;
6324 struct skb_frag_struct *frag;
6325 unsigned int f = 0;
6326 unsigned int data_len = skb->data_len;
6327 unsigned int size = skb_headlen(skb);
6328 u32 offset = 0;
6329 u32 paylen = skb->len - hdr_len;
6330 u16 i = tx_ring->next_to_use;
6331 u16 gso_segs;
6332
6333 #ifdef IXGBE_FCOE
6334 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6335 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6336 data_len -= sizeof(struct fcoe_crc_eof);
6337 } else {
6338 size -= sizeof(struct fcoe_crc_eof) - data_len;
6339 data_len = 0;
6340 }
6341 }
6342
6343 #endif
6344 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6345 if (dma_mapping_error(dev, dma))
6346 goto dma_error;
6347
6348 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6349 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
6350
6351 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6352
6353 for (;;) {
6354 while (size > IXGBE_MAX_DATA_PER_TXD) {
6355 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6356 tx_desc->read.cmd_type_len =
6357 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6358 tx_desc->read.olinfo_status = olinfo_status;
6359
6360 offset += IXGBE_MAX_DATA_PER_TXD;
6361 size -= IXGBE_MAX_DATA_PER_TXD;
6362
6363 tx_desc++;
6364 i++;
6365 if (i == tx_ring->count) {
6366 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6367 i = 0;
6368 }
6369 }
6370
6371 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6372 tx_buffer_info->length = offset + size;
6373 tx_buffer_info->tx_flags = tx_flags;
6374 tx_buffer_info->dma = dma;
6375
6376 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6377 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6378 tx_desc->read.olinfo_status = olinfo_status;
6379
6380 if (!data_len)
6381 break;
6382
6383 frag = &skb_shinfo(skb)->frags[f];
6384 #ifdef IXGBE_FCOE
6385 size = min_t(unsigned int, data_len, frag->size);
6386 #else
6387 size = frag->size;
6388 #endif
6389 data_len -= size;
6390 f++;
6391
6392 offset = 0;
6393 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
6394
6395 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
6396 if (dma_mapping_error(dev, dma))
6397 goto dma_error;
6398
6399 tx_desc++;
6400 i++;
6401 if (i == tx_ring->count) {
6402 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6403 i = 0;
6404 }
6405 }
6406
6407 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
6408
6409 i++;
6410 if (i == tx_ring->count)
6411 i = 0;
6412
6413 tx_ring->next_to_use = i;
6414
6415 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6416 gso_segs = skb_shinfo(skb)->gso_segs;
6417 #ifdef IXGBE_FCOE
6418 /* adjust for FCoE Sequence Offload */
6419 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6420 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6421 skb_shinfo(skb)->gso_size);
6422 #endif /* IXGBE_FCOE */
6423 else
6424 gso_segs = 1;
6425
6426 /* multiply data chunks by size of headers */
6427 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6428 tx_buffer_info->gso_segs = gso_segs;
6429 tx_buffer_info->skb = skb;
6430
6431 /* set the timestamp */
6432 first->time_stamp = jiffies;
6433
6434 /*
6435 * Force memory writes to complete before letting h/w
6436 * know there are new descriptors to fetch. (Only
6437 * applicable for weak-ordered memory model archs,
6438 * such as IA-64).
6439 */
6440 wmb();
6441
6442 /* set next_to_watch value indicating a packet is present */
6443 first->next_to_watch = tx_desc;
6444
6445 /* notify HW of packet */
6446 writel(i, tx_ring->tail);
6447
6448 return;
6449 dma_error:
6450 dev_err(dev, "TX DMA map failed\n");
6451
6452 /* clear dma mappings for failed tx_buffer_info map */
6453 for (;;) {
6454 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6455 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6456 if (tx_buffer_info == first)
6457 break;
6458 if (i == 0)
6459 i = tx_ring->count;
6460 i--;
6461 }
6462
6463 dev_kfree_skb_any(skb);
6464
6465 tx_ring->next_to_use = i;
6466 }
6467
6468 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6469 u32 tx_flags, __be16 protocol)
6470 {
6471 struct ixgbe_q_vector *q_vector = ring->q_vector;
6472 union ixgbe_atr_hash_dword input = { .dword = 0 };
6473 union ixgbe_atr_hash_dword common = { .dword = 0 };
6474 union {
6475 unsigned char *network;
6476 struct iphdr *ipv4;
6477 struct ipv6hdr *ipv6;
6478 } hdr;
6479 struct tcphdr *th;
6480 __be16 vlan_id;
6481
6482 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6483 if (!q_vector)
6484 return;
6485
6486 /* do nothing if sampling is disabled */
6487 if (!ring->atr_sample_rate)
6488 return;
6489
6490 ring->atr_count++;
6491
6492 /* snag network header to get L4 type and address */
6493 hdr.network = skb_network_header(skb);
6494
6495 /* Currently only IPv4/IPv6 with TCP is supported */
6496 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6497 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6498 (protocol != __constant_htons(ETH_P_IP) ||
6499 hdr.ipv4->protocol != IPPROTO_TCP))
6500 return;
6501
6502 th = tcp_hdr(skb);
6503
6504 /* skip this packet since it is invalid or the socket is closing */
6505 if (!th || th->fin)
6506 return;
6507
6508 /* sample on all syn packets or once every atr sample count */
6509 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6510 return;
6511
6512 /* reset sample count */
6513 ring->atr_count = 0;
6514
6515 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6516
6517 /*
6518 * src and dst are inverted, think how the receiver sees them
6519 *
6520 * The input is broken into two sections, a non-compressed section
6521 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6522 * is XORed together and stored in the compressed dword.
6523 */
6524 input.formatted.vlan_id = vlan_id;
6525
6526 /*
6527 * since src port and flex bytes occupy the same word XOR them together
6528 * and write the value to source port portion of compressed dword
6529 */
6530 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6531 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6532 else
6533 common.port.src ^= th->dest ^ protocol;
6534 common.port.dst ^= th->source;
6535
6536 if (protocol == __constant_htons(ETH_P_IP)) {
6537 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6538 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6539 } else {
6540 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6541 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6542 hdr.ipv6->saddr.s6_addr32[1] ^
6543 hdr.ipv6->saddr.s6_addr32[2] ^
6544 hdr.ipv6->saddr.s6_addr32[3] ^
6545 hdr.ipv6->daddr.s6_addr32[0] ^
6546 hdr.ipv6->daddr.s6_addr32[1] ^
6547 hdr.ipv6->daddr.s6_addr32[2] ^
6548 hdr.ipv6->daddr.s6_addr32[3];
6549 }
6550
6551 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6552 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6553 input, common, ring->queue_index);
6554 }
6555
6556 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6557 {
6558 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6559 /* Herbert's original patch had:
6560 * smp_mb__after_netif_stop_queue();
6561 * but since that doesn't exist yet, just open code it. */
6562 smp_mb();
6563
6564 /* We need to check again in a case another CPU has just
6565 * made room available. */
6566 if (likely(ixgbe_desc_unused(tx_ring) < size))
6567 return -EBUSY;
6568
6569 /* A reprieve! - use start_queue because it doesn't call schedule */
6570 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6571 ++tx_ring->tx_stats.restart_queue;
6572 return 0;
6573 }
6574
6575 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6576 {
6577 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6578 return 0;
6579 return __ixgbe_maybe_stop_tx(tx_ring, size);
6580 }
6581
6582 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6583 {
6584 struct ixgbe_adapter *adapter = netdev_priv(dev);
6585 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6586 smp_processor_id();
6587 #ifdef IXGBE_FCOE
6588 __be16 protocol = vlan_get_protocol(skb);
6589
6590 if (((protocol == htons(ETH_P_FCOE)) ||
6591 (protocol == htons(ETH_P_FIP))) &&
6592 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6593 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6594 txq += adapter->ring_feature[RING_F_FCOE].mask;
6595 return txq;
6596 }
6597 #endif
6598
6599 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6600 while (unlikely(txq >= dev->real_num_tx_queues))
6601 txq -= dev->real_num_tx_queues;
6602 return txq;
6603 }
6604
6605 return skb_tx_hash(dev, skb);
6606 }
6607
6608 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6609 struct ixgbe_adapter *adapter,
6610 struct ixgbe_ring *tx_ring)
6611 {
6612 struct ixgbe_tx_buffer *first;
6613 int tso;
6614 u32 tx_flags = 0;
6615 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6616 unsigned short f;
6617 #endif
6618 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6619 __be16 protocol = skb->protocol;
6620 u8 hdr_len = 0;
6621
6622 /*
6623 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6624 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6625 * + 2 desc gap to keep tail from touching head,
6626 * + 1 desc for context descriptor,
6627 * otherwise try next time
6628 */
6629 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6630 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6631 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6632 #else
6633 count += skb_shinfo(skb)->nr_frags;
6634 #endif
6635 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6636 tx_ring->tx_stats.tx_busy++;
6637 return NETDEV_TX_BUSY;
6638 }
6639
6640 #ifdef CONFIG_PCI_IOV
6641 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6642 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6643
6644 #endif
6645 /* if we have a HW VLAN tag being added default to the HW one */
6646 if (vlan_tx_tag_present(skb)) {
6647 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6648 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6649 /* else if it is a SW VLAN check the next protocol and store the tag */
6650 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6651 struct vlan_hdr *vhdr, _vhdr;
6652 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6653 if (!vhdr)
6654 goto out_drop;
6655
6656 protocol = vhdr->h_vlan_encapsulated_proto;
6657 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6658 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6659 }
6660
6661 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6662 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6663 (skb->priority != TC_PRIO_CONTROL))) {
6664 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6665 tx_flags |= tx_ring->dcb_tc <<
6666 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6667 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6668 struct vlan_ethhdr *vhdr;
6669 if (skb_header_cloned(skb) &&
6670 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6671 goto out_drop;
6672 vhdr = (struct vlan_ethhdr *)skb->data;
6673 vhdr->h_vlan_TCI = htons(tx_flags >>
6674 IXGBE_TX_FLAGS_VLAN_SHIFT);
6675 } else {
6676 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6677 }
6678 }
6679
6680 /* record the location of the first descriptor for this packet */
6681 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6682
6683 #ifdef IXGBE_FCOE
6684 /* setup tx offload for FCoE */
6685 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6686 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6687 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6688 if (tso < 0)
6689 goto out_drop;
6690 else if (tso)
6691 tx_flags |= IXGBE_TX_FLAGS_FSO |
6692 IXGBE_TX_FLAGS_FCOE;
6693 else
6694 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6695
6696 goto xmit_fcoe;
6697 }
6698
6699 #endif /* IXGBE_FCOE */
6700 /* setup IPv4/IPv6 offloads */
6701 if (protocol == __constant_htons(ETH_P_IP))
6702 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6703
6704 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6705 if (tso < 0)
6706 goto out_drop;
6707 else if (tso)
6708 tx_flags |= IXGBE_TX_FLAGS_TSO;
6709 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6710 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6711
6712 /* add the ATR filter if ATR is on */
6713 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6714 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6715
6716 #ifdef IXGBE_FCOE
6717 xmit_fcoe:
6718 #endif /* IXGBE_FCOE */
6719 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6720
6721 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6722
6723 return NETDEV_TX_OK;
6724
6725 out_drop:
6726 dev_kfree_skb_any(skb);
6727 return NETDEV_TX_OK;
6728 }
6729
6730 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6731 {
6732 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6733 struct ixgbe_ring *tx_ring;
6734
6735 tx_ring = adapter->tx_ring[skb->queue_mapping];
6736 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6737 }
6738
6739 /**
6740 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6741 * @netdev: network interface device structure
6742 * @p: pointer to an address structure
6743 *
6744 * Returns 0 on success, negative on failure
6745 **/
6746 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6747 {
6748 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6749 struct ixgbe_hw *hw = &adapter->hw;
6750 struct sockaddr *addr = p;
6751
6752 if (!is_valid_ether_addr(addr->sa_data))
6753 return -EADDRNOTAVAIL;
6754
6755 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6756 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6757
6758 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6759 IXGBE_RAH_AV);
6760
6761 return 0;
6762 }
6763
6764 static int
6765 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6766 {
6767 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6768 struct ixgbe_hw *hw = &adapter->hw;
6769 u16 value;
6770 int rc;
6771
6772 if (prtad != hw->phy.mdio.prtad)
6773 return -EINVAL;
6774 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6775 if (!rc)
6776 rc = value;
6777 return rc;
6778 }
6779
6780 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6781 u16 addr, u16 value)
6782 {
6783 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6784 struct ixgbe_hw *hw = &adapter->hw;
6785
6786 if (prtad != hw->phy.mdio.prtad)
6787 return -EINVAL;
6788 return hw->phy.ops.write_reg(hw, addr, devad, value);
6789 }
6790
6791 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6792 {
6793 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6794
6795 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6796 }
6797
6798 /**
6799 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6800 * netdev->dev_addrs
6801 * @netdev: network interface device structure
6802 *
6803 * Returns non-zero on failure
6804 **/
6805 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6806 {
6807 int err = 0;
6808 struct ixgbe_adapter *adapter = netdev_priv(dev);
6809 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6810
6811 if (is_valid_ether_addr(mac->san_addr)) {
6812 rtnl_lock();
6813 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6814 rtnl_unlock();
6815 }
6816 return err;
6817 }
6818
6819 /**
6820 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6821 * netdev->dev_addrs
6822 * @netdev: network interface device structure
6823 *
6824 * Returns non-zero on failure
6825 **/
6826 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6827 {
6828 int err = 0;
6829 struct ixgbe_adapter *adapter = netdev_priv(dev);
6830 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6831
6832 if (is_valid_ether_addr(mac->san_addr)) {
6833 rtnl_lock();
6834 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6835 rtnl_unlock();
6836 }
6837 return err;
6838 }
6839
6840 #ifdef CONFIG_NET_POLL_CONTROLLER
6841 /*
6842 * Polling 'interrupt' - used by things like netconsole to send skbs
6843 * without having to re-enable interrupts. It's not called while
6844 * the interrupt routine is executing.
6845 */
6846 static void ixgbe_netpoll(struct net_device *netdev)
6847 {
6848 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6849 int i;
6850
6851 /* if interface is down do nothing */
6852 if (test_bit(__IXGBE_DOWN, &adapter->state))
6853 return;
6854
6855 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6856 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6857 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6858 for (i = 0; i < num_q_vectors; i++) {
6859 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6860 ixgbe_msix_clean_rings(0, q_vector);
6861 }
6862 } else {
6863 ixgbe_intr(adapter->pdev->irq, netdev);
6864 }
6865 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6866 }
6867 #endif
6868
6869 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6870 struct rtnl_link_stats64 *stats)
6871 {
6872 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6873 int i;
6874
6875 rcu_read_lock();
6876 for (i = 0; i < adapter->num_rx_queues; i++) {
6877 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6878 u64 bytes, packets;
6879 unsigned int start;
6880
6881 if (ring) {
6882 do {
6883 start = u64_stats_fetch_begin_bh(&ring->syncp);
6884 packets = ring->stats.packets;
6885 bytes = ring->stats.bytes;
6886 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6887 stats->rx_packets += packets;
6888 stats->rx_bytes += bytes;
6889 }
6890 }
6891
6892 for (i = 0; i < adapter->num_tx_queues; i++) {
6893 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6894 u64 bytes, packets;
6895 unsigned int start;
6896
6897 if (ring) {
6898 do {
6899 start = u64_stats_fetch_begin_bh(&ring->syncp);
6900 packets = ring->stats.packets;
6901 bytes = ring->stats.bytes;
6902 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6903 stats->tx_packets += packets;
6904 stats->tx_bytes += bytes;
6905 }
6906 }
6907 rcu_read_unlock();
6908 /* following stats updated by ixgbe_watchdog_task() */
6909 stats->multicast = netdev->stats.multicast;
6910 stats->rx_errors = netdev->stats.rx_errors;
6911 stats->rx_length_errors = netdev->stats.rx_length_errors;
6912 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6913 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6914 return stats;
6915 }
6916
6917 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6918 * #adapter: pointer to ixgbe_adapter
6919 * @tc: number of traffic classes currently enabled
6920 *
6921 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6922 * 802.1Q priority maps to a packet buffer that exists.
6923 */
6924 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6925 {
6926 struct ixgbe_hw *hw = &adapter->hw;
6927 u32 reg, rsave;
6928 int i;
6929
6930 /* 82598 have a static priority to TC mapping that can not
6931 * be changed so no validation is needed.
6932 */
6933 if (hw->mac.type == ixgbe_mac_82598EB)
6934 return;
6935
6936 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6937 rsave = reg;
6938
6939 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6940 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6941
6942 /* If up2tc is out of bounds default to zero */
6943 if (up2tc > tc)
6944 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6945 }
6946
6947 if (reg != rsave)
6948 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6949
6950 return;
6951 }
6952
6953
6954 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
6955 * classes.
6956 *
6957 * @netdev: net device to configure
6958 * @tc: number of traffic classes to enable
6959 */
6960 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6961 {
6962 struct ixgbe_adapter *adapter = netdev_priv(dev);
6963 struct ixgbe_hw *hw = &adapter->hw;
6964
6965 /* Multiple traffic classes requires multiple queues */
6966 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6967 e_err(drv, "Enable failed, needs MSI-X\n");
6968 return -EINVAL;
6969 }
6970
6971 /* Hardware supports up to 8 traffic classes */
6972 if (tc > MAX_TRAFFIC_CLASS ||
6973 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
6974 return -EINVAL;
6975
6976 /* Hardware has to reinitialize queues and interrupts to
6977 * match packet buffer alignment. Unfortunantly, the
6978 * hardware is not flexible enough to do this dynamically.
6979 */
6980 if (netif_running(dev))
6981 ixgbe_close(dev);
6982 ixgbe_clear_interrupt_scheme(adapter);
6983
6984 if (tc) {
6985 netdev_set_num_tc(dev, tc);
6986 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
6987
6988 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6989 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6990
6991 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6992 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6993 } else {
6994 netdev_reset_tc(dev);
6995
6996 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6997
6998 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6999 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7000
7001 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7002 adapter->dcb_cfg.pfc_mode_enable = false;
7003 }
7004
7005 ixgbe_init_interrupt_scheme(adapter);
7006 ixgbe_validate_rtr(adapter, tc);
7007 if (netif_running(dev))
7008 ixgbe_open(dev);
7009
7010 return 0;
7011 }
7012
7013 void ixgbe_do_reset(struct net_device *netdev)
7014 {
7015 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7016
7017 if (netif_running(netdev))
7018 ixgbe_reinit_locked(adapter);
7019 else
7020 ixgbe_reset(adapter);
7021 }
7022
7023 static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
7024 {
7025 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7026
7027 #ifdef CONFIG_DCB
7028 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7029 data &= ~NETIF_F_HW_VLAN_RX;
7030 #endif
7031
7032 /* return error if RXHASH is being enabled when RSS is not supported */
7033 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7034 data &= ~NETIF_F_RXHASH;
7035
7036 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7037 if (!(data & NETIF_F_RXCSUM))
7038 data &= ~NETIF_F_LRO;
7039
7040 /* Turn off LRO if not RSC capable or invalid ITR settings */
7041 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7042 data &= ~NETIF_F_LRO;
7043 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7044 (adapter->rx_itr_setting != 1 &&
7045 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7046 data &= ~NETIF_F_LRO;
7047 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7048 }
7049
7050 return data;
7051 }
7052
7053 static int ixgbe_set_features(struct net_device *netdev, u32 data)
7054 {
7055 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7056 bool need_reset = false;
7057
7058 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7059 if (!(data & NETIF_F_RXCSUM))
7060 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7061 else
7062 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7063
7064 /* Make sure RSC matches LRO, reset if change */
7065 if (!!(data & NETIF_F_LRO) !=
7066 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7067 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7068 switch (adapter->hw.mac.type) {
7069 case ixgbe_mac_X540:
7070 case ixgbe_mac_82599EB:
7071 need_reset = true;
7072 break;
7073 default:
7074 break;
7075 }
7076 }
7077
7078 /*
7079 * Check if Flow Director n-tuple support was enabled or disabled. If
7080 * the state changed, we need to reset.
7081 */
7082 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7083 /* turn off ATR, enable perfect filters and reset */
7084 if (data & NETIF_F_NTUPLE) {
7085 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7086 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7087 need_reset = true;
7088 }
7089 } else if (!(data & NETIF_F_NTUPLE)) {
7090 /* turn off Flow Director, set ATR and reset */
7091 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7092 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7093 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7094 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7095 need_reset = true;
7096 }
7097
7098 if (need_reset)
7099 ixgbe_do_reset(netdev);
7100
7101 return 0;
7102
7103 }
7104
7105 static const struct net_device_ops ixgbe_netdev_ops = {
7106 .ndo_open = ixgbe_open,
7107 .ndo_stop = ixgbe_close,
7108 .ndo_start_xmit = ixgbe_xmit_frame,
7109 .ndo_select_queue = ixgbe_select_queue,
7110 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7111 .ndo_validate_addr = eth_validate_addr,
7112 .ndo_set_mac_address = ixgbe_set_mac,
7113 .ndo_change_mtu = ixgbe_change_mtu,
7114 .ndo_tx_timeout = ixgbe_tx_timeout,
7115 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7116 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7117 .ndo_do_ioctl = ixgbe_ioctl,
7118 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7119 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7120 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7121 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7122 .ndo_get_stats64 = ixgbe_get_stats64,
7123 .ndo_setup_tc = ixgbe_setup_tc,
7124 #ifdef CONFIG_NET_POLL_CONTROLLER
7125 .ndo_poll_controller = ixgbe_netpoll,
7126 #endif
7127 #ifdef IXGBE_FCOE
7128 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7129 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7130 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7131 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7132 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7133 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7134 #endif /* IXGBE_FCOE */
7135 .ndo_set_features = ixgbe_set_features,
7136 .ndo_fix_features = ixgbe_fix_features,
7137 };
7138
7139 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7140 const struct ixgbe_info *ii)
7141 {
7142 #ifdef CONFIG_PCI_IOV
7143 struct ixgbe_hw *hw = &adapter->hw;
7144
7145 if (hw->mac.type == ixgbe_mac_82598EB)
7146 return;
7147
7148 /* The 82599 supports up to 64 VFs per physical function
7149 * but this implementation limits allocation to 63 so that
7150 * basic networking resources are still available to the
7151 * physical function
7152 */
7153 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7154 ixgbe_enable_sriov(adapter, ii);
7155 #endif /* CONFIG_PCI_IOV */
7156 }
7157
7158 /**
7159 * ixgbe_probe - Device Initialization Routine
7160 * @pdev: PCI device information struct
7161 * @ent: entry in ixgbe_pci_tbl
7162 *
7163 * Returns 0 on success, negative on failure
7164 *
7165 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7166 * The OS initialization, configuring of the adapter private structure,
7167 * and a hardware reset occur.
7168 **/
7169 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7170 const struct pci_device_id *ent)
7171 {
7172 struct net_device *netdev;
7173 struct ixgbe_adapter *adapter = NULL;
7174 struct ixgbe_hw *hw;
7175 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7176 static int cards_found;
7177 int i, err, pci_using_dac;
7178 u8 part_str[IXGBE_PBANUM_LENGTH];
7179 unsigned int indices = num_possible_cpus();
7180 #ifdef IXGBE_FCOE
7181 u16 device_caps;
7182 #endif
7183 u32 eec;
7184 u16 wol_cap;
7185
7186 /* Catch broken hardware that put the wrong VF device ID in
7187 * the PCIe SR-IOV capability.
7188 */
7189 if (pdev->is_virtfn) {
7190 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7191 pci_name(pdev), pdev->vendor, pdev->device);
7192 return -EINVAL;
7193 }
7194
7195 err = pci_enable_device_mem(pdev);
7196 if (err)
7197 return err;
7198
7199 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7200 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7201 pci_using_dac = 1;
7202 } else {
7203 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7204 if (err) {
7205 err = dma_set_coherent_mask(&pdev->dev,
7206 DMA_BIT_MASK(32));
7207 if (err) {
7208 dev_err(&pdev->dev,
7209 "No usable DMA configuration, aborting\n");
7210 goto err_dma;
7211 }
7212 }
7213 pci_using_dac = 0;
7214 }
7215
7216 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7217 IORESOURCE_MEM), ixgbe_driver_name);
7218 if (err) {
7219 dev_err(&pdev->dev,
7220 "pci_request_selected_regions failed 0x%x\n", err);
7221 goto err_pci_reg;
7222 }
7223
7224 pci_enable_pcie_error_reporting(pdev);
7225
7226 pci_set_master(pdev);
7227 pci_save_state(pdev);
7228
7229 #ifdef CONFIG_IXGBE_DCB
7230 indices *= MAX_TRAFFIC_CLASS;
7231 #endif
7232
7233 if (ii->mac == ixgbe_mac_82598EB)
7234 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7235 else
7236 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7237
7238 #ifdef IXGBE_FCOE
7239 indices += min_t(unsigned int, num_possible_cpus(),
7240 IXGBE_MAX_FCOE_INDICES);
7241 #endif
7242 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7243 if (!netdev) {
7244 err = -ENOMEM;
7245 goto err_alloc_etherdev;
7246 }
7247
7248 SET_NETDEV_DEV(netdev, &pdev->dev);
7249
7250 adapter = netdev_priv(netdev);
7251 pci_set_drvdata(pdev, adapter);
7252
7253 adapter->netdev = netdev;
7254 adapter->pdev = pdev;
7255 hw = &adapter->hw;
7256 hw->back = adapter;
7257 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7258
7259 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7260 pci_resource_len(pdev, 0));
7261 if (!hw->hw_addr) {
7262 err = -EIO;
7263 goto err_ioremap;
7264 }
7265
7266 for (i = 1; i <= 5; i++) {
7267 if (pci_resource_len(pdev, i) == 0)
7268 continue;
7269 }
7270
7271 netdev->netdev_ops = &ixgbe_netdev_ops;
7272 ixgbe_set_ethtool_ops(netdev);
7273 netdev->watchdog_timeo = 5 * HZ;
7274 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7275
7276 adapter->bd_number = cards_found;
7277
7278 /* Setup hw api */
7279 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7280 hw->mac.type = ii->mac;
7281
7282 /* EEPROM */
7283 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7284 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7285 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7286 if (!(eec & (1 << 8)))
7287 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7288
7289 /* PHY */
7290 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7291 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7292 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7293 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7294 hw->phy.mdio.mmds = 0;
7295 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7296 hw->phy.mdio.dev = netdev;
7297 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7298 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7299
7300 ii->get_invariants(hw);
7301
7302 /* setup the private structure */
7303 err = ixgbe_sw_init(adapter);
7304 if (err)
7305 goto err_sw_init;
7306
7307 /* Make it possible the adapter to be woken up via WOL */
7308 switch (adapter->hw.mac.type) {
7309 case ixgbe_mac_82599EB:
7310 case ixgbe_mac_X540:
7311 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7312 break;
7313 default:
7314 break;
7315 }
7316
7317 /*
7318 * If there is a fan on this device and it has failed log the
7319 * failure.
7320 */
7321 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7322 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7323 if (esdp & IXGBE_ESDP_SDP1)
7324 e_crit(probe, "Fan has stopped, replace the adapter\n");
7325 }
7326
7327 /* reset_hw fills in the perm_addr as well */
7328 hw->phy.reset_if_overtemp = true;
7329 err = hw->mac.ops.reset_hw(hw);
7330 hw->phy.reset_if_overtemp = false;
7331 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7332 hw->mac.type == ixgbe_mac_82598EB) {
7333 err = 0;
7334 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7335 e_dev_err("failed to load because an unsupported SFP+ "
7336 "module type was detected.\n");
7337 e_dev_err("Reload the driver after installing a supported "
7338 "module.\n");
7339 goto err_sw_init;
7340 } else if (err) {
7341 e_dev_err("HW Init failed: %d\n", err);
7342 goto err_sw_init;
7343 }
7344
7345 ixgbe_probe_vf(adapter, ii);
7346
7347 netdev->features = NETIF_F_SG |
7348 NETIF_F_IP_CSUM |
7349 NETIF_F_IPV6_CSUM |
7350 NETIF_F_HW_VLAN_TX |
7351 NETIF_F_HW_VLAN_RX |
7352 NETIF_F_HW_VLAN_FILTER |
7353 NETIF_F_TSO |
7354 NETIF_F_TSO6 |
7355 NETIF_F_RXHASH |
7356 NETIF_F_RXCSUM;
7357
7358 netdev->hw_features = netdev->features;
7359
7360 switch (adapter->hw.mac.type) {
7361 case ixgbe_mac_82599EB:
7362 case ixgbe_mac_X540:
7363 netdev->features |= NETIF_F_SCTP_CSUM;
7364 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7365 NETIF_F_NTUPLE;
7366 break;
7367 default:
7368 break;
7369 }
7370
7371 netdev->vlan_features |= NETIF_F_TSO;
7372 netdev->vlan_features |= NETIF_F_TSO6;
7373 netdev->vlan_features |= NETIF_F_IP_CSUM;
7374 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7375 netdev->vlan_features |= NETIF_F_SG;
7376
7377 netdev->priv_flags |= IFF_UNICAST_FLT;
7378
7379 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7380 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7381 IXGBE_FLAG_DCB_ENABLED);
7382
7383 #ifdef CONFIG_IXGBE_DCB
7384 netdev->dcbnl_ops = &dcbnl_ops;
7385 #endif
7386
7387 #ifdef IXGBE_FCOE
7388 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7389 if (hw->mac.ops.get_device_caps) {
7390 hw->mac.ops.get_device_caps(hw, &device_caps);
7391 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7392 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7393 }
7394 }
7395 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7396 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7397 netdev->vlan_features |= NETIF_F_FSO;
7398 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7399 }
7400 #endif /* IXGBE_FCOE */
7401 if (pci_using_dac) {
7402 netdev->features |= NETIF_F_HIGHDMA;
7403 netdev->vlan_features |= NETIF_F_HIGHDMA;
7404 }
7405
7406 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7407 netdev->hw_features |= NETIF_F_LRO;
7408 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7409 netdev->features |= NETIF_F_LRO;
7410
7411 /* make sure the EEPROM is good */
7412 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7413 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7414 err = -EIO;
7415 goto err_eeprom;
7416 }
7417
7418 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7419 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7420
7421 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7422 e_dev_err("invalid MAC address\n");
7423 err = -EIO;
7424 goto err_eeprom;
7425 }
7426
7427 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7428 if (hw->mac.ops.disable_tx_laser &&
7429 ((hw->phy.multispeed_fiber) ||
7430 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7431 (hw->mac.type == ixgbe_mac_82599EB))))
7432 hw->mac.ops.disable_tx_laser(hw);
7433
7434 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7435 (unsigned long) adapter);
7436
7437 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7438 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7439
7440 err = ixgbe_init_interrupt_scheme(adapter);
7441 if (err)
7442 goto err_sw_init;
7443
7444 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7445 netdev->hw_features &= ~NETIF_F_RXHASH;
7446 netdev->features &= ~NETIF_F_RXHASH;
7447 }
7448
7449 /* WOL not supported for all but the following */
7450 adapter->wol = 0;
7451 switch (pdev->device) {
7452 case IXGBE_DEV_ID_82599_SFP:
7453 /* Only this subdevice supports WOL */
7454 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7455 adapter->wol = IXGBE_WUFC_MAG;
7456 break;
7457 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7458 /* All except this subdevice support WOL */
7459 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7460 adapter->wol = IXGBE_WUFC_MAG;
7461 break;
7462 case IXGBE_DEV_ID_82599_KX4:
7463 adapter->wol = IXGBE_WUFC_MAG;
7464 break;
7465 case IXGBE_DEV_ID_X540T:
7466 /* Check eeprom to see if it is enabled */
7467 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7468 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7469
7470 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7471 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7472 (hw->bus.func == 0)))
7473 adapter->wol = IXGBE_WUFC_MAG;
7474 break;
7475 }
7476 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7477
7478 /* pick up the PCI bus settings for reporting later */
7479 hw->mac.ops.get_bus_info(hw);
7480
7481 /* print bus type/speed/width info */
7482 e_dev_info("(PCI Express:%s:%s) %pM\n",
7483 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7484 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7485 "Unknown"),
7486 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7487 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7488 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7489 "Unknown"),
7490 netdev->dev_addr);
7491
7492 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7493 if (err)
7494 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7495 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7496 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7497 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7498 part_str);
7499 else
7500 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7501 hw->mac.type, hw->phy.type, part_str);
7502
7503 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7504 e_dev_warn("PCI-Express bandwidth available for this card is "
7505 "not sufficient for optimal performance.\n");
7506 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7507 "is required.\n");
7508 }
7509
7510 /* save off EEPROM version number */
7511 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7512
7513 /* reset the hardware with the new settings */
7514 err = hw->mac.ops.start_hw(hw);
7515
7516 if (err == IXGBE_ERR_EEPROM_VERSION) {
7517 /* We are running on a pre-production device, log a warning */
7518 e_dev_warn("This device is a pre-production adapter/LOM. "
7519 "Please be aware there may be issues associated "
7520 "with your hardware. If you are experiencing "
7521 "problems please contact your Intel or hardware "
7522 "representative who provided you with this "
7523 "hardware.\n");
7524 }
7525 strcpy(netdev->name, "eth%d");
7526 err = register_netdev(netdev);
7527 if (err)
7528 goto err_register;
7529
7530 /* carrier off reporting is important to ethtool even BEFORE open */
7531 netif_carrier_off(netdev);
7532
7533 #ifdef CONFIG_IXGBE_DCA
7534 if (dca_add_requester(&pdev->dev) == 0) {
7535 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7536 ixgbe_setup_dca(adapter);
7537 }
7538 #endif
7539 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7540 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7541 for (i = 0; i < adapter->num_vfs; i++)
7542 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7543 }
7544
7545 /* Inform firmware of driver version */
7546 if (hw->mac.ops.set_fw_drv_ver)
7547 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7548 FW_CEM_UNUSED_VER);
7549
7550 /* add san mac addr to netdev */
7551 ixgbe_add_sanmac_netdev(netdev);
7552
7553 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7554 cards_found++;
7555 return 0;
7556
7557 err_register:
7558 ixgbe_release_hw_control(adapter);
7559 ixgbe_clear_interrupt_scheme(adapter);
7560 err_sw_init:
7561 err_eeprom:
7562 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7563 ixgbe_disable_sriov(adapter);
7564 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7565 iounmap(hw->hw_addr);
7566 err_ioremap:
7567 free_netdev(netdev);
7568 err_alloc_etherdev:
7569 pci_release_selected_regions(pdev,
7570 pci_select_bars(pdev, IORESOURCE_MEM));
7571 err_pci_reg:
7572 err_dma:
7573 pci_disable_device(pdev);
7574 return err;
7575 }
7576
7577 /**
7578 * ixgbe_remove - Device Removal Routine
7579 * @pdev: PCI device information struct
7580 *
7581 * ixgbe_remove is called by the PCI subsystem to alert the driver
7582 * that it should release a PCI device. The could be caused by a
7583 * Hot-Plug event, or because the driver is going to be removed from
7584 * memory.
7585 **/
7586 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7587 {
7588 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7589 struct net_device *netdev = adapter->netdev;
7590
7591 set_bit(__IXGBE_DOWN, &adapter->state);
7592 cancel_work_sync(&adapter->service_task);
7593
7594 #ifdef CONFIG_IXGBE_DCA
7595 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7596 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7597 dca_remove_requester(&pdev->dev);
7598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7599 }
7600
7601 #endif
7602 #ifdef IXGBE_FCOE
7603 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7604 ixgbe_cleanup_fcoe(adapter);
7605
7606 #endif /* IXGBE_FCOE */
7607
7608 /* remove the added san mac */
7609 ixgbe_del_sanmac_netdev(netdev);
7610
7611 if (netdev->reg_state == NETREG_REGISTERED)
7612 unregister_netdev(netdev);
7613
7614 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7615 if (!(ixgbe_check_vf_assignment(adapter)))
7616 ixgbe_disable_sriov(adapter);
7617 else
7618 e_dev_warn("Unloading driver while VFs are assigned "
7619 "- VFs will not be deallocated\n");
7620 }
7621
7622 ixgbe_clear_interrupt_scheme(adapter);
7623
7624 ixgbe_release_hw_control(adapter);
7625
7626 iounmap(adapter->hw.hw_addr);
7627 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7628 IORESOURCE_MEM));
7629
7630 e_dev_info("complete\n");
7631
7632 free_netdev(netdev);
7633
7634 pci_disable_pcie_error_reporting(pdev);
7635
7636 pci_disable_device(pdev);
7637 }
7638
7639 /**
7640 * ixgbe_io_error_detected - called when PCI error is detected
7641 * @pdev: Pointer to PCI device
7642 * @state: The current pci connection state
7643 *
7644 * This function is called after a PCI bus error affecting
7645 * this device has been detected.
7646 */
7647 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7648 pci_channel_state_t state)
7649 {
7650 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7651 struct net_device *netdev = adapter->netdev;
7652
7653 netif_device_detach(netdev);
7654
7655 if (state == pci_channel_io_perm_failure)
7656 return PCI_ERS_RESULT_DISCONNECT;
7657
7658 if (netif_running(netdev))
7659 ixgbe_down(adapter);
7660 pci_disable_device(pdev);
7661
7662 /* Request a slot reset. */
7663 return PCI_ERS_RESULT_NEED_RESET;
7664 }
7665
7666 /**
7667 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7668 * @pdev: Pointer to PCI device
7669 *
7670 * Restart the card from scratch, as if from a cold-boot.
7671 */
7672 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7673 {
7674 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7675 pci_ers_result_t result;
7676 int err;
7677
7678 if (pci_enable_device_mem(pdev)) {
7679 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7680 result = PCI_ERS_RESULT_DISCONNECT;
7681 } else {
7682 pci_set_master(pdev);
7683 pci_restore_state(pdev);
7684 pci_save_state(pdev);
7685
7686 pci_wake_from_d3(pdev, false);
7687
7688 ixgbe_reset(adapter);
7689 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7690 result = PCI_ERS_RESULT_RECOVERED;
7691 }
7692
7693 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7694 if (err) {
7695 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7696 "failed 0x%0x\n", err);
7697 /* non-fatal, continue */
7698 }
7699
7700 return result;
7701 }
7702
7703 /**
7704 * ixgbe_io_resume - called when traffic can start flowing again.
7705 * @pdev: Pointer to PCI device
7706 *
7707 * This callback is called when the error recovery driver tells us that
7708 * its OK to resume normal operation.
7709 */
7710 static void ixgbe_io_resume(struct pci_dev *pdev)
7711 {
7712 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7713 struct net_device *netdev = adapter->netdev;
7714
7715 if (netif_running(netdev))
7716 ixgbe_up(adapter);
7717
7718 netif_device_attach(netdev);
7719 }
7720
7721 static struct pci_error_handlers ixgbe_err_handler = {
7722 .error_detected = ixgbe_io_error_detected,
7723 .slot_reset = ixgbe_io_slot_reset,
7724 .resume = ixgbe_io_resume,
7725 };
7726
7727 static struct pci_driver ixgbe_driver = {
7728 .name = ixgbe_driver_name,
7729 .id_table = ixgbe_pci_tbl,
7730 .probe = ixgbe_probe,
7731 .remove = __devexit_p(ixgbe_remove),
7732 #ifdef CONFIG_PM
7733 .suspend = ixgbe_suspend,
7734 .resume = ixgbe_resume,
7735 #endif
7736 .shutdown = ixgbe_shutdown,
7737 .err_handler = &ixgbe_err_handler
7738 };
7739
7740 /**
7741 * ixgbe_init_module - Driver Registration Routine
7742 *
7743 * ixgbe_init_module is the first routine called when the driver is
7744 * loaded. All it does is register with the PCI subsystem.
7745 **/
7746 static int __init ixgbe_init_module(void)
7747 {
7748 int ret;
7749 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7750 pr_info("%s\n", ixgbe_copyright);
7751
7752 #ifdef CONFIG_IXGBE_DCA
7753 dca_register_notify(&dca_notifier);
7754 #endif
7755
7756 ret = pci_register_driver(&ixgbe_driver);
7757 return ret;
7758 }
7759
7760 module_init(ixgbe_init_module);
7761
7762 /**
7763 * ixgbe_exit_module - Driver Exit Cleanup Routine
7764 *
7765 * ixgbe_exit_module is called just before the driver is removed
7766 * from memory.
7767 **/
7768 static void __exit ixgbe_exit_module(void)
7769 {
7770 #ifdef CONFIG_IXGBE_DCA
7771 dca_unregister_notify(&dca_notifier);
7772 #endif
7773 pci_unregister_driver(&ixgbe_driver);
7774 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7775 }
7776
7777 #ifdef CONFIG_IXGBE_DCA
7778 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7779 void *p)
7780 {
7781 int ret_val;
7782
7783 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7784 __ixgbe_notify_dca);
7785
7786 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7787 }
7788
7789 #endif /* CONFIG_IXGBE_DCA */
7790
7791 module_exit(ixgbe_exit_module);
7792
7793 /* ixgbe_main.c */
Linux kernel - Deliverables
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