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net: Explicitly initialize u64_stats_sync structures for lockdep
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/if_bridge.h>
48 #include <linux/prefetch.h>
49 #include <scsi/fc/fc_fcoe.h>
50
51 #include "ixgbe.h"
52 #include "ixgbe_common.h"
53 #include "ixgbe_dcb_82599.h"
54 #include "ixgbe_sriov.h"
55
56 char ixgbe_driver_name[] = "ixgbe";
57 static const char ixgbe_driver_string[] =
58 "Intel(R) 10 Gigabit PCI Express Network Driver";
59 #ifdef IXGBE_FCOE
60 char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
62 #else
63 static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
65 #endif
66 #define DRV_VERSION "3.15.1-k"
67 const char ixgbe_driver_version[] = DRV_VERSION;
68 static const char ixgbe_copyright[] =
69 "Copyright (c) 1999-2013 Intel Corporation.";
70
71 static const struct ixgbe_info *ixgbe_info_tbl[] = {
72 [board_82598] = &ixgbe_82598_info,
73 [board_82599] = &ixgbe_82599_info,
74 [board_X540] = &ixgbe_X540_info,
75 };
76
77 /* ixgbe_pci_tbl - PCI Device ID Table
78 *
79 * Wildcard entries (PCI_ANY_ID) should come last
80 * Last entry must be all 0s
81 *
82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
83 * Class, Class Mask, private data (not used) }
84 */
85 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
116 /* required last entry */
117 {0, }
118 };
119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
120
121 #ifdef CONFIG_IXGBE_DCA
122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
123 void *p);
124 static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
126 .next = NULL,
127 .priority = 0
128 };
129 #endif
130
131 #ifdef CONFIG_PCI_IOV
132 static unsigned int max_vfs;
133 module_param(max_vfs, uint, 0);
134 MODULE_PARM_DESC(max_vfs,
135 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
136 #endif /* CONFIG_PCI_IOV */
137
138 static unsigned int allow_unsupported_sfp;
139 module_param(allow_unsupported_sfp, uint, 0);
140 MODULE_PARM_DESC(allow_unsupported_sfp,
141 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
142
143 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
144 static int debug = -1;
145 module_param(debug, int, 0);
146 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
147
148 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
149 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
150 MODULE_LICENSE("GPL");
151 MODULE_VERSION(DRV_VERSION);
152
153 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
154 u32 reg, u16 *value)
155 {
156 int pos = 0;
157 struct pci_dev *parent_dev;
158 struct pci_bus *parent_bus;
159
160 parent_bus = adapter->pdev->bus->parent;
161 if (!parent_bus)
162 return -1;
163
164 parent_dev = parent_bus->self;
165 if (!parent_dev)
166 return -1;
167
168 pos = pci_find_capability(parent_dev, PCI_CAP_ID_EXP);
169 if (!pos)
170 return -1;
171
172 pci_read_config_word(parent_dev, pos + reg, value);
173 return 0;
174 }
175
176 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
177 {
178 struct ixgbe_hw *hw = &adapter->hw;
179 u16 link_status = 0;
180 int err;
181
182 hw->bus.type = ixgbe_bus_type_pci_express;
183
184 /* Get the negotiated link width and speed from PCI config space of the
185 * parent, as this device is behind a switch
186 */
187 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
188
189 /* assume caller will handle error case */
190 if (err)
191 return err;
192
193 hw->bus.width = ixgbe_convert_bus_width(link_status);
194 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
195
196 return 0;
197 }
198
199 /**
200 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
201 * @hw: hw specific details
202 *
203 * This function is used by probe to determine whether a device's PCI-Express
204 * bandwidth details should be gathered from the parent bus instead of from the
205 * device. Used to ensure that various locations all have the correct device ID
206 * checks.
207 */
208 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
209 {
210 switch (hw->device_id) {
211 case IXGBE_DEV_ID_82599_SFP_SF_QP:
212 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
213 return true;
214 default:
215 return false;
216 }
217 }
218
219 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
220 int expected_gts)
221 {
222 int max_gts = 0;
223 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
224 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
225 struct pci_dev *pdev;
226
227 /* determine whether to use the the parent device
228 */
229 if (ixgbe_pcie_from_parent(&adapter->hw))
230 pdev = adapter->pdev->bus->parent->self;
231 else
232 pdev = adapter->pdev;
233
234 if (pcie_get_minimum_link(pdev, &speed, &width) ||
235 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
236 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
237 return;
238 }
239
240 switch (speed) {
241 case PCIE_SPEED_2_5GT:
242 /* 8b/10b encoding reduces max throughput by 20% */
243 max_gts = 2 * width;
244 break;
245 case PCIE_SPEED_5_0GT:
246 /* 8b/10b encoding reduces max throughput by 20% */
247 max_gts = 4 * width;
248 break;
249 case PCIE_SPEED_8_0GT:
250 /* 128b/130b encoding only reduces throughput by 1% */
251 max_gts = 8 * width;
252 break;
253 default:
254 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
255 return;
256 }
257
258 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
259 max_gts);
260 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
261 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
262 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
263 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
264 "Unknown"),
265 width,
266 (speed == PCIE_SPEED_2_5GT ? "20%" :
267 speed == PCIE_SPEED_5_0GT ? "20%" :
268 speed == PCIE_SPEED_8_0GT ? "N/a" :
269 "Unknown"));
270
271 if (max_gts < expected_gts) {
272 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
273 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
274 expected_gts);
275 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
276 }
277 }
278
279 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
280 {
281 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
282 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
283 schedule_work(&adapter->service_task);
284 }
285
286 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
287 {
288 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
289
290 /* flush memory to make sure state is correct before next watchdog */
291 smp_mb__before_clear_bit();
292 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
293 }
294
295 struct ixgbe_reg_info {
296 u32 ofs;
297 char *name;
298 };
299
300 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
301
302 /* General Registers */
303 {IXGBE_CTRL, "CTRL"},
304 {IXGBE_STATUS, "STATUS"},
305 {IXGBE_CTRL_EXT, "CTRL_EXT"},
306
307 /* Interrupt Registers */
308 {IXGBE_EICR, "EICR"},
309
310 /* RX Registers */
311 {IXGBE_SRRCTL(0), "SRRCTL"},
312 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
313 {IXGBE_RDLEN(0), "RDLEN"},
314 {IXGBE_RDH(0), "RDH"},
315 {IXGBE_RDT(0), "RDT"},
316 {IXGBE_RXDCTL(0), "RXDCTL"},
317 {IXGBE_RDBAL(0), "RDBAL"},
318 {IXGBE_RDBAH(0), "RDBAH"},
319
320 /* TX Registers */
321 {IXGBE_TDBAL(0), "TDBAL"},
322 {IXGBE_TDBAH(0), "TDBAH"},
323 {IXGBE_TDLEN(0), "TDLEN"},
324 {IXGBE_TDH(0), "TDH"},
325 {IXGBE_TDT(0), "TDT"},
326 {IXGBE_TXDCTL(0), "TXDCTL"},
327
328 /* List Terminator */
329 {}
330 };
331
332
333 /*
334 * ixgbe_regdump - register printout routine
335 */
336 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
337 {
338 int i = 0, j = 0;
339 char rname[16];
340 u32 regs[64];
341
342 switch (reginfo->ofs) {
343 case IXGBE_SRRCTL(0):
344 for (i = 0; i < 64; i++)
345 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
346 break;
347 case IXGBE_DCA_RXCTRL(0):
348 for (i = 0; i < 64; i++)
349 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
350 break;
351 case IXGBE_RDLEN(0):
352 for (i = 0; i < 64; i++)
353 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
354 break;
355 case IXGBE_RDH(0):
356 for (i = 0; i < 64; i++)
357 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
358 break;
359 case IXGBE_RDT(0):
360 for (i = 0; i < 64; i++)
361 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
362 break;
363 case IXGBE_RXDCTL(0):
364 for (i = 0; i < 64; i++)
365 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
366 break;
367 case IXGBE_RDBAL(0):
368 for (i = 0; i < 64; i++)
369 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
370 break;
371 case IXGBE_RDBAH(0):
372 for (i = 0; i < 64; i++)
373 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
374 break;
375 case IXGBE_TDBAL(0):
376 for (i = 0; i < 64; i++)
377 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
378 break;
379 case IXGBE_TDBAH(0):
380 for (i = 0; i < 64; i++)
381 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
382 break;
383 case IXGBE_TDLEN(0):
384 for (i = 0; i < 64; i++)
385 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
386 break;
387 case IXGBE_TDH(0):
388 for (i = 0; i < 64; i++)
389 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
390 break;
391 case IXGBE_TDT(0):
392 for (i = 0; i < 64; i++)
393 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
394 break;
395 case IXGBE_TXDCTL(0):
396 for (i = 0; i < 64; i++)
397 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
398 break;
399 default:
400 pr_info("%-15s %08x\n", reginfo->name,
401 IXGBE_READ_REG(hw, reginfo->ofs));
402 return;
403 }
404
405 for (i = 0; i < 8; i++) {
406 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
407 pr_err("%-15s", rname);
408 for (j = 0; j < 8; j++)
409 pr_cont(" %08x", regs[i*8+j]);
410 pr_cont("\n");
411 }
412
413 }
414
415 /*
416 * ixgbe_dump - Print registers, tx-rings and rx-rings
417 */
418 static void ixgbe_dump(struct ixgbe_adapter *adapter)
419 {
420 struct net_device *netdev = adapter->netdev;
421 struct ixgbe_hw *hw = &adapter->hw;
422 struct ixgbe_reg_info *reginfo;
423 int n = 0;
424 struct ixgbe_ring *tx_ring;
425 struct ixgbe_tx_buffer *tx_buffer;
426 union ixgbe_adv_tx_desc *tx_desc;
427 struct my_u0 { u64 a; u64 b; } *u0;
428 struct ixgbe_ring *rx_ring;
429 union ixgbe_adv_rx_desc *rx_desc;
430 struct ixgbe_rx_buffer *rx_buffer_info;
431 u32 staterr;
432 int i = 0;
433
434 if (!netif_msg_hw(adapter))
435 return;
436
437 /* Print netdevice Info */
438 if (netdev) {
439 dev_info(&adapter->pdev->dev, "Net device Info\n");
440 pr_info("Device Name state "
441 "trans_start last_rx\n");
442 pr_info("%-15s %016lX %016lX %016lX\n",
443 netdev->name,
444 netdev->state,
445 netdev->trans_start,
446 netdev->last_rx);
447 }
448
449 /* Print Registers */
450 dev_info(&adapter->pdev->dev, "Register Dump\n");
451 pr_info(" Register Name Value\n");
452 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
453 reginfo->name; reginfo++) {
454 ixgbe_regdump(hw, reginfo);
455 }
456
457 /* Print TX Ring Summary */
458 if (!netdev || !netif_running(netdev))
459 goto exit;
460
461 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
462 pr_info(" %s %s %s %s\n",
463 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
464 "leng", "ntw", "timestamp");
465 for (n = 0; n < adapter->num_tx_queues; n++) {
466 tx_ring = adapter->tx_ring[n];
467 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
468 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
469 n, tx_ring->next_to_use, tx_ring->next_to_clean,
470 (u64)dma_unmap_addr(tx_buffer, dma),
471 dma_unmap_len(tx_buffer, len),
472 tx_buffer->next_to_watch,
473 (u64)tx_buffer->time_stamp);
474 }
475
476 /* Print TX Rings */
477 if (!netif_msg_tx_done(adapter))
478 goto rx_ring_summary;
479
480 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
481
482 /* Transmit Descriptor Formats
483 *
484 * 82598 Advanced Transmit Descriptor
485 * +--------------------------------------------------------------+
486 * 0 | Buffer Address [63:0] |
487 * +--------------------------------------------------------------+
488 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
489 * +--------------------------------------------------------------+
490 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
491 *
492 * 82598 Advanced Transmit Descriptor (Write-Back Format)
493 * +--------------------------------------------------------------+
494 * 0 | RSV [63:0] |
495 * +--------------------------------------------------------------+
496 * 8 | RSV | STA | NXTSEQ |
497 * +--------------------------------------------------------------+
498 * 63 36 35 32 31 0
499 *
500 * 82599+ Advanced Transmit Descriptor
501 * +--------------------------------------------------------------+
502 * 0 | Buffer Address [63:0] |
503 * +--------------------------------------------------------------+
504 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
505 * +--------------------------------------------------------------+
506 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
507 *
508 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
509 * +--------------------------------------------------------------+
510 * 0 | RSV [63:0] |
511 * +--------------------------------------------------------------+
512 * 8 | RSV | STA | RSV |
513 * +--------------------------------------------------------------+
514 * 63 36 35 32 31 0
515 */
516
517 for (n = 0; n < adapter->num_tx_queues; n++) {
518 tx_ring = adapter->tx_ring[n];
519 pr_info("------------------------------------\n");
520 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
521 pr_info("------------------------------------\n");
522 pr_info("%s%s %s %s %s %s\n",
523 "T [desc] [address 63:0 ] ",
524 "[PlPOIdStDDt Ln] [bi->dma ] ",
525 "leng", "ntw", "timestamp", "bi->skb");
526
527 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
528 tx_desc = IXGBE_TX_DESC(tx_ring, i);
529 tx_buffer = &tx_ring->tx_buffer_info[i];
530 u0 = (struct my_u0 *)tx_desc;
531 if (dma_unmap_len(tx_buffer, len) > 0) {
532 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
533 i,
534 le64_to_cpu(u0->a),
535 le64_to_cpu(u0->b),
536 (u64)dma_unmap_addr(tx_buffer, dma),
537 dma_unmap_len(tx_buffer, len),
538 tx_buffer->next_to_watch,
539 (u64)tx_buffer->time_stamp,
540 tx_buffer->skb);
541 if (i == tx_ring->next_to_use &&
542 i == tx_ring->next_to_clean)
543 pr_cont(" NTC/U\n");
544 else if (i == tx_ring->next_to_use)
545 pr_cont(" NTU\n");
546 else if (i == tx_ring->next_to_clean)
547 pr_cont(" NTC\n");
548 else
549 pr_cont("\n");
550
551 if (netif_msg_pktdata(adapter) &&
552 tx_buffer->skb)
553 print_hex_dump(KERN_INFO, "",
554 DUMP_PREFIX_ADDRESS, 16, 1,
555 tx_buffer->skb->data,
556 dma_unmap_len(tx_buffer, len),
557 true);
558 }
559 }
560 }
561
562 /* Print RX Rings Summary */
563 rx_ring_summary:
564 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
565 pr_info("Queue [NTU] [NTC]\n");
566 for (n = 0; n < adapter->num_rx_queues; n++) {
567 rx_ring = adapter->rx_ring[n];
568 pr_info("%5d %5X %5X\n",
569 n, rx_ring->next_to_use, rx_ring->next_to_clean);
570 }
571
572 /* Print RX Rings */
573 if (!netif_msg_rx_status(adapter))
574 goto exit;
575
576 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
577
578 /* Receive Descriptor Formats
579 *
580 * 82598 Advanced Receive Descriptor (Read) Format
581 * 63 1 0
582 * +-----------------------------------------------------+
583 * 0 | Packet Buffer Address [63:1] |A0/NSE|
584 * +----------------------------------------------+------+
585 * 8 | Header Buffer Address [63:1] | DD |
586 * +-----------------------------------------------------+
587 *
588 *
589 * 82598 Advanced Receive Descriptor (Write-Back) Format
590 *
591 * 63 48 47 32 31 30 21 20 16 15 4 3 0
592 * +------------------------------------------------------+
593 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
594 * | Packet | IP | | | | Type | Type |
595 * | Checksum | Ident | | | | | |
596 * +------------------------------------------------------+
597 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
598 * +------------------------------------------------------+
599 * 63 48 47 32 31 20 19 0
600 *
601 * 82599+ Advanced Receive Descriptor (Read) Format
602 * 63 1 0
603 * +-----------------------------------------------------+
604 * 0 | Packet Buffer Address [63:1] |A0/NSE|
605 * +----------------------------------------------+------+
606 * 8 | Header Buffer Address [63:1] | DD |
607 * +-----------------------------------------------------+
608 *
609 *
610 * 82599+ Advanced Receive Descriptor (Write-Back) Format
611 *
612 * 63 48 47 32 31 30 21 20 17 16 4 3 0
613 * +------------------------------------------------------+
614 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
615 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
616 * |/ Flow Dir Flt ID | | | | | |
617 * +------------------------------------------------------+
618 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
619 * +------------------------------------------------------+
620 * 63 48 47 32 31 20 19 0
621 */
622
623 for (n = 0; n < adapter->num_rx_queues; n++) {
624 rx_ring = adapter->rx_ring[n];
625 pr_info("------------------------------------\n");
626 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
627 pr_info("------------------------------------\n");
628 pr_info("%s%s%s",
629 "R [desc] [ PktBuf A0] ",
630 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
631 "<-- Adv Rx Read format\n");
632 pr_info("%s%s%s",
633 "RWB[desc] [PcsmIpSHl PtRs] ",
634 "[vl er S cks ln] ---------------- [bi->skb ] ",
635 "<-- Adv Rx Write-Back format\n");
636
637 for (i = 0; i < rx_ring->count; i++) {
638 rx_buffer_info = &rx_ring->rx_buffer_info[i];
639 rx_desc = IXGBE_RX_DESC(rx_ring, i);
640 u0 = (struct my_u0 *)rx_desc;
641 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
642 if (staterr & IXGBE_RXD_STAT_DD) {
643 /* Descriptor Done */
644 pr_info("RWB[0x%03X] %016llX "
645 "%016llX ---------------- %p", i,
646 le64_to_cpu(u0->a),
647 le64_to_cpu(u0->b),
648 rx_buffer_info->skb);
649 } else {
650 pr_info("R [0x%03X] %016llX "
651 "%016llX %016llX %p", i,
652 le64_to_cpu(u0->a),
653 le64_to_cpu(u0->b),
654 (u64)rx_buffer_info->dma,
655 rx_buffer_info->skb);
656
657 if (netif_msg_pktdata(adapter) &&
658 rx_buffer_info->dma) {
659 print_hex_dump(KERN_INFO, "",
660 DUMP_PREFIX_ADDRESS, 16, 1,
661 page_address(rx_buffer_info->page) +
662 rx_buffer_info->page_offset,
663 ixgbe_rx_bufsz(rx_ring), true);
664 }
665 }
666
667 if (i == rx_ring->next_to_use)
668 pr_cont(" NTU\n");
669 else if (i == rx_ring->next_to_clean)
670 pr_cont(" NTC\n");
671 else
672 pr_cont("\n");
673
674 }
675 }
676
677 exit:
678 return;
679 }
680
681 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
682 {
683 u32 ctrl_ext;
684
685 /* Let firmware take over control of h/w */
686 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
687 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
688 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
689 }
690
691 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
692 {
693 u32 ctrl_ext;
694
695 /* Let firmware know the driver has taken over */
696 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
697 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
698 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
699 }
700
701 /**
702 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
703 * @adapter: pointer to adapter struct
704 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
705 * @queue: queue to map the corresponding interrupt to
706 * @msix_vector: the vector to map to the corresponding queue
707 *
708 */
709 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
710 u8 queue, u8 msix_vector)
711 {
712 u32 ivar, index;
713 struct ixgbe_hw *hw = &adapter->hw;
714 switch (hw->mac.type) {
715 case ixgbe_mac_82598EB:
716 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
717 if (direction == -1)
718 direction = 0;
719 index = (((direction * 64) + queue) >> 2) & 0x1F;
720 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
721 ivar &= ~(0xFF << (8 * (queue & 0x3)));
722 ivar |= (msix_vector << (8 * (queue & 0x3)));
723 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
724 break;
725 case ixgbe_mac_82599EB:
726 case ixgbe_mac_X540:
727 if (direction == -1) {
728 /* other causes */
729 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
730 index = ((queue & 1) * 8);
731 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
732 ivar &= ~(0xFF << index);
733 ivar |= (msix_vector << index);
734 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
735 break;
736 } else {
737 /* tx or rx causes */
738 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
739 index = ((16 * (queue & 1)) + (8 * direction));
740 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
741 ivar &= ~(0xFF << index);
742 ivar |= (msix_vector << index);
743 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
744 break;
745 }
746 default:
747 break;
748 }
749 }
750
751 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
752 u64 qmask)
753 {
754 u32 mask;
755
756 switch (adapter->hw.mac.type) {
757 case ixgbe_mac_82598EB:
758 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
759 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
760 break;
761 case ixgbe_mac_82599EB:
762 case ixgbe_mac_X540:
763 mask = (qmask & 0xFFFFFFFF);
764 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
765 mask = (qmask >> 32);
766 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
767 break;
768 default:
769 break;
770 }
771 }
772
773 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
774 struct ixgbe_tx_buffer *tx_buffer)
775 {
776 if (tx_buffer->skb) {
777 dev_kfree_skb_any(tx_buffer->skb);
778 if (dma_unmap_len(tx_buffer, len))
779 dma_unmap_single(ring->dev,
780 dma_unmap_addr(tx_buffer, dma),
781 dma_unmap_len(tx_buffer, len),
782 DMA_TO_DEVICE);
783 } else if (dma_unmap_len(tx_buffer, len)) {
784 dma_unmap_page(ring->dev,
785 dma_unmap_addr(tx_buffer, dma),
786 dma_unmap_len(tx_buffer, len),
787 DMA_TO_DEVICE);
788 }
789 tx_buffer->next_to_watch = NULL;
790 tx_buffer->skb = NULL;
791 dma_unmap_len_set(tx_buffer, len, 0);
792 /* tx_buffer must be completely set up in the transmit path */
793 }
794
795 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
796 {
797 struct ixgbe_hw *hw = &adapter->hw;
798 struct ixgbe_hw_stats *hwstats = &adapter->stats;
799 int i;
800 u32 data;
801
802 if ((hw->fc.current_mode != ixgbe_fc_full) &&
803 (hw->fc.current_mode != ixgbe_fc_rx_pause))
804 return;
805
806 switch (hw->mac.type) {
807 case ixgbe_mac_82598EB:
808 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
809 break;
810 default:
811 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
812 }
813 hwstats->lxoffrxc += data;
814
815 /* refill credits (no tx hang) if we received xoff */
816 if (!data)
817 return;
818
819 for (i = 0; i < adapter->num_tx_queues; i++)
820 clear_bit(__IXGBE_HANG_CHECK_ARMED,
821 &adapter->tx_ring[i]->state);
822 }
823
824 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
825 {
826 struct ixgbe_hw *hw = &adapter->hw;
827 struct ixgbe_hw_stats *hwstats = &adapter->stats;
828 u32 xoff[8] = {0};
829 u8 tc;
830 int i;
831 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
832
833 if (adapter->ixgbe_ieee_pfc)
834 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
835
836 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
837 ixgbe_update_xoff_rx_lfc(adapter);
838 return;
839 }
840
841 /* update stats for each tc, only valid with PFC enabled */
842 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
843 u32 pxoffrxc;
844
845 switch (hw->mac.type) {
846 case ixgbe_mac_82598EB:
847 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
848 break;
849 default:
850 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
851 }
852 hwstats->pxoffrxc[i] += pxoffrxc;
853 /* Get the TC for given UP */
854 tc = netdev_get_prio_tc_map(adapter->netdev, i);
855 xoff[tc] += pxoffrxc;
856 }
857
858 /* disarm tx queues that have received xoff frames */
859 for (i = 0; i < adapter->num_tx_queues; i++) {
860 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
861
862 tc = tx_ring->dcb_tc;
863 if (xoff[tc])
864 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
865 }
866 }
867
868 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
869 {
870 return ring->stats.packets;
871 }
872
873 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
874 {
875 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
876 struct ixgbe_hw *hw = &adapter->hw;
877
878 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
879 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
880
881 if (head != tail)
882 return (head < tail) ?
883 tail - head : (tail + ring->count - head);
884
885 return 0;
886 }
887
888 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
889 {
890 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
891 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
892 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
893 bool ret = false;
894
895 clear_check_for_tx_hang(tx_ring);
896
897 /*
898 * Check for a hung queue, but be thorough. This verifies
899 * that a transmit has been completed since the previous
900 * check AND there is at least one packet pending. The
901 * ARMED bit is set to indicate a potential hang. The
902 * bit is cleared if a pause frame is received to remove
903 * false hang detection due to PFC or 802.3x frames. By
904 * requiring this to fail twice we avoid races with
905 * pfc clearing the ARMED bit and conditions where we
906 * run the check_tx_hang logic with a transmit completion
907 * pending but without time to complete it yet.
908 */
909 if ((tx_done_old == tx_done) && tx_pending) {
910 /* make sure it is true for two checks in a row */
911 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
912 &tx_ring->state);
913 } else {
914 /* update completed stats and continue */
915 tx_ring->tx_stats.tx_done_old = tx_done;
916 /* reset the countdown */
917 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
918 }
919
920 return ret;
921 }
922
923 /**
924 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
925 * @adapter: driver private struct
926 **/
927 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
928 {
929
930 /* Do the reset outside of interrupt context */
931 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
932 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
933 e_warn(drv, "initiating reset due to tx timeout\n");
934 ixgbe_service_event_schedule(adapter);
935 }
936 }
937
938 /**
939 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
940 * @q_vector: structure containing interrupt and ring information
941 * @tx_ring: tx ring to clean
942 **/
943 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
944 struct ixgbe_ring *tx_ring)
945 {
946 struct ixgbe_adapter *adapter = q_vector->adapter;
947 struct ixgbe_tx_buffer *tx_buffer;
948 union ixgbe_adv_tx_desc *tx_desc;
949 unsigned int total_bytes = 0, total_packets = 0;
950 unsigned int budget = q_vector->tx.work_limit;
951 unsigned int i = tx_ring->next_to_clean;
952
953 if (test_bit(__IXGBE_DOWN, &adapter->state))
954 return true;
955
956 tx_buffer = &tx_ring->tx_buffer_info[i];
957 tx_desc = IXGBE_TX_DESC(tx_ring, i);
958 i -= tx_ring->count;
959
960 do {
961 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
962
963 /* if next_to_watch is not set then there is no work pending */
964 if (!eop_desc)
965 break;
966
967 /* prevent any other reads prior to eop_desc */
968 read_barrier_depends();
969
970 /* if DD is not set pending work has not been completed */
971 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
972 break;
973
974 /* clear next_to_watch to prevent false hangs */
975 tx_buffer->next_to_watch = NULL;
976
977 /* update the statistics for this packet */
978 total_bytes += tx_buffer->bytecount;
979 total_packets += tx_buffer->gso_segs;
980
981 /* free the skb */
982 dev_kfree_skb_any(tx_buffer->skb);
983
984 /* unmap skb header data */
985 dma_unmap_single(tx_ring->dev,
986 dma_unmap_addr(tx_buffer, dma),
987 dma_unmap_len(tx_buffer, len),
988 DMA_TO_DEVICE);
989
990 /* clear tx_buffer data */
991 tx_buffer->skb = NULL;
992 dma_unmap_len_set(tx_buffer, len, 0);
993
994 /* unmap remaining buffers */
995 while (tx_desc != eop_desc) {
996 tx_buffer++;
997 tx_desc++;
998 i++;
999 if (unlikely(!i)) {
1000 i -= tx_ring->count;
1001 tx_buffer = tx_ring->tx_buffer_info;
1002 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1003 }
1004
1005 /* unmap any remaining paged data */
1006 if (dma_unmap_len(tx_buffer, len)) {
1007 dma_unmap_page(tx_ring->dev,
1008 dma_unmap_addr(tx_buffer, dma),
1009 dma_unmap_len(tx_buffer, len),
1010 DMA_TO_DEVICE);
1011 dma_unmap_len_set(tx_buffer, len, 0);
1012 }
1013 }
1014
1015 /* move us one more past the eop_desc for start of next pkt */
1016 tx_buffer++;
1017 tx_desc++;
1018 i++;
1019 if (unlikely(!i)) {
1020 i -= tx_ring->count;
1021 tx_buffer = tx_ring->tx_buffer_info;
1022 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1023 }
1024
1025 /* issue prefetch for next Tx descriptor */
1026 prefetch(tx_desc);
1027
1028 /* update budget accounting */
1029 budget--;
1030 } while (likely(budget));
1031
1032 i += tx_ring->count;
1033 tx_ring->next_to_clean = i;
1034 u64_stats_update_begin(&tx_ring->syncp);
1035 tx_ring->stats.bytes += total_bytes;
1036 tx_ring->stats.packets += total_packets;
1037 u64_stats_update_end(&tx_ring->syncp);
1038 q_vector->tx.total_bytes += total_bytes;
1039 q_vector->tx.total_packets += total_packets;
1040
1041 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1042 /* schedule immediate reset if we believe we hung */
1043 struct ixgbe_hw *hw = &adapter->hw;
1044 e_err(drv, "Detected Tx Unit Hang\n"
1045 " Tx Queue <%d>\n"
1046 " TDH, TDT <%x>, <%x>\n"
1047 " next_to_use <%x>\n"
1048 " next_to_clean <%x>\n"
1049 "tx_buffer_info[next_to_clean]\n"
1050 " time_stamp <%lx>\n"
1051 " jiffies <%lx>\n",
1052 tx_ring->queue_index,
1053 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1054 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1055 tx_ring->next_to_use, i,
1056 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1057
1058 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1059
1060 e_info(probe,
1061 "tx hang %d detected on queue %d, resetting adapter\n",
1062 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1063
1064 /* schedule immediate reset if we believe we hung */
1065 ixgbe_tx_timeout_reset(adapter);
1066
1067 /* the adapter is about to reset, no point in enabling stuff */
1068 return true;
1069 }
1070
1071 netdev_tx_completed_queue(txring_txq(tx_ring),
1072 total_packets, total_bytes);
1073
1074 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1075 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1076 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1077 /* Make sure that anybody stopping the queue after this
1078 * sees the new next_to_clean.
1079 */
1080 smp_mb();
1081 if (__netif_subqueue_stopped(tx_ring->netdev,
1082 tx_ring->queue_index)
1083 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1084 netif_wake_subqueue(tx_ring->netdev,
1085 tx_ring->queue_index);
1086 ++tx_ring->tx_stats.restart_queue;
1087 }
1088 }
1089
1090 return !!budget;
1091 }
1092
1093 #ifdef CONFIG_IXGBE_DCA
1094 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1095 struct ixgbe_ring *tx_ring,
1096 int cpu)
1097 {
1098 struct ixgbe_hw *hw = &adapter->hw;
1099 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1100 u16 reg_offset;
1101
1102 switch (hw->mac.type) {
1103 case ixgbe_mac_82598EB:
1104 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1105 break;
1106 case ixgbe_mac_82599EB:
1107 case ixgbe_mac_X540:
1108 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1109 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1110 break;
1111 default:
1112 /* for unknown hardware do not write register */
1113 return;
1114 }
1115
1116 /*
1117 * We can enable relaxed ordering for reads, but not writes when
1118 * DCA is enabled. This is due to a known issue in some chipsets
1119 * which will cause the DCA tag to be cleared.
1120 */
1121 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1122 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1123 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1124
1125 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1126 }
1127
1128 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1129 struct ixgbe_ring *rx_ring,
1130 int cpu)
1131 {
1132 struct ixgbe_hw *hw = &adapter->hw;
1133 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1134 u8 reg_idx = rx_ring->reg_idx;
1135
1136
1137 switch (hw->mac.type) {
1138 case ixgbe_mac_82599EB:
1139 case ixgbe_mac_X540:
1140 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1141 break;
1142 default:
1143 break;
1144 }
1145
1146 /*
1147 * We can enable relaxed ordering for reads, but not writes when
1148 * DCA is enabled. This is due to a known issue in some chipsets
1149 * which will cause the DCA tag to be cleared.
1150 */
1151 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1152 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1153
1154 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1155 }
1156
1157 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1158 {
1159 struct ixgbe_adapter *adapter = q_vector->adapter;
1160 struct ixgbe_ring *ring;
1161 int cpu = get_cpu();
1162
1163 if (q_vector->cpu == cpu)
1164 goto out_no_update;
1165
1166 ixgbe_for_each_ring(ring, q_vector->tx)
1167 ixgbe_update_tx_dca(adapter, ring, cpu);
1168
1169 ixgbe_for_each_ring(ring, q_vector->rx)
1170 ixgbe_update_rx_dca(adapter, ring, cpu);
1171
1172 q_vector->cpu = cpu;
1173 out_no_update:
1174 put_cpu();
1175 }
1176
1177 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1178 {
1179 int i;
1180
1181 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1182 return;
1183
1184 /* always use CB2 mode, difference is masked in the CB driver */
1185 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1186
1187 for (i = 0; i < adapter->num_q_vectors; i++) {
1188 adapter->q_vector[i]->cpu = -1;
1189 ixgbe_update_dca(adapter->q_vector[i]);
1190 }
1191 }
1192
1193 static int __ixgbe_notify_dca(struct device *dev, void *data)
1194 {
1195 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1196 unsigned long event = *(unsigned long *)data;
1197
1198 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1199 return 0;
1200
1201 switch (event) {
1202 case DCA_PROVIDER_ADD:
1203 /* if we're already enabled, don't do it again */
1204 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1205 break;
1206 if (dca_add_requester(dev) == 0) {
1207 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1208 ixgbe_setup_dca(adapter);
1209 break;
1210 }
1211 /* Fall Through since DCA is disabled. */
1212 case DCA_PROVIDER_REMOVE:
1213 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1214 dca_remove_requester(dev);
1215 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1216 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1217 }
1218 break;
1219 }
1220
1221 return 0;
1222 }
1223
1224 #endif /* CONFIG_IXGBE_DCA */
1225 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1226 union ixgbe_adv_rx_desc *rx_desc,
1227 struct sk_buff *skb)
1228 {
1229 if (ring->netdev->features & NETIF_F_RXHASH)
1230 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1231 }
1232
1233 #ifdef IXGBE_FCOE
1234 /**
1235 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1236 * @ring: structure containing ring specific data
1237 * @rx_desc: advanced rx descriptor
1238 *
1239 * Returns : true if it is FCoE pkt
1240 */
1241 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1242 union ixgbe_adv_rx_desc *rx_desc)
1243 {
1244 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1245
1246 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1247 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1248 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1249 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1250 }
1251
1252 #endif /* IXGBE_FCOE */
1253 /**
1254 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1255 * @ring: structure containing ring specific data
1256 * @rx_desc: current Rx descriptor being processed
1257 * @skb: skb currently being received and modified
1258 **/
1259 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1260 union ixgbe_adv_rx_desc *rx_desc,
1261 struct sk_buff *skb)
1262 {
1263 skb_checksum_none_assert(skb);
1264
1265 /* Rx csum disabled */
1266 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1267 return;
1268
1269 /* if IP and error */
1270 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1271 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1272 ring->rx_stats.csum_err++;
1273 return;
1274 }
1275
1276 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1277 return;
1278
1279 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1280 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1281
1282 /*
1283 * 82599 errata, UDP frames with a 0 checksum can be marked as
1284 * checksum errors.
1285 */
1286 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1287 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1288 return;
1289
1290 ring->rx_stats.csum_err++;
1291 return;
1292 }
1293
1294 /* It must be a TCP or UDP packet with a valid checksum */
1295 skb->ip_summed = CHECKSUM_UNNECESSARY;
1296 }
1297
1298 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1299 {
1300 rx_ring->next_to_use = val;
1301
1302 /* update next to alloc since we have filled the ring */
1303 rx_ring->next_to_alloc = val;
1304 /*
1305 * Force memory writes to complete before letting h/w
1306 * know there are new descriptors to fetch. (Only
1307 * applicable for weak-ordered memory model archs,
1308 * such as IA-64).
1309 */
1310 wmb();
1311 writel(val, rx_ring->tail);
1312 }
1313
1314 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1315 struct ixgbe_rx_buffer *bi)
1316 {
1317 struct page *page = bi->page;
1318 dma_addr_t dma = bi->dma;
1319
1320 /* since we are recycling buffers we should seldom need to alloc */
1321 if (likely(dma))
1322 return true;
1323
1324 /* alloc new page for storage */
1325 if (likely(!page)) {
1326 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1327 bi->skb, ixgbe_rx_pg_order(rx_ring));
1328 if (unlikely(!page)) {
1329 rx_ring->rx_stats.alloc_rx_page_failed++;
1330 return false;
1331 }
1332 bi->page = page;
1333 }
1334
1335 /* map page for use */
1336 dma = dma_map_page(rx_ring->dev, page, 0,
1337 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1338
1339 /*
1340 * if mapping failed free memory back to system since
1341 * there isn't much point in holding memory we can't use
1342 */
1343 if (dma_mapping_error(rx_ring->dev, dma)) {
1344 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1345 bi->page = NULL;
1346
1347 rx_ring->rx_stats.alloc_rx_page_failed++;
1348 return false;
1349 }
1350
1351 bi->dma = dma;
1352 bi->page_offset = 0;
1353
1354 return true;
1355 }
1356
1357 /**
1358 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1359 * @rx_ring: ring to place buffers on
1360 * @cleaned_count: number of buffers to replace
1361 **/
1362 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1363 {
1364 union ixgbe_adv_rx_desc *rx_desc;
1365 struct ixgbe_rx_buffer *bi;
1366 u16 i = rx_ring->next_to_use;
1367
1368 /* nothing to do */
1369 if (!cleaned_count)
1370 return;
1371
1372 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1373 bi = &rx_ring->rx_buffer_info[i];
1374 i -= rx_ring->count;
1375
1376 do {
1377 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1378 break;
1379
1380 /*
1381 * Refresh the desc even if buffer_addrs didn't change
1382 * because each write-back erases this info.
1383 */
1384 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1385
1386 rx_desc++;
1387 bi++;
1388 i++;
1389 if (unlikely(!i)) {
1390 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1391 bi = rx_ring->rx_buffer_info;
1392 i -= rx_ring->count;
1393 }
1394
1395 /* clear the hdr_addr for the next_to_use descriptor */
1396 rx_desc->read.hdr_addr = 0;
1397
1398 cleaned_count--;
1399 } while (cleaned_count);
1400
1401 i += rx_ring->count;
1402
1403 if (rx_ring->next_to_use != i)
1404 ixgbe_release_rx_desc(rx_ring, i);
1405 }
1406
1407 /**
1408 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1409 * @data: pointer to the start of the headers
1410 * @max_len: total length of section to find headers in
1411 *
1412 * This function is meant to determine the length of headers that will
1413 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1414 * motivation of doing this is to only perform one pull for IPv4 TCP
1415 * packets so that we can do basic things like calculating the gso_size
1416 * based on the average data per packet.
1417 **/
1418 static unsigned int ixgbe_get_headlen(unsigned char *data,
1419 unsigned int max_len)
1420 {
1421 union {
1422 unsigned char *network;
1423 /* l2 headers */
1424 struct ethhdr *eth;
1425 struct vlan_hdr *vlan;
1426 /* l3 headers */
1427 struct iphdr *ipv4;
1428 struct ipv6hdr *ipv6;
1429 } hdr;
1430 __be16 protocol;
1431 u8 nexthdr = 0; /* default to not TCP */
1432 u8 hlen;
1433
1434 /* this should never happen, but better safe than sorry */
1435 if (max_len < ETH_HLEN)
1436 return max_len;
1437
1438 /* initialize network frame pointer */
1439 hdr.network = data;
1440
1441 /* set first protocol and move network header forward */
1442 protocol = hdr.eth->h_proto;
1443 hdr.network += ETH_HLEN;
1444
1445 /* handle any vlan tag if present */
1446 if (protocol == __constant_htons(ETH_P_8021Q)) {
1447 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1448 return max_len;
1449
1450 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1451 hdr.network += VLAN_HLEN;
1452 }
1453
1454 /* handle L3 protocols */
1455 if (protocol == __constant_htons(ETH_P_IP)) {
1456 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1457 return max_len;
1458
1459 /* access ihl as a u8 to avoid unaligned access on ia64 */
1460 hlen = (hdr.network[0] & 0x0F) << 2;
1461
1462 /* verify hlen meets minimum size requirements */
1463 if (hlen < sizeof(struct iphdr))
1464 return hdr.network - data;
1465
1466 /* record next protocol if header is present */
1467 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
1468 nexthdr = hdr.ipv4->protocol;
1469 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1470 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1471 return max_len;
1472
1473 /* record next protocol */
1474 nexthdr = hdr.ipv6->nexthdr;
1475 hlen = sizeof(struct ipv6hdr);
1476 #ifdef IXGBE_FCOE
1477 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1478 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1479 return max_len;
1480 hlen = FCOE_HEADER_LEN;
1481 #endif
1482 } else {
1483 return hdr.network - data;
1484 }
1485
1486 /* relocate pointer to start of L4 header */
1487 hdr.network += hlen;
1488
1489 /* finally sort out TCP/UDP */
1490 if (nexthdr == IPPROTO_TCP) {
1491 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1492 return max_len;
1493
1494 /* access doff as a u8 to avoid unaligned access on ia64 */
1495 hlen = (hdr.network[12] & 0xF0) >> 2;
1496
1497 /* verify hlen meets minimum size requirements */
1498 if (hlen < sizeof(struct tcphdr))
1499 return hdr.network - data;
1500
1501 hdr.network += hlen;
1502 } else if (nexthdr == IPPROTO_UDP) {
1503 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1504 return max_len;
1505
1506 hdr.network += sizeof(struct udphdr);
1507 }
1508
1509 /*
1510 * If everything has gone correctly hdr.network should be the
1511 * data section of the packet and will be the end of the header.
1512 * If not then it probably represents the end of the last recognized
1513 * header.
1514 */
1515 if ((hdr.network - data) < max_len)
1516 return hdr.network - data;
1517 else
1518 return max_len;
1519 }
1520
1521 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1522 struct sk_buff *skb)
1523 {
1524 u16 hdr_len = skb_headlen(skb);
1525
1526 /* set gso_size to avoid messing up TCP MSS */
1527 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1528 IXGBE_CB(skb)->append_cnt);
1529 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1530 }
1531
1532 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1533 struct sk_buff *skb)
1534 {
1535 /* if append_cnt is 0 then frame is not RSC */
1536 if (!IXGBE_CB(skb)->append_cnt)
1537 return;
1538
1539 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1540 rx_ring->rx_stats.rsc_flush++;
1541
1542 ixgbe_set_rsc_gso_size(rx_ring, skb);
1543
1544 /* gso_size is computed using append_cnt so always clear it last */
1545 IXGBE_CB(skb)->append_cnt = 0;
1546 }
1547
1548 /**
1549 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1550 * @rx_ring: rx descriptor ring packet is being transacted on
1551 * @rx_desc: pointer to the EOP Rx descriptor
1552 * @skb: pointer to current skb being populated
1553 *
1554 * This function checks the ring, descriptor, and packet information in
1555 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1556 * other fields within the skb.
1557 **/
1558 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1559 union ixgbe_adv_rx_desc *rx_desc,
1560 struct sk_buff *skb)
1561 {
1562 struct net_device *dev = rx_ring->netdev;
1563
1564 ixgbe_update_rsc_stats(rx_ring, skb);
1565
1566 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1567
1568 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1569
1570 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1571
1572 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1573 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1574 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1575 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1576 }
1577
1578 skb_record_rx_queue(skb, rx_ring->queue_index);
1579
1580 skb->protocol = eth_type_trans(skb, dev);
1581 }
1582
1583 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1584 struct sk_buff *skb)
1585 {
1586 struct ixgbe_adapter *adapter = q_vector->adapter;
1587
1588 if (ixgbe_qv_ll_polling(q_vector))
1589 netif_receive_skb(skb);
1590 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1591 napi_gro_receive(&q_vector->napi, skb);
1592 else
1593 netif_rx(skb);
1594 }
1595
1596 /**
1597 * ixgbe_is_non_eop - process handling of non-EOP buffers
1598 * @rx_ring: Rx ring being processed
1599 * @rx_desc: Rx descriptor for current buffer
1600 * @skb: Current socket buffer containing buffer in progress
1601 *
1602 * This function updates next to clean. If the buffer is an EOP buffer
1603 * this function exits returning false, otherwise it will place the
1604 * sk_buff in the next buffer to be chained and return true indicating
1605 * that this is in fact a non-EOP buffer.
1606 **/
1607 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1608 union ixgbe_adv_rx_desc *rx_desc,
1609 struct sk_buff *skb)
1610 {
1611 u32 ntc = rx_ring->next_to_clean + 1;
1612
1613 /* fetch, update, and store next to clean */
1614 ntc = (ntc < rx_ring->count) ? ntc : 0;
1615 rx_ring->next_to_clean = ntc;
1616
1617 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1618
1619 /* update RSC append count if present */
1620 if (ring_is_rsc_enabled(rx_ring)) {
1621 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1622 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1623
1624 if (unlikely(rsc_enabled)) {
1625 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1626
1627 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1628 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1629
1630 /* update ntc based on RSC value */
1631 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1632 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1633 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1634 }
1635 }
1636
1637 /* if we are the last buffer then there is nothing else to do */
1638 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1639 return false;
1640
1641 /* place skb in next buffer to be received */
1642 rx_ring->rx_buffer_info[ntc].skb = skb;
1643 rx_ring->rx_stats.non_eop_descs++;
1644
1645 return true;
1646 }
1647
1648 /**
1649 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1650 * @rx_ring: rx descriptor ring packet is being transacted on
1651 * @skb: pointer to current skb being adjusted
1652 *
1653 * This function is an ixgbe specific version of __pskb_pull_tail. The
1654 * main difference between this version and the original function is that
1655 * this function can make several assumptions about the state of things
1656 * that allow for significant optimizations versus the standard function.
1657 * As a result we can do things like drop a frag and maintain an accurate
1658 * truesize for the skb.
1659 */
1660 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1661 struct sk_buff *skb)
1662 {
1663 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1664 unsigned char *va;
1665 unsigned int pull_len;
1666
1667 /*
1668 * it is valid to use page_address instead of kmap since we are
1669 * working with pages allocated out of the lomem pool per
1670 * alloc_page(GFP_ATOMIC)
1671 */
1672 va = skb_frag_address(frag);
1673
1674 /*
1675 * we need the header to contain the greater of either ETH_HLEN or
1676 * 60 bytes if the skb->len is less than 60 for skb_pad.
1677 */
1678 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
1679
1680 /* align pull length to size of long to optimize memcpy performance */
1681 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1682
1683 /* update all of the pointers */
1684 skb_frag_size_sub(frag, pull_len);
1685 frag->page_offset += pull_len;
1686 skb->data_len -= pull_len;
1687 skb->tail += pull_len;
1688 }
1689
1690 /**
1691 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1692 * @rx_ring: rx descriptor ring packet is being transacted on
1693 * @skb: pointer to current skb being updated
1694 *
1695 * This function provides a basic DMA sync up for the first fragment of an
1696 * skb. The reason for doing this is that the first fragment cannot be
1697 * unmapped until we have reached the end of packet descriptor for a buffer
1698 * chain.
1699 */
1700 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1701 struct sk_buff *skb)
1702 {
1703 /* if the page was released unmap it, else just sync our portion */
1704 if (unlikely(IXGBE_CB(skb)->page_released)) {
1705 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1706 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1707 IXGBE_CB(skb)->page_released = false;
1708 } else {
1709 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1710
1711 dma_sync_single_range_for_cpu(rx_ring->dev,
1712 IXGBE_CB(skb)->dma,
1713 frag->page_offset,
1714 ixgbe_rx_bufsz(rx_ring),
1715 DMA_FROM_DEVICE);
1716 }
1717 IXGBE_CB(skb)->dma = 0;
1718 }
1719
1720 /**
1721 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1722 * @rx_ring: rx descriptor ring packet is being transacted on
1723 * @rx_desc: pointer to the EOP Rx descriptor
1724 * @skb: pointer to current skb being fixed
1725 *
1726 * Check for corrupted packet headers caused by senders on the local L2
1727 * embedded NIC switch not setting up their Tx Descriptors right. These
1728 * should be very rare.
1729 *
1730 * Also address the case where we are pulling data in on pages only
1731 * and as such no data is present in the skb header.
1732 *
1733 * In addition if skb is not at least 60 bytes we need to pad it so that
1734 * it is large enough to qualify as a valid Ethernet frame.
1735 *
1736 * Returns true if an error was encountered and skb was freed.
1737 **/
1738 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1739 union ixgbe_adv_rx_desc *rx_desc,
1740 struct sk_buff *skb)
1741 {
1742 struct net_device *netdev = rx_ring->netdev;
1743
1744 /* verify that the packet does not have any known errors */
1745 if (unlikely(ixgbe_test_staterr(rx_desc,
1746 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1747 !(netdev->features & NETIF_F_RXALL))) {
1748 dev_kfree_skb_any(skb);
1749 return true;
1750 }
1751
1752 /* place header in linear portion of buffer */
1753 if (skb_is_nonlinear(skb))
1754 ixgbe_pull_tail(rx_ring, skb);
1755
1756 #ifdef IXGBE_FCOE
1757 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1758 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1759 return false;
1760
1761 #endif
1762 /* if skb_pad returns an error the skb was freed */
1763 if (unlikely(skb->len < 60)) {
1764 int pad_len = 60 - skb->len;
1765
1766 if (skb_pad(skb, pad_len))
1767 return true;
1768 __skb_put(skb, pad_len);
1769 }
1770
1771 return false;
1772 }
1773
1774 /**
1775 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1776 * @rx_ring: rx descriptor ring to store buffers on
1777 * @old_buff: donor buffer to have page reused
1778 *
1779 * Synchronizes page for reuse by the adapter
1780 **/
1781 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1782 struct ixgbe_rx_buffer *old_buff)
1783 {
1784 struct ixgbe_rx_buffer *new_buff;
1785 u16 nta = rx_ring->next_to_alloc;
1786
1787 new_buff = &rx_ring->rx_buffer_info[nta];
1788
1789 /* update, and store next to alloc */
1790 nta++;
1791 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1792
1793 /* transfer page from old buffer to new buffer */
1794 new_buff->page = old_buff->page;
1795 new_buff->dma = old_buff->dma;
1796 new_buff->page_offset = old_buff->page_offset;
1797
1798 /* sync the buffer for use by the device */
1799 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1800 new_buff->page_offset,
1801 ixgbe_rx_bufsz(rx_ring),
1802 DMA_FROM_DEVICE);
1803 }
1804
1805 /**
1806 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1807 * @rx_ring: rx descriptor ring to transact packets on
1808 * @rx_buffer: buffer containing page to add
1809 * @rx_desc: descriptor containing length of buffer written by hardware
1810 * @skb: sk_buff to place the data into
1811 *
1812 * This function will add the data contained in rx_buffer->page to the skb.
1813 * This is done either through a direct copy if the data in the buffer is
1814 * less than the skb header size, otherwise it will just attach the page as
1815 * a frag to the skb.
1816 *
1817 * The function will then update the page offset if necessary and return
1818 * true if the buffer can be reused by the adapter.
1819 **/
1820 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1821 struct ixgbe_rx_buffer *rx_buffer,
1822 union ixgbe_adv_rx_desc *rx_desc,
1823 struct sk_buff *skb)
1824 {
1825 struct page *page = rx_buffer->page;
1826 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1827 #if (PAGE_SIZE < 8192)
1828 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1829 #else
1830 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1831 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1832 ixgbe_rx_bufsz(rx_ring);
1833 #endif
1834
1835 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1836 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1837
1838 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1839
1840 /* we can reuse buffer as-is, just make sure it is local */
1841 if (likely(page_to_nid(page) == numa_node_id()))
1842 return true;
1843
1844 /* this page cannot be reused so discard it */
1845 put_page(page);
1846 return false;
1847 }
1848
1849 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1850 rx_buffer->page_offset, size, truesize);
1851
1852 /* avoid re-using remote pages */
1853 if (unlikely(page_to_nid(page) != numa_node_id()))
1854 return false;
1855
1856 #if (PAGE_SIZE < 8192)
1857 /* if we are only owner of page we can reuse it */
1858 if (unlikely(page_count(page) != 1))
1859 return false;
1860
1861 /* flip page offset to other buffer */
1862 rx_buffer->page_offset ^= truesize;
1863
1864 /*
1865 * since we are the only owner of the page and we need to
1866 * increment it, just set the value to 2 in order to avoid
1867 * an unecessary locked operation
1868 */
1869 atomic_set(&page->_count, 2);
1870 #else
1871 /* move offset up to the next cache line */
1872 rx_buffer->page_offset += truesize;
1873
1874 if (rx_buffer->page_offset > last_offset)
1875 return false;
1876
1877 /* bump ref count on page before it is given to the stack */
1878 get_page(page);
1879 #endif
1880
1881 return true;
1882 }
1883
1884 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1885 union ixgbe_adv_rx_desc *rx_desc)
1886 {
1887 struct ixgbe_rx_buffer *rx_buffer;
1888 struct sk_buff *skb;
1889 struct page *page;
1890
1891 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1892 page = rx_buffer->page;
1893 prefetchw(page);
1894
1895 skb = rx_buffer->skb;
1896
1897 if (likely(!skb)) {
1898 void *page_addr = page_address(page) +
1899 rx_buffer->page_offset;
1900
1901 /* prefetch first cache line of first page */
1902 prefetch(page_addr);
1903 #if L1_CACHE_BYTES < 128
1904 prefetch(page_addr + L1_CACHE_BYTES);
1905 #endif
1906
1907 /* allocate a skb to store the frags */
1908 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1909 IXGBE_RX_HDR_SIZE);
1910 if (unlikely(!skb)) {
1911 rx_ring->rx_stats.alloc_rx_buff_failed++;
1912 return NULL;
1913 }
1914
1915 /*
1916 * we will be copying header into skb->data in
1917 * pskb_may_pull so it is in our interest to prefetch
1918 * it now to avoid a possible cache miss
1919 */
1920 prefetchw(skb->data);
1921
1922 /*
1923 * Delay unmapping of the first packet. It carries the
1924 * header information, HW may still access the header
1925 * after the writeback. Only unmap it when EOP is
1926 * reached
1927 */
1928 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1929 goto dma_sync;
1930
1931 IXGBE_CB(skb)->dma = rx_buffer->dma;
1932 } else {
1933 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1934 ixgbe_dma_sync_frag(rx_ring, skb);
1935
1936 dma_sync:
1937 /* we are reusing so sync this buffer for CPU use */
1938 dma_sync_single_range_for_cpu(rx_ring->dev,
1939 rx_buffer->dma,
1940 rx_buffer->page_offset,
1941 ixgbe_rx_bufsz(rx_ring),
1942 DMA_FROM_DEVICE);
1943 }
1944
1945 /* pull page into skb */
1946 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1947 /* hand second half of page back to the ring */
1948 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1949 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1950 /* the page has been released from the ring */
1951 IXGBE_CB(skb)->page_released = true;
1952 } else {
1953 /* we are not reusing the buffer so unmap it */
1954 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1955 ixgbe_rx_pg_size(rx_ring),
1956 DMA_FROM_DEVICE);
1957 }
1958
1959 /* clear contents of buffer_info */
1960 rx_buffer->skb = NULL;
1961 rx_buffer->dma = 0;
1962 rx_buffer->page = NULL;
1963
1964 return skb;
1965 }
1966
1967 /**
1968 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1969 * @q_vector: structure containing interrupt and ring information
1970 * @rx_ring: rx descriptor ring to transact packets on
1971 * @budget: Total limit on number of packets to process
1972 *
1973 * This function provides a "bounce buffer" approach to Rx interrupt
1974 * processing. The advantage to this is that on systems that have
1975 * expensive overhead for IOMMU access this provides a means of avoiding
1976 * it by maintaining the mapping of the page to the syste.
1977 *
1978 * Returns amount of work completed
1979 **/
1980 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1981 struct ixgbe_ring *rx_ring,
1982 const int budget)
1983 {
1984 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1985 #ifdef IXGBE_FCOE
1986 struct ixgbe_adapter *adapter = q_vector->adapter;
1987 int ddp_bytes;
1988 unsigned int mss = 0;
1989 #endif /* IXGBE_FCOE */
1990 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1991
1992 do {
1993 union ixgbe_adv_rx_desc *rx_desc;
1994 struct sk_buff *skb;
1995
1996 /* return some buffers to hardware, one at a time is too slow */
1997 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1998 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1999 cleaned_count = 0;
2000 }
2001
2002 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2003
2004 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2005 break;
2006
2007 /*
2008 * This memory barrier is needed to keep us from reading
2009 * any other fields out of the rx_desc until we know the
2010 * RXD_STAT_DD bit is set
2011 */
2012 rmb();
2013
2014 /* retrieve a buffer from the ring */
2015 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
2016
2017 /* exit if we failed to retrieve a buffer */
2018 if (!skb)
2019 break;
2020
2021 cleaned_count++;
2022
2023 /* place incomplete frames back on ring for completion */
2024 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2025 continue;
2026
2027 /* verify the packet layout is correct */
2028 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2029 continue;
2030
2031 /* probably a little skewed due to removing CRC */
2032 total_rx_bytes += skb->len;
2033
2034 /* populate checksum, timestamp, VLAN, and protocol */
2035 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2036
2037 #ifdef IXGBE_FCOE
2038 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2039 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2040 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2041 /* include DDPed FCoE data */
2042 if (ddp_bytes > 0) {
2043 if (!mss) {
2044 mss = rx_ring->netdev->mtu -
2045 sizeof(struct fcoe_hdr) -
2046 sizeof(struct fc_frame_header) -
2047 sizeof(struct fcoe_crc_eof);
2048 if (mss > 512)
2049 mss &= ~511;
2050 }
2051 total_rx_bytes += ddp_bytes;
2052 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2053 mss);
2054 }
2055 if (!ddp_bytes) {
2056 dev_kfree_skb_any(skb);
2057 continue;
2058 }
2059 }
2060
2061 #endif /* IXGBE_FCOE */
2062 skb_mark_napi_id(skb, &q_vector->napi);
2063 ixgbe_rx_skb(q_vector, skb);
2064
2065 /* update budget accounting */
2066 total_rx_packets++;
2067 } while (likely(total_rx_packets < budget));
2068
2069 u64_stats_update_begin(&rx_ring->syncp);
2070 rx_ring->stats.packets += total_rx_packets;
2071 rx_ring->stats.bytes += total_rx_bytes;
2072 u64_stats_update_end(&rx_ring->syncp);
2073 q_vector->rx.total_packets += total_rx_packets;
2074 q_vector->rx.total_bytes += total_rx_bytes;
2075
2076 if (cleaned_count)
2077 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2078
2079 return total_rx_packets;
2080 }
2081
2082 #ifdef CONFIG_NET_RX_BUSY_POLL
2083 /* must be called with local_bh_disable()d */
2084 static int ixgbe_low_latency_recv(struct napi_struct *napi)
2085 {
2086 struct ixgbe_q_vector *q_vector =
2087 container_of(napi, struct ixgbe_q_vector, napi);
2088 struct ixgbe_adapter *adapter = q_vector->adapter;
2089 struct ixgbe_ring *ring;
2090 int found = 0;
2091
2092 if (test_bit(__IXGBE_DOWN, &adapter->state))
2093 return LL_FLUSH_FAILED;
2094
2095 if (!ixgbe_qv_lock_poll(q_vector))
2096 return LL_FLUSH_BUSY;
2097
2098 ixgbe_for_each_ring(ring, q_vector->rx) {
2099 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
2100 #ifdef LL_EXTENDED_STATS
2101 if (found)
2102 ring->stats.cleaned += found;
2103 else
2104 ring->stats.misses++;
2105 #endif
2106 if (found)
2107 break;
2108 }
2109
2110 ixgbe_qv_unlock_poll(q_vector);
2111
2112 return found;
2113 }
2114 #endif /* CONFIG_NET_RX_BUSY_POLL */
2115
2116 /**
2117 * ixgbe_configure_msix - Configure MSI-X hardware
2118 * @adapter: board private structure
2119 *
2120 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2121 * interrupts.
2122 **/
2123 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2124 {
2125 struct ixgbe_q_vector *q_vector;
2126 int v_idx;
2127 u32 mask;
2128
2129 /* Populate MSIX to EITR Select */
2130 if (adapter->num_vfs > 32) {
2131 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2132 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2133 }
2134
2135 /*
2136 * Populate the IVAR table and set the ITR values to the
2137 * corresponding register.
2138 */
2139 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2140 struct ixgbe_ring *ring;
2141 q_vector = adapter->q_vector[v_idx];
2142
2143 ixgbe_for_each_ring(ring, q_vector->rx)
2144 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2145
2146 ixgbe_for_each_ring(ring, q_vector->tx)
2147 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2148
2149 ixgbe_write_eitr(q_vector);
2150 }
2151
2152 switch (adapter->hw.mac.type) {
2153 case ixgbe_mac_82598EB:
2154 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2155 v_idx);
2156 break;
2157 case ixgbe_mac_82599EB:
2158 case ixgbe_mac_X540:
2159 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2160 break;
2161 default:
2162 break;
2163 }
2164 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2165
2166 /* set up to autoclear timer, and the vectors */
2167 mask = IXGBE_EIMS_ENABLE_MASK;
2168 mask &= ~(IXGBE_EIMS_OTHER |
2169 IXGBE_EIMS_MAILBOX |
2170 IXGBE_EIMS_LSC);
2171
2172 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2173 }
2174
2175 enum latency_range {
2176 lowest_latency = 0,
2177 low_latency = 1,
2178 bulk_latency = 2,
2179 latency_invalid = 255
2180 };
2181
2182 /**
2183 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2184 * @q_vector: structure containing interrupt and ring information
2185 * @ring_container: structure containing ring performance data
2186 *
2187 * Stores a new ITR value based on packets and byte
2188 * counts during the last interrupt. The advantage of per interrupt
2189 * computation is faster updates and more accurate ITR for the current
2190 * traffic pattern. Constants in this function were computed
2191 * based on theoretical maximum wire speed and thresholds were set based
2192 * on testing data as well as attempting to minimize response time
2193 * while increasing bulk throughput.
2194 * this functionality is controlled by the InterruptThrottleRate module
2195 * parameter (see ixgbe_param.c)
2196 **/
2197 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2198 struct ixgbe_ring_container *ring_container)
2199 {
2200 int bytes = ring_container->total_bytes;
2201 int packets = ring_container->total_packets;
2202 u32 timepassed_us;
2203 u64 bytes_perint;
2204 u8 itr_setting = ring_container->itr;
2205
2206 if (packets == 0)
2207 return;
2208
2209 /* simple throttlerate management
2210 * 0-10MB/s lowest (100000 ints/s)
2211 * 10-20MB/s low (20000 ints/s)
2212 * 20-1249MB/s bulk (8000 ints/s)
2213 */
2214 /* what was last interrupt timeslice? */
2215 timepassed_us = q_vector->itr >> 2;
2216 if (timepassed_us == 0)
2217 return;
2218
2219 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2220
2221 switch (itr_setting) {
2222 case lowest_latency:
2223 if (bytes_perint > 10)
2224 itr_setting = low_latency;
2225 break;
2226 case low_latency:
2227 if (bytes_perint > 20)
2228 itr_setting = bulk_latency;
2229 else if (bytes_perint <= 10)
2230 itr_setting = lowest_latency;
2231 break;
2232 case bulk_latency:
2233 if (bytes_perint <= 20)
2234 itr_setting = low_latency;
2235 break;
2236 }
2237
2238 /* clear work counters since we have the values we need */
2239 ring_container->total_bytes = 0;
2240 ring_container->total_packets = 0;
2241
2242 /* write updated itr to ring container */
2243 ring_container->itr = itr_setting;
2244 }
2245
2246 /**
2247 * ixgbe_write_eitr - write EITR register in hardware specific way
2248 * @q_vector: structure containing interrupt and ring information
2249 *
2250 * This function is made to be called by ethtool and by the driver
2251 * when it needs to update EITR registers at runtime. Hardware
2252 * specific quirks/differences are taken care of here.
2253 */
2254 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2255 {
2256 struct ixgbe_adapter *adapter = q_vector->adapter;
2257 struct ixgbe_hw *hw = &adapter->hw;
2258 int v_idx = q_vector->v_idx;
2259 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2260
2261 switch (adapter->hw.mac.type) {
2262 case ixgbe_mac_82598EB:
2263 /* must write high and low 16 bits to reset counter */
2264 itr_reg |= (itr_reg << 16);
2265 break;
2266 case ixgbe_mac_82599EB:
2267 case ixgbe_mac_X540:
2268 /*
2269 * set the WDIS bit to not clear the timer bits and cause an
2270 * immediate assertion of the interrupt
2271 */
2272 itr_reg |= IXGBE_EITR_CNT_WDIS;
2273 break;
2274 default:
2275 break;
2276 }
2277 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2278 }
2279
2280 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2281 {
2282 u32 new_itr = q_vector->itr;
2283 u8 current_itr;
2284
2285 ixgbe_update_itr(q_vector, &q_vector->tx);
2286 ixgbe_update_itr(q_vector, &q_vector->rx);
2287
2288 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2289
2290 switch (current_itr) {
2291 /* counts and packets in update_itr are dependent on these numbers */
2292 case lowest_latency:
2293 new_itr = IXGBE_100K_ITR;
2294 break;
2295 case low_latency:
2296 new_itr = IXGBE_20K_ITR;
2297 break;
2298 case bulk_latency:
2299 new_itr = IXGBE_8K_ITR;
2300 break;
2301 default:
2302 break;
2303 }
2304
2305 if (new_itr != q_vector->itr) {
2306 /* do an exponential smoothing */
2307 new_itr = (10 * new_itr * q_vector->itr) /
2308 ((9 * new_itr) + q_vector->itr);
2309
2310 /* save the algorithm value here */
2311 q_vector->itr = new_itr;
2312
2313 ixgbe_write_eitr(q_vector);
2314 }
2315 }
2316
2317 /**
2318 * ixgbe_check_overtemp_subtask - check for over temperature
2319 * @adapter: pointer to adapter
2320 **/
2321 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2322 {
2323 struct ixgbe_hw *hw = &adapter->hw;
2324 u32 eicr = adapter->interrupt_event;
2325
2326 if (test_bit(__IXGBE_DOWN, &adapter->state))
2327 return;
2328
2329 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2330 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2331 return;
2332
2333 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2334
2335 switch (hw->device_id) {
2336 case IXGBE_DEV_ID_82599_T3_LOM:
2337 /*
2338 * Since the warning interrupt is for both ports
2339 * we don't have to check if:
2340 * - This interrupt wasn't for our port.
2341 * - We may have missed the interrupt so always have to
2342 * check if we got a LSC
2343 */
2344 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2345 !(eicr & IXGBE_EICR_LSC))
2346 return;
2347
2348 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2349 u32 speed;
2350 bool link_up = false;
2351
2352 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2353
2354 if (link_up)
2355 return;
2356 }
2357
2358 /* Check if this is not due to overtemp */
2359 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2360 return;
2361
2362 break;
2363 default:
2364 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2365 return;
2366 break;
2367 }
2368 e_crit(drv,
2369 "Network adapter has been stopped because it has over heated. "
2370 "Restart the computer. If the problem persists, "
2371 "power off the system and replace the adapter\n");
2372
2373 adapter->interrupt_event = 0;
2374 }
2375
2376 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2377 {
2378 struct ixgbe_hw *hw = &adapter->hw;
2379
2380 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2381 (eicr & IXGBE_EICR_GPI_SDP1)) {
2382 e_crit(probe, "Fan has stopped, replace the adapter\n");
2383 /* write to clear the interrupt */
2384 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2385 }
2386 }
2387
2388 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2389 {
2390 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2391 return;
2392
2393 switch (adapter->hw.mac.type) {
2394 case ixgbe_mac_82599EB:
2395 /*
2396 * Need to check link state so complete overtemp check
2397 * on service task
2398 */
2399 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2400 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2401 adapter->interrupt_event = eicr;
2402 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2403 ixgbe_service_event_schedule(adapter);
2404 return;
2405 }
2406 return;
2407 case ixgbe_mac_X540:
2408 if (!(eicr & IXGBE_EICR_TS))
2409 return;
2410 break;
2411 default:
2412 return;
2413 }
2414
2415 e_crit(drv,
2416 "Network adapter has been stopped because it has over heated. "
2417 "Restart the computer. If the problem persists, "
2418 "power off the system and replace the adapter\n");
2419 }
2420
2421 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2422 {
2423 struct ixgbe_hw *hw = &adapter->hw;
2424
2425 if (eicr & IXGBE_EICR_GPI_SDP2) {
2426 /* Clear the interrupt */
2427 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2428 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2429 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2430 ixgbe_service_event_schedule(adapter);
2431 }
2432 }
2433
2434 if (eicr & IXGBE_EICR_GPI_SDP1) {
2435 /* Clear the interrupt */
2436 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2437 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2438 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2439 ixgbe_service_event_schedule(adapter);
2440 }
2441 }
2442 }
2443
2444 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2445 {
2446 struct ixgbe_hw *hw = &adapter->hw;
2447
2448 adapter->lsc_int++;
2449 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2450 adapter->link_check_timeout = jiffies;
2451 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2452 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2453 IXGBE_WRITE_FLUSH(hw);
2454 ixgbe_service_event_schedule(adapter);
2455 }
2456 }
2457
2458 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2459 u64 qmask)
2460 {
2461 u32 mask;
2462 struct ixgbe_hw *hw = &adapter->hw;
2463
2464 switch (hw->mac.type) {
2465 case ixgbe_mac_82598EB:
2466 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2467 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2468 break;
2469 case ixgbe_mac_82599EB:
2470 case ixgbe_mac_X540:
2471 mask = (qmask & 0xFFFFFFFF);
2472 if (mask)
2473 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2474 mask = (qmask >> 32);
2475 if (mask)
2476 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2477 break;
2478 default:
2479 break;
2480 }
2481 /* skip the flush */
2482 }
2483
2484 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2485 u64 qmask)
2486 {
2487 u32 mask;
2488 struct ixgbe_hw *hw = &adapter->hw;
2489
2490 switch (hw->mac.type) {
2491 case ixgbe_mac_82598EB:
2492 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2493 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2494 break;
2495 case ixgbe_mac_82599EB:
2496 case ixgbe_mac_X540:
2497 mask = (qmask & 0xFFFFFFFF);
2498 if (mask)
2499 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2500 mask = (qmask >> 32);
2501 if (mask)
2502 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2503 break;
2504 default:
2505 break;
2506 }
2507 /* skip the flush */
2508 }
2509
2510 /**
2511 * ixgbe_irq_enable - Enable default interrupt generation settings
2512 * @adapter: board private structure
2513 **/
2514 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2515 bool flush)
2516 {
2517 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2518
2519 /* don't reenable LSC while waiting for link */
2520 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2521 mask &= ~IXGBE_EIMS_LSC;
2522
2523 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2524 switch (adapter->hw.mac.type) {
2525 case ixgbe_mac_82599EB:
2526 mask |= IXGBE_EIMS_GPI_SDP0;
2527 break;
2528 case ixgbe_mac_X540:
2529 mask |= IXGBE_EIMS_TS;
2530 break;
2531 default:
2532 break;
2533 }
2534 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2535 mask |= IXGBE_EIMS_GPI_SDP1;
2536 switch (adapter->hw.mac.type) {
2537 case ixgbe_mac_82599EB:
2538 mask |= IXGBE_EIMS_GPI_SDP1;
2539 mask |= IXGBE_EIMS_GPI_SDP2;
2540 case ixgbe_mac_X540:
2541 mask |= IXGBE_EIMS_ECC;
2542 mask |= IXGBE_EIMS_MAILBOX;
2543 break;
2544 default:
2545 break;
2546 }
2547
2548 if (adapter->hw.mac.type == ixgbe_mac_X540)
2549 mask |= IXGBE_EIMS_TIMESYNC;
2550
2551 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2552 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2553 mask |= IXGBE_EIMS_FLOW_DIR;
2554
2555 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2556 if (queues)
2557 ixgbe_irq_enable_queues(adapter, ~0);
2558 if (flush)
2559 IXGBE_WRITE_FLUSH(&adapter->hw);
2560 }
2561
2562 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2563 {
2564 struct ixgbe_adapter *adapter = data;
2565 struct ixgbe_hw *hw = &adapter->hw;
2566 u32 eicr;
2567
2568 /*
2569 * Workaround for Silicon errata. Use clear-by-write instead
2570 * of clear-by-read. Reading with EICS will return the
2571 * interrupt causes without clearing, which later be done
2572 * with the write to EICR.
2573 */
2574 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2575
2576 /* The lower 16bits of the EICR register are for the queue interrupts
2577 * which should be masked here in order to not accidently clear them if
2578 * the bits are high when ixgbe_msix_other is called. There is a race
2579 * condition otherwise which results in possible performance loss
2580 * especially if the ixgbe_msix_other interrupt is triggering
2581 * consistently (as it would when PPS is turned on for the X540 device)
2582 */
2583 eicr &= 0xFFFF0000;
2584
2585 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2586
2587 if (eicr & IXGBE_EICR_LSC)
2588 ixgbe_check_lsc(adapter);
2589
2590 if (eicr & IXGBE_EICR_MAILBOX)
2591 ixgbe_msg_task(adapter);
2592
2593 switch (hw->mac.type) {
2594 case ixgbe_mac_82599EB:
2595 case ixgbe_mac_X540:
2596 if (eicr & IXGBE_EICR_ECC)
2597 e_info(link, "Received unrecoverable ECC Err, please "
2598 "reboot\n");
2599 /* Handle Flow Director Full threshold interrupt */
2600 if (eicr & IXGBE_EICR_FLOW_DIR) {
2601 int reinit_count = 0;
2602 int i;
2603 for (i = 0; i < adapter->num_tx_queues; i++) {
2604 struct ixgbe_ring *ring = adapter->tx_ring[i];
2605 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2606 &ring->state))
2607 reinit_count++;
2608 }
2609 if (reinit_count) {
2610 /* no more flow director interrupts until after init */
2611 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2612 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2613 ixgbe_service_event_schedule(adapter);
2614 }
2615 }
2616 ixgbe_check_sfp_event(adapter, eicr);
2617 ixgbe_check_overtemp_event(adapter, eicr);
2618 break;
2619 default:
2620 break;
2621 }
2622
2623 ixgbe_check_fan_failure(adapter, eicr);
2624
2625 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2626 ixgbe_ptp_check_pps_event(adapter, eicr);
2627
2628 /* re-enable the original interrupt state, no lsc, no queues */
2629 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2630 ixgbe_irq_enable(adapter, false, false);
2631
2632 return IRQ_HANDLED;
2633 }
2634
2635 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2636 {
2637 struct ixgbe_q_vector *q_vector = data;
2638
2639 /* EIAM disabled interrupts (on this vector) for us */
2640
2641 if (q_vector->rx.ring || q_vector->tx.ring)
2642 napi_schedule(&q_vector->napi);
2643
2644 return IRQ_HANDLED;
2645 }
2646
2647 /**
2648 * ixgbe_poll - NAPI Rx polling callback
2649 * @napi: structure for representing this polling device
2650 * @budget: how many packets driver is allowed to clean
2651 *
2652 * This function is used for legacy and MSI, NAPI mode
2653 **/
2654 int ixgbe_poll(struct napi_struct *napi, int budget)
2655 {
2656 struct ixgbe_q_vector *q_vector =
2657 container_of(napi, struct ixgbe_q_vector, napi);
2658 struct ixgbe_adapter *adapter = q_vector->adapter;
2659 struct ixgbe_ring *ring;
2660 int per_ring_budget;
2661 bool clean_complete = true;
2662
2663 #ifdef CONFIG_IXGBE_DCA
2664 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2665 ixgbe_update_dca(q_vector);
2666 #endif
2667
2668 ixgbe_for_each_ring(ring, q_vector->tx)
2669 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2670
2671 if (!ixgbe_qv_lock_napi(q_vector))
2672 return budget;
2673
2674 /* attempt to distribute budget to each queue fairly, but don't allow
2675 * the budget to go below 1 because we'll exit polling */
2676 if (q_vector->rx.count > 1)
2677 per_ring_budget = max(budget/q_vector->rx.count, 1);
2678 else
2679 per_ring_budget = budget;
2680
2681 ixgbe_for_each_ring(ring, q_vector->rx)
2682 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2683 per_ring_budget) < per_ring_budget);
2684
2685 ixgbe_qv_unlock_napi(q_vector);
2686 /* If all work not completed, return budget and keep polling */
2687 if (!clean_complete)
2688 return budget;
2689
2690 /* all work done, exit the polling mode */
2691 napi_complete(napi);
2692 if (adapter->rx_itr_setting & 1)
2693 ixgbe_set_itr(q_vector);
2694 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2695 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2696
2697 return 0;
2698 }
2699
2700 /**
2701 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2702 * @adapter: board private structure
2703 *
2704 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2705 * interrupts from the kernel.
2706 **/
2707 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2708 {
2709 struct net_device *netdev = adapter->netdev;
2710 int vector, err;
2711 int ri = 0, ti = 0;
2712
2713 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2714 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2715 struct msix_entry *entry = &adapter->msix_entries[vector];
2716
2717 if (q_vector->tx.ring && q_vector->rx.ring) {
2718 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2719 "%s-%s-%d", netdev->name, "TxRx", ri++);
2720 ti++;
2721 } else if (q_vector->rx.ring) {
2722 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2723 "%s-%s-%d", netdev->name, "rx", ri++);
2724 } else if (q_vector->tx.ring) {
2725 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2726 "%s-%s-%d", netdev->name, "tx", ti++);
2727 } else {
2728 /* skip this unused q_vector */
2729 continue;
2730 }
2731 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2732 q_vector->name, q_vector);
2733 if (err) {
2734 e_err(probe, "request_irq failed for MSIX interrupt "
2735 "Error: %d\n", err);
2736 goto free_queue_irqs;
2737 }
2738 /* If Flow Director is enabled, set interrupt affinity */
2739 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2740 /* assign the mask for this irq */
2741 irq_set_affinity_hint(entry->vector,
2742 &q_vector->affinity_mask);
2743 }
2744 }
2745
2746 err = request_irq(adapter->msix_entries[vector].vector,
2747 ixgbe_msix_other, 0, netdev->name, adapter);
2748 if (err) {
2749 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2750 goto free_queue_irqs;
2751 }
2752
2753 return 0;
2754
2755 free_queue_irqs:
2756 while (vector) {
2757 vector--;
2758 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2759 NULL);
2760 free_irq(adapter->msix_entries[vector].vector,
2761 adapter->q_vector[vector]);
2762 }
2763 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2764 pci_disable_msix(adapter->pdev);
2765 kfree(adapter->msix_entries);
2766 adapter->msix_entries = NULL;
2767 return err;
2768 }
2769
2770 /**
2771 * ixgbe_intr - legacy mode Interrupt Handler
2772 * @irq: interrupt number
2773 * @data: pointer to a network interface device structure
2774 **/
2775 static irqreturn_t ixgbe_intr(int irq, void *data)
2776 {
2777 struct ixgbe_adapter *adapter = data;
2778 struct ixgbe_hw *hw = &adapter->hw;
2779 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2780 u32 eicr;
2781
2782 /*
2783 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2784 * before the read of EICR.
2785 */
2786 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2787
2788 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2789 * therefore no explicit interrupt disable is necessary */
2790 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2791 if (!eicr) {
2792 /*
2793 * shared interrupt alert!
2794 * make sure interrupts are enabled because the read will
2795 * have disabled interrupts due to EIAM
2796 * finish the workaround of silicon errata on 82598. Unmask
2797 * the interrupt that we masked before the EICR read.
2798 */
2799 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2800 ixgbe_irq_enable(adapter, true, true);
2801 return IRQ_NONE; /* Not our interrupt */
2802 }
2803
2804 if (eicr & IXGBE_EICR_LSC)
2805 ixgbe_check_lsc(adapter);
2806
2807 switch (hw->mac.type) {
2808 case ixgbe_mac_82599EB:
2809 ixgbe_check_sfp_event(adapter, eicr);
2810 /* Fall through */
2811 case ixgbe_mac_X540:
2812 if (eicr & IXGBE_EICR_ECC)
2813 e_info(link, "Received unrecoverable ECC err, please "
2814 "reboot\n");
2815 ixgbe_check_overtemp_event(adapter, eicr);
2816 break;
2817 default:
2818 break;
2819 }
2820
2821 ixgbe_check_fan_failure(adapter, eicr);
2822 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2823 ixgbe_ptp_check_pps_event(adapter, eicr);
2824
2825 /* would disable interrupts here but EIAM disabled it */
2826 napi_schedule(&q_vector->napi);
2827
2828 /*
2829 * re-enable link(maybe) and non-queue interrupts, no flush.
2830 * ixgbe_poll will re-enable the queue interrupts
2831 */
2832 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2833 ixgbe_irq_enable(adapter, false, false);
2834
2835 return IRQ_HANDLED;
2836 }
2837
2838 /**
2839 * ixgbe_request_irq - initialize interrupts
2840 * @adapter: board private structure
2841 *
2842 * Attempts to configure interrupts using the best available
2843 * capabilities of the hardware and kernel.
2844 **/
2845 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2846 {
2847 struct net_device *netdev = adapter->netdev;
2848 int err;
2849
2850 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2851 err = ixgbe_request_msix_irqs(adapter);
2852 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2853 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2854 netdev->name, adapter);
2855 else
2856 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2857 netdev->name, adapter);
2858
2859 if (err)
2860 e_err(probe, "request_irq failed, Error %d\n", err);
2861
2862 return err;
2863 }
2864
2865 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2866 {
2867 int vector;
2868
2869 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2870 free_irq(adapter->pdev->irq, adapter);
2871 return;
2872 }
2873
2874 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2875 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2876 struct msix_entry *entry = &adapter->msix_entries[vector];
2877
2878 /* free only the irqs that were actually requested */
2879 if (!q_vector->rx.ring && !q_vector->tx.ring)
2880 continue;
2881
2882 /* clear the affinity_mask in the IRQ descriptor */
2883 irq_set_affinity_hint(entry->vector, NULL);
2884
2885 free_irq(entry->vector, q_vector);
2886 }
2887
2888 free_irq(adapter->msix_entries[vector++].vector, adapter);
2889 }
2890
2891 /**
2892 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2893 * @adapter: board private structure
2894 **/
2895 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2896 {
2897 switch (adapter->hw.mac.type) {
2898 case ixgbe_mac_82598EB:
2899 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2900 break;
2901 case ixgbe_mac_82599EB:
2902 case ixgbe_mac_X540:
2903 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2904 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2905 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2906 break;
2907 default:
2908 break;
2909 }
2910 IXGBE_WRITE_FLUSH(&adapter->hw);
2911 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2912 int vector;
2913
2914 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2915 synchronize_irq(adapter->msix_entries[vector].vector);
2916
2917 synchronize_irq(adapter->msix_entries[vector++].vector);
2918 } else {
2919 synchronize_irq(adapter->pdev->irq);
2920 }
2921 }
2922
2923 /**
2924 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2925 *
2926 **/
2927 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2928 {
2929 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2930
2931 ixgbe_write_eitr(q_vector);
2932
2933 ixgbe_set_ivar(adapter, 0, 0, 0);
2934 ixgbe_set_ivar(adapter, 1, 0, 0);
2935
2936 e_info(hw, "Legacy interrupt IVAR setup done\n");
2937 }
2938
2939 /**
2940 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2941 * @adapter: board private structure
2942 * @ring: structure containing ring specific data
2943 *
2944 * Configure the Tx descriptor ring after a reset.
2945 **/
2946 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2947 struct ixgbe_ring *ring)
2948 {
2949 struct ixgbe_hw *hw = &adapter->hw;
2950 u64 tdba = ring->dma;
2951 int wait_loop = 10;
2952 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2953 u8 reg_idx = ring->reg_idx;
2954
2955 /* disable queue to avoid issues while updating state */
2956 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2957 IXGBE_WRITE_FLUSH(hw);
2958
2959 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2960 (tdba & DMA_BIT_MASK(32)));
2961 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2962 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2963 ring->count * sizeof(union ixgbe_adv_tx_desc));
2964 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2965 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2966 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2967
2968 /*
2969 * set WTHRESH to encourage burst writeback, it should not be set
2970 * higher than 1 when:
2971 * - ITR is 0 as it could cause false TX hangs
2972 * - ITR is set to > 100k int/sec and BQL is enabled
2973 *
2974 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2975 * to or less than the number of on chip descriptors, which is
2976 * currently 40.
2977 */
2978 #if IS_ENABLED(CONFIG_BQL)
2979 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
2980 #else
2981 if (!ring->q_vector || (ring->q_vector->itr < 8))
2982 #endif
2983 txdctl |= (1 << 16); /* WTHRESH = 1 */
2984 else
2985 txdctl |= (8 << 16); /* WTHRESH = 8 */
2986
2987 /*
2988 * Setting PTHRESH to 32 both improves performance
2989 * and avoids a TX hang with DFP enabled
2990 */
2991 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2992 32; /* PTHRESH = 32 */
2993
2994 /* reinitialize flowdirector state */
2995 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2996 ring->atr_sample_rate = adapter->atr_sample_rate;
2997 ring->atr_count = 0;
2998 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2999 } else {
3000 ring->atr_sample_rate = 0;
3001 }
3002
3003 /* initialize XPS */
3004 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3005 struct ixgbe_q_vector *q_vector = ring->q_vector;
3006
3007 if (q_vector)
3008 netif_set_xps_queue(adapter->netdev,
3009 &q_vector->affinity_mask,
3010 ring->queue_index);
3011 }
3012
3013 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3014
3015 /* enable queue */
3016 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3017
3018 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3019 if (hw->mac.type == ixgbe_mac_82598EB &&
3020 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3021 return;
3022
3023 /* poll to verify queue is enabled */
3024 do {
3025 usleep_range(1000, 2000);
3026 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3027 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3028 if (!wait_loop)
3029 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
3030 }
3031
3032 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3033 {
3034 struct ixgbe_hw *hw = &adapter->hw;
3035 u32 rttdcs, mtqc;
3036 u8 tcs = netdev_get_num_tc(adapter->netdev);
3037
3038 if (hw->mac.type == ixgbe_mac_82598EB)
3039 return;
3040
3041 /* disable the arbiter while setting MTQC */
3042 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3043 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3044 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3045
3046 /* set transmit pool layout */
3047 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3048 mtqc = IXGBE_MTQC_VT_ENA;
3049 if (tcs > 4)
3050 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3051 else if (tcs > 1)
3052 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3053 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3054 mtqc |= IXGBE_MTQC_32VF;
3055 else
3056 mtqc |= IXGBE_MTQC_64VF;
3057 } else {
3058 if (tcs > 4)
3059 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3060 else if (tcs > 1)
3061 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3062 else
3063 mtqc = IXGBE_MTQC_64Q_1PB;
3064 }
3065
3066 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3067
3068 /* Enable Security TX Buffer IFG for multiple pb */
3069 if (tcs) {
3070 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3071 sectx |= IXGBE_SECTX_DCB;
3072 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3073 }
3074
3075 /* re-enable the arbiter */
3076 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3077 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3078 }
3079
3080 /**
3081 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3082 * @adapter: board private structure
3083 *
3084 * Configure the Tx unit of the MAC after a reset.
3085 **/
3086 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3087 {
3088 struct ixgbe_hw *hw = &adapter->hw;
3089 u32 dmatxctl;
3090 u32 i;
3091
3092 ixgbe_setup_mtqc(adapter);
3093
3094 if (hw->mac.type != ixgbe_mac_82598EB) {
3095 /* DMATXCTL.EN must be before Tx queues are enabled */
3096 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3097 dmatxctl |= IXGBE_DMATXCTL_TE;
3098 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3099 }
3100
3101 /* Setup the HW Tx Head and Tail descriptor pointers */
3102 for (i = 0; i < adapter->num_tx_queues; i++)
3103 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3104 }
3105
3106 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3107 struct ixgbe_ring *ring)
3108 {
3109 struct ixgbe_hw *hw = &adapter->hw;
3110 u8 reg_idx = ring->reg_idx;
3111 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3112
3113 srrctl |= IXGBE_SRRCTL_DROP_EN;
3114
3115 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3116 }
3117
3118 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3119 struct ixgbe_ring *ring)
3120 {
3121 struct ixgbe_hw *hw = &adapter->hw;
3122 u8 reg_idx = ring->reg_idx;
3123 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3124
3125 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3126
3127 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3128 }
3129
3130 #ifdef CONFIG_IXGBE_DCB
3131 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3132 #else
3133 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3134 #endif
3135 {
3136 int i;
3137 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3138
3139 if (adapter->ixgbe_ieee_pfc)
3140 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3141
3142 /*
3143 * We should set the drop enable bit if:
3144 * SR-IOV is enabled
3145 * or
3146 * Number of Rx queues > 1 and flow control is disabled
3147 *
3148 * This allows us to avoid head of line blocking for security
3149 * and performance reasons.
3150 */
3151 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3152 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3153 for (i = 0; i < adapter->num_rx_queues; i++)
3154 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3155 } else {
3156 for (i = 0; i < adapter->num_rx_queues; i++)
3157 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3158 }
3159 }
3160
3161 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3162
3163 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3164 struct ixgbe_ring *rx_ring)
3165 {
3166 struct ixgbe_hw *hw = &adapter->hw;
3167 u32 srrctl;
3168 u8 reg_idx = rx_ring->reg_idx;
3169
3170 if (hw->mac.type == ixgbe_mac_82598EB) {
3171 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3172
3173 /*
3174 * if VMDq is not active we must program one srrctl register
3175 * per RSS queue since we have enabled RDRXCTL.MVMEN
3176 */
3177 reg_idx &= mask;
3178 }
3179
3180 /* configure header buffer length, needed for RSC */
3181 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3182
3183 /* configure the packet buffer length */
3184 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3185
3186 /* configure descriptor type */
3187 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3188
3189 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3190 }
3191
3192 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3193 {
3194 struct ixgbe_hw *hw = &adapter->hw;
3195 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
3196 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3197 0x6A3E67EA, 0x14364D17, 0x3BED200D};
3198 u32 mrqc = 0, reta = 0;
3199 u32 rxcsum;
3200 int i, j;
3201 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3202
3203 /*
3204 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3205 * make full use of any rings they may have. We will use the
3206 * PSRTYPE register to control how many rings we use within the PF.
3207 */
3208 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3209 rss_i = 2;
3210
3211 /* Fill out hash function seeds */
3212 for (i = 0; i < 10; i++)
3213 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3214
3215 /* Fill out redirection table */
3216 for (i = 0, j = 0; i < 128; i++, j++) {
3217 if (j == rss_i)
3218 j = 0;
3219 /* reta = 4-byte sliding window of
3220 * 0x00..(indices-1)(indices-1)00..etc. */
3221 reta = (reta << 8) | (j * 0x11);
3222 if ((i & 3) == 3)
3223 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3224 }
3225
3226 /* Disable indicating checksum in descriptor, enables RSS hash */
3227 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3228 rxcsum |= IXGBE_RXCSUM_PCSD;
3229 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3230
3231 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3232 if (adapter->ring_feature[RING_F_RSS].mask)
3233 mrqc = IXGBE_MRQC_RSSEN;
3234 } else {
3235 u8 tcs = netdev_get_num_tc(adapter->netdev);
3236
3237 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3238 if (tcs > 4)
3239 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3240 else if (tcs > 1)
3241 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3242 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3243 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3244 else
3245 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3246 } else {
3247 if (tcs > 4)
3248 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3249 else if (tcs > 1)
3250 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3251 else
3252 mrqc = IXGBE_MRQC_RSSEN;
3253 }
3254 }
3255
3256 /* Perform hash on these packet types */
3257 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3258 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3259 IXGBE_MRQC_RSS_FIELD_IPV6 |
3260 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3261
3262 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3263 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3264 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3265 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3266
3267 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3268 }
3269
3270 /**
3271 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3272 * @adapter: address of board private structure
3273 * @index: index of ring to set
3274 **/
3275 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3276 struct ixgbe_ring *ring)
3277 {
3278 struct ixgbe_hw *hw = &adapter->hw;
3279 u32 rscctrl;
3280 u8 reg_idx = ring->reg_idx;
3281
3282 if (!ring_is_rsc_enabled(ring))
3283 return;
3284
3285 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3286 rscctrl |= IXGBE_RSCCTL_RSCEN;
3287 /*
3288 * we must limit the number of descriptors so that the
3289 * total size of max desc * buf_len is not greater
3290 * than 65536
3291 */
3292 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3293 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3294 }
3295
3296 #define IXGBE_MAX_RX_DESC_POLL 10
3297 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3298 struct ixgbe_ring *ring)
3299 {
3300 struct ixgbe_hw *hw = &adapter->hw;
3301 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3302 u32 rxdctl;
3303 u8 reg_idx = ring->reg_idx;
3304
3305 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3306 if (hw->mac.type == ixgbe_mac_82598EB &&
3307 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3308 return;
3309
3310 do {
3311 usleep_range(1000, 2000);
3312 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3313 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3314
3315 if (!wait_loop) {
3316 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3317 "the polling period\n", reg_idx);
3318 }
3319 }
3320
3321 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3322 struct ixgbe_ring *ring)
3323 {
3324 struct ixgbe_hw *hw = &adapter->hw;
3325 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3326 u32 rxdctl;
3327 u8 reg_idx = ring->reg_idx;
3328
3329 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3330 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3331
3332 /* write value back with RXDCTL.ENABLE bit cleared */
3333 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3334
3335 if (hw->mac.type == ixgbe_mac_82598EB &&
3336 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3337 return;
3338
3339 /* the hardware may take up to 100us to really disable the rx queue */
3340 do {
3341 udelay(10);
3342 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3343 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3344
3345 if (!wait_loop) {
3346 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3347 "the polling period\n", reg_idx);
3348 }
3349 }
3350
3351 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3352 struct ixgbe_ring *ring)
3353 {
3354 struct ixgbe_hw *hw = &adapter->hw;
3355 u64 rdba = ring->dma;
3356 u32 rxdctl;
3357 u8 reg_idx = ring->reg_idx;
3358
3359 /* disable queue to avoid issues while updating state */
3360 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3361 ixgbe_disable_rx_queue(adapter, ring);
3362
3363 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3364 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3365 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3366 ring->count * sizeof(union ixgbe_adv_rx_desc));
3367 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3368 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3369 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3370
3371 ixgbe_configure_srrctl(adapter, ring);
3372 ixgbe_configure_rscctl(adapter, ring);
3373
3374 if (hw->mac.type == ixgbe_mac_82598EB) {
3375 /*
3376 * enable cache line friendly hardware writes:
3377 * PTHRESH=32 descriptors (half the internal cache),
3378 * this also removes ugly rx_no_buffer_count increment
3379 * HTHRESH=4 descriptors (to minimize latency on fetch)
3380 * WTHRESH=8 burst writeback up to two cache lines
3381 */
3382 rxdctl &= ~0x3FFFFF;
3383 rxdctl |= 0x080420;
3384 }
3385
3386 /* enable receive descriptor ring */
3387 rxdctl |= IXGBE_RXDCTL_ENABLE;
3388 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3389
3390 ixgbe_rx_desc_queue_enable(adapter, ring);
3391 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3392 }
3393
3394 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3395 {
3396 struct ixgbe_hw *hw = &adapter->hw;
3397 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3398 int p;
3399
3400 /* PSRTYPE must be initialized in non 82598 adapters */
3401 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3402 IXGBE_PSRTYPE_UDPHDR |
3403 IXGBE_PSRTYPE_IPV4HDR |
3404 IXGBE_PSRTYPE_L2HDR |
3405 IXGBE_PSRTYPE_IPV6HDR;
3406
3407 if (hw->mac.type == ixgbe_mac_82598EB)
3408 return;
3409
3410 if (rss_i > 3)
3411 psrtype |= 2 << 29;
3412 else if (rss_i > 1)
3413 psrtype |= 1 << 29;
3414
3415 for (p = 0; p < adapter->num_rx_pools; p++)
3416 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
3417 psrtype);
3418 }
3419
3420 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3421 {
3422 struct ixgbe_hw *hw = &adapter->hw;
3423 u32 reg_offset, vf_shift;
3424 u32 gcr_ext, vmdctl;
3425 int i;
3426
3427 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3428 return;
3429
3430 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3431 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3432 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3433 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3434 vmdctl |= IXGBE_VT_CTL_REPLEN;
3435 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3436
3437 vf_shift = VMDQ_P(0) % 32;
3438 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3439
3440 /* Enable only the PF's pool for Tx/Rx */
3441 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3442 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3443 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3444 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3445 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3446 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3447
3448 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3449 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3450
3451 /*
3452 * Set up VF register offsets for selected VT Mode,
3453 * i.e. 32 or 64 VFs for SR-IOV
3454 */
3455 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3456 case IXGBE_82599_VMDQ_8Q_MASK:
3457 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3458 break;
3459 case IXGBE_82599_VMDQ_4Q_MASK:
3460 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3461 break;
3462 default:
3463 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3464 break;
3465 }
3466
3467 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3468
3469
3470 /* Enable MAC Anti-Spoofing */
3471 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3472 adapter->num_vfs);
3473 /* For VFs that have spoof checking turned off */
3474 for (i = 0; i < adapter->num_vfs; i++) {
3475 if (!adapter->vfinfo[i].spoofchk_enabled)
3476 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3477 }
3478 }
3479
3480 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3481 {
3482 struct ixgbe_hw *hw = &adapter->hw;
3483 struct net_device *netdev = adapter->netdev;
3484 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3485 struct ixgbe_ring *rx_ring;
3486 int i;
3487 u32 mhadd, hlreg0;
3488
3489 #ifdef IXGBE_FCOE
3490 /* adjust max frame to be able to do baby jumbo for FCoE */
3491 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3492 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3493 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3494
3495 #endif /* IXGBE_FCOE */
3496
3497 /* adjust max frame to be at least the size of a standard frame */
3498 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3499 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3500
3501 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3502 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3503 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3504 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3505
3506 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3507 }
3508
3509 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3510 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3511 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3512 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3513
3514 /*
3515 * Setup the HW Rx Head and Tail Descriptor Pointers and
3516 * the Base and Length of the Rx Descriptor Ring
3517 */
3518 for (i = 0; i < adapter->num_rx_queues; i++) {
3519 rx_ring = adapter->rx_ring[i];
3520 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3521 set_ring_rsc_enabled(rx_ring);
3522 else
3523 clear_ring_rsc_enabled(rx_ring);
3524 }
3525 }
3526
3527 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3528 {
3529 struct ixgbe_hw *hw = &adapter->hw;
3530 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3531
3532 switch (hw->mac.type) {
3533 case ixgbe_mac_82598EB:
3534 /*
3535 * For VMDq support of different descriptor types or
3536 * buffer sizes through the use of multiple SRRCTL
3537 * registers, RDRXCTL.MVMEN must be set to 1
3538 *
3539 * also, the manual doesn't mention it clearly but DCA hints
3540 * will only use queue 0's tags unless this bit is set. Side
3541 * effects of setting this bit are only that SRRCTL must be
3542 * fully programmed [0..15]
3543 */
3544 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3545 break;
3546 case ixgbe_mac_82599EB:
3547 case ixgbe_mac_X540:
3548 /* Disable RSC for ACK packets */
3549 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3550 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3551 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3552 /* hardware requires some bits to be set by default */
3553 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3554 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3555 break;
3556 default:
3557 /* We should do nothing since we don't know this hardware */
3558 return;
3559 }
3560
3561 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3562 }
3563
3564 /**
3565 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3566 * @adapter: board private structure
3567 *
3568 * Configure the Rx unit of the MAC after a reset.
3569 **/
3570 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3571 {
3572 struct ixgbe_hw *hw = &adapter->hw;
3573 int i;
3574 u32 rxctrl, rfctl;
3575
3576 /* disable receives while setting up the descriptors */
3577 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3578 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3579
3580 ixgbe_setup_psrtype(adapter);
3581 ixgbe_setup_rdrxctl(adapter);
3582
3583 /* RSC Setup */
3584 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3585 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3586 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3587 rfctl |= IXGBE_RFCTL_RSC_DIS;
3588 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3589
3590 /* Program registers for the distribution of queues */
3591 ixgbe_setup_mrqc(adapter);
3592
3593 /* set_rx_buffer_len must be called before ring initialization */
3594 ixgbe_set_rx_buffer_len(adapter);
3595
3596 /*
3597 * Setup the HW Rx Head and Tail Descriptor Pointers and
3598 * the Base and Length of the Rx Descriptor Ring
3599 */
3600 for (i = 0; i < adapter->num_rx_queues; i++)
3601 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3602
3603 /* disable drop enable for 82598 parts */
3604 if (hw->mac.type == ixgbe_mac_82598EB)
3605 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3606
3607 /* enable all receives */
3608 rxctrl |= IXGBE_RXCTRL_RXEN;
3609 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3610 }
3611
3612 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3613 __be16 proto, u16 vid)
3614 {
3615 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3616 struct ixgbe_hw *hw = &adapter->hw;
3617
3618 /* add VID to filter table */
3619 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3620 set_bit(vid, adapter->active_vlans);
3621
3622 return 0;
3623 }
3624
3625 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3626 __be16 proto, u16 vid)
3627 {
3628 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3629 struct ixgbe_hw *hw = &adapter->hw;
3630
3631 /* remove VID from filter table */
3632 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3633 clear_bit(vid, adapter->active_vlans);
3634
3635 return 0;
3636 }
3637
3638 /**
3639 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3640 * @adapter: driver data
3641 */
3642 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3643 {
3644 struct ixgbe_hw *hw = &adapter->hw;
3645 u32 vlnctrl;
3646
3647 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3648 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3649 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3650 }
3651
3652 /**
3653 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3654 * @adapter: driver data
3655 */
3656 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3657 {
3658 struct ixgbe_hw *hw = &adapter->hw;
3659 u32 vlnctrl;
3660
3661 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3662 vlnctrl |= IXGBE_VLNCTRL_VFE;
3663 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3664 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3665 }
3666
3667 /**
3668 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3669 * @adapter: driver data
3670 */
3671 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3672 {
3673 struct ixgbe_hw *hw = &adapter->hw;
3674 u32 vlnctrl;
3675 int i, j;
3676
3677 switch (hw->mac.type) {
3678 case ixgbe_mac_82598EB:
3679 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3680 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3681 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3682 break;
3683 case ixgbe_mac_82599EB:
3684 case ixgbe_mac_X540:
3685 for (i = 0; i < adapter->num_rx_queues; i++) {
3686 j = adapter->rx_ring[i]->reg_idx;
3687 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3688 vlnctrl &= ~IXGBE_RXDCTL_VME;
3689 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3690 }
3691 break;
3692 default:
3693 break;
3694 }
3695 }
3696
3697 /**
3698 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3699 * @adapter: driver data
3700 */
3701 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3702 {
3703 struct ixgbe_hw *hw = &adapter->hw;
3704 u32 vlnctrl;
3705 int i, j;
3706
3707 switch (hw->mac.type) {
3708 case ixgbe_mac_82598EB:
3709 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3710 vlnctrl |= IXGBE_VLNCTRL_VME;
3711 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3712 break;
3713 case ixgbe_mac_82599EB:
3714 case ixgbe_mac_X540:
3715 for (i = 0; i < adapter->num_rx_queues; i++) {
3716 j = adapter->rx_ring[i]->reg_idx;
3717 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3718 vlnctrl |= IXGBE_RXDCTL_VME;
3719 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3720 }
3721 break;
3722 default:
3723 break;
3724 }
3725 }
3726
3727 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3728 {
3729 u16 vid;
3730
3731 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
3732
3733 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3734 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
3735 }
3736
3737 /**
3738 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3739 * @netdev: network interface device structure
3740 *
3741 * Writes unicast address list to the RAR table.
3742 * Returns: -ENOMEM on failure/insufficient address space
3743 * 0 on no addresses written
3744 * X on writing X addresses to the RAR table
3745 **/
3746 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3747 {
3748 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3749 struct ixgbe_hw *hw = &adapter->hw;
3750 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
3751 int count = 0;
3752
3753 /* In SR-IOV mode significantly less RAR entries are available */
3754 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3755 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3756
3757 /* return ENOMEM indicating insufficient memory for addresses */
3758 if (netdev_uc_count(netdev) > rar_entries)
3759 return -ENOMEM;
3760
3761 if (!netdev_uc_empty(netdev)) {
3762 struct netdev_hw_addr *ha;
3763 /* return error if we do not support writing to RAR table */
3764 if (!hw->mac.ops.set_rar)
3765 return -ENOMEM;
3766
3767 netdev_for_each_uc_addr(ha, netdev) {
3768 if (!rar_entries)
3769 break;
3770 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3771 VMDQ_P(0), IXGBE_RAH_AV);
3772 count++;
3773 }
3774 }
3775 /* write the addresses in reverse order to avoid write combining */
3776 for (; rar_entries > 0 ; rar_entries--)
3777 hw->mac.ops.clear_rar(hw, rar_entries);
3778
3779 return count;
3780 }
3781
3782 /**
3783 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3784 * @netdev: network interface device structure
3785 *
3786 * The set_rx_method entry point is called whenever the unicast/multicast
3787 * address list or the network interface flags are updated. This routine is
3788 * responsible for configuring the hardware for proper unicast, multicast and
3789 * promiscuous mode.
3790 **/
3791 void ixgbe_set_rx_mode(struct net_device *netdev)
3792 {
3793 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3794 struct ixgbe_hw *hw = &adapter->hw;
3795 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3796 int count;
3797
3798 /* Check for Promiscuous and All Multicast modes */
3799
3800 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3801
3802 /* set all bits that we expect to always be set */
3803 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3804 fctrl |= IXGBE_FCTRL_BAM;
3805 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3806 fctrl |= IXGBE_FCTRL_PMCF;
3807
3808 /* clear the bits we are changing the status of */
3809 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3810
3811 if (netdev->flags & IFF_PROMISC) {
3812 hw->addr_ctrl.user_set_promisc = true;
3813 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3814 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3815 /* Only disable hardware filter vlans in promiscuous mode
3816 * if SR-IOV and VMDQ are disabled - otherwise ensure
3817 * that hardware VLAN filters remain enabled.
3818 */
3819 if (!(adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
3820 IXGBE_FLAG_SRIOV_ENABLED)))
3821 ixgbe_vlan_filter_disable(adapter);
3822 else
3823 ixgbe_vlan_filter_enable(adapter);
3824 } else {
3825 if (netdev->flags & IFF_ALLMULTI) {
3826 fctrl |= IXGBE_FCTRL_MPE;
3827 vmolr |= IXGBE_VMOLR_MPE;
3828 } else {
3829 /*
3830 * Write addresses to the MTA, if the attempt fails
3831 * then we should just turn on promiscuous mode so
3832 * that we can at least receive multicast traffic
3833 */
3834 hw->mac.ops.update_mc_addr_list(hw, netdev);
3835 vmolr |= IXGBE_VMOLR_ROMPE;
3836 }
3837 ixgbe_vlan_filter_enable(adapter);
3838 hw->addr_ctrl.user_set_promisc = false;
3839 }
3840
3841 /*
3842 * Write addresses to available RAR registers, if there is not
3843 * sufficient space to store all the addresses then enable
3844 * unicast promiscuous mode
3845 */
3846 count = ixgbe_write_uc_addr_list(netdev);
3847 if (count < 0) {
3848 fctrl |= IXGBE_FCTRL_UPE;
3849 vmolr |= IXGBE_VMOLR_ROPE;
3850 }
3851
3852 if (adapter->num_vfs)
3853 ixgbe_restore_vf_multicasts(adapter);
3854
3855 if (hw->mac.type != ixgbe_mac_82598EB) {
3856 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
3857 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3858 IXGBE_VMOLR_ROPE);
3859 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
3860 }
3861
3862 /* This is useful for sniffing bad packets. */
3863 if (adapter->netdev->features & NETIF_F_RXALL) {
3864 /* UPE and MPE will be handled by normal PROMISC logic
3865 * in e1000e_set_rx_mode */
3866 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3867 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3868 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3869
3870 fctrl &= ~(IXGBE_FCTRL_DPF);
3871 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3872 }
3873
3874 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3875
3876 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3877 ixgbe_vlan_strip_enable(adapter);
3878 else
3879 ixgbe_vlan_strip_disable(adapter);
3880 }
3881
3882 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3883 {
3884 int q_idx;
3885
3886 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
3887 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
3888 napi_enable(&adapter->q_vector[q_idx]->napi);
3889 }
3890 }
3891
3892 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3893 {
3894 int q_idx;
3895
3896 local_bh_disable(); /* for ixgbe_qv_lock_napi() */
3897 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
3898 napi_disable(&adapter->q_vector[q_idx]->napi);
3899 while (!ixgbe_qv_lock_napi(adapter->q_vector[q_idx])) {
3900 pr_info("QV %d locked\n", q_idx);
3901 mdelay(1);
3902 }
3903 }
3904 local_bh_enable();
3905 }
3906
3907 #ifdef CONFIG_IXGBE_DCB
3908 /**
3909 * ixgbe_configure_dcb - Configure DCB hardware
3910 * @adapter: ixgbe adapter struct
3911 *
3912 * This is called by the driver on open to configure the DCB hardware.
3913 * This is also called by the gennetlink interface when reconfiguring
3914 * the DCB state.
3915 */
3916 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3917 {
3918 struct ixgbe_hw *hw = &adapter->hw;
3919 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3920
3921 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3922 if (hw->mac.type == ixgbe_mac_82598EB)
3923 netif_set_gso_max_size(adapter->netdev, 65536);
3924 return;
3925 }
3926
3927 if (hw->mac.type == ixgbe_mac_82598EB)
3928 netif_set_gso_max_size(adapter->netdev, 32768);
3929
3930 #ifdef IXGBE_FCOE
3931 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3932 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3933 #endif
3934
3935 /* reconfigure the hardware */
3936 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3937 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3938 DCB_TX_CONFIG);
3939 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3940 DCB_RX_CONFIG);
3941 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3942 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3943 ixgbe_dcb_hw_ets(&adapter->hw,
3944 adapter->ixgbe_ieee_ets,
3945 max_frame);
3946 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3947 adapter->ixgbe_ieee_pfc->pfc_en,
3948 adapter->ixgbe_ieee_ets->prio_tc);
3949 }
3950
3951 /* Enable RSS Hash per TC */
3952 if (hw->mac.type != ixgbe_mac_82598EB) {
3953 u32 msb = 0;
3954 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
3955
3956 while (rss_i) {
3957 msb++;
3958 rss_i >>= 1;
3959 }
3960
3961 /* write msb to all 8 TCs in one write */
3962 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
3963 }
3964 }
3965 #endif
3966
3967 /* Additional bittime to account for IXGBE framing */
3968 #define IXGBE_ETH_FRAMING 20
3969
3970 /**
3971 * ixgbe_hpbthresh - calculate high water mark for flow control
3972 *
3973 * @adapter: board private structure to calculate for
3974 * @pb: packet buffer to calculate
3975 */
3976 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3977 {
3978 struct ixgbe_hw *hw = &adapter->hw;
3979 struct net_device *dev = adapter->netdev;
3980 int link, tc, kb, marker;
3981 u32 dv_id, rx_pba;
3982
3983 /* Calculate max LAN frame size */
3984 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3985
3986 #ifdef IXGBE_FCOE
3987 /* FCoE traffic class uses FCOE jumbo frames */
3988 if ((dev->features & NETIF_F_FCOE_MTU) &&
3989 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3990 (pb == ixgbe_fcoe_get_tc(adapter)))
3991 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3992
3993 #endif
3994 /* Calculate delay value for device */
3995 switch (hw->mac.type) {
3996 case ixgbe_mac_X540:
3997 dv_id = IXGBE_DV_X540(link, tc);
3998 break;
3999 default:
4000 dv_id = IXGBE_DV(link, tc);
4001 break;
4002 }
4003
4004 /* Loopback switch introduces additional latency */
4005 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4006 dv_id += IXGBE_B2BT(tc);
4007
4008 /* Delay value is calculated in bit times convert to KB */
4009 kb = IXGBE_BT2KB(dv_id);
4010 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4011
4012 marker = rx_pba - kb;
4013
4014 /* It is possible that the packet buffer is not large enough
4015 * to provide required headroom. In this case throw an error
4016 * to user and a do the best we can.
4017 */
4018 if (marker < 0) {
4019 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4020 "headroom to support flow control."
4021 "Decrease MTU or number of traffic classes\n", pb);
4022 marker = tc + 1;
4023 }
4024
4025 return marker;
4026 }
4027
4028 /**
4029 * ixgbe_lpbthresh - calculate low water mark for for flow control
4030 *
4031 * @adapter: board private structure to calculate for
4032 * @pb: packet buffer to calculate
4033 */
4034 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
4035 {
4036 struct ixgbe_hw *hw = &adapter->hw;
4037 struct net_device *dev = adapter->netdev;
4038 int tc;
4039 u32 dv_id;
4040
4041 /* Calculate max LAN frame size */
4042 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4043
4044 /* Calculate delay value for device */
4045 switch (hw->mac.type) {
4046 case ixgbe_mac_X540:
4047 dv_id = IXGBE_LOW_DV_X540(tc);
4048 break;
4049 default:
4050 dv_id = IXGBE_LOW_DV(tc);
4051 break;
4052 }
4053
4054 /* Delay value is calculated in bit times convert to KB */
4055 return IXGBE_BT2KB(dv_id);
4056 }
4057
4058 /*
4059 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4060 */
4061 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4062 {
4063 struct ixgbe_hw *hw = &adapter->hw;
4064 int num_tc = netdev_get_num_tc(adapter->netdev);
4065 int i;
4066
4067 if (!num_tc)
4068 num_tc = 1;
4069
4070 hw->fc.low_water = ixgbe_lpbthresh(adapter);
4071
4072 for (i = 0; i < num_tc; i++) {
4073 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4074
4075 /* Low water marks must not be larger than high water marks */
4076 if (hw->fc.low_water > hw->fc.high_water[i])
4077 hw->fc.low_water = 0;
4078 }
4079 }
4080
4081 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4082 {
4083 struct ixgbe_hw *hw = &adapter->hw;
4084 int hdrm;
4085 u8 tc = netdev_get_num_tc(adapter->netdev);
4086
4087 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4088 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4089 hdrm = 32 << adapter->fdir_pballoc;
4090 else
4091 hdrm = 0;
4092
4093 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
4094 ixgbe_pbthresh_setup(adapter);
4095 }
4096
4097 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4098 {
4099 struct ixgbe_hw *hw = &adapter->hw;
4100 struct hlist_node *node2;
4101 struct ixgbe_fdir_filter *filter;
4102
4103 spin_lock(&adapter->fdir_perfect_lock);
4104
4105 if (!hlist_empty(&adapter->fdir_filter_list))
4106 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4107
4108 hlist_for_each_entry_safe(filter, node2,
4109 &adapter->fdir_filter_list, fdir_node) {
4110 ixgbe_fdir_write_perfect_filter_82599(hw,
4111 &filter->filter,
4112 filter->sw_idx,
4113 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4114 IXGBE_FDIR_DROP_QUEUE :
4115 adapter->rx_ring[filter->action]->reg_idx);
4116 }
4117
4118 spin_unlock(&adapter->fdir_perfect_lock);
4119 }
4120
4121 static void ixgbe_configure(struct ixgbe_adapter *adapter)
4122 {
4123 struct ixgbe_hw *hw = &adapter->hw;
4124
4125 ixgbe_configure_pb(adapter);
4126 #ifdef CONFIG_IXGBE_DCB
4127 ixgbe_configure_dcb(adapter);
4128 #endif
4129 /*
4130 * We must restore virtualization before VLANs or else
4131 * the VLVF registers will not be populated
4132 */
4133 ixgbe_configure_virtualization(adapter);
4134
4135 ixgbe_set_rx_mode(adapter->netdev);
4136 ixgbe_restore_vlan(adapter);
4137
4138 switch (hw->mac.type) {
4139 case ixgbe_mac_82599EB:
4140 case ixgbe_mac_X540:
4141 hw->mac.ops.disable_rx_buff(hw);
4142 break;
4143 default:
4144 break;
4145 }
4146
4147 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4148 ixgbe_init_fdir_signature_82599(&adapter->hw,
4149 adapter->fdir_pballoc);
4150 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4151 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4152 adapter->fdir_pballoc);
4153 ixgbe_fdir_filter_restore(adapter);
4154 }
4155
4156 switch (hw->mac.type) {
4157 case ixgbe_mac_82599EB:
4158 case ixgbe_mac_X540:
4159 hw->mac.ops.enable_rx_buff(hw);
4160 break;
4161 default:
4162 break;
4163 }
4164
4165 #ifdef IXGBE_FCOE
4166 /* configure FCoE L2 filters, redirection table, and Rx control */
4167 ixgbe_configure_fcoe(adapter);
4168
4169 #endif /* IXGBE_FCOE */
4170 ixgbe_configure_tx(adapter);
4171 ixgbe_configure_rx(adapter);
4172 }
4173
4174 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4175 {
4176 switch (hw->phy.type) {
4177 case ixgbe_phy_sfp_avago:
4178 case ixgbe_phy_sfp_ftl:
4179 case ixgbe_phy_sfp_intel:
4180 case ixgbe_phy_sfp_unknown:
4181 case ixgbe_phy_sfp_passive_tyco:
4182 case ixgbe_phy_sfp_passive_unknown:
4183 case ixgbe_phy_sfp_active_unknown:
4184 case ixgbe_phy_sfp_ftl_active:
4185 case ixgbe_phy_qsfp_passive_unknown:
4186 case ixgbe_phy_qsfp_active_unknown:
4187 case ixgbe_phy_qsfp_intel:
4188 case ixgbe_phy_qsfp_unknown:
4189 return true;
4190 case ixgbe_phy_nl:
4191 if (hw->mac.type == ixgbe_mac_82598EB)
4192 return true;
4193 default:
4194 return false;
4195 }
4196 }
4197
4198 /**
4199 * ixgbe_sfp_link_config - set up SFP+ link
4200 * @adapter: pointer to private adapter struct
4201 **/
4202 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4203 {
4204 /*
4205 * We are assuming the worst case scenario here, and that
4206 * is that an SFP was inserted/removed after the reset
4207 * but before SFP detection was enabled. As such the best
4208 * solution is to just start searching as soon as we start
4209 */
4210 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4211 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4212
4213 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4214 }
4215
4216 /**
4217 * ixgbe_non_sfp_link_config - set up non-SFP+ link
4218 * @hw: pointer to private hardware struct
4219 *
4220 * Returns 0 on success, negative on failure
4221 **/
4222 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4223 {
4224 u32 speed;
4225 bool autoneg, link_up = false;
4226 u32 ret = IXGBE_ERR_LINK_SETUP;
4227
4228 if (hw->mac.ops.check_link)
4229 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
4230
4231 if (ret)
4232 goto link_cfg_out;
4233
4234 speed = hw->phy.autoneg_advertised;
4235 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4236 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4237 &autoneg);
4238 if (ret)
4239 goto link_cfg_out;
4240
4241 if (hw->mac.ops.setup_link)
4242 ret = hw->mac.ops.setup_link(hw, speed, link_up);
4243 link_cfg_out:
4244 return ret;
4245 }
4246
4247 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4248 {
4249 struct ixgbe_hw *hw = &adapter->hw;
4250 u32 gpie = 0;
4251
4252 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4253 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4254 IXGBE_GPIE_OCD;
4255 gpie |= IXGBE_GPIE_EIAME;
4256 /*
4257 * use EIAM to auto-mask when MSI-X interrupt is asserted
4258 * this saves a register write for every interrupt
4259 */
4260 switch (hw->mac.type) {
4261 case ixgbe_mac_82598EB:
4262 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4263 break;
4264 case ixgbe_mac_82599EB:
4265 case ixgbe_mac_X540:
4266 default:
4267 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4268 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4269 break;
4270 }
4271 } else {
4272 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4273 * specifically only auto mask tx and rx interrupts */
4274 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4275 }
4276
4277 /* XXX: to interrupt immediately for EICS writes, enable this */
4278 /* gpie |= IXGBE_GPIE_EIMEN; */
4279
4280 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4281 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4282
4283 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4284 case IXGBE_82599_VMDQ_8Q_MASK:
4285 gpie |= IXGBE_GPIE_VTMODE_16;
4286 break;
4287 case IXGBE_82599_VMDQ_4Q_MASK:
4288 gpie |= IXGBE_GPIE_VTMODE_32;
4289 break;
4290 default:
4291 gpie |= IXGBE_GPIE_VTMODE_64;
4292 break;
4293 }
4294 }
4295
4296 /* Enable Thermal over heat sensor interrupt */
4297 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4298 switch (adapter->hw.mac.type) {
4299 case ixgbe_mac_82599EB:
4300 gpie |= IXGBE_SDP0_GPIEN;
4301 break;
4302 case ixgbe_mac_X540:
4303 gpie |= IXGBE_EIMS_TS;
4304 break;
4305 default:
4306 break;
4307 }
4308 }
4309
4310 /* Enable fan failure interrupt */
4311 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4312 gpie |= IXGBE_SDP1_GPIEN;
4313
4314 if (hw->mac.type == ixgbe_mac_82599EB) {
4315 gpie |= IXGBE_SDP1_GPIEN;
4316 gpie |= IXGBE_SDP2_GPIEN;
4317 }
4318
4319 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4320 }
4321
4322 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4323 {
4324 struct ixgbe_hw *hw = &adapter->hw;
4325 int err;
4326 u32 ctrl_ext;
4327
4328 ixgbe_get_hw_control(adapter);
4329 ixgbe_setup_gpie(adapter);
4330
4331 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4332 ixgbe_configure_msix(adapter);
4333 else
4334 ixgbe_configure_msi_and_legacy(adapter);
4335
4336 /* enable the optics for 82599 SFP+ fiber */
4337 if (hw->mac.ops.enable_tx_laser)
4338 hw->mac.ops.enable_tx_laser(hw);
4339
4340 clear_bit(__IXGBE_DOWN, &adapter->state);
4341 ixgbe_napi_enable_all(adapter);
4342
4343 if (ixgbe_is_sfp(hw)) {
4344 ixgbe_sfp_link_config(adapter);
4345 } else {
4346 err = ixgbe_non_sfp_link_config(hw);
4347 if (err)
4348 e_err(probe, "link_config FAILED %d\n", err);
4349 }
4350
4351 /* clear any pending interrupts, may auto mask */
4352 IXGBE_READ_REG(hw, IXGBE_EICR);
4353 ixgbe_irq_enable(adapter, true, true);
4354
4355 /*
4356 * If this adapter has a fan, check to see if we had a failure
4357 * before we enabled the interrupt.
4358 */
4359 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4360 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4361 if (esdp & IXGBE_ESDP_SDP1)
4362 e_crit(drv, "Fan has stopped, replace the adapter\n");
4363 }
4364
4365 /* enable transmits */
4366 netif_tx_start_all_queues(adapter->netdev);
4367
4368 /* bring the link up in the watchdog, this could race with our first
4369 * link up interrupt but shouldn't be a problem */
4370 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4371 adapter->link_check_timeout = jiffies;
4372 mod_timer(&adapter->service_timer, jiffies);
4373
4374 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4375 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4376 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4377 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4378 }
4379
4380 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4381 {
4382 WARN_ON(in_interrupt());
4383 /* put off any impending NetWatchDogTimeout */
4384 adapter->netdev->trans_start = jiffies;
4385
4386 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4387 usleep_range(1000, 2000);
4388 ixgbe_down(adapter);
4389 /*
4390 * If SR-IOV enabled then wait a bit before bringing the adapter
4391 * back up to give the VFs time to respond to the reset. The
4392 * two second wait is based upon the watchdog timer cycle in
4393 * the VF driver.
4394 */
4395 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4396 msleep(2000);
4397 ixgbe_up(adapter);
4398 clear_bit(__IXGBE_RESETTING, &adapter->state);
4399 }
4400
4401 void ixgbe_up(struct ixgbe_adapter *adapter)
4402 {
4403 /* hardware has been reset, we need to reload some things */
4404 ixgbe_configure(adapter);
4405
4406 ixgbe_up_complete(adapter);
4407 }
4408
4409 void ixgbe_reset(struct ixgbe_adapter *adapter)
4410 {
4411 struct ixgbe_hw *hw = &adapter->hw;
4412 int err;
4413
4414 /* lock SFP init bit to prevent race conditions with the watchdog */
4415 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4416 usleep_range(1000, 2000);
4417
4418 /* clear all SFP and link config related flags while holding SFP_INIT */
4419 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4420 IXGBE_FLAG2_SFP_NEEDS_RESET);
4421 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4422
4423 err = hw->mac.ops.init_hw(hw);
4424 switch (err) {
4425 case 0:
4426 case IXGBE_ERR_SFP_NOT_PRESENT:
4427 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4428 break;
4429 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4430 e_dev_err("master disable timed out\n");
4431 break;
4432 case IXGBE_ERR_EEPROM_VERSION:
4433 /* We are running on a pre-production device, log a warning */
4434 e_dev_warn("This device is a pre-production adapter/LOM. "
4435 "Please be aware there may be issues associated with "
4436 "your hardware. If you are experiencing problems "
4437 "please contact your Intel or hardware "
4438 "representative who provided you with this "
4439 "hardware.\n");
4440 break;
4441 default:
4442 e_dev_err("Hardware Error: %d\n", err);
4443 }
4444
4445 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4446
4447 /* reprogram the RAR[0] in case user changed it. */
4448 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
4449
4450 /* update SAN MAC vmdq pool selection */
4451 if (hw->mac.san_mac_rar_index)
4452 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4453
4454 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
4455 ixgbe_ptp_reset(adapter);
4456 }
4457
4458 /**
4459 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4460 * @rx_ring: ring to free buffers from
4461 **/
4462 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4463 {
4464 struct device *dev = rx_ring->dev;
4465 unsigned long size;
4466 u16 i;
4467
4468 /* ring already cleared, nothing to do */
4469 if (!rx_ring->rx_buffer_info)
4470 return;
4471
4472 /* Free all the Rx ring sk_buffs */
4473 for (i = 0; i < rx_ring->count; i++) {
4474 struct ixgbe_rx_buffer *rx_buffer;
4475
4476 rx_buffer = &rx_ring->rx_buffer_info[i];
4477 if (rx_buffer->skb) {
4478 struct sk_buff *skb = rx_buffer->skb;
4479 if (IXGBE_CB(skb)->page_released) {
4480 dma_unmap_page(dev,
4481 IXGBE_CB(skb)->dma,
4482 ixgbe_rx_bufsz(rx_ring),
4483 DMA_FROM_DEVICE);
4484 IXGBE_CB(skb)->page_released = false;
4485 }
4486 dev_kfree_skb(skb);
4487 }
4488 rx_buffer->skb = NULL;
4489 if (rx_buffer->dma)
4490 dma_unmap_page(dev, rx_buffer->dma,
4491 ixgbe_rx_pg_size(rx_ring),
4492 DMA_FROM_DEVICE);
4493 rx_buffer->dma = 0;
4494 if (rx_buffer->page)
4495 __free_pages(rx_buffer->page,
4496 ixgbe_rx_pg_order(rx_ring));
4497 rx_buffer->page = NULL;
4498 }
4499
4500 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4501 memset(rx_ring->rx_buffer_info, 0, size);
4502
4503 /* Zero out the descriptor ring */
4504 memset(rx_ring->desc, 0, rx_ring->size);
4505
4506 rx_ring->next_to_alloc = 0;
4507 rx_ring->next_to_clean = 0;
4508 rx_ring->next_to_use = 0;
4509 }
4510
4511 /**
4512 * ixgbe_clean_tx_ring - Free Tx Buffers
4513 * @tx_ring: ring to be cleaned
4514 **/
4515 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4516 {
4517 struct ixgbe_tx_buffer *tx_buffer_info;
4518 unsigned long size;
4519 u16 i;
4520
4521 /* ring already cleared, nothing to do */
4522 if (!tx_ring->tx_buffer_info)
4523 return;
4524
4525 /* Free all the Tx ring sk_buffs */
4526 for (i = 0; i < tx_ring->count; i++) {
4527 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4528 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4529 }
4530
4531 netdev_tx_reset_queue(txring_txq(tx_ring));
4532
4533 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4534 memset(tx_ring->tx_buffer_info, 0, size);
4535
4536 /* Zero out the descriptor ring */
4537 memset(tx_ring->desc, 0, tx_ring->size);
4538
4539 tx_ring->next_to_use = 0;
4540 tx_ring->next_to_clean = 0;
4541 }
4542
4543 /**
4544 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4545 * @adapter: board private structure
4546 **/
4547 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4548 {
4549 int i;
4550
4551 for (i = 0; i < adapter->num_rx_queues; i++)
4552 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4553 }
4554
4555 /**
4556 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4557 * @adapter: board private structure
4558 **/
4559 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4560 {
4561 int i;
4562
4563 for (i = 0; i < adapter->num_tx_queues; i++)
4564 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4565 }
4566
4567 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4568 {
4569 struct hlist_node *node2;
4570 struct ixgbe_fdir_filter *filter;
4571
4572 spin_lock(&adapter->fdir_perfect_lock);
4573
4574 hlist_for_each_entry_safe(filter, node2,
4575 &adapter->fdir_filter_list, fdir_node) {
4576 hlist_del(&filter->fdir_node);
4577 kfree(filter);
4578 }
4579 adapter->fdir_filter_count = 0;
4580
4581 spin_unlock(&adapter->fdir_perfect_lock);
4582 }
4583
4584 void ixgbe_down(struct ixgbe_adapter *adapter)
4585 {
4586 struct net_device *netdev = adapter->netdev;
4587 struct ixgbe_hw *hw = &adapter->hw;
4588 u32 rxctrl;
4589 int i;
4590
4591 /* signal that we are down to the interrupt handler */
4592 set_bit(__IXGBE_DOWN, &adapter->state);
4593
4594 /* disable receives */
4595 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4596 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4597
4598 /* disable all enabled rx queues */
4599 for (i = 0; i < adapter->num_rx_queues; i++)
4600 /* this call also flushes the previous write */
4601 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4602
4603 usleep_range(10000, 20000);
4604
4605 netif_tx_stop_all_queues(netdev);
4606
4607 /* call carrier off first to avoid false dev_watchdog timeouts */
4608 netif_carrier_off(netdev);
4609 netif_tx_disable(netdev);
4610
4611 ixgbe_irq_disable(adapter);
4612
4613 ixgbe_napi_disable_all(adapter);
4614
4615 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4616 IXGBE_FLAG2_RESET_REQUESTED);
4617 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4618
4619 del_timer_sync(&adapter->service_timer);
4620
4621 if (adapter->num_vfs) {
4622 /* Clear EITR Select mapping */
4623 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4624
4625 /* Mark all the VFs as inactive */
4626 for (i = 0 ; i < adapter->num_vfs; i++)
4627 adapter->vfinfo[i].clear_to_send = false;
4628
4629 /* ping all the active vfs to let them know we are going down */
4630 ixgbe_ping_all_vfs(adapter);
4631
4632 /* Disable all VFTE/VFRE TX/RX */
4633 ixgbe_disable_tx_rx(adapter);
4634 }
4635
4636 /* disable transmits in the hardware now that interrupts are off */
4637 for (i = 0; i < adapter->num_tx_queues; i++) {
4638 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4639 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4640 }
4641
4642 /* Disable the Tx DMA engine on 82599 and X540 */
4643 switch (hw->mac.type) {
4644 case ixgbe_mac_82599EB:
4645 case ixgbe_mac_X540:
4646 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4647 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4648 ~IXGBE_DMATXCTL_TE));
4649 break;
4650 default:
4651 break;
4652 }
4653
4654 if (!pci_channel_offline(adapter->pdev))
4655 ixgbe_reset(adapter);
4656
4657 /* power down the optics for 82599 SFP+ fiber */
4658 if (hw->mac.ops.disable_tx_laser)
4659 hw->mac.ops.disable_tx_laser(hw);
4660
4661 ixgbe_clean_all_tx_rings(adapter);
4662 ixgbe_clean_all_rx_rings(adapter);
4663
4664 #ifdef CONFIG_IXGBE_DCA
4665 /* since we reset the hardware DCA settings were cleared */
4666 ixgbe_setup_dca(adapter);
4667 #endif
4668 }
4669
4670 /**
4671 * ixgbe_tx_timeout - Respond to a Tx Hang
4672 * @netdev: network interface device structure
4673 **/
4674 static void ixgbe_tx_timeout(struct net_device *netdev)
4675 {
4676 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4677
4678 /* Do the reset outside of interrupt context */
4679 ixgbe_tx_timeout_reset(adapter);
4680 }
4681
4682 /**
4683 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4684 * @adapter: board private structure to initialize
4685 *
4686 * ixgbe_sw_init initializes the Adapter private data structure.
4687 * Fields are initialized based on PCI device information and
4688 * OS network device settings (MTU size).
4689 **/
4690 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
4691 {
4692 struct ixgbe_hw *hw = &adapter->hw;
4693 struct pci_dev *pdev = adapter->pdev;
4694 unsigned int rss, fdir;
4695 u32 fwsm;
4696 #ifdef CONFIG_IXGBE_DCB
4697 int j;
4698 struct tc_configuration *tc;
4699 #endif
4700
4701 /* PCI config space info */
4702
4703 hw->vendor_id = pdev->vendor;
4704 hw->device_id = pdev->device;
4705 hw->revision_id = pdev->revision;
4706 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4707 hw->subsystem_device_id = pdev->subsystem_device;
4708
4709 /* Set common capability flags and settings */
4710 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4711 adapter->ring_feature[RING_F_RSS].limit = rss;
4712 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4713 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4714 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
4715 adapter->atr_sample_rate = 20;
4716 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
4717 adapter->ring_feature[RING_F_FDIR].limit = fdir;
4718 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4719 #ifdef CONFIG_IXGBE_DCA
4720 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
4721 #endif
4722 #ifdef IXGBE_FCOE
4723 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4724 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4725 #ifdef CONFIG_IXGBE_DCB
4726 /* Default traffic class to use for FCoE */
4727 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4728 #endif /* CONFIG_IXGBE_DCB */
4729 #endif /* IXGBE_FCOE */
4730
4731 /* Set MAC specific capability flags and exceptions */
4732 switch (hw->mac.type) {
4733 case ixgbe_mac_82598EB:
4734 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
4735 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
4736
4737 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4738 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4739
4740 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
4741 adapter->ring_feature[RING_F_FDIR].limit = 0;
4742 adapter->atr_sample_rate = 0;
4743 adapter->fdir_pballoc = 0;
4744 #ifdef IXGBE_FCOE
4745 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
4746 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4747 #ifdef CONFIG_IXGBE_DCB
4748 adapter->fcoe.up = 0;
4749 #endif /* IXGBE_DCB */
4750 #endif /* IXGBE_FCOE */
4751 break;
4752 case ixgbe_mac_82599EB:
4753 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4754 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4755 break;
4756 case ixgbe_mac_X540:
4757 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4758 if (fwsm & IXGBE_FWSM_TS_ENABLED)
4759 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4760 break;
4761 default:
4762 break;
4763 }
4764
4765 #ifdef IXGBE_FCOE
4766 /* FCoE support exists, always init the FCoE lock */
4767 spin_lock_init(&adapter->fcoe.lock);
4768
4769 #endif
4770 /* n-tuple support exists, always init our spinlock */
4771 spin_lock_init(&adapter->fdir_perfect_lock);
4772
4773 #ifdef CONFIG_IXGBE_DCB
4774 switch (hw->mac.type) {
4775 case ixgbe_mac_X540:
4776 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4777 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4778 break;
4779 default:
4780 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4781 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4782 break;
4783 }
4784
4785 /* Configure DCB traffic classes */
4786 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4787 tc = &adapter->dcb_cfg.tc_config[j];
4788 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4789 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4790 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4791 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4792 tc->dcb_pfc = pfc_disabled;
4793 }
4794
4795 /* Initialize default user to priority mapping, UPx->TC0 */
4796 tc = &adapter->dcb_cfg.tc_config[0];
4797 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4798 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4799
4800 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4801 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4802 adapter->dcb_cfg.pfc_mode_enable = false;
4803 adapter->dcb_set_bitmap = 0x00;
4804 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4805 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4806 sizeof(adapter->temp_dcb_cfg));
4807
4808 #endif
4809
4810 /* default flow control settings */
4811 hw->fc.requested_mode = ixgbe_fc_full;
4812 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4813 ixgbe_pbthresh_setup(adapter);
4814 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4815 hw->fc.send_xon = true;
4816 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
4817
4818 #ifdef CONFIG_PCI_IOV
4819 /* assign number of SR-IOV VFs */
4820 if (hw->mac.type != ixgbe_mac_82598EB)
4821 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4822
4823 #endif
4824 /* enable itr by default in dynamic mode */
4825 adapter->rx_itr_setting = 1;
4826 adapter->tx_itr_setting = 1;
4827
4828 /* set default ring sizes */
4829 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4830 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4831
4832 /* set default work limits */
4833 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4834
4835 /* initialize eeprom parameters */
4836 if (ixgbe_init_eeprom_params_generic(hw)) {
4837 e_dev_err("EEPROM initialization failed\n");
4838 return -EIO;
4839 }
4840
4841 set_bit(__IXGBE_DOWN, &adapter->state);
4842
4843 return 0;
4844 }
4845
4846 /**
4847 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4848 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4849 *
4850 * Return 0 on success, negative on failure
4851 **/
4852 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4853 {
4854 struct device *dev = tx_ring->dev;
4855 int orig_node = dev_to_node(dev);
4856 int numa_node = -1;
4857 int size;
4858
4859 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4860
4861 if (tx_ring->q_vector)
4862 numa_node = tx_ring->q_vector->numa_node;
4863
4864 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4865 if (!tx_ring->tx_buffer_info)
4866 tx_ring->tx_buffer_info = vzalloc(size);
4867 if (!tx_ring->tx_buffer_info)
4868 goto err;
4869
4870 u64_stats_init(&tx_ring->syncp);
4871
4872 /* round up to nearest 4K */
4873 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4874 tx_ring->size = ALIGN(tx_ring->size, 4096);
4875
4876 set_dev_node(dev, numa_node);
4877 tx_ring->desc = dma_alloc_coherent(dev,
4878 tx_ring->size,
4879 &tx_ring->dma,
4880 GFP_KERNEL);
4881 set_dev_node(dev, orig_node);
4882 if (!tx_ring->desc)
4883 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4884 &tx_ring->dma, GFP_KERNEL);
4885 if (!tx_ring->desc)
4886 goto err;
4887
4888 tx_ring->next_to_use = 0;
4889 tx_ring->next_to_clean = 0;
4890 return 0;
4891
4892 err:
4893 vfree(tx_ring->tx_buffer_info);
4894 tx_ring->tx_buffer_info = NULL;
4895 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4896 return -ENOMEM;
4897 }
4898
4899 /**
4900 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4901 * @adapter: board private structure
4902 *
4903 * If this function returns with an error, then it's possible one or
4904 * more of the rings is populated (while the rest are not). It is the
4905 * callers duty to clean those orphaned rings.
4906 *
4907 * Return 0 on success, negative on failure
4908 **/
4909 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4910 {
4911 int i, err = 0;
4912
4913 for (i = 0; i < adapter->num_tx_queues; i++) {
4914 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4915 if (!err)
4916 continue;
4917
4918 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4919 goto err_setup_tx;
4920 }
4921
4922 return 0;
4923 err_setup_tx:
4924 /* rewind the index freeing the rings as we go */
4925 while (i--)
4926 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4927 return err;
4928 }
4929
4930 /**
4931 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4932 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4933 *
4934 * Returns 0 on success, negative on failure
4935 **/
4936 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4937 {
4938 struct device *dev = rx_ring->dev;
4939 int orig_node = dev_to_node(dev);
4940 int numa_node = -1;
4941 int size;
4942
4943 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4944
4945 if (rx_ring->q_vector)
4946 numa_node = rx_ring->q_vector->numa_node;
4947
4948 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4949 if (!rx_ring->rx_buffer_info)
4950 rx_ring->rx_buffer_info = vzalloc(size);
4951 if (!rx_ring->rx_buffer_info)
4952 goto err;
4953
4954 u64_stats_init(&rx_ring->syncp);
4955
4956 /* Round up to nearest 4K */
4957 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4958 rx_ring->size = ALIGN(rx_ring->size, 4096);
4959
4960 set_dev_node(dev, numa_node);
4961 rx_ring->desc = dma_alloc_coherent(dev,
4962 rx_ring->size,
4963 &rx_ring->dma,
4964 GFP_KERNEL);
4965 set_dev_node(dev, orig_node);
4966 if (!rx_ring->desc)
4967 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4968 &rx_ring->dma, GFP_KERNEL);
4969 if (!rx_ring->desc)
4970 goto err;
4971
4972 rx_ring->next_to_clean = 0;
4973 rx_ring->next_to_use = 0;
4974
4975 return 0;
4976 err:
4977 vfree(rx_ring->rx_buffer_info);
4978 rx_ring->rx_buffer_info = NULL;
4979 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4980 return -ENOMEM;
4981 }
4982
4983 /**
4984 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4985 * @adapter: board private structure
4986 *
4987 * If this function returns with an error, then it's possible one or
4988 * more of the rings is populated (while the rest are not). It is the
4989 * callers duty to clean those orphaned rings.
4990 *
4991 * Return 0 on success, negative on failure
4992 **/
4993 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4994 {
4995 int i, err = 0;
4996
4997 for (i = 0; i < adapter->num_rx_queues; i++) {
4998 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4999 if (!err)
5000 continue;
5001
5002 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5003 goto err_setup_rx;
5004 }
5005
5006 #ifdef IXGBE_FCOE
5007 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5008 if (!err)
5009 #endif
5010 return 0;
5011 err_setup_rx:
5012 /* rewind the index freeing the rings as we go */
5013 while (i--)
5014 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5015 return err;
5016 }
5017
5018 /**
5019 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5020 * @tx_ring: Tx descriptor ring for a specific queue
5021 *
5022 * Free all transmit software resources
5023 **/
5024 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5025 {
5026 ixgbe_clean_tx_ring(tx_ring);
5027
5028 vfree(tx_ring->tx_buffer_info);
5029 tx_ring->tx_buffer_info = NULL;
5030
5031 /* if not set, then don't free */
5032 if (!tx_ring->desc)
5033 return;
5034
5035 dma_free_coherent(tx_ring->dev, tx_ring->size,
5036 tx_ring->desc, tx_ring->dma);
5037
5038 tx_ring->desc = NULL;
5039 }
5040
5041 /**
5042 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5043 * @adapter: board private structure
5044 *
5045 * Free all transmit software resources
5046 **/
5047 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5048 {
5049 int i;
5050
5051 for (i = 0; i < adapter->num_tx_queues; i++)
5052 if (adapter->tx_ring[i]->desc)
5053 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5054 }
5055
5056 /**
5057 * ixgbe_free_rx_resources - Free Rx Resources
5058 * @rx_ring: ring to clean the resources from
5059 *
5060 * Free all receive software resources
5061 **/
5062 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5063 {
5064 ixgbe_clean_rx_ring(rx_ring);
5065
5066 vfree(rx_ring->rx_buffer_info);
5067 rx_ring->rx_buffer_info = NULL;
5068
5069 /* if not set, then don't free */
5070 if (!rx_ring->desc)
5071 return;
5072
5073 dma_free_coherent(rx_ring->dev, rx_ring->size,
5074 rx_ring->desc, rx_ring->dma);
5075
5076 rx_ring->desc = NULL;
5077 }
5078
5079 /**
5080 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5081 * @adapter: board private structure
5082 *
5083 * Free all receive software resources
5084 **/
5085 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5086 {
5087 int i;
5088
5089 #ifdef IXGBE_FCOE
5090 ixgbe_free_fcoe_ddp_resources(adapter);
5091
5092 #endif
5093 for (i = 0; i < adapter->num_rx_queues; i++)
5094 if (adapter->rx_ring[i]->desc)
5095 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5096 }
5097
5098 /**
5099 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5100 * @netdev: network interface device structure
5101 * @new_mtu: new value for maximum frame size
5102 *
5103 * Returns 0 on success, negative on failure
5104 **/
5105 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5106 {
5107 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5108 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5109
5110 /* MTU < 68 is an error and causes problems on some kernels */
5111 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5112 return -EINVAL;
5113
5114 /*
5115 * For 82599EB we cannot allow legacy VFs to enable their receive
5116 * paths when MTU greater than 1500 is configured. So display a
5117 * warning that legacy VFs will be disabled.
5118 */
5119 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5120 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
5121 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
5122 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
5123
5124 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5125
5126 /* must set new MTU before calling down or up */
5127 netdev->mtu = new_mtu;
5128
5129 if (netif_running(netdev))
5130 ixgbe_reinit_locked(adapter);
5131
5132 return 0;
5133 }
5134
5135 /**
5136 * ixgbe_open - Called when a network interface is made active
5137 * @netdev: network interface device structure
5138 *
5139 * Returns 0 on success, negative value on failure
5140 *
5141 * The open entry point is called when a network interface is made
5142 * active by the system (IFF_UP). At this point all resources needed
5143 * for transmit and receive operations are allocated, the interrupt
5144 * handler is registered with the OS, the watchdog timer is started,
5145 * and the stack is notified that the interface is ready.
5146 **/
5147 static int ixgbe_open(struct net_device *netdev)
5148 {
5149 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5150 int err;
5151
5152 /* disallow open during test */
5153 if (test_bit(__IXGBE_TESTING, &adapter->state))
5154 return -EBUSY;
5155
5156 netif_carrier_off(netdev);
5157
5158 /* allocate transmit descriptors */
5159 err = ixgbe_setup_all_tx_resources(adapter);
5160 if (err)
5161 goto err_setup_tx;
5162
5163 /* allocate receive descriptors */
5164 err = ixgbe_setup_all_rx_resources(adapter);
5165 if (err)
5166 goto err_setup_rx;
5167
5168 ixgbe_configure(adapter);
5169
5170 err = ixgbe_request_irq(adapter);
5171 if (err)
5172 goto err_req_irq;
5173
5174 /* Notify the stack of the actual queue counts. */
5175 err = netif_set_real_num_tx_queues(netdev,
5176 adapter->num_rx_pools > 1 ? 1 :
5177 adapter->num_tx_queues);
5178 if (err)
5179 goto err_set_queues;
5180
5181
5182 err = netif_set_real_num_rx_queues(netdev,
5183 adapter->num_rx_pools > 1 ? 1 :
5184 adapter->num_rx_queues);
5185 if (err)
5186 goto err_set_queues;
5187
5188 ixgbe_ptp_init(adapter);
5189
5190 ixgbe_up_complete(adapter);
5191
5192 return 0;
5193
5194 err_set_queues:
5195 ixgbe_free_irq(adapter);
5196 err_req_irq:
5197 ixgbe_free_all_rx_resources(adapter);
5198 err_setup_rx:
5199 ixgbe_free_all_tx_resources(adapter);
5200 err_setup_tx:
5201 ixgbe_reset(adapter);
5202
5203 return err;
5204 }
5205
5206 /**
5207 * ixgbe_close - Disables a network interface
5208 * @netdev: network interface device structure
5209 *
5210 * Returns 0, this is not allowed to fail
5211 *
5212 * The close entry point is called when an interface is de-activated
5213 * by the OS. The hardware is still under the drivers control, but
5214 * needs to be disabled. A global MAC reset is issued to stop the
5215 * hardware, and all transmit and receive resources are freed.
5216 **/
5217 static int ixgbe_close(struct net_device *netdev)
5218 {
5219 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5220
5221 ixgbe_ptp_stop(adapter);
5222
5223 ixgbe_down(adapter);
5224 ixgbe_free_irq(adapter);
5225
5226 ixgbe_fdir_filter_exit(adapter);
5227
5228 ixgbe_free_all_tx_resources(adapter);
5229 ixgbe_free_all_rx_resources(adapter);
5230
5231 ixgbe_release_hw_control(adapter);
5232
5233 return 0;
5234 }
5235
5236 #ifdef CONFIG_PM
5237 static int ixgbe_resume(struct pci_dev *pdev)
5238 {
5239 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5240 struct net_device *netdev = adapter->netdev;
5241 u32 err;
5242
5243 pci_set_power_state(pdev, PCI_D0);
5244 pci_restore_state(pdev);
5245 /*
5246 * pci_restore_state clears dev->state_saved so call
5247 * pci_save_state to restore it.
5248 */
5249 pci_save_state(pdev);
5250
5251 err = pci_enable_device_mem(pdev);
5252 if (err) {
5253 e_dev_err("Cannot enable PCI device from suspend\n");
5254 return err;
5255 }
5256 pci_set_master(pdev);
5257
5258 pci_wake_from_d3(pdev, false);
5259
5260 ixgbe_reset(adapter);
5261
5262 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5263
5264 rtnl_lock();
5265 err = ixgbe_init_interrupt_scheme(adapter);
5266 if (!err && netif_running(netdev))
5267 err = ixgbe_open(netdev);
5268
5269 rtnl_unlock();
5270
5271 if (err)
5272 return err;
5273
5274 netif_device_attach(netdev);
5275
5276 return 0;
5277 }
5278 #endif /* CONFIG_PM */
5279
5280 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5281 {
5282 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5283 struct net_device *netdev = adapter->netdev;
5284 struct ixgbe_hw *hw = &adapter->hw;
5285 u32 ctrl, fctrl;
5286 u32 wufc = adapter->wol;
5287 #ifdef CONFIG_PM
5288 int retval = 0;
5289 #endif
5290
5291 netif_device_detach(netdev);
5292
5293 rtnl_lock();
5294 if (netif_running(netdev)) {
5295 ixgbe_down(adapter);
5296 ixgbe_free_irq(adapter);
5297 ixgbe_free_all_tx_resources(adapter);
5298 ixgbe_free_all_rx_resources(adapter);
5299 }
5300 rtnl_unlock();
5301
5302 ixgbe_clear_interrupt_scheme(adapter);
5303
5304 #ifdef CONFIG_PM
5305 retval = pci_save_state(pdev);
5306 if (retval)
5307 return retval;
5308
5309 #endif
5310 if (hw->mac.ops.stop_link_on_d3)
5311 hw->mac.ops.stop_link_on_d3(hw);
5312
5313 if (wufc) {
5314 ixgbe_set_rx_mode(netdev);
5315
5316 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5317 if (hw->mac.ops.enable_tx_laser)
5318 hw->mac.ops.enable_tx_laser(hw);
5319
5320 /* turn on all-multi mode if wake on multicast is enabled */
5321 if (wufc & IXGBE_WUFC_MC) {
5322 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5323 fctrl |= IXGBE_FCTRL_MPE;
5324 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5325 }
5326
5327 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5328 ctrl |= IXGBE_CTRL_GIO_DIS;
5329 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5330
5331 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5332 } else {
5333 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5334 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5335 }
5336
5337 switch (hw->mac.type) {
5338 case ixgbe_mac_82598EB:
5339 pci_wake_from_d3(pdev, false);
5340 break;
5341 case ixgbe_mac_82599EB:
5342 case ixgbe_mac_X540:
5343 pci_wake_from_d3(pdev, !!wufc);
5344 break;
5345 default:
5346 break;
5347 }
5348
5349 *enable_wake = !!wufc;
5350
5351 ixgbe_release_hw_control(adapter);
5352
5353 pci_disable_device(pdev);
5354
5355 return 0;
5356 }
5357
5358 #ifdef CONFIG_PM
5359 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5360 {
5361 int retval;
5362 bool wake;
5363
5364 retval = __ixgbe_shutdown(pdev, &wake);
5365 if (retval)
5366 return retval;
5367
5368 if (wake) {
5369 pci_prepare_to_sleep(pdev);
5370 } else {
5371 pci_wake_from_d3(pdev, false);
5372 pci_set_power_state(pdev, PCI_D3hot);
5373 }
5374
5375 return 0;
5376 }
5377 #endif /* CONFIG_PM */
5378
5379 static void ixgbe_shutdown(struct pci_dev *pdev)
5380 {
5381 bool wake;
5382
5383 __ixgbe_shutdown(pdev, &wake);
5384
5385 if (system_state == SYSTEM_POWER_OFF) {
5386 pci_wake_from_d3(pdev, wake);
5387 pci_set_power_state(pdev, PCI_D3hot);
5388 }
5389 }
5390
5391 /**
5392 * ixgbe_update_stats - Update the board statistics counters.
5393 * @adapter: board private structure
5394 **/
5395 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5396 {
5397 struct net_device *netdev = adapter->netdev;
5398 struct ixgbe_hw *hw = &adapter->hw;
5399 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5400 u64 total_mpc = 0;
5401 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5402 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5403 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5404 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5405
5406 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5407 test_bit(__IXGBE_RESETTING, &adapter->state))
5408 return;
5409
5410 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5411 u64 rsc_count = 0;
5412 u64 rsc_flush = 0;
5413 for (i = 0; i < adapter->num_rx_queues; i++) {
5414 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5415 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5416 }
5417 adapter->rsc_total_count = rsc_count;
5418 adapter->rsc_total_flush = rsc_flush;
5419 }
5420
5421 for (i = 0; i < adapter->num_rx_queues; i++) {
5422 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5423 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5424 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5425 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5426 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5427 bytes += rx_ring->stats.bytes;
5428 packets += rx_ring->stats.packets;
5429 }
5430 adapter->non_eop_descs = non_eop_descs;
5431 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5432 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5433 adapter->hw_csum_rx_error = hw_csum_rx_error;
5434 netdev->stats.rx_bytes = bytes;
5435 netdev->stats.rx_packets = packets;
5436
5437 bytes = 0;
5438 packets = 0;
5439 /* gather some stats to the adapter struct that are per queue */
5440 for (i = 0; i < adapter->num_tx_queues; i++) {
5441 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5442 restart_queue += tx_ring->tx_stats.restart_queue;
5443 tx_busy += tx_ring->tx_stats.tx_busy;
5444 bytes += tx_ring->stats.bytes;
5445 packets += tx_ring->stats.packets;
5446 }
5447 adapter->restart_queue = restart_queue;
5448 adapter->tx_busy = tx_busy;
5449 netdev->stats.tx_bytes = bytes;
5450 netdev->stats.tx_packets = packets;
5451
5452 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5453
5454 /* 8 register reads */
5455 for (i = 0; i < 8; i++) {
5456 /* for packet buffers not used, the register should read 0 */
5457 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5458 missed_rx += mpc;
5459 hwstats->mpc[i] += mpc;
5460 total_mpc += hwstats->mpc[i];
5461 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5462 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5463 switch (hw->mac.type) {
5464 case ixgbe_mac_82598EB:
5465 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5466 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5467 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5468 hwstats->pxonrxc[i] +=
5469 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5470 break;
5471 case ixgbe_mac_82599EB:
5472 case ixgbe_mac_X540:
5473 hwstats->pxonrxc[i] +=
5474 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5475 break;
5476 default:
5477 break;
5478 }
5479 }
5480
5481 /*16 register reads */
5482 for (i = 0; i < 16; i++) {
5483 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5484 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5485 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5486 (hw->mac.type == ixgbe_mac_X540)) {
5487 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5488 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5489 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5490 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5491 }
5492 }
5493
5494 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5495 /* work around hardware counting issue */
5496 hwstats->gprc -= missed_rx;
5497
5498 ixgbe_update_xoff_received(adapter);
5499
5500 /* 82598 hardware only has a 32 bit counter in the high register */
5501 switch (hw->mac.type) {
5502 case ixgbe_mac_82598EB:
5503 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5504 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5505 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5506 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5507 break;
5508 case ixgbe_mac_X540:
5509 /* OS2BMC stats are X540 only*/
5510 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5511 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5512 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5513 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5514 case ixgbe_mac_82599EB:
5515 for (i = 0; i < 16; i++)
5516 adapter->hw_rx_no_dma_resources +=
5517 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5518 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5519 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5520 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5521 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5522 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5523 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5524 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5525 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5526 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5527 #ifdef IXGBE_FCOE
5528 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5529 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5530 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5531 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5532 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5533 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5534 /* Add up per cpu counters for total ddp aloc fail */
5535 if (adapter->fcoe.ddp_pool) {
5536 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5537 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5538 unsigned int cpu;
5539 u64 noddp = 0, noddp_ext_buff = 0;
5540 for_each_possible_cpu(cpu) {
5541 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5542 noddp += ddp_pool->noddp;
5543 noddp_ext_buff += ddp_pool->noddp_ext_buff;
5544 }
5545 hwstats->fcoe_noddp = noddp;
5546 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
5547 }
5548 #endif /* IXGBE_FCOE */
5549 break;
5550 default:
5551 break;
5552 }
5553 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5554 hwstats->bprc += bprc;
5555 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5556 if (hw->mac.type == ixgbe_mac_82598EB)
5557 hwstats->mprc -= bprc;
5558 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5559 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5560 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5561 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5562 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5563 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5564 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5565 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5566 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5567 hwstats->lxontxc += lxon;
5568 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5569 hwstats->lxofftxc += lxoff;
5570 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5571 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5572 /*
5573 * 82598 errata - tx of flow control packets is included in tx counters
5574 */
5575 xon_off_tot = lxon + lxoff;
5576 hwstats->gptc -= xon_off_tot;
5577 hwstats->mptc -= xon_off_tot;
5578 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5579 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5580 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5581 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5582 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5583 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5584 hwstats->ptc64 -= xon_off_tot;
5585 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5586 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5587 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5588 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5589 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5590 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5591
5592 /* Fill out the OS statistics structure */
5593 netdev->stats.multicast = hwstats->mprc;
5594
5595 /* Rx Errors */
5596 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5597 netdev->stats.rx_dropped = 0;
5598 netdev->stats.rx_length_errors = hwstats->rlec;
5599 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5600 netdev->stats.rx_missed_errors = total_mpc;
5601 }
5602
5603 /**
5604 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5605 * @adapter: pointer to the device adapter structure
5606 **/
5607 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5608 {
5609 struct ixgbe_hw *hw = &adapter->hw;
5610 int i;
5611
5612 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5613 return;
5614
5615 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5616
5617 /* if interface is down do nothing */
5618 if (test_bit(__IXGBE_DOWN, &adapter->state))
5619 return;
5620
5621 /* do nothing if we are not using signature filters */
5622 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5623 return;
5624
5625 adapter->fdir_overflow++;
5626
5627 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5628 for (i = 0; i < adapter->num_tx_queues; i++)
5629 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5630 &(adapter->tx_ring[i]->state));
5631 /* re-enable flow director interrupts */
5632 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5633 } else {
5634 e_err(probe, "failed to finish FDIR re-initialization, "
5635 "ignored adding FDIR ATR filters\n");
5636 }
5637 }
5638
5639 /**
5640 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5641 * @adapter: pointer to the device adapter structure
5642 *
5643 * This function serves two purposes. First it strobes the interrupt lines
5644 * in order to make certain interrupts are occurring. Secondly it sets the
5645 * bits needed to check for TX hangs. As a result we should immediately
5646 * determine if a hang has occurred.
5647 */
5648 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5649 {
5650 struct ixgbe_hw *hw = &adapter->hw;
5651 u64 eics = 0;
5652 int i;
5653
5654 /* If we're down or resetting, just bail */
5655 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5656 test_bit(__IXGBE_RESETTING, &adapter->state))
5657 return;
5658
5659 /* Force detection of hung controller */
5660 if (netif_carrier_ok(adapter->netdev)) {
5661 for (i = 0; i < adapter->num_tx_queues; i++)
5662 set_check_for_tx_hang(adapter->tx_ring[i]);
5663 }
5664
5665 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5666 /*
5667 * for legacy and MSI interrupts don't set any bits
5668 * that are enabled for EIAM, because this operation
5669 * would set *both* EIMS and EICS for any bit in EIAM
5670 */
5671 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5672 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5673 } else {
5674 /* get one bit for every active tx/rx interrupt vector */
5675 for (i = 0; i < adapter->num_q_vectors; i++) {
5676 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5677 if (qv->rx.ring || qv->tx.ring)
5678 eics |= ((u64)1 << i);
5679 }
5680 }
5681
5682 /* Cause software interrupt to ensure rings are cleaned */
5683 ixgbe_irq_rearm_queues(adapter, eics);
5684
5685 }
5686
5687 /**
5688 * ixgbe_watchdog_update_link - update the link status
5689 * @adapter: pointer to the device adapter structure
5690 * @link_speed: pointer to a u32 to store the link_speed
5691 **/
5692 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5693 {
5694 struct ixgbe_hw *hw = &adapter->hw;
5695 u32 link_speed = adapter->link_speed;
5696 bool link_up = adapter->link_up;
5697 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
5698
5699 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5700 return;
5701
5702 if (hw->mac.ops.check_link) {
5703 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5704 } else {
5705 /* always assume link is up, if no check link function */
5706 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5707 link_up = true;
5708 }
5709
5710 if (adapter->ixgbe_ieee_pfc)
5711 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5712
5713 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
5714 hw->mac.ops.fc_enable(hw);
5715 ixgbe_set_rx_drop_en(adapter);
5716 }
5717
5718 if (link_up ||
5719 time_after(jiffies, (adapter->link_check_timeout +
5720 IXGBE_TRY_LINK_TIMEOUT))) {
5721 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5722 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5723 IXGBE_WRITE_FLUSH(hw);
5724 }
5725
5726 adapter->link_up = link_up;
5727 adapter->link_speed = link_speed;
5728 }
5729
5730 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5731 {
5732 #ifdef CONFIG_IXGBE_DCB
5733 struct net_device *netdev = adapter->netdev;
5734 struct dcb_app app = {
5735 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5736 .protocol = 0,
5737 };
5738 u8 up = 0;
5739
5740 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5741 up = dcb_ieee_getapp_mask(netdev, &app);
5742
5743 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5744 #endif
5745 }
5746
5747 /**
5748 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5749 * print link up message
5750 * @adapter: pointer to the device adapter structure
5751 **/
5752 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5753 {
5754 struct net_device *netdev = adapter->netdev;
5755 struct ixgbe_hw *hw = &adapter->hw;
5756 u32 link_speed = adapter->link_speed;
5757 bool flow_rx, flow_tx;
5758
5759 /* only continue if link was previously down */
5760 if (netif_carrier_ok(netdev))
5761 return;
5762
5763 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5764
5765 switch (hw->mac.type) {
5766 case ixgbe_mac_82598EB: {
5767 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5768 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5769 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5770 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5771 }
5772 break;
5773 case ixgbe_mac_X540:
5774 case ixgbe_mac_82599EB: {
5775 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5776 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5777 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5778 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5779 }
5780 break;
5781 default:
5782 flow_tx = false;
5783 flow_rx = false;
5784 break;
5785 }
5786
5787 adapter->last_rx_ptp_check = jiffies;
5788
5789 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
5790 ixgbe_ptp_start_cyclecounter(adapter);
5791
5792 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5793 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5794 "10 Gbps" :
5795 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5796 "1 Gbps" :
5797 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5798 "100 Mbps" :
5799 "unknown speed"))),
5800 ((flow_rx && flow_tx) ? "RX/TX" :
5801 (flow_rx ? "RX" :
5802 (flow_tx ? "TX" : "None"))));
5803
5804 netif_carrier_on(netdev);
5805 ixgbe_check_vf_rate_limit(adapter);
5806
5807 /* update the default user priority for VFs */
5808 ixgbe_update_default_up(adapter);
5809
5810 /* ping all the active vfs to let them know link has changed */
5811 ixgbe_ping_all_vfs(adapter);
5812 }
5813
5814 /**
5815 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5816 * print link down message
5817 * @adapter: pointer to the adapter structure
5818 **/
5819 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5820 {
5821 struct net_device *netdev = adapter->netdev;
5822 struct ixgbe_hw *hw = &adapter->hw;
5823
5824 adapter->link_up = false;
5825 adapter->link_speed = 0;
5826
5827 /* only continue if link was up previously */
5828 if (!netif_carrier_ok(netdev))
5829 return;
5830
5831 /* poll for SFP+ cable when link is down */
5832 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5833 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5834
5835 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
5836 ixgbe_ptp_start_cyclecounter(adapter);
5837
5838 e_info(drv, "NIC Link is Down\n");
5839 netif_carrier_off(netdev);
5840
5841 /* ping all the active vfs to let them know link has changed */
5842 ixgbe_ping_all_vfs(adapter);
5843 }
5844
5845 /**
5846 * ixgbe_watchdog_flush_tx - flush queues on link down
5847 * @adapter: pointer to the device adapter structure
5848 **/
5849 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5850 {
5851 int i;
5852 int some_tx_pending = 0;
5853
5854 if (!netif_carrier_ok(adapter->netdev)) {
5855 for (i = 0; i < adapter->num_tx_queues; i++) {
5856 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5857 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5858 some_tx_pending = 1;
5859 break;
5860 }
5861 }
5862
5863 if (some_tx_pending) {
5864 /* We've lost link, so the controller stops DMA,
5865 * but we've got queued Tx work that's never going
5866 * to get done, so reset controller to flush Tx.
5867 * (Do the reset outside of interrupt context).
5868 */
5869 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
5870 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5871 }
5872 }
5873 }
5874
5875 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5876 {
5877 u32 ssvpc;
5878
5879 /* Do not perform spoof check for 82598 or if not in IOV mode */
5880 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5881 adapter->num_vfs == 0)
5882 return;
5883
5884 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5885
5886 /*
5887 * ssvpc register is cleared on read, if zero then no
5888 * spoofed packets in the last interval.
5889 */
5890 if (!ssvpc)
5891 return;
5892
5893 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
5894 }
5895
5896 /**
5897 * ixgbe_watchdog_subtask - check and bring link up
5898 * @adapter: pointer to the device adapter structure
5899 **/
5900 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5901 {
5902 /* if interface is down do nothing */
5903 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5904 test_bit(__IXGBE_RESETTING, &adapter->state))
5905 return;
5906
5907 ixgbe_watchdog_update_link(adapter);
5908
5909 if (adapter->link_up)
5910 ixgbe_watchdog_link_is_up(adapter);
5911 else
5912 ixgbe_watchdog_link_is_down(adapter);
5913
5914 ixgbe_spoof_check(adapter);
5915 ixgbe_update_stats(adapter);
5916
5917 ixgbe_watchdog_flush_tx(adapter);
5918 }
5919
5920 /**
5921 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5922 * @adapter: the ixgbe adapter structure
5923 **/
5924 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5925 {
5926 struct ixgbe_hw *hw = &adapter->hw;
5927 s32 err;
5928
5929 /* not searching for SFP so there is nothing to do here */
5930 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5931 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5932 return;
5933
5934 /* someone else is in init, wait until next service event */
5935 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5936 return;
5937
5938 err = hw->phy.ops.identify_sfp(hw);
5939 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5940 goto sfp_out;
5941
5942 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5943 /* If no cable is present, then we need to reset
5944 * the next time we find a good cable. */
5945 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5946 }
5947
5948 /* exit on error */
5949 if (err)
5950 goto sfp_out;
5951
5952 /* exit if reset not needed */
5953 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5954 goto sfp_out;
5955
5956 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5957
5958 /*
5959 * A module may be identified correctly, but the EEPROM may not have
5960 * support for that module. setup_sfp() will fail in that case, so
5961 * we should not allow that module to load.
5962 */
5963 if (hw->mac.type == ixgbe_mac_82598EB)
5964 err = hw->phy.ops.reset(hw);
5965 else
5966 err = hw->mac.ops.setup_sfp(hw);
5967
5968 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5969 goto sfp_out;
5970
5971 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5972 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5973
5974 sfp_out:
5975 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5976
5977 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5978 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5979 e_dev_err("failed to initialize because an unsupported "
5980 "SFP+ module type was detected.\n");
5981 e_dev_err("Reload the driver after installing a "
5982 "supported module.\n");
5983 unregister_netdev(adapter->netdev);
5984 }
5985 }
5986
5987 /**
5988 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5989 * @adapter: the ixgbe adapter structure
5990 **/
5991 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5992 {
5993 struct ixgbe_hw *hw = &adapter->hw;
5994 u32 speed;
5995 bool autoneg = false;
5996
5997 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5998 return;
5999
6000 /* someone else is in init, wait until next service event */
6001 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6002 return;
6003
6004 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6005
6006 speed = hw->phy.autoneg_advertised;
6007 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
6008 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
6009
6010 /* setup the highest link when no autoneg */
6011 if (!autoneg) {
6012 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6013 speed = IXGBE_LINK_SPEED_10GB_FULL;
6014 }
6015 }
6016
6017 if (hw->mac.ops.setup_link)
6018 hw->mac.ops.setup_link(hw, speed, true);
6019
6020 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6021 adapter->link_check_timeout = jiffies;
6022 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6023 }
6024
6025 #ifdef CONFIG_PCI_IOV
6026 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6027 {
6028 int vf;
6029 struct ixgbe_hw *hw = &adapter->hw;
6030 struct net_device *netdev = adapter->netdev;
6031 u32 gpc;
6032 u32 ciaa, ciad;
6033
6034 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6035 if (gpc) /* If incrementing then no need for the check below */
6036 return;
6037 /*
6038 * Check to see if a bad DMA write target from an errant or
6039 * malicious VF has caused a PCIe error. If so then we can
6040 * issue a VFLR to the offending VF(s) and then resume without
6041 * requesting a full slot reset.
6042 */
6043
6044 for (vf = 0; vf < adapter->num_vfs; vf++) {
6045 ciaa = (vf << 16) | 0x80000000;
6046 /* 32 bit read so align, we really want status at offset 6 */
6047 ciaa |= PCI_COMMAND;
6048 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6049 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6050 ciaa &= 0x7FFFFFFF;
6051 /* disable debug mode asap after reading data */
6052 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6053 /* Get the upper 16 bits which will be the PCI status reg */
6054 ciad >>= 16;
6055 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6056 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6057 /* Issue VFLR */
6058 ciaa = (vf << 16) | 0x80000000;
6059 ciaa |= 0xA8;
6060 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6061 ciad = 0x00008000; /* VFLR */
6062 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6063 ciaa &= 0x7FFFFFFF;
6064 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6065 }
6066 }
6067 }
6068
6069 #endif
6070 /**
6071 * ixgbe_service_timer - Timer Call-back
6072 * @data: pointer to adapter cast into an unsigned long
6073 **/
6074 static void ixgbe_service_timer(unsigned long data)
6075 {
6076 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6077 unsigned long next_event_offset;
6078 bool ready = true;
6079
6080 /* poll faster when waiting for link */
6081 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6082 next_event_offset = HZ / 10;
6083 else
6084 next_event_offset = HZ * 2;
6085
6086 #ifdef CONFIG_PCI_IOV
6087 /*
6088 * don't bother with SR-IOV VF DMA hang check if there are
6089 * no VFs or the link is down
6090 */
6091 if (!adapter->num_vfs ||
6092 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6093 goto normal_timer_service;
6094
6095 /* If we have VFs allocated then we must check for DMA hangs */
6096 ixgbe_check_for_bad_vf(adapter);
6097 next_event_offset = HZ / 50;
6098 adapter->timer_event_accumulator++;
6099
6100 if (adapter->timer_event_accumulator >= 100)
6101 adapter->timer_event_accumulator = 0;
6102 else
6103 ready = false;
6104
6105 normal_timer_service:
6106 #endif
6107 /* Reset the timer */
6108 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6109
6110 if (ready)
6111 ixgbe_service_event_schedule(adapter);
6112 }
6113
6114 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6115 {
6116 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6117 return;
6118
6119 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6120
6121 /* If we're already down or resetting, just bail */
6122 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6123 test_bit(__IXGBE_RESETTING, &adapter->state))
6124 return;
6125
6126 ixgbe_dump(adapter);
6127 netdev_err(adapter->netdev, "Reset adapter\n");
6128 adapter->tx_timeout_count++;
6129
6130 ixgbe_reinit_locked(adapter);
6131 }
6132
6133 /**
6134 * ixgbe_service_task - manages and runs subtasks
6135 * @work: pointer to work_struct containing our data
6136 **/
6137 static void ixgbe_service_task(struct work_struct *work)
6138 {
6139 struct ixgbe_adapter *adapter = container_of(work,
6140 struct ixgbe_adapter,
6141 service_task);
6142 ixgbe_reset_subtask(adapter);
6143 ixgbe_sfp_detection_subtask(adapter);
6144 ixgbe_sfp_link_config_subtask(adapter);
6145 ixgbe_check_overtemp_subtask(adapter);
6146 ixgbe_watchdog_subtask(adapter);
6147 ixgbe_fdir_reinit_subtask(adapter);
6148 ixgbe_check_hang_subtask(adapter);
6149
6150 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
6151 ixgbe_ptp_overflow_check(adapter);
6152 ixgbe_ptp_rx_hang(adapter);
6153 }
6154
6155 ixgbe_service_event_complete(adapter);
6156 }
6157
6158 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6159 struct ixgbe_tx_buffer *first,
6160 u8 *hdr_len)
6161 {
6162 struct sk_buff *skb = first->skb;
6163 u32 vlan_macip_lens, type_tucmd;
6164 u32 mss_l4len_idx, l4len;
6165
6166 if (skb->ip_summed != CHECKSUM_PARTIAL)
6167 return 0;
6168
6169 if (!skb_is_gso(skb))
6170 return 0;
6171
6172 if (skb_header_cloned(skb)) {
6173 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6174 if (err)
6175 return err;
6176 }
6177
6178 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6179 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6180
6181 if (first->protocol == __constant_htons(ETH_P_IP)) {
6182 struct iphdr *iph = ip_hdr(skb);
6183 iph->tot_len = 0;
6184 iph->check = 0;
6185 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6186 iph->daddr, 0,
6187 IPPROTO_TCP,
6188 0);
6189 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6190 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6191 IXGBE_TX_FLAGS_CSUM |
6192 IXGBE_TX_FLAGS_IPV4;
6193 } else if (skb_is_gso_v6(skb)) {
6194 ipv6_hdr(skb)->payload_len = 0;
6195 tcp_hdr(skb)->check =
6196 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6197 &ipv6_hdr(skb)->daddr,
6198 0, IPPROTO_TCP, 0);
6199 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6200 IXGBE_TX_FLAGS_CSUM;
6201 }
6202
6203 /* compute header lengths */
6204 l4len = tcp_hdrlen(skb);
6205 *hdr_len = skb_transport_offset(skb) + l4len;
6206
6207 /* update gso size and bytecount with header size */
6208 first->gso_segs = skb_shinfo(skb)->gso_segs;
6209 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6210
6211 /* mss_l4len_id: use 0 as index for TSO */
6212 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6213 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6214
6215 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6216 vlan_macip_lens = skb_network_header_len(skb);
6217 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6218 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6219
6220 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6221 mss_l4len_idx);
6222
6223 return 1;
6224 }
6225
6226 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6227 struct ixgbe_tx_buffer *first)
6228 {
6229 struct sk_buff *skb = first->skb;
6230 u32 vlan_macip_lens = 0;
6231 u32 mss_l4len_idx = 0;
6232 u32 type_tucmd = 0;
6233
6234 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6235 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6236 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6237 return;
6238 } else {
6239 u8 l4_hdr = 0;
6240 switch (first->protocol) {
6241 case __constant_htons(ETH_P_IP):
6242 vlan_macip_lens |= skb_network_header_len(skb);
6243 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6244 l4_hdr = ip_hdr(skb)->protocol;
6245 break;
6246 case __constant_htons(ETH_P_IPV6):
6247 vlan_macip_lens |= skb_network_header_len(skb);
6248 l4_hdr = ipv6_hdr(skb)->nexthdr;
6249 break;
6250 default:
6251 if (unlikely(net_ratelimit())) {
6252 dev_warn(tx_ring->dev,
6253 "partial checksum but proto=%x!\n",
6254 first->protocol);
6255 }
6256 break;
6257 }
6258
6259 switch (l4_hdr) {
6260 case IPPROTO_TCP:
6261 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6262 mss_l4len_idx = tcp_hdrlen(skb) <<
6263 IXGBE_ADVTXD_L4LEN_SHIFT;
6264 break;
6265 case IPPROTO_SCTP:
6266 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6267 mss_l4len_idx = sizeof(struct sctphdr) <<
6268 IXGBE_ADVTXD_L4LEN_SHIFT;
6269 break;
6270 case IPPROTO_UDP:
6271 mss_l4len_idx = sizeof(struct udphdr) <<
6272 IXGBE_ADVTXD_L4LEN_SHIFT;
6273 break;
6274 default:
6275 if (unlikely(net_ratelimit())) {
6276 dev_warn(tx_ring->dev,
6277 "partial checksum but l4 proto=%x!\n",
6278 l4_hdr);
6279 }
6280 break;
6281 }
6282
6283 /* update TX checksum flag */
6284 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
6285 }
6286
6287 /* vlan_macip_lens: MACLEN, VLAN tag */
6288 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6289 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6290
6291 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6292 type_tucmd, mss_l4len_idx);
6293 }
6294
6295 #define IXGBE_SET_FLAG(_input, _flag, _result) \
6296 ((_flag <= _result) ? \
6297 ((u32)(_input & _flag) * (_result / _flag)) : \
6298 ((u32)(_input & _flag) / (_flag / _result)))
6299
6300 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6301 {
6302 /* set type for advanced descriptor with frame checksum insertion */
6303 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6304 IXGBE_ADVTXD_DCMD_DEXT |
6305 IXGBE_ADVTXD_DCMD_IFCS;
6306
6307 /* set HW vlan bit if vlan is present */
6308 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6309 IXGBE_ADVTXD_DCMD_VLE);
6310
6311 /* set segmentation enable bits for TSO/FSO */
6312 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6313 IXGBE_ADVTXD_DCMD_TSE);
6314
6315 /* set timestamp bit if present */
6316 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6317 IXGBE_ADVTXD_MAC_TSTAMP);
6318
6319 /* insert frame checksum */
6320 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
6321
6322 return cmd_type;
6323 }
6324
6325 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6326 u32 tx_flags, unsigned int paylen)
6327 {
6328 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
6329
6330 /* enable L4 checksum for TSO and TX checksum offload */
6331 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6332 IXGBE_TX_FLAGS_CSUM,
6333 IXGBE_ADVTXD_POPTS_TXSM);
6334
6335 /* enble IPv4 checksum for TSO */
6336 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6337 IXGBE_TX_FLAGS_IPV4,
6338 IXGBE_ADVTXD_POPTS_IXSM);
6339
6340 /*
6341 * Check Context must be set if Tx switch is enabled, which it
6342 * always is for case where virtual functions are running
6343 */
6344 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6345 IXGBE_TX_FLAGS_CC,
6346 IXGBE_ADVTXD_CC);
6347
6348 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6349 }
6350
6351 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6352 IXGBE_TXD_CMD_RS)
6353
6354 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6355 struct ixgbe_tx_buffer *first,
6356 const u8 hdr_len)
6357 {
6358 struct sk_buff *skb = first->skb;
6359 struct ixgbe_tx_buffer *tx_buffer;
6360 union ixgbe_adv_tx_desc *tx_desc;
6361 struct skb_frag_struct *frag;
6362 dma_addr_t dma;
6363 unsigned int data_len, size;
6364 u32 tx_flags = first->tx_flags;
6365 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
6366 u16 i = tx_ring->next_to_use;
6367
6368 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6369
6370 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6371
6372 size = skb_headlen(skb);
6373 data_len = skb->data_len;
6374
6375 #ifdef IXGBE_FCOE
6376 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6377 if (data_len < sizeof(struct fcoe_crc_eof)) {
6378 size -= sizeof(struct fcoe_crc_eof) - data_len;
6379 data_len = 0;
6380 } else {
6381 data_len -= sizeof(struct fcoe_crc_eof);
6382 }
6383 }
6384
6385 #endif
6386 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6387
6388 tx_buffer = first;
6389
6390 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6391 if (dma_mapping_error(tx_ring->dev, dma))
6392 goto dma_error;
6393
6394 /* record length, and DMA address */
6395 dma_unmap_len_set(tx_buffer, len, size);
6396 dma_unmap_addr_set(tx_buffer, dma, dma);
6397
6398 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6399
6400 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6401 tx_desc->read.cmd_type_len =
6402 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
6403
6404 i++;
6405 tx_desc++;
6406 if (i == tx_ring->count) {
6407 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6408 i = 0;
6409 }
6410 tx_desc->read.olinfo_status = 0;
6411
6412 dma += IXGBE_MAX_DATA_PER_TXD;
6413 size -= IXGBE_MAX_DATA_PER_TXD;
6414
6415 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6416 }
6417
6418 if (likely(!data_len))
6419 break;
6420
6421 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6422
6423 i++;
6424 tx_desc++;
6425 if (i == tx_ring->count) {
6426 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6427 i = 0;
6428 }
6429 tx_desc->read.olinfo_status = 0;
6430
6431 #ifdef IXGBE_FCOE
6432 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6433 #else
6434 size = skb_frag_size(frag);
6435 #endif
6436 data_len -= size;
6437
6438 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6439 DMA_TO_DEVICE);
6440
6441 tx_buffer = &tx_ring->tx_buffer_info[i];
6442 }
6443
6444 /* write last descriptor with RS and EOP bits */
6445 cmd_type |= size | IXGBE_TXD_CMD;
6446 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6447
6448 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6449
6450 /* set the timestamp */
6451 first->time_stamp = jiffies;
6452
6453 /*
6454 * Force memory writes to complete before letting h/w know there
6455 * are new descriptors to fetch. (Only applicable for weak-ordered
6456 * memory model archs, such as IA-64).
6457 *
6458 * We also need this memory barrier to make certain all of the
6459 * status bits have been updated before next_to_watch is written.
6460 */
6461 wmb();
6462
6463 /* set next_to_watch value indicating a packet is present */
6464 first->next_to_watch = tx_desc;
6465
6466 i++;
6467 if (i == tx_ring->count)
6468 i = 0;
6469
6470 tx_ring->next_to_use = i;
6471
6472 /* notify HW of packet */
6473 writel(i, tx_ring->tail);
6474
6475 return;
6476 dma_error:
6477 dev_err(tx_ring->dev, "TX DMA map failed\n");
6478
6479 /* clear dma mappings for failed tx_buffer_info map */
6480 for (;;) {
6481 tx_buffer = &tx_ring->tx_buffer_info[i];
6482 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6483 if (tx_buffer == first)
6484 break;
6485 if (i == 0)
6486 i = tx_ring->count;
6487 i--;
6488 }
6489
6490 tx_ring->next_to_use = i;
6491 }
6492
6493 static void ixgbe_atr(struct ixgbe_ring *ring,
6494 struct ixgbe_tx_buffer *first)
6495 {
6496 struct ixgbe_q_vector *q_vector = ring->q_vector;
6497 union ixgbe_atr_hash_dword input = { .dword = 0 };
6498 union ixgbe_atr_hash_dword common = { .dword = 0 };
6499 union {
6500 unsigned char *network;
6501 struct iphdr *ipv4;
6502 struct ipv6hdr *ipv6;
6503 } hdr;
6504 struct tcphdr *th;
6505 __be16 vlan_id;
6506
6507 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6508 if (!q_vector)
6509 return;
6510
6511 /* do nothing if sampling is disabled */
6512 if (!ring->atr_sample_rate)
6513 return;
6514
6515 ring->atr_count++;
6516
6517 /* snag network header to get L4 type and address */
6518 hdr.network = skb_network_header(first->skb);
6519
6520 /* Currently only IPv4/IPv6 with TCP is supported */
6521 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6522 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6523 (first->protocol != __constant_htons(ETH_P_IP) ||
6524 hdr.ipv4->protocol != IPPROTO_TCP))
6525 return;
6526
6527 th = tcp_hdr(first->skb);
6528
6529 /* skip this packet since it is invalid or the socket is closing */
6530 if (!th || th->fin)
6531 return;
6532
6533 /* sample on all syn packets or once every atr sample count */
6534 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6535 return;
6536
6537 /* reset sample count */
6538 ring->atr_count = 0;
6539
6540 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6541
6542 /*
6543 * src and dst are inverted, think how the receiver sees them
6544 *
6545 * The input is broken into two sections, a non-compressed section
6546 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6547 * is XORed together and stored in the compressed dword.
6548 */
6549 input.formatted.vlan_id = vlan_id;
6550
6551 /*
6552 * since src port and flex bytes occupy the same word XOR them together
6553 * and write the value to source port portion of compressed dword
6554 */
6555 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6556 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6557 else
6558 common.port.src ^= th->dest ^ first->protocol;
6559 common.port.dst ^= th->source;
6560
6561 if (first->protocol == __constant_htons(ETH_P_IP)) {
6562 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6563 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6564 } else {
6565 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6566 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6567 hdr.ipv6->saddr.s6_addr32[1] ^
6568 hdr.ipv6->saddr.s6_addr32[2] ^
6569 hdr.ipv6->saddr.s6_addr32[3] ^
6570 hdr.ipv6->daddr.s6_addr32[0] ^
6571 hdr.ipv6->daddr.s6_addr32[1] ^
6572 hdr.ipv6->daddr.s6_addr32[2] ^
6573 hdr.ipv6->daddr.s6_addr32[3];
6574 }
6575
6576 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6577 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6578 input, common, ring->queue_index);
6579 }
6580
6581 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6582 {
6583 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6584 /* Herbert's original patch had:
6585 * smp_mb__after_netif_stop_queue();
6586 * but since that doesn't exist yet, just open code it. */
6587 smp_mb();
6588
6589 /* We need to check again in a case another CPU has just
6590 * made room available. */
6591 if (likely(ixgbe_desc_unused(tx_ring) < size))
6592 return -EBUSY;
6593
6594 /* A reprieve! - use start_queue because it doesn't call schedule */
6595 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6596 ++tx_ring->tx_stats.restart_queue;
6597 return 0;
6598 }
6599
6600 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6601 {
6602 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6603 return 0;
6604 return __ixgbe_maybe_stop_tx(tx_ring, size);
6605 }
6606
6607 #ifdef IXGBE_FCOE
6608 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6609 {
6610 struct ixgbe_adapter *adapter;
6611 struct ixgbe_ring_feature *f;
6612 int txq;
6613
6614 /*
6615 * only execute the code below if protocol is FCoE
6616 * or FIP and we have FCoE enabled on the adapter
6617 */
6618 switch (vlan_get_protocol(skb)) {
6619 case __constant_htons(ETH_P_FCOE):
6620 case __constant_htons(ETH_P_FIP):
6621 adapter = netdev_priv(dev);
6622
6623 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6624 break;
6625 default:
6626 return __netdev_pick_tx(dev, skb);
6627 }
6628
6629 f = &adapter->ring_feature[RING_F_FCOE];
6630
6631 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6632 smp_processor_id();
6633
6634 while (txq >= f->indices)
6635 txq -= f->indices;
6636
6637 return txq + f->offset;
6638 }
6639
6640 #endif
6641 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6642 struct ixgbe_adapter *adapter,
6643 struct ixgbe_ring *tx_ring)
6644 {
6645 struct ixgbe_tx_buffer *first;
6646 int tso;
6647 u32 tx_flags = 0;
6648 unsigned short f;
6649 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6650 __be16 protocol = skb->protocol;
6651 u8 hdr_len = 0;
6652
6653 /*
6654 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6655 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6656 * + 2 desc gap to keep tail from touching head,
6657 * + 1 desc for context descriptor,
6658 * otherwise try next time
6659 */
6660 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6661 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6662
6663 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6664 tx_ring->tx_stats.tx_busy++;
6665 return NETDEV_TX_BUSY;
6666 }
6667
6668 /* record the location of the first descriptor for this packet */
6669 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6670 first->skb = skb;
6671 first->bytecount = skb->len;
6672 first->gso_segs = 1;
6673
6674 /* if we have a HW VLAN tag being added default to the HW one */
6675 if (vlan_tx_tag_present(skb)) {
6676 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6677 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6678 /* else if it is a SW VLAN check the next protocol and store the tag */
6679 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6680 struct vlan_hdr *vhdr, _vhdr;
6681 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6682 if (!vhdr)
6683 goto out_drop;
6684
6685 protocol = vhdr->h_vlan_encapsulated_proto;
6686 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6687 IXGBE_TX_FLAGS_VLAN_SHIFT;
6688 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6689 }
6690
6691 skb_tx_timestamp(skb);
6692
6693 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6694 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6695 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6696
6697 /* schedule check for Tx timestamp */
6698 adapter->ptp_tx_skb = skb_get(skb);
6699 adapter->ptp_tx_start = jiffies;
6700 schedule_work(&adapter->ptp_tx_work);
6701 }
6702
6703 #ifdef CONFIG_PCI_IOV
6704 /*
6705 * Use the l2switch_enable flag - would be false if the DMA
6706 * Tx switch had been disabled.
6707 */
6708 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6709 tx_flags |= IXGBE_TX_FLAGS_CC;
6710
6711 #endif
6712 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6713 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6714 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6715 (skb->priority != TC_PRIO_CONTROL))) {
6716 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6717 tx_flags |= (skb->priority & 0x7) <<
6718 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6719 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6720 struct vlan_ethhdr *vhdr;
6721 if (skb_header_cloned(skb) &&
6722 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6723 goto out_drop;
6724 vhdr = (struct vlan_ethhdr *)skb->data;
6725 vhdr->h_vlan_TCI = htons(tx_flags >>
6726 IXGBE_TX_FLAGS_VLAN_SHIFT);
6727 } else {
6728 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6729 }
6730 }
6731
6732 /* record initial flags and protocol */
6733 first->tx_flags = tx_flags;
6734 first->protocol = protocol;
6735
6736 #ifdef IXGBE_FCOE
6737 /* setup tx offload for FCoE */
6738 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6739 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
6740 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6741 if (tso < 0)
6742 goto out_drop;
6743
6744 goto xmit_fcoe;
6745 }
6746
6747 #endif /* IXGBE_FCOE */
6748 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6749 if (tso < 0)
6750 goto out_drop;
6751 else if (!tso)
6752 ixgbe_tx_csum(tx_ring, first);
6753
6754 /* add the ATR filter if ATR is on */
6755 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6756 ixgbe_atr(tx_ring, first);
6757
6758 #ifdef IXGBE_FCOE
6759 xmit_fcoe:
6760 #endif /* IXGBE_FCOE */
6761 ixgbe_tx_map(tx_ring, first, hdr_len);
6762
6763 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6764
6765 return NETDEV_TX_OK;
6766
6767 out_drop:
6768 dev_kfree_skb_any(first->skb);
6769 first->skb = NULL;
6770
6771 return NETDEV_TX_OK;
6772 }
6773
6774 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6775 struct net_device *netdev)
6776 {
6777 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6778 struct ixgbe_ring *tx_ring;
6779
6780 /*
6781 * The minimum packet size for olinfo paylen is 17 so pad the skb
6782 * in order to meet this minimum size requirement.
6783 */
6784 if (unlikely(skb->len < 17)) {
6785 if (skb_pad(skb, 17 - skb->len))
6786 return NETDEV_TX_OK;
6787 skb->len = 17;
6788 skb_set_tail_pointer(skb, 17);
6789 }
6790
6791 tx_ring = adapter->tx_ring[skb->queue_mapping];
6792 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6793 }
6794
6795 /**
6796 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6797 * @netdev: network interface device structure
6798 * @p: pointer to an address structure
6799 *
6800 * Returns 0 on success, negative on failure
6801 **/
6802 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6803 {
6804 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6805 struct ixgbe_hw *hw = &adapter->hw;
6806 struct sockaddr *addr = p;
6807
6808 if (!is_valid_ether_addr(addr->sa_data))
6809 return -EADDRNOTAVAIL;
6810
6811 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6812 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6813
6814 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
6815
6816 return 0;
6817 }
6818
6819 static int
6820 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6821 {
6822 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6823 struct ixgbe_hw *hw = &adapter->hw;
6824 u16 value;
6825 int rc;
6826
6827 if (prtad != hw->phy.mdio.prtad)
6828 return -EINVAL;
6829 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6830 if (!rc)
6831 rc = value;
6832 return rc;
6833 }
6834
6835 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6836 u16 addr, u16 value)
6837 {
6838 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6839 struct ixgbe_hw *hw = &adapter->hw;
6840
6841 if (prtad != hw->phy.mdio.prtad)
6842 return -EINVAL;
6843 return hw->phy.ops.write_reg(hw, addr, devad, value);
6844 }
6845
6846 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6847 {
6848 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6849
6850 switch (cmd) {
6851 case SIOCSHWTSTAMP:
6852 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6853 default:
6854 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6855 }
6856 }
6857
6858 /**
6859 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6860 * netdev->dev_addrs
6861 * @netdev: network interface device structure
6862 *
6863 * Returns non-zero on failure
6864 **/
6865 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6866 {
6867 int err = 0;
6868 struct ixgbe_adapter *adapter = netdev_priv(dev);
6869 struct ixgbe_hw *hw = &adapter->hw;
6870
6871 if (is_valid_ether_addr(hw->mac.san_addr)) {
6872 rtnl_lock();
6873 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
6874 rtnl_unlock();
6875
6876 /* update SAN MAC vmdq pool selection */
6877 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
6878 }
6879 return err;
6880 }
6881
6882 /**
6883 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6884 * netdev->dev_addrs
6885 * @netdev: network interface device structure
6886 *
6887 * Returns non-zero on failure
6888 **/
6889 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6890 {
6891 int err = 0;
6892 struct ixgbe_adapter *adapter = netdev_priv(dev);
6893 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6894
6895 if (is_valid_ether_addr(mac->san_addr)) {
6896 rtnl_lock();
6897 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6898 rtnl_unlock();
6899 }
6900 return err;
6901 }
6902
6903 #ifdef CONFIG_NET_POLL_CONTROLLER
6904 /*
6905 * Polling 'interrupt' - used by things like netconsole to send skbs
6906 * without having to re-enable interrupts. It's not called while
6907 * the interrupt routine is executing.
6908 */
6909 static void ixgbe_netpoll(struct net_device *netdev)
6910 {
6911 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6912 int i;
6913
6914 /* if interface is down do nothing */
6915 if (test_bit(__IXGBE_DOWN, &adapter->state))
6916 return;
6917
6918 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6919 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6920 for (i = 0; i < adapter->num_q_vectors; i++)
6921 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
6922 } else {
6923 ixgbe_intr(adapter->pdev->irq, netdev);
6924 }
6925 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6926 }
6927
6928 #endif
6929 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6930 struct rtnl_link_stats64 *stats)
6931 {
6932 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6933 int i;
6934
6935 rcu_read_lock();
6936 for (i = 0; i < adapter->num_rx_queues; i++) {
6937 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6938 u64 bytes, packets;
6939 unsigned int start;
6940
6941 if (ring) {
6942 do {
6943 start = u64_stats_fetch_begin_bh(&ring->syncp);
6944 packets = ring->stats.packets;
6945 bytes = ring->stats.bytes;
6946 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6947 stats->rx_packets += packets;
6948 stats->rx_bytes += bytes;
6949 }
6950 }
6951
6952 for (i = 0; i < adapter->num_tx_queues; i++) {
6953 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6954 u64 bytes, packets;
6955 unsigned int start;
6956
6957 if (ring) {
6958 do {
6959 start = u64_stats_fetch_begin_bh(&ring->syncp);
6960 packets = ring->stats.packets;
6961 bytes = ring->stats.bytes;
6962 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6963 stats->tx_packets += packets;
6964 stats->tx_bytes += bytes;
6965 }
6966 }
6967 rcu_read_unlock();
6968 /* following stats updated by ixgbe_watchdog_task() */
6969 stats->multicast = netdev->stats.multicast;
6970 stats->rx_errors = netdev->stats.rx_errors;
6971 stats->rx_length_errors = netdev->stats.rx_length_errors;
6972 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6973 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6974 return stats;
6975 }
6976
6977 #ifdef CONFIG_IXGBE_DCB
6978 /**
6979 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6980 * @adapter: pointer to ixgbe_adapter
6981 * @tc: number of traffic classes currently enabled
6982 *
6983 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6984 * 802.1Q priority maps to a packet buffer that exists.
6985 */
6986 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6987 {
6988 struct ixgbe_hw *hw = &adapter->hw;
6989 u32 reg, rsave;
6990 int i;
6991
6992 /* 82598 have a static priority to TC mapping that can not
6993 * be changed so no validation is needed.
6994 */
6995 if (hw->mac.type == ixgbe_mac_82598EB)
6996 return;
6997
6998 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6999 rsave = reg;
7000
7001 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7002 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7003
7004 /* If up2tc is out of bounds default to zero */
7005 if (up2tc > tc)
7006 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7007 }
7008
7009 if (reg != rsave)
7010 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7011
7012 return;
7013 }
7014
7015 /**
7016 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7017 * @adapter: Pointer to adapter struct
7018 *
7019 * Populate the netdev user priority to tc map
7020 */
7021 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7022 {
7023 struct net_device *dev = adapter->netdev;
7024 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7025 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7026 u8 prio;
7027
7028 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7029 u8 tc = 0;
7030
7031 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7032 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7033 else if (ets)
7034 tc = ets->prio_tc[prio];
7035
7036 netdev_set_prio_tc_map(dev, prio, tc);
7037 }
7038 }
7039
7040 #endif /* CONFIG_IXGBE_DCB */
7041 /**
7042 * ixgbe_setup_tc - configure net_device for multiple traffic classes
7043 *
7044 * @netdev: net device to configure
7045 * @tc: number of traffic classes to enable
7046 */
7047 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7048 {
7049 struct ixgbe_adapter *adapter = netdev_priv(dev);
7050 struct ixgbe_hw *hw = &adapter->hw;
7051
7052 /* Hardware supports up to 8 traffic classes */
7053 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
7054 (hw->mac.type == ixgbe_mac_82598EB &&
7055 tc < MAX_TRAFFIC_CLASS))
7056 return -EINVAL;
7057
7058 /* Hardware has to reinitialize queues and interrupts to
7059 * match packet buffer alignment. Unfortunately, the
7060 * hardware is not flexible enough to do this dynamically.
7061 */
7062 if (netif_running(dev))
7063 ixgbe_close(dev);
7064 ixgbe_clear_interrupt_scheme(adapter);
7065
7066 #ifdef CONFIG_IXGBE_DCB
7067 if (tc) {
7068 netdev_set_num_tc(dev, tc);
7069 ixgbe_set_prio_tc_map(adapter);
7070
7071 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7072
7073 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7074 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
7075 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7076 }
7077 } else {
7078 netdev_reset_tc(dev);
7079
7080 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7081 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7082
7083 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7084
7085 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7086 adapter->dcb_cfg.pfc_mode_enable = false;
7087 }
7088
7089 ixgbe_validate_rtr(adapter, tc);
7090
7091 #endif /* CONFIG_IXGBE_DCB */
7092 ixgbe_init_interrupt_scheme(adapter);
7093
7094 if (netif_running(dev))
7095 return ixgbe_open(dev);
7096
7097 return 0;
7098 }
7099
7100 #ifdef CONFIG_PCI_IOV
7101 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7102 {
7103 struct net_device *netdev = adapter->netdev;
7104
7105 rtnl_lock();
7106 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
7107 rtnl_unlock();
7108 }
7109
7110 #endif
7111 void ixgbe_do_reset(struct net_device *netdev)
7112 {
7113 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7114
7115 if (netif_running(netdev))
7116 ixgbe_reinit_locked(adapter);
7117 else
7118 ixgbe_reset(adapter);
7119 }
7120
7121 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7122 netdev_features_t features)
7123 {
7124 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7125
7126 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7127 if (!(features & NETIF_F_RXCSUM))
7128 features &= ~NETIF_F_LRO;
7129
7130 /* Turn off LRO if not RSC capable */
7131 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7132 features &= ~NETIF_F_LRO;
7133
7134 return features;
7135 }
7136
7137 static int ixgbe_set_features(struct net_device *netdev,
7138 netdev_features_t features)
7139 {
7140 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7141 netdev_features_t changed = netdev->features ^ features;
7142 bool need_reset = false;
7143
7144 /* Make sure RSC matches LRO, reset if change */
7145 if (!(features & NETIF_F_LRO)) {
7146 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7147 need_reset = true;
7148 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7149 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7150 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7151 if (adapter->rx_itr_setting == 1 ||
7152 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7153 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7154 need_reset = true;
7155 } else if ((changed ^ features) & NETIF_F_LRO) {
7156 e_info(probe, "rx-usecs set too low, "
7157 "disabling RSC\n");
7158 }
7159 }
7160
7161 /*
7162 * Check if Flow Director n-tuple support was enabled or disabled. If
7163 * the state changed, we need to reset.
7164 */
7165 switch (features & NETIF_F_NTUPLE) {
7166 case NETIF_F_NTUPLE:
7167 /* turn off ATR, enable perfect filters and reset */
7168 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7169 need_reset = true;
7170
7171 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7172 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7173 break;
7174 default:
7175 /* turn off perfect filters, enable ATR and reset */
7176 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7177 need_reset = true;
7178
7179 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7180
7181 /* We cannot enable ATR if SR-IOV is enabled */
7182 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7183 break;
7184
7185 /* We cannot enable ATR if we have 2 or more traffic classes */
7186 if (netdev_get_num_tc(netdev) > 1)
7187 break;
7188
7189 /* We cannot enable ATR if RSS is disabled */
7190 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7191 break;
7192
7193 /* A sample rate of 0 indicates ATR disabled */
7194 if (!adapter->atr_sample_rate)
7195 break;
7196
7197 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7198 break;
7199 }
7200
7201 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7202 ixgbe_vlan_strip_enable(adapter);
7203 else
7204 ixgbe_vlan_strip_disable(adapter);
7205
7206 if (changed & NETIF_F_RXALL)
7207 need_reset = true;
7208
7209 netdev->features = features;
7210 if (need_reset)
7211 ixgbe_do_reset(netdev);
7212
7213 return 0;
7214 }
7215
7216 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7217 struct net_device *dev,
7218 const unsigned char *addr,
7219 u16 flags)
7220 {
7221 struct ixgbe_adapter *adapter = netdev_priv(dev);
7222 int err;
7223
7224 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7225 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
7226
7227 /* Hardware does not support aging addresses so if a
7228 * ndm_state is given only allow permanent addresses
7229 */
7230 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7231 pr_info("%s: FDB only supports static addresses\n",
7232 ixgbe_driver_name);
7233 return -EINVAL;
7234 }
7235
7236 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
7237 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7238
7239 if (netdev_uc_count(dev) < rar_uc_entries)
7240 err = dev_uc_add_excl(dev, addr);
7241 else
7242 err = -ENOMEM;
7243 } else if (is_multicast_ether_addr(addr)) {
7244 err = dev_mc_add_excl(dev, addr);
7245 } else {
7246 err = -EINVAL;
7247 }
7248
7249 /* Only return duplicate errors if NLM_F_EXCL is set */
7250 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7251 err = 0;
7252
7253 return err;
7254 }
7255
7256 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7257 struct nlmsghdr *nlh)
7258 {
7259 struct ixgbe_adapter *adapter = netdev_priv(dev);
7260 struct nlattr *attr, *br_spec;
7261 int rem;
7262
7263 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7264 return -EOPNOTSUPP;
7265
7266 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7267
7268 nla_for_each_nested(attr, br_spec, rem) {
7269 __u16 mode;
7270 u32 reg = 0;
7271
7272 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7273 continue;
7274
7275 mode = nla_get_u16(attr);
7276 if (mode == BRIDGE_MODE_VEPA) {
7277 reg = 0;
7278 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7279 } else if (mode == BRIDGE_MODE_VEB) {
7280 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7281 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7282 } else
7283 return -EINVAL;
7284
7285 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7286
7287 e_info(drv, "enabling bridge mode: %s\n",
7288 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7289 }
7290
7291 return 0;
7292 }
7293
7294 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7295 struct net_device *dev,
7296 u32 filter_mask)
7297 {
7298 struct ixgbe_adapter *adapter = netdev_priv(dev);
7299 u16 mode;
7300
7301 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7302 return 0;
7303
7304 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
7305 mode = BRIDGE_MODE_VEB;
7306 else
7307 mode = BRIDGE_MODE_VEPA;
7308
7309 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7310 }
7311
7312 static const struct net_device_ops ixgbe_netdev_ops = {
7313 .ndo_open = ixgbe_open,
7314 .ndo_stop = ixgbe_close,
7315 .ndo_start_xmit = ixgbe_xmit_frame,
7316 #ifdef IXGBE_FCOE
7317 .ndo_select_queue = ixgbe_select_queue,
7318 #endif
7319 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7320 .ndo_validate_addr = eth_validate_addr,
7321 .ndo_set_mac_address = ixgbe_set_mac,
7322 .ndo_change_mtu = ixgbe_change_mtu,
7323 .ndo_tx_timeout = ixgbe_tx_timeout,
7324 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7325 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7326 .ndo_do_ioctl = ixgbe_ioctl,
7327 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7328 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7329 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7330 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7331 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7332 .ndo_get_stats64 = ixgbe_get_stats64,
7333 #ifdef CONFIG_IXGBE_DCB
7334 .ndo_setup_tc = ixgbe_setup_tc,
7335 #endif
7336 #ifdef CONFIG_NET_POLL_CONTROLLER
7337 .ndo_poll_controller = ixgbe_netpoll,
7338 #endif
7339 #ifdef CONFIG_NET_RX_BUSY_POLL
7340 .ndo_busy_poll = ixgbe_low_latency_recv,
7341 #endif
7342 #ifdef IXGBE_FCOE
7343 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7344 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7345 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7346 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7347 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7348 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7349 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7350 #endif /* IXGBE_FCOE */
7351 .ndo_set_features = ixgbe_set_features,
7352 .ndo_fix_features = ixgbe_fix_features,
7353 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7354 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7355 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
7356 };
7357
7358 /**
7359 * ixgbe_enumerate_functions - Get the number of ports this device has
7360 * @adapter: adapter structure
7361 *
7362 * This function enumerates the phsyical functions co-located on a single slot,
7363 * in order to determine how many ports a device has. This is most useful in
7364 * determining the required GT/s of PCIe bandwidth necessary for optimal
7365 * performance.
7366 **/
7367 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7368 {
7369 struct ixgbe_hw *hw = &adapter->hw;
7370 struct list_head *entry;
7371 int physfns = 0;
7372
7373 /* Some cards can not use the generic count PCIe functions method, and
7374 * so must be hardcoded to the correct value.
7375 */
7376 switch (hw->device_id) {
7377 case IXGBE_DEV_ID_82599_SFP_SF_QP:
7378 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
7379 physfns = 4;
7380 break;
7381 default:
7382 list_for_each(entry, &adapter->pdev->bus_list) {
7383 struct pci_dev *pdev =
7384 list_entry(entry, struct pci_dev, bus_list);
7385 /* don't count virtual functions */
7386 if (!pdev->is_virtfn)
7387 physfns++;
7388 }
7389 }
7390
7391 return physfns;
7392 }
7393
7394 /**
7395 * ixgbe_wol_supported - Check whether device supports WoL
7396 * @hw: hw specific details
7397 * @device_id: the device ID
7398 * @subdev_id: the subsystem device ID
7399 *
7400 * This function is used by probe and ethtool to determine
7401 * which devices have WoL support
7402 *
7403 **/
7404 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7405 u16 subdevice_id)
7406 {
7407 struct ixgbe_hw *hw = &adapter->hw;
7408 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7409 int is_wol_supported = 0;
7410
7411 switch (device_id) {
7412 case IXGBE_DEV_ID_82599_SFP:
7413 /* Only these subdevices could supports WOL */
7414 switch (subdevice_id) {
7415 case IXGBE_SUBDEV_ID_82599_560FLR:
7416 /* only support first port */
7417 if (hw->bus.func != 0)
7418 break;
7419 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
7420 case IXGBE_SUBDEV_ID_82599_SFP:
7421 case IXGBE_SUBDEV_ID_82599_RNDC:
7422 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
7423 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
7424 is_wol_supported = 1;
7425 break;
7426 }
7427 break;
7428 case IXGBE_DEV_ID_82599EN_SFP:
7429 /* Only this subdevice supports WOL */
7430 switch (subdevice_id) {
7431 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
7432 is_wol_supported = 1;
7433 break;
7434 }
7435 break;
7436 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7437 /* All except this subdevice support WOL */
7438 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7439 is_wol_supported = 1;
7440 break;
7441 case IXGBE_DEV_ID_82599_KX4:
7442 is_wol_supported = 1;
7443 break;
7444 case IXGBE_DEV_ID_X540T:
7445 case IXGBE_DEV_ID_X540T1:
7446 /* check eeprom to see if enabled wol */
7447 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7448 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7449 (hw->bus.func == 0))) {
7450 is_wol_supported = 1;
7451 }
7452 break;
7453 }
7454
7455 return is_wol_supported;
7456 }
7457
7458 /**
7459 * ixgbe_probe - Device Initialization Routine
7460 * @pdev: PCI device information struct
7461 * @ent: entry in ixgbe_pci_tbl
7462 *
7463 * Returns 0 on success, negative on failure
7464 *
7465 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7466 * The OS initialization, configuring of the adapter private structure,
7467 * and a hardware reset occur.
7468 **/
7469 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7470 {
7471 struct net_device *netdev;
7472 struct ixgbe_adapter *adapter = NULL;
7473 struct ixgbe_hw *hw;
7474 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7475 static int cards_found;
7476 int i, err, pci_using_dac, expected_gts;
7477 unsigned int indices = MAX_TX_QUEUES;
7478 u8 part_str[IXGBE_PBANUM_LENGTH];
7479 #ifdef IXGBE_FCOE
7480 u16 device_caps;
7481 #endif
7482 u32 eec;
7483
7484 /* Catch broken hardware that put the wrong VF device ID in
7485 * the PCIe SR-IOV capability.
7486 */
7487 if (pdev->is_virtfn) {
7488 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7489 pci_name(pdev), pdev->vendor, pdev->device);
7490 return -EINVAL;
7491 }
7492
7493 err = pci_enable_device_mem(pdev);
7494 if (err)
7495 return err;
7496
7497 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7498 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7499 pci_using_dac = 1;
7500 } else {
7501 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7502 if (err) {
7503 err = dma_set_coherent_mask(&pdev->dev,
7504 DMA_BIT_MASK(32));
7505 if (err) {
7506 dev_err(&pdev->dev,
7507 "No usable DMA configuration, aborting\n");
7508 goto err_dma;
7509 }
7510 }
7511 pci_using_dac = 0;
7512 }
7513
7514 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7515 IORESOURCE_MEM), ixgbe_driver_name);
7516 if (err) {
7517 dev_err(&pdev->dev,
7518 "pci_request_selected_regions failed 0x%x\n", err);
7519 goto err_pci_reg;
7520 }
7521
7522 pci_enable_pcie_error_reporting(pdev);
7523
7524 pci_set_master(pdev);
7525 pci_save_state(pdev);
7526
7527 if (ii->mac == ixgbe_mac_82598EB) {
7528 #ifdef CONFIG_IXGBE_DCB
7529 /* 8 TC w/ 4 queues per TC */
7530 indices = 4 * MAX_TRAFFIC_CLASS;
7531 #else
7532 indices = IXGBE_MAX_RSS_INDICES;
7533 #endif
7534 }
7535
7536 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7537 if (!netdev) {
7538 err = -ENOMEM;
7539 goto err_alloc_etherdev;
7540 }
7541
7542 SET_NETDEV_DEV(netdev, &pdev->dev);
7543
7544 adapter = netdev_priv(netdev);
7545 pci_set_drvdata(pdev, adapter);
7546
7547 adapter->netdev = netdev;
7548 adapter->pdev = pdev;
7549 hw = &adapter->hw;
7550 hw->back = adapter;
7551 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7552
7553 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7554 pci_resource_len(pdev, 0));
7555 if (!hw->hw_addr) {
7556 err = -EIO;
7557 goto err_ioremap;
7558 }
7559
7560 netdev->netdev_ops = &ixgbe_netdev_ops;
7561 ixgbe_set_ethtool_ops(netdev);
7562 netdev->watchdog_timeo = 5 * HZ;
7563 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7564
7565 adapter->bd_number = cards_found;
7566
7567 /* Setup hw api */
7568 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7569 hw->mac.type = ii->mac;
7570
7571 /* EEPROM */
7572 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7573 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7574 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7575 if (!(eec & (1 << 8)))
7576 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7577
7578 /* PHY */
7579 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7580 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7581 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7582 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7583 hw->phy.mdio.mmds = 0;
7584 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7585 hw->phy.mdio.dev = netdev;
7586 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7587 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7588
7589 ii->get_invariants(hw);
7590
7591 /* setup the private structure */
7592 err = ixgbe_sw_init(adapter);
7593 if (err)
7594 goto err_sw_init;
7595
7596 /* Cache if MNG FW is up so we don't have to read the REG later */
7597 if (hw->mac.ops.mng_fw_enabled)
7598 hw->mng_fw_enabled = hw->mac.ops.mng_fw_enabled(hw);
7599
7600 /* Make it possible the adapter to be woken up via WOL */
7601 switch (adapter->hw.mac.type) {
7602 case ixgbe_mac_82599EB:
7603 case ixgbe_mac_X540:
7604 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7605 break;
7606 default:
7607 break;
7608 }
7609
7610 /*
7611 * If there is a fan on this device and it has failed log the
7612 * failure.
7613 */
7614 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7615 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7616 if (esdp & IXGBE_ESDP_SDP1)
7617 e_crit(probe, "Fan has stopped, replace the adapter\n");
7618 }
7619
7620 if (allow_unsupported_sfp)
7621 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7622
7623 /* reset_hw fills in the perm_addr as well */
7624 hw->phy.reset_if_overtemp = true;
7625 err = hw->mac.ops.reset_hw(hw);
7626 hw->phy.reset_if_overtemp = false;
7627 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7628 hw->mac.type == ixgbe_mac_82598EB) {
7629 err = 0;
7630 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7631 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
7632 e_dev_err("Reload the driver after installing a supported module.\n");
7633 goto err_sw_init;
7634 } else if (err) {
7635 e_dev_err("HW Init failed: %d\n", err);
7636 goto err_sw_init;
7637 }
7638
7639 #ifdef CONFIG_PCI_IOV
7640 /* SR-IOV not supported on the 82598 */
7641 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7642 goto skip_sriov;
7643 /* Mailbox */
7644 ixgbe_init_mbx_params_pf(hw);
7645 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
7646 ixgbe_enable_sriov(adapter);
7647 pci_sriov_set_totalvfs(pdev, 63);
7648 skip_sriov:
7649
7650 #endif
7651 netdev->features = NETIF_F_SG |
7652 NETIF_F_IP_CSUM |
7653 NETIF_F_IPV6_CSUM |
7654 NETIF_F_HW_VLAN_CTAG_TX |
7655 NETIF_F_HW_VLAN_CTAG_RX |
7656 NETIF_F_HW_VLAN_CTAG_FILTER |
7657 NETIF_F_TSO |
7658 NETIF_F_TSO6 |
7659 NETIF_F_RXHASH |
7660 NETIF_F_RXCSUM;
7661
7662 netdev->hw_features = netdev->features;
7663
7664 switch (adapter->hw.mac.type) {
7665 case ixgbe_mac_82599EB:
7666 case ixgbe_mac_X540:
7667 netdev->features |= NETIF_F_SCTP_CSUM;
7668 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7669 NETIF_F_NTUPLE;
7670 break;
7671 default:
7672 break;
7673 }
7674
7675 netdev->hw_features |= NETIF_F_RXALL;
7676
7677 netdev->vlan_features |= NETIF_F_TSO;
7678 netdev->vlan_features |= NETIF_F_TSO6;
7679 netdev->vlan_features |= NETIF_F_IP_CSUM;
7680 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7681 netdev->vlan_features |= NETIF_F_SG;
7682
7683 netdev->priv_flags |= IFF_UNICAST_FLT;
7684 netdev->priv_flags |= IFF_SUPP_NOFCS;
7685
7686 #ifdef CONFIG_IXGBE_DCB
7687 netdev->dcbnl_ops = &dcbnl_ops;
7688 #endif
7689
7690 #ifdef IXGBE_FCOE
7691 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7692 unsigned int fcoe_l;
7693
7694 if (hw->mac.ops.get_device_caps) {
7695 hw->mac.ops.get_device_caps(hw, &device_caps);
7696 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7697 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7698 }
7699
7700
7701 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
7702 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7703
7704 netdev->features |= NETIF_F_FSO |
7705 NETIF_F_FCOE_CRC;
7706
7707 netdev->vlan_features |= NETIF_F_FSO |
7708 NETIF_F_FCOE_CRC |
7709 NETIF_F_FCOE_MTU;
7710 }
7711 #endif /* IXGBE_FCOE */
7712 if (pci_using_dac) {
7713 netdev->features |= NETIF_F_HIGHDMA;
7714 netdev->vlan_features |= NETIF_F_HIGHDMA;
7715 }
7716
7717 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7718 netdev->hw_features |= NETIF_F_LRO;
7719 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7720 netdev->features |= NETIF_F_LRO;
7721
7722 /* make sure the EEPROM is good */
7723 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7724 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7725 err = -EIO;
7726 goto err_sw_init;
7727 }
7728
7729 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7730
7731 if (!is_valid_ether_addr(netdev->dev_addr)) {
7732 e_dev_err("invalid MAC address\n");
7733 err = -EIO;
7734 goto err_sw_init;
7735 }
7736
7737 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7738 (unsigned long) adapter);
7739
7740 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7741 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7742
7743 err = ixgbe_init_interrupt_scheme(adapter);
7744 if (err)
7745 goto err_sw_init;
7746
7747 /* WOL not supported for all devices */
7748 adapter->wol = 0;
7749 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7750 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
7751 pdev->subsystem_device);
7752 if (hw->wol_enabled)
7753 adapter->wol = IXGBE_WUFC_MAG;
7754
7755 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7756
7757 /* save off EEPROM version number */
7758 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7759 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7760
7761 /* pick up the PCI bus settings for reporting later */
7762 hw->mac.ops.get_bus_info(hw);
7763 if (ixgbe_pcie_from_parent(hw))
7764 ixgbe_get_parent_bus_info(adapter);
7765
7766 /* print bus type/speed/width info */
7767 e_dev_info("(PCI Express:%s:%s) %pM\n",
7768 (hw->bus.speed == ixgbe_bus_speed_8000 ? "8.0GT/s" :
7769 hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7770 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7771 "Unknown"),
7772 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7773 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7774 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7775 "Unknown"),
7776 netdev->dev_addr);
7777
7778 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7779 if (err)
7780 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7781 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7782 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7783 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7784 part_str);
7785 else
7786 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7787 hw->mac.type, hw->phy.type, part_str);
7788
7789 /* calculate the expected PCIe bandwidth required for optimal
7790 * performance. Note that some older parts will never have enough
7791 * bandwidth due to being older generation PCIe parts. We clamp these
7792 * parts to ensure no warning is displayed if it can't be fixed.
7793 */
7794 switch (hw->mac.type) {
7795 case ixgbe_mac_82598EB:
7796 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
7797 break;
7798 default:
7799 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
7800 break;
7801 }
7802 ixgbe_check_minimum_link(adapter, expected_gts);
7803
7804 /* reset the hardware with the new settings */
7805 err = hw->mac.ops.start_hw(hw);
7806 if (err == IXGBE_ERR_EEPROM_VERSION) {
7807 /* We are running on a pre-production device, log a warning */
7808 e_dev_warn("This device is a pre-production adapter/LOM. "
7809 "Please be aware there may be issues associated "
7810 "with your hardware. If you are experiencing "
7811 "problems please contact your Intel or hardware "
7812 "representative who provided you with this "
7813 "hardware.\n");
7814 }
7815 strcpy(netdev->name, "eth%d");
7816 err = register_netdev(netdev);
7817 if (err)
7818 goto err_register;
7819
7820 /* power down the optics for 82599 SFP+ fiber */
7821 if (hw->mac.ops.disable_tx_laser)
7822 hw->mac.ops.disable_tx_laser(hw);
7823
7824 /* carrier off reporting is important to ethtool even BEFORE open */
7825 netif_carrier_off(netdev);
7826
7827 #ifdef CONFIG_IXGBE_DCA
7828 if (dca_add_requester(&pdev->dev) == 0) {
7829 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7830 ixgbe_setup_dca(adapter);
7831 }
7832 #endif
7833 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7834 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7835 for (i = 0; i < adapter->num_vfs; i++)
7836 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7837 }
7838
7839 /* firmware requires driver version to be 0xFFFFFFFF
7840 * since os does not support feature
7841 */
7842 if (hw->mac.ops.set_fw_drv_ver)
7843 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7844 0xFF);
7845
7846 /* add san mac addr to netdev */
7847 ixgbe_add_sanmac_netdev(netdev);
7848
7849 e_dev_info("%s\n", ixgbe_default_device_descr);
7850 cards_found++;
7851
7852 #ifdef CONFIG_IXGBE_HWMON
7853 if (ixgbe_sysfs_init(adapter))
7854 e_err(probe, "failed to allocate sysfs resources\n");
7855 #endif /* CONFIG_IXGBE_HWMON */
7856
7857 ixgbe_dbg_adapter_init(adapter);
7858
7859 /* Need link setup for MNG FW, else wait for IXGBE_UP */
7860 if (hw->mng_fw_enabled && hw->mac.ops.setup_link)
7861 hw->mac.ops.setup_link(hw,
7862 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
7863 true);
7864
7865 return 0;
7866
7867 err_register:
7868 ixgbe_release_hw_control(adapter);
7869 ixgbe_clear_interrupt_scheme(adapter);
7870 err_sw_init:
7871 ixgbe_disable_sriov(adapter);
7872 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7873 iounmap(hw->hw_addr);
7874 err_ioremap:
7875 free_netdev(netdev);
7876 err_alloc_etherdev:
7877 pci_release_selected_regions(pdev,
7878 pci_select_bars(pdev, IORESOURCE_MEM));
7879 err_pci_reg:
7880 err_dma:
7881 pci_disable_device(pdev);
7882 return err;
7883 }
7884
7885 /**
7886 * ixgbe_remove - Device Removal Routine
7887 * @pdev: PCI device information struct
7888 *
7889 * ixgbe_remove is called by the PCI subsystem to alert the driver
7890 * that it should release a PCI device. The could be caused by a
7891 * Hot-Plug event, or because the driver is going to be removed from
7892 * memory.
7893 **/
7894 static void ixgbe_remove(struct pci_dev *pdev)
7895 {
7896 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7897 struct net_device *netdev = adapter->netdev;
7898
7899 ixgbe_dbg_adapter_exit(adapter);
7900
7901 set_bit(__IXGBE_DOWN, &adapter->state);
7902 cancel_work_sync(&adapter->service_task);
7903
7904
7905 #ifdef CONFIG_IXGBE_DCA
7906 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7907 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7908 dca_remove_requester(&pdev->dev);
7909 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7910 }
7911
7912 #endif
7913 #ifdef CONFIG_IXGBE_HWMON
7914 ixgbe_sysfs_exit(adapter);
7915 #endif /* CONFIG_IXGBE_HWMON */
7916
7917 /* remove the added san mac */
7918 ixgbe_del_sanmac_netdev(netdev);
7919
7920 if (netdev->reg_state == NETREG_REGISTERED)
7921 unregister_netdev(netdev);
7922
7923 #ifdef CONFIG_PCI_IOV
7924 /*
7925 * Only disable SR-IOV on unload if the user specified the now
7926 * deprecated max_vfs module parameter.
7927 */
7928 if (max_vfs)
7929 ixgbe_disable_sriov(adapter);
7930 #endif
7931 ixgbe_clear_interrupt_scheme(adapter);
7932
7933 ixgbe_release_hw_control(adapter);
7934
7935 #ifdef CONFIG_DCB
7936 kfree(adapter->ixgbe_ieee_pfc);
7937 kfree(adapter->ixgbe_ieee_ets);
7938
7939 #endif
7940 iounmap(adapter->hw.hw_addr);
7941 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7942 IORESOURCE_MEM));
7943
7944 e_dev_info("complete\n");
7945
7946 free_netdev(netdev);
7947
7948 pci_disable_pcie_error_reporting(pdev);
7949
7950 pci_disable_device(pdev);
7951 }
7952
7953 /**
7954 * ixgbe_io_error_detected - called when PCI error is detected
7955 * @pdev: Pointer to PCI device
7956 * @state: The current pci connection state
7957 *
7958 * This function is called after a PCI bus error affecting
7959 * this device has been detected.
7960 */
7961 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7962 pci_channel_state_t state)
7963 {
7964 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7965 struct net_device *netdev = adapter->netdev;
7966
7967 #ifdef CONFIG_PCI_IOV
7968 struct pci_dev *bdev, *vfdev;
7969 u32 dw0, dw1, dw2, dw3;
7970 int vf, pos;
7971 u16 req_id, pf_func;
7972
7973 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7974 adapter->num_vfs == 0)
7975 goto skip_bad_vf_detection;
7976
7977 bdev = pdev->bus->self;
7978 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
7979 bdev = bdev->bus->self;
7980
7981 if (!bdev)
7982 goto skip_bad_vf_detection;
7983
7984 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7985 if (!pos)
7986 goto skip_bad_vf_detection;
7987
7988 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7989 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7990 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7991 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7992
7993 req_id = dw1 >> 16;
7994 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7995 if (!(req_id & 0x0080))
7996 goto skip_bad_vf_detection;
7997
7998 pf_func = req_id & 0x01;
7999 if ((pf_func & 1) == (pdev->devfn & 1)) {
8000 unsigned int device_id;
8001
8002 vf = (req_id & 0x7F) >> 1;
8003 e_dev_err("VF %d has caused a PCIe error\n", vf);
8004 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8005 "%8.8x\tdw3: %8.8x\n",
8006 dw0, dw1, dw2, dw3);
8007 switch (adapter->hw.mac.type) {
8008 case ixgbe_mac_82599EB:
8009 device_id = IXGBE_82599_VF_DEVICE_ID;
8010 break;
8011 case ixgbe_mac_X540:
8012 device_id = IXGBE_X540_VF_DEVICE_ID;
8013 break;
8014 default:
8015 device_id = 0;
8016 break;
8017 }
8018
8019 /* Find the pci device of the offending VF */
8020 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
8021 while (vfdev) {
8022 if (vfdev->devfn == (req_id & 0xFF))
8023 break;
8024 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
8025 device_id, vfdev);
8026 }
8027 /*
8028 * There's a slim chance the VF could have been hot plugged,
8029 * so if it is no longer present we don't need to issue the
8030 * VFLR. Just clean up the AER in that case.
8031 */
8032 if (vfdev) {
8033 e_dev_err("Issuing VFLR to VF %d\n", vf);
8034 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
8035 /* Free device reference count */
8036 pci_dev_put(vfdev);
8037 }
8038
8039 pci_cleanup_aer_uncorrect_error_status(pdev);
8040 }
8041
8042 /*
8043 * Even though the error may have occurred on the other port
8044 * we still need to increment the vf error reference count for
8045 * both ports because the I/O resume function will be called
8046 * for both of them.
8047 */
8048 adapter->vferr_refcount++;
8049
8050 return PCI_ERS_RESULT_RECOVERED;
8051
8052 skip_bad_vf_detection:
8053 #endif /* CONFIG_PCI_IOV */
8054 netif_device_detach(netdev);
8055
8056 if (state == pci_channel_io_perm_failure)
8057 return PCI_ERS_RESULT_DISCONNECT;
8058
8059 if (netif_running(netdev))
8060 ixgbe_down(adapter);
8061 pci_disable_device(pdev);
8062
8063 /* Request a slot reset. */
8064 return PCI_ERS_RESULT_NEED_RESET;
8065 }
8066
8067 /**
8068 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8069 * @pdev: Pointer to PCI device
8070 *
8071 * Restart the card from scratch, as if from a cold-boot.
8072 */
8073 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8074 {
8075 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8076 pci_ers_result_t result;
8077 int err;
8078
8079 if (pci_enable_device_mem(pdev)) {
8080 e_err(probe, "Cannot re-enable PCI device after reset.\n");
8081 result = PCI_ERS_RESULT_DISCONNECT;
8082 } else {
8083 pci_set_master(pdev);
8084 pci_restore_state(pdev);
8085 pci_save_state(pdev);
8086
8087 pci_wake_from_d3(pdev, false);
8088
8089 ixgbe_reset(adapter);
8090 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
8091 result = PCI_ERS_RESULT_RECOVERED;
8092 }
8093
8094 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8095 if (err) {
8096 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8097 "failed 0x%0x\n", err);
8098 /* non-fatal, continue */
8099 }
8100
8101 return result;
8102 }
8103
8104 /**
8105 * ixgbe_io_resume - called when traffic can start flowing again.
8106 * @pdev: Pointer to PCI device
8107 *
8108 * This callback is called when the error recovery driver tells us that
8109 * its OK to resume normal operation.
8110 */
8111 static void ixgbe_io_resume(struct pci_dev *pdev)
8112 {
8113 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8114 struct net_device *netdev = adapter->netdev;
8115
8116 #ifdef CONFIG_PCI_IOV
8117 if (adapter->vferr_refcount) {
8118 e_info(drv, "Resuming after VF err\n");
8119 adapter->vferr_refcount--;
8120 return;
8121 }
8122
8123 #endif
8124 if (netif_running(netdev))
8125 ixgbe_up(adapter);
8126
8127 netif_device_attach(netdev);
8128 }
8129
8130 static const struct pci_error_handlers ixgbe_err_handler = {
8131 .error_detected = ixgbe_io_error_detected,
8132 .slot_reset = ixgbe_io_slot_reset,
8133 .resume = ixgbe_io_resume,
8134 };
8135
8136 static struct pci_driver ixgbe_driver = {
8137 .name = ixgbe_driver_name,
8138 .id_table = ixgbe_pci_tbl,
8139 .probe = ixgbe_probe,
8140 .remove = ixgbe_remove,
8141 #ifdef CONFIG_PM
8142 .suspend = ixgbe_suspend,
8143 .resume = ixgbe_resume,
8144 #endif
8145 .shutdown = ixgbe_shutdown,
8146 .sriov_configure = ixgbe_pci_sriov_configure,
8147 .err_handler = &ixgbe_err_handler
8148 };
8149
8150 /**
8151 * ixgbe_init_module - Driver Registration Routine
8152 *
8153 * ixgbe_init_module is the first routine called when the driver is
8154 * loaded. All it does is register with the PCI subsystem.
8155 **/
8156 static int __init ixgbe_init_module(void)
8157 {
8158 int ret;
8159 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
8160 pr_info("%s\n", ixgbe_copyright);
8161
8162 ixgbe_dbg_init();
8163
8164 ret = pci_register_driver(&ixgbe_driver);
8165 if (ret) {
8166 ixgbe_dbg_exit();
8167 return ret;
8168 }
8169
8170 #ifdef CONFIG_IXGBE_DCA
8171 dca_register_notify(&dca_notifier);
8172 #endif
8173
8174 return 0;
8175 }
8176
8177 module_init(ixgbe_init_module);
8178
8179 /**
8180 * ixgbe_exit_module - Driver Exit Cleanup Routine
8181 *
8182 * ixgbe_exit_module is called just before the driver is removed
8183 * from memory.
8184 **/
8185 static void __exit ixgbe_exit_module(void)
8186 {
8187 #ifdef CONFIG_IXGBE_DCA
8188 dca_unregister_notify(&dca_notifier);
8189 #endif
8190 pci_unregister_driver(&ixgbe_driver);
8191
8192 ixgbe_dbg_exit();
8193
8194 rcu_barrier(); /* Wait for completion of call_rcu()'s */
8195 }
8196
8197 #ifdef CONFIG_IXGBE_DCA
8198 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
8199 void *p)
8200 {
8201 int ret_val;
8202
8203 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
8204 __ixgbe_notify_dca);
8205
8206 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8207 }
8208
8209 #endif /* CONFIG_IXGBE_DCA */
8210
8211 module_exit(ixgbe_exit_module);
8212
8213 /* ixgbe_main.c */
Linux kernel - Deliverables
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