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ixgbe: fix setting of TXDCTL.WTRHESH when ITR is set to 0 and no BQL
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2014 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/types.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/vmalloc.h>
34 #include <linux/string.h>
35 #include <linux/in.h>
36 #include <linux/interrupt.h>
37 #include <linux/ip.h>
38 #include <linux/tcp.h>
39 #include <linux/sctp.h>
40 #include <linux/pkt_sched.h>
41 #include <linux/ipv6.h>
42 #include <linux/slab.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/ethtool.h>
46 #include <linux/if.h>
47 #include <linux/if_vlan.h>
48 #include <linux/if_macvlan.h>
49 #include <linux/if_bridge.h>
50 #include <linux/prefetch.h>
51 #include <scsi/fc/fc_fcoe.h>
52
53 #include "ixgbe.h"
54 #include "ixgbe_common.h"
55 #include "ixgbe_dcb_82599.h"
56 #include "ixgbe_sriov.h"
57
58 char ixgbe_driver_name[] = "ixgbe";
59 static const char ixgbe_driver_string[] =
60 "Intel(R) 10 Gigabit PCI Express Network Driver";
61 #ifdef IXGBE_FCOE
62 char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
64 #else
65 static char ixgbe_default_device_descr[] =
66 "Intel(R) 10 Gigabit Network Connection";
67 #endif
68 #define DRV_VERSION "3.19.1-k"
69 const char ixgbe_driver_version[] = DRV_VERSION;
70 static const char ixgbe_copyright[] =
71 "Copyright (c) 1999-2014 Intel Corporation.";
72
73 static const struct ixgbe_info *ixgbe_info_tbl[] = {
74 [board_82598] = &ixgbe_82598_info,
75 [board_82599] = &ixgbe_82599_info,
76 [board_X540] = &ixgbe_X540_info,
77 };
78
79 /* ixgbe_pci_tbl - PCI Device ID Table
80 *
81 * Wildcard entries (PCI_ANY_ID) should come last
82 * Last entry must be all 0s
83 *
84 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
85 * Class, Class Mask, private data (not used) }
86 */
87 static const struct pci_device_id ixgbe_pci_tbl[] = {
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
118 /* required last entry */
119 {0, }
120 };
121 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
122
123 #ifdef CONFIG_IXGBE_DCA
124 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
125 void *p);
126 static struct notifier_block dca_notifier = {
127 .notifier_call = ixgbe_notify_dca,
128 .next = NULL,
129 .priority = 0
130 };
131 #endif
132
133 #ifdef CONFIG_PCI_IOV
134 static unsigned int max_vfs;
135 module_param(max_vfs, uint, 0);
136 MODULE_PARM_DESC(max_vfs,
137 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
138 #endif /* CONFIG_PCI_IOV */
139
140 static unsigned int allow_unsupported_sfp;
141 module_param(allow_unsupported_sfp, uint, 0);
142 MODULE_PARM_DESC(allow_unsupported_sfp,
143 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
144
145 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
146 static int debug = -1;
147 module_param(debug, int, 0);
148 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
149
150 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
151 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
152 MODULE_LICENSE("GPL");
153 MODULE_VERSION(DRV_VERSION);
154
155 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
156
157 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
158 u32 reg, u16 *value)
159 {
160 struct pci_dev *parent_dev;
161 struct pci_bus *parent_bus;
162
163 parent_bus = adapter->pdev->bus->parent;
164 if (!parent_bus)
165 return -1;
166
167 parent_dev = parent_bus->self;
168 if (!parent_dev)
169 return -1;
170
171 if (!pci_is_pcie(parent_dev))
172 return -1;
173
174 pcie_capability_read_word(parent_dev, reg, value);
175 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
176 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
177 return -1;
178 return 0;
179 }
180
181 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
182 {
183 struct ixgbe_hw *hw = &adapter->hw;
184 u16 link_status = 0;
185 int err;
186
187 hw->bus.type = ixgbe_bus_type_pci_express;
188
189 /* Get the negotiated link width and speed from PCI config space of the
190 * parent, as this device is behind a switch
191 */
192 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
193
194 /* assume caller will handle error case */
195 if (err)
196 return err;
197
198 hw->bus.width = ixgbe_convert_bus_width(link_status);
199 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
200
201 return 0;
202 }
203
204 /**
205 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
206 * @hw: hw specific details
207 *
208 * This function is used by probe to determine whether a device's PCI-Express
209 * bandwidth details should be gathered from the parent bus instead of from the
210 * device. Used to ensure that various locations all have the correct device ID
211 * checks.
212 */
213 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
214 {
215 switch (hw->device_id) {
216 case IXGBE_DEV_ID_82599_SFP_SF_QP:
217 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
218 return true;
219 default:
220 return false;
221 }
222 }
223
224 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
225 int expected_gts)
226 {
227 int max_gts = 0;
228 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
229 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
230 struct pci_dev *pdev;
231
232 /* determine whether to use the the parent device
233 */
234 if (ixgbe_pcie_from_parent(&adapter->hw))
235 pdev = adapter->pdev->bus->parent->self;
236 else
237 pdev = adapter->pdev;
238
239 if (pcie_get_minimum_link(pdev, &speed, &width) ||
240 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
241 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
242 return;
243 }
244
245 switch (speed) {
246 case PCIE_SPEED_2_5GT:
247 /* 8b/10b encoding reduces max throughput by 20% */
248 max_gts = 2 * width;
249 break;
250 case PCIE_SPEED_5_0GT:
251 /* 8b/10b encoding reduces max throughput by 20% */
252 max_gts = 4 * width;
253 break;
254 case PCIE_SPEED_8_0GT:
255 /* 128b/130b encoding reduces throughput by less than 2% */
256 max_gts = 8 * width;
257 break;
258 default:
259 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
260 return;
261 }
262
263 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
264 max_gts);
265 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
266 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
267 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
268 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
269 "Unknown"),
270 width,
271 (speed == PCIE_SPEED_2_5GT ? "20%" :
272 speed == PCIE_SPEED_5_0GT ? "20%" :
273 speed == PCIE_SPEED_8_0GT ? "<2%" :
274 "Unknown"));
275
276 if (max_gts < expected_gts) {
277 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
278 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
279 expected_gts);
280 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
281 }
282 }
283
284 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
285 {
286 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
287 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
288 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
289 schedule_work(&adapter->service_task);
290 }
291
292 static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
293 {
294 struct ixgbe_adapter *adapter = hw->back;
295
296 if (!hw->hw_addr)
297 return;
298 hw->hw_addr = NULL;
299 e_dev_err("Adapter removed\n");
300 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
301 ixgbe_service_event_schedule(adapter);
302 }
303
304 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
305 {
306 u32 value;
307
308 /* The following check not only optimizes a bit by not
309 * performing a read on the status register when the
310 * register just read was a status register read that
311 * returned IXGBE_FAILED_READ_REG. It also blocks any
312 * potential recursion.
313 */
314 if (reg == IXGBE_STATUS) {
315 ixgbe_remove_adapter(hw);
316 return;
317 }
318 value = ixgbe_read_reg(hw, IXGBE_STATUS);
319 if (value == IXGBE_FAILED_READ_REG)
320 ixgbe_remove_adapter(hw);
321 }
322
323 /**
324 * ixgbe_read_reg - Read from device register
325 * @hw: hw specific details
326 * @reg: offset of register to read
327 *
328 * Returns : value read or IXGBE_FAILED_READ_REG if removed
329 *
330 * This function is used to read device registers. It checks for device
331 * removal by confirming any read that returns all ones by checking the
332 * status register value for all ones. This function avoids reading from
333 * the hardware if a removal was previously detected in which case it
334 * returns IXGBE_FAILED_READ_REG (all ones).
335 */
336 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
337 {
338 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
339 u32 value;
340
341 if (ixgbe_removed(reg_addr))
342 return IXGBE_FAILED_READ_REG;
343 value = readl(reg_addr + reg);
344 if (unlikely(value == IXGBE_FAILED_READ_REG))
345 ixgbe_check_remove(hw, reg);
346 return value;
347 }
348
349 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
350 {
351 u16 value;
352
353 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
354 if (value == IXGBE_FAILED_READ_CFG_WORD) {
355 ixgbe_remove_adapter(hw);
356 return true;
357 }
358 return false;
359 }
360
361 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
362 {
363 struct ixgbe_adapter *adapter = hw->back;
364 u16 value;
365
366 if (ixgbe_removed(hw->hw_addr))
367 return IXGBE_FAILED_READ_CFG_WORD;
368 pci_read_config_word(adapter->pdev, reg, &value);
369 if (value == IXGBE_FAILED_READ_CFG_WORD &&
370 ixgbe_check_cfg_remove(hw, adapter->pdev))
371 return IXGBE_FAILED_READ_CFG_WORD;
372 return value;
373 }
374
375 #ifdef CONFIG_PCI_IOV
376 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
377 {
378 struct ixgbe_adapter *adapter = hw->back;
379 u32 value;
380
381 if (ixgbe_removed(hw->hw_addr))
382 return IXGBE_FAILED_READ_CFG_DWORD;
383 pci_read_config_dword(adapter->pdev, reg, &value);
384 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
385 ixgbe_check_cfg_remove(hw, adapter->pdev))
386 return IXGBE_FAILED_READ_CFG_DWORD;
387 return value;
388 }
389 #endif /* CONFIG_PCI_IOV */
390
391 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
392 {
393 struct ixgbe_adapter *adapter = hw->back;
394
395 if (ixgbe_removed(hw->hw_addr))
396 return;
397 pci_write_config_word(adapter->pdev, reg, value);
398 }
399
400 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
401 {
402 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
403
404 /* flush memory to make sure state is correct before next watchdog */
405 smp_mb__before_atomic();
406 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
407 }
408
409 struct ixgbe_reg_info {
410 u32 ofs;
411 char *name;
412 };
413
414 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
415
416 /* General Registers */
417 {IXGBE_CTRL, "CTRL"},
418 {IXGBE_STATUS, "STATUS"},
419 {IXGBE_CTRL_EXT, "CTRL_EXT"},
420
421 /* Interrupt Registers */
422 {IXGBE_EICR, "EICR"},
423
424 /* RX Registers */
425 {IXGBE_SRRCTL(0), "SRRCTL"},
426 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
427 {IXGBE_RDLEN(0), "RDLEN"},
428 {IXGBE_RDH(0), "RDH"},
429 {IXGBE_RDT(0), "RDT"},
430 {IXGBE_RXDCTL(0), "RXDCTL"},
431 {IXGBE_RDBAL(0), "RDBAL"},
432 {IXGBE_RDBAH(0), "RDBAH"},
433
434 /* TX Registers */
435 {IXGBE_TDBAL(0), "TDBAL"},
436 {IXGBE_TDBAH(0), "TDBAH"},
437 {IXGBE_TDLEN(0), "TDLEN"},
438 {IXGBE_TDH(0), "TDH"},
439 {IXGBE_TDT(0), "TDT"},
440 {IXGBE_TXDCTL(0), "TXDCTL"},
441
442 /* List Terminator */
443 { .name = NULL }
444 };
445
446
447 /*
448 * ixgbe_regdump - register printout routine
449 */
450 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
451 {
452 int i = 0, j = 0;
453 char rname[16];
454 u32 regs[64];
455
456 switch (reginfo->ofs) {
457 case IXGBE_SRRCTL(0):
458 for (i = 0; i < 64; i++)
459 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
460 break;
461 case IXGBE_DCA_RXCTRL(0):
462 for (i = 0; i < 64; i++)
463 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
464 break;
465 case IXGBE_RDLEN(0):
466 for (i = 0; i < 64; i++)
467 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
468 break;
469 case IXGBE_RDH(0):
470 for (i = 0; i < 64; i++)
471 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
472 break;
473 case IXGBE_RDT(0):
474 for (i = 0; i < 64; i++)
475 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
476 break;
477 case IXGBE_RXDCTL(0):
478 for (i = 0; i < 64; i++)
479 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
480 break;
481 case IXGBE_RDBAL(0):
482 for (i = 0; i < 64; i++)
483 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
484 break;
485 case IXGBE_RDBAH(0):
486 for (i = 0; i < 64; i++)
487 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
488 break;
489 case IXGBE_TDBAL(0):
490 for (i = 0; i < 64; i++)
491 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
492 break;
493 case IXGBE_TDBAH(0):
494 for (i = 0; i < 64; i++)
495 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
496 break;
497 case IXGBE_TDLEN(0):
498 for (i = 0; i < 64; i++)
499 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
500 break;
501 case IXGBE_TDH(0):
502 for (i = 0; i < 64; i++)
503 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
504 break;
505 case IXGBE_TDT(0):
506 for (i = 0; i < 64; i++)
507 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
508 break;
509 case IXGBE_TXDCTL(0):
510 for (i = 0; i < 64; i++)
511 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
512 break;
513 default:
514 pr_info("%-15s %08x\n", reginfo->name,
515 IXGBE_READ_REG(hw, reginfo->ofs));
516 return;
517 }
518
519 for (i = 0; i < 8; i++) {
520 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
521 pr_err("%-15s", rname);
522 for (j = 0; j < 8; j++)
523 pr_cont(" %08x", regs[i*8+j]);
524 pr_cont("\n");
525 }
526
527 }
528
529 /*
530 * ixgbe_dump - Print registers, tx-rings and rx-rings
531 */
532 static void ixgbe_dump(struct ixgbe_adapter *adapter)
533 {
534 struct net_device *netdev = adapter->netdev;
535 struct ixgbe_hw *hw = &adapter->hw;
536 struct ixgbe_reg_info *reginfo;
537 int n = 0;
538 struct ixgbe_ring *tx_ring;
539 struct ixgbe_tx_buffer *tx_buffer;
540 union ixgbe_adv_tx_desc *tx_desc;
541 struct my_u0 { u64 a; u64 b; } *u0;
542 struct ixgbe_ring *rx_ring;
543 union ixgbe_adv_rx_desc *rx_desc;
544 struct ixgbe_rx_buffer *rx_buffer_info;
545 u32 staterr;
546 int i = 0;
547
548 if (!netif_msg_hw(adapter))
549 return;
550
551 /* Print netdevice Info */
552 if (netdev) {
553 dev_info(&adapter->pdev->dev, "Net device Info\n");
554 pr_info("Device Name state "
555 "trans_start last_rx\n");
556 pr_info("%-15s %016lX %016lX %016lX\n",
557 netdev->name,
558 netdev->state,
559 netdev->trans_start,
560 netdev->last_rx);
561 }
562
563 /* Print Registers */
564 dev_info(&adapter->pdev->dev, "Register Dump\n");
565 pr_info(" Register Name Value\n");
566 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
567 reginfo->name; reginfo++) {
568 ixgbe_regdump(hw, reginfo);
569 }
570
571 /* Print TX Ring Summary */
572 if (!netdev || !netif_running(netdev))
573 return;
574
575 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
576 pr_info(" %s %s %s %s\n",
577 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
578 "leng", "ntw", "timestamp");
579 for (n = 0; n < adapter->num_tx_queues; n++) {
580 tx_ring = adapter->tx_ring[n];
581 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
582 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
583 n, tx_ring->next_to_use, tx_ring->next_to_clean,
584 (u64)dma_unmap_addr(tx_buffer, dma),
585 dma_unmap_len(tx_buffer, len),
586 tx_buffer->next_to_watch,
587 (u64)tx_buffer->time_stamp);
588 }
589
590 /* Print TX Rings */
591 if (!netif_msg_tx_done(adapter))
592 goto rx_ring_summary;
593
594 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
595
596 /* Transmit Descriptor Formats
597 *
598 * 82598 Advanced Transmit Descriptor
599 * +--------------------------------------------------------------+
600 * 0 | Buffer Address [63:0] |
601 * +--------------------------------------------------------------+
602 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
603 * +--------------------------------------------------------------+
604 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
605 *
606 * 82598 Advanced Transmit Descriptor (Write-Back Format)
607 * +--------------------------------------------------------------+
608 * 0 | RSV [63:0] |
609 * +--------------------------------------------------------------+
610 * 8 | RSV | STA | NXTSEQ |
611 * +--------------------------------------------------------------+
612 * 63 36 35 32 31 0
613 *
614 * 82599+ Advanced Transmit Descriptor
615 * +--------------------------------------------------------------+
616 * 0 | Buffer Address [63:0] |
617 * +--------------------------------------------------------------+
618 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
619 * +--------------------------------------------------------------+
620 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
621 *
622 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
623 * +--------------------------------------------------------------+
624 * 0 | RSV [63:0] |
625 * +--------------------------------------------------------------+
626 * 8 | RSV | STA | RSV |
627 * +--------------------------------------------------------------+
628 * 63 36 35 32 31 0
629 */
630
631 for (n = 0; n < adapter->num_tx_queues; n++) {
632 tx_ring = adapter->tx_ring[n];
633 pr_info("------------------------------------\n");
634 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
635 pr_info("------------------------------------\n");
636 pr_info("%s%s %s %s %s %s\n",
637 "T [desc] [address 63:0 ] ",
638 "[PlPOIdStDDt Ln] [bi->dma ] ",
639 "leng", "ntw", "timestamp", "bi->skb");
640
641 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
642 tx_desc = IXGBE_TX_DESC(tx_ring, i);
643 tx_buffer = &tx_ring->tx_buffer_info[i];
644 u0 = (struct my_u0 *)tx_desc;
645 if (dma_unmap_len(tx_buffer, len) > 0) {
646 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
647 i,
648 le64_to_cpu(u0->a),
649 le64_to_cpu(u0->b),
650 (u64)dma_unmap_addr(tx_buffer, dma),
651 dma_unmap_len(tx_buffer, len),
652 tx_buffer->next_to_watch,
653 (u64)tx_buffer->time_stamp,
654 tx_buffer->skb);
655 if (i == tx_ring->next_to_use &&
656 i == tx_ring->next_to_clean)
657 pr_cont(" NTC/U\n");
658 else if (i == tx_ring->next_to_use)
659 pr_cont(" NTU\n");
660 else if (i == tx_ring->next_to_clean)
661 pr_cont(" NTC\n");
662 else
663 pr_cont("\n");
664
665 if (netif_msg_pktdata(adapter) &&
666 tx_buffer->skb)
667 print_hex_dump(KERN_INFO, "",
668 DUMP_PREFIX_ADDRESS, 16, 1,
669 tx_buffer->skb->data,
670 dma_unmap_len(tx_buffer, len),
671 true);
672 }
673 }
674 }
675
676 /* Print RX Rings Summary */
677 rx_ring_summary:
678 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
679 pr_info("Queue [NTU] [NTC]\n");
680 for (n = 0; n < adapter->num_rx_queues; n++) {
681 rx_ring = adapter->rx_ring[n];
682 pr_info("%5d %5X %5X\n",
683 n, rx_ring->next_to_use, rx_ring->next_to_clean);
684 }
685
686 /* Print RX Rings */
687 if (!netif_msg_rx_status(adapter))
688 return;
689
690 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
691
692 /* Receive Descriptor Formats
693 *
694 * 82598 Advanced Receive Descriptor (Read) Format
695 * 63 1 0
696 * +-----------------------------------------------------+
697 * 0 | Packet Buffer Address [63:1] |A0/NSE|
698 * +----------------------------------------------+------+
699 * 8 | Header Buffer Address [63:1] | DD |
700 * +-----------------------------------------------------+
701 *
702 *
703 * 82598 Advanced Receive Descriptor (Write-Back) Format
704 *
705 * 63 48 47 32 31 30 21 20 16 15 4 3 0
706 * +------------------------------------------------------+
707 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
708 * | Packet | IP | | | | Type | Type |
709 * | Checksum | Ident | | | | | |
710 * +------------------------------------------------------+
711 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
712 * +------------------------------------------------------+
713 * 63 48 47 32 31 20 19 0
714 *
715 * 82599+ Advanced Receive Descriptor (Read) Format
716 * 63 1 0
717 * +-----------------------------------------------------+
718 * 0 | Packet Buffer Address [63:1] |A0/NSE|
719 * +----------------------------------------------+------+
720 * 8 | Header Buffer Address [63:1] | DD |
721 * +-----------------------------------------------------+
722 *
723 *
724 * 82599+ Advanced Receive Descriptor (Write-Back) Format
725 *
726 * 63 48 47 32 31 30 21 20 17 16 4 3 0
727 * +------------------------------------------------------+
728 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
729 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
730 * |/ Flow Dir Flt ID | | | | | |
731 * +------------------------------------------------------+
732 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
733 * +------------------------------------------------------+
734 * 63 48 47 32 31 20 19 0
735 */
736
737 for (n = 0; n < adapter->num_rx_queues; n++) {
738 rx_ring = adapter->rx_ring[n];
739 pr_info("------------------------------------\n");
740 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
741 pr_info("------------------------------------\n");
742 pr_info("%s%s%s",
743 "R [desc] [ PktBuf A0] ",
744 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
745 "<-- Adv Rx Read format\n");
746 pr_info("%s%s%s",
747 "RWB[desc] [PcsmIpSHl PtRs] ",
748 "[vl er S cks ln] ---------------- [bi->skb ] ",
749 "<-- Adv Rx Write-Back format\n");
750
751 for (i = 0; i < rx_ring->count; i++) {
752 rx_buffer_info = &rx_ring->rx_buffer_info[i];
753 rx_desc = IXGBE_RX_DESC(rx_ring, i);
754 u0 = (struct my_u0 *)rx_desc;
755 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
756 if (staterr & IXGBE_RXD_STAT_DD) {
757 /* Descriptor Done */
758 pr_info("RWB[0x%03X] %016llX "
759 "%016llX ---------------- %p", i,
760 le64_to_cpu(u0->a),
761 le64_to_cpu(u0->b),
762 rx_buffer_info->skb);
763 } else {
764 pr_info("R [0x%03X] %016llX "
765 "%016llX %016llX %p", i,
766 le64_to_cpu(u0->a),
767 le64_to_cpu(u0->b),
768 (u64)rx_buffer_info->dma,
769 rx_buffer_info->skb);
770
771 if (netif_msg_pktdata(adapter) &&
772 rx_buffer_info->dma) {
773 print_hex_dump(KERN_INFO, "",
774 DUMP_PREFIX_ADDRESS, 16, 1,
775 page_address(rx_buffer_info->page) +
776 rx_buffer_info->page_offset,
777 ixgbe_rx_bufsz(rx_ring), true);
778 }
779 }
780
781 if (i == rx_ring->next_to_use)
782 pr_cont(" NTU\n");
783 else if (i == rx_ring->next_to_clean)
784 pr_cont(" NTC\n");
785 else
786 pr_cont("\n");
787
788 }
789 }
790 }
791
792 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
793 {
794 u32 ctrl_ext;
795
796 /* Let firmware take over control of h/w */
797 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
798 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
799 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
800 }
801
802 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
803 {
804 u32 ctrl_ext;
805
806 /* Let firmware know the driver has taken over */
807 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
808 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
809 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
810 }
811
812 /**
813 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
814 * @adapter: pointer to adapter struct
815 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
816 * @queue: queue to map the corresponding interrupt to
817 * @msix_vector: the vector to map to the corresponding queue
818 *
819 */
820 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
821 u8 queue, u8 msix_vector)
822 {
823 u32 ivar, index;
824 struct ixgbe_hw *hw = &adapter->hw;
825 switch (hw->mac.type) {
826 case ixgbe_mac_82598EB:
827 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
828 if (direction == -1)
829 direction = 0;
830 index = (((direction * 64) + queue) >> 2) & 0x1F;
831 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
832 ivar &= ~(0xFF << (8 * (queue & 0x3)));
833 ivar |= (msix_vector << (8 * (queue & 0x3)));
834 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
835 break;
836 case ixgbe_mac_82599EB:
837 case ixgbe_mac_X540:
838 if (direction == -1) {
839 /* other causes */
840 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
841 index = ((queue & 1) * 8);
842 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
843 ivar &= ~(0xFF << index);
844 ivar |= (msix_vector << index);
845 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
846 break;
847 } else {
848 /* tx or rx causes */
849 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
850 index = ((16 * (queue & 1)) + (8 * direction));
851 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
852 ivar &= ~(0xFF << index);
853 ivar |= (msix_vector << index);
854 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
855 break;
856 }
857 default:
858 break;
859 }
860 }
861
862 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
863 u64 qmask)
864 {
865 u32 mask;
866
867 switch (adapter->hw.mac.type) {
868 case ixgbe_mac_82598EB:
869 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
870 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
871 break;
872 case ixgbe_mac_82599EB:
873 case ixgbe_mac_X540:
874 mask = (qmask & 0xFFFFFFFF);
875 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
876 mask = (qmask >> 32);
877 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
878 break;
879 default:
880 break;
881 }
882 }
883
884 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
885 struct ixgbe_tx_buffer *tx_buffer)
886 {
887 if (tx_buffer->skb) {
888 dev_kfree_skb_any(tx_buffer->skb);
889 if (dma_unmap_len(tx_buffer, len))
890 dma_unmap_single(ring->dev,
891 dma_unmap_addr(tx_buffer, dma),
892 dma_unmap_len(tx_buffer, len),
893 DMA_TO_DEVICE);
894 } else if (dma_unmap_len(tx_buffer, len)) {
895 dma_unmap_page(ring->dev,
896 dma_unmap_addr(tx_buffer, dma),
897 dma_unmap_len(tx_buffer, len),
898 DMA_TO_DEVICE);
899 }
900 tx_buffer->next_to_watch = NULL;
901 tx_buffer->skb = NULL;
902 dma_unmap_len_set(tx_buffer, len, 0);
903 /* tx_buffer must be completely set up in the transmit path */
904 }
905
906 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
907 {
908 struct ixgbe_hw *hw = &adapter->hw;
909 struct ixgbe_hw_stats *hwstats = &adapter->stats;
910 int i;
911 u32 data;
912
913 if ((hw->fc.current_mode != ixgbe_fc_full) &&
914 (hw->fc.current_mode != ixgbe_fc_rx_pause))
915 return;
916
917 switch (hw->mac.type) {
918 case ixgbe_mac_82598EB:
919 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
920 break;
921 default:
922 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
923 }
924 hwstats->lxoffrxc += data;
925
926 /* refill credits (no tx hang) if we received xoff */
927 if (!data)
928 return;
929
930 for (i = 0; i < adapter->num_tx_queues; i++)
931 clear_bit(__IXGBE_HANG_CHECK_ARMED,
932 &adapter->tx_ring[i]->state);
933 }
934
935 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
936 {
937 struct ixgbe_hw *hw = &adapter->hw;
938 struct ixgbe_hw_stats *hwstats = &adapter->stats;
939 u32 xoff[8] = {0};
940 u8 tc;
941 int i;
942 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
943
944 if (adapter->ixgbe_ieee_pfc)
945 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
946
947 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
948 ixgbe_update_xoff_rx_lfc(adapter);
949 return;
950 }
951
952 /* update stats for each tc, only valid with PFC enabled */
953 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
954 u32 pxoffrxc;
955
956 switch (hw->mac.type) {
957 case ixgbe_mac_82598EB:
958 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
959 break;
960 default:
961 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
962 }
963 hwstats->pxoffrxc[i] += pxoffrxc;
964 /* Get the TC for given UP */
965 tc = netdev_get_prio_tc_map(adapter->netdev, i);
966 xoff[tc] += pxoffrxc;
967 }
968
969 /* disarm tx queues that have received xoff frames */
970 for (i = 0; i < adapter->num_tx_queues; i++) {
971 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
972
973 tc = tx_ring->dcb_tc;
974 if (xoff[tc])
975 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
976 }
977 }
978
979 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
980 {
981 return ring->stats.packets;
982 }
983
984 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
985 {
986 struct ixgbe_adapter *adapter;
987 struct ixgbe_hw *hw;
988 u32 head, tail;
989
990 if (ring->l2_accel_priv)
991 adapter = ring->l2_accel_priv->real_adapter;
992 else
993 adapter = netdev_priv(ring->netdev);
994
995 hw = &adapter->hw;
996 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
997 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
998
999 if (head != tail)
1000 return (head < tail) ?
1001 tail - head : (tail + ring->count - head);
1002
1003 return 0;
1004 }
1005
1006 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1007 {
1008 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1009 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1010 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1011
1012 clear_check_for_tx_hang(tx_ring);
1013
1014 /*
1015 * Check for a hung queue, but be thorough. This verifies
1016 * that a transmit has been completed since the previous
1017 * check AND there is at least one packet pending. The
1018 * ARMED bit is set to indicate a potential hang. The
1019 * bit is cleared if a pause frame is received to remove
1020 * false hang detection due to PFC or 802.3x frames. By
1021 * requiring this to fail twice we avoid races with
1022 * pfc clearing the ARMED bit and conditions where we
1023 * run the check_tx_hang logic with a transmit completion
1024 * pending but without time to complete it yet.
1025 */
1026 if (tx_done_old == tx_done && tx_pending)
1027 /* make sure it is true for two checks in a row */
1028 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1029 &tx_ring->state);
1030 /* update completed stats and continue */
1031 tx_ring->tx_stats.tx_done_old = tx_done;
1032 /* reset the countdown */
1033 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1034
1035 return false;
1036 }
1037
1038 /**
1039 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1040 * @adapter: driver private struct
1041 **/
1042 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1043 {
1044
1045 /* Do the reset outside of interrupt context */
1046 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1047 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
1048 e_warn(drv, "initiating reset due to tx timeout\n");
1049 ixgbe_service_event_schedule(adapter);
1050 }
1051 }
1052
1053 /**
1054 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
1055 * @q_vector: structure containing interrupt and ring information
1056 * @tx_ring: tx ring to clean
1057 **/
1058 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
1059 struct ixgbe_ring *tx_ring)
1060 {
1061 struct ixgbe_adapter *adapter = q_vector->adapter;
1062 struct ixgbe_tx_buffer *tx_buffer;
1063 union ixgbe_adv_tx_desc *tx_desc;
1064 unsigned int total_bytes = 0, total_packets = 0;
1065 unsigned int budget = q_vector->tx.work_limit;
1066 unsigned int i = tx_ring->next_to_clean;
1067
1068 if (test_bit(__IXGBE_DOWN, &adapter->state))
1069 return true;
1070
1071 tx_buffer = &tx_ring->tx_buffer_info[i];
1072 tx_desc = IXGBE_TX_DESC(tx_ring, i);
1073 i -= tx_ring->count;
1074
1075 do {
1076 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1077
1078 /* if next_to_watch is not set then there is no work pending */
1079 if (!eop_desc)
1080 break;
1081
1082 /* prevent any other reads prior to eop_desc */
1083 read_barrier_depends();
1084
1085 /* if DD is not set pending work has not been completed */
1086 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1087 break;
1088
1089 /* clear next_to_watch to prevent false hangs */
1090 tx_buffer->next_to_watch = NULL;
1091
1092 /* update the statistics for this packet */
1093 total_bytes += tx_buffer->bytecount;
1094 total_packets += tx_buffer->gso_segs;
1095
1096 /* free the skb */
1097 dev_consume_skb_any(tx_buffer->skb);
1098
1099 /* unmap skb header data */
1100 dma_unmap_single(tx_ring->dev,
1101 dma_unmap_addr(tx_buffer, dma),
1102 dma_unmap_len(tx_buffer, len),
1103 DMA_TO_DEVICE);
1104
1105 /* clear tx_buffer data */
1106 tx_buffer->skb = NULL;
1107 dma_unmap_len_set(tx_buffer, len, 0);
1108
1109 /* unmap remaining buffers */
1110 while (tx_desc != eop_desc) {
1111 tx_buffer++;
1112 tx_desc++;
1113 i++;
1114 if (unlikely(!i)) {
1115 i -= tx_ring->count;
1116 tx_buffer = tx_ring->tx_buffer_info;
1117 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1118 }
1119
1120 /* unmap any remaining paged data */
1121 if (dma_unmap_len(tx_buffer, len)) {
1122 dma_unmap_page(tx_ring->dev,
1123 dma_unmap_addr(tx_buffer, dma),
1124 dma_unmap_len(tx_buffer, len),
1125 DMA_TO_DEVICE);
1126 dma_unmap_len_set(tx_buffer, len, 0);
1127 }
1128 }
1129
1130 /* move us one more past the eop_desc for start of next pkt */
1131 tx_buffer++;
1132 tx_desc++;
1133 i++;
1134 if (unlikely(!i)) {
1135 i -= tx_ring->count;
1136 tx_buffer = tx_ring->tx_buffer_info;
1137 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1138 }
1139
1140 /* issue prefetch for next Tx descriptor */
1141 prefetch(tx_desc);
1142
1143 /* update budget accounting */
1144 budget--;
1145 } while (likely(budget));
1146
1147 i += tx_ring->count;
1148 tx_ring->next_to_clean = i;
1149 u64_stats_update_begin(&tx_ring->syncp);
1150 tx_ring->stats.bytes += total_bytes;
1151 tx_ring->stats.packets += total_packets;
1152 u64_stats_update_end(&tx_ring->syncp);
1153 q_vector->tx.total_bytes += total_bytes;
1154 q_vector->tx.total_packets += total_packets;
1155
1156 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1157 /* schedule immediate reset if we believe we hung */
1158 struct ixgbe_hw *hw = &adapter->hw;
1159 e_err(drv, "Detected Tx Unit Hang\n"
1160 " Tx Queue <%d>\n"
1161 " TDH, TDT <%x>, <%x>\n"
1162 " next_to_use <%x>\n"
1163 " next_to_clean <%x>\n"
1164 "tx_buffer_info[next_to_clean]\n"
1165 " time_stamp <%lx>\n"
1166 " jiffies <%lx>\n",
1167 tx_ring->queue_index,
1168 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1169 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1170 tx_ring->next_to_use, i,
1171 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1172
1173 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1174
1175 e_info(probe,
1176 "tx hang %d detected on queue %d, resetting adapter\n",
1177 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1178
1179 /* schedule immediate reset if we believe we hung */
1180 ixgbe_tx_timeout_reset(adapter);
1181
1182 /* the adapter is about to reset, no point in enabling stuff */
1183 return true;
1184 }
1185
1186 netdev_tx_completed_queue(txring_txq(tx_ring),
1187 total_packets, total_bytes);
1188
1189 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1190 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1191 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1192 /* Make sure that anybody stopping the queue after this
1193 * sees the new next_to_clean.
1194 */
1195 smp_mb();
1196 if (__netif_subqueue_stopped(tx_ring->netdev,
1197 tx_ring->queue_index)
1198 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1199 netif_wake_subqueue(tx_ring->netdev,
1200 tx_ring->queue_index);
1201 ++tx_ring->tx_stats.restart_queue;
1202 }
1203 }
1204
1205 return !!budget;
1206 }
1207
1208 #ifdef CONFIG_IXGBE_DCA
1209 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1210 struct ixgbe_ring *tx_ring,
1211 int cpu)
1212 {
1213 struct ixgbe_hw *hw = &adapter->hw;
1214 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1215 u16 reg_offset;
1216
1217 switch (hw->mac.type) {
1218 case ixgbe_mac_82598EB:
1219 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1220 break;
1221 case ixgbe_mac_82599EB:
1222 case ixgbe_mac_X540:
1223 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1224 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1225 break;
1226 default:
1227 /* for unknown hardware do not write register */
1228 return;
1229 }
1230
1231 /*
1232 * We can enable relaxed ordering for reads, but not writes when
1233 * DCA is enabled. This is due to a known issue in some chipsets
1234 * which will cause the DCA tag to be cleared.
1235 */
1236 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1237 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1238 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1239
1240 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1241 }
1242
1243 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1244 struct ixgbe_ring *rx_ring,
1245 int cpu)
1246 {
1247 struct ixgbe_hw *hw = &adapter->hw;
1248 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1249 u8 reg_idx = rx_ring->reg_idx;
1250
1251
1252 switch (hw->mac.type) {
1253 case ixgbe_mac_82599EB:
1254 case ixgbe_mac_X540:
1255 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1256 break;
1257 default:
1258 break;
1259 }
1260
1261 /*
1262 * We can enable relaxed ordering for reads, but not writes when
1263 * DCA is enabled. This is due to a known issue in some chipsets
1264 * which will cause the DCA tag to be cleared.
1265 */
1266 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1267 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1268
1269 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1270 }
1271
1272 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1273 {
1274 struct ixgbe_adapter *adapter = q_vector->adapter;
1275 struct ixgbe_ring *ring;
1276 int cpu = get_cpu();
1277
1278 if (q_vector->cpu == cpu)
1279 goto out_no_update;
1280
1281 ixgbe_for_each_ring(ring, q_vector->tx)
1282 ixgbe_update_tx_dca(adapter, ring, cpu);
1283
1284 ixgbe_for_each_ring(ring, q_vector->rx)
1285 ixgbe_update_rx_dca(adapter, ring, cpu);
1286
1287 q_vector->cpu = cpu;
1288 out_no_update:
1289 put_cpu();
1290 }
1291
1292 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1293 {
1294 int i;
1295
1296 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1297 return;
1298
1299 /* always use CB2 mode, difference is masked in the CB driver */
1300 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1301
1302 for (i = 0; i < adapter->num_q_vectors; i++) {
1303 adapter->q_vector[i]->cpu = -1;
1304 ixgbe_update_dca(adapter->q_vector[i]);
1305 }
1306 }
1307
1308 static int __ixgbe_notify_dca(struct device *dev, void *data)
1309 {
1310 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1311 unsigned long event = *(unsigned long *)data;
1312
1313 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1314 return 0;
1315
1316 switch (event) {
1317 case DCA_PROVIDER_ADD:
1318 /* if we're already enabled, don't do it again */
1319 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1320 break;
1321 if (dca_add_requester(dev) == 0) {
1322 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1323 ixgbe_setup_dca(adapter);
1324 break;
1325 }
1326 /* Fall Through since DCA is disabled. */
1327 case DCA_PROVIDER_REMOVE:
1328 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1329 dca_remove_requester(dev);
1330 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1331 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1332 }
1333 break;
1334 }
1335
1336 return 0;
1337 }
1338
1339 #endif /* CONFIG_IXGBE_DCA */
1340 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1341 union ixgbe_adv_rx_desc *rx_desc,
1342 struct sk_buff *skb)
1343 {
1344 if (ring->netdev->features & NETIF_F_RXHASH)
1345 skb_set_hash(skb,
1346 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1347 PKT_HASH_TYPE_L3);
1348 }
1349
1350 #ifdef IXGBE_FCOE
1351 /**
1352 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1353 * @ring: structure containing ring specific data
1354 * @rx_desc: advanced rx descriptor
1355 *
1356 * Returns : true if it is FCoE pkt
1357 */
1358 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1359 union ixgbe_adv_rx_desc *rx_desc)
1360 {
1361 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1362
1363 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1364 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1365 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1366 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1367 }
1368
1369 #endif /* IXGBE_FCOE */
1370 /**
1371 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1372 * @ring: structure containing ring specific data
1373 * @rx_desc: current Rx descriptor being processed
1374 * @skb: skb currently being received and modified
1375 **/
1376 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1377 union ixgbe_adv_rx_desc *rx_desc,
1378 struct sk_buff *skb)
1379 {
1380 skb_checksum_none_assert(skb);
1381
1382 /* Rx csum disabled */
1383 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1384 return;
1385
1386 /* if IP and error */
1387 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1388 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1389 ring->rx_stats.csum_err++;
1390 return;
1391 }
1392
1393 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1394 return;
1395
1396 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1397 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1398
1399 /*
1400 * 82599 errata, UDP frames with a 0 checksum can be marked as
1401 * checksum errors.
1402 */
1403 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1404 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1405 return;
1406
1407 ring->rx_stats.csum_err++;
1408 return;
1409 }
1410
1411 /* It must be a TCP or UDP packet with a valid checksum */
1412 skb->ip_summed = CHECKSUM_UNNECESSARY;
1413 }
1414
1415 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1416 {
1417 rx_ring->next_to_use = val;
1418
1419 /* update next to alloc since we have filled the ring */
1420 rx_ring->next_to_alloc = val;
1421 /*
1422 * Force memory writes to complete before letting h/w
1423 * know there are new descriptors to fetch. (Only
1424 * applicable for weak-ordered memory model archs,
1425 * such as IA-64).
1426 */
1427 wmb();
1428 ixgbe_write_tail(rx_ring, val);
1429 }
1430
1431 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1432 struct ixgbe_rx_buffer *bi)
1433 {
1434 struct page *page = bi->page;
1435 dma_addr_t dma = bi->dma;
1436
1437 /* since we are recycling buffers we should seldom need to alloc */
1438 if (likely(dma))
1439 return true;
1440
1441 /* alloc new page for storage */
1442 if (likely(!page)) {
1443 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1444 bi->skb, ixgbe_rx_pg_order(rx_ring));
1445 if (unlikely(!page)) {
1446 rx_ring->rx_stats.alloc_rx_page_failed++;
1447 return false;
1448 }
1449 bi->page = page;
1450 }
1451
1452 /* map page for use */
1453 dma = dma_map_page(rx_ring->dev, page, 0,
1454 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1455
1456 /*
1457 * if mapping failed free memory back to system since
1458 * there isn't much point in holding memory we can't use
1459 */
1460 if (dma_mapping_error(rx_ring->dev, dma)) {
1461 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1462 bi->page = NULL;
1463
1464 rx_ring->rx_stats.alloc_rx_page_failed++;
1465 return false;
1466 }
1467
1468 bi->dma = dma;
1469 bi->page_offset = 0;
1470
1471 return true;
1472 }
1473
1474 /**
1475 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1476 * @rx_ring: ring to place buffers on
1477 * @cleaned_count: number of buffers to replace
1478 **/
1479 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1480 {
1481 union ixgbe_adv_rx_desc *rx_desc;
1482 struct ixgbe_rx_buffer *bi;
1483 u16 i = rx_ring->next_to_use;
1484
1485 /* nothing to do */
1486 if (!cleaned_count)
1487 return;
1488
1489 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1490 bi = &rx_ring->rx_buffer_info[i];
1491 i -= rx_ring->count;
1492
1493 do {
1494 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1495 break;
1496
1497 /*
1498 * Refresh the desc even if buffer_addrs didn't change
1499 * because each write-back erases this info.
1500 */
1501 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1502
1503 rx_desc++;
1504 bi++;
1505 i++;
1506 if (unlikely(!i)) {
1507 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1508 bi = rx_ring->rx_buffer_info;
1509 i -= rx_ring->count;
1510 }
1511
1512 /* clear the hdr_addr for the next_to_use descriptor */
1513 rx_desc->read.hdr_addr = 0;
1514
1515 cleaned_count--;
1516 } while (cleaned_count);
1517
1518 i += rx_ring->count;
1519
1520 if (rx_ring->next_to_use != i)
1521 ixgbe_release_rx_desc(rx_ring, i);
1522 }
1523
1524 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1525 struct sk_buff *skb)
1526 {
1527 u16 hdr_len = skb_headlen(skb);
1528
1529 /* set gso_size to avoid messing up TCP MSS */
1530 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1531 IXGBE_CB(skb)->append_cnt);
1532 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1533 }
1534
1535 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1536 struct sk_buff *skb)
1537 {
1538 /* if append_cnt is 0 then frame is not RSC */
1539 if (!IXGBE_CB(skb)->append_cnt)
1540 return;
1541
1542 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1543 rx_ring->rx_stats.rsc_flush++;
1544
1545 ixgbe_set_rsc_gso_size(rx_ring, skb);
1546
1547 /* gso_size is computed using append_cnt so always clear it last */
1548 IXGBE_CB(skb)->append_cnt = 0;
1549 }
1550
1551 /**
1552 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1553 * @rx_ring: rx descriptor ring packet is being transacted on
1554 * @rx_desc: pointer to the EOP Rx descriptor
1555 * @skb: pointer to current skb being populated
1556 *
1557 * This function checks the ring, descriptor, and packet information in
1558 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1559 * other fields within the skb.
1560 **/
1561 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1562 union ixgbe_adv_rx_desc *rx_desc,
1563 struct sk_buff *skb)
1564 {
1565 struct net_device *dev = rx_ring->netdev;
1566
1567 ixgbe_update_rsc_stats(rx_ring, skb);
1568
1569 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1570
1571 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1572
1573 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1574 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
1575
1576 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1577 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1578 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1579 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1580 }
1581
1582 skb_record_rx_queue(skb, rx_ring->queue_index);
1583
1584 skb->protocol = eth_type_trans(skb, dev);
1585 }
1586
1587 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1588 struct sk_buff *skb)
1589 {
1590 struct ixgbe_adapter *adapter = q_vector->adapter;
1591
1592 if (ixgbe_qv_busy_polling(q_vector))
1593 netif_receive_skb(skb);
1594 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1595 napi_gro_receive(&q_vector->napi, skb);
1596 else
1597 netif_rx(skb);
1598 }
1599
1600 /**
1601 * ixgbe_is_non_eop - process handling of non-EOP buffers
1602 * @rx_ring: Rx ring being processed
1603 * @rx_desc: Rx descriptor for current buffer
1604 * @skb: Current socket buffer containing buffer in progress
1605 *
1606 * This function updates next to clean. If the buffer is an EOP buffer
1607 * this function exits returning false, otherwise it will place the
1608 * sk_buff in the next buffer to be chained and return true indicating
1609 * that this is in fact a non-EOP buffer.
1610 **/
1611 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1612 union ixgbe_adv_rx_desc *rx_desc,
1613 struct sk_buff *skb)
1614 {
1615 u32 ntc = rx_ring->next_to_clean + 1;
1616
1617 /* fetch, update, and store next to clean */
1618 ntc = (ntc < rx_ring->count) ? ntc : 0;
1619 rx_ring->next_to_clean = ntc;
1620
1621 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1622
1623 /* update RSC append count if present */
1624 if (ring_is_rsc_enabled(rx_ring)) {
1625 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1626 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1627
1628 if (unlikely(rsc_enabled)) {
1629 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1630
1631 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1632 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1633
1634 /* update ntc based on RSC value */
1635 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1636 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1637 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1638 }
1639 }
1640
1641 /* if we are the last buffer then there is nothing else to do */
1642 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1643 return false;
1644
1645 /* place skb in next buffer to be received */
1646 rx_ring->rx_buffer_info[ntc].skb = skb;
1647 rx_ring->rx_stats.non_eop_descs++;
1648
1649 return true;
1650 }
1651
1652 /**
1653 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1654 * @rx_ring: rx descriptor ring packet is being transacted on
1655 * @skb: pointer to current skb being adjusted
1656 *
1657 * This function is an ixgbe specific version of __pskb_pull_tail. The
1658 * main difference between this version and the original function is that
1659 * this function can make several assumptions about the state of things
1660 * that allow for significant optimizations versus the standard function.
1661 * As a result we can do things like drop a frag and maintain an accurate
1662 * truesize for the skb.
1663 */
1664 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1665 struct sk_buff *skb)
1666 {
1667 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1668 unsigned char *va;
1669 unsigned int pull_len;
1670
1671 /*
1672 * it is valid to use page_address instead of kmap since we are
1673 * working with pages allocated out of the lomem pool per
1674 * alloc_page(GFP_ATOMIC)
1675 */
1676 va = skb_frag_address(frag);
1677
1678 /*
1679 * we need the header to contain the greater of either ETH_HLEN or
1680 * 60 bytes if the skb->len is less than 60 for skb_pad.
1681 */
1682 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
1683
1684 /* align pull length to size of long to optimize memcpy performance */
1685 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1686
1687 /* update all of the pointers */
1688 skb_frag_size_sub(frag, pull_len);
1689 frag->page_offset += pull_len;
1690 skb->data_len -= pull_len;
1691 skb->tail += pull_len;
1692 }
1693
1694 /**
1695 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1696 * @rx_ring: rx descriptor ring packet is being transacted on
1697 * @skb: pointer to current skb being updated
1698 *
1699 * This function provides a basic DMA sync up for the first fragment of an
1700 * skb. The reason for doing this is that the first fragment cannot be
1701 * unmapped until we have reached the end of packet descriptor for a buffer
1702 * chain.
1703 */
1704 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1705 struct sk_buff *skb)
1706 {
1707 /* if the page was released unmap it, else just sync our portion */
1708 if (unlikely(IXGBE_CB(skb)->page_released)) {
1709 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1710 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1711 IXGBE_CB(skb)->page_released = false;
1712 } else {
1713 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1714
1715 dma_sync_single_range_for_cpu(rx_ring->dev,
1716 IXGBE_CB(skb)->dma,
1717 frag->page_offset,
1718 ixgbe_rx_bufsz(rx_ring),
1719 DMA_FROM_DEVICE);
1720 }
1721 IXGBE_CB(skb)->dma = 0;
1722 }
1723
1724 /**
1725 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1726 * @rx_ring: rx descriptor ring packet is being transacted on
1727 * @rx_desc: pointer to the EOP Rx descriptor
1728 * @skb: pointer to current skb being fixed
1729 *
1730 * Check for corrupted packet headers caused by senders on the local L2
1731 * embedded NIC switch not setting up their Tx Descriptors right. These
1732 * should be very rare.
1733 *
1734 * Also address the case where we are pulling data in on pages only
1735 * and as such no data is present in the skb header.
1736 *
1737 * In addition if skb is not at least 60 bytes we need to pad it so that
1738 * it is large enough to qualify as a valid Ethernet frame.
1739 *
1740 * Returns true if an error was encountered and skb was freed.
1741 **/
1742 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1743 union ixgbe_adv_rx_desc *rx_desc,
1744 struct sk_buff *skb)
1745 {
1746 struct net_device *netdev = rx_ring->netdev;
1747
1748 /* verify that the packet does not have any known errors */
1749 if (unlikely(ixgbe_test_staterr(rx_desc,
1750 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1751 !(netdev->features & NETIF_F_RXALL))) {
1752 dev_kfree_skb_any(skb);
1753 return true;
1754 }
1755
1756 /* place header in linear portion of buffer */
1757 if (skb_is_nonlinear(skb))
1758 ixgbe_pull_tail(rx_ring, skb);
1759
1760 #ifdef IXGBE_FCOE
1761 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1762 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1763 return false;
1764
1765 #endif
1766 /* if skb_pad returns an error the skb was freed */
1767 if (unlikely(skb->len < 60)) {
1768 int pad_len = 60 - skb->len;
1769
1770 if (skb_pad(skb, pad_len))
1771 return true;
1772 __skb_put(skb, pad_len);
1773 }
1774
1775 return false;
1776 }
1777
1778 /**
1779 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1780 * @rx_ring: rx descriptor ring to store buffers on
1781 * @old_buff: donor buffer to have page reused
1782 *
1783 * Synchronizes page for reuse by the adapter
1784 **/
1785 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1786 struct ixgbe_rx_buffer *old_buff)
1787 {
1788 struct ixgbe_rx_buffer *new_buff;
1789 u16 nta = rx_ring->next_to_alloc;
1790
1791 new_buff = &rx_ring->rx_buffer_info[nta];
1792
1793 /* update, and store next to alloc */
1794 nta++;
1795 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1796
1797 /* transfer page from old buffer to new buffer */
1798 new_buff->page = old_buff->page;
1799 new_buff->dma = old_buff->dma;
1800 new_buff->page_offset = old_buff->page_offset;
1801
1802 /* sync the buffer for use by the device */
1803 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1804 new_buff->page_offset,
1805 ixgbe_rx_bufsz(rx_ring),
1806 DMA_FROM_DEVICE);
1807 }
1808
1809 /**
1810 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1811 * @rx_ring: rx descriptor ring to transact packets on
1812 * @rx_buffer: buffer containing page to add
1813 * @rx_desc: descriptor containing length of buffer written by hardware
1814 * @skb: sk_buff to place the data into
1815 *
1816 * This function will add the data contained in rx_buffer->page to the skb.
1817 * This is done either through a direct copy if the data in the buffer is
1818 * less than the skb header size, otherwise it will just attach the page as
1819 * a frag to the skb.
1820 *
1821 * The function will then update the page offset if necessary and return
1822 * true if the buffer can be reused by the adapter.
1823 **/
1824 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1825 struct ixgbe_rx_buffer *rx_buffer,
1826 union ixgbe_adv_rx_desc *rx_desc,
1827 struct sk_buff *skb)
1828 {
1829 struct page *page = rx_buffer->page;
1830 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1831 #if (PAGE_SIZE < 8192)
1832 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1833 #else
1834 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1835 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1836 ixgbe_rx_bufsz(rx_ring);
1837 #endif
1838
1839 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1840 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1841
1842 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1843
1844 /* we can reuse buffer as-is, just make sure it is local */
1845 if (likely(page_to_nid(page) == numa_node_id()))
1846 return true;
1847
1848 /* this page cannot be reused so discard it */
1849 put_page(page);
1850 return false;
1851 }
1852
1853 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1854 rx_buffer->page_offset, size, truesize);
1855
1856 /* avoid re-using remote pages */
1857 if (unlikely(page_to_nid(page) != numa_node_id()))
1858 return false;
1859
1860 #if (PAGE_SIZE < 8192)
1861 /* if we are only owner of page we can reuse it */
1862 if (unlikely(page_count(page) != 1))
1863 return false;
1864
1865 /* flip page offset to other buffer */
1866 rx_buffer->page_offset ^= truesize;
1867
1868 /*
1869 * since we are the only owner of the page and we need to
1870 * increment it, just set the value to 2 in order to avoid
1871 * an unecessary locked operation
1872 */
1873 atomic_set(&page->_count, 2);
1874 #else
1875 /* move offset up to the next cache line */
1876 rx_buffer->page_offset += truesize;
1877
1878 if (rx_buffer->page_offset > last_offset)
1879 return false;
1880
1881 /* bump ref count on page before it is given to the stack */
1882 get_page(page);
1883 #endif
1884
1885 return true;
1886 }
1887
1888 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1889 union ixgbe_adv_rx_desc *rx_desc)
1890 {
1891 struct ixgbe_rx_buffer *rx_buffer;
1892 struct sk_buff *skb;
1893 struct page *page;
1894
1895 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1896 page = rx_buffer->page;
1897 prefetchw(page);
1898
1899 skb = rx_buffer->skb;
1900
1901 if (likely(!skb)) {
1902 void *page_addr = page_address(page) +
1903 rx_buffer->page_offset;
1904
1905 /* prefetch first cache line of first page */
1906 prefetch(page_addr);
1907 #if L1_CACHE_BYTES < 128
1908 prefetch(page_addr + L1_CACHE_BYTES);
1909 #endif
1910
1911 /* allocate a skb to store the frags */
1912 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1913 IXGBE_RX_HDR_SIZE);
1914 if (unlikely(!skb)) {
1915 rx_ring->rx_stats.alloc_rx_buff_failed++;
1916 return NULL;
1917 }
1918
1919 /*
1920 * we will be copying header into skb->data in
1921 * pskb_may_pull so it is in our interest to prefetch
1922 * it now to avoid a possible cache miss
1923 */
1924 prefetchw(skb->data);
1925
1926 /*
1927 * Delay unmapping of the first packet. It carries the
1928 * header information, HW may still access the header
1929 * after the writeback. Only unmap it when EOP is
1930 * reached
1931 */
1932 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1933 goto dma_sync;
1934
1935 IXGBE_CB(skb)->dma = rx_buffer->dma;
1936 } else {
1937 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1938 ixgbe_dma_sync_frag(rx_ring, skb);
1939
1940 dma_sync:
1941 /* we are reusing so sync this buffer for CPU use */
1942 dma_sync_single_range_for_cpu(rx_ring->dev,
1943 rx_buffer->dma,
1944 rx_buffer->page_offset,
1945 ixgbe_rx_bufsz(rx_ring),
1946 DMA_FROM_DEVICE);
1947 }
1948
1949 /* pull page into skb */
1950 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1951 /* hand second half of page back to the ring */
1952 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1953 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1954 /* the page has been released from the ring */
1955 IXGBE_CB(skb)->page_released = true;
1956 } else {
1957 /* we are not reusing the buffer so unmap it */
1958 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1959 ixgbe_rx_pg_size(rx_ring),
1960 DMA_FROM_DEVICE);
1961 }
1962
1963 /* clear contents of buffer_info */
1964 rx_buffer->skb = NULL;
1965 rx_buffer->dma = 0;
1966 rx_buffer->page = NULL;
1967
1968 return skb;
1969 }
1970
1971 /**
1972 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1973 * @q_vector: structure containing interrupt and ring information
1974 * @rx_ring: rx descriptor ring to transact packets on
1975 * @budget: Total limit on number of packets to process
1976 *
1977 * This function provides a "bounce buffer" approach to Rx interrupt
1978 * processing. The advantage to this is that on systems that have
1979 * expensive overhead for IOMMU access this provides a means of avoiding
1980 * it by maintaining the mapping of the page to the syste.
1981 *
1982 * Returns amount of work completed
1983 **/
1984 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1985 struct ixgbe_ring *rx_ring,
1986 const int budget)
1987 {
1988 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1989 #ifdef IXGBE_FCOE
1990 struct ixgbe_adapter *adapter = q_vector->adapter;
1991 int ddp_bytes;
1992 unsigned int mss = 0;
1993 #endif /* IXGBE_FCOE */
1994 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1995
1996 while (likely(total_rx_packets < budget)) {
1997 union ixgbe_adv_rx_desc *rx_desc;
1998 struct sk_buff *skb;
1999
2000 /* return some buffers to hardware, one at a time is too slow */
2001 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2002 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2003 cleaned_count = 0;
2004 }
2005
2006 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2007
2008 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2009 break;
2010
2011 /*
2012 * This memory barrier is needed to keep us from reading
2013 * any other fields out of the rx_desc until we know the
2014 * RXD_STAT_DD bit is set
2015 */
2016 rmb();
2017
2018 /* retrieve a buffer from the ring */
2019 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
2020
2021 /* exit if we failed to retrieve a buffer */
2022 if (!skb)
2023 break;
2024
2025 cleaned_count++;
2026
2027 /* place incomplete frames back on ring for completion */
2028 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2029 continue;
2030
2031 /* verify the packet layout is correct */
2032 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2033 continue;
2034
2035 /* probably a little skewed due to removing CRC */
2036 total_rx_bytes += skb->len;
2037
2038 /* populate checksum, timestamp, VLAN, and protocol */
2039 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2040
2041 #ifdef IXGBE_FCOE
2042 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2043 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2044 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2045 /* include DDPed FCoE data */
2046 if (ddp_bytes > 0) {
2047 if (!mss) {
2048 mss = rx_ring->netdev->mtu -
2049 sizeof(struct fcoe_hdr) -
2050 sizeof(struct fc_frame_header) -
2051 sizeof(struct fcoe_crc_eof);
2052 if (mss > 512)
2053 mss &= ~511;
2054 }
2055 total_rx_bytes += ddp_bytes;
2056 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2057 mss);
2058 }
2059 if (!ddp_bytes) {
2060 dev_kfree_skb_any(skb);
2061 continue;
2062 }
2063 }
2064
2065 #endif /* IXGBE_FCOE */
2066 skb_mark_napi_id(skb, &q_vector->napi);
2067 ixgbe_rx_skb(q_vector, skb);
2068
2069 /* update budget accounting */
2070 total_rx_packets++;
2071 }
2072
2073 u64_stats_update_begin(&rx_ring->syncp);
2074 rx_ring->stats.packets += total_rx_packets;
2075 rx_ring->stats.bytes += total_rx_bytes;
2076 u64_stats_update_end(&rx_ring->syncp);
2077 q_vector->rx.total_packets += total_rx_packets;
2078 q_vector->rx.total_bytes += total_rx_bytes;
2079
2080 return total_rx_packets;
2081 }
2082
2083 #ifdef CONFIG_NET_RX_BUSY_POLL
2084 /* must be called with local_bh_disable()d */
2085 static int ixgbe_low_latency_recv(struct napi_struct *napi)
2086 {
2087 struct ixgbe_q_vector *q_vector =
2088 container_of(napi, struct ixgbe_q_vector, napi);
2089 struct ixgbe_adapter *adapter = q_vector->adapter;
2090 struct ixgbe_ring *ring;
2091 int found = 0;
2092
2093 if (test_bit(__IXGBE_DOWN, &adapter->state))
2094 return LL_FLUSH_FAILED;
2095
2096 if (!ixgbe_qv_lock_poll(q_vector))
2097 return LL_FLUSH_BUSY;
2098
2099 ixgbe_for_each_ring(ring, q_vector->rx) {
2100 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
2101 #ifdef BP_EXTENDED_STATS
2102 if (found)
2103 ring->stats.cleaned += found;
2104 else
2105 ring->stats.misses++;
2106 #endif
2107 if (found)
2108 break;
2109 }
2110
2111 ixgbe_qv_unlock_poll(q_vector);
2112
2113 return found;
2114 }
2115 #endif /* CONFIG_NET_RX_BUSY_POLL */
2116
2117 /**
2118 * ixgbe_configure_msix - Configure MSI-X hardware
2119 * @adapter: board private structure
2120 *
2121 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2122 * interrupts.
2123 **/
2124 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2125 {
2126 struct ixgbe_q_vector *q_vector;
2127 int v_idx;
2128 u32 mask;
2129
2130 /* Populate MSIX to EITR Select */
2131 if (adapter->num_vfs > 32) {
2132 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2133 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2134 }
2135
2136 /*
2137 * Populate the IVAR table and set the ITR values to the
2138 * corresponding register.
2139 */
2140 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2141 struct ixgbe_ring *ring;
2142 q_vector = adapter->q_vector[v_idx];
2143
2144 ixgbe_for_each_ring(ring, q_vector->rx)
2145 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2146
2147 ixgbe_for_each_ring(ring, q_vector->tx)
2148 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2149
2150 ixgbe_write_eitr(q_vector);
2151 }
2152
2153 switch (adapter->hw.mac.type) {
2154 case ixgbe_mac_82598EB:
2155 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2156 v_idx);
2157 break;
2158 case ixgbe_mac_82599EB:
2159 case ixgbe_mac_X540:
2160 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2161 break;
2162 default:
2163 break;
2164 }
2165 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2166
2167 /* set up to autoclear timer, and the vectors */
2168 mask = IXGBE_EIMS_ENABLE_MASK;
2169 mask &= ~(IXGBE_EIMS_OTHER |
2170 IXGBE_EIMS_MAILBOX |
2171 IXGBE_EIMS_LSC);
2172
2173 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2174 }
2175
2176 enum latency_range {
2177 lowest_latency = 0,
2178 low_latency = 1,
2179 bulk_latency = 2,
2180 latency_invalid = 255
2181 };
2182
2183 /**
2184 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2185 * @q_vector: structure containing interrupt and ring information
2186 * @ring_container: structure containing ring performance data
2187 *
2188 * Stores a new ITR value based on packets and byte
2189 * counts during the last interrupt. The advantage of per interrupt
2190 * computation is faster updates and more accurate ITR for the current
2191 * traffic pattern. Constants in this function were computed
2192 * based on theoretical maximum wire speed and thresholds were set based
2193 * on testing data as well as attempting to minimize response time
2194 * while increasing bulk throughput.
2195 * this functionality is controlled by the InterruptThrottleRate module
2196 * parameter (see ixgbe_param.c)
2197 **/
2198 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2199 struct ixgbe_ring_container *ring_container)
2200 {
2201 int bytes = ring_container->total_bytes;
2202 int packets = ring_container->total_packets;
2203 u32 timepassed_us;
2204 u64 bytes_perint;
2205 u8 itr_setting = ring_container->itr;
2206
2207 if (packets == 0)
2208 return;
2209
2210 /* simple throttlerate management
2211 * 0-10MB/s lowest (100000 ints/s)
2212 * 10-20MB/s low (20000 ints/s)
2213 * 20-1249MB/s bulk (8000 ints/s)
2214 */
2215 /* what was last interrupt timeslice? */
2216 timepassed_us = q_vector->itr >> 2;
2217 if (timepassed_us == 0)
2218 return;
2219
2220 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2221
2222 switch (itr_setting) {
2223 case lowest_latency:
2224 if (bytes_perint > 10)
2225 itr_setting = low_latency;
2226 break;
2227 case low_latency:
2228 if (bytes_perint > 20)
2229 itr_setting = bulk_latency;
2230 else if (bytes_perint <= 10)
2231 itr_setting = lowest_latency;
2232 break;
2233 case bulk_latency:
2234 if (bytes_perint <= 20)
2235 itr_setting = low_latency;
2236 break;
2237 }
2238
2239 /* clear work counters since we have the values we need */
2240 ring_container->total_bytes = 0;
2241 ring_container->total_packets = 0;
2242
2243 /* write updated itr to ring container */
2244 ring_container->itr = itr_setting;
2245 }
2246
2247 /**
2248 * ixgbe_write_eitr - write EITR register in hardware specific way
2249 * @q_vector: structure containing interrupt and ring information
2250 *
2251 * This function is made to be called by ethtool and by the driver
2252 * when it needs to update EITR registers at runtime. Hardware
2253 * specific quirks/differences are taken care of here.
2254 */
2255 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2256 {
2257 struct ixgbe_adapter *adapter = q_vector->adapter;
2258 struct ixgbe_hw *hw = &adapter->hw;
2259 int v_idx = q_vector->v_idx;
2260 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2261
2262 switch (adapter->hw.mac.type) {
2263 case ixgbe_mac_82598EB:
2264 /* must write high and low 16 bits to reset counter */
2265 itr_reg |= (itr_reg << 16);
2266 break;
2267 case ixgbe_mac_82599EB:
2268 case ixgbe_mac_X540:
2269 /*
2270 * set the WDIS bit to not clear the timer bits and cause an
2271 * immediate assertion of the interrupt
2272 */
2273 itr_reg |= IXGBE_EITR_CNT_WDIS;
2274 break;
2275 default:
2276 break;
2277 }
2278 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2279 }
2280
2281 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2282 {
2283 u32 new_itr = q_vector->itr;
2284 u8 current_itr;
2285
2286 ixgbe_update_itr(q_vector, &q_vector->tx);
2287 ixgbe_update_itr(q_vector, &q_vector->rx);
2288
2289 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2290
2291 switch (current_itr) {
2292 /* counts and packets in update_itr are dependent on these numbers */
2293 case lowest_latency:
2294 new_itr = IXGBE_100K_ITR;
2295 break;
2296 case low_latency:
2297 new_itr = IXGBE_20K_ITR;
2298 break;
2299 case bulk_latency:
2300 new_itr = IXGBE_8K_ITR;
2301 break;
2302 default:
2303 break;
2304 }
2305
2306 if (new_itr != q_vector->itr) {
2307 /* do an exponential smoothing */
2308 new_itr = (10 * new_itr * q_vector->itr) /
2309 ((9 * new_itr) + q_vector->itr);
2310
2311 /* save the algorithm value here */
2312 q_vector->itr = new_itr;
2313
2314 ixgbe_write_eitr(q_vector);
2315 }
2316 }
2317
2318 /**
2319 * ixgbe_check_overtemp_subtask - check for over temperature
2320 * @adapter: pointer to adapter
2321 **/
2322 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2323 {
2324 struct ixgbe_hw *hw = &adapter->hw;
2325 u32 eicr = adapter->interrupt_event;
2326
2327 if (test_bit(__IXGBE_DOWN, &adapter->state))
2328 return;
2329
2330 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2331 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2332 return;
2333
2334 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2335
2336 switch (hw->device_id) {
2337 case IXGBE_DEV_ID_82599_T3_LOM:
2338 /*
2339 * Since the warning interrupt is for both ports
2340 * we don't have to check if:
2341 * - This interrupt wasn't for our port.
2342 * - We may have missed the interrupt so always have to
2343 * check if we got a LSC
2344 */
2345 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2346 !(eicr & IXGBE_EICR_LSC))
2347 return;
2348
2349 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2350 u32 speed;
2351 bool link_up = false;
2352
2353 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2354
2355 if (link_up)
2356 return;
2357 }
2358
2359 /* Check if this is not due to overtemp */
2360 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2361 return;
2362
2363 break;
2364 default:
2365 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2366 return;
2367 break;
2368 }
2369 e_crit(drv,
2370 "Network adapter has been stopped because it has over heated. "
2371 "Restart the computer. If the problem persists, "
2372 "power off the system and replace the adapter\n");
2373
2374 adapter->interrupt_event = 0;
2375 }
2376
2377 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2378 {
2379 struct ixgbe_hw *hw = &adapter->hw;
2380
2381 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2382 (eicr & IXGBE_EICR_GPI_SDP1)) {
2383 e_crit(probe, "Fan has stopped, replace the adapter\n");
2384 /* write to clear the interrupt */
2385 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2386 }
2387 }
2388
2389 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2390 {
2391 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2392 return;
2393
2394 switch (adapter->hw.mac.type) {
2395 case ixgbe_mac_82599EB:
2396 /*
2397 * Need to check link state so complete overtemp check
2398 * on service task
2399 */
2400 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2401 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2402 adapter->interrupt_event = eicr;
2403 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2404 ixgbe_service_event_schedule(adapter);
2405 return;
2406 }
2407 return;
2408 case ixgbe_mac_X540:
2409 if (!(eicr & IXGBE_EICR_TS))
2410 return;
2411 break;
2412 default:
2413 return;
2414 }
2415
2416 e_crit(drv,
2417 "Network adapter has been stopped because it has over heated. "
2418 "Restart the computer. If the problem persists, "
2419 "power off the system and replace the adapter\n");
2420 }
2421
2422 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2423 {
2424 struct ixgbe_hw *hw = &adapter->hw;
2425
2426 if (eicr & IXGBE_EICR_GPI_SDP2) {
2427 /* Clear the interrupt */
2428 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2429 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2430 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2431 ixgbe_service_event_schedule(adapter);
2432 }
2433 }
2434
2435 if (eicr & IXGBE_EICR_GPI_SDP1) {
2436 /* Clear the interrupt */
2437 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2438 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2439 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2440 ixgbe_service_event_schedule(adapter);
2441 }
2442 }
2443 }
2444
2445 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2446 {
2447 struct ixgbe_hw *hw = &adapter->hw;
2448
2449 adapter->lsc_int++;
2450 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2451 adapter->link_check_timeout = jiffies;
2452 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2453 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2454 IXGBE_WRITE_FLUSH(hw);
2455 ixgbe_service_event_schedule(adapter);
2456 }
2457 }
2458
2459 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2460 u64 qmask)
2461 {
2462 u32 mask;
2463 struct ixgbe_hw *hw = &adapter->hw;
2464
2465 switch (hw->mac.type) {
2466 case ixgbe_mac_82598EB:
2467 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2468 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2469 break;
2470 case ixgbe_mac_82599EB:
2471 case ixgbe_mac_X540:
2472 mask = (qmask & 0xFFFFFFFF);
2473 if (mask)
2474 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2475 mask = (qmask >> 32);
2476 if (mask)
2477 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2478 break;
2479 default:
2480 break;
2481 }
2482 /* skip the flush */
2483 }
2484
2485 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2486 u64 qmask)
2487 {
2488 u32 mask;
2489 struct ixgbe_hw *hw = &adapter->hw;
2490
2491 switch (hw->mac.type) {
2492 case ixgbe_mac_82598EB:
2493 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2494 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2495 break;
2496 case ixgbe_mac_82599EB:
2497 case ixgbe_mac_X540:
2498 mask = (qmask & 0xFFFFFFFF);
2499 if (mask)
2500 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2501 mask = (qmask >> 32);
2502 if (mask)
2503 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2504 break;
2505 default:
2506 break;
2507 }
2508 /* skip the flush */
2509 }
2510
2511 /**
2512 * ixgbe_irq_enable - Enable default interrupt generation settings
2513 * @adapter: board private structure
2514 **/
2515 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2516 bool flush)
2517 {
2518 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2519
2520 /* don't reenable LSC while waiting for link */
2521 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2522 mask &= ~IXGBE_EIMS_LSC;
2523
2524 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2525 switch (adapter->hw.mac.type) {
2526 case ixgbe_mac_82599EB:
2527 mask |= IXGBE_EIMS_GPI_SDP0;
2528 break;
2529 case ixgbe_mac_X540:
2530 mask |= IXGBE_EIMS_TS;
2531 break;
2532 default:
2533 break;
2534 }
2535 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2536 mask |= IXGBE_EIMS_GPI_SDP1;
2537 switch (adapter->hw.mac.type) {
2538 case ixgbe_mac_82599EB:
2539 mask |= IXGBE_EIMS_GPI_SDP1;
2540 mask |= IXGBE_EIMS_GPI_SDP2;
2541 case ixgbe_mac_X540:
2542 mask |= IXGBE_EIMS_ECC;
2543 mask |= IXGBE_EIMS_MAILBOX;
2544 break;
2545 default:
2546 break;
2547 }
2548
2549 if (adapter->hw.mac.type == ixgbe_mac_X540)
2550 mask |= IXGBE_EIMS_TIMESYNC;
2551
2552 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2553 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2554 mask |= IXGBE_EIMS_FLOW_DIR;
2555
2556 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2557 if (queues)
2558 ixgbe_irq_enable_queues(adapter, ~0);
2559 if (flush)
2560 IXGBE_WRITE_FLUSH(&adapter->hw);
2561 }
2562
2563 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2564 {
2565 struct ixgbe_adapter *adapter = data;
2566 struct ixgbe_hw *hw = &adapter->hw;
2567 u32 eicr;
2568
2569 /*
2570 * Workaround for Silicon errata. Use clear-by-write instead
2571 * of clear-by-read. Reading with EICS will return the
2572 * interrupt causes without clearing, which later be done
2573 * with the write to EICR.
2574 */
2575 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2576
2577 /* The lower 16bits of the EICR register are for the queue interrupts
2578 * which should be masked here in order to not accidently clear them if
2579 * the bits are high when ixgbe_msix_other is called. There is a race
2580 * condition otherwise which results in possible performance loss
2581 * especially if the ixgbe_msix_other interrupt is triggering
2582 * consistently (as it would when PPS is turned on for the X540 device)
2583 */
2584 eicr &= 0xFFFF0000;
2585
2586 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2587
2588 if (eicr & IXGBE_EICR_LSC)
2589 ixgbe_check_lsc(adapter);
2590
2591 if (eicr & IXGBE_EICR_MAILBOX)
2592 ixgbe_msg_task(adapter);
2593
2594 switch (hw->mac.type) {
2595 case ixgbe_mac_82599EB:
2596 case ixgbe_mac_X540:
2597 if (eicr & IXGBE_EICR_ECC) {
2598 e_info(link, "Received ECC Err, initiating reset\n");
2599 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2600 ixgbe_service_event_schedule(adapter);
2601 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2602 }
2603 /* Handle Flow Director Full threshold interrupt */
2604 if (eicr & IXGBE_EICR_FLOW_DIR) {
2605 int reinit_count = 0;
2606 int i;
2607 for (i = 0; i < adapter->num_tx_queues; i++) {
2608 struct ixgbe_ring *ring = adapter->tx_ring[i];
2609 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2610 &ring->state))
2611 reinit_count++;
2612 }
2613 if (reinit_count) {
2614 /* no more flow director interrupts until after init */
2615 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2616 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2617 ixgbe_service_event_schedule(adapter);
2618 }
2619 }
2620 ixgbe_check_sfp_event(adapter, eicr);
2621 ixgbe_check_overtemp_event(adapter, eicr);
2622 break;
2623 default:
2624 break;
2625 }
2626
2627 ixgbe_check_fan_failure(adapter, eicr);
2628
2629 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2630 ixgbe_ptp_check_pps_event(adapter, eicr);
2631
2632 /* re-enable the original interrupt state, no lsc, no queues */
2633 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2634 ixgbe_irq_enable(adapter, false, false);
2635
2636 return IRQ_HANDLED;
2637 }
2638
2639 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2640 {
2641 struct ixgbe_q_vector *q_vector = data;
2642
2643 /* EIAM disabled interrupts (on this vector) for us */
2644
2645 if (q_vector->rx.ring || q_vector->tx.ring)
2646 napi_schedule(&q_vector->napi);
2647
2648 return IRQ_HANDLED;
2649 }
2650
2651 /**
2652 * ixgbe_poll - NAPI Rx polling callback
2653 * @napi: structure for representing this polling device
2654 * @budget: how many packets driver is allowed to clean
2655 *
2656 * This function is used for legacy and MSI, NAPI mode
2657 **/
2658 int ixgbe_poll(struct napi_struct *napi, int budget)
2659 {
2660 struct ixgbe_q_vector *q_vector =
2661 container_of(napi, struct ixgbe_q_vector, napi);
2662 struct ixgbe_adapter *adapter = q_vector->adapter;
2663 struct ixgbe_ring *ring;
2664 int per_ring_budget;
2665 bool clean_complete = true;
2666
2667 #ifdef CONFIG_IXGBE_DCA
2668 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2669 ixgbe_update_dca(q_vector);
2670 #endif
2671
2672 ixgbe_for_each_ring(ring, q_vector->tx)
2673 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2674
2675 if (!ixgbe_qv_lock_napi(q_vector))
2676 return budget;
2677
2678 /* attempt to distribute budget to each queue fairly, but don't allow
2679 * the budget to go below 1 because we'll exit polling */
2680 if (q_vector->rx.count > 1)
2681 per_ring_budget = max(budget/q_vector->rx.count, 1);
2682 else
2683 per_ring_budget = budget;
2684
2685 ixgbe_for_each_ring(ring, q_vector->rx)
2686 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2687 per_ring_budget) < per_ring_budget);
2688
2689 ixgbe_qv_unlock_napi(q_vector);
2690 /* If all work not completed, return budget and keep polling */
2691 if (!clean_complete)
2692 return budget;
2693
2694 /* all work done, exit the polling mode */
2695 napi_complete(napi);
2696 if (adapter->rx_itr_setting & 1)
2697 ixgbe_set_itr(q_vector);
2698 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2699 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2700
2701 return 0;
2702 }
2703
2704 /**
2705 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2706 * @adapter: board private structure
2707 *
2708 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2709 * interrupts from the kernel.
2710 **/
2711 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2712 {
2713 struct net_device *netdev = adapter->netdev;
2714 int vector, err;
2715 int ri = 0, ti = 0;
2716
2717 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2718 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2719 struct msix_entry *entry = &adapter->msix_entries[vector];
2720
2721 if (q_vector->tx.ring && q_vector->rx.ring) {
2722 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2723 "%s-%s-%d", netdev->name, "TxRx", ri++);
2724 ti++;
2725 } else if (q_vector->rx.ring) {
2726 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2727 "%s-%s-%d", netdev->name, "rx", ri++);
2728 } else if (q_vector->tx.ring) {
2729 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2730 "%s-%s-%d", netdev->name, "tx", ti++);
2731 } else {
2732 /* skip this unused q_vector */
2733 continue;
2734 }
2735 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2736 q_vector->name, q_vector);
2737 if (err) {
2738 e_err(probe, "request_irq failed for MSIX interrupt "
2739 "Error: %d\n", err);
2740 goto free_queue_irqs;
2741 }
2742 /* If Flow Director is enabled, set interrupt affinity */
2743 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2744 /* assign the mask for this irq */
2745 irq_set_affinity_hint(entry->vector,
2746 &q_vector->affinity_mask);
2747 }
2748 }
2749
2750 err = request_irq(adapter->msix_entries[vector].vector,
2751 ixgbe_msix_other, 0, netdev->name, adapter);
2752 if (err) {
2753 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2754 goto free_queue_irqs;
2755 }
2756
2757 return 0;
2758
2759 free_queue_irqs:
2760 while (vector) {
2761 vector--;
2762 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2763 NULL);
2764 free_irq(adapter->msix_entries[vector].vector,
2765 adapter->q_vector[vector]);
2766 }
2767 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2768 pci_disable_msix(adapter->pdev);
2769 kfree(adapter->msix_entries);
2770 adapter->msix_entries = NULL;
2771 return err;
2772 }
2773
2774 /**
2775 * ixgbe_intr - legacy mode Interrupt Handler
2776 * @irq: interrupt number
2777 * @data: pointer to a network interface device structure
2778 **/
2779 static irqreturn_t ixgbe_intr(int irq, void *data)
2780 {
2781 struct ixgbe_adapter *adapter = data;
2782 struct ixgbe_hw *hw = &adapter->hw;
2783 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2784 u32 eicr;
2785
2786 /*
2787 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2788 * before the read of EICR.
2789 */
2790 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2791
2792 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2793 * therefore no explicit interrupt disable is necessary */
2794 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2795 if (!eicr) {
2796 /*
2797 * shared interrupt alert!
2798 * make sure interrupts are enabled because the read will
2799 * have disabled interrupts due to EIAM
2800 * finish the workaround of silicon errata on 82598. Unmask
2801 * the interrupt that we masked before the EICR read.
2802 */
2803 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2804 ixgbe_irq_enable(adapter, true, true);
2805 return IRQ_NONE; /* Not our interrupt */
2806 }
2807
2808 if (eicr & IXGBE_EICR_LSC)
2809 ixgbe_check_lsc(adapter);
2810
2811 switch (hw->mac.type) {
2812 case ixgbe_mac_82599EB:
2813 ixgbe_check_sfp_event(adapter, eicr);
2814 /* Fall through */
2815 case ixgbe_mac_X540:
2816 if (eicr & IXGBE_EICR_ECC) {
2817 e_info(link, "Received ECC Err, initiating reset\n");
2818 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2819 ixgbe_service_event_schedule(adapter);
2820 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2821 }
2822 ixgbe_check_overtemp_event(adapter, eicr);
2823 break;
2824 default:
2825 break;
2826 }
2827
2828 ixgbe_check_fan_failure(adapter, eicr);
2829 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2830 ixgbe_ptp_check_pps_event(adapter, eicr);
2831
2832 /* would disable interrupts here but EIAM disabled it */
2833 napi_schedule(&q_vector->napi);
2834
2835 /*
2836 * re-enable link(maybe) and non-queue interrupts, no flush.
2837 * ixgbe_poll will re-enable the queue interrupts
2838 */
2839 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2840 ixgbe_irq_enable(adapter, false, false);
2841
2842 return IRQ_HANDLED;
2843 }
2844
2845 /**
2846 * ixgbe_request_irq - initialize interrupts
2847 * @adapter: board private structure
2848 *
2849 * Attempts to configure interrupts using the best available
2850 * capabilities of the hardware and kernel.
2851 **/
2852 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2853 {
2854 struct net_device *netdev = adapter->netdev;
2855 int err;
2856
2857 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2858 err = ixgbe_request_msix_irqs(adapter);
2859 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2860 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2861 netdev->name, adapter);
2862 else
2863 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2864 netdev->name, adapter);
2865
2866 if (err)
2867 e_err(probe, "request_irq failed, Error %d\n", err);
2868
2869 return err;
2870 }
2871
2872 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2873 {
2874 int vector;
2875
2876 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2877 free_irq(adapter->pdev->irq, adapter);
2878 return;
2879 }
2880
2881 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2882 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2883 struct msix_entry *entry = &adapter->msix_entries[vector];
2884
2885 /* free only the irqs that were actually requested */
2886 if (!q_vector->rx.ring && !q_vector->tx.ring)
2887 continue;
2888
2889 /* clear the affinity_mask in the IRQ descriptor */
2890 irq_set_affinity_hint(entry->vector, NULL);
2891
2892 free_irq(entry->vector, q_vector);
2893 }
2894
2895 free_irq(adapter->msix_entries[vector++].vector, adapter);
2896 }
2897
2898 /**
2899 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2900 * @adapter: board private structure
2901 **/
2902 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2903 {
2904 switch (adapter->hw.mac.type) {
2905 case ixgbe_mac_82598EB:
2906 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2907 break;
2908 case ixgbe_mac_82599EB:
2909 case ixgbe_mac_X540:
2910 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2911 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2912 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2913 break;
2914 default:
2915 break;
2916 }
2917 IXGBE_WRITE_FLUSH(&adapter->hw);
2918 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2919 int vector;
2920
2921 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2922 synchronize_irq(adapter->msix_entries[vector].vector);
2923
2924 synchronize_irq(adapter->msix_entries[vector++].vector);
2925 } else {
2926 synchronize_irq(adapter->pdev->irq);
2927 }
2928 }
2929
2930 /**
2931 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2932 *
2933 **/
2934 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2935 {
2936 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2937
2938 ixgbe_write_eitr(q_vector);
2939
2940 ixgbe_set_ivar(adapter, 0, 0, 0);
2941 ixgbe_set_ivar(adapter, 1, 0, 0);
2942
2943 e_info(hw, "Legacy interrupt IVAR setup done\n");
2944 }
2945
2946 /**
2947 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2948 * @adapter: board private structure
2949 * @ring: structure containing ring specific data
2950 *
2951 * Configure the Tx descriptor ring after a reset.
2952 **/
2953 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2954 struct ixgbe_ring *ring)
2955 {
2956 struct ixgbe_hw *hw = &adapter->hw;
2957 u64 tdba = ring->dma;
2958 int wait_loop = 10;
2959 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2960 u8 reg_idx = ring->reg_idx;
2961
2962 /* disable queue to avoid issues while updating state */
2963 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2964 IXGBE_WRITE_FLUSH(hw);
2965
2966 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2967 (tdba & DMA_BIT_MASK(32)));
2968 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2969 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2970 ring->count * sizeof(union ixgbe_adv_tx_desc));
2971 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2972 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2973 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
2974
2975 /*
2976 * set WTHRESH to encourage burst writeback, it should not be set
2977 * higher than 1 when:
2978 * - ITR is 0 as it could cause false TX hangs
2979 * - ITR is set to > 100k int/sec and BQL is enabled
2980 *
2981 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2982 * to or less than the number of on chip descriptors, which is
2983 * currently 40.
2984 */
2985 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
2986 txdctl |= (1 << 16); /* WTHRESH = 1 */
2987 else
2988 txdctl |= (8 << 16); /* WTHRESH = 8 */
2989
2990 /*
2991 * Setting PTHRESH to 32 both improves performance
2992 * and avoids a TX hang with DFP enabled
2993 */
2994 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2995 32; /* PTHRESH = 32 */
2996
2997 /* reinitialize flowdirector state */
2998 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2999 ring->atr_sample_rate = adapter->atr_sample_rate;
3000 ring->atr_count = 0;
3001 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3002 } else {
3003 ring->atr_sample_rate = 0;
3004 }
3005
3006 /* initialize XPS */
3007 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3008 struct ixgbe_q_vector *q_vector = ring->q_vector;
3009
3010 if (q_vector)
3011 netif_set_xps_queue(ring->netdev,
3012 &q_vector->affinity_mask,
3013 ring->queue_index);
3014 }
3015
3016 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3017
3018 /* enable queue */
3019 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3020
3021 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3022 if (hw->mac.type == ixgbe_mac_82598EB &&
3023 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3024 return;
3025
3026 /* poll to verify queue is enabled */
3027 do {
3028 usleep_range(1000, 2000);
3029 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3030 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3031 if (!wait_loop)
3032 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
3033 }
3034
3035 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3036 {
3037 struct ixgbe_hw *hw = &adapter->hw;
3038 u32 rttdcs, mtqc;
3039 u8 tcs = netdev_get_num_tc(adapter->netdev);
3040
3041 if (hw->mac.type == ixgbe_mac_82598EB)
3042 return;
3043
3044 /* disable the arbiter while setting MTQC */
3045 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3046 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3047 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3048
3049 /* set transmit pool layout */
3050 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3051 mtqc = IXGBE_MTQC_VT_ENA;
3052 if (tcs > 4)
3053 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3054 else if (tcs > 1)
3055 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3056 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3057 mtqc |= IXGBE_MTQC_32VF;
3058 else
3059 mtqc |= IXGBE_MTQC_64VF;
3060 } else {
3061 if (tcs > 4)
3062 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3063 else if (tcs > 1)
3064 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3065 else
3066 mtqc = IXGBE_MTQC_64Q_1PB;
3067 }
3068
3069 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3070
3071 /* Enable Security TX Buffer IFG for multiple pb */
3072 if (tcs) {
3073 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3074 sectx |= IXGBE_SECTX_DCB;
3075 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3076 }
3077
3078 /* re-enable the arbiter */
3079 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3080 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3081 }
3082
3083 /**
3084 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3085 * @adapter: board private structure
3086 *
3087 * Configure the Tx unit of the MAC after a reset.
3088 **/
3089 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3090 {
3091 struct ixgbe_hw *hw = &adapter->hw;
3092 u32 dmatxctl;
3093 u32 i;
3094
3095 ixgbe_setup_mtqc(adapter);
3096
3097 if (hw->mac.type != ixgbe_mac_82598EB) {
3098 /* DMATXCTL.EN must be before Tx queues are enabled */
3099 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3100 dmatxctl |= IXGBE_DMATXCTL_TE;
3101 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3102 }
3103
3104 /* Setup the HW Tx Head and Tail descriptor pointers */
3105 for (i = 0; i < adapter->num_tx_queues; i++)
3106 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3107 }
3108
3109 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3110 struct ixgbe_ring *ring)
3111 {
3112 struct ixgbe_hw *hw = &adapter->hw;
3113 u8 reg_idx = ring->reg_idx;
3114 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3115
3116 srrctl |= IXGBE_SRRCTL_DROP_EN;
3117
3118 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3119 }
3120
3121 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3122 struct ixgbe_ring *ring)
3123 {
3124 struct ixgbe_hw *hw = &adapter->hw;
3125 u8 reg_idx = ring->reg_idx;
3126 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3127
3128 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3129
3130 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3131 }
3132
3133 #ifdef CONFIG_IXGBE_DCB
3134 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3135 #else
3136 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3137 #endif
3138 {
3139 int i;
3140 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3141
3142 if (adapter->ixgbe_ieee_pfc)
3143 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3144
3145 /*
3146 * We should set the drop enable bit if:
3147 * SR-IOV is enabled
3148 * or
3149 * Number of Rx queues > 1 and flow control is disabled
3150 *
3151 * This allows us to avoid head of line blocking for security
3152 * and performance reasons.
3153 */
3154 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3155 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3156 for (i = 0; i < adapter->num_rx_queues; i++)
3157 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3158 } else {
3159 for (i = 0; i < adapter->num_rx_queues; i++)
3160 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3161 }
3162 }
3163
3164 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3165
3166 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3167 struct ixgbe_ring *rx_ring)
3168 {
3169 struct ixgbe_hw *hw = &adapter->hw;
3170 u32 srrctl;
3171 u8 reg_idx = rx_ring->reg_idx;
3172
3173 if (hw->mac.type == ixgbe_mac_82598EB) {
3174 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3175
3176 /*
3177 * if VMDq is not active we must program one srrctl register
3178 * per RSS queue since we have enabled RDRXCTL.MVMEN
3179 */
3180 reg_idx &= mask;
3181 }
3182
3183 /* configure header buffer length, needed for RSC */
3184 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3185
3186 /* configure the packet buffer length */
3187 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3188
3189 /* configure descriptor type */
3190 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3191
3192 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3193 }
3194
3195 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3196 {
3197 struct ixgbe_hw *hw = &adapter->hw;
3198 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
3199 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3200 0x6A3E67EA, 0x14364D17, 0x3BED200D};
3201 u32 mrqc = 0, reta = 0;
3202 u32 rxcsum;
3203 int i, j;
3204 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3205
3206 /*
3207 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3208 * make full use of any rings they may have. We will use the
3209 * PSRTYPE register to control how many rings we use within the PF.
3210 */
3211 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3212 rss_i = 2;
3213
3214 /* Fill out hash function seeds */
3215 for (i = 0; i < 10; i++)
3216 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3217
3218 /* Fill out redirection table */
3219 for (i = 0, j = 0; i < 128; i++, j++) {
3220 if (j == rss_i)
3221 j = 0;
3222 /* reta = 4-byte sliding window of
3223 * 0x00..(indices-1)(indices-1)00..etc. */
3224 reta = (reta << 8) | (j * 0x11);
3225 if ((i & 3) == 3)
3226 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3227 }
3228
3229 /* Disable indicating checksum in descriptor, enables RSS hash */
3230 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3231 rxcsum |= IXGBE_RXCSUM_PCSD;
3232 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3233
3234 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3235 if (adapter->ring_feature[RING_F_RSS].mask)
3236 mrqc = IXGBE_MRQC_RSSEN;
3237 } else {
3238 u8 tcs = netdev_get_num_tc(adapter->netdev);
3239
3240 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3241 if (tcs > 4)
3242 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3243 else if (tcs > 1)
3244 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3245 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3246 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3247 else
3248 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3249 } else {
3250 if (tcs > 4)
3251 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3252 else if (tcs > 1)
3253 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3254 else
3255 mrqc = IXGBE_MRQC_RSSEN;
3256 }
3257 }
3258
3259 /* Perform hash on these packet types */
3260 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3261 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3262 IXGBE_MRQC_RSS_FIELD_IPV6 |
3263 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3264
3265 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3266 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3267 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3268 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3269
3270 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3271 }
3272
3273 /**
3274 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3275 * @adapter: address of board private structure
3276 * @index: index of ring to set
3277 **/
3278 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3279 struct ixgbe_ring *ring)
3280 {
3281 struct ixgbe_hw *hw = &adapter->hw;
3282 u32 rscctrl;
3283 u8 reg_idx = ring->reg_idx;
3284
3285 if (!ring_is_rsc_enabled(ring))
3286 return;
3287
3288 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3289 rscctrl |= IXGBE_RSCCTL_RSCEN;
3290 /*
3291 * we must limit the number of descriptors so that the
3292 * total size of max desc * buf_len is not greater
3293 * than 65536
3294 */
3295 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3296 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3297 }
3298
3299 #define IXGBE_MAX_RX_DESC_POLL 10
3300 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3301 struct ixgbe_ring *ring)
3302 {
3303 struct ixgbe_hw *hw = &adapter->hw;
3304 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3305 u32 rxdctl;
3306 u8 reg_idx = ring->reg_idx;
3307
3308 if (ixgbe_removed(hw->hw_addr))
3309 return;
3310 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3311 if (hw->mac.type == ixgbe_mac_82598EB &&
3312 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3313 return;
3314
3315 do {
3316 usleep_range(1000, 2000);
3317 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3318 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3319
3320 if (!wait_loop) {
3321 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3322 "the polling period\n", reg_idx);
3323 }
3324 }
3325
3326 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3327 struct ixgbe_ring *ring)
3328 {
3329 struct ixgbe_hw *hw = &adapter->hw;
3330 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3331 u32 rxdctl;
3332 u8 reg_idx = ring->reg_idx;
3333
3334 if (ixgbe_removed(hw->hw_addr))
3335 return;
3336 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3337 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3338
3339 /* write value back with RXDCTL.ENABLE bit cleared */
3340 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3341
3342 if (hw->mac.type == ixgbe_mac_82598EB &&
3343 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3344 return;
3345
3346 /* the hardware may take up to 100us to really disable the rx queue */
3347 do {
3348 udelay(10);
3349 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3350 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3351
3352 if (!wait_loop) {
3353 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3354 "the polling period\n", reg_idx);
3355 }
3356 }
3357
3358 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3359 struct ixgbe_ring *ring)
3360 {
3361 struct ixgbe_hw *hw = &adapter->hw;
3362 u64 rdba = ring->dma;
3363 u32 rxdctl;
3364 u8 reg_idx = ring->reg_idx;
3365
3366 /* disable queue to avoid issues while updating state */
3367 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3368 ixgbe_disable_rx_queue(adapter, ring);
3369
3370 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3371 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3372 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3373 ring->count * sizeof(union ixgbe_adv_rx_desc));
3374 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3375 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3376 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
3377
3378 ixgbe_configure_srrctl(adapter, ring);
3379 ixgbe_configure_rscctl(adapter, ring);
3380
3381 if (hw->mac.type == ixgbe_mac_82598EB) {
3382 /*
3383 * enable cache line friendly hardware writes:
3384 * PTHRESH=32 descriptors (half the internal cache),
3385 * this also removes ugly rx_no_buffer_count increment
3386 * HTHRESH=4 descriptors (to minimize latency on fetch)
3387 * WTHRESH=8 burst writeback up to two cache lines
3388 */
3389 rxdctl &= ~0x3FFFFF;
3390 rxdctl |= 0x080420;
3391 }
3392
3393 /* enable receive descriptor ring */
3394 rxdctl |= IXGBE_RXDCTL_ENABLE;
3395 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3396
3397 ixgbe_rx_desc_queue_enable(adapter, ring);
3398 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3399 }
3400
3401 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3402 {
3403 struct ixgbe_hw *hw = &adapter->hw;
3404 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3405 u16 pool;
3406
3407 /* PSRTYPE must be initialized in non 82598 adapters */
3408 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3409 IXGBE_PSRTYPE_UDPHDR |
3410 IXGBE_PSRTYPE_IPV4HDR |
3411 IXGBE_PSRTYPE_L2HDR |
3412 IXGBE_PSRTYPE_IPV6HDR;
3413
3414 if (hw->mac.type == ixgbe_mac_82598EB)
3415 return;
3416
3417 if (rss_i > 3)
3418 psrtype |= 2 << 29;
3419 else if (rss_i > 1)
3420 psrtype |= 1 << 29;
3421
3422 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3423 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
3424 }
3425
3426 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3427 {
3428 struct ixgbe_hw *hw = &adapter->hw;
3429 u32 reg_offset, vf_shift;
3430 u32 gcr_ext, vmdctl;
3431 int i;
3432
3433 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3434 return;
3435
3436 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3437 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3438 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3439 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3440 vmdctl |= IXGBE_VT_CTL_REPLEN;
3441 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3442
3443 vf_shift = VMDQ_P(0) % 32;
3444 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3445
3446 /* Enable only the PF's pool for Tx/Rx */
3447 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3448 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3449 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3450 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3451 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3452 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3453
3454 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3455 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3456
3457 /*
3458 * Set up VF register offsets for selected VT Mode,
3459 * i.e. 32 or 64 VFs for SR-IOV
3460 */
3461 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3462 case IXGBE_82599_VMDQ_8Q_MASK:
3463 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3464 break;
3465 case IXGBE_82599_VMDQ_4Q_MASK:
3466 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3467 break;
3468 default:
3469 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3470 break;
3471 }
3472
3473 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3474
3475
3476 /* Enable MAC Anti-Spoofing */
3477 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3478 adapter->num_vfs);
3479 /* For VFs that have spoof checking turned off */
3480 for (i = 0; i < adapter->num_vfs; i++) {
3481 if (!adapter->vfinfo[i].spoofchk_enabled)
3482 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3483 }
3484 }
3485
3486 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3487 {
3488 struct ixgbe_hw *hw = &adapter->hw;
3489 struct net_device *netdev = adapter->netdev;
3490 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3491 struct ixgbe_ring *rx_ring;
3492 int i;
3493 u32 mhadd, hlreg0;
3494
3495 #ifdef IXGBE_FCOE
3496 /* adjust max frame to be able to do baby jumbo for FCoE */
3497 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3498 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3499 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3500
3501 #endif /* IXGBE_FCOE */
3502
3503 /* adjust max frame to be at least the size of a standard frame */
3504 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3505 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3506
3507 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3508 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3509 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3510 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3511
3512 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3513 }
3514
3515 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3516 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3517 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3518 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3519
3520 /*
3521 * Setup the HW Rx Head and Tail Descriptor Pointers and
3522 * the Base and Length of the Rx Descriptor Ring
3523 */
3524 for (i = 0; i < adapter->num_rx_queues; i++) {
3525 rx_ring = adapter->rx_ring[i];
3526 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3527 set_ring_rsc_enabled(rx_ring);
3528 else
3529 clear_ring_rsc_enabled(rx_ring);
3530 }
3531 }
3532
3533 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3534 {
3535 struct ixgbe_hw *hw = &adapter->hw;
3536 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3537
3538 switch (hw->mac.type) {
3539 case ixgbe_mac_82598EB:
3540 /*
3541 * For VMDq support of different descriptor types or
3542 * buffer sizes through the use of multiple SRRCTL
3543 * registers, RDRXCTL.MVMEN must be set to 1
3544 *
3545 * also, the manual doesn't mention it clearly but DCA hints
3546 * will only use queue 0's tags unless this bit is set. Side
3547 * effects of setting this bit are only that SRRCTL must be
3548 * fully programmed [0..15]
3549 */
3550 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3551 break;
3552 case ixgbe_mac_82599EB:
3553 case ixgbe_mac_X540:
3554 /* Disable RSC for ACK packets */
3555 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3556 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3557 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3558 /* hardware requires some bits to be set by default */
3559 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3560 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3561 break;
3562 default:
3563 /* We should do nothing since we don't know this hardware */
3564 return;
3565 }
3566
3567 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3568 }
3569
3570 /**
3571 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3572 * @adapter: board private structure
3573 *
3574 * Configure the Rx unit of the MAC after a reset.
3575 **/
3576 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3577 {
3578 struct ixgbe_hw *hw = &adapter->hw;
3579 int i;
3580 u32 rxctrl, rfctl;
3581
3582 /* disable receives while setting up the descriptors */
3583 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3584 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3585
3586 ixgbe_setup_psrtype(adapter);
3587 ixgbe_setup_rdrxctl(adapter);
3588
3589 /* RSC Setup */
3590 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3591 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3592 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3593 rfctl |= IXGBE_RFCTL_RSC_DIS;
3594 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3595
3596 /* Program registers for the distribution of queues */
3597 ixgbe_setup_mrqc(adapter);
3598
3599 /* set_rx_buffer_len must be called before ring initialization */
3600 ixgbe_set_rx_buffer_len(adapter);
3601
3602 /*
3603 * Setup the HW Rx Head and Tail Descriptor Pointers and
3604 * the Base and Length of the Rx Descriptor Ring
3605 */
3606 for (i = 0; i < adapter->num_rx_queues; i++)
3607 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3608
3609 /* disable drop enable for 82598 parts */
3610 if (hw->mac.type == ixgbe_mac_82598EB)
3611 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3612
3613 /* enable all receives */
3614 rxctrl |= IXGBE_RXCTRL_RXEN;
3615 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3616 }
3617
3618 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3619 __be16 proto, u16 vid)
3620 {
3621 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3622 struct ixgbe_hw *hw = &adapter->hw;
3623
3624 /* add VID to filter table */
3625 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3626 set_bit(vid, adapter->active_vlans);
3627
3628 return 0;
3629 }
3630
3631 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3632 __be16 proto, u16 vid)
3633 {
3634 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3635 struct ixgbe_hw *hw = &adapter->hw;
3636
3637 /* remove VID from filter table */
3638 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3639 clear_bit(vid, adapter->active_vlans);
3640
3641 return 0;
3642 }
3643
3644 /**
3645 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3646 * @adapter: driver data
3647 */
3648 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3649 {
3650 struct ixgbe_hw *hw = &adapter->hw;
3651 u32 vlnctrl;
3652 int i, j;
3653
3654 switch (hw->mac.type) {
3655 case ixgbe_mac_82598EB:
3656 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3657 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3658 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3659 break;
3660 case ixgbe_mac_82599EB:
3661 case ixgbe_mac_X540:
3662 for (i = 0; i < adapter->num_rx_queues; i++) {
3663 struct ixgbe_ring *ring = adapter->rx_ring[i];
3664
3665 if (ring->l2_accel_priv)
3666 continue;
3667 j = ring->reg_idx;
3668 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3669 vlnctrl &= ~IXGBE_RXDCTL_VME;
3670 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3671 }
3672 break;
3673 default:
3674 break;
3675 }
3676 }
3677
3678 /**
3679 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3680 * @adapter: driver data
3681 */
3682 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3683 {
3684 struct ixgbe_hw *hw = &adapter->hw;
3685 u32 vlnctrl;
3686 int i, j;
3687
3688 switch (hw->mac.type) {
3689 case ixgbe_mac_82598EB:
3690 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3691 vlnctrl |= IXGBE_VLNCTRL_VME;
3692 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3693 break;
3694 case ixgbe_mac_82599EB:
3695 case ixgbe_mac_X540:
3696 for (i = 0; i < adapter->num_rx_queues; i++) {
3697 struct ixgbe_ring *ring = adapter->rx_ring[i];
3698
3699 if (ring->l2_accel_priv)
3700 continue;
3701 j = ring->reg_idx;
3702 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3703 vlnctrl |= IXGBE_RXDCTL_VME;
3704 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3705 }
3706 break;
3707 default:
3708 break;
3709 }
3710 }
3711
3712 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3713 {
3714 u16 vid;
3715
3716 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
3717
3718 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3719 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
3720 }
3721
3722 /**
3723 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
3724 * @netdev: network interface device structure
3725 *
3726 * Writes multicast address list to the MTA hash table.
3727 * Returns: -ENOMEM on failure
3728 * 0 on no addresses written
3729 * X on writing X addresses to MTA
3730 **/
3731 static int ixgbe_write_mc_addr_list(struct net_device *netdev)
3732 {
3733 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3734 struct ixgbe_hw *hw = &adapter->hw;
3735
3736 if (!netif_running(netdev))
3737 return 0;
3738
3739 if (hw->mac.ops.update_mc_addr_list)
3740 hw->mac.ops.update_mc_addr_list(hw, netdev);
3741 else
3742 return -ENOMEM;
3743
3744 #ifdef CONFIG_PCI_IOV
3745 ixgbe_restore_vf_multicasts(adapter);
3746 #endif
3747
3748 return netdev_mc_count(netdev);
3749 }
3750
3751 #ifdef CONFIG_PCI_IOV
3752 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
3753 {
3754 struct ixgbe_hw *hw = &adapter->hw;
3755 int i;
3756 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3757 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3758 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
3759 adapter->mac_table[i].queue,
3760 IXGBE_RAH_AV);
3761 else
3762 hw->mac.ops.clear_rar(hw, i);
3763
3764 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED);
3765 }
3766 }
3767 #endif
3768
3769 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
3770 {
3771 struct ixgbe_hw *hw = &adapter->hw;
3772 int i;
3773 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3774 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
3775 if (adapter->mac_table[i].state &
3776 IXGBE_MAC_STATE_IN_USE)
3777 hw->mac.ops.set_rar(hw, i,
3778 adapter->mac_table[i].addr,
3779 adapter->mac_table[i].queue,
3780 IXGBE_RAH_AV);
3781 else
3782 hw->mac.ops.clear_rar(hw, i);
3783
3784 adapter->mac_table[i].state &=
3785 ~(IXGBE_MAC_STATE_MODIFIED);
3786 }
3787 }
3788 }
3789
3790 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
3791 {
3792 int i;
3793 struct ixgbe_hw *hw = &adapter->hw;
3794
3795 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3796 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3797 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
3798 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
3799 adapter->mac_table[i].queue = 0;
3800 }
3801 ixgbe_sync_mac_table(adapter);
3802 }
3803
3804 static int ixgbe_available_rars(struct ixgbe_adapter *adapter)
3805 {
3806 struct ixgbe_hw *hw = &adapter->hw;
3807 int i, count = 0;
3808
3809 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3810 if (adapter->mac_table[i].state == 0)
3811 count++;
3812 }
3813 return count;
3814 }
3815
3816 /* this function destroys the first RAR entry */
3817 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter,
3818 u8 *addr)
3819 {
3820 struct ixgbe_hw *hw = &adapter->hw;
3821
3822 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN);
3823 adapter->mac_table[0].queue = VMDQ_P(0);
3824 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
3825 IXGBE_MAC_STATE_IN_USE);
3826 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
3827 adapter->mac_table[0].queue,
3828 IXGBE_RAH_AV);
3829 }
3830
3831 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3832 {
3833 struct ixgbe_hw *hw = &adapter->hw;
3834 int i;
3835
3836 if (is_zero_ether_addr(addr))
3837 return -EINVAL;
3838
3839 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3840 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3841 continue;
3842 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
3843 IXGBE_MAC_STATE_IN_USE);
3844 ether_addr_copy(adapter->mac_table[i].addr, addr);
3845 adapter->mac_table[i].queue = queue;
3846 ixgbe_sync_mac_table(adapter);
3847 return i;
3848 }
3849 return -ENOMEM;
3850 }
3851
3852 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3853 {
3854 /* search table for addr, if found, set to 0 and sync */
3855 int i;
3856 struct ixgbe_hw *hw = &adapter->hw;
3857
3858 if (is_zero_ether_addr(addr))
3859 return -EINVAL;
3860
3861 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3862 if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
3863 adapter->mac_table[i].queue == queue) {
3864 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3865 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
3866 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
3867 adapter->mac_table[i].queue = 0;
3868 ixgbe_sync_mac_table(adapter);
3869 return 0;
3870 }
3871 }
3872 return -ENOMEM;
3873 }
3874 /**
3875 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3876 * @netdev: network interface device structure
3877 *
3878 * Writes unicast address list to the RAR table.
3879 * Returns: -ENOMEM on failure/insufficient address space
3880 * 0 on no addresses written
3881 * X on writing X addresses to the RAR table
3882 **/
3883 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
3884 {
3885 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3886 int count = 0;
3887
3888 /* return ENOMEM indicating insufficient memory for addresses */
3889 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
3890 return -ENOMEM;
3891
3892 if (!netdev_uc_empty(netdev)) {
3893 struct netdev_hw_addr *ha;
3894 netdev_for_each_uc_addr(ha, netdev) {
3895 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
3896 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
3897 count++;
3898 }
3899 }
3900 return count;
3901 }
3902
3903 /**
3904 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3905 * @netdev: network interface device structure
3906 *
3907 * The set_rx_method entry point is called whenever the unicast/multicast
3908 * address list or the network interface flags are updated. This routine is
3909 * responsible for configuring the hardware for proper unicast, multicast and
3910 * promiscuous mode.
3911 **/
3912 void ixgbe_set_rx_mode(struct net_device *netdev)
3913 {
3914 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3915 struct ixgbe_hw *hw = &adapter->hw;
3916 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3917 u32 vlnctrl;
3918 int count;
3919
3920 /* Check for Promiscuous and All Multicast modes */
3921 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3922 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3923
3924 /* set all bits that we expect to always be set */
3925 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3926 fctrl |= IXGBE_FCTRL_BAM;
3927 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3928 fctrl |= IXGBE_FCTRL_PMCF;
3929
3930 /* clear the bits we are changing the status of */
3931 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3932 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3933 if (netdev->flags & IFF_PROMISC) {
3934 hw->addr_ctrl.user_set_promisc = true;
3935 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3936 vmolr |= IXGBE_VMOLR_MPE;
3937 /* Only disable hardware filter vlans in promiscuous mode
3938 * if SR-IOV and VMDQ are disabled - otherwise ensure
3939 * that hardware VLAN filters remain enabled.
3940 */
3941 if (!(adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
3942 IXGBE_FLAG_SRIOV_ENABLED)))
3943 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3944 } else {
3945 if (netdev->flags & IFF_ALLMULTI) {
3946 fctrl |= IXGBE_FCTRL_MPE;
3947 vmolr |= IXGBE_VMOLR_MPE;
3948 }
3949 vlnctrl |= IXGBE_VLNCTRL_VFE;
3950 hw->addr_ctrl.user_set_promisc = false;
3951 }
3952
3953 /*
3954 * Write addresses to available RAR registers, if there is not
3955 * sufficient space to store all the addresses then enable
3956 * unicast promiscuous mode
3957 */
3958 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0));
3959 if (count < 0) {
3960 fctrl |= IXGBE_FCTRL_UPE;
3961 vmolr |= IXGBE_VMOLR_ROPE;
3962 }
3963
3964 /* Write addresses to the MTA, if the attempt fails
3965 * then we should just turn on promiscuous mode so
3966 * that we can at least receive multicast traffic
3967 */
3968 count = ixgbe_write_mc_addr_list(netdev);
3969 if (count < 0) {
3970 fctrl |= IXGBE_FCTRL_MPE;
3971 vmolr |= IXGBE_VMOLR_MPE;
3972 } else if (count) {
3973 vmolr |= IXGBE_VMOLR_ROMPE;
3974 }
3975
3976 if (hw->mac.type != ixgbe_mac_82598EB) {
3977 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
3978 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3979 IXGBE_VMOLR_ROPE);
3980 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
3981 }
3982
3983 /* This is useful for sniffing bad packets. */
3984 if (adapter->netdev->features & NETIF_F_RXALL) {
3985 /* UPE and MPE will be handled by normal PROMISC logic
3986 * in e1000e_set_rx_mode */
3987 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3988 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3989 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3990
3991 fctrl &= ~(IXGBE_FCTRL_DPF);
3992 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3993 }
3994
3995 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3996 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3997
3998 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3999 ixgbe_vlan_strip_enable(adapter);
4000 else
4001 ixgbe_vlan_strip_disable(adapter);
4002 }
4003
4004 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4005 {
4006 int q_idx;
4007
4008 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4009 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
4010 napi_enable(&adapter->q_vector[q_idx]->napi);
4011 }
4012 }
4013
4014 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4015 {
4016 int q_idx;
4017
4018 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4019 napi_disable(&adapter->q_vector[q_idx]->napi);
4020 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
4021 pr_info("QV %d locked\n", q_idx);
4022 usleep_range(1000, 20000);
4023 }
4024 }
4025 }
4026
4027 #ifdef CONFIG_IXGBE_DCB
4028 /**
4029 * ixgbe_configure_dcb - Configure DCB hardware
4030 * @adapter: ixgbe adapter struct
4031 *
4032 * This is called by the driver on open to configure the DCB hardware.
4033 * This is also called by the gennetlink interface when reconfiguring
4034 * the DCB state.
4035 */
4036 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4037 {
4038 struct ixgbe_hw *hw = &adapter->hw;
4039 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4040
4041 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4042 if (hw->mac.type == ixgbe_mac_82598EB)
4043 netif_set_gso_max_size(adapter->netdev, 65536);
4044 return;
4045 }
4046
4047 if (hw->mac.type == ixgbe_mac_82598EB)
4048 netif_set_gso_max_size(adapter->netdev, 32768);
4049
4050 #ifdef IXGBE_FCOE
4051 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4052 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
4053 #endif
4054
4055 /* reconfigure the hardware */
4056 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
4057 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4058 DCB_TX_CONFIG);
4059 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4060 DCB_RX_CONFIG);
4061 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
4062 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4063 ixgbe_dcb_hw_ets(&adapter->hw,
4064 adapter->ixgbe_ieee_ets,
4065 max_frame);
4066 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4067 adapter->ixgbe_ieee_pfc->pfc_en,
4068 adapter->ixgbe_ieee_ets->prio_tc);
4069 }
4070
4071 /* Enable RSS Hash per TC */
4072 if (hw->mac.type != ixgbe_mac_82598EB) {
4073 u32 msb = 0;
4074 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
4075
4076 while (rss_i) {
4077 msb++;
4078 rss_i >>= 1;
4079 }
4080
4081 /* write msb to all 8 TCs in one write */
4082 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
4083 }
4084 }
4085 #endif
4086
4087 /* Additional bittime to account for IXGBE framing */
4088 #define IXGBE_ETH_FRAMING 20
4089
4090 /**
4091 * ixgbe_hpbthresh - calculate high water mark for flow control
4092 *
4093 * @adapter: board private structure to calculate for
4094 * @pb: packet buffer to calculate
4095 */
4096 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4097 {
4098 struct ixgbe_hw *hw = &adapter->hw;
4099 struct net_device *dev = adapter->netdev;
4100 int link, tc, kb, marker;
4101 u32 dv_id, rx_pba;
4102
4103 /* Calculate max LAN frame size */
4104 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4105
4106 #ifdef IXGBE_FCOE
4107 /* FCoE traffic class uses FCOE jumbo frames */
4108 if ((dev->features & NETIF_F_FCOE_MTU) &&
4109 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4110 (pb == ixgbe_fcoe_get_tc(adapter)))
4111 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4112 #endif
4113
4114 /* Calculate delay value for device */
4115 switch (hw->mac.type) {
4116 case ixgbe_mac_X540:
4117 dv_id = IXGBE_DV_X540(link, tc);
4118 break;
4119 default:
4120 dv_id = IXGBE_DV(link, tc);
4121 break;
4122 }
4123
4124 /* Loopback switch introduces additional latency */
4125 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4126 dv_id += IXGBE_B2BT(tc);
4127
4128 /* Delay value is calculated in bit times convert to KB */
4129 kb = IXGBE_BT2KB(dv_id);
4130 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4131
4132 marker = rx_pba - kb;
4133
4134 /* It is possible that the packet buffer is not large enough
4135 * to provide required headroom. In this case throw an error
4136 * to user and a do the best we can.
4137 */
4138 if (marker < 0) {
4139 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4140 "headroom to support flow control."
4141 "Decrease MTU or number of traffic classes\n", pb);
4142 marker = tc + 1;
4143 }
4144
4145 return marker;
4146 }
4147
4148 /**
4149 * ixgbe_lpbthresh - calculate low water mark for for flow control
4150 *
4151 * @adapter: board private structure to calculate for
4152 * @pb: packet buffer to calculate
4153 */
4154 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
4155 {
4156 struct ixgbe_hw *hw = &adapter->hw;
4157 struct net_device *dev = adapter->netdev;
4158 int tc;
4159 u32 dv_id;
4160
4161 /* Calculate max LAN frame size */
4162 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4163
4164 #ifdef IXGBE_FCOE
4165 /* FCoE traffic class uses FCOE jumbo frames */
4166 if ((dev->features & NETIF_F_FCOE_MTU) &&
4167 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4168 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4169 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4170 #endif
4171
4172 /* Calculate delay value for device */
4173 switch (hw->mac.type) {
4174 case ixgbe_mac_X540:
4175 dv_id = IXGBE_LOW_DV_X540(tc);
4176 break;
4177 default:
4178 dv_id = IXGBE_LOW_DV(tc);
4179 break;
4180 }
4181
4182 /* Delay value is calculated in bit times convert to KB */
4183 return IXGBE_BT2KB(dv_id);
4184 }
4185
4186 /*
4187 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4188 */
4189 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4190 {
4191 struct ixgbe_hw *hw = &adapter->hw;
4192 int num_tc = netdev_get_num_tc(adapter->netdev);
4193 int i;
4194
4195 if (!num_tc)
4196 num_tc = 1;
4197
4198 for (i = 0; i < num_tc; i++) {
4199 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4200 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
4201
4202 /* Low water marks must not be larger than high water marks */
4203 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4204 hw->fc.low_water[i] = 0;
4205 }
4206
4207 for (; i < MAX_TRAFFIC_CLASS; i++)
4208 hw->fc.high_water[i] = 0;
4209 }
4210
4211 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4212 {
4213 struct ixgbe_hw *hw = &adapter->hw;
4214 int hdrm;
4215 u8 tc = netdev_get_num_tc(adapter->netdev);
4216
4217 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4218 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4219 hdrm = 32 << adapter->fdir_pballoc;
4220 else
4221 hdrm = 0;
4222
4223 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
4224 ixgbe_pbthresh_setup(adapter);
4225 }
4226
4227 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4228 {
4229 struct ixgbe_hw *hw = &adapter->hw;
4230 struct hlist_node *node2;
4231 struct ixgbe_fdir_filter *filter;
4232
4233 spin_lock(&adapter->fdir_perfect_lock);
4234
4235 if (!hlist_empty(&adapter->fdir_filter_list))
4236 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4237
4238 hlist_for_each_entry_safe(filter, node2,
4239 &adapter->fdir_filter_list, fdir_node) {
4240 ixgbe_fdir_write_perfect_filter_82599(hw,
4241 &filter->filter,
4242 filter->sw_idx,
4243 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4244 IXGBE_FDIR_DROP_QUEUE :
4245 adapter->rx_ring[filter->action]->reg_idx);
4246 }
4247
4248 spin_unlock(&adapter->fdir_perfect_lock);
4249 }
4250
4251 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4252 struct ixgbe_adapter *adapter)
4253 {
4254 struct ixgbe_hw *hw = &adapter->hw;
4255 u32 vmolr;
4256
4257 /* No unicast promiscuous support for VMDQ devices. */
4258 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4259 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4260
4261 /* clear the affected bit */
4262 vmolr &= ~IXGBE_VMOLR_MPE;
4263
4264 if (dev->flags & IFF_ALLMULTI) {
4265 vmolr |= IXGBE_VMOLR_MPE;
4266 } else {
4267 vmolr |= IXGBE_VMOLR_ROMPE;
4268 hw->mac.ops.update_mc_addr_list(hw, dev);
4269 }
4270 ixgbe_write_uc_addr_list(adapter->netdev, pool);
4271 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4272 }
4273
4274 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4275 {
4276 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4277 int rss_i = adapter->num_rx_queues_per_pool;
4278 struct ixgbe_hw *hw = &adapter->hw;
4279 u16 pool = vadapter->pool;
4280 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4281 IXGBE_PSRTYPE_UDPHDR |
4282 IXGBE_PSRTYPE_IPV4HDR |
4283 IXGBE_PSRTYPE_L2HDR |
4284 IXGBE_PSRTYPE_IPV6HDR;
4285
4286 if (hw->mac.type == ixgbe_mac_82598EB)
4287 return;
4288
4289 if (rss_i > 3)
4290 psrtype |= 2 << 29;
4291 else if (rss_i > 1)
4292 psrtype |= 1 << 29;
4293
4294 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4295 }
4296
4297 /**
4298 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4299 * @rx_ring: ring to free buffers from
4300 **/
4301 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4302 {
4303 struct device *dev = rx_ring->dev;
4304 unsigned long size;
4305 u16 i;
4306
4307 /* ring already cleared, nothing to do */
4308 if (!rx_ring->rx_buffer_info)
4309 return;
4310
4311 /* Free all the Rx ring sk_buffs */
4312 for (i = 0; i < rx_ring->count; i++) {
4313 struct ixgbe_rx_buffer *rx_buffer;
4314
4315 rx_buffer = &rx_ring->rx_buffer_info[i];
4316 if (rx_buffer->skb) {
4317 struct sk_buff *skb = rx_buffer->skb;
4318 if (IXGBE_CB(skb)->page_released) {
4319 dma_unmap_page(dev,
4320 IXGBE_CB(skb)->dma,
4321 ixgbe_rx_bufsz(rx_ring),
4322 DMA_FROM_DEVICE);
4323 IXGBE_CB(skb)->page_released = false;
4324 }
4325 dev_kfree_skb(skb);
4326 }
4327 rx_buffer->skb = NULL;
4328 if (rx_buffer->dma)
4329 dma_unmap_page(dev, rx_buffer->dma,
4330 ixgbe_rx_pg_size(rx_ring),
4331 DMA_FROM_DEVICE);
4332 rx_buffer->dma = 0;
4333 if (rx_buffer->page)
4334 __free_pages(rx_buffer->page,
4335 ixgbe_rx_pg_order(rx_ring));
4336 rx_buffer->page = NULL;
4337 }
4338
4339 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4340 memset(rx_ring->rx_buffer_info, 0, size);
4341
4342 /* Zero out the descriptor ring */
4343 memset(rx_ring->desc, 0, rx_ring->size);
4344
4345 rx_ring->next_to_alloc = 0;
4346 rx_ring->next_to_clean = 0;
4347 rx_ring->next_to_use = 0;
4348 }
4349
4350 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4351 struct ixgbe_ring *rx_ring)
4352 {
4353 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4354 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4355
4356 /* shutdown specific queue receive and wait for dma to settle */
4357 ixgbe_disable_rx_queue(adapter, rx_ring);
4358 usleep_range(10000, 20000);
4359 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4360 ixgbe_clean_rx_ring(rx_ring);
4361 rx_ring->l2_accel_priv = NULL;
4362 }
4363
4364 static int ixgbe_fwd_ring_down(struct net_device *vdev,
4365 struct ixgbe_fwd_adapter *accel)
4366 {
4367 struct ixgbe_adapter *adapter = accel->real_adapter;
4368 unsigned int rxbase = accel->rx_base_queue;
4369 unsigned int txbase = accel->tx_base_queue;
4370 int i;
4371
4372 netif_tx_stop_all_queues(vdev);
4373
4374 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4375 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4376 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4377 }
4378
4379 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4380 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4381 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4382 }
4383
4384
4385 return 0;
4386 }
4387
4388 static int ixgbe_fwd_ring_up(struct net_device *vdev,
4389 struct ixgbe_fwd_adapter *accel)
4390 {
4391 struct ixgbe_adapter *adapter = accel->real_adapter;
4392 unsigned int rxbase, txbase, queues;
4393 int i, baseq, err = 0;
4394
4395 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4396 return 0;
4397
4398 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4399 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4400 accel->pool, adapter->num_rx_pools,
4401 baseq, baseq + adapter->num_rx_queues_per_pool,
4402 adapter->fwd_bitmask);
4403
4404 accel->netdev = vdev;
4405 accel->rx_base_queue = rxbase = baseq;
4406 accel->tx_base_queue = txbase = baseq;
4407
4408 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4409 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4410
4411 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4412 adapter->rx_ring[rxbase + i]->netdev = vdev;
4413 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4414 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4415 }
4416
4417 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4418 adapter->tx_ring[txbase + i]->netdev = vdev;
4419 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4420 }
4421
4422 queues = min_t(unsigned int,
4423 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4424 err = netif_set_real_num_tx_queues(vdev, queues);
4425 if (err)
4426 goto fwd_queue_err;
4427
4428 err = netif_set_real_num_rx_queues(vdev, queues);
4429 if (err)
4430 goto fwd_queue_err;
4431
4432 if (is_valid_ether_addr(vdev->dev_addr))
4433 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4434
4435 ixgbe_fwd_psrtype(accel);
4436 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4437 return err;
4438 fwd_queue_err:
4439 ixgbe_fwd_ring_down(vdev, accel);
4440 return err;
4441 }
4442
4443 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4444 {
4445 struct net_device *upper;
4446 struct list_head *iter;
4447 int err;
4448
4449 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4450 if (netif_is_macvlan(upper)) {
4451 struct macvlan_dev *dfwd = netdev_priv(upper);
4452 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4453
4454 if (dfwd->fwd_priv) {
4455 err = ixgbe_fwd_ring_up(upper, vadapter);
4456 if (err)
4457 continue;
4458 }
4459 }
4460 }
4461 }
4462
4463 static void ixgbe_configure(struct ixgbe_adapter *adapter)
4464 {
4465 struct ixgbe_hw *hw = &adapter->hw;
4466
4467 ixgbe_configure_pb(adapter);
4468 #ifdef CONFIG_IXGBE_DCB
4469 ixgbe_configure_dcb(adapter);
4470 #endif
4471 /*
4472 * We must restore virtualization before VLANs or else
4473 * the VLVF registers will not be populated
4474 */
4475 ixgbe_configure_virtualization(adapter);
4476
4477 ixgbe_set_rx_mode(adapter->netdev);
4478 ixgbe_restore_vlan(adapter);
4479
4480 switch (hw->mac.type) {
4481 case ixgbe_mac_82599EB:
4482 case ixgbe_mac_X540:
4483 hw->mac.ops.disable_rx_buff(hw);
4484 break;
4485 default:
4486 break;
4487 }
4488
4489 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4490 ixgbe_init_fdir_signature_82599(&adapter->hw,
4491 adapter->fdir_pballoc);
4492 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4493 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4494 adapter->fdir_pballoc);
4495 ixgbe_fdir_filter_restore(adapter);
4496 }
4497
4498 switch (hw->mac.type) {
4499 case ixgbe_mac_82599EB:
4500 case ixgbe_mac_X540:
4501 hw->mac.ops.enable_rx_buff(hw);
4502 break;
4503 default:
4504 break;
4505 }
4506
4507 #ifdef IXGBE_FCOE
4508 /* configure FCoE L2 filters, redirection table, and Rx control */
4509 ixgbe_configure_fcoe(adapter);
4510
4511 #endif /* IXGBE_FCOE */
4512 ixgbe_configure_tx(adapter);
4513 ixgbe_configure_rx(adapter);
4514 ixgbe_configure_dfwd(adapter);
4515 }
4516
4517 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4518 {
4519 switch (hw->phy.type) {
4520 case ixgbe_phy_sfp_avago:
4521 case ixgbe_phy_sfp_ftl:
4522 case ixgbe_phy_sfp_intel:
4523 case ixgbe_phy_sfp_unknown:
4524 case ixgbe_phy_sfp_passive_tyco:
4525 case ixgbe_phy_sfp_passive_unknown:
4526 case ixgbe_phy_sfp_active_unknown:
4527 case ixgbe_phy_sfp_ftl_active:
4528 case ixgbe_phy_qsfp_passive_unknown:
4529 case ixgbe_phy_qsfp_active_unknown:
4530 case ixgbe_phy_qsfp_intel:
4531 case ixgbe_phy_qsfp_unknown:
4532 /* ixgbe_phy_none is set when no SFP module is present */
4533 case ixgbe_phy_none:
4534 return true;
4535 case ixgbe_phy_nl:
4536 if (hw->mac.type == ixgbe_mac_82598EB)
4537 return true;
4538 default:
4539 return false;
4540 }
4541 }
4542
4543 /**
4544 * ixgbe_sfp_link_config - set up SFP+ link
4545 * @adapter: pointer to private adapter struct
4546 **/
4547 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4548 {
4549 /*
4550 * We are assuming the worst case scenario here, and that
4551 * is that an SFP was inserted/removed after the reset
4552 * but before SFP detection was enabled. As such the best
4553 * solution is to just start searching as soon as we start
4554 */
4555 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4556 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4557
4558 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4559 }
4560
4561 /**
4562 * ixgbe_non_sfp_link_config - set up non-SFP+ link
4563 * @hw: pointer to private hardware struct
4564 *
4565 * Returns 0 on success, negative on failure
4566 **/
4567 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4568 {
4569 u32 speed;
4570 bool autoneg, link_up = false;
4571 u32 ret = IXGBE_ERR_LINK_SETUP;
4572
4573 if (hw->mac.ops.check_link)
4574 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
4575
4576 if (ret)
4577 return ret;
4578
4579 speed = hw->phy.autoneg_advertised;
4580 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4581 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4582 &autoneg);
4583 if (ret)
4584 return ret;
4585
4586 if (hw->mac.ops.setup_link)
4587 ret = hw->mac.ops.setup_link(hw, speed, link_up);
4588
4589 return ret;
4590 }
4591
4592 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4593 {
4594 struct ixgbe_hw *hw = &adapter->hw;
4595 u32 gpie = 0;
4596
4597 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4598 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4599 IXGBE_GPIE_OCD;
4600 gpie |= IXGBE_GPIE_EIAME;
4601 /*
4602 * use EIAM to auto-mask when MSI-X interrupt is asserted
4603 * this saves a register write for every interrupt
4604 */
4605 switch (hw->mac.type) {
4606 case ixgbe_mac_82598EB:
4607 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4608 break;
4609 case ixgbe_mac_82599EB:
4610 case ixgbe_mac_X540:
4611 default:
4612 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4613 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4614 break;
4615 }
4616 } else {
4617 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4618 * specifically only auto mask tx and rx interrupts */
4619 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4620 }
4621
4622 /* XXX: to interrupt immediately for EICS writes, enable this */
4623 /* gpie |= IXGBE_GPIE_EIMEN; */
4624
4625 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4626 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4627
4628 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4629 case IXGBE_82599_VMDQ_8Q_MASK:
4630 gpie |= IXGBE_GPIE_VTMODE_16;
4631 break;
4632 case IXGBE_82599_VMDQ_4Q_MASK:
4633 gpie |= IXGBE_GPIE_VTMODE_32;
4634 break;
4635 default:
4636 gpie |= IXGBE_GPIE_VTMODE_64;
4637 break;
4638 }
4639 }
4640
4641 /* Enable Thermal over heat sensor interrupt */
4642 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4643 switch (adapter->hw.mac.type) {
4644 case ixgbe_mac_82599EB:
4645 gpie |= IXGBE_SDP0_GPIEN;
4646 break;
4647 case ixgbe_mac_X540:
4648 gpie |= IXGBE_EIMS_TS;
4649 break;
4650 default:
4651 break;
4652 }
4653 }
4654
4655 /* Enable fan failure interrupt */
4656 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4657 gpie |= IXGBE_SDP1_GPIEN;
4658
4659 if (hw->mac.type == ixgbe_mac_82599EB) {
4660 gpie |= IXGBE_SDP1_GPIEN;
4661 gpie |= IXGBE_SDP2_GPIEN;
4662 }
4663
4664 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4665 }
4666
4667 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4668 {
4669 struct ixgbe_hw *hw = &adapter->hw;
4670 int err;
4671 u32 ctrl_ext;
4672
4673 ixgbe_get_hw_control(adapter);
4674 ixgbe_setup_gpie(adapter);
4675
4676 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4677 ixgbe_configure_msix(adapter);
4678 else
4679 ixgbe_configure_msi_and_legacy(adapter);
4680
4681 /* enable the optics for 82599 SFP+ fiber */
4682 if (hw->mac.ops.enable_tx_laser)
4683 hw->mac.ops.enable_tx_laser(hw);
4684
4685 smp_mb__before_atomic();
4686 clear_bit(__IXGBE_DOWN, &adapter->state);
4687 ixgbe_napi_enable_all(adapter);
4688
4689 if (ixgbe_is_sfp(hw)) {
4690 ixgbe_sfp_link_config(adapter);
4691 } else {
4692 err = ixgbe_non_sfp_link_config(hw);
4693 if (err)
4694 e_err(probe, "link_config FAILED %d\n", err);
4695 }
4696
4697 /* clear any pending interrupts, may auto mask */
4698 IXGBE_READ_REG(hw, IXGBE_EICR);
4699 ixgbe_irq_enable(adapter, true, true);
4700
4701 /*
4702 * If this adapter has a fan, check to see if we had a failure
4703 * before we enabled the interrupt.
4704 */
4705 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4706 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4707 if (esdp & IXGBE_ESDP_SDP1)
4708 e_crit(drv, "Fan has stopped, replace the adapter\n");
4709 }
4710
4711 /* bring the link up in the watchdog, this could race with our first
4712 * link up interrupt but shouldn't be a problem */
4713 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4714 adapter->link_check_timeout = jiffies;
4715 mod_timer(&adapter->service_timer, jiffies);
4716
4717 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4718 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4719 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4720 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4721 }
4722
4723 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4724 {
4725 WARN_ON(in_interrupt());
4726 /* put off any impending NetWatchDogTimeout */
4727 adapter->netdev->trans_start = jiffies;
4728
4729 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4730 usleep_range(1000, 2000);
4731 ixgbe_down(adapter);
4732 /*
4733 * If SR-IOV enabled then wait a bit before bringing the adapter
4734 * back up to give the VFs time to respond to the reset. The
4735 * two second wait is based upon the watchdog timer cycle in
4736 * the VF driver.
4737 */
4738 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4739 msleep(2000);
4740 ixgbe_up(adapter);
4741 clear_bit(__IXGBE_RESETTING, &adapter->state);
4742 }
4743
4744 void ixgbe_up(struct ixgbe_adapter *adapter)
4745 {
4746 /* hardware has been reset, we need to reload some things */
4747 ixgbe_configure(adapter);
4748
4749 ixgbe_up_complete(adapter);
4750 }
4751
4752 void ixgbe_reset(struct ixgbe_adapter *adapter)
4753 {
4754 struct ixgbe_hw *hw = &adapter->hw;
4755 struct net_device *netdev = adapter->netdev;
4756 int err;
4757 u8 old_addr[ETH_ALEN];
4758
4759 if (ixgbe_removed(hw->hw_addr))
4760 return;
4761 /* lock SFP init bit to prevent race conditions with the watchdog */
4762 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4763 usleep_range(1000, 2000);
4764
4765 /* clear all SFP and link config related flags while holding SFP_INIT */
4766 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4767 IXGBE_FLAG2_SFP_NEEDS_RESET);
4768 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4769
4770 err = hw->mac.ops.init_hw(hw);
4771 switch (err) {
4772 case 0:
4773 case IXGBE_ERR_SFP_NOT_PRESENT:
4774 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4775 break;
4776 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4777 e_dev_err("master disable timed out\n");
4778 break;
4779 case IXGBE_ERR_EEPROM_VERSION:
4780 /* We are running on a pre-production device, log a warning */
4781 e_dev_warn("This device is a pre-production adapter/LOM. "
4782 "Please be aware there may be issues associated with "
4783 "your hardware. If you are experiencing problems "
4784 "please contact your Intel or hardware "
4785 "representative who provided you with this "
4786 "hardware.\n");
4787 break;
4788 default:
4789 e_dev_err("Hardware Error: %d\n", err);
4790 }
4791
4792 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4793 /* do not flush user set addresses */
4794 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len);
4795 ixgbe_flush_sw_mac_table(adapter);
4796 ixgbe_mac_set_default_filter(adapter, old_addr);
4797
4798 /* update SAN MAC vmdq pool selection */
4799 if (hw->mac.san_mac_rar_index)
4800 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4801
4802 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
4803 ixgbe_ptp_reset(adapter);
4804 }
4805
4806 /**
4807 * ixgbe_clean_tx_ring - Free Tx Buffers
4808 * @tx_ring: ring to be cleaned
4809 **/
4810 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4811 {
4812 struct ixgbe_tx_buffer *tx_buffer_info;
4813 unsigned long size;
4814 u16 i;
4815
4816 /* ring already cleared, nothing to do */
4817 if (!tx_ring->tx_buffer_info)
4818 return;
4819
4820 /* Free all the Tx ring sk_buffs */
4821 for (i = 0; i < tx_ring->count; i++) {
4822 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4823 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4824 }
4825
4826 netdev_tx_reset_queue(txring_txq(tx_ring));
4827
4828 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4829 memset(tx_ring->tx_buffer_info, 0, size);
4830
4831 /* Zero out the descriptor ring */
4832 memset(tx_ring->desc, 0, tx_ring->size);
4833
4834 tx_ring->next_to_use = 0;
4835 tx_ring->next_to_clean = 0;
4836 }
4837
4838 /**
4839 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4840 * @adapter: board private structure
4841 **/
4842 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4843 {
4844 int i;
4845
4846 for (i = 0; i < adapter->num_rx_queues; i++)
4847 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4848 }
4849
4850 /**
4851 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4852 * @adapter: board private structure
4853 **/
4854 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4855 {
4856 int i;
4857
4858 for (i = 0; i < adapter->num_tx_queues; i++)
4859 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4860 }
4861
4862 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4863 {
4864 struct hlist_node *node2;
4865 struct ixgbe_fdir_filter *filter;
4866
4867 spin_lock(&adapter->fdir_perfect_lock);
4868
4869 hlist_for_each_entry_safe(filter, node2,
4870 &adapter->fdir_filter_list, fdir_node) {
4871 hlist_del(&filter->fdir_node);
4872 kfree(filter);
4873 }
4874 adapter->fdir_filter_count = 0;
4875
4876 spin_unlock(&adapter->fdir_perfect_lock);
4877 }
4878
4879 void ixgbe_down(struct ixgbe_adapter *adapter)
4880 {
4881 struct net_device *netdev = adapter->netdev;
4882 struct ixgbe_hw *hw = &adapter->hw;
4883 struct net_device *upper;
4884 struct list_head *iter;
4885 u32 rxctrl;
4886 int i;
4887
4888 /* signal that we are down to the interrupt handler */
4889 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
4890 return; /* do nothing if already down */
4891
4892 /* disable receives */
4893 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4894 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4895
4896 /* disable all enabled rx queues */
4897 for (i = 0; i < adapter->num_rx_queues; i++)
4898 /* this call also flushes the previous write */
4899 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4900
4901 usleep_range(10000, 20000);
4902
4903 netif_tx_stop_all_queues(netdev);
4904
4905 /* call carrier off first to avoid false dev_watchdog timeouts */
4906 netif_carrier_off(netdev);
4907 netif_tx_disable(netdev);
4908
4909 /* disable any upper devices */
4910 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4911 if (netif_is_macvlan(upper)) {
4912 struct macvlan_dev *vlan = netdev_priv(upper);
4913
4914 if (vlan->fwd_priv) {
4915 netif_tx_stop_all_queues(upper);
4916 netif_carrier_off(upper);
4917 netif_tx_disable(upper);
4918 }
4919 }
4920 }
4921
4922 ixgbe_irq_disable(adapter);
4923
4924 ixgbe_napi_disable_all(adapter);
4925
4926 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4927 IXGBE_FLAG2_RESET_REQUESTED);
4928 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4929
4930 del_timer_sync(&adapter->service_timer);
4931
4932 if (adapter->num_vfs) {
4933 /* Clear EITR Select mapping */
4934 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4935
4936 /* Mark all the VFs as inactive */
4937 for (i = 0 ; i < adapter->num_vfs; i++)
4938 adapter->vfinfo[i].clear_to_send = false;
4939
4940 /* ping all the active vfs to let them know we are going down */
4941 ixgbe_ping_all_vfs(adapter);
4942
4943 /* Disable all VFTE/VFRE TX/RX */
4944 ixgbe_disable_tx_rx(adapter);
4945 }
4946
4947 /* disable transmits in the hardware now that interrupts are off */
4948 for (i = 0; i < adapter->num_tx_queues; i++) {
4949 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4950 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4951 }
4952
4953 /* Disable the Tx DMA engine on 82599 and X540 */
4954 switch (hw->mac.type) {
4955 case ixgbe_mac_82599EB:
4956 case ixgbe_mac_X540:
4957 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4958 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4959 ~IXGBE_DMATXCTL_TE));
4960 break;
4961 default:
4962 break;
4963 }
4964
4965 if (!pci_channel_offline(adapter->pdev))
4966 ixgbe_reset(adapter);
4967
4968 /* power down the optics for 82599 SFP+ fiber */
4969 if (hw->mac.ops.disable_tx_laser)
4970 hw->mac.ops.disable_tx_laser(hw);
4971
4972 ixgbe_clean_all_tx_rings(adapter);
4973 ixgbe_clean_all_rx_rings(adapter);
4974
4975 #ifdef CONFIG_IXGBE_DCA
4976 /* since we reset the hardware DCA settings were cleared */
4977 ixgbe_setup_dca(adapter);
4978 #endif
4979 }
4980
4981 /**
4982 * ixgbe_tx_timeout - Respond to a Tx Hang
4983 * @netdev: network interface device structure
4984 **/
4985 static void ixgbe_tx_timeout(struct net_device *netdev)
4986 {
4987 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4988
4989 /* Do the reset outside of interrupt context */
4990 ixgbe_tx_timeout_reset(adapter);
4991 }
4992
4993 /**
4994 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4995 * @adapter: board private structure to initialize
4996 *
4997 * ixgbe_sw_init initializes the Adapter private data structure.
4998 * Fields are initialized based on PCI device information and
4999 * OS network device settings (MTU size).
5000 **/
5001 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
5002 {
5003 struct ixgbe_hw *hw = &adapter->hw;
5004 struct pci_dev *pdev = adapter->pdev;
5005 unsigned int rss, fdir;
5006 u32 fwsm;
5007 #ifdef CONFIG_IXGBE_DCB
5008 int j;
5009 struct tc_configuration *tc;
5010 #endif
5011
5012 /* PCI config space info */
5013
5014 hw->vendor_id = pdev->vendor;
5015 hw->device_id = pdev->device;
5016 hw->revision_id = pdev->revision;
5017 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5018 hw->subsystem_device_id = pdev->subsystem_device;
5019
5020 /* Set common capability flags and settings */
5021 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
5022 adapter->ring_feature[RING_F_RSS].limit = rss;
5023 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5024 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5025 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5026 adapter->atr_sample_rate = 20;
5027 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5028 adapter->ring_feature[RING_F_FDIR].limit = fdir;
5029 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5030 #ifdef CONFIG_IXGBE_DCA
5031 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5032 #endif
5033 #ifdef IXGBE_FCOE
5034 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5035 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5036 #ifdef CONFIG_IXGBE_DCB
5037 /* Default traffic class to use for FCoE */
5038 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5039 #endif /* CONFIG_IXGBE_DCB */
5040 #endif /* IXGBE_FCOE */
5041
5042 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5043 hw->mac.num_rar_entries,
5044 GFP_ATOMIC);
5045
5046 /* Set MAC specific capability flags and exceptions */
5047 switch (hw->mac.type) {
5048 case ixgbe_mac_82598EB:
5049 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5050 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5051
5052 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5053 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5054
5055 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
5056 adapter->ring_feature[RING_F_FDIR].limit = 0;
5057 adapter->atr_sample_rate = 0;
5058 adapter->fdir_pballoc = 0;
5059 #ifdef IXGBE_FCOE
5060 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5061 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5062 #ifdef CONFIG_IXGBE_DCB
5063 adapter->fcoe.up = 0;
5064 #endif /* IXGBE_DCB */
5065 #endif /* IXGBE_FCOE */
5066 break;
5067 case ixgbe_mac_82599EB:
5068 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5069 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5070 break;
5071 case ixgbe_mac_X540:
5072 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
5073 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5074 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5075 break;
5076 default:
5077 break;
5078 }
5079
5080 #ifdef IXGBE_FCOE
5081 /* FCoE support exists, always init the FCoE lock */
5082 spin_lock_init(&adapter->fcoe.lock);
5083
5084 #endif
5085 /* n-tuple support exists, always init our spinlock */
5086 spin_lock_init(&adapter->fdir_perfect_lock);
5087
5088 #ifdef CONFIG_IXGBE_DCB
5089 switch (hw->mac.type) {
5090 case ixgbe_mac_X540:
5091 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5092 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5093 break;
5094 default:
5095 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5096 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5097 break;
5098 }
5099
5100 /* Configure DCB traffic classes */
5101 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5102 tc = &adapter->dcb_cfg.tc_config[j];
5103 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5104 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5105 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5106 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5107 tc->dcb_pfc = pfc_disabled;
5108 }
5109
5110 /* Initialize default user to priority mapping, UPx->TC0 */
5111 tc = &adapter->dcb_cfg.tc_config[0];
5112 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5113 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5114
5115 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5116 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5117 adapter->dcb_cfg.pfc_mode_enable = false;
5118 adapter->dcb_set_bitmap = 0x00;
5119 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5120 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5121 sizeof(adapter->temp_dcb_cfg));
5122
5123 #endif
5124
5125 /* default flow control settings */
5126 hw->fc.requested_mode = ixgbe_fc_full;
5127 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5128 ixgbe_pbthresh_setup(adapter);
5129 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5130 hw->fc.send_xon = true;
5131 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
5132
5133 #ifdef CONFIG_PCI_IOV
5134 if (max_vfs > 0)
5135 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5136
5137 /* assign number of SR-IOV VFs */
5138 if (hw->mac.type != ixgbe_mac_82598EB) {
5139 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
5140 adapter->num_vfs = 0;
5141 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5142 } else {
5143 adapter->num_vfs = max_vfs;
5144 }
5145 }
5146 #endif /* CONFIG_PCI_IOV */
5147
5148 /* enable itr by default in dynamic mode */
5149 adapter->rx_itr_setting = 1;
5150 adapter->tx_itr_setting = 1;
5151
5152 /* set default ring sizes */
5153 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5154 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5155
5156 /* set default work limits */
5157 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5158
5159 /* initialize eeprom parameters */
5160 if (ixgbe_init_eeprom_params_generic(hw)) {
5161 e_dev_err("EEPROM initialization failed\n");
5162 return -EIO;
5163 }
5164
5165 /* PF holds first pool slot */
5166 set_bit(0, &adapter->fwd_bitmask);
5167 set_bit(__IXGBE_DOWN, &adapter->state);
5168
5169 return 0;
5170 }
5171
5172 /**
5173 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5174 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5175 *
5176 * Return 0 on success, negative on failure
5177 **/
5178 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5179 {
5180 struct device *dev = tx_ring->dev;
5181 int orig_node = dev_to_node(dev);
5182 int ring_node = -1;
5183 int size;
5184
5185 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5186
5187 if (tx_ring->q_vector)
5188 ring_node = tx_ring->q_vector->numa_node;
5189
5190 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
5191 if (!tx_ring->tx_buffer_info)
5192 tx_ring->tx_buffer_info = vzalloc(size);
5193 if (!tx_ring->tx_buffer_info)
5194 goto err;
5195
5196 u64_stats_init(&tx_ring->syncp);
5197
5198 /* round up to nearest 4K */
5199 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5200 tx_ring->size = ALIGN(tx_ring->size, 4096);
5201
5202 set_dev_node(dev, ring_node);
5203 tx_ring->desc = dma_alloc_coherent(dev,
5204 tx_ring->size,
5205 &tx_ring->dma,
5206 GFP_KERNEL);
5207 set_dev_node(dev, orig_node);
5208 if (!tx_ring->desc)
5209 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5210 &tx_ring->dma, GFP_KERNEL);
5211 if (!tx_ring->desc)
5212 goto err;
5213
5214 tx_ring->next_to_use = 0;
5215 tx_ring->next_to_clean = 0;
5216 return 0;
5217
5218 err:
5219 vfree(tx_ring->tx_buffer_info);
5220 tx_ring->tx_buffer_info = NULL;
5221 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5222 return -ENOMEM;
5223 }
5224
5225 /**
5226 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5227 * @adapter: board private structure
5228 *
5229 * If this function returns with an error, then it's possible one or
5230 * more of the rings is populated (while the rest are not). It is the
5231 * callers duty to clean those orphaned rings.
5232 *
5233 * Return 0 on success, negative on failure
5234 **/
5235 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5236 {
5237 int i, err = 0;
5238
5239 for (i = 0; i < adapter->num_tx_queues; i++) {
5240 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5241 if (!err)
5242 continue;
5243
5244 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5245 goto err_setup_tx;
5246 }
5247
5248 return 0;
5249 err_setup_tx:
5250 /* rewind the index freeing the rings as we go */
5251 while (i--)
5252 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5253 return err;
5254 }
5255
5256 /**
5257 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5258 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5259 *
5260 * Returns 0 on success, negative on failure
5261 **/
5262 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5263 {
5264 struct device *dev = rx_ring->dev;
5265 int orig_node = dev_to_node(dev);
5266 int ring_node = -1;
5267 int size;
5268
5269 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5270
5271 if (rx_ring->q_vector)
5272 ring_node = rx_ring->q_vector->numa_node;
5273
5274 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
5275 if (!rx_ring->rx_buffer_info)
5276 rx_ring->rx_buffer_info = vzalloc(size);
5277 if (!rx_ring->rx_buffer_info)
5278 goto err;
5279
5280 u64_stats_init(&rx_ring->syncp);
5281
5282 /* Round up to nearest 4K */
5283 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5284 rx_ring->size = ALIGN(rx_ring->size, 4096);
5285
5286 set_dev_node(dev, ring_node);
5287 rx_ring->desc = dma_alloc_coherent(dev,
5288 rx_ring->size,
5289 &rx_ring->dma,
5290 GFP_KERNEL);
5291 set_dev_node(dev, orig_node);
5292 if (!rx_ring->desc)
5293 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5294 &rx_ring->dma, GFP_KERNEL);
5295 if (!rx_ring->desc)
5296 goto err;
5297
5298 rx_ring->next_to_clean = 0;
5299 rx_ring->next_to_use = 0;
5300
5301 return 0;
5302 err:
5303 vfree(rx_ring->rx_buffer_info);
5304 rx_ring->rx_buffer_info = NULL;
5305 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5306 return -ENOMEM;
5307 }
5308
5309 /**
5310 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5311 * @adapter: board private structure
5312 *
5313 * If this function returns with an error, then it's possible one or
5314 * more of the rings is populated (while the rest are not). It is the
5315 * callers duty to clean those orphaned rings.
5316 *
5317 * Return 0 on success, negative on failure
5318 **/
5319 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5320 {
5321 int i, err = 0;
5322
5323 for (i = 0; i < adapter->num_rx_queues; i++) {
5324 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5325 if (!err)
5326 continue;
5327
5328 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5329 goto err_setup_rx;
5330 }
5331
5332 #ifdef IXGBE_FCOE
5333 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5334 if (!err)
5335 #endif
5336 return 0;
5337 err_setup_rx:
5338 /* rewind the index freeing the rings as we go */
5339 while (i--)
5340 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5341 return err;
5342 }
5343
5344 /**
5345 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5346 * @tx_ring: Tx descriptor ring for a specific queue
5347 *
5348 * Free all transmit software resources
5349 **/
5350 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5351 {
5352 ixgbe_clean_tx_ring(tx_ring);
5353
5354 vfree(tx_ring->tx_buffer_info);
5355 tx_ring->tx_buffer_info = NULL;
5356
5357 /* if not set, then don't free */
5358 if (!tx_ring->desc)
5359 return;
5360
5361 dma_free_coherent(tx_ring->dev, tx_ring->size,
5362 tx_ring->desc, tx_ring->dma);
5363
5364 tx_ring->desc = NULL;
5365 }
5366
5367 /**
5368 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5369 * @adapter: board private structure
5370 *
5371 * Free all transmit software resources
5372 **/
5373 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5374 {
5375 int i;
5376
5377 for (i = 0; i < adapter->num_tx_queues; i++)
5378 if (adapter->tx_ring[i]->desc)
5379 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5380 }
5381
5382 /**
5383 * ixgbe_free_rx_resources - Free Rx Resources
5384 * @rx_ring: ring to clean the resources from
5385 *
5386 * Free all receive software resources
5387 **/
5388 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5389 {
5390 ixgbe_clean_rx_ring(rx_ring);
5391
5392 vfree(rx_ring->rx_buffer_info);
5393 rx_ring->rx_buffer_info = NULL;
5394
5395 /* if not set, then don't free */
5396 if (!rx_ring->desc)
5397 return;
5398
5399 dma_free_coherent(rx_ring->dev, rx_ring->size,
5400 rx_ring->desc, rx_ring->dma);
5401
5402 rx_ring->desc = NULL;
5403 }
5404
5405 /**
5406 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5407 * @adapter: board private structure
5408 *
5409 * Free all receive software resources
5410 **/
5411 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5412 {
5413 int i;
5414
5415 #ifdef IXGBE_FCOE
5416 ixgbe_free_fcoe_ddp_resources(adapter);
5417
5418 #endif
5419 for (i = 0; i < adapter->num_rx_queues; i++)
5420 if (adapter->rx_ring[i]->desc)
5421 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5422 }
5423
5424 /**
5425 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5426 * @netdev: network interface device structure
5427 * @new_mtu: new value for maximum frame size
5428 *
5429 * Returns 0 on success, negative on failure
5430 **/
5431 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5432 {
5433 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5434 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5435
5436 /* MTU < 68 is an error and causes problems on some kernels */
5437 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5438 return -EINVAL;
5439
5440 /*
5441 * For 82599EB we cannot allow legacy VFs to enable their receive
5442 * paths when MTU greater than 1500 is configured. So display a
5443 * warning that legacy VFs will be disabled.
5444 */
5445 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5446 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
5447 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
5448 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
5449
5450 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5451
5452 /* must set new MTU before calling down or up */
5453 netdev->mtu = new_mtu;
5454
5455 if (netif_running(netdev))
5456 ixgbe_reinit_locked(adapter);
5457
5458 return 0;
5459 }
5460
5461 /**
5462 * ixgbe_open - Called when a network interface is made active
5463 * @netdev: network interface device structure
5464 *
5465 * Returns 0 on success, negative value on failure
5466 *
5467 * The open entry point is called when a network interface is made
5468 * active by the system (IFF_UP). At this point all resources needed
5469 * for transmit and receive operations are allocated, the interrupt
5470 * handler is registered with the OS, the watchdog timer is started,
5471 * and the stack is notified that the interface is ready.
5472 **/
5473 static int ixgbe_open(struct net_device *netdev)
5474 {
5475 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5476 int err, queues;
5477
5478 /* disallow open during test */
5479 if (test_bit(__IXGBE_TESTING, &adapter->state))
5480 return -EBUSY;
5481
5482 netif_carrier_off(netdev);
5483
5484 /* allocate transmit descriptors */
5485 err = ixgbe_setup_all_tx_resources(adapter);
5486 if (err)
5487 goto err_setup_tx;
5488
5489 /* allocate receive descriptors */
5490 err = ixgbe_setup_all_rx_resources(adapter);
5491 if (err)
5492 goto err_setup_rx;
5493
5494 ixgbe_configure(adapter);
5495
5496 err = ixgbe_request_irq(adapter);
5497 if (err)
5498 goto err_req_irq;
5499
5500 /* Notify the stack of the actual queue counts. */
5501 if (adapter->num_rx_pools > 1)
5502 queues = adapter->num_rx_queues_per_pool;
5503 else
5504 queues = adapter->num_tx_queues;
5505
5506 err = netif_set_real_num_tx_queues(netdev, queues);
5507 if (err)
5508 goto err_set_queues;
5509
5510 if (adapter->num_rx_pools > 1 &&
5511 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5512 queues = IXGBE_MAX_L2A_QUEUES;
5513 else
5514 queues = adapter->num_rx_queues;
5515 err = netif_set_real_num_rx_queues(netdev, queues);
5516 if (err)
5517 goto err_set_queues;
5518
5519 ixgbe_ptp_init(adapter);
5520
5521 ixgbe_up_complete(adapter);
5522
5523 return 0;
5524
5525 err_set_queues:
5526 ixgbe_free_irq(adapter);
5527 err_req_irq:
5528 ixgbe_free_all_rx_resources(adapter);
5529 err_setup_rx:
5530 ixgbe_free_all_tx_resources(adapter);
5531 err_setup_tx:
5532 ixgbe_reset(adapter);
5533
5534 return err;
5535 }
5536
5537 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5538 {
5539 ixgbe_ptp_suspend(adapter);
5540
5541 ixgbe_down(adapter);
5542 ixgbe_free_irq(adapter);
5543
5544 ixgbe_free_all_tx_resources(adapter);
5545 ixgbe_free_all_rx_resources(adapter);
5546 }
5547
5548 /**
5549 * ixgbe_close - Disables a network interface
5550 * @netdev: network interface device structure
5551 *
5552 * Returns 0, this is not allowed to fail
5553 *
5554 * The close entry point is called when an interface is de-activated
5555 * by the OS. The hardware is still under the drivers control, but
5556 * needs to be disabled. A global MAC reset is issued to stop the
5557 * hardware, and all transmit and receive resources are freed.
5558 **/
5559 static int ixgbe_close(struct net_device *netdev)
5560 {
5561 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5562
5563 ixgbe_ptp_stop(adapter);
5564
5565 ixgbe_close_suspend(adapter);
5566
5567 ixgbe_fdir_filter_exit(adapter);
5568
5569 ixgbe_release_hw_control(adapter);
5570
5571 return 0;
5572 }
5573
5574 #ifdef CONFIG_PM
5575 static int ixgbe_resume(struct pci_dev *pdev)
5576 {
5577 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5578 struct net_device *netdev = adapter->netdev;
5579 u32 err;
5580
5581 adapter->hw.hw_addr = adapter->io_addr;
5582 pci_set_power_state(pdev, PCI_D0);
5583 pci_restore_state(pdev);
5584 /*
5585 * pci_restore_state clears dev->state_saved so call
5586 * pci_save_state to restore it.
5587 */
5588 pci_save_state(pdev);
5589
5590 err = pci_enable_device_mem(pdev);
5591 if (err) {
5592 e_dev_err("Cannot enable PCI device from suspend\n");
5593 return err;
5594 }
5595 smp_mb__before_atomic();
5596 clear_bit(__IXGBE_DISABLED, &adapter->state);
5597 pci_set_master(pdev);
5598
5599 pci_wake_from_d3(pdev, false);
5600
5601 ixgbe_reset(adapter);
5602
5603 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5604
5605 rtnl_lock();
5606 err = ixgbe_init_interrupt_scheme(adapter);
5607 if (!err && netif_running(netdev))
5608 err = ixgbe_open(netdev);
5609
5610 rtnl_unlock();
5611
5612 if (err)
5613 return err;
5614
5615 netif_device_attach(netdev);
5616
5617 return 0;
5618 }
5619 #endif /* CONFIG_PM */
5620
5621 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5622 {
5623 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5624 struct net_device *netdev = adapter->netdev;
5625 struct ixgbe_hw *hw = &adapter->hw;
5626 u32 ctrl, fctrl;
5627 u32 wufc = adapter->wol;
5628 #ifdef CONFIG_PM
5629 int retval = 0;
5630 #endif
5631
5632 netif_device_detach(netdev);
5633
5634 rtnl_lock();
5635 if (netif_running(netdev))
5636 ixgbe_close_suspend(adapter);
5637 rtnl_unlock();
5638
5639 ixgbe_clear_interrupt_scheme(adapter);
5640
5641 #ifdef CONFIG_PM
5642 retval = pci_save_state(pdev);
5643 if (retval)
5644 return retval;
5645
5646 #endif
5647 if (hw->mac.ops.stop_link_on_d3)
5648 hw->mac.ops.stop_link_on_d3(hw);
5649
5650 if (wufc) {
5651 ixgbe_set_rx_mode(netdev);
5652
5653 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5654 if (hw->mac.ops.enable_tx_laser)
5655 hw->mac.ops.enable_tx_laser(hw);
5656
5657 /* turn on all-multi mode if wake on multicast is enabled */
5658 if (wufc & IXGBE_WUFC_MC) {
5659 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5660 fctrl |= IXGBE_FCTRL_MPE;
5661 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5662 }
5663
5664 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5665 ctrl |= IXGBE_CTRL_GIO_DIS;
5666 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5667
5668 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5669 } else {
5670 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5671 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5672 }
5673
5674 switch (hw->mac.type) {
5675 case ixgbe_mac_82598EB:
5676 pci_wake_from_d3(pdev, false);
5677 break;
5678 case ixgbe_mac_82599EB:
5679 case ixgbe_mac_X540:
5680 pci_wake_from_d3(pdev, !!wufc);
5681 break;
5682 default:
5683 break;
5684 }
5685
5686 *enable_wake = !!wufc;
5687
5688 ixgbe_release_hw_control(adapter);
5689
5690 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
5691 pci_disable_device(pdev);
5692
5693 return 0;
5694 }
5695
5696 #ifdef CONFIG_PM
5697 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5698 {
5699 int retval;
5700 bool wake;
5701
5702 retval = __ixgbe_shutdown(pdev, &wake);
5703 if (retval)
5704 return retval;
5705
5706 if (wake) {
5707 pci_prepare_to_sleep(pdev);
5708 } else {
5709 pci_wake_from_d3(pdev, false);
5710 pci_set_power_state(pdev, PCI_D3hot);
5711 }
5712
5713 return 0;
5714 }
5715 #endif /* CONFIG_PM */
5716
5717 static void ixgbe_shutdown(struct pci_dev *pdev)
5718 {
5719 bool wake;
5720
5721 __ixgbe_shutdown(pdev, &wake);
5722
5723 if (system_state == SYSTEM_POWER_OFF) {
5724 pci_wake_from_d3(pdev, wake);
5725 pci_set_power_state(pdev, PCI_D3hot);
5726 }
5727 }
5728
5729 /**
5730 * ixgbe_update_stats - Update the board statistics counters.
5731 * @adapter: board private structure
5732 **/
5733 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5734 {
5735 struct net_device *netdev = adapter->netdev;
5736 struct ixgbe_hw *hw = &adapter->hw;
5737 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5738 u64 total_mpc = 0;
5739 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5740 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5741 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5742 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5743
5744 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5745 test_bit(__IXGBE_RESETTING, &adapter->state))
5746 return;
5747
5748 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5749 u64 rsc_count = 0;
5750 u64 rsc_flush = 0;
5751 for (i = 0; i < adapter->num_rx_queues; i++) {
5752 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5753 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5754 }
5755 adapter->rsc_total_count = rsc_count;
5756 adapter->rsc_total_flush = rsc_flush;
5757 }
5758
5759 for (i = 0; i < adapter->num_rx_queues; i++) {
5760 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5761 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5762 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5763 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5764 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5765 bytes += rx_ring->stats.bytes;
5766 packets += rx_ring->stats.packets;
5767 }
5768 adapter->non_eop_descs = non_eop_descs;
5769 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5770 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5771 adapter->hw_csum_rx_error = hw_csum_rx_error;
5772 netdev->stats.rx_bytes = bytes;
5773 netdev->stats.rx_packets = packets;
5774
5775 bytes = 0;
5776 packets = 0;
5777 /* gather some stats to the adapter struct that are per queue */
5778 for (i = 0; i < adapter->num_tx_queues; i++) {
5779 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5780 restart_queue += tx_ring->tx_stats.restart_queue;
5781 tx_busy += tx_ring->tx_stats.tx_busy;
5782 bytes += tx_ring->stats.bytes;
5783 packets += tx_ring->stats.packets;
5784 }
5785 adapter->restart_queue = restart_queue;
5786 adapter->tx_busy = tx_busy;
5787 netdev->stats.tx_bytes = bytes;
5788 netdev->stats.tx_packets = packets;
5789
5790 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5791
5792 /* 8 register reads */
5793 for (i = 0; i < 8; i++) {
5794 /* for packet buffers not used, the register should read 0 */
5795 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5796 missed_rx += mpc;
5797 hwstats->mpc[i] += mpc;
5798 total_mpc += hwstats->mpc[i];
5799 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5800 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5801 switch (hw->mac.type) {
5802 case ixgbe_mac_82598EB:
5803 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5804 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5805 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5806 hwstats->pxonrxc[i] +=
5807 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5808 break;
5809 case ixgbe_mac_82599EB:
5810 case ixgbe_mac_X540:
5811 hwstats->pxonrxc[i] +=
5812 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5813 break;
5814 default:
5815 break;
5816 }
5817 }
5818
5819 /*16 register reads */
5820 for (i = 0; i < 16; i++) {
5821 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5822 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5823 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5824 (hw->mac.type == ixgbe_mac_X540)) {
5825 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5826 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5827 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5828 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5829 }
5830 }
5831
5832 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5833 /* work around hardware counting issue */
5834 hwstats->gprc -= missed_rx;
5835
5836 ixgbe_update_xoff_received(adapter);
5837
5838 /* 82598 hardware only has a 32 bit counter in the high register */
5839 switch (hw->mac.type) {
5840 case ixgbe_mac_82598EB:
5841 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5842 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5843 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5844 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5845 break;
5846 case ixgbe_mac_X540:
5847 /* OS2BMC stats are X540 only*/
5848 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5849 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5850 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5851 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5852 case ixgbe_mac_82599EB:
5853 for (i = 0; i < 16; i++)
5854 adapter->hw_rx_no_dma_resources +=
5855 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5856 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5857 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5858 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5859 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5860 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5861 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5862 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5863 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5864 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5865 #ifdef IXGBE_FCOE
5866 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5867 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5868 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5869 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5870 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5871 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5872 /* Add up per cpu counters for total ddp aloc fail */
5873 if (adapter->fcoe.ddp_pool) {
5874 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5875 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5876 unsigned int cpu;
5877 u64 noddp = 0, noddp_ext_buff = 0;
5878 for_each_possible_cpu(cpu) {
5879 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5880 noddp += ddp_pool->noddp;
5881 noddp_ext_buff += ddp_pool->noddp_ext_buff;
5882 }
5883 hwstats->fcoe_noddp = noddp;
5884 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
5885 }
5886 #endif /* IXGBE_FCOE */
5887 break;
5888 default:
5889 break;
5890 }
5891 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5892 hwstats->bprc += bprc;
5893 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5894 if (hw->mac.type == ixgbe_mac_82598EB)
5895 hwstats->mprc -= bprc;
5896 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5897 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5898 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5899 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5900 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5901 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5902 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5903 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5904 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5905 hwstats->lxontxc += lxon;
5906 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5907 hwstats->lxofftxc += lxoff;
5908 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5909 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5910 /*
5911 * 82598 errata - tx of flow control packets is included in tx counters
5912 */
5913 xon_off_tot = lxon + lxoff;
5914 hwstats->gptc -= xon_off_tot;
5915 hwstats->mptc -= xon_off_tot;
5916 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5917 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5918 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5919 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5920 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5921 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5922 hwstats->ptc64 -= xon_off_tot;
5923 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5924 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5925 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5926 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5927 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5928 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5929
5930 /* Fill out the OS statistics structure */
5931 netdev->stats.multicast = hwstats->mprc;
5932
5933 /* Rx Errors */
5934 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5935 netdev->stats.rx_dropped = 0;
5936 netdev->stats.rx_length_errors = hwstats->rlec;
5937 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5938 netdev->stats.rx_missed_errors = total_mpc;
5939 }
5940
5941 /**
5942 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5943 * @adapter: pointer to the device adapter structure
5944 **/
5945 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5946 {
5947 struct ixgbe_hw *hw = &adapter->hw;
5948 int i;
5949
5950 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5951 return;
5952
5953 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5954
5955 /* if interface is down do nothing */
5956 if (test_bit(__IXGBE_DOWN, &adapter->state))
5957 return;
5958
5959 /* do nothing if we are not using signature filters */
5960 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5961 return;
5962
5963 adapter->fdir_overflow++;
5964
5965 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5966 for (i = 0; i < adapter->num_tx_queues; i++)
5967 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5968 &(adapter->tx_ring[i]->state));
5969 /* re-enable flow director interrupts */
5970 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5971 } else {
5972 e_err(probe, "failed to finish FDIR re-initialization, "
5973 "ignored adding FDIR ATR filters\n");
5974 }
5975 }
5976
5977 /**
5978 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5979 * @adapter: pointer to the device adapter structure
5980 *
5981 * This function serves two purposes. First it strobes the interrupt lines
5982 * in order to make certain interrupts are occurring. Secondly it sets the
5983 * bits needed to check for TX hangs. As a result we should immediately
5984 * determine if a hang has occurred.
5985 */
5986 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5987 {
5988 struct ixgbe_hw *hw = &adapter->hw;
5989 u64 eics = 0;
5990 int i;
5991
5992 /* If we're down, removing or resetting, just bail */
5993 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5994 test_bit(__IXGBE_REMOVING, &adapter->state) ||
5995 test_bit(__IXGBE_RESETTING, &adapter->state))
5996 return;
5997
5998 /* Force detection of hung controller */
5999 if (netif_carrier_ok(adapter->netdev)) {
6000 for (i = 0; i < adapter->num_tx_queues; i++)
6001 set_check_for_tx_hang(adapter->tx_ring[i]);
6002 }
6003
6004 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6005 /*
6006 * for legacy and MSI interrupts don't set any bits
6007 * that are enabled for EIAM, because this operation
6008 * would set *both* EIMS and EICS for any bit in EIAM
6009 */
6010 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6011 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
6012 } else {
6013 /* get one bit for every active tx/rx interrupt vector */
6014 for (i = 0; i < adapter->num_q_vectors; i++) {
6015 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6016 if (qv->rx.ring || qv->tx.ring)
6017 eics |= ((u64)1 << i);
6018 }
6019 }
6020
6021 /* Cause software interrupt to ensure rings are cleaned */
6022 ixgbe_irq_rearm_queues(adapter, eics);
6023
6024 }
6025
6026 /**
6027 * ixgbe_watchdog_update_link - update the link status
6028 * @adapter: pointer to the device adapter structure
6029 * @link_speed: pointer to a u32 to store the link_speed
6030 **/
6031 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
6032 {
6033 struct ixgbe_hw *hw = &adapter->hw;
6034 u32 link_speed = adapter->link_speed;
6035 bool link_up = adapter->link_up;
6036 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
6037
6038 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6039 return;
6040
6041 if (hw->mac.ops.check_link) {
6042 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6043 } else {
6044 /* always assume link is up, if no check link function */
6045 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6046 link_up = true;
6047 }
6048
6049 if (adapter->ixgbe_ieee_pfc)
6050 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6051
6052 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
6053 hw->mac.ops.fc_enable(hw);
6054 ixgbe_set_rx_drop_en(adapter);
6055 }
6056
6057 if (link_up ||
6058 time_after(jiffies, (adapter->link_check_timeout +
6059 IXGBE_TRY_LINK_TIMEOUT))) {
6060 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6061 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6062 IXGBE_WRITE_FLUSH(hw);
6063 }
6064
6065 adapter->link_up = link_up;
6066 adapter->link_speed = link_speed;
6067 }
6068
6069 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6070 {
6071 #ifdef CONFIG_IXGBE_DCB
6072 struct net_device *netdev = adapter->netdev;
6073 struct dcb_app app = {
6074 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6075 .protocol = 0,
6076 };
6077 u8 up = 0;
6078
6079 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6080 up = dcb_ieee_getapp_mask(netdev, &app);
6081
6082 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6083 #endif
6084 }
6085
6086 /**
6087 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6088 * print link up message
6089 * @adapter: pointer to the device adapter structure
6090 **/
6091 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
6092 {
6093 struct net_device *netdev = adapter->netdev;
6094 struct ixgbe_hw *hw = &adapter->hw;
6095 struct net_device *upper;
6096 struct list_head *iter;
6097 u32 link_speed = adapter->link_speed;
6098 bool flow_rx, flow_tx;
6099
6100 /* only continue if link was previously down */
6101 if (netif_carrier_ok(netdev))
6102 return;
6103
6104 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
6105
6106 switch (hw->mac.type) {
6107 case ixgbe_mac_82598EB: {
6108 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6109 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6110 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6111 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6112 }
6113 break;
6114 case ixgbe_mac_X540:
6115 case ixgbe_mac_82599EB: {
6116 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6117 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6118 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6119 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6120 }
6121 break;
6122 default:
6123 flow_tx = false;
6124 flow_rx = false;
6125 break;
6126 }
6127
6128 adapter->last_rx_ptp_check = jiffies;
6129
6130 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6131 ixgbe_ptp_start_cyclecounter(adapter);
6132
6133 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6134 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6135 "10 Gbps" :
6136 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6137 "1 Gbps" :
6138 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6139 "100 Mbps" :
6140 "unknown speed"))),
6141 ((flow_rx && flow_tx) ? "RX/TX" :
6142 (flow_rx ? "RX" :
6143 (flow_tx ? "TX" : "None"))));
6144
6145 netif_carrier_on(netdev);
6146 ixgbe_check_vf_rate_limit(adapter);
6147
6148 /* enable transmits */
6149 netif_tx_wake_all_queues(adapter->netdev);
6150
6151 /* enable any upper devices */
6152 rtnl_lock();
6153 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6154 if (netif_is_macvlan(upper)) {
6155 struct macvlan_dev *vlan = netdev_priv(upper);
6156
6157 if (vlan->fwd_priv)
6158 netif_tx_wake_all_queues(upper);
6159 }
6160 }
6161 rtnl_unlock();
6162
6163 /* update the default user priority for VFs */
6164 ixgbe_update_default_up(adapter);
6165
6166 /* ping all the active vfs to let them know link has changed */
6167 ixgbe_ping_all_vfs(adapter);
6168 }
6169
6170 /**
6171 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6172 * print link down message
6173 * @adapter: pointer to the adapter structure
6174 **/
6175 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
6176 {
6177 struct net_device *netdev = adapter->netdev;
6178 struct ixgbe_hw *hw = &adapter->hw;
6179
6180 adapter->link_up = false;
6181 adapter->link_speed = 0;
6182
6183 /* only continue if link was up previously */
6184 if (!netif_carrier_ok(netdev))
6185 return;
6186
6187 /* poll for SFP+ cable when link is down */
6188 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6189 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6190
6191 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6192 ixgbe_ptp_start_cyclecounter(adapter);
6193
6194 e_info(drv, "NIC Link is Down\n");
6195 netif_carrier_off(netdev);
6196
6197 /* ping all the active vfs to let them know link has changed */
6198 ixgbe_ping_all_vfs(adapter);
6199 }
6200
6201 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6202 {
6203 int i;
6204
6205 for (i = 0; i < adapter->num_tx_queues; i++) {
6206 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6207
6208 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6209 return true;
6210 }
6211
6212 return false;
6213 }
6214
6215 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6216 {
6217 struct ixgbe_hw *hw = &adapter->hw;
6218 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6219 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6220
6221 int i, j;
6222
6223 if (!adapter->num_vfs)
6224 return false;
6225
6226 for (i = 0; i < adapter->num_vfs; i++) {
6227 for (j = 0; j < q_per_pool; j++) {
6228 u32 h, t;
6229
6230 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6231 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6232
6233 if (h != t)
6234 return true;
6235 }
6236 }
6237
6238 return false;
6239 }
6240
6241 /**
6242 * ixgbe_watchdog_flush_tx - flush queues on link down
6243 * @adapter: pointer to the device adapter structure
6244 **/
6245 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6246 {
6247 if (!netif_carrier_ok(adapter->netdev)) {
6248 if (ixgbe_ring_tx_pending(adapter) ||
6249 ixgbe_vf_tx_pending(adapter)) {
6250 /* We've lost link, so the controller stops DMA,
6251 * but we've got queued Tx work that's never going
6252 * to get done, so reset controller to flush Tx.
6253 * (Do the reset outside of interrupt context).
6254 */
6255 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
6256 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6257 }
6258 }
6259 }
6260
6261 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6262 {
6263 u32 ssvpc;
6264
6265 /* Do not perform spoof check for 82598 or if not in IOV mode */
6266 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6267 adapter->num_vfs == 0)
6268 return;
6269
6270 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6271
6272 /*
6273 * ssvpc register is cleared on read, if zero then no
6274 * spoofed packets in the last interval.
6275 */
6276 if (!ssvpc)
6277 return;
6278
6279 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
6280 }
6281
6282 /**
6283 * ixgbe_watchdog_subtask - check and bring link up
6284 * @adapter: pointer to the device adapter structure
6285 **/
6286 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6287 {
6288 /* if interface is down, removing or resetting, do nothing */
6289 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6290 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6291 test_bit(__IXGBE_RESETTING, &adapter->state))
6292 return;
6293
6294 ixgbe_watchdog_update_link(adapter);
6295
6296 if (adapter->link_up)
6297 ixgbe_watchdog_link_is_up(adapter);
6298 else
6299 ixgbe_watchdog_link_is_down(adapter);
6300
6301 ixgbe_spoof_check(adapter);
6302 ixgbe_update_stats(adapter);
6303
6304 ixgbe_watchdog_flush_tx(adapter);
6305 }
6306
6307 /**
6308 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6309 * @adapter: the ixgbe adapter structure
6310 **/
6311 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6312 {
6313 struct ixgbe_hw *hw = &adapter->hw;
6314 s32 err;
6315
6316 /* not searching for SFP so there is nothing to do here */
6317 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6318 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6319 return;
6320
6321 /* someone else is in init, wait until next service event */
6322 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6323 return;
6324
6325 err = hw->phy.ops.identify_sfp(hw);
6326 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6327 goto sfp_out;
6328
6329 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6330 /* If no cable is present, then we need to reset
6331 * the next time we find a good cable. */
6332 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6333 }
6334
6335 /* exit on error */
6336 if (err)
6337 goto sfp_out;
6338
6339 /* exit if reset not needed */
6340 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6341 goto sfp_out;
6342
6343 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6344
6345 /*
6346 * A module may be identified correctly, but the EEPROM may not have
6347 * support for that module. setup_sfp() will fail in that case, so
6348 * we should not allow that module to load.
6349 */
6350 if (hw->mac.type == ixgbe_mac_82598EB)
6351 err = hw->phy.ops.reset(hw);
6352 else
6353 err = hw->mac.ops.setup_sfp(hw);
6354
6355 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6356 goto sfp_out;
6357
6358 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6359 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6360
6361 sfp_out:
6362 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6363
6364 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6365 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6366 e_dev_err("failed to initialize because an unsupported "
6367 "SFP+ module type was detected.\n");
6368 e_dev_err("Reload the driver after installing a "
6369 "supported module.\n");
6370 unregister_netdev(adapter->netdev);
6371 }
6372 }
6373
6374 /**
6375 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6376 * @adapter: the ixgbe adapter structure
6377 **/
6378 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6379 {
6380 struct ixgbe_hw *hw = &adapter->hw;
6381 u32 speed;
6382 bool autoneg = false;
6383
6384 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6385 return;
6386
6387 /* someone else is in init, wait until next service event */
6388 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6389 return;
6390
6391 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6392
6393 speed = hw->phy.autoneg_advertised;
6394 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
6395 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
6396
6397 /* setup the highest link when no autoneg */
6398 if (!autoneg) {
6399 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6400 speed = IXGBE_LINK_SPEED_10GB_FULL;
6401 }
6402 }
6403
6404 if (hw->mac.ops.setup_link)
6405 hw->mac.ops.setup_link(hw, speed, true);
6406
6407 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6408 adapter->link_check_timeout = jiffies;
6409 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6410 }
6411
6412 #ifdef CONFIG_PCI_IOV
6413 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6414 {
6415 int vf;
6416 struct ixgbe_hw *hw = &adapter->hw;
6417 struct net_device *netdev = adapter->netdev;
6418 u32 gpc;
6419 u32 ciaa, ciad;
6420
6421 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6422 if (gpc) /* If incrementing then no need for the check below */
6423 return;
6424 /*
6425 * Check to see if a bad DMA write target from an errant or
6426 * malicious VF has caused a PCIe error. If so then we can
6427 * issue a VFLR to the offending VF(s) and then resume without
6428 * requesting a full slot reset.
6429 */
6430
6431 for (vf = 0; vf < adapter->num_vfs; vf++) {
6432 ciaa = (vf << 16) | 0x80000000;
6433 /* 32 bit read so align, we really want status at offset 6 */
6434 ciaa |= PCI_COMMAND;
6435 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6436 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6437 ciaa &= 0x7FFFFFFF;
6438 /* disable debug mode asap after reading data */
6439 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6440 /* Get the upper 16 bits which will be the PCI status reg */
6441 ciad >>= 16;
6442 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6443 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6444 /* Issue VFLR */
6445 ciaa = (vf << 16) | 0x80000000;
6446 ciaa |= 0xA8;
6447 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6448 ciad = 0x00008000; /* VFLR */
6449 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6450 ciaa &= 0x7FFFFFFF;
6451 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6452 }
6453 }
6454 }
6455
6456 #endif
6457 /**
6458 * ixgbe_service_timer - Timer Call-back
6459 * @data: pointer to adapter cast into an unsigned long
6460 **/
6461 static void ixgbe_service_timer(unsigned long data)
6462 {
6463 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6464 unsigned long next_event_offset;
6465 bool ready = true;
6466
6467 /* poll faster when waiting for link */
6468 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6469 next_event_offset = HZ / 10;
6470 else
6471 next_event_offset = HZ * 2;
6472
6473 #ifdef CONFIG_PCI_IOV
6474 /*
6475 * don't bother with SR-IOV VF DMA hang check if there are
6476 * no VFs or the link is down
6477 */
6478 if (!adapter->num_vfs ||
6479 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6480 goto normal_timer_service;
6481
6482 /* If we have VFs allocated then we must check for DMA hangs */
6483 ixgbe_check_for_bad_vf(adapter);
6484 next_event_offset = HZ / 50;
6485 adapter->timer_event_accumulator++;
6486
6487 if (adapter->timer_event_accumulator >= 100)
6488 adapter->timer_event_accumulator = 0;
6489 else
6490 ready = false;
6491
6492 normal_timer_service:
6493 #endif
6494 /* Reset the timer */
6495 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6496
6497 if (ready)
6498 ixgbe_service_event_schedule(adapter);
6499 }
6500
6501 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6502 {
6503 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6504 return;
6505
6506 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6507
6508 /* If we're already down, removing or resetting, just bail */
6509 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6510 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6511 test_bit(__IXGBE_RESETTING, &adapter->state))
6512 return;
6513
6514 ixgbe_dump(adapter);
6515 netdev_err(adapter->netdev, "Reset adapter\n");
6516 adapter->tx_timeout_count++;
6517
6518 rtnl_lock();
6519 ixgbe_reinit_locked(adapter);
6520 rtnl_unlock();
6521 }
6522
6523 /**
6524 * ixgbe_service_task - manages and runs subtasks
6525 * @work: pointer to work_struct containing our data
6526 **/
6527 static void ixgbe_service_task(struct work_struct *work)
6528 {
6529 struct ixgbe_adapter *adapter = container_of(work,
6530 struct ixgbe_adapter,
6531 service_task);
6532 if (ixgbe_removed(adapter->hw.hw_addr)) {
6533 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6534 rtnl_lock();
6535 ixgbe_down(adapter);
6536 rtnl_unlock();
6537 }
6538 ixgbe_service_event_complete(adapter);
6539 return;
6540 }
6541 ixgbe_reset_subtask(adapter);
6542 ixgbe_sfp_detection_subtask(adapter);
6543 ixgbe_sfp_link_config_subtask(adapter);
6544 ixgbe_check_overtemp_subtask(adapter);
6545 ixgbe_watchdog_subtask(adapter);
6546 ixgbe_fdir_reinit_subtask(adapter);
6547 ixgbe_check_hang_subtask(adapter);
6548
6549 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
6550 ixgbe_ptp_overflow_check(adapter);
6551 ixgbe_ptp_rx_hang(adapter);
6552 }
6553
6554 ixgbe_service_event_complete(adapter);
6555 }
6556
6557 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6558 struct ixgbe_tx_buffer *first,
6559 u8 *hdr_len)
6560 {
6561 struct sk_buff *skb = first->skb;
6562 u32 vlan_macip_lens, type_tucmd;
6563 u32 mss_l4len_idx, l4len;
6564 int err;
6565
6566 if (skb->ip_summed != CHECKSUM_PARTIAL)
6567 return 0;
6568
6569 if (!skb_is_gso(skb))
6570 return 0;
6571
6572 err = skb_cow_head(skb, 0);
6573 if (err < 0)
6574 return err;
6575
6576 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6577 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6578
6579 if (first->protocol == htons(ETH_P_IP)) {
6580 struct iphdr *iph = ip_hdr(skb);
6581 iph->tot_len = 0;
6582 iph->check = 0;
6583 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6584 iph->daddr, 0,
6585 IPPROTO_TCP,
6586 0);
6587 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6588 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6589 IXGBE_TX_FLAGS_CSUM |
6590 IXGBE_TX_FLAGS_IPV4;
6591 } else if (skb_is_gso_v6(skb)) {
6592 ipv6_hdr(skb)->payload_len = 0;
6593 tcp_hdr(skb)->check =
6594 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6595 &ipv6_hdr(skb)->daddr,
6596 0, IPPROTO_TCP, 0);
6597 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6598 IXGBE_TX_FLAGS_CSUM;
6599 }
6600
6601 /* compute header lengths */
6602 l4len = tcp_hdrlen(skb);
6603 *hdr_len = skb_transport_offset(skb) + l4len;
6604
6605 /* update gso size and bytecount with header size */
6606 first->gso_segs = skb_shinfo(skb)->gso_segs;
6607 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6608
6609 /* mss_l4len_id: use 0 as index for TSO */
6610 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6611 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6612
6613 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6614 vlan_macip_lens = skb_network_header_len(skb);
6615 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6616 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6617
6618 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6619 mss_l4len_idx);
6620
6621 return 1;
6622 }
6623
6624 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6625 struct ixgbe_tx_buffer *first)
6626 {
6627 struct sk_buff *skb = first->skb;
6628 u32 vlan_macip_lens = 0;
6629 u32 mss_l4len_idx = 0;
6630 u32 type_tucmd = 0;
6631
6632 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6633 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6634 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6635 return;
6636 } else {
6637 u8 l4_hdr = 0;
6638 switch (first->protocol) {
6639 case htons(ETH_P_IP):
6640 vlan_macip_lens |= skb_network_header_len(skb);
6641 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6642 l4_hdr = ip_hdr(skb)->protocol;
6643 break;
6644 case htons(ETH_P_IPV6):
6645 vlan_macip_lens |= skb_network_header_len(skb);
6646 l4_hdr = ipv6_hdr(skb)->nexthdr;
6647 break;
6648 default:
6649 if (unlikely(net_ratelimit())) {
6650 dev_warn(tx_ring->dev,
6651 "partial checksum but proto=%x!\n",
6652 first->protocol);
6653 }
6654 break;
6655 }
6656
6657 switch (l4_hdr) {
6658 case IPPROTO_TCP:
6659 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6660 mss_l4len_idx = tcp_hdrlen(skb) <<
6661 IXGBE_ADVTXD_L4LEN_SHIFT;
6662 break;
6663 case IPPROTO_SCTP:
6664 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6665 mss_l4len_idx = sizeof(struct sctphdr) <<
6666 IXGBE_ADVTXD_L4LEN_SHIFT;
6667 break;
6668 case IPPROTO_UDP:
6669 mss_l4len_idx = sizeof(struct udphdr) <<
6670 IXGBE_ADVTXD_L4LEN_SHIFT;
6671 break;
6672 default:
6673 if (unlikely(net_ratelimit())) {
6674 dev_warn(tx_ring->dev,
6675 "partial checksum but l4 proto=%x!\n",
6676 l4_hdr);
6677 }
6678 break;
6679 }
6680
6681 /* update TX checksum flag */
6682 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
6683 }
6684
6685 /* vlan_macip_lens: MACLEN, VLAN tag */
6686 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6687 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6688
6689 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6690 type_tucmd, mss_l4len_idx);
6691 }
6692
6693 #define IXGBE_SET_FLAG(_input, _flag, _result) \
6694 ((_flag <= _result) ? \
6695 ((u32)(_input & _flag) * (_result / _flag)) : \
6696 ((u32)(_input & _flag) / (_flag / _result)))
6697
6698 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6699 {
6700 /* set type for advanced descriptor with frame checksum insertion */
6701 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6702 IXGBE_ADVTXD_DCMD_DEXT |
6703 IXGBE_ADVTXD_DCMD_IFCS;
6704
6705 /* set HW vlan bit if vlan is present */
6706 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6707 IXGBE_ADVTXD_DCMD_VLE);
6708
6709 /* set segmentation enable bits for TSO/FSO */
6710 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6711 IXGBE_ADVTXD_DCMD_TSE);
6712
6713 /* set timestamp bit if present */
6714 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6715 IXGBE_ADVTXD_MAC_TSTAMP);
6716
6717 /* insert frame checksum */
6718 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
6719
6720 return cmd_type;
6721 }
6722
6723 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6724 u32 tx_flags, unsigned int paylen)
6725 {
6726 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
6727
6728 /* enable L4 checksum for TSO and TX checksum offload */
6729 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6730 IXGBE_TX_FLAGS_CSUM,
6731 IXGBE_ADVTXD_POPTS_TXSM);
6732
6733 /* enble IPv4 checksum for TSO */
6734 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6735 IXGBE_TX_FLAGS_IPV4,
6736 IXGBE_ADVTXD_POPTS_IXSM);
6737
6738 /*
6739 * Check Context must be set if Tx switch is enabled, which it
6740 * always is for case where virtual functions are running
6741 */
6742 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6743 IXGBE_TX_FLAGS_CC,
6744 IXGBE_ADVTXD_CC);
6745
6746 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6747 }
6748
6749 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6750 {
6751 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6752
6753 /* Herbert's original patch had:
6754 * smp_mb__after_netif_stop_queue();
6755 * but since that doesn't exist yet, just open code it.
6756 */
6757 smp_mb();
6758
6759 /* We need to check again in a case another CPU has just
6760 * made room available.
6761 */
6762 if (likely(ixgbe_desc_unused(tx_ring) < size))
6763 return -EBUSY;
6764
6765 /* A reprieve! - use start_queue because it doesn't call schedule */
6766 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6767 ++tx_ring->tx_stats.restart_queue;
6768 return 0;
6769 }
6770
6771 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6772 {
6773 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6774 return 0;
6775
6776 return __ixgbe_maybe_stop_tx(tx_ring, size);
6777 }
6778
6779 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6780 IXGBE_TXD_CMD_RS)
6781
6782 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6783 struct ixgbe_tx_buffer *first,
6784 const u8 hdr_len)
6785 {
6786 struct sk_buff *skb = first->skb;
6787 struct ixgbe_tx_buffer *tx_buffer;
6788 union ixgbe_adv_tx_desc *tx_desc;
6789 struct skb_frag_struct *frag;
6790 dma_addr_t dma;
6791 unsigned int data_len, size;
6792 u32 tx_flags = first->tx_flags;
6793 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
6794 u16 i = tx_ring->next_to_use;
6795
6796 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6797
6798 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6799
6800 size = skb_headlen(skb);
6801 data_len = skb->data_len;
6802
6803 #ifdef IXGBE_FCOE
6804 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6805 if (data_len < sizeof(struct fcoe_crc_eof)) {
6806 size -= sizeof(struct fcoe_crc_eof) - data_len;
6807 data_len = 0;
6808 } else {
6809 data_len -= sizeof(struct fcoe_crc_eof);
6810 }
6811 }
6812
6813 #endif
6814 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6815
6816 tx_buffer = first;
6817
6818 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6819 if (dma_mapping_error(tx_ring->dev, dma))
6820 goto dma_error;
6821
6822 /* record length, and DMA address */
6823 dma_unmap_len_set(tx_buffer, len, size);
6824 dma_unmap_addr_set(tx_buffer, dma, dma);
6825
6826 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6827
6828 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6829 tx_desc->read.cmd_type_len =
6830 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
6831
6832 i++;
6833 tx_desc++;
6834 if (i == tx_ring->count) {
6835 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6836 i = 0;
6837 }
6838 tx_desc->read.olinfo_status = 0;
6839
6840 dma += IXGBE_MAX_DATA_PER_TXD;
6841 size -= IXGBE_MAX_DATA_PER_TXD;
6842
6843 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6844 }
6845
6846 if (likely(!data_len))
6847 break;
6848
6849 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6850
6851 i++;
6852 tx_desc++;
6853 if (i == tx_ring->count) {
6854 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6855 i = 0;
6856 }
6857 tx_desc->read.olinfo_status = 0;
6858
6859 #ifdef IXGBE_FCOE
6860 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6861 #else
6862 size = skb_frag_size(frag);
6863 #endif
6864 data_len -= size;
6865
6866 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6867 DMA_TO_DEVICE);
6868
6869 tx_buffer = &tx_ring->tx_buffer_info[i];
6870 }
6871
6872 /* write last descriptor with RS and EOP bits */
6873 cmd_type |= size | IXGBE_TXD_CMD;
6874 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6875
6876 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6877
6878 /* set the timestamp */
6879 first->time_stamp = jiffies;
6880
6881 /*
6882 * Force memory writes to complete before letting h/w know there
6883 * are new descriptors to fetch. (Only applicable for weak-ordered
6884 * memory model archs, such as IA-64).
6885 *
6886 * We also need this memory barrier to make certain all of the
6887 * status bits have been updated before next_to_watch is written.
6888 */
6889 wmb();
6890
6891 /* set next_to_watch value indicating a packet is present */
6892 first->next_to_watch = tx_desc;
6893
6894 i++;
6895 if (i == tx_ring->count)
6896 i = 0;
6897
6898 tx_ring->next_to_use = i;
6899
6900 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6901
6902 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
6903 /* notify HW of packet */
6904 ixgbe_write_tail(tx_ring, i);
6905 }
6906
6907 return;
6908 dma_error:
6909 dev_err(tx_ring->dev, "TX DMA map failed\n");
6910
6911 /* clear dma mappings for failed tx_buffer_info map */
6912 for (;;) {
6913 tx_buffer = &tx_ring->tx_buffer_info[i];
6914 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6915 if (tx_buffer == first)
6916 break;
6917 if (i == 0)
6918 i = tx_ring->count;
6919 i--;
6920 }
6921
6922 tx_ring->next_to_use = i;
6923 }
6924
6925 static void ixgbe_atr(struct ixgbe_ring *ring,
6926 struct ixgbe_tx_buffer *first)
6927 {
6928 struct ixgbe_q_vector *q_vector = ring->q_vector;
6929 union ixgbe_atr_hash_dword input = { .dword = 0 };
6930 union ixgbe_atr_hash_dword common = { .dword = 0 };
6931 union {
6932 unsigned char *network;
6933 struct iphdr *ipv4;
6934 struct ipv6hdr *ipv6;
6935 } hdr;
6936 struct tcphdr *th;
6937 __be16 vlan_id;
6938
6939 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6940 if (!q_vector)
6941 return;
6942
6943 /* do nothing if sampling is disabled */
6944 if (!ring->atr_sample_rate)
6945 return;
6946
6947 ring->atr_count++;
6948
6949 /* snag network header to get L4 type and address */
6950 hdr.network = skb_network_header(first->skb);
6951
6952 /* Currently only IPv4/IPv6 with TCP is supported */
6953 if ((first->protocol != htons(ETH_P_IPV6) ||
6954 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6955 (first->protocol != htons(ETH_P_IP) ||
6956 hdr.ipv4->protocol != IPPROTO_TCP))
6957 return;
6958
6959 th = tcp_hdr(first->skb);
6960
6961 /* skip this packet since it is invalid or the socket is closing */
6962 if (!th || th->fin)
6963 return;
6964
6965 /* sample on all syn packets or once every atr sample count */
6966 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6967 return;
6968
6969 /* reset sample count */
6970 ring->atr_count = 0;
6971
6972 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6973
6974 /*
6975 * src and dst are inverted, think how the receiver sees them
6976 *
6977 * The input is broken into two sections, a non-compressed section
6978 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6979 * is XORed together and stored in the compressed dword.
6980 */
6981 input.formatted.vlan_id = vlan_id;
6982
6983 /*
6984 * since src port and flex bytes occupy the same word XOR them together
6985 * and write the value to source port portion of compressed dword
6986 */
6987 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6988 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
6989 else
6990 common.port.src ^= th->dest ^ first->protocol;
6991 common.port.dst ^= th->source;
6992
6993 if (first->protocol == htons(ETH_P_IP)) {
6994 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6995 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6996 } else {
6997 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6998 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6999 hdr.ipv6->saddr.s6_addr32[1] ^
7000 hdr.ipv6->saddr.s6_addr32[2] ^
7001 hdr.ipv6->saddr.s6_addr32[3] ^
7002 hdr.ipv6->daddr.s6_addr32[0] ^
7003 hdr.ipv6->daddr.s6_addr32[1] ^
7004 hdr.ipv6->daddr.s6_addr32[2] ^
7005 hdr.ipv6->daddr.s6_addr32[3];
7006 }
7007
7008 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
7009 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7010 input, common, ring->queue_index);
7011 }
7012
7013 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
7014 void *accel_priv, select_queue_fallback_t fallback)
7015 {
7016 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7017 #ifdef IXGBE_FCOE
7018 struct ixgbe_adapter *adapter;
7019 struct ixgbe_ring_feature *f;
7020 int txq;
7021 #endif
7022
7023 if (fwd_adapter)
7024 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7025
7026 #ifdef IXGBE_FCOE
7027
7028 /*
7029 * only execute the code below if protocol is FCoE
7030 * or FIP and we have FCoE enabled on the adapter
7031 */
7032 switch (vlan_get_protocol(skb)) {
7033 case htons(ETH_P_FCOE):
7034 case htons(ETH_P_FIP):
7035 adapter = netdev_priv(dev);
7036
7037 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7038 break;
7039 default:
7040 return fallback(dev, skb);
7041 }
7042
7043 f = &adapter->ring_feature[RING_F_FCOE];
7044
7045 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7046 smp_processor_id();
7047
7048 while (txq >= f->indices)
7049 txq -= f->indices;
7050
7051 return txq + f->offset;
7052 #else
7053 return fallback(dev, skb);
7054 #endif
7055 }
7056
7057 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
7058 struct ixgbe_adapter *adapter,
7059 struct ixgbe_ring *tx_ring)
7060 {
7061 struct ixgbe_tx_buffer *first;
7062 int tso;
7063 u32 tx_flags = 0;
7064 unsigned short f;
7065 u16 count = TXD_USE_COUNT(skb_headlen(skb));
7066 __be16 protocol = skb->protocol;
7067 u8 hdr_len = 0;
7068
7069 /*
7070 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
7071 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
7072 * + 2 desc gap to keep tail from touching head,
7073 * + 1 desc for context descriptor,
7074 * otherwise try next time
7075 */
7076 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7077 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7078
7079 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7080 tx_ring->tx_stats.tx_busy++;
7081 return NETDEV_TX_BUSY;
7082 }
7083
7084 /* record the location of the first descriptor for this packet */
7085 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7086 first->skb = skb;
7087 first->bytecount = skb->len;
7088 first->gso_segs = 1;
7089
7090 /* if we have a HW VLAN tag being added default to the HW one */
7091 if (vlan_tx_tag_present(skb)) {
7092 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7093 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7094 /* else if it is a SW VLAN check the next protocol and store the tag */
7095 } else if (protocol == htons(ETH_P_8021Q)) {
7096 struct vlan_hdr *vhdr, _vhdr;
7097 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7098 if (!vhdr)
7099 goto out_drop;
7100
7101 protocol = vhdr->h_vlan_encapsulated_proto;
7102 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7103 IXGBE_TX_FLAGS_VLAN_SHIFT;
7104 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7105 }
7106
7107 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7108 adapter->ptp_clock &&
7109 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7110 &adapter->state)) {
7111 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7112 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
7113
7114 /* schedule check for Tx timestamp */
7115 adapter->ptp_tx_skb = skb_get(skb);
7116 adapter->ptp_tx_start = jiffies;
7117 schedule_work(&adapter->ptp_tx_work);
7118 }
7119
7120 skb_tx_timestamp(skb);
7121
7122 #ifdef CONFIG_PCI_IOV
7123 /*
7124 * Use the l2switch_enable flag - would be false if the DMA
7125 * Tx switch had been disabled.
7126 */
7127 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7128 tx_flags |= IXGBE_TX_FLAGS_CC;
7129
7130 #endif
7131 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
7132 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7133 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7134 (skb->priority != TC_PRIO_CONTROL))) {
7135 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
7136 tx_flags |= (skb->priority & 0x7) <<
7137 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
7138 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7139 struct vlan_ethhdr *vhdr;
7140
7141 if (skb_cow_head(skb, 0))
7142 goto out_drop;
7143 vhdr = (struct vlan_ethhdr *)skb->data;
7144 vhdr->h_vlan_TCI = htons(tx_flags >>
7145 IXGBE_TX_FLAGS_VLAN_SHIFT);
7146 } else {
7147 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7148 }
7149 }
7150
7151 /* record initial flags and protocol */
7152 first->tx_flags = tx_flags;
7153 first->protocol = protocol;
7154
7155 #ifdef IXGBE_FCOE
7156 /* setup tx offload for FCoE */
7157 if ((protocol == htons(ETH_P_FCOE)) &&
7158 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
7159 tso = ixgbe_fso(tx_ring, first, &hdr_len);
7160 if (tso < 0)
7161 goto out_drop;
7162
7163 goto xmit_fcoe;
7164 }
7165
7166 #endif /* IXGBE_FCOE */
7167 tso = ixgbe_tso(tx_ring, first, &hdr_len);
7168 if (tso < 0)
7169 goto out_drop;
7170 else if (!tso)
7171 ixgbe_tx_csum(tx_ring, first);
7172
7173 /* add the ATR filter if ATR is on */
7174 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7175 ixgbe_atr(tx_ring, first);
7176
7177 #ifdef IXGBE_FCOE
7178 xmit_fcoe:
7179 #endif /* IXGBE_FCOE */
7180 ixgbe_tx_map(tx_ring, first, hdr_len);
7181
7182 return NETDEV_TX_OK;
7183
7184 out_drop:
7185 dev_kfree_skb_any(first->skb);
7186 first->skb = NULL;
7187
7188 return NETDEV_TX_OK;
7189 }
7190
7191 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7192 struct net_device *netdev,
7193 struct ixgbe_ring *ring)
7194 {
7195 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7196 struct ixgbe_ring *tx_ring;
7197
7198 /*
7199 * The minimum packet size for olinfo paylen is 17 so pad the skb
7200 * in order to meet this minimum size requirement.
7201 */
7202 if (unlikely(skb->len < 17)) {
7203 if (skb_pad(skb, 17 - skb->len))
7204 return NETDEV_TX_OK;
7205 skb->len = 17;
7206 skb_set_tail_pointer(skb, 17);
7207 }
7208
7209 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7210
7211 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
7212 }
7213
7214 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7215 struct net_device *netdev)
7216 {
7217 return __ixgbe_xmit_frame(skb, netdev, NULL);
7218 }
7219
7220 /**
7221 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7222 * @netdev: network interface device structure
7223 * @p: pointer to an address structure
7224 *
7225 * Returns 0 on success, negative on failure
7226 **/
7227 static int ixgbe_set_mac(struct net_device *netdev, void *p)
7228 {
7229 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7230 struct ixgbe_hw *hw = &adapter->hw;
7231 struct sockaddr *addr = p;
7232 int ret;
7233
7234 if (!is_valid_ether_addr(addr->sa_data))
7235 return -EADDRNOTAVAIL;
7236
7237 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7238 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
7239 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
7240
7241 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7242 return ret > 0 ? 0 : ret;
7243 }
7244
7245 static int
7246 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7247 {
7248 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7249 struct ixgbe_hw *hw = &adapter->hw;
7250 u16 value;
7251 int rc;
7252
7253 if (prtad != hw->phy.mdio.prtad)
7254 return -EINVAL;
7255 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7256 if (!rc)
7257 rc = value;
7258 return rc;
7259 }
7260
7261 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7262 u16 addr, u16 value)
7263 {
7264 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7265 struct ixgbe_hw *hw = &adapter->hw;
7266
7267 if (prtad != hw->phy.mdio.prtad)
7268 return -EINVAL;
7269 return hw->phy.ops.write_reg(hw, addr, devad, value);
7270 }
7271
7272 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7273 {
7274 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7275
7276 switch (cmd) {
7277 case SIOCSHWTSTAMP:
7278 return ixgbe_ptp_set_ts_config(adapter, req);
7279 case SIOCGHWTSTAMP:
7280 return ixgbe_ptp_get_ts_config(adapter, req);
7281 default:
7282 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7283 }
7284 }
7285
7286 /**
7287 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
7288 * netdev->dev_addrs
7289 * @netdev: network interface device structure
7290 *
7291 * Returns non-zero on failure
7292 **/
7293 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7294 {
7295 int err = 0;
7296 struct ixgbe_adapter *adapter = netdev_priv(dev);
7297 struct ixgbe_hw *hw = &adapter->hw;
7298
7299 if (is_valid_ether_addr(hw->mac.san_addr)) {
7300 rtnl_lock();
7301 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
7302 rtnl_unlock();
7303
7304 /* update SAN MAC vmdq pool selection */
7305 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
7306 }
7307 return err;
7308 }
7309
7310 /**
7311 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7312 * netdev->dev_addrs
7313 * @netdev: network interface device structure
7314 *
7315 * Returns non-zero on failure
7316 **/
7317 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7318 {
7319 int err = 0;
7320 struct ixgbe_adapter *adapter = netdev_priv(dev);
7321 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7322
7323 if (is_valid_ether_addr(mac->san_addr)) {
7324 rtnl_lock();
7325 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7326 rtnl_unlock();
7327 }
7328 return err;
7329 }
7330
7331 #ifdef CONFIG_NET_POLL_CONTROLLER
7332 /*
7333 * Polling 'interrupt' - used by things like netconsole to send skbs
7334 * without having to re-enable interrupts. It's not called while
7335 * the interrupt routine is executing.
7336 */
7337 static void ixgbe_netpoll(struct net_device *netdev)
7338 {
7339 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7340 int i;
7341
7342 /* if interface is down do nothing */
7343 if (test_bit(__IXGBE_DOWN, &adapter->state))
7344 return;
7345
7346 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
7347 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7348 for (i = 0; i < adapter->num_q_vectors; i++)
7349 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
7350 } else {
7351 ixgbe_intr(adapter->pdev->irq, netdev);
7352 }
7353 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7354 }
7355
7356 #endif
7357 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7358 struct rtnl_link_stats64 *stats)
7359 {
7360 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7361 int i;
7362
7363 rcu_read_lock();
7364 for (i = 0; i < adapter->num_rx_queues; i++) {
7365 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7366 u64 bytes, packets;
7367 unsigned int start;
7368
7369 if (ring) {
7370 do {
7371 start = u64_stats_fetch_begin_irq(&ring->syncp);
7372 packets = ring->stats.packets;
7373 bytes = ring->stats.bytes;
7374 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
7375 stats->rx_packets += packets;
7376 stats->rx_bytes += bytes;
7377 }
7378 }
7379
7380 for (i = 0; i < adapter->num_tx_queues; i++) {
7381 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7382 u64 bytes, packets;
7383 unsigned int start;
7384
7385 if (ring) {
7386 do {
7387 start = u64_stats_fetch_begin_irq(&ring->syncp);
7388 packets = ring->stats.packets;
7389 bytes = ring->stats.bytes;
7390 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
7391 stats->tx_packets += packets;
7392 stats->tx_bytes += bytes;
7393 }
7394 }
7395 rcu_read_unlock();
7396 /* following stats updated by ixgbe_watchdog_task() */
7397 stats->multicast = netdev->stats.multicast;
7398 stats->rx_errors = netdev->stats.rx_errors;
7399 stats->rx_length_errors = netdev->stats.rx_length_errors;
7400 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7401 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7402 return stats;
7403 }
7404
7405 #ifdef CONFIG_IXGBE_DCB
7406 /**
7407 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7408 * @adapter: pointer to ixgbe_adapter
7409 * @tc: number of traffic classes currently enabled
7410 *
7411 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7412 * 802.1Q priority maps to a packet buffer that exists.
7413 */
7414 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7415 {
7416 struct ixgbe_hw *hw = &adapter->hw;
7417 u32 reg, rsave;
7418 int i;
7419
7420 /* 82598 have a static priority to TC mapping that can not
7421 * be changed so no validation is needed.
7422 */
7423 if (hw->mac.type == ixgbe_mac_82598EB)
7424 return;
7425
7426 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7427 rsave = reg;
7428
7429 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7430 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7431
7432 /* If up2tc is out of bounds default to zero */
7433 if (up2tc > tc)
7434 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7435 }
7436
7437 if (reg != rsave)
7438 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7439
7440 return;
7441 }
7442
7443 /**
7444 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7445 * @adapter: Pointer to adapter struct
7446 *
7447 * Populate the netdev user priority to tc map
7448 */
7449 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7450 {
7451 struct net_device *dev = adapter->netdev;
7452 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7453 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7454 u8 prio;
7455
7456 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7457 u8 tc = 0;
7458
7459 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7460 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7461 else if (ets)
7462 tc = ets->prio_tc[prio];
7463
7464 netdev_set_prio_tc_map(dev, prio, tc);
7465 }
7466 }
7467
7468 #endif /* CONFIG_IXGBE_DCB */
7469 /**
7470 * ixgbe_setup_tc - configure net_device for multiple traffic classes
7471 *
7472 * @netdev: net device to configure
7473 * @tc: number of traffic classes to enable
7474 */
7475 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7476 {
7477 struct ixgbe_adapter *adapter = netdev_priv(dev);
7478 struct ixgbe_hw *hw = &adapter->hw;
7479 bool pools;
7480
7481 /* Hardware supports up to 8 traffic classes */
7482 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
7483 (hw->mac.type == ixgbe_mac_82598EB &&
7484 tc < MAX_TRAFFIC_CLASS))
7485 return -EINVAL;
7486
7487 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7488 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7489 return -EBUSY;
7490
7491 /* Hardware has to reinitialize queues and interrupts to
7492 * match packet buffer alignment. Unfortunately, the
7493 * hardware is not flexible enough to do this dynamically.
7494 */
7495 if (netif_running(dev))
7496 ixgbe_close(dev);
7497 ixgbe_clear_interrupt_scheme(adapter);
7498
7499 #ifdef CONFIG_IXGBE_DCB
7500 if (tc) {
7501 netdev_set_num_tc(dev, tc);
7502 ixgbe_set_prio_tc_map(adapter);
7503
7504 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7505
7506 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7507 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
7508 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7509 }
7510 } else {
7511 netdev_reset_tc(dev);
7512
7513 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7514 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7515
7516 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7517
7518 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7519 adapter->dcb_cfg.pfc_mode_enable = false;
7520 }
7521
7522 ixgbe_validate_rtr(adapter, tc);
7523
7524 #endif /* CONFIG_IXGBE_DCB */
7525 ixgbe_init_interrupt_scheme(adapter);
7526
7527 if (netif_running(dev))
7528 return ixgbe_open(dev);
7529
7530 return 0;
7531 }
7532
7533 #ifdef CONFIG_PCI_IOV
7534 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7535 {
7536 struct net_device *netdev = adapter->netdev;
7537
7538 rtnl_lock();
7539 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
7540 rtnl_unlock();
7541 }
7542
7543 #endif
7544 void ixgbe_do_reset(struct net_device *netdev)
7545 {
7546 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7547
7548 if (netif_running(netdev))
7549 ixgbe_reinit_locked(adapter);
7550 else
7551 ixgbe_reset(adapter);
7552 }
7553
7554 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7555 netdev_features_t features)
7556 {
7557 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7558
7559 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7560 if (!(features & NETIF_F_RXCSUM))
7561 features &= ~NETIF_F_LRO;
7562
7563 /* Turn off LRO if not RSC capable */
7564 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7565 features &= ~NETIF_F_LRO;
7566
7567 return features;
7568 }
7569
7570 static int ixgbe_set_features(struct net_device *netdev,
7571 netdev_features_t features)
7572 {
7573 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7574 netdev_features_t changed = netdev->features ^ features;
7575 bool need_reset = false;
7576
7577 /* Make sure RSC matches LRO, reset if change */
7578 if (!(features & NETIF_F_LRO)) {
7579 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7580 need_reset = true;
7581 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7582 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7583 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7584 if (adapter->rx_itr_setting == 1 ||
7585 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7586 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7587 need_reset = true;
7588 } else if ((changed ^ features) & NETIF_F_LRO) {
7589 e_info(probe, "rx-usecs set too low, "
7590 "disabling RSC\n");
7591 }
7592 }
7593
7594 /*
7595 * Check if Flow Director n-tuple support was enabled or disabled. If
7596 * the state changed, we need to reset.
7597 */
7598 switch (features & NETIF_F_NTUPLE) {
7599 case NETIF_F_NTUPLE:
7600 /* turn off ATR, enable perfect filters and reset */
7601 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7602 need_reset = true;
7603
7604 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7605 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7606 break;
7607 default:
7608 /* turn off perfect filters, enable ATR and reset */
7609 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7610 need_reset = true;
7611
7612 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7613
7614 /* We cannot enable ATR if SR-IOV is enabled */
7615 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7616 break;
7617
7618 /* We cannot enable ATR if we have 2 or more traffic classes */
7619 if (netdev_get_num_tc(netdev) > 1)
7620 break;
7621
7622 /* We cannot enable ATR if RSS is disabled */
7623 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7624 break;
7625
7626 /* A sample rate of 0 indicates ATR disabled */
7627 if (!adapter->atr_sample_rate)
7628 break;
7629
7630 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7631 break;
7632 }
7633
7634 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7635 ixgbe_vlan_strip_enable(adapter);
7636 else
7637 ixgbe_vlan_strip_disable(adapter);
7638
7639 if (changed & NETIF_F_RXALL)
7640 need_reset = true;
7641
7642 netdev->features = features;
7643 if (need_reset)
7644 ixgbe_do_reset(netdev);
7645
7646 return 0;
7647 }
7648
7649 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7650 struct net_device *dev,
7651 const unsigned char *addr,
7652 u16 flags)
7653 {
7654 /* guarantee we can provide a unique filter for the unicast address */
7655 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
7656 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev))
7657 return -ENOMEM;
7658 }
7659
7660 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
7661 }
7662
7663 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7664 struct nlmsghdr *nlh)
7665 {
7666 struct ixgbe_adapter *adapter = netdev_priv(dev);
7667 struct nlattr *attr, *br_spec;
7668 int rem;
7669
7670 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7671 return -EOPNOTSUPP;
7672
7673 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7674
7675 nla_for_each_nested(attr, br_spec, rem) {
7676 __u16 mode;
7677 u32 reg = 0;
7678
7679 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7680 continue;
7681
7682 mode = nla_get_u16(attr);
7683 if (mode == BRIDGE_MODE_VEPA) {
7684 reg = 0;
7685 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7686 } else if (mode == BRIDGE_MODE_VEB) {
7687 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7688 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7689 } else
7690 return -EINVAL;
7691
7692 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7693
7694 e_info(drv, "enabling bridge mode: %s\n",
7695 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7696 }
7697
7698 return 0;
7699 }
7700
7701 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7702 struct net_device *dev,
7703 u32 filter_mask)
7704 {
7705 struct ixgbe_adapter *adapter = netdev_priv(dev);
7706 u16 mode;
7707
7708 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7709 return 0;
7710
7711 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
7712 mode = BRIDGE_MODE_VEB;
7713 else
7714 mode = BRIDGE_MODE_VEPA;
7715
7716 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7717 }
7718
7719 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
7720 {
7721 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
7722 struct ixgbe_adapter *adapter = netdev_priv(pdev);
7723 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
7724 unsigned int limit;
7725 int pool, err;
7726
7727 /* Hardware has a limited number of available pools. Each VF, and the
7728 * PF require a pool. Check to ensure we don't attempt to use more
7729 * then the available number of pools.
7730 */
7731 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
7732 return ERR_PTR(-EINVAL);
7733
7734 #ifdef CONFIG_RPS
7735 if (vdev->num_rx_queues != vdev->num_tx_queues) {
7736 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
7737 vdev->name);
7738 return ERR_PTR(-EINVAL);
7739 }
7740 #endif
7741 /* Check for hardware restriction on number of rx/tx queues */
7742 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
7743 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
7744 netdev_info(pdev,
7745 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
7746 pdev->name);
7747 return ERR_PTR(-EINVAL);
7748 }
7749
7750 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7751 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
7752 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
7753 return ERR_PTR(-EBUSY);
7754
7755 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL);
7756 if (!fwd_adapter)
7757 return ERR_PTR(-ENOMEM);
7758
7759 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
7760 adapter->num_rx_pools++;
7761 set_bit(pool, &adapter->fwd_bitmask);
7762 limit = find_last_bit(&adapter->fwd_bitmask, 32);
7763
7764 /* Enable VMDq flag so device will be set in VM mode */
7765 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
7766 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
7767 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
7768
7769 /* Force reinit of ring allocation with VMDQ enabled */
7770 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7771 if (err)
7772 goto fwd_add_err;
7773 fwd_adapter->pool = pool;
7774 fwd_adapter->real_adapter = adapter;
7775 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
7776 if (err)
7777 goto fwd_add_err;
7778 netif_tx_start_all_queues(vdev);
7779 return fwd_adapter;
7780 fwd_add_err:
7781 /* unwind counter and free adapter struct */
7782 netdev_info(pdev,
7783 "%s: dfwd hardware acceleration failed\n", vdev->name);
7784 clear_bit(pool, &adapter->fwd_bitmask);
7785 adapter->num_rx_pools--;
7786 kfree(fwd_adapter);
7787 return ERR_PTR(err);
7788 }
7789
7790 static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
7791 {
7792 struct ixgbe_fwd_adapter *fwd_adapter = priv;
7793 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
7794 unsigned int limit;
7795
7796 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
7797 adapter->num_rx_pools--;
7798
7799 limit = find_last_bit(&adapter->fwd_bitmask, 32);
7800 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
7801 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
7802 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7803 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
7804 fwd_adapter->pool, adapter->num_rx_pools,
7805 fwd_adapter->rx_base_queue,
7806 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
7807 adapter->fwd_bitmask);
7808 kfree(fwd_adapter);
7809 }
7810
7811 static const struct net_device_ops ixgbe_netdev_ops = {
7812 .ndo_open = ixgbe_open,
7813 .ndo_stop = ixgbe_close,
7814 .ndo_start_xmit = ixgbe_xmit_frame,
7815 .ndo_select_queue = ixgbe_select_queue,
7816 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7817 .ndo_validate_addr = eth_validate_addr,
7818 .ndo_set_mac_address = ixgbe_set_mac,
7819 .ndo_change_mtu = ixgbe_change_mtu,
7820 .ndo_tx_timeout = ixgbe_tx_timeout,
7821 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7822 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7823 .ndo_do_ioctl = ixgbe_ioctl,
7824 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7825 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7826 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
7827 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7828 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7829 .ndo_get_stats64 = ixgbe_get_stats64,
7830 #ifdef CONFIG_IXGBE_DCB
7831 .ndo_setup_tc = ixgbe_setup_tc,
7832 #endif
7833 #ifdef CONFIG_NET_POLL_CONTROLLER
7834 .ndo_poll_controller = ixgbe_netpoll,
7835 #endif
7836 #ifdef CONFIG_NET_RX_BUSY_POLL
7837 .ndo_busy_poll = ixgbe_low_latency_recv,
7838 #endif
7839 #ifdef IXGBE_FCOE
7840 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7841 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7842 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7843 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7844 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7845 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7846 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7847 #endif /* IXGBE_FCOE */
7848 .ndo_set_features = ixgbe_set_features,
7849 .ndo_fix_features = ixgbe_fix_features,
7850 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7851 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7852 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
7853 .ndo_dfwd_add_station = ixgbe_fwd_add,
7854 .ndo_dfwd_del_station = ixgbe_fwd_del,
7855 };
7856
7857 /**
7858 * ixgbe_enumerate_functions - Get the number of ports this device has
7859 * @adapter: adapter structure
7860 *
7861 * This function enumerates the phsyical functions co-located on a single slot,
7862 * in order to determine how many ports a device has. This is most useful in
7863 * determining the required GT/s of PCIe bandwidth necessary for optimal
7864 * performance.
7865 **/
7866 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7867 {
7868 struct pci_dev *entry, *pdev = adapter->pdev;
7869 int physfns = 0;
7870
7871 /* Some cards can not use the generic count PCIe functions method,
7872 * because they are behind a parent switch, so we hardcode these with
7873 * the correct number of functions.
7874 */
7875 if (ixgbe_pcie_from_parent(&adapter->hw))
7876 physfns = 4;
7877
7878 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
7879 /* don't count virtual functions */
7880 if (entry->is_virtfn)
7881 continue;
7882
7883 /* When the devices on the bus don't all match our device ID,
7884 * we can't reliably determine the correct number of
7885 * functions. This can occur if a function has been direct
7886 * attached to a virtual machine using VT-d, for example. In
7887 * this case, simply return -1 to indicate this.
7888 */
7889 if ((entry->vendor != pdev->vendor) ||
7890 (entry->device != pdev->device))
7891 return -1;
7892
7893 physfns++;
7894 }
7895
7896 return physfns;
7897 }
7898
7899 /**
7900 * ixgbe_wol_supported - Check whether device supports WoL
7901 * @hw: hw specific details
7902 * @device_id: the device ID
7903 * @subdev_id: the subsystem device ID
7904 *
7905 * This function is used by probe and ethtool to determine
7906 * which devices have WoL support
7907 *
7908 **/
7909 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7910 u16 subdevice_id)
7911 {
7912 struct ixgbe_hw *hw = &adapter->hw;
7913 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7914 int is_wol_supported = 0;
7915
7916 switch (device_id) {
7917 case IXGBE_DEV_ID_82599_SFP:
7918 /* Only these subdevices could supports WOL */
7919 switch (subdevice_id) {
7920 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
7921 case IXGBE_SUBDEV_ID_82599_560FLR:
7922 /* only support first port */
7923 if (hw->bus.func != 0)
7924 break;
7925 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
7926 case IXGBE_SUBDEV_ID_82599_SFP:
7927 case IXGBE_SUBDEV_ID_82599_RNDC:
7928 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
7929 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
7930 is_wol_supported = 1;
7931 break;
7932 }
7933 break;
7934 case IXGBE_DEV_ID_82599EN_SFP:
7935 /* Only this subdevice supports WOL */
7936 switch (subdevice_id) {
7937 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
7938 is_wol_supported = 1;
7939 break;
7940 }
7941 break;
7942 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7943 /* All except this subdevice support WOL */
7944 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7945 is_wol_supported = 1;
7946 break;
7947 case IXGBE_DEV_ID_82599_KX4:
7948 is_wol_supported = 1;
7949 break;
7950 case IXGBE_DEV_ID_X540T:
7951 case IXGBE_DEV_ID_X540T1:
7952 /* check eeprom to see if enabled wol */
7953 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7954 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7955 (hw->bus.func == 0))) {
7956 is_wol_supported = 1;
7957 }
7958 break;
7959 }
7960
7961 return is_wol_supported;
7962 }
7963
7964 /**
7965 * ixgbe_probe - Device Initialization Routine
7966 * @pdev: PCI device information struct
7967 * @ent: entry in ixgbe_pci_tbl
7968 *
7969 * Returns 0 on success, negative on failure
7970 *
7971 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7972 * The OS initialization, configuring of the adapter private structure,
7973 * and a hardware reset occur.
7974 **/
7975 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7976 {
7977 struct net_device *netdev;
7978 struct ixgbe_adapter *adapter = NULL;
7979 struct ixgbe_hw *hw;
7980 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7981 int i, err, pci_using_dac, expected_gts;
7982 unsigned int indices = MAX_TX_QUEUES;
7983 u8 part_str[IXGBE_PBANUM_LENGTH];
7984 #ifdef IXGBE_FCOE
7985 u16 device_caps;
7986 #endif
7987 u32 eec;
7988
7989 /* Catch broken hardware that put the wrong VF device ID in
7990 * the PCIe SR-IOV capability.
7991 */
7992 if (pdev->is_virtfn) {
7993 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7994 pci_name(pdev), pdev->vendor, pdev->device);
7995 return -EINVAL;
7996 }
7997
7998 err = pci_enable_device_mem(pdev);
7999 if (err)
8000 return err;
8001
8002 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
8003 pci_using_dac = 1;
8004 } else {
8005 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8006 if (err) {
8007 dev_err(&pdev->dev,
8008 "No usable DMA configuration, aborting\n");
8009 goto err_dma;
8010 }
8011 pci_using_dac = 0;
8012 }
8013
8014 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8015 IORESOURCE_MEM), ixgbe_driver_name);
8016 if (err) {
8017 dev_err(&pdev->dev,
8018 "pci_request_selected_regions failed 0x%x\n", err);
8019 goto err_pci_reg;
8020 }
8021
8022 pci_enable_pcie_error_reporting(pdev);
8023
8024 pci_set_master(pdev);
8025 pci_save_state(pdev);
8026
8027 if (ii->mac == ixgbe_mac_82598EB) {
8028 #ifdef CONFIG_IXGBE_DCB
8029 /* 8 TC w/ 4 queues per TC */
8030 indices = 4 * MAX_TRAFFIC_CLASS;
8031 #else
8032 indices = IXGBE_MAX_RSS_INDICES;
8033 #endif
8034 }
8035
8036 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
8037 if (!netdev) {
8038 err = -ENOMEM;
8039 goto err_alloc_etherdev;
8040 }
8041
8042 SET_NETDEV_DEV(netdev, &pdev->dev);
8043
8044 adapter = netdev_priv(netdev);
8045 pci_set_drvdata(pdev, adapter);
8046
8047 adapter->netdev = netdev;
8048 adapter->pdev = pdev;
8049 hw = &adapter->hw;
8050 hw->back = adapter;
8051 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
8052
8053 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8054 pci_resource_len(pdev, 0));
8055 adapter->io_addr = hw->hw_addr;
8056 if (!hw->hw_addr) {
8057 err = -EIO;
8058 goto err_ioremap;
8059 }
8060
8061 netdev->netdev_ops = &ixgbe_netdev_ops;
8062 ixgbe_set_ethtool_ops(netdev);
8063 netdev->watchdog_timeo = 5 * HZ;
8064 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
8065
8066 /* Setup hw api */
8067 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
8068 hw->mac.type = ii->mac;
8069
8070 /* EEPROM */
8071 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
8072 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
8073 if (ixgbe_removed(hw->hw_addr)) {
8074 err = -EIO;
8075 goto err_ioremap;
8076 }
8077 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8078 if (!(eec & (1 << 8)))
8079 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8080
8081 /* PHY */
8082 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
8083 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
8084 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8085 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8086 hw->phy.mdio.mmds = 0;
8087 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8088 hw->phy.mdio.dev = netdev;
8089 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8090 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
8091
8092 ii->get_invariants(hw);
8093
8094 /* setup the private structure */
8095 err = ixgbe_sw_init(adapter);
8096 if (err)
8097 goto err_sw_init;
8098
8099 /* Make it possible the adapter to be woken up via WOL */
8100 switch (adapter->hw.mac.type) {
8101 case ixgbe_mac_82599EB:
8102 case ixgbe_mac_X540:
8103 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
8104 break;
8105 default:
8106 break;
8107 }
8108
8109 /*
8110 * If there is a fan on this device and it has failed log the
8111 * failure.
8112 */
8113 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8114 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8115 if (esdp & IXGBE_ESDP_SDP1)
8116 e_crit(probe, "Fan has stopped, replace the adapter\n");
8117 }
8118
8119 if (allow_unsupported_sfp)
8120 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8121
8122 /* reset_hw fills in the perm_addr as well */
8123 hw->phy.reset_if_overtemp = true;
8124 err = hw->mac.ops.reset_hw(hw);
8125 hw->phy.reset_if_overtemp = false;
8126 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
8127 hw->mac.type == ixgbe_mac_82598EB) {
8128 err = 0;
8129 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
8130 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8131 e_dev_err("Reload the driver after installing a supported module.\n");
8132 goto err_sw_init;
8133 } else if (err) {
8134 e_dev_err("HW Init failed: %d\n", err);
8135 goto err_sw_init;
8136 }
8137
8138 #ifdef CONFIG_PCI_IOV
8139 /* SR-IOV not supported on the 82598 */
8140 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8141 goto skip_sriov;
8142 /* Mailbox */
8143 ixgbe_init_mbx_params_pf(hw);
8144 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
8145 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
8146 ixgbe_enable_sriov(adapter);
8147 skip_sriov:
8148
8149 #endif
8150 netdev->features = NETIF_F_SG |
8151 NETIF_F_IP_CSUM |
8152 NETIF_F_IPV6_CSUM |
8153 NETIF_F_HW_VLAN_CTAG_TX |
8154 NETIF_F_HW_VLAN_CTAG_RX |
8155 NETIF_F_HW_VLAN_CTAG_FILTER |
8156 NETIF_F_TSO |
8157 NETIF_F_TSO6 |
8158 NETIF_F_RXHASH |
8159 NETIF_F_RXCSUM;
8160
8161 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
8162
8163 switch (adapter->hw.mac.type) {
8164 case ixgbe_mac_82599EB:
8165 case ixgbe_mac_X540:
8166 netdev->features |= NETIF_F_SCTP_CSUM;
8167 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8168 NETIF_F_NTUPLE;
8169 break;
8170 default:
8171 break;
8172 }
8173
8174 netdev->hw_features |= NETIF_F_RXALL;
8175
8176 netdev->vlan_features |= NETIF_F_TSO;
8177 netdev->vlan_features |= NETIF_F_TSO6;
8178 netdev->vlan_features |= NETIF_F_IP_CSUM;
8179 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
8180 netdev->vlan_features |= NETIF_F_SG;
8181
8182 netdev->priv_flags |= IFF_UNICAST_FLT;
8183 netdev->priv_flags |= IFF_SUPP_NOFCS;
8184
8185 #ifdef CONFIG_IXGBE_DCB
8186 netdev->dcbnl_ops = &dcbnl_ops;
8187 #endif
8188
8189 #ifdef IXGBE_FCOE
8190 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
8191 unsigned int fcoe_l;
8192
8193 if (hw->mac.ops.get_device_caps) {
8194 hw->mac.ops.get_device_caps(hw, &device_caps);
8195 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8196 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
8197 }
8198
8199
8200 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8201 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
8202
8203 netdev->features |= NETIF_F_FSO |
8204 NETIF_F_FCOE_CRC;
8205
8206 netdev->vlan_features |= NETIF_F_FSO |
8207 NETIF_F_FCOE_CRC |
8208 NETIF_F_FCOE_MTU;
8209 }
8210 #endif /* IXGBE_FCOE */
8211 if (pci_using_dac) {
8212 netdev->features |= NETIF_F_HIGHDMA;
8213 netdev->vlan_features |= NETIF_F_HIGHDMA;
8214 }
8215
8216 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8217 netdev->hw_features |= NETIF_F_LRO;
8218 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
8219 netdev->features |= NETIF_F_LRO;
8220
8221 /* make sure the EEPROM is good */
8222 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
8223 e_dev_err("The EEPROM Checksum Is Not Valid\n");
8224 err = -EIO;
8225 goto err_sw_init;
8226 }
8227
8228 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
8229
8230 if (!is_valid_ether_addr(netdev->dev_addr)) {
8231 e_dev_err("invalid MAC address\n");
8232 err = -EIO;
8233 goto err_sw_init;
8234 }
8235
8236 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr);
8237
8238 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
8239 (unsigned long) adapter);
8240
8241 if (ixgbe_removed(hw->hw_addr)) {
8242 err = -EIO;
8243 goto err_sw_init;
8244 }
8245 INIT_WORK(&adapter->service_task, ixgbe_service_task);
8246 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
8247 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
8248
8249 err = ixgbe_init_interrupt_scheme(adapter);
8250 if (err)
8251 goto err_sw_init;
8252
8253 /* WOL not supported for all devices */
8254 adapter->wol = 0;
8255 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
8256 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
8257 pdev->subsystem_device);
8258 if (hw->wol_enabled)
8259 adapter->wol = IXGBE_WUFC_MAG;
8260
8261 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8262
8263 /* save off EEPROM version number */
8264 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8265 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8266
8267 /* pick up the PCI bus settings for reporting later */
8268 hw->mac.ops.get_bus_info(hw);
8269 if (ixgbe_pcie_from_parent(hw))
8270 ixgbe_get_parent_bus_info(adapter);
8271
8272 /* calculate the expected PCIe bandwidth required for optimal
8273 * performance. Note that some older parts will never have enough
8274 * bandwidth due to being older generation PCIe parts. We clamp these
8275 * parts to ensure no warning is displayed if it can't be fixed.
8276 */
8277 switch (hw->mac.type) {
8278 case ixgbe_mac_82598EB:
8279 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8280 break;
8281 default:
8282 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8283 break;
8284 }
8285
8286 /* don't check link if we failed to enumerate functions */
8287 if (expected_gts > 0)
8288 ixgbe_check_minimum_link(adapter, expected_gts);
8289
8290 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
8291 if (err)
8292 strlcpy(part_str, "Unknown", sizeof(part_str));
8293 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8294 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8295 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
8296 part_str);
8297 else
8298 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8299 hw->mac.type, hw->phy.type, part_str);
8300
8301 e_dev_info("%pM\n", netdev->dev_addr);
8302
8303 /* reset the hardware with the new settings */
8304 err = hw->mac.ops.start_hw(hw);
8305 if (err == IXGBE_ERR_EEPROM_VERSION) {
8306 /* We are running on a pre-production device, log a warning */
8307 e_dev_warn("This device is a pre-production adapter/LOM. "
8308 "Please be aware there may be issues associated "
8309 "with your hardware. If you are experiencing "
8310 "problems please contact your Intel or hardware "
8311 "representative who provided you with this "
8312 "hardware.\n");
8313 }
8314 strcpy(netdev->name, "eth%d");
8315 err = register_netdev(netdev);
8316 if (err)
8317 goto err_register;
8318
8319 /* power down the optics for 82599 SFP+ fiber */
8320 if (hw->mac.ops.disable_tx_laser)
8321 hw->mac.ops.disable_tx_laser(hw);
8322
8323 /* carrier off reporting is important to ethtool even BEFORE open */
8324 netif_carrier_off(netdev);
8325
8326 #ifdef CONFIG_IXGBE_DCA
8327 if (dca_add_requester(&pdev->dev) == 0) {
8328 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
8329 ixgbe_setup_dca(adapter);
8330 }
8331 #endif
8332 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
8333 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
8334 for (i = 0; i < adapter->num_vfs; i++)
8335 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8336 }
8337
8338 /* firmware requires driver version to be 0xFFFFFFFF
8339 * since os does not support feature
8340 */
8341 if (hw->mac.ops.set_fw_drv_ver)
8342 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8343 0xFF);
8344
8345 /* add san mac addr to netdev */
8346 ixgbe_add_sanmac_netdev(netdev);
8347
8348 e_dev_info("%s\n", ixgbe_default_device_descr);
8349
8350 #ifdef CONFIG_IXGBE_HWMON
8351 if (ixgbe_sysfs_init(adapter))
8352 e_err(probe, "failed to allocate sysfs resources\n");
8353 #endif /* CONFIG_IXGBE_HWMON */
8354
8355 ixgbe_dbg_adapter_init(adapter);
8356
8357 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
8358 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
8359 hw->mac.ops.setup_link(hw,
8360 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8361 true);
8362
8363 return 0;
8364
8365 err_register:
8366 ixgbe_release_hw_control(adapter);
8367 ixgbe_clear_interrupt_scheme(adapter);
8368 err_sw_init:
8369 ixgbe_disable_sriov(adapter);
8370 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
8371 iounmap(adapter->io_addr);
8372 kfree(adapter->mac_table);
8373 err_ioremap:
8374 free_netdev(netdev);
8375 err_alloc_etherdev:
8376 pci_release_selected_regions(pdev,
8377 pci_select_bars(pdev, IORESOURCE_MEM));
8378 err_pci_reg:
8379 err_dma:
8380 if (!adapter || !test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8381 pci_disable_device(pdev);
8382 return err;
8383 }
8384
8385 /**
8386 * ixgbe_remove - Device Removal Routine
8387 * @pdev: PCI device information struct
8388 *
8389 * ixgbe_remove is called by the PCI subsystem to alert the driver
8390 * that it should release a PCI device. The could be caused by a
8391 * Hot-Plug event, or because the driver is going to be removed from
8392 * memory.
8393 **/
8394 static void ixgbe_remove(struct pci_dev *pdev)
8395 {
8396 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8397 struct net_device *netdev = adapter->netdev;
8398
8399 ixgbe_dbg_adapter_exit(adapter);
8400
8401 set_bit(__IXGBE_REMOVING, &adapter->state);
8402 cancel_work_sync(&adapter->service_task);
8403
8404
8405 #ifdef CONFIG_IXGBE_DCA
8406 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8407 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8408 dca_remove_requester(&pdev->dev);
8409 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8410 }
8411
8412 #endif
8413 #ifdef CONFIG_IXGBE_HWMON
8414 ixgbe_sysfs_exit(adapter);
8415 #endif /* CONFIG_IXGBE_HWMON */
8416
8417 /* remove the added san mac */
8418 ixgbe_del_sanmac_netdev(netdev);
8419
8420 if (netdev->reg_state == NETREG_REGISTERED)
8421 unregister_netdev(netdev);
8422
8423 #ifdef CONFIG_PCI_IOV
8424 /*
8425 * Only disable SR-IOV on unload if the user specified the now
8426 * deprecated max_vfs module parameter.
8427 */
8428 if (max_vfs)
8429 ixgbe_disable_sriov(adapter);
8430 #endif
8431 ixgbe_clear_interrupt_scheme(adapter);
8432
8433 ixgbe_release_hw_control(adapter);
8434
8435 #ifdef CONFIG_DCB
8436 kfree(adapter->ixgbe_ieee_pfc);
8437 kfree(adapter->ixgbe_ieee_ets);
8438
8439 #endif
8440 iounmap(adapter->io_addr);
8441 pci_release_selected_regions(pdev, pci_select_bars(pdev,
8442 IORESOURCE_MEM));
8443
8444 e_dev_info("complete\n");
8445
8446 kfree(adapter->mac_table);
8447 free_netdev(netdev);
8448
8449 pci_disable_pcie_error_reporting(pdev);
8450
8451 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8452 pci_disable_device(pdev);
8453 }
8454
8455 /**
8456 * ixgbe_io_error_detected - called when PCI error is detected
8457 * @pdev: Pointer to PCI device
8458 * @state: The current pci connection state
8459 *
8460 * This function is called after a PCI bus error affecting
8461 * this device has been detected.
8462 */
8463 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
8464 pci_channel_state_t state)
8465 {
8466 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8467 struct net_device *netdev = adapter->netdev;
8468
8469 #ifdef CONFIG_PCI_IOV
8470 struct ixgbe_hw *hw = &adapter->hw;
8471 struct pci_dev *bdev, *vfdev;
8472 u32 dw0, dw1, dw2, dw3;
8473 int vf, pos;
8474 u16 req_id, pf_func;
8475
8476 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8477 adapter->num_vfs == 0)
8478 goto skip_bad_vf_detection;
8479
8480 bdev = pdev->bus->self;
8481 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
8482 bdev = bdev->bus->self;
8483
8484 if (!bdev)
8485 goto skip_bad_vf_detection;
8486
8487 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8488 if (!pos)
8489 goto skip_bad_vf_detection;
8490
8491 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
8492 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
8493 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
8494 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
8495 if (ixgbe_removed(hw->hw_addr))
8496 goto skip_bad_vf_detection;
8497
8498 req_id = dw1 >> 16;
8499 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8500 if (!(req_id & 0x0080))
8501 goto skip_bad_vf_detection;
8502
8503 pf_func = req_id & 0x01;
8504 if ((pf_func & 1) == (pdev->devfn & 1)) {
8505 unsigned int device_id;
8506
8507 vf = (req_id & 0x7F) >> 1;
8508 e_dev_err("VF %d has caused a PCIe error\n", vf);
8509 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8510 "%8.8x\tdw3: %8.8x\n",
8511 dw0, dw1, dw2, dw3);
8512 switch (adapter->hw.mac.type) {
8513 case ixgbe_mac_82599EB:
8514 device_id = IXGBE_82599_VF_DEVICE_ID;
8515 break;
8516 case ixgbe_mac_X540:
8517 device_id = IXGBE_X540_VF_DEVICE_ID;
8518 break;
8519 default:
8520 device_id = 0;
8521 break;
8522 }
8523
8524 /* Find the pci device of the offending VF */
8525 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
8526 while (vfdev) {
8527 if (vfdev->devfn == (req_id & 0xFF))
8528 break;
8529 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
8530 device_id, vfdev);
8531 }
8532 /*
8533 * There's a slim chance the VF could have been hot plugged,
8534 * so if it is no longer present we don't need to issue the
8535 * VFLR. Just clean up the AER in that case.
8536 */
8537 if (vfdev) {
8538 e_dev_err("Issuing VFLR to VF %d\n", vf);
8539 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
8540 /* Free device reference count */
8541 pci_dev_put(vfdev);
8542 }
8543
8544 pci_cleanup_aer_uncorrect_error_status(pdev);
8545 }
8546
8547 /*
8548 * Even though the error may have occurred on the other port
8549 * we still need to increment the vf error reference count for
8550 * both ports because the I/O resume function will be called
8551 * for both of them.
8552 */
8553 adapter->vferr_refcount++;
8554
8555 return PCI_ERS_RESULT_RECOVERED;
8556
8557 skip_bad_vf_detection:
8558 #endif /* CONFIG_PCI_IOV */
8559 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
8560 return PCI_ERS_RESULT_DISCONNECT;
8561
8562 rtnl_lock();
8563 netif_device_detach(netdev);
8564
8565 if (state == pci_channel_io_perm_failure) {
8566 rtnl_unlock();
8567 return PCI_ERS_RESULT_DISCONNECT;
8568 }
8569
8570 if (netif_running(netdev))
8571 ixgbe_down(adapter);
8572
8573 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8574 pci_disable_device(pdev);
8575 rtnl_unlock();
8576
8577 /* Request a slot reset. */
8578 return PCI_ERS_RESULT_NEED_RESET;
8579 }
8580
8581 /**
8582 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8583 * @pdev: Pointer to PCI device
8584 *
8585 * Restart the card from scratch, as if from a cold-boot.
8586 */
8587 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8588 {
8589 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8590 pci_ers_result_t result;
8591 int err;
8592
8593 if (pci_enable_device_mem(pdev)) {
8594 e_err(probe, "Cannot re-enable PCI device after reset.\n");
8595 result = PCI_ERS_RESULT_DISCONNECT;
8596 } else {
8597 smp_mb__before_atomic();
8598 clear_bit(__IXGBE_DISABLED, &adapter->state);
8599 adapter->hw.hw_addr = adapter->io_addr;
8600 pci_set_master(pdev);
8601 pci_restore_state(pdev);
8602 pci_save_state(pdev);
8603
8604 pci_wake_from_d3(pdev, false);
8605
8606 ixgbe_reset(adapter);
8607 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
8608 result = PCI_ERS_RESULT_RECOVERED;
8609 }
8610
8611 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8612 if (err) {
8613 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8614 "failed 0x%0x\n", err);
8615 /* non-fatal, continue */
8616 }
8617
8618 return result;
8619 }
8620
8621 /**
8622 * ixgbe_io_resume - called when traffic can start flowing again.
8623 * @pdev: Pointer to PCI device
8624 *
8625 * This callback is called when the error recovery driver tells us that
8626 * its OK to resume normal operation.
8627 */
8628 static void ixgbe_io_resume(struct pci_dev *pdev)
8629 {
8630 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8631 struct net_device *netdev = adapter->netdev;
8632
8633 #ifdef CONFIG_PCI_IOV
8634 if (adapter->vferr_refcount) {
8635 e_info(drv, "Resuming after VF err\n");
8636 adapter->vferr_refcount--;
8637 return;
8638 }
8639
8640 #endif
8641 if (netif_running(netdev))
8642 ixgbe_up(adapter);
8643
8644 netif_device_attach(netdev);
8645 }
8646
8647 static const struct pci_error_handlers ixgbe_err_handler = {
8648 .error_detected = ixgbe_io_error_detected,
8649 .slot_reset = ixgbe_io_slot_reset,
8650 .resume = ixgbe_io_resume,
8651 };
8652
8653 static struct pci_driver ixgbe_driver = {
8654 .name = ixgbe_driver_name,
8655 .id_table = ixgbe_pci_tbl,
8656 .probe = ixgbe_probe,
8657 .remove = ixgbe_remove,
8658 #ifdef CONFIG_PM
8659 .suspend = ixgbe_suspend,
8660 .resume = ixgbe_resume,
8661 #endif
8662 .shutdown = ixgbe_shutdown,
8663 .sriov_configure = ixgbe_pci_sriov_configure,
8664 .err_handler = &ixgbe_err_handler
8665 };
8666
8667 /**
8668 * ixgbe_init_module - Driver Registration Routine
8669 *
8670 * ixgbe_init_module is the first routine called when the driver is
8671 * loaded. All it does is register with the PCI subsystem.
8672 **/
8673 static int __init ixgbe_init_module(void)
8674 {
8675 int ret;
8676 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
8677 pr_info("%s\n", ixgbe_copyright);
8678
8679 ixgbe_dbg_init();
8680
8681 ret = pci_register_driver(&ixgbe_driver);
8682 if (ret) {
8683 ixgbe_dbg_exit();
8684 return ret;
8685 }
8686
8687 #ifdef CONFIG_IXGBE_DCA
8688 dca_register_notify(&dca_notifier);
8689 #endif
8690
8691 return 0;
8692 }
8693
8694 module_init(ixgbe_init_module);
8695
8696 /**
8697 * ixgbe_exit_module - Driver Exit Cleanup Routine
8698 *
8699 * ixgbe_exit_module is called just before the driver is removed
8700 * from memory.
8701 **/
8702 static void __exit ixgbe_exit_module(void)
8703 {
8704 #ifdef CONFIG_IXGBE_DCA
8705 dca_unregister_notify(&dca_notifier);
8706 #endif
8707 pci_unregister_driver(&ixgbe_driver);
8708
8709 ixgbe_dbg_exit();
8710
8711 rcu_barrier(); /* Wait for completion of call_rcu()'s */
8712 }
8713
8714 #ifdef CONFIG_IXGBE_DCA
8715 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
8716 void *p)
8717 {
8718 int ret_val;
8719
8720 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
8721 __ixgbe_notify_dca);
8722
8723 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8724 }
8725
8726 #endif /* CONFIG_IXGBE_DCA */
8727
8728 module_exit(ixgbe_exit_module);
8729
8730 /* ixgbe_main.c */
Linux kernel - Deliverables
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