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ixgbe: Add support for toggling VLAN filtering flag via ethtool
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2016 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/types.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/vmalloc.h>
34 #include <linux/string.h>
35 #include <linux/in.h>
36 #include <linux/interrupt.h>
37 #include <linux/ip.h>
38 #include <linux/tcp.h>
39 #include <linux/sctp.h>
40 #include <linux/pkt_sched.h>
41 #include <linux/ipv6.h>
42 #include <linux/slab.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/etherdevice.h>
46 #include <linux/ethtool.h>
47 #include <linux/if.h>
48 #include <linux/if_vlan.h>
49 #include <linux/if_macvlan.h>
50 #include <linux/if_bridge.h>
51 #include <linux/prefetch.h>
52 #include <scsi/fc/fc_fcoe.h>
53 #include <net/vxlan.h>
54 #include <net/pkt_cls.h>
55 #include <net/tc_act/tc_gact.h>
56
57 #include "ixgbe.h"
58 #include "ixgbe_common.h"
59 #include "ixgbe_dcb_82599.h"
60 #include "ixgbe_sriov.h"
61 #include "ixgbe_model.h"
62
63 char ixgbe_driver_name[] = "ixgbe";
64 static const char ixgbe_driver_string[] =
65 "Intel(R) 10 Gigabit PCI Express Network Driver";
66 #ifdef IXGBE_FCOE
67 char ixgbe_default_device_descr[] =
68 "Intel(R) 10 Gigabit Network Connection";
69 #else
70 static char ixgbe_default_device_descr[] =
71 "Intel(R) 10 Gigabit Network Connection";
72 #endif
73 #define DRV_VERSION "4.2.1-k"
74 const char ixgbe_driver_version[] = DRV_VERSION;
75 static const char ixgbe_copyright[] =
76 "Copyright (c) 1999-2015 Intel Corporation.";
77
78 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
79
80 static const struct ixgbe_info *ixgbe_info_tbl[] = {
81 [board_82598] = &ixgbe_82598_info,
82 [board_82599] = &ixgbe_82599_info,
83 [board_X540] = &ixgbe_X540_info,
84 [board_X550] = &ixgbe_X550_info,
85 [board_X550EM_x] = &ixgbe_X550EM_x_info,
86 };
87
88 /* ixgbe_pci_tbl - PCI Device ID Table
89 *
90 * Wildcard entries (PCI_ANY_ID) should come last
91 * Last entry must be all 0s
92 *
93 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
94 * Class, Class Mask, private data (not used) }
95 */
96 static const struct pci_device_id ixgbe_pci_tbl[] = {
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
132 /* required last entry */
133 {0, }
134 };
135 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
136
137 #ifdef CONFIG_IXGBE_DCA
138 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
139 void *p);
140 static struct notifier_block dca_notifier = {
141 .notifier_call = ixgbe_notify_dca,
142 .next = NULL,
143 .priority = 0
144 };
145 #endif
146
147 #ifdef CONFIG_PCI_IOV
148 static unsigned int max_vfs;
149 module_param(max_vfs, uint, 0);
150 MODULE_PARM_DESC(max_vfs,
151 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
152 #endif /* CONFIG_PCI_IOV */
153
154 static unsigned int allow_unsupported_sfp;
155 module_param(allow_unsupported_sfp, uint, 0);
156 MODULE_PARM_DESC(allow_unsupported_sfp,
157 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
158
159 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
160 static int debug = -1;
161 module_param(debug, int, 0);
162 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
163
164 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
165 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
166 MODULE_LICENSE("GPL");
167 MODULE_VERSION(DRV_VERSION);
168
169 static struct workqueue_struct *ixgbe_wq;
170
171 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
172
173 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
174 u32 reg, u16 *value)
175 {
176 struct pci_dev *parent_dev;
177 struct pci_bus *parent_bus;
178
179 parent_bus = adapter->pdev->bus->parent;
180 if (!parent_bus)
181 return -1;
182
183 parent_dev = parent_bus->self;
184 if (!parent_dev)
185 return -1;
186
187 if (!pci_is_pcie(parent_dev))
188 return -1;
189
190 pcie_capability_read_word(parent_dev, reg, value);
191 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
192 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
193 return -1;
194 return 0;
195 }
196
197 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
198 {
199 struct ixgbe_hw *hw = &adapter->hw;
200 u16 link_status = 0;
201 int err;
202
203 hw->bus.type = ixgbe_bus_type_pci_express;
204
205 /* Get the negotiated link width and speed from PCI config space of the
206 * parent, as this device is behind a switch
207 */
208 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
209
210 /* assume caller will handle error case */
211 if (err)
212 return err;
213
214 hw->bus.width = ixgbe_convert_bus_width(link_status);
215 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
216
217 return 0;
218 }
219
220 /**
221 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
222 * @hw: hw specific details
223 *
224 * This function is used by probe to determine whether a device's PCI-Express
225 * bandwidth details should be gathered from the parent bus instead of from the
226 * device. Used to ensure that various locations all have the correct device ID
227 * checks.
228 */
229 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
230 {
231 switch (hw->device_id) {
232 case IXGBE_DEV_ID_82599_SFP_SF_QP:
233 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
234 return true;
235 default:
236 return false;
237 }
238 }
239
240 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
241 int expected_gts)
242 {
243 struct ixgbe_hw *hw = &adapter->hw;
244 int max_gts = 0;
245 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
246 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
247 struct pci_dev *pdev;
248
249 /* Some devices are not connected over PCIe and thus do not negotiate
250 * speed. These devices do not have valid bus info, and thus any report
251 * we generate may not be correct.
252 */
253 if (hw->bus.type == ixgbe_bus_type_internal)
254 return;
255
256 /* determine whether to use the parent device */
257 if (ixgbe_pcie_from_parent(&adapter->hw))
258 pdev = adapter->pdev->bus->parent->self;
259 else
260 pdev = adapter->pdev;
261
262 if (pcie_get_minimum_link(pdev, &speed, &width) ||
263 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
264 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
265 return;
266 }
267
268 switch (speed) {
269 case PCIE_SPEED_2_5GT:
270 /* 8b/10b encoding reduces max throughput by 20% */
271 max_gts = 2 * width;
272 break;
273 case PCIE_SPEED_5_0GT:
274 /* 8b/10b encoding reduces max throughput by 20% */
275 max_gts = 4 * width;
276 break;
277 case PCIE_SPEED_8_0GT:
278 /* 128b/130b encoding reduces throughput by less than 2% */
279 max_gts = 8 * width;
280 break;
281 default:
282 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
283 return;
284 }
285
286 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
287 max_gts);
288 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
289 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
290 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
291 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
292 "Unknown"),
293 width,
294 (speed == PCIE_SPEED_2_5GT ? "20%" :
295 speed == PCIE_SPEED_5_0GT ? "20%" :
296 speed == PCIE_SPEED_8_0GT ? "<2%" :
297 "Unknown"));
298
299 if (max_gts < expected_gts) {
300 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
301 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
302 expected_gts);
303 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
304 }
305 }
306
307 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
308 {
309 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
310 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
311 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
312 queue_work(ixgbe_wq, &adapter->service_task);
313 }
314
315 static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
316 {
317 struct ixgbe_adapter *adapter = hw->back;
318
319 if (!hw->hw_addr)
320 return;
321 hw->hw_addr = NULL;
322 e_dev_err("Adapter removed\n");
323 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
324 ixgbe_service_event_schedule(adapter);
325 }
326
327 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
328 {
329 u32 value;
330
331 /* The following check not only optimizes a bit by not
332 * performing a read on the status register when the
333 * register just read was a status register read that
334 * returned IXGBE_FAILED_READ_REG. It also blocks any
335 * potential recursion.
336 */
337 if (reg == IXGBE_STATUS) {
338 ixgbe_remove_adapter(hw);
339 return;
340 }
341 value = ixgbe_read_reg(hw, IXGBE_STATUS);
342 if (value == IXGBE_FAILED_READ_REG)
343 ixgbe_remove_adapter(hw);
344 }
345
346 /**
347 * ixgbe_read_reg - Read from device register
348 * @hw: hw specific details
349 * @reg: offset of register to read
350 *
351 * Returns : value read or IXGBE_FAILED_READ_REG if removed
352 *
353 * This function is used to read device registers. It checks for device
354 * removal by confirming any read that returns all ones by checking the
355 * status register value for all ones. This function avoids reading from
356 * the hardware if a removal was previously detected in which case it
357 * returns IXGBE_FAILED_READ_REG (all ones).
358 */
359 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
360 {
361 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
362 u32 value;
363
364 if (ixgbe_removed(reg_addr))
365 return IXGBE_FAILED_READ_REG;
366 value = readl(reg_addr + reg);
367 if (unlikely(value == IXGBE_FAILED_READ_REG))
368 ixgbe_check_remove(hw, reg);
369 return value;
370 }
371
372 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
373 {
374 u16 value;
375
376 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
377 if (value == IXGBE_FAILED_READ_CFG_WORD) {
378 ixgbe_remove_adapter(hw);
379 return true;
380 }
381 return false;
382 }
383
384 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
385 {
386 struct ixgbe_adapter *adapter = hw->back;
387 u16 value;
388
389 if (ixgbe_removed(hw->hw_addr))
390 return IXGBE_FAILED_READ_CFG_WORD;
391 pci_read_config_word(adapter->pdev, reg, &value);
392 if (value == IXGBE_FAILED_READ_CFG_WORD &&
393 ixgbe_check_cfg_remove(hw, adapter->pdev))
394 return IXGBE_FAILED_READ_CFG_WORD;
395 return value;
396 }
397
398 #ifdef CONFIG_PCI_IOV
399 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
400 {
401 struct ixgbe_adapter *adapter = hw->back;
402 u32 value;
403
404 if (ixgbe_removed(hw->hw_addr))
405 return IXGBE_FAILED_READ_CFG_DWORD;
406 pci_read_config_dword(adapter->pdev, reg, &value);
407 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
408 ixgbe_check_cfg_remove(hw, adapter->pdev))
409 return IXGBE_FAILED_READ_CFG_DWORD;
410 return value;
411 }
412 #endif /* CONFIG_PCI_IOV */
413
414 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
415 {
416 struct ixgbe_adapter *adapter = hw->back;
417
418 if (ixgbe_removed(hw->hw_addr))
419 return;
420 pci_write_config_word(adapter->pdev, reg, value);
421 }
422
423 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
424 {
425 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
426
427 /* flush memory to make sure state is correct before next watchdog */
428 smp_mb__before_atomic();
429 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
430 }
431
432 struct ixgbe_reg_info {
433 u32 ofs;
434 char *name;
435 };
436
437 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
438
439 /* General Registers */
440 {IXGBE_CTRL, "CTRL"},
441 {IXGBE_STATUS, "STATUS"},
442 {IXGBE_CTRL_EXT, "CTRL_EXT"},
443
444 /* Interrupt Registers */
445 {IXGBE_EICR, "EICR"},
446
447 /* RX Registers */
448 {IXGBE_SRRCTL(0), "SRRCTL"},
449 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
450 {IXGBE_RDLEN(0), "RDLEN"},
451 {IXGBE_RDH(0), "RDH"},
452 {IXGBE_RDT(0), "RDT"},
453 {IXGBE_RXDCTL(0), "RXDCTL"},
454 {IXGBE_RDBAL(0), "RDBAL"},
455 {IXGBE_RDBAH(0), "RDBAH"},
456
457 /* TX Registers */
458 {IXGBE_TDBAL(0), "TDBAL"},
459 {IXGBE_TDBAH(0), "TDBAH"},
460 {IXGBE_TDLEN(0), "TDLEN"},
461 {IXGBE_TDH(0), "TDH"},
462 {IXGBE_TDT(0), "TDT"},
463 {IXGBE_TXDCTL(0), "TXDCTL"},
464
465 /* List Terminator */
466 { .name = NULL }
467 };
468
469
470 /*
471 * ixgbe_regdump - register printout routine
472 */
473 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
474 {
475 int i = 0, j = 0;
476 char rname[16];
477 u32 regs[64];
478
479 switch (reginfo->ofs) {
480 case IXGBE_SRRCTL(0):
481 for (i = 0; i < 64; i++)
482 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
483 break;
484 case IXGBE_DCA_RXCTRL(0):
485 for (i = 0; i < 64; i++)
486 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
487 break;
488 case IXGBE_RDLEN(0):
489 for (i = 0; i < 64; i++)
490 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
491 break;
492 case IXGBE_RDH(0):
493 for (i = 0; i < 64; i++)
494 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
495 break;
496 case IXGBE_RDT(0):
497 for (i = 0; i < 64; i++)
498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
499 break;
500 case IXGBE_RXDCTL(0):
501 for (i = 0; i < 64; i++)
502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
503 break;
504 case IXGBE_RDBAL(0):
505 for (i = 0; i < 64; i++)
506 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
507 break;
508 case IXGBE_RDBAH(0):
509 for (i = 0; i < 64; i++)
510 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
511 break;
512 case IXGBE_TDBAL(0):
513 for (i = 0; i < 64; i++)
514 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
515 break;
516 case IXGBE_TDBAH(0):
517 for (i = 0; i < 64; i++)
518 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
519 break;
520 case IXGBE_TDLEN(0):
521 for (i = 0; i < 64; i++)
522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
523 break;
524 case IXGBE_TDH(0):
525 for (i = 0; i < 64; i++)
526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
527 break;
528 case IXGBE_TDT(0):
529 for (i = 0; i < 64; i++)
530 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
531 break;
532 case IXGBE_TXDCTL(0):
533 for (i = 0; i < 64; i++)
534 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
535 break;
536 default:
537 pr_info("%-15s %08x\n", reginfo->name,
538 IXGBE_READ_REG(hw, reginfo->ofs));
539 return;
540 }
541
542 for (i = 0; i < 8; i++) {
543 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
544 pr_err("%-15s", rname);
545 for (j = 0; j < 8; j++)
546 pr_cont(" %08x", regs[i*8+j]);
547 pr_cont("\n");
548 }
549
550 }
551
552 /*
553 * ixgbe_dump - Print registers, tx-rings and rx-rings
554 */
555 static void ixgbe_dump(struct ixgbe_adapter *adapter)
556 {
557 struct net_device *netdev = adapter->netdev;
558 struct ixgbe_hw *hw = &adapter->hw;
559 struct ixgbe_reg_info *reginfo;
560 int n = 0;
561 struct ixgbe_ring *tx_ring;
562 struct ixgbe_tx_buffer *tx_buffer;
563 union ixgbe_adv_tx_desc *tx_desc;
564 struct my_u0 { u64 a; u64 b; } *u0;
565 struct ixgbe_ring *rx_ring;
566 union ixgbe_adv_rx_desc *rx_desc;
567 struct ixgbe_rx_buffer *rx_buffer_info;
568 u32 staterr;
569 int i = 0;
570
571 if (!netif_msg_hw(adapter))
572 return;
573
574 /* Print netdevice Info */
575 if (netdev) {
576 dev_info(&adapter->pdev->dev, "Net device Info\n");
577 pr_info("Device Name state "
578 "trans_start last_rx\n");
579 pr_info("%-15s %016lX %016lX %016lX\n",
580 netdev->name,
581 netdev->state,
582 netdev->trans_start,
583 netdev->last_rx);
584 }
585
586 /* Print Registers */
587 dev_info(&adapter->pdev->dev, "Register Dump\n");
588 pr_info(" Register Name Value\n");
589 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
590 reginfo->name; reginfo++) {
591 ixgbe_regdump(hw, reginfo);
592 }
593
594 /* Print TX Ring Summary */
595 if (!netdev || !netif_running(netdev))
596 return;
597
598 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
599 pr_info(" %s %s %s %s\n",
600 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
601 "leng", "ntw", "timestamp");
602 for (n = 0; n < adapter->num_tx_queues; n++) {
603 tx_ring = adapter->tx_ring[n];
604 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
605 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
606 n, tx_ring->next_to_use, tx_ring->next_to_clean,
607 (u64)dma_unmap_addr(tx_buffer, dma),
608 dma_unmap_len(tx_buffer, len),
609 tx_buffer->next_to_watch,
610 (u64)tx_buffer->time_stamp);
611 }
612
613 /* Print TX Rings */
614 if (!netif_msg_tx_done(adapter))
615 goto rx_ring_summary;
616
617 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
618
619 /* Transmit Descriptor Formats
620 *
621 * 82598 Advanced Transmit Descriptor
622 * +--------------------------------------------------------------+
623 * 0 | Buffer Address [63:0] |
624 * +--------------------------------------------------------------+
625 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
626 * +--------------------------------------------------------------+
627 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
628 *
629 * 82598 Advanced Transmit Descriptor (Write-Back Format)
630 * +--------------------------------------------------------------+
631 * 0 | RSV [63:0] |
632 * +--------------------------------------------------------------+
633 * 8 | RSV | STA | NXTSEQ |
634 * +--------------------------------------------------------------+
635 * 63 36 35 32 31 0
636 *
637 * 82599+ Advanced Transmit Descriptor
638 * +--------------------------------------------------------------+
639 * 0 | Buffer Address [63:0] |
640 * +--------------------------------------------------------------+
641 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
642 * +--------------------------------------------------------------+
643 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
644 *
645 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
646 * +--------------------------------------------------------------+
647 * 0 | RSV [63:0] |
648 * +--------------------------------------------------------------+
649 * 8 | RSV | STA | RSV |
650 * +--------------------------------------------------------------+
651 * 63 36 35 32 31 0
652 */
653
654 for (n = 0; n < adapter->num_tx_queues; n++) {
655 tx_ring = adapter->tx_ring[n];
656 pr_info("------------------------------------\n");
657 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
658 pr_info("------------------------------------\n");
659 pr_info("%s%s %s %s %s %s\n",
660 "T [desc] [address 63:0 ] ",
661 "[PlPOIdStDDt Ln] [bi->dma ] ",
662 "leng", "ntw", "timestamp", "bi->skb");
663
664 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
665 tx_desc = IXGBE_TX_DESC(tx_ring, i);
666 tx_buffer = &tx_ring->tx_buffer_info[i];
667 u0 = (struct my_u0 *)tx_desc;
668 if (dma_unmap_len(tx_buffer, len) > 0) {
669 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
670 i,
671 le64_to_cpu(u0->a),
672 le64_to_cpu(u0->b),
673 (u64)dma_unmap_addr(tx_buffer, dma),
674 dma_unmap_len(tx_buffer, len),
675 tx_buffer->next_to_watch,
676 (u64)tx_buffer->time_stamp,
677 tx_buffer->skb);
678 if (i == tx_ring->next_to_use &&
679 i == tx_ring->next_to_clean)
680 pr_cont(" NTC/U\n");
681 else if (i == tx_ring->next_to_use)
682 pr_cont(" NTU\n");
683 else if (i == tx_ring->next_to_clean)
684 pr_cont(" NTC\n");
685 else
686 pr_cont("\n");
687
688 if (netif_msg_pktdata(adapter) &&
689 tx_buffer->skb)
690 print_hex_dump(KERN_INFO, "",
691 DUMP_PREFIX_ADDRESS, 16, 1,
692 tx_buffer->skb->data,
693 dma_unmap_len(tx_buffer, len),
694 true);
695 }
696 }
697 }
698
699 /* Print RX Rings Summary */
700 rx_ring_summary:
701 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
702 pr_info("Queue [NTU] [NTC]\n");
703 for (n = 0; n < adapter->num_rx_queues; n++) {
704 rx_ring = adapter->rx_ring[n];
705 pr_info("%5d %5X %5X\n",
706 n, rx_ring->next_to_use, rx_ring->next_to_clean);
707 }
708
709 /* Print RX Rings */
710 if (!netif_msg_rx_status(adapter))
711 return;
712
713 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
714
715 /* Receive Descriptor Formats
716 *
717 * 82598 Advanced Receive Descriptor (Read) Format
718 * 63 1 0
719 * +-----------------------------------------------------+
720 * 0 | Packet Buffer Address [63:1] |A0/NSE|
721 * +----------------------------------------------+------+
722 * 8 | Header Buffer Address [63:1] | DD |
723 * +-----------------------------------------------------+
724 *
725 *
726 * 82598 Advanced Receive Descriptor (Write-Back) Format
727 *
728 * 63 48 47 32 31 30 21 20 16 15 4 3 0
729 * +------------------------------------------------------+
730 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
731 * | Packet | IP | | | | Type | Type |
732 * | Checksum | Ident | | | | | |
733 * +------------------------------------------------------+
734 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
735 * +------------------------------------------------------+
736 * 63 48 47 32 31 20 19 0
737 *
738 * 82599+ Advanced Receive Descriptor (Read) Format
739 * 63 1 0
740 * +-----------------------------------------------------+
741 * 0 | Packet Buffer Address [63:1] |A0/NSE|
742 * +----------------------------------------------+------+
743 * 8 | Header Buffer Address [63:1] | DD |
744 * +-----------------------------------------------------+
745 *
746 *
747 * 82599+ Advanced Receive Descriptor (Write-Back) Format
748 *
749 * 63 48 47 32 31 30 21 20 17 16 4 3 0
750 * +------------------------------------------------------+
751 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
752 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
753 * |/ Flow Dir Flt ID | | | | | |
754 * +------------------------------------------------------+
755 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
756 * +------------------------------------------------------+
757 * 63 48 47 32 31 20 19 0
758 */
759
760 for (n = 0; n < adapter->num_rx_queues; n++) {
761 rx_ring = adapter->rx_ring[n];
762 pr_info("------------------------------------\n");
763 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
764 pr_info("------------------------------------\n");
765 pr_info("%s%s%s",
766 "R [desc] [ PktBuf A0] ",
767 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
768 "<-- Adv Rx Read format\n");
769 pr_info("%s%s%s",
770 "RWB[desc] [PcsmIpSHl PtRs] ",
771 "[vl er S cks ln] ---------------- [bi->skb ] ",
772 "<-- Adv Rx Write-Back format\n");
773
774 for (i = 0; i < rx_ring->count; i++) {
775 rx_buffer_info = &rx_ring->rx_buffer_info[i];
776 rx_desc = IXGBE_RX_DESC(rx_ring, i);
777 u0 = (struct my_u0 *)rx_desc;
778 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
779 if (staterr & IXGBE_RXD_STAT_DD) {
780 /* Descriptor Done */
781 pr_info("RWB[0x%03X] %016llX "
782 "%016llX ---------------- %p", i,
783 le64_to_cpu(u0->a),
784 le64_to_cpu(u0->b),
785 rx_buffer_info->skb);
786 } else {
787 pr_info("R [0x%03X] %016llX "
788 "%016llX %016llX %p", i,
789 le64_to_cpu(u0->a),
790 le64_to_cpu(u0->b),
791 (u64)rx_buffer_info->dma,
792 rx_buffer_info->skb);
793
794 if (netif_msg_pktdata(adapter) &&
795 rx_buffer_info->dma) {
796 print_hex_dump(KERN_INFO, "",
797 DUMP_PREFIX_ADDRESS, 16, 1,
798 page_address(rx_buffer_info->page) +
799 rx_buffer_info->page_offset,
800 ixgbe_rx_bufsz(rx_ring), true);
801 }
802 }
803
804 if (i == rx_ring->next_to_use)
805 pr_cont(" NTU\n");
806 else if (i == rx_ring->next_to_clean)
807 pr_cont(" NTC\n");
808 else
809 pr_cont("\n");
810
811 }
812 }
813 }
814
815 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
816 {
817 u32 ctrl_ext;
818
819 /* Let firmware take over control of h/w */
820 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
821 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
822 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
823 }
824
825 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
826 {
827 u32 ctrl_ext;
828
829 /* Let firmware know the driver has taken over */
830 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
831 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
832 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
833 }
834
835 /**
836 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
837 * @adapter: pointer to adapter struct
838 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
839 * @queue: queue to map the corresponding interrupt to
840 * @msix_vector: the vector to map to the corresponding queue
841 *
842 */
843 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
844 u8 queue, u8 msix_vector)
845 {
846 u32 ivar, index;
847 struct ixgbe_hw *hw = &adapter->hw;
848 switch (hw->mac.type) {
849 case ixgbe_mac_82598EB:
850 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
851 if (direction == -1)
852 direction = 0;
853 index = (((direction * 64) + queue) >> 2) & 0x1F;
854 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
855 ivar &= ~(0xFF << (8 * (queue & 0x3)));
856 ivar |= (msix_vector << (8 * (queue & 0x3)));
857 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
858 break;
859 case ixgbe_mac_82599EB:
860 case ixgbe_mac_X540:
861 case ixgbe_mac_X550:
862 case ixgbe_mac_X550EM_x:
863 if (direction == -1) {
864 /* other causes */
865 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
866 index = ((queue & 1) * 8);
867 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
868 ivar &= ~(0xFF << index);
869 ivar |= (msix_vector << index);
870 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
871 break;
872 } else {
873 /* tx or rx causes */
874 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
875 index = ((16 * (queue & 1)) + (8 * direction));
876 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
877 ivar &= ~(0xFF << index);
878 ivar |= (msix_vector << index);
879 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
880 break;
881 }
882 default:
883 break;
884 }
885 }
886
887 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
888 u64 qmask)
889 {
890 u32 mask;
891
892 switch (adapter->hw.mac.type) {
893 case ixgbe_mac_82598EB:
894 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
895 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
896 break;
897 case ixgbe_mac_82599EB:
898 case ixgbe_mac_X540:
899 case ixgbe_mac_X550:
900 case ixgbe_mac_X550EM_x:
901 mask = (qmask & 0xFFFFFFFF);
902 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
903 mask = (qmask >> 32);
904 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
905 break;
906 default:
907 break;
908 }
909 }
910
911 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
912 struct ixgbe_tx_buffer *tx_buffer)
913 {
914 if (tx_buffer->skb) {
915 dev_kfree_skb_any(tx_buffer->skb);
916 if (dma_unmap_len(tx_buffer, len))
917 dma_unmap_single(ring->dev,
918 dma_unmap_addr(tx_buffer, dma),
919 dma_unmap_len(tx_buffer, len),
920 DMA_TO_DEVICE);
921 } else if (dma_unmap_len(tx_buffer, len)) {
922 dma_unmap_page(ring->dev,
923 dma_unmap_addr(tx_buffer, dma),
924 dma_unmap_len(tx_buffer, len),
925 DMA_TO_DEVICE);
926 }
927 tx_buffer->next_to_watch = NULL;
928 tx_buffer->skb = NULL;
929 dma_unmap_len_set(tx_buffer, len, 0);
930 /* tx_buffer must be completely set up in the transmit path */
931 }
932
933 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
934 {
935 struct ixgbe_hw *hw = &adapter->hw;
936 struct ixgbe_hw_stats *hwstats = &adapter->stats;
937 int i;
938 u32 data;
939
940 if ((hw->fc.current_mode != ixgbe_fc_full) &&
941 (hw->fc.current_mode != ixgbe_fc_rx_pause))
942 return;
943
944 switch (hw->mac.type) {
945 case ixgbe_mac_82598EB:
946 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
947 break;
948 default:
949 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
950 }
951 hwstats->lxoffrxc += data;
952
953 /* refill credits (no tx hang) if we received xoff */
954 if (!data)
955 return;
956
957 for (i = 0; i < adapter->num_tx_queues; i++)
958 clear_bit(__IXGBE_HANG_CHECK_ARMED,
959 &adapter->tx_ring[i]->state);
960 }
961
962 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
963 {
964 struct ixgbe_hw *hw = &adapter->hw;
965 struct ixgbe_hw_stats *hwstats = &adapter->stats;
966 u32 xoff[8] = {0};
967 u8 tc;
968 int i;
969 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
970
971 if (adapter->ixgbe_ieee_pfc)
972 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
973
974 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
975 ixgbe_update_xoff_rx_lfc(adapter);
976 return;
977 }
978
979 /* update stats for each tc, only valid with PFC enabled */
980 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
981 u32 pxoffrxc;
982
983 switch (hw->mac.type) {
984 case ixgbe_mac_82598EB:
985 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
986 break;
987 default:
988 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
989 }
990 hwstats->pxoffrxc[i] += pxoffrxc;
991 /* Get the TC for given UP */
992 tc = netdev_get_prio_tc_map(adapter->netdev, i);
993 xoff[tc] += pxoffrxc;
994 }
995
996 /* disarm tx queues that have received xoff frames */
997 for (i = 0; i < adapter->num_tx_queues; i++) {
998 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
999
1000 tc = tx_ring->dcb_tc;
1001 if (xoff[tc])
1002 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1003 }
1004 }
1005
1006 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
1007 {
1008 return ring->stats.packets;
1009 }
1010
1011 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1012 {
1013 struct ixgbe_adapter *adapter;
1014 struct ixgbe_hw *hw;
1015 u32 head, tail;
1016
1017 if (ring->l2_accel_priv)
1018 adapter = ring->l2_accel_priv->real_adapter;
1019 else
1020 adapter = netdev_priv(ring->netdev);
1021
1022 hw = &adapter->hw;
1023 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1024 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
1025
1026 if (head != tail)
1027 return (head < tail) ?
1028 tail - head : (tail + ring->count - head);
1029
1030 return 0;
1031 }
1032
1033 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1034 {
1035 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1036 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1037 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1038
1039 clear_check_for_tx_hang(tx_ring);
1040
1041 /*
1042 * Check for a hung queue, but be thorough. This verifies
1043 * that a transmit has been completed since the previous
1044 * check AND there is at least one packet pending. The
1045 * ARMED bit is set to indicate a potential hang. The
1046 * bit is cleared if a pause frame is received to remove
1047 * false hang detection due to PFC or 802.3x frames. By
1048 * requiring this to fail twice we avoid races with
1049 * pfc clearing the ARMED bit and conditions where we
1050 * run the check_tx_hang logic with a transmit completion
1051 * pending but without time to complete it yet.
1052 */
1053 if (tx_done_old == tx_done && tx_pending)
1054 /* make sure it is true for two checks in a row */
1055 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1056 &tx_ring->state);
1057 /* update completed stats and continue */
1058 tx_ring->tx_stats.tx_done_old = tx_done;
1059 /* reset the countdown */
1060 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1061
1062 return false;
1063 }
1064
1065 /**
1066 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1067 * @adapter: driver private struct
1068 **/
1069 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1070 {
1071
1072 /* Do the reset outside of interrupt context */
1073 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1074 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
1075 e_warn(drv, "initiating reset due to tx timeout\n");
1076 ixgbe_service_event_schedule(adapter);
1077 }
1078 }
1079
1080 /**
1081 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate
1082 **/
1083 static int ixgbe_tx_maxrate(struct net_device *netdev,
1084 int queue_index, u32 maxrate)
1085 {
1086 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1087 struct ixgbe_hw *hw = &adapter->hw;
1088 u32 bcnrc_val = ixgbe_link_mbps(adapter);
1089
1090 if (!maxrate)
1091 return 0;
1092
1093 /* Calculate the rate factor values to set */
1094 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT;
1095 bcnrc_val /= maxrate;
1096
1097 /* clear everything but the rate factor */
1098 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK |
1099 IXGBE_RTTBCNRC_RF_DEC_MASK;
1100
1101 /* enable the rate scheduler */
1102 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA;
1103
1104 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index);
1105 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
1106
1107 return 0;
1108 }
1109
1110 /**
1111 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
1112 * @q_vector: structure containing interrupt and ring information
1113 * @tx_ring: tx ring to clean
1114 **/
1115 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
1116 struct ixgbe_ring *tx_ring, int napi_budget)
1117 {
1118 struct ixgbe_adapter *adapter = q_vector->adapter;
1119 struct ixgbe_tx_buffer *tx_buffer;
1120 union ixgbe_adv_tx_desc *tx_desc;
1121 unsigned int total_bytes = 0, total_packets = 0;
1122 unsigned int budget = q_vector->tx.work_limit;
1123 unsigned int i = tx_ring->next_to_clean;
1124
1125 if (test_bit(__IXGBE_DOWN, &adapter->state))
1126 return true;
1127
1128 tx_buffer = &tx_ring->tx_buffer_info[i];
1129 tx_desc = IXGBE_TX_DESC(tx_ring, i);
1130 i -= tx_ring->count;
1131
1132 do {
1133 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1134
1135 /* if next_to_watch is not set then there is no work pending */
1136 if (!eop_desc)
1137 break;
1138
1139 /* prevent any other reads prior to eop_desc */
1140 read_barrier_depends();
1141
1142 /* if DD is not set pending work has not been completed */
1143 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1144 break;
1145
1146 /* clear next_to_watch to prevent false hangs */
1147 tx_buffer->next_to_watch = NULL;
1148
1149 /* update the statistics for this packet */
1150 total_bytes += tx_buffer->bytecount;
1151 total_packets += tx_buffer->gso_segs;
1152
1153 /* free the skb */
1154 napi_consume_skb(tx_buffer->skb, napi_budget);
1155
1156 /* unmap skb header data */
1157 dma_unmap_single(tx_ring->dev,
1158 dma_unmap_addr(tx_buffer, dma),
1159 dma_unmap_len(tx_buffer, len),
1160 DMA_TO_DEVICE);
1161
1162 /* clear tx_buffer data */
1163 tx_buffer->skb = NULL;
1164 dma_unmap_len_set(tx_buffer, len, 0);
1165
1166 /* unmap remaining buffers */
1167 while (tx_desc != eop_desc) {
1168 tx_buffer++;
1169 tx_desc++;
1170 i++;
1171 if (unlikely(!i)) {
1172 i -= tx_ring->count;
1173 tx_buffer = tx_ring->tx_buffer_info;
1174 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1175 }
1176
1177 /* unmap any remaining paged data */
1178 if (dma_unmap_len(tx_buffer, len)) {
1179 dma_unmap_page(tx_ring->dev,
1180 dma_unmap_addr(tx_buffer, dma),
1181 dma_unmap_len(tx_buffer, len),
1182 DMA_TO_DEVICE);
1183 dma_unmap_len_set(tx_buffer, len, 0);
1184 }
1185 }
1186
1187 /* move us one more past the eop_desc for start of next pkt */
1188 tx_buffer++;
1189 tx_desc++;
1190 i++;
1191 if (unlikely(!i)) {
1192 i -= tx_ring->count;
1193 tx_buffer = tx_ring->tx_buffer_info;
1194 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1195 }
1196
1197 /* issue prefetch for next Tx descriptor */
1198 prefetch(tx_desc);
1199
1200 /* update budget accounting */
1201 budget--;
1202 } while (likely(budget));
1203
1204 i += tx_ring->count;
1205 tx_ring->next_to_clean = i;
1206 u64_stats_update_begin(&tx_ring->syncp);
1207 tx_ring->stats.bytes += total_bytes;
1208 tx_ring->stats.packets += total_packets;
1209 u64_stats_update_end(&tx_ring->syncp);
1210 q_vector->tx.total_bytes += total_bytes;
1211 q_vector->tx.total_packets += total_packets;
1212
1213 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1214 /* schedule immediate reset if we believe we hung */
1215 struct ixgbe_hw *hw = &adapter->hw;
1216 e_err(drv, "Detected Tx Unit Hang\n"
1217 " Tx Queue <%d>\n"
1218 " TDH, TDT <%x>, <%x>\n"
1219 " next_to_use <%x>\n"
1220 " next_to_clean <%x>\n"
1221 "tx_buffer_info[next_to_clean]\n"
1222 " time_stamp <%lx>\n"
1223 " jiffies <%lx>\n",
1224 tx_ring->queue_index,
1225 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1226 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1227 tx_ring->next_to_use, i,
1228 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1229
1230 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1231
1232 e_info(probe,
1233 "tx hang %d detected on queue %d, resetting adapter\n",
1234 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1235
1236 /* schedule immediate reset if we believe we hung */
1237 ixgbe_tx_timeout_reset(adapter);
1238
1239 /* the adapter is about to reset, no point in enabling stuff */
1240 return true;
1241 }
1242
1243 netdev_tx_completed_queue(txring_txq(tx_ring),
1244 total_packets, total_bytes);
1245
1246 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1247 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1248 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1249 /* Make sure that anybody stopping the queue after this
1250 * sees the new next_to_clean.
1251 */
1252 smp_mb();
1253 if (__netif_subqueue_stopped(tx_ring->netdev,
1254 tx_ring->queue_index)
1255 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1256 netif_wake_subqueue(tx_ring->netdev,
1257 tx_ring->queue_index);
1258 ++tx_ring->tx_stats.restart_queue;
1259 }
1260 }
1261
1262 return !!budget;
1263 }
1264
1265 #ifdef CONFIG_IXGBE_DCA
1266 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1267 struct ixgbe_ring *tx_ring,
1268 int cpu)
1269 {
1270 struct ixgbe_hw *hw = &adapter->hw;
1271 u32 txctrl = 0;
1272 u16 reg_offset;
1273
1274 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1275 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1276
1277 switch (hw->mac.type) {
1278 case ixgbe_mac_82598EB:
1279 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1280 break;
1281 case ixgbe_mac_82599EB:
1282 case ixgbe_mac_X540:
1283 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1284 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1285 break;
1286 default:
1287 /* for unknown hardware do not write register */
1288 return;
1289 }
1290
1291 /*
1292 * We can enable relaxed ordering for reads, but not writes when
1293 * DCA is enabled. This is due to a known issue in some chipsets
1294 * which will cause the DCA tag to be cleared.
1295 */
1296 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1297 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1298 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1299
1300 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1301 }
1302
1303 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1304 struct ixgbe_ring *rx_ring,
1305 int cpu)
1306 {
1307 struct ixgbe_hw *hw = &adapter->hw;
1308 u32 rxctrl = 0;
1309 u8 reg_idx = rx_ring->reg_idx;
1310
1311 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1312 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1313
1314 switch (hw->mac.type) {
1315 case ixgbe_mac_82599EB:
1316 case ixgbe_mac_X540:
1317 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1318 break;
1319 default:
1320 break;
1321 }
1322
1323 /*
1324 * We can enable relaxed ordering for reads, but not writes when
1325 * DCA is enabled. This is due to a known issue in some chipsets
1326 * which will cause the DCA tag to be cleared.
1327 */
1328 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1329 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
1330 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1331
1332 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1333 }
1334
1335 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1336 {
1337 struct ixgbe_adapter *adapter = q_vector->adapter;
1338 struct ixgbe_ring *ring;
1339 int cpu = get_cpu();
1340
1341 if (q_vector->cpu == cpu)
1342 goto out_no_update;
1343
1344 ixgbe_for_each_ring(ring, q_vector->tx)
1345 ixgbe_update_tx_dca(adapter, ring, cpu);
1346
1347 ixgbe_for_each_ring(ring, q_vector->rx)
1348 ixgbe_update_rx_dca(adapter, ring, cpu);
1349
1350 q_vector->cpu = cpu;
1351 out_no_update:
1352 put_cpu();
1353 }
1354
1355 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1356 {
1357 int i;
1358
1359 /* always use CB2 mode, difference is masked in the CB driver */
1360 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1361 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1362 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1363 else
1364 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1365 IXGBE_DCA_CTRL_DCA_DISABLE);
1366
1367 for (i = 0; i < adapter->num_q_vectors; i++) {
1368 adapter->q_vector[i]->cpu = -1;
1369 ixgbe_update_dca(adapter->q_vector[i]);
1370 }
1371 }
1372
1373 static int __ixgbe_notify_dca(struct device *dev, void *data)
1374 {
1375 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1376 unsigned long event = *(unsigned long *)data;
1377
1378 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1379 return 0;
1380
1381 switch (event) {
1382 case DCA_PROVIDER_ADD:
1383 /* if we're already enabled, don't do it again */
1384 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1385 break;
1386 if (dca_add_requester(dev) == 0) {
1387 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1388 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1389 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1390 break;
1391 }
1392 /* Fall Through since DCA is disabled. */
1393 case DCA_PROVIDER_REMOVE:
1394 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1395 dca_remove_requester(dev);
1396 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1397 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1398 IXGBE_DCA_CTRL_DCA_DISABLE);
1399 }
1400 break;
1401 }
1402
1403 return 0;
1404 }
1405
1406 #endif /* CONFIG_IXGBE_DCA */
1407
1408 #define IXGBE_RSS_L4_TYPES_MASK \
1409 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1410 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1411 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1412 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1413
1414 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1415 union ixgbe_adv_rx_desc *rx_desc,
1416 struct sk_buff *skb)
1417 {
1418 u16 rss_type;
1419
1420 if (!(ring->netdev->features & NETIF_F_RXHASH))
1421 return;
1422
1423 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1424 IXGBE_RXDADV_RSSTYPE_MASK;
1425
1426 if (!rss_type)
1427 return;
1428
1429 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1430 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1431 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
1432 }
1433
1434 #ifdef IXGBE_FCOE
1435 /**
1436 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1437 * @ring: structure containing ring specific data
1438 * @rx_desc: advanced rx descriptor
1439 *
1440 * Returns : true if it is FCoE pkt
1441 */
1442 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1443 union ixgbe_adv_rx_desc *rx_desc)
1444 {
1445 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1446
1447 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1448 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1449 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1450 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1451 }
1452
1453 #endif /* IXGBE_FCOE */
1454 /**
1455 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1456 * @ring: structure containing ring specific data
1457 * @rx_desc: current Rx descriptor being processed
1458 * @skb: skb currently being received and modified
1459 **/
1460 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1461 union ixgbe_adv_rx_desc *rx_desc,
1462 struct sk_buff *skb)
1463 {
1464 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1465 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1466 bool encap_pkt = false;
1467
1468 skb_checksum_none_assert(skb);
1469
1470 /* Rx csum disabled */
1471 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1472 return;
1473
1474 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1475 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1476 encap_pkt = true;
1477 skb->encapsulation = 1;
1478 }
1479
1480 /* if IP and error */
1481 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1482 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1483 ring->rx_stats.csum_err++;
1484 return;
1485 }
1486
1487 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1488 return;
1489
1490 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1491 /*
1492 * 82599 errata, UDP frames with a 0 checksum can be marked as
1493 * checksum errors.
1494 */
1495 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1496 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1497 return;
1498
1499 ring->rx_stats.csum_err++;
1500 return;
1501 }
1502
1503 /* It must be a TCP or UDP packet with a valid checksum */
1504 skb->ip_summed = CHECKSUM_UNNECESSARY;
1505 if (encap_pkt) {
1506 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1507 return;
1508
1509 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1510 skb->ip_summed = CHECKSUM_NONE;
1511 return;
1512 }
1513 /* If we checked the outer header let the stack know */
1514 skb->csum_level = 1;
1515 }
1516 }
1517
1518 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1519 struct ixgbe_rx_buffer *bi)
1520 {
1521 struct page *page = bi->page;
1522 dma_addr_t dma;
1523
1524 /* since we are recycling buffers we should seldom need to alloc */
1525 if (likely(page))
1526 return true;
1527
1528 /* alloc new page for storage */
1529 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1530 if (unlikely(!page)) {
1531 rx_ring->rx_stats.alloc_rx_page_failed++;
1532 return false;
1533 }
1534
1535 /* map page for use */
1536 dma = dma_map_page(rx_ring->dev, page, 0,
1537 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1538
1539 /*
1540 * if mapping failed free memory back to system since
1541 * there isn't much point in holding memory we can't use
1542 */
1543 if (dma_mapping_error(rx_ring->dev, dma)) {
1544 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1545
1546 rx_ring->rx_stats.alloc_rx_page_failed++;
1547 return false;
1548 }
1549
1550 bi->dma = dma;
1551 bi->page = page;
1552 bi->page_offset = 0;
1553
1554 return true;
1555 }
1556
1557 /**
1558 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1559 * @rx_ring: ring to place buffers on
1560 * @cleaned_count: number of buffers to replace
1561 **/
1562 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1563 {
1564 union ixgbe_adv_rx_desc *rx_desc;
1565 struct ixgbe_rx_buffer *bi;
1566 u16 i = rx_ring->next_to_use;
1567
1568 /* nothing to do */
1569 if (!cleaned_count)
1570 return;
1571
1572 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1573 bi = &rx_ring->rx_buffer_info[i];
1574 i -= rx_ring->count;
1575
1576 do {
1577 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1578 break;
1579
1580 /*
1581 * Refresh the desc even if buffer_addrs didn't change
1582 * because each write-back erases this info.
1583 */
1584 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1585
1586 rx_desc++;
1587 bi++;
1588 i++;
1589 if (unlikely(!i)) {
1590 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1591 bi = rx_ring->rx_buffer_info;
1592 i -= rx_ring->count;
1593 }
1594
1595 /* clear the status bits for the next_to_use descriptor */
1596 rx_desc->wb.upper.status_error = 0;
1597
1598 cleaned_count--;
1599 } while (cleaned_count);
1600
1601 i += rx_ring->count;
1602
1603 if (rx_ring->next_to_use != i) {
1604 rx_ring->next_to_use = i;
1605
1606 /* update next to alloc since we have filled the ring */
1607 rx_ring->next_to_alloc = i;
1608
1609 /* Force memory writes to complete before letting h/w
1610 * know there are new descriptors to fetch. (Only
1611 * applicable for weak-ordered memory model archs,
1612 * such as IA-64).
1613 */
1614 wmb();
1615 writel(i, rx_ring->tail);
1616 }
1617 }
1618
1619 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1620 struct sk_buff *skb)
1621 {
1622 u16 hdr_len = skb_headlen(skb);
1623
1624 /* set gso_size to avoid messing up TCP MSS */
1625 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1626 IXGBE_CB(skb)->append_cnt);
1627 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1628 }
1629
1630 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1631 struct sk_buff *skb)
1632 {
1633 /* if append_cnt is 0 then frame is not RSC */
1634 if (!IXGBE_CB(skb)->append_cnt)
1635 return;
1636
1637 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1638 rx_ring->rx_stats.rsc_flush++;
1639
1640 ixgbe_set_rsc_gso_size(rx_ring, skb);
1641
1642 /* gso_size is computed using append_cnt so always clear it last */
1643 IXGBE_CB(skb)->append_cnt = 0;
1644 }
1645
1646 /**
1647 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1648 * @rx_ring: rx descriptor ring packet is being transacted on
1649 * @rx_desc: pointer to the EOP Rx descriptor
1650 * @skb: pointer to current skb being populated
1651 *
1652 * This function checks the ring, descriptor, and packet information in
1653 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1654 * other fields within the skb.
1655 **/
1656 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1657 union ixgbe_adv_rx_desc *rx_desc,
1658 struct sk_buff *skb)
1659 {
1660 struct net_device *dev = rx_ring->netdev;
1661 u32 flags = rx_ring->q_vector->adapter->flags;
1662
1663 ixgbe_update_rsc_stats(rx_ring, skb);
1664
1665 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1666
1667 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1668
1669 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED))
1670 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1671
1672 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1673 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1674 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1675 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1676 }
1677
1678 skb_record_rx_queue(skb, rx_ring->queue_index);
1679
1680 skb->protocol = eth_type_trans(skb, dev);
1681 }
1682
1683 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1684 struct sk_buff *skb)
1685 {
1686 skb_mark_napi_id(skb, &q_vector->napi);
1687 if (ixgbe_qv_busy_polling(q_vector))
1688 netif_receive_skb(skb);
1689 else
1690 napi_gro_receive(&q_vector->napi, skb);
1691 }
1692
1693 /**
1694 * ixgbe_is_non_eop - process handling of non-EOP buffers
1695 * @rx_ring: Rx ring being processed
1696 * @rx_desc: Rx descriptor for current buffer
1697 * @skb: Current socket buffer containing buffer in progress
1698 *
1699 * This function updates next to clean. If the buffer is an EOP buffer
1700 * this function exits returning false, otherwise it will place the
1701 * sk_buff in the next buffer to be chained and return true indicating
1702 * that this is in fact a non-EOP buffer.
1703 **/
1704 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1705 union ixgbe_adv_rx_desc *rx_desc,
1706 struct sk_buff *skb)
1707 {
1708 u32 ntc = rx_ring->next_to_clean + 1;
1709
1710 /* fetch, update, and store next to clean */
1711 ntc = (ntc < rx_ring->count) ? ntc : 0;
1712 rx_ring->next_to_clean = ntc;
1713
1714 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1715
1716 /* update RSC append count if present */
1717 if (ring_is_rsc_enabled(rx_ring)) {
1718 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1719 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1720
1721 if (unlikely(rsc_enabled)) {
1722 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1723
1724 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1725 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1726
1727 /* update ntc based on RSC value */
1728 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1729 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1730 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1731 }
1732 }
1733
1734 /* if we are the last buffer then there is nothing else to do */
1735 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1736 return false;
1737
1738 /* place skb in next buffer to be received */
1739 rx_ring->rx_buffer_info[ntc].skb = skb;
1740 rx_ring->rx_stats.non_eop_descs++;
1741
1742 return true;
1743 }
1744
1745 /**
1746 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1747 * @rx_ring: rx descriptor ring packet is being transacted on
1748 * @skb: pointer to current skb being adjusted
1749 *
1750 * This function is an ixgbe specific version of __pskb_pull_tail. The
1751 * main difference between this version and the original function is that
1752 * this function can make several assumptions about the state of things
1753 * that allow for significant optimizations versus the standard function.
1754 * As a result we can do things like drop a frag and maintain an accurate
1755 * truesize for the skb.
1756 */
1757 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1758 struct sk_buff *skb)
1759 {
1760 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1761 unsigned char *va;
1762 unsigned int pull_len;
1763
1764 /*
1765 * it is valid to use page_address instead of kmap since we are
1766 * working with pages allocated out of the lomem pool per
1767 * alloc_page(GFP_ATOMIC)
1768 */
1769 va = skb_frag_address(frag);
1770
1771 /*
1772 * we need the header to contain the greater of either ETH_HLEN or
1773 * 60 bytes if the skb->len is less than 60 for skb_pad.
1774 */
1775 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
1776
1777 /* align pull length to size of long to optimize memcpy performance */
1778 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1779
1780 /* update all of the pointers */
1781 skb_frag_size_sub(frag, pull_len);
1782 frag->page_offset += pull_len;
1783 skb->data_len -= pull_len;
1784 skb->tail += pull_len;
1785 }
1786
1787 /**
1788 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1789 * @rx_ring: rx descriptor ring packet is being transacted on
1790 * @skb: pointer to current skb being updated
1791 *
1792 * This function provides a basic DMA sync up for the first fragment of an
1793 * skb. The reason for doing this is that the first fragment cannot be
1794 * unmapped until we have reached the end of packet descriptor for a buffer
1795 * chain.
1796 */
1797 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1798 struct sk_buff *skb)
1799 {
1800 /* if the page was released unmap it, else just sync our portion */
1801 if (unlikely(IXGBE_CB(skb)->page_released)) {
1802 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1803 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1804 IXGBE_CB(skb)->page_released = false;
1805 } else {
1806 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1807
1808 dma_sync_single_range_for_cpu(rx_ring->dev,
1809 IXGBE_CB(skb)->dma,
1810 frag->page_offset,
1811 ixgbe_rx_bufsz(rx_ring),
1812 DMA_FROM_DEVICE);
1813 }
1814 IXGBE_CB(skb)->dma = 0;
1815 }
1816
1817 /**
1818 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1819 * @rx_ring: rx descriptor ring packet is being transacted on
1820 * @rx_desc: pointer to the EOP Rx descriptor
1821 * @skb: pointer to current skb being fixed
1822 *
1823 * Check for corrupted packet headers caused by senders on the local L2
1824 * embedded NIC switch not setting up their Tx Descriptors right. These
1825 * should be very rare.
1826 *
1827 * Also address the case where we are pulling data in on pages only
1828 * and as such no data is present in the skb header.
1829 *
1830 * In addition if skb is not at least 60 bytes we need to pad it so that
1831 * it is large enough to qualify as a valid Ethernet frame.
1832 *
1833 * Returns true if an error was encountered and skb was freed.
1834 **/
1835 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1836 union ixgbe_adv_rx_desc *rx_desc,
1837 struct sk_buff *skb)
1838 {
1839 struct net_device *netdev = rx_ring->netdev;
1840
1841 /* verify that the packet does not have any known errors */
1842 if (unlikely(ixgbe_test_staterr(rx_desc,
1843 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1844 !(netdev->features & NETIF_F_RXALL))) {
1845 dev_kfree_skb_any(skb);
1846 return true;
1847 }
1848
1849 /* place header in linear portion of buffer */
1850 if (skb_is_nonlinear(skb))
1851 ixgbe_pull_tail(rx_ring, skb);
1852
1853 #ifdef IXGBE_FCOE
1854 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1855 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1856 return false;
1857
1858 #endif
1859 /* if eth_skb_pad returns an error the skb was freed */
1860 if (eth_skb_pad(skb))
1861 return true;
1862
1863 return false;
1864 }
1865
1866 /**
1867 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1868 * @rx_ring: rx descriptor ring to store buffers on
1869 * @old_buff: donor buffer to have page reused
1870 *
1871 * Synchronizes page for reuse by the adapter
1872 **/
1873 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1874 struct ixgbe_rx_buffer *old_buff)
1875 {
1876 struct ixgbe_rx_buffer *new_buff;
1877 u16 nta = rx_ring->next_to_alloc;
1878
1879 new_buff = &rx_ring->rx_buffer_info[nta];
1880
1881 /* update, and store next to alloc */
1882 nta++;
1883 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1884
1885 /* transfer page from old buffer to new buffer */
1886 *new_buff = *old_buff;
1887
1888 /* sync the buffer for use by the device */
1889 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1890 new_buff->page_offset,
1891 ixgbe_rx_bufsz(rx_ring),
1892 DMA_FROM_DEVICE);
1893 }
1894
1895 static inline bool ixgbe_page_is_reserved(struct page *page)
1896 {
1897 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
1898 }
1899
1900 /**
1901 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1902 * @rx_ring: rx descriptor ring to transact packets on
1903 * @rx_buffer: buffer containing page to add
1904 * @rx_desc: descriptor containing length of buffer written by hardware
1905 * @skb: sk_buff to place the data into
1906 *
1907 * This function will add the data contained in rx_buffer->page to the skb.
1908 * This is done either through a direct copy if the data in the buffer is
1909 * less than the skb header size, otherwise it will just attach the page as
1910 * a frag to the skb.
1911 *
1912 * The function will then update the page offset if necessary and return
1913 * true if the buffer can be reused by the adapter.
1914 **/
1915 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1916 struct ixgbe_rx_buffer *rx_buffer,
1917 union ixgbe_adv_rx_desc *rx_desc,
1918 struct sk_buff *skb)
1919 {
1920 struct page *page = rx_buffer->page;
1921 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1922 #if (PAGE_SIZE < 8192)
1923 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1924 #else
1925 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1926 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1927 ixgbe_rx_bufsz(rx_ring);
1928 #endif
1929
1930 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1931 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1932
1933 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1934
1935 /* page is not reserved, we can reuse buffer as-is */
1936 if (likely(!ixgbe_page_is_reserved(page)))
1937 return true;
1938
1939 /* this page cannot be reused so discard it */
1940 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1941 return false;
1942 }
1943
1944 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1945 rx_buffer->page_offset, size, truesize);
1946
1947 /* avoid re-using remote pages */
1948 if (unlikely(ixgbe_page_is_reserved(page)))
1949 return false;
1950
1951 #if (PAGE_SIZE < 8192)
1952 /* if we are only owner of page we can reuse it */
1953 if (unlikely(page_count(page) != 1))
1954 return false;
1955
1956 /* flip page offset to other buffer */
1957 rx_buffer->page_offset ^= truesize;
1958 #else
1959 /* move offset up to the next cache line */
1960 rx_buffer->page_offset += truesize;
1961
1962 if (rx_buffer->page_offset > last_offset)
1963 return false;
1964 #endif
1965
1966 /* Even if we own the page, we are not allowed to use atomic_set()
1967 * This would break get_page_unless_zero() users.
1968 */
1969 page_ref_inc(page);
1970
1971 return true;
1972 }
1973
1974 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1975 union ixgbe_adv_rx_desc *rx_desc)
1976 {
1977 struct ixgbe_rx_buffer *rx_buffer;
1978 struct sk_buff *skb;
1979 struct page *page;
1980
1981 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1982 page = rx_buffer->page;
1983 prefetchw(page);
1984
1985 skb = rx_buffer->skb;
1986
1987 if (likely(!skb)) {
1988 void *page_addr = page_address(page) +
1989 rx_buffer->page_offset;
1990
1991 /* prefetch first cache line of first page */
1992 prefetch(page_addr);
1993 #if L1_CACHE_BYTES < 128
1994 prefetch(page_addr + L1_CACHE_BYTES);
1995 #endif
1996
1997 /* allocate a skb to store the frags */
1998 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
1999 IXGBE_RX_HDR_SIZE);
2000 if (unlikely(!skb)) {
2001 rx_ring->rx_stats.alloc_rx_buff_failed++;
2002 return NULL;
2003 }
2004
2005 /*
2006 * we will be copying header into skb->data in
2007 * pskb_may_pull so it is in our interest to prefetch
2008 * it now to avoid a possible cache miss
2009 */
2010 prefetchw(skb->data);
2011
2012 /*
2013 * Delay unmapping of the first packet. It carries the
2014 * header information, HW may still access the header
2015 * after the writeback. Only unmap it when EOP is
2016 * reached
2017 */
2018 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
2019 goto dma_sync;
2020
2021 IXGBE_CB(skb)->dma = rx_buffer->dma;
2022 } else {
2023 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2024 ixgbe_dma_sync_frag(rx_ring, skb);
2025
2026 dma_sync:
2027 /* we are reusing so sync this buffer for CPU use */
2028 dma_sync_single_range_for_cpu(rx_ring->dev,
2029 rx_buffer->dma,
2030 rx_buffer->page_offset,
2031 ixgbe_rx_bufsz(rx_ring),
2032 DMA_FROM_DEVICE);
2033
2034 rx_buffer->skb = NULL;
2035 }
2036
2037 /* pull page into skb */
2038 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2039 /* hand second half of page back to the ring */
2040 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2041 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2042 /* the page has been released from the ring */
2043 IXGBE_CB(skb)->page_released = true;
2044 } else {
2045 /* we are not reusing the buffer so unmap it */
2046 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2047 ixgbe_rx_pg_size(rx_ring),
2048 DMA_FROM_DEVICE);
2049 }
2050
2051 /* clear contents of buffer_info */
2052 rx_buffer->page = NULL;
2053
2054 return skb;
2055 }
2056
2057 /**
2058 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2059 * @q_vector: structure containing interrupt and ring information
2060 * @rx_ring: rx descriptor ring to transact packets on
2061 * @budget: Total limit on number of packets to process
2062 *
2063 * This function provides a "bounce buffer" approach to Rx interrupt
2064 * processing. The advantage to this is that on systems that have
2065 * expensive overhead for IOMMU access this provides a means of avoiding
2066 * it by maintaining the mapping of the page to the syste.
2067 *
2068 * Returns amount of work completed
2069 **/
2070 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
2071 struct ixgbe_ring *rx_ring,
2072 const int budget)
2073 {
2074 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2075 #ifdef IXGBE_FCOE
2076 struct ixgbe_adapter *adapter = q_vector->adapter;
2077 int ddp_bytes;
2078 unsigned int mss = 0;
2079 #endif /* IXGBE_FCOE */
2080 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
2081
2082 while (likely(total_rx_packets < budget)) {
2083 union ixgbe_adv_rx_desc *rx_desc;
2084 struct sk_buff *skb;
2085
2086 /* return some buffers to hardware, one at a time is too slow */
2087 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2088 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2089 cleaned_count = 0;
2090 }
2091
2092 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2093
2094 if (!rx_desc->wb.upper.status_error)
2095 break;
2096
2097 /* This memory barrier is needed to keep us from reading
2098 * any other fields out of the rx_desc until we know the
2099 * descriptor has been written back
2100 */
2101 dma_rmb();
2102
2103 /* retrieve a buffer from the ring */
2104 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
2105
2106 /* exit if we failed to retrieve a buffer */
2107 if (!skb)
2108 break;
2109
2110 cleaned_count++;
2111
2112 /* place incomplete frames back on ring for completion */
2113 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2114 continue;
2115
2116 /* verify the packet layout is correct */
2117 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2118 continue;
2119
2120 /* probably a little skewed due to removing CRC */
2121 total_rx_bytes += skb->len;
2122
2123 /* populate checksum, timestamp, VLAN, and protocol */
2124 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2125
2126 #ifdef IXGBE_FCOE
2127 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2128 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2129 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2130 /* include DDPed FCoE data */
2131 if (ddp_bytes > 0) {
2132 if (!mss) {
2133 mss = rx_ring->netdev->mtu -
2134 sizeof(struct fcoe_hdr) -
2135 sizeof(struct fc_frame_header) -
2136 sizeof(struct fcoe_crc_eof);
2137 if (mss > 512)
2138 mss &= ~511;
2139 }
2140 total_rx_bytes += ddp_bytes;
2141 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2142 mss);
2143 }
2144 if (!ddp_bytes) {
2145 dev_kfree_skb_any(skb);
2146 continue;
2147 }
2148 }
2149
2150 #endif /* IXGBE_FCOE */
2151 ixgbe_rx_skb(q_vector, skb);
2152
2153 /* update budget accounting */
2154 total_rx_packets++;
2155 }
2156
2157 u64_stats_update_begin(&rx_ring->syncp);
2158 rx_ring->stats.packets += total_rx_packets;
2159 rx_ring->stats.bytes += total_rx_bytes;
2160 u64_stats_update_end(&rx_ring->syncp);
2161 q_vector->rx.total_packets += total_rx_packets;
2162 q_vector->rx.total_bytes += total_rx_bytes;
2163
2164 return total_rx_packets;
2165 }
2166
2167 #ifdef CONFIG_NET_RX_BUSY_POLL
2168 /* must be called with local_bh_disable()d */
2169 static int ixgbe_low_latency_recv(struct napi_struct *napi)
2170 {
2171 struct ixgbe_q_vector *q_vector =
2172 container_of(napi, struct ixgbe_q_vector, napi);
2173 struct ixgbe_adapter *adapter = q_vector->adapter;
2174 struct ixgbe_ring *ring;
2175 int found = 0;
2176
2177 if (test_bit(__IXGBE_DOWN, &adapter->state))
2178 return LL_FLUSH_FAILED;
2179
2180 if (!ixgbe_qv_lock_poll(q_vector))
2181 return LL_FLUSH_BUSY;
2182
2183 ixgbe_for_each_ring(ring, q_vector->rx) {
2184 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
2185 #ifdef BP_EXTENDED_STATS
2186 if (found)
2187 ring->stats.cleaned += found;
2188 else
2189 ring->stats.misses++;
2190 #endif
2191 if (found)
2192 break;
2193 }
2194
2195 ixgbe_qv_unlock_poll(q_vector);
2196
2197 return found;
2198 }
2199 #endif /* CONFIG_NET_RX_BUSY_POLL */
2200
2201 /**
2202 * ixgbe_configure_msix - Configure MSI-X hardware
2203 * @adapter: board private structure
2204 *
2205 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2206 * interrupts.
2207 **/
2208 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2209 {
2210 struct ixgbe_q_vector *q_vector;
2211 int v_idx;
2212 u32 mask;
2213
2214 /* Populate MSIX to EITR Select */
2215 if (adapter->num_vfs > 32) {
2216 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2217 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2218 }
2219
2220 /*
2221 * Populate the IVAR table and set the ITR values to the
2222 * corresponding register.
2223 */
2224 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2225 struct ixgbe_ring *ring;
2226 q_vector = adapter->q_vector[v_idx];
2227
2228 ixgbe_for_each_ring(ring, q_vector->rx)
2229 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2230
2231 ixgbe_for_each_ring(ring, q_vector->tx)
2232 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2233
2234 ixgbe_write_eitr(q_vector);
2235 }
2236
2237 switch (adapter->hw.mac.type) {
2238 case ixgbe_mac_82598EB:
2239 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2240 v_idx);
2241 break;
2242 case ixgbe_mac_82599EB:
2243 case ixgbe_mac_X540:
2244 case ixgbe_mac_X550:
2245 case ixgbe_mac_X550EM_x:
2246 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2247 break;
2248 default:
2249 break;
2250 }
2251 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2252
2253 /* set up to autoclear timer, and the vectors */
2254 mask = IXGBE_EIMS_ENABLE_MASK;
2255 mask &= ~(IXGBE_EIMS_OTHER |
2256 IXGBE_EIMS_MAILBOX |
2257 IXGBE_EIMS_LSC);
2258
2259 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2260 }
2261
2262 enum latency_range {
2263 lowest_latency = 0,
2264 low_latency = 1,
2265 bulk_latency = 2,
2266 latency_invalid = 255
2267 };
2268
2269 /**
2270 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2271 * @q_vector: structure containing interrupt and ring information
2272 * @ring_container: structure containing ring performance data
2273 *
2274 * Stores a new ITR value based on packets and byte
2275 * counts during the last interrupt. The advantage of per interrupt
2276 * computation is faster updates and more accurate ITR for the current
2277 * traffic pattern. Constants in this function were computed
2278 * based on theoretical maximum wire speed and thresholds were set based
2279 * on testing data as well as attempting to minimize response time
2280 * while increasing bulk throughput.
2281 * this functionality is controlled by the InterruptThrottleRate module
2282 * parameter (see ixgbe_param.c)
2283 **/
2284 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2285 struct ixgbe_ring_container *ring_container)
2286 {
2287 int bytes = ring_container->total_bytes;
2288 int packets = ring_container->total_packets;
2289 u32 timepassed_us;
2290 u64 bytes_perint;
2291 u8 itr_setting = ring_container->itr;
2292
2293 if (packets == 0)
2294 return;
2295
2296 /* simple throttlerate management
2297 * 0-10MB/s lowest (100000 ints/s)
2298 * 10-20MB/s low (20000 ints/s)
2299 * 20-1249MB/s bulk (12000 ints/s)
2300 */
2301 /* what was last interrupt timeslice? */
2302 timepassed_us = q_vector->itr >> 2;
2303 if (timepassed_us == 0)
2304 return;
2305
2306 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2307
2308 switch (itr_setting) {
2309 case lowest_latency:
2310 if (bytes_perint > 10)
2311 itr_setting = low_latency;
2312 break;
2313 case low_latency:
2314 if (bytes_perint > 20)
2315 itr_setting = bulk_latency;
2316 else if (bytes_perint <= 10)
2317 itr_setting = lowest_latency;
2318 break;
2319 case bulk_latency:
2320 if (bytes_perint <= 20)
2321 itr_setting = low_latency;
2322 break;
2323 }
2324
2325 /* clear work counters since we have the values we need */
2326 ring_container->total_bytes = 0;
2327 ring_container->total_packets = 0;
2328
2329 /* write updated itr to ring container */
2330 ring_container->itr = itr_setting;
2331 }
2332
2333 /**
2334 * ixgbe_write_eitr - write EITR register in hardware specific way
2335 * @q_vector: structure containing interrupt and ring information
2336 *
2337 * This function is made to be called by ethtool and by the driver
2338 * when it needs to update EITR registers at runtime. Hardware
2339 * specific quirks/differences are taken care of here.
2340 */
2341 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2342 {
2343 struct ixgbe_adapter *adapter = q_vector->adapter;
2344 struct ixgbe_hw *hw = &adapter->hw;
2345 int v_idx = q_vector->v_idx;
2346 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2347
2348 switch (adapter->hw.mac.type) {
2349 case ixgbe_mac_82598EB:
2350 /* must write high and low 16 bits to reset counter */
2351 itr_reg |= (itr_reg << 16);
2352 break;
2353 case ixgbe_mac_82599EB:
2354 case ixgbe_mac_X540:
2355 case ixgbe_mac_X550:
2356 case ixgbe_mac_X550EM_x:
2357 /*
2358 * set the WDIS bit to not clear the timer bits and cause an
2359 * immediate assertion of the interrupt
2360 */
2361 itr_reg |= IXGBE_EITR_CNT_WDIS;
2362 break;
2363 default:
2364 break;
2365 }
2366 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2367 }
2368
2369 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2370 {
2371 u32 new_itr = q_vector->itr;
2372 u8 current_itr;
2373
2374 ixgbe_update_itr(q_vector, &q_vector->tx);
2375 ixgbe_update_itr(q_vector, &q_vector->rx);
2376
2377 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2378
2379 switch (current_itr) {
2380 /* counts and packets in update_itr are dependent on these numbers */
2381 case lowest_latency:
2382 new_itr = IXGBE_100K_ITR;
2383 break;
2384 case low_latency:
2385 new_itr = IXGBE_20K_ITR;
2386 break;
2387 case bulk_latency:
2388 new_itr = IXGBE_12K_ITR;
2389 break;
2390 default:
2391 break;
2392 }
2393
2394 if (new_itr != q_vector->itr) {
2395 /* do an exponential smoothing */
2396 new_itr = (10 * new_itr * q_vector->itr) /
2397 ((9 * new_itr) + q_vector->itr);
2398
2399 /* save the algorithm value here */
2400 q_vector->itr = new_itr;
2401
2402 ixgbe_write_eitr(q_vector);
2403 }
2404 }
2405
2406 /**
2407 * ixgbe_check_overtemp_subtask - check for over temperature
2408 * @adapter: pointer to adapter
2409 **/
2410 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2411 {
2412 struct ixgbe_hw *hw = &adapter->hw;
2413 u32 eicr = adapter->interrupt_event;
2414
2415 if (test_bit(__IXGBE_DOWN, &adapter->state))
2416 return;
2417
2418 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2419 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2420 return;
2421
2422 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2423
2424 switch (hw->device_id) {
2425 case IXGBE_DEV_ID_82599_T3_LOM:
2426 /*
2427 * Since the warning interrupt is for both ports
2428 * we don't have to check if:
2429 * - This interrupt wasn't for our port.
2430 * - We may have missed the interrupt so always have to
2431 * check if we got a LSC
2432 */
2433 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
2434 !(eicr & IXGBE_EICR_LSC))
2435 return;
2436
2437 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2438 u32 speed;
2439 bool link_up = false;
2440
2441 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2442
2443 if (link_up)
2444 return;
2445 }
2446
2447 /* Check if this is not due to overtemp */
2448 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2449 return;
2450
2451 break;
2452 default:
2453 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2454 return;
2455 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
2456 return;
2457 break;
2458 }
2459 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2460
2461 adapter->interrupt_event = 0;
2462 }
2463
2464 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2465 {
2466 struct ixgbe_hw *hw = &adapter->hw;
2467
2468 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2469 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2470 e_crit(probe, "Fan has stopped, replace the adapter\n");
2471 /* write to clear the interrupt */
2472 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2473 }
2474 }
2475
2476 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2477 {
2478 struct ixgbe_hw *hw = &adapter->hw;
2479
2480 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2481 return;
2482
2483 switch (adapter->hw.mac.type) {
2484 case ixgbe_mac_82599EB:
2485 /*
2486 * Need to check link state so complete overtemp check
2487 * on service task
2488 */
2489 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2490 (eicr & IXGBE_EICR_LSC)) &&
2491 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2492 adapter->interrupt_event = eicr;
2493 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2494 ixgbe_service_event_schedule(adapter);
2495 return;
2496 }
2497 return;
2498 case ixgbe_mac_X540:
2499 if (!(eicr & IXGBE_EICR_TS))
2500 return;
2501 break;
2502 default:
2503 return;
2504 }
2505
2506 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2507 }
2508
2509 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2510 {
2511 switch (hw->mac.type) {
2512 case ixgbe_mac_82598EB:
2513 if (hw->phy.type == ixgbe_phy_nl)
2514 return true;
2515 return false;
2516 case ixgbe_mac_82599EB:
2517 case ixgbe_mac_X550EM_x:
2518 switch (hw->mac.ops.get_media_type(hw)) {
2519 case ixgbe_media_type_fiber:
2520 case ixgbe_media_type_fiber_qsfp:
2521 return true;
2522 default:
2523 return false;
2524 }
2525 default:
2526 return false;
2527 }
2528 }
2529
2530 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2531 {
2532 struct ixgbe_hw *hw = &adapter->hw;
2533 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
2534
2535 if (!ixgbe_is_sfp(hw))
2536 return;
2537
2538 /* Later MAC's use different SDP */
2539 if (hw->mac.type >= ixgbe_mac_X540)
2540 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2541
2542 if (eicr & eicr_mask) {
2543 /* Clear the interrupt */
2544 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
2545 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2546 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2547 adapter->sfp_poll_time = 0;
2548 ixgbe_service_event_schedule(adapter);
2549 }
2550 }
2551
2552 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2553 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2554 /* Clear the interrupt */
2555 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2556 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2557 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2558 ixgbe_service_event_schedule(adapter);
2559 }
2560 }
2561 }
2562
2563 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2564 {
2565 struct ixgbe_hw *hw = &adapter->hw;
2566
2567 adapter->lsc_int++;
2568 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2569 adapter->link_check_timeout = jiffies;
2570 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2571 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2572 IXGBE_WRITE_FLUSH(hw);
2573 ixgbe_service_event_schedule(adapter);
2574 }
2575 }
2576
2577 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2578 u64 qmask)
2579 {
2580 u32 mask;
2581 struct ixgbe_hw *hw = &adapter->hw;
2582
2583 switch (hw->mac.type) {
2584 case ixgbe_mac_82598EB:
2585 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2586 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2587 break;
2588 case ixgbe_mac_82599EB:
2589 case ixgbe_mac_X540:
2590 case ixgbe_mac_X550:
2591 case ixgbe_mac_X550EM_x:
2592 mask = (qmask & 0xFFFFFFFF);
2593 if (mask)
2594 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2595 mask = (qmask >> 32);
2596 if (mask)
2597 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2598 break;
2599 default:
2600 break;
2601 }
2602 /* skip the flush */
2603 }
2604
2605 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2606 u64 qmask)
2607 {
2608 u32 mask;
2609 struct ixgbe_hw *hw = &adapter->hw;
2610
2611 switch (hw->mac.type) {
2612 case ixgbe_mac_82598EB:
2613 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2614 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2615 break;
2616 case ixgbe_mac_82599EB:
2617 case ixgbe_mac_X540:
2618 case ixgbe_mac_X550:
2619 case ixgbe_mac_X550EM_x:
2620 mask = (qmask & 0xFFFFFFFF);
2621 if (mask)
2622 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2623 mask = (qmask >> 32);
2624 if (mask)
2625 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2626 break;
2627 default:
2628 break;
2629 }
2630 /* skip the flush */
2631 }
2632
2633 /**
2634 * ixgbe_irq_enable - Enable default interrupt generation settings
2635 * @adapter: board private structure
2636 **/
2637 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2638 bool flush)
2639 {
2640 struct ixgbe_hw *hw = &adapter->hw;
2641 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2642
2643 /* don't reenable LSC while waiting for link */
2644 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2645 mask &= ~IXGBE_EIMS_LSC;
2646
2647 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2648 switch (adapter->hw.mac.type) {
2649 case ixgbe_mac_82599EB:
2650 mask |= IXGBE_EIMS_GPI_SDP0(hw);
2651 break;
2652 case ixgbe_mac_X540:
2653 case ixgbe_mac_X550:
2654 case ixgbe_mac_X550EM_x:
2655 mask |= IXGBE_EIMS_TS;
2656 break;
2657 default:
2658 break;
2659 }
2660 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2661 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2662 switch (adapter->hw.mac.type) {
2663 case ixgbe_mac_82599EB:
2664 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2665 mask |= IXGBE_EIMS_GPI_SDP2(hw);
2666 /* fall through */
2667 case ixgbe_mac_X540:
2668 case ixgbe_mac_X550:
2669 case ixgbe_mac_X550EM_x:
2670 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2671 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
2672 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2673 mask |= IXGBE_EICR_GPI_SDP0_X540;
2674 mask |= IXGBE_EIMS_ECC;
2675 mask |= IXGBE_EIMS_MAILBOX;
2676 break;
2677 default:
2678 break;
2679 }
2680
2681 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2682 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2683 mask |= IXGBE_EIMS_FLOW_DIR;
2684
2685 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2686 if (queues)
2687 ixgbe_irq_enable_queues(adapter, ~0);
2688 if (flush)
2689 IXGBE_WRITE_FLUSH(&adapter->hw);
2690 }
2691
2692 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2693 {
2694 struct ixgbe_adapter *adapter = data;
2695 struct ixgbe_hw *hw = &adapter->hw;
2696 u32 eicr;
2697
2698 /*
2699 * Workaround for Silicon errata. Use clear-by-write instead
2700 * of clear-by-read. Reading with EICS will return the
2701 * interrupt causes without clearing, which later be done
2702 * with the write to EICR.
2703 */
2704 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2705
2706 /* The lower 16bits of the EICR register are for the queue interrupts
2707 * which should be masked here in order to not accidentally clear them if
2708 * the bits are high when ixgbe_msix_other is called. There is a race
2709 * condition otherwise which results in possible performance loss
2710 * especially if the ixgbe_msix_other interrupt is triggering
2711 * consistently (as it would when PPS is turned on for the X540 device)
2712 */
2713 eicr &= 0xFFFF0000;
2714
2715 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2716
2717 if (eicr & IXGBE_EICR_LSC)
2718 ixgbe_check_lsc(adapter);
2719
2720 if (eicr & IXGBE_EICR_MAILBOX)
2721 ixgbe_msg_task(adapter);
2722
2723 switch (hw->mac.type) {
2724 case ixgbe_mac_82599EB:
2725 case ixgbe_mac_X540:
2726 case ixgbe_mac_X550:
2727 case ixgbe_mac_X550EM_x:
2728 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2729 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2730 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2731 ixgbe_service_event_schedule(adapter);
2732 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2733 IXGBE_EICR_GPI_SDP0_X540);
2734 }
2735 if (eicr & IXGBE_EICR_ECC) {
2736 e_info(link, "Received ECC Err, initiating reset\n");
2737 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2738 ixgbe_service_event_schedule(adapter);
2739 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2740 }
2741 /* Handle Flow Director Full threshold interrupt */
2742 if (eicr & IXGBE_EICR_FLOW_DIR) {
2743 int reinit_count = 0;
2744 int i;
2745 for (i = 0; i < adapter->num_tx_queues; i++) {
2746 struct ixgbe_ring *ring = adapter->tx_ring[i];
2747 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2748 &ring->state))
2749 reinit_count++;
2750 }
2751 if (reinit_count) {
2752 /* no more flow director interrupts until after init */
2753 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2754 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2755 ixgbe_service_event_schedule(adapter);
2756 }
2757 }
2758 ixgbe_check_sfp_event(adapter, eicr);
2759 ixgbe_check_overtemp_event(adapter, eicr);
2760 break;
2761 default:
2762 break;
2763 }
2764
2765 ixgbe_check_fan_failure(adapter, eicr);
2766
2767 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2768 ixgbe_ptp_check_pps_event(adapter);
2769
2770 /* re-enable the original interrupt state, no lsc, no queues */
2771 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2772 ixgbe_irq_enable(adapter, false, false);
2773
2774 return IRQ_HANDLED;
2775 }
2776
2777 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2778 {
2779 struct ixgbe_q_vector *q_vector = data;
2780
2781 /* EIAM disabled interrupts (on this vector) for us */
2782
2783 if (q_vector->rx.ring || q_vector->tx.ring)
2784 napi_schedule_irqoff(&q_vector->napi);
2785
2786 return IRQ_HANDLED;
2787 }
2788
2789 /**
2790 * ixgbe_poll - NAPI Rx polling callback
2791 * @napi: structure for representing this polling device
2792 * @budget: how many packets driver is allowed to clean
2793 *
2794 * This function is used for legacy and MSI, NAPI mode
2795 **/
2796 int ixgbe_poll(struct napi_struct *napi, int budget)
2797 {
2798 struct ixgbe_q_vector *q_vector =
2799 container_of(napi, struct ixgbe_q_vector, napi);
2800 struct ixgbe_adapter *adapter = q_vector->adapter;
2801 struct ixgbe_ring *ring;
2802 int per_ring_budget, work_done = 0;
2803 bool clean_complete = true;
2804
2805 #ifdef CONFIG_IXGBE_DCA
2806 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2807 ixgbe_update_dca(q_vector);
2808 #endif
2809
2810 ixgbe_for_each_ring(ring, q_vector->tx)
2811 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring, budget);
2812
2813 /* Exit if we are called by netpoll or busy polling is active */
2814 if ((budget <= 0) || !ixgbe_qv_lock_napi(q_vector))
2815 return budget;
2816
2817 /* attempt to distribute budget to each queue fairly, but don't allow
2818 * the budget to go below 1 because we'll exit polling */
2819 if (q_vector->rx.count > 1)
2820 per_ring_budget = max(budget/q_vector->rx.count, 1);
2821 else
2822 per_ring_budget = budget;
2823
2824 ixgbe_for_each_ring(ring, q_vector->rx) {
2825 int cleaned = ixgbe_clean_rx_irq(q_vector, ring,
2826 per_ring_budget);
2827
2828 work_done += cleaned;
2829 clean_complete &= (cleaned < per_ring_budget);
2830 }
2831
2832 ixgbe_qv_unlock_napi(q_vector);
2833 /* If all work not completed, return budget and keep polling */
2834 if (!clean_complete)
2835 return budget;
2836
2837 /* all work done, exit the polling mode */
2838 napi_complete_done(napi, work_done);
2839 if (adapter->rx_itr_setting & 1)
2840 ixgbe_set_itr(q_vector);
2841 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2842 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2843
2844 return 0;
2845 }
2846
2847 /**
2848 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2849 * @adapter: board private structure
2850 *
2851 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2852 * interrupts from the kernel.
2853 **/
2854 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2855 {
2856 struct net_device *netdev = adapter->netdev;
2857 int vector, err;
2858 int ri = 0, ti = 0;
2859
2860 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2861 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2862 struct msix_entry *entry = &adapter->msix_entries[vector];
2863
2864 if (q_vector->tx.ring && q_vector->rx.ring) {
2865 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2866 "%s-%s-%d", netdev->name, "TxRx", ri++);
2867 ti++;
2868 } else if (q_vector->rx.ring) {
2869 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2870 "%s-%s-%d", netdev->name, "rx", ri++);
2871 } else if (q_vector->tx.ring) {
2872 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2873 "%s-%s-%d", netdev->name, "tx", ti++);
2874 } else {
2875 /* skip this unused q_vector */
2876 continue;
2877 }
2878 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2879 q_vector->name, q_vector);
2880 if (err) {
2881 e_err(probe, "request_irq failed for MSIX interrupt "
2882 "Error: %d\n", err);
2883 goto free_queue_irqs;
2884 }
2885 /* If Flow Director is enabled, set interrupt affinity */
2886 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2887 /* assign the mask for this irq */
2888 irq_set_affinity_hint(entry->vector,
2889 &q_vector->affinity_mask);
2890 }
2891 }
2892
2893 err = request_irq(adapter->msix_entries[vector].vector,
2894 ixgbe_msix_other, 0, netdev->name, adapter);
2895 if (err) {
2896 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2897 goto free_queue_irqs;
2898 }
2899
2900 return 0;
2901
2902 free_queue_irqs:
2903 while (vector) {
2904 vector--;
2905 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2906 NULL);
2907 free_irq(adapter->msix_entries[vector].vector,
2908 adapter->q_vector[vector]);
2909 }
2910 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2911 pci_disable_msix(adapter->pdev);
2912 kfree(adapter->msix_entries);
2913 adapter->msix_entries = NULL;
2914 return err;
2915 }
2916
2917 /**
2918 * ixgbe_intr - legacy mode Interrupt Handler
2919 * @irq: interrupt number
2920 * @data: pointer to a network interface device structure
2921 **/
2922 static irqreturn_t ixgbe_intr(int irq, void *data)
2923 {
2924 struct ixgbe_adapter *adapter = data;
2925 struct ixgbe_hw *hw = &adapter->hw;
2926 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2927 u32 eicr;
2928
2929 /*
2930 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2931 * before the read of EICR.
2932 */
2933 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2934
2935 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2936 * therefore no explicit interrupt disable is necessary */
2937 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2938 if (!eicr) {
2939 /*
2940 * shared interrupt alert!
2941 * make sure interrupts are enabled because the read will
2942 * have disabled interrupts due to EIAM
2943 * finish the workaround of silicon errata on 82598. Unmask
2944 * the interrupt that we masked before the EICR read.
2945 */
2946 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2947 ixgbe_irq_enable(adapter, true, true);
2948 return IRQ_NONE; /* Not our interrupt */
2949 }
2950
2951 if (eicr & IXGBE_EICR_LSC)
2952 ixgbe_check_lsc(adapter);
2953
2954 switch (hw->mac.type) {
2955 case ixgbe_mac_82599EB:
2956 ixgbe_check_sfp_event(adapter, eicr);
2957 /* Fall through */
2958 case ixgbe_mac_X540:
2959 case ixgbe_mac_X550:
2960 case ixgbe_mac_X550EM_x:
2961 if (eicr & IXGBE_EICR_ECC) {
2962 e_info(link, "Received ECC Err, initiating reset\n");
2963 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2964 ixgbe_service_event_schedule(adapter);
2965 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2966 }
2967 ixgbe_check_overtemp_event(adapter, eicr);
2968 break;
2969 default:
2970 break;
2971 }
2972
2973 ixgbe_check_fan_failure(adapter, eicr);
2974 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2975 ixgbe_ptp_check_pps_event(adapter);
2976
2977 /* would disable interrupts here but EIAM disabled it */
2978 napi_schedule_irqoff(&q_vector->napi);
2979
2980 /*
2981 * re-enable link(maybe) and non-queue interrupts, no flush.
2982 * ixgbe_poll will re-enable the queue interrupts
2983 */
2984 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2985 ixgbe_irq_enable(adapter, false, false);
2986
2987 return IRQ_HANDLED;
2988 }
2989
2990 /**
2991 * ixgbe_request_irq - initialize interrupts
2992 * @adapter: board private structure
2993 *
2994 * Attempts to configure interrupts using the best available
2995 * capabilities of the hardware and kernel.
2996 **/
2997 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2998 {
2999 struct net_device *netdev = adapter->netdev;
3000 int err;
3001
3002 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3003 err = ixgbe_request_msix_irqs(adapter);
3004 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
3005 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
3006 netdev->name, adapter);
3007 else
3008 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
3009 netdev->name, adapter);
3010
3011 if (err)
3012 e_err(probe, "request_irq failed, Error %d\n", err);
3013
3014 return err;
3015 }
3016
3017 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
3018 {
3019 int vector;
3020
3021 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3022 free_irq(adapter->pdev->irq, adapter);
3023 return;
3024 }
3025
3026 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3027 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3028 struct msix_entry *entry = &adapter->msix_entries[vector];
3029
3030 /* free only the irqs that were actually requested */
3031 if (!q_vector->rx.ring && !q_vector->tx.ring)
3032 continue;
3033
3034 /* clear the affinity_mask in the IRQ descriptor */
3035 irq_set_affinity_hint(entry->vector, NULL);
3036
3037 free_irq(entry->vector, q_vector);
3038 }
3039
3040 free_irq(adapter->msix_entries[vector++].vector, adapter);
3041 }
3042
3043 /**
3044 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3045 * @adapter: board private structure
3046 **/
3047 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3048 {
3049 switch (adapter->hw.mac.type) {
3050 case ixgbe_mac_82598EB:
3051 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
3052 break;
3053 case ixgbe_mac_82599EB:
3054 case ixgbe_mac_X540:
3055 case ixgbe_mac_X550:
3056 case ixgbe_mac_X550EM_x:
3057 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3058 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
3059 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
3060 break;
3061 default:
3062 break;
3063 }
3064 IXGBE_WRITE_FLUSH(&adapter->hw);
3065 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3066 int vector;
3067
3068 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3069 synchronize_irq(adapter->msix_entries[vector].vector);
3070
3071 synchronize_irq(adapter->msix_entries[vector++].vector);
3072 } else {
3073 synchronize_irq(adapter->pdev->irq);
3074 }
3075 }
3076
3077 /**
3078 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3079 *
3080 **/
3081 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3082 {
3083 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3084
3085 ixgbe_write_eitr(q_vector);
3086
3087 ixgbe_set_ivar(adapter, 0, 0, 0);
3088 ixgbe_set_ivar(adapter, 1, 0, 0);
3089
3090 e_info(hw, "Legacy interrupt IVAR setup done\n");
3091 }
3092
3093 /**
3094 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3095 * @adapter: board private structure
3096 * @ring: structure containing ring specific data
3097 *
3098 * Configure the Tx descriptor ring after a reset.
3099 **/
3100 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3101 struct ixgbe_ring *ring)
3102 {
3103 struct ixgbe_hw *hw = &adapter->hw;
3104 u64 tdba = ring->dma;
3105 int wait_loop = 10;
3106 u32 txdctl = IXGBE_TXDCTL_ENABLE;
3107 u8 reg_idx = ring->reg_idx;
3108
3109 /* disable queue to avoid issues while updating state */
3110 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
3111 IXGBE_WRITE_FLUSH(hw);
3112
3113 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
3114 (tdba & DMA_BIT_MASK(32)));
3115 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3116 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3117 ring->count * sizeof(union ixgbe_adv_tx_desc));
3118 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3119 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
3120 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
3121
3122 /*
3123 * set WTHRESH to encourage burst writeback, it should not be set
3124 * higher than 1 when:
3125 * - ITR is 0 as it could cause false TX hangs
3126 * - ITR is set to > 100k int/sec and BQL is enabled
3127 *
3128 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3129 * to or less than the number of on chip descriptors, which is
3130 * currently 40.
3131 */
3132 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3133 txdctl |= (1 << 16); /* WTHRESH = 1 */
3134 else
3135 txdctl |= (8 << 16); /* WTHRESH = 8 */
3136
3137 /*
3138 * Setting PTHRESH to 32 both improves performance
3139 * and avoids a TX hang with DFP enabled
3140 */
3141 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3142 32; /* PTHRESH = 32 */
3143
3144 /* reinitialize flowdirector state */
3145 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3146 ring->atr_sample_rate = adapter->atr_sample_rate;
3147 ring->atr_count = 0;
3148 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3149 } else {
3150 ring->atr_sample_rate = 0;
3151 }
3152
3153 /* initialize XPS */
3154 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3155 struct ixgbe_q_vector *q_vector = ring->q_vector;
3156
3157 if (q_vector)
3158 netif_set_xps_queue(ring->netdev,
3159 &q_vector->affinity_mask,
3160 ring->queue_index);
3161 }
3162
3163 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3164
3165 /* enable queue */
3166 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3167
3168 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3169 if (hw->mac.type == ixgbe_mac_82598EB &&
3170 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3171 return;
3172
3173 /* poll to verify queue is enabled */
3174 do {
3175 usleep_range(1000, 2000);
3176 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3177 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3178 if (!wait_loop)
3179 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
3180 }
3181
3182 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3183 {
3184 struct ixgbe_hw *hw = &adapter->hw;
3185 u32 rttdcs, mtqc;
3186 u8 tcs = netdev_get_num_tc(adapter->netdev);
3187
3188 if (hw->mac.type == ixgbe_mac_82598EB)
3189 return;
3190
3191 /* disable the arbiter while setting MTQC */
3192 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3193 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3194 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3195
3196 /* set transmit pool layout */
3197 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3198 mtqc = IXGBE_MTQC_VT_ENA;
3199 if (tcs > 4)
3200 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3201 else if (tcs > 1)
3202 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3203 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3204 mtqc |= IXGBE_MTQC_32VF;
3205 else
3206 mtqc |= IXGBE_MTQC_64VF;
3207 } else {
3208 if (tcs > 4)
3209 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3210 else if (tcs > 1)
3211 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3212 else
3213 mtqc = IXGBE_MTQC_64Q_1PB;
3214 }
3215
3216 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3217
3218 /* Enable Security TX Buffer IFG for multiple pb */
3219 if (tcs) {
3220 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3221 sectx |= IXGBE_SECTX_DCB;
3222 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3223 }
3224
3225 /* re-enable the arbiter */
3226 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3227 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3228 }
3229
3230 /**
3231 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3232 * @adapter: board private structure
3233 *
3234 * Configure the Tx unit of the MAC after a reset.
3235 **/
3236 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3237 {
3238 struct ixgbe_hw *hw = &adapter->hw;
3239 u32 dmatxctl;
3240 u32 i;
3241
3242 ixgbe_setup_mtqc(adapter);
3243
3244 if (hw->mac.type != ixgbe_mac_82598EB) {
3245 /* DMATXCTL.EN must be before Tx queues are enabled */
3246 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3247 dmatxctl |= IXGBE_DMATXCTL_TE;
3248 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3249 }
3250
3251 /* Setup the HW Tx Head and Tail descriptor pointers */
3252 for (i = 0; i < adapter->num_tx_queues; i++)
3253 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3254 }
3255
3256 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3257 struct ixgbe_ring *ring)
3258 {
3259 struct ixgbe_hw *hw = &adapter->hw;
3260 u8 reg_idx = ring->reg_idx;
3261 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3262
3263 srrctl |= IXGBE_SRRCTL_DROP_EN;
3264
3265 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3266 }
3267
3268 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3269 struct ixgbe_ring *ring)
3270 {
3271 struct ixgbe_hw *hw = &adapter->hw;
3272 u8 reg_idx = ring->reg_idx;
3273 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3274
3275 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3276
3277 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3278 }
3279
3280 #ifdef CONFIG_IXGBE_DCB
3281 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3282 #else
3283 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3284 #endif
3285 {
3286 int i;
3287 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3288
3289 if (adapter->ixgbe_ieee_pfc)
3290 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3291
3292 /*
3293 * We should set the drop enable bit if:
3294 * SR-IOV is enabled
3295 * or
3296 * Number of Rx queues > 1 and flow control is disabled
3297 *
3298 * This allows us to avoid head of line blocking for security
3299 * and performance reasons.
3300 */
3301 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3302 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3303 for (i = 0; i < adapter->num_rx_queues; i++)
3304 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3305 } else {
3306 for (i = 0; i < adapter->num_rx_queues; i++)
3307 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3308 }
3309 }
3310
3311 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3312
3313 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3314 struct ixgbe_ring *rx_ring)
3315 {
3316 struct ixgbe_hw *hw = &adapter->hw;
3317 u32 srrctl;
3318 u8 reg_idx = rx_ring->reg_idx;
3319
3320 if (hw->mac.type == ixgbe_mac_82598EB) {
3321 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3322
3323 /*
3324 * if VMDq is not active we must program one srrctl register
3325 * per RSS queue since we have enabled RDRXCTL.MVMEN
3326 */
3327 reg_idx &= mask;
3328 }
3329
3330 /* configure header buffer length, needed for RSC */
3331 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3332
3333 /* configure the packet buffer length */
3334 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3335
3336 /* configure descriptor type */
3337 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3338
3339 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3340 }
3341
3342 /**
3343 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
3344 * @adapter: device handle
3345 *
3346 * - 82598/82599/X540: 128
3347 * - X550(non-SRIOV mode): 512
3348 * - X550(SRIOV mode): 64
3349 */
3350 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
3351 {
3352 if (adapter->hw.mac.type < ixgbe_mac_X550)
3353 return 128;
3354 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3355 return 64;
3356 else
3357 return 512;
3358 }
3359
3360 /**
3361 * ixgbe_store_reta - Write the RETA table to HW
3362 * @adapter: device handle
3363 *
3364 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3365 */
3366 void ixgbe_store_reta(struct ixgbe_adapter *adapter)
3367 {
3368 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3369 struct ixgbe_hw *hw = &adapter->hw;
3370 u32 reta = 0;
3371 u32 indices_multi;
3372 u8 *indir_tbl = adapter->rss_indir_tbl;
3373
3374 /* Fill out the redirection table as follows:
3375 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3376 * indices.
3377 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3378 * - X550: 8 bit wide entries containing 6 bit RSS index
3379 */
3380 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3381 indices_multi = 0x11;
3382 else
3383 indices_multi = 0x1;
3384
3385 /* Write redirection table to HW */
3386 for (i = 0; i < reta_entries; i++) {
3387 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
3388 if ((i & 3) == 3) {
3389 if (i < 128)
3390 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3391 else
3392 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3393 reta);
3394 reta = 0;
3395 }
3396 }
3397 }
3398
3399 /**
3400 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
3401 * @adapter: device handle
3402 *
3403 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3404 */
3405 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
3406 {
3407 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3408 struct ixgbe_hw *hw = &adapter->hw;
3409 u32 vfreta = 0;
3410 unsigned int pf_pool = adapter->num_vfs;
3411
3412 /* Write redirection table to HW */
3413 for (i = 0; i < reta_entries; i++) {
3414 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3415 if ((i & 3) == 3) {
3416 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3417 vfreta);
3418 vfreta = 0;
3419 }
3420 }
3421 }
3422
3423 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3424 {
3425 struct ixgbe_hw *hw = &adapter->hw;
3426 u32 i, j;
3427 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3428 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3429
3430 /* Program table for at least 2 queues w/ SR-IOV so that VFs can
3431 * make full use of any rings they may have. We will use the
3432 * PSRTYPE register to control how many rings we use within the PF.
3433 */
3434 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3435 rss_i = 2;
3436
3437 /* Fill out hash function seeds */
3438 for (i = 0; i < 10; i++)
3439 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3440
3441 /* Fill out redirection table */
3442 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3443
3444 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3445 if (j == rss_i)
3446 j = 0;
3447
3448 adapter->rss_indir_tbl[i] = j;
3449 }
3450
3451 ixgbe_store_reta(adapter);
3452 }
3453
3454 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3455 {
3456 struct ixgbe_hw *hw = &adapter->hw;
3457 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3458 unsigned int pf_pool = adapter->num_vfs;
3459 int i, j;
3460
3461 /* Fill out hash function seeds */
3462 for (i = 0; i < 10; i++)
3463 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3464 adapter->rss_key[i]);
3465
3466 /* Fill out the redirection table */
3467 for (i = 0, j = 0; i < 64; i++, j++) {
3468 if (j == rss_i)
3469 j = 0;
3470
3471 adapter->rss_indir_tbl[i] = j;
3472 }
3473
3474 ixgbe_store_vfreta(adapter);
3475 }
3476
3477 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3478 {
3479 struct ixgbe_hw *hw = &adapter->hw;
3480 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
3481 u32 rxcsum;
3482
3483 /* Disable indicating checksum in descriptor, enables RSS hash */
3484 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3485 rxcsum |= IXGBE_RXCSUM_PCSD;
3486 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3487
3488 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3489 if (adapter->ring_feature[RING_F_RSS].mask)
3490 mrqc = IXGBE_MRQC_RSSEN;
3491 } else {
3492 u8 tcs = netdev_get_num_tc(adapter->netdev);
3493
3494 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3495 if (tcs > 4)
3496 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3497 else if (tcs > 1)
3498 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3499 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3500 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3501 else
3502 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3503 } else {
3504 if (tcs > 4)
3505 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3506 else if (tcs > 1)
3507 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3508 else
3509 mrqc = IXGBE_MRQC_RSSEN;
3510 }
3511 }
3512
3513 /* Perform hash on these packet types */
3514 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3515 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3516 IXGBE_MRQC_RSS_FIELD_IPV6 |
3517 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3518
3519 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3520 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3521 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3522 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3523
3524 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
3525 if ((hw->mac.type >= ixgbe_mac_X550) &&
3526 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3527 unsigned int pf_pool = adapter->num_vfs;
3528
3529 /* Enable VF RSS mode */
3530 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3531 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3532
3533 /* Setup RSS through the VF registers */
3534 ixgbe_setup_vfreta(adapter);
3535 vfmrqc = IXGBE_MRQC_RSSEN;
3536 vfmrqc |= rss_field;
3537 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3538 } else {
3539 ixgbe_setup_reta(adapter);
3540 mrqc |= rss_field;
3541 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3542 }
3543 }
3544
3545 /**
3546 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3547 * @adapter: address of board private structure
3548 * @index: index of ring to set
3549 **/
3550 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3551 struct ixgbe_ring *ring)
3552 {
3553 struct ixgbe_hw *hw = &adapter->hw;
3554 u32 rscctrl;
3555 u8 reg_idx = ring->reg_idx;
3556
3557 if (!ring_is_rsc_enabled(ring))
3558 return;
3559
3560 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3561 rscctrl |= IXGBE_RSCCTL_RSCEN;
3562 /*
3563 * we must limit the number of descriptors so that the
3564 * total size of max desc * buf_len is not greater
3565 * than 65536
3566 */
3567 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3568 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3569 }
3570
3571 #define IXGBE_MAX_RX_DESC_POLL 10
3572 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3573 struct ixgbe_ring *ring)
3574 {
3575 struct ixgbe_hw *hw = &adapter->hw;
3576 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3577 u32 rxdctl;
3578 u8 reg_idx = ring->reg_idx;
3579
3580 if (ixgbe_removed(hw->hw_addr))
3581 return;
3582 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3583 if (hw->mac.type == ixgbe_mac_82598EB &&
3584 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3585 return;
3586
3587 do {
3588 usleep_range(1000, 2000);
3589 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3590 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3591
3592 if (!wait_loop) {
3593 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3594 "the polling period\n", reg_idx);
3595 }
3596 }
3597
3598 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3599 struct ixgbe_ring *ring)
3600 {
3601 struct ixgbe_hw *hw = &adapter->hw;
3602 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3603 u32 rxdctl;
3604 u8 reg_idx = ring->reg_idx;
3605
3606 if (ixgbe_removed(hw->hw_addr))
3607 return;
3608 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3609 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3610
3611 /* write value back with RXDCTL.ENABLE bit cleared */
3612 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3613
3614 if (hw->mac.type == ixgbe_mac_82598EB &&
3615 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3616 return;
3617
3618 /* the hardware may take up to 100us to really disable the rx queue */
3619 do {
3620 udelay(10);
3621 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3622 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3623
3624 if (!wait_loop) {
3625 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3626 "the polling period\n", reg_idx);
3627 }
3628 }
3629
3630 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3631 struct ixgbe_ring *ring)
3632 {
3633 struct ixgbe_hw *hw = &adapter->hw;
3634 u64 rdba = ring->dma;
3635 u32 rxdctl;
3636 u8 reg_idx = ring->reg_idx;
3637
3638 /* disable queue to avoid issues while updating state */
3639 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3640 ixgbe_disable_rx_queue(adapter, ring);
3641
3642 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3643 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3644 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3645 ring->count * sizeof(union ixgbe_adv_rx_desc));
3646 /* Force flushing of IXGBE_RDLEN to prevent MDD */
3647 IXGBE_WRITE_FLUSH(hw);
3648
3649 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3650 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3651 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
3652
3653 ixgbe_configure_srrctl(adapter, ring);
3654 ixgbe_configure_rscctl(adapter, ring);
3655
3656 if (hw->mac.type == ixgbe_mac_82598EB) {
3657 /*
3658 * enable cache line friendly hardware writes:
3659 * PTHRESH=32 descriptors (half the internal cache),
3660 * this also removes ugly rx_no_buffer_count increment
3661 * HTHRESH=4 descriptors (to minimize latency on fetch)
3662 * WTHRESH=8 burst writeback up to two cache lines
3663 */
3664 rxdctl &= ~0x3FFFFF;
3665 rxdctl |= 0x080420;
3666 }
3667
3668 /* enable receive descriptor ring */
3669 rxdctl |= IXGBE_RXDCTL_ENABLE;
3670 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3671
3672 ixgbe_rx_desc_queue_enable(adapter, ring);
3673 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3674 }
3675
3676 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3677 {
3678 struct ixgbe_hw *hw = &adapter->hw;
3679 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3680 u16 pool;
3681
3682 /* PSRTYPE must be initialized in non 82598 adapters */
3683 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3684 IXGBE_PSRTYPE_UDPHDR |
3685 IXGBE_PSRTYPE_IPV4HDR |
3686 IXGBE_PSRTYPE_L2HDR |
3687 IXGBE_PSRTYPE_IPV6HDR;
3688
3689 if (hw->mac.type == ixgbe_mac_82598EB)
3690 return;
3691
3692 if (rss_i > 3)
3693 psrtype |= 2 << 29;
3694 else if (rss_i > 1)
3695 psrtype |= 1 << 29;
3696
3697 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3698 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
3699 }
3700
3701 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3702 {
3703 struct ixgbe_hw *hw = &adapter->hw;
3704 u32 reg_offset, vf_shift;
3705 u32 gcr_ext, vmdctl;
3706 int i;
3707
3708 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3709 return;
3710
3711 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3712 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3713 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3714 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3715 vmdctl |= IXGBE_VT_CTL_REPLEN;
3716 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3717
3718 vf_shift = VMDQ_P(0) % 32;
3719 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3720
3721 /* Enable only the PF's pool for Tx/Rx */
3722 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3723 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3724 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3725 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3726 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
3727 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3728
3729 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3730 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3731
3732 /* clear VLAN promisc flag so VFTA will be updated if necessary */
3733 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
3734
3735 /*
3736 * Set up VF register offsets for selected VT Mode,
3737 * i.e. 32 or 64 VFs for SR-IOV
3738 */
3739 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3740 case IXGBE_82599_VMDQ_8Q_MASK:
3741 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3742 break;
3743 case IXGBE_82599_VMDQ_4Q_MASK:
3744 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3745 break;
3746 default:
3747 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3748 break;
3749 }
3750
3751 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3752
3753
3754 /* Enable MAC Anti-Spoofing */
3755 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3756 adapter->num_vfs);
3757
3758 /* Ensure LLDP and FC is set for Ethertype Antispoofing if we will be
3759 * calling set_ethertype_anti_spoofing for each VF in loop below
3760 */
3761 if (hw->mac.ops.set_ethertype_anti_spoofing) {
3762 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
3763 (IXGBE_ETQF_FILTER_EN |
3764 IXGBE_ETQF_TX_ANTISPOOF |
3765 IXGBE_ETH_P_LLDP));
3766
3767 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FC),
3768 (IXGBE_ETQF_FILTER_EN |
3769 IXGBE_ETQF_TX_ANTISPOOF |
3770 ETH_P_PAUSE));
3771 }
3772
3773 /* For VFs that have spoof checking turned off */
3774 for (i = 0; i < adapter->num_vfs; i++) {
3775 if (!adapter->vfinfo[i].spoofchk_enabled)
3776 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3777
3778 /* enable ethertype anti spoofing if hw supports it */
3779 if (hw->mac.ops.set_ethertype_anti_spoofing)
3780 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
3781
3782 /* Enable/Disable RSS query feature */
3783 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
3784 adapter->vfinfo[i].rss_query_enabled);
3785 }
3786 }
3787
3788 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3789 {
3790 struct ixgbe_hw *hw = &adapter->hw;
3791 struct net_device *netdev = adapter->netdev;
3792 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3793 struct ixgbe_ring *rx_ring;
3794 int i;
3795 u32 mhadd, hlreg0;
3796
3797 #ifdef IXGBE_FCOE
3798 /* adjust max frame to be able to do baby jumbo for FCoE */
3799 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3800 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3801 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3802
3803 #endif /* IXGBE_FCOE */
3804
3805 /* adjust max frame to be at least the size of a standard frame */
3806 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3807 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3808
3809 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3810 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3811 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3812 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3813
3814 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3815 }
3816
3817 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3818 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3819 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3820 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3821
3822 /*
3823 * Setup the HW Rx Head and Tail Descriptor Pointers and
3824 * the Base and Length of the Rx Descriptor Ring
3825 */
3826 for (i = 0; i < adapter->num_rx_queues; i++) {
3827 rx_ring = adapter->rx_ring[i];
3828 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3829 set_ring_rsc_enabled(rx_ring);
3830 else
3831 clear_ring_rsc_enabled(rx_ring);
3832 }
3833 }
3834
3835 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3836 {
3837 struct ixgbe_hw *hw = &adapter->hw;
3838 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3839
3840 switch (hw->mac.type) {
3841 case ixgbe_mac_82598EB:
3842 /*
3843 * For VMDq support of different descriptor types or
3844 * buffer sizes through the use of multiple SRRCTL
3845 * registers, RDRXCTL.MVMEN must be set to 1
3846 *
3847 * also, the manual doesn't mention it clearly but DCA hints
3848 * will only use queue 0's tags unless this bit is set. Side
3849 * effects of setting this bit are only that SRRCTL must be
3850 * fully programmed [0..15]
3851 */
3852 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3853 break;
3854 case ixgbe_mac_X550:
3855 case ixgbe_mac_X550EM_x:
3856 if (adapter->num_vfs)
3857 rdrxctl |= IXGBE_RDRXCTL_PSP;
3858 /* fall through for older HW */
3859 case ixgbe_mac_82599EB:
3860 case ixgbe_mac_X540:
3861 /* Disable RSC for ACK packets */
3862 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3863 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3864 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3865 /* hardware requires some bits to be set by default */
3866 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3867 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3868 break;
3869 default:
3870 /* We should do nothing since we don't know this hardware */
3871 return;
3872 }
3873
3874 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3875 }
3876
3877 /**
3878 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3879 * @adapter: board private structure
3880 *
3881 * Configure the Rx unit of the MAC after a reset.
3882 **/
3883 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3884 {
3885 struct ixgbe_hw *hw = &adapter->hw;
3886 int i;
3887 u32 rxctrl, rfctl;
3888
3889 /* disable receives while setting up the descriptors */
3890 hw->mac.ops.disable_rx(hw);
3891
3892 ixgbe_setup_psrtype(adapter);
3893 ixgbe_setup_rdrxctl(adapter);
3894
3895 /* RSC Setup */
3896 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3897 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3898 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3899 rfctl |= IXGBE_RFCTL_RSC_DIS;
3900 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3901
3902 /* Program registers for the distribution of queues */
3903 ixgbe_setup_mrqc(adapter);
3904
3905 /* set_rx_buffer_len must be called before ring initialization */
3906 ixgbe_set_rx_buffer_len(adapter);
3907
3908 /*
3909 * Setup the HW Rx Head and Tail Descriptor Pointers and
3910 * the Base and Length of the Rx Descriptor Ring
3911 */
3912 for (i = 0; i < adapter->num_rx_queues; i++)
3913 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3914
3915 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3916 /* disable drop enable for 82598 parts */
3917 if (hw->mac.type == ixgbe_mac_82598EB)
3918 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3919
3920 /* enable all receives */
3921 rxctrl |= IXGBE_RXCTRL_RXEN;
3922 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3923 }
3924
3925 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3926 __be16 proto, u16 vid)
3927 {
3928 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3929 struct ixgbe_hw *hw = &adapter->hw;
3930
3931 /* add VID to filter table */
3932 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
3933 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid);
3934
3935 set_bit(vid, adapter->active_vlans);
3936
3937 return 0;
3938 }
3939
3940 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan)
3941 {
3942 u32 vlvf;
3943 int idx;
3944
3945 /* short cut the special case */
3946 if (vlan == 0)
3947 return 0;
3948
3949 /* Search for the vlan id in the VLVF entries */
3950 for (idx = IXGBE_VLVF_ENTRIES; --idx;) {
3951 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx));
3952 if ((vlvf & VLAN_VID_MASK) == vlan)
3953 break;
3954 }
3955
3956 return idx;
3957 }
3958
3959 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid)
3960 {
3961 struct ixgbe_hw *hw = &adapter->hw;
3962 u32 bits, word;
3963 int idx;
3964
3965 idx = ixgbe_find_vlvf_entry(hw, vid);
3966 if (!idx)
3967 return;
3968
3969 /* See if any other pools are set for this VLAN filter
3970 * entry other than the PF.
3971 */
3972 word = idx * 2 + (VMDQ_P(0) / 32);
3973 bits = ~(1 << (VMDQ_P(0)) % 32);
3974 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
3975
3976 /* Disable the filter so this falls into the default pool. */
3977 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) {
3978 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
3979 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0);
3980 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0);
3981 }
3982 }
3983
3984 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3985 __be16 proto, u16 vid)
3986 {
3987 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3988 struct ixgbe_hw *hw = &adapter->hw;
3989
3990 /* remove VID from filter table */
3991 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
3992 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true);
3993
3994 clear_bit(vid, adapter->active_vlans);
3995
3996 return 0;
3997 }
3998
3999 /**
4000 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
4001 * @adapter: driver data
4002 */
4003 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
4004 {
4005 struct ixgbe_hw *hw = &adapter->hw;
4006 u32 vlnctrl;
4007 int i, j;
4008
4009 switch (hw->mac.type) {
4010 case ixgbe_mac_82598EB:
4011 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4012 vlnctrl &= ~IXGBE_VLNCTRL_VME;
4013 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4014 break;
4015 case ixgbe_mac_82599EB:
4016 case ixgbe_mac_X540:
4017 case ixgbe_mac_X550:
4018 case ixgbe_mac_X550EM_x:
4019 for (i = 0; i < adapter->num_rx_queues; i++) {
4020 struct ixgbe_ring *ring = adapter->rx_ring[i];
4021
4022 if (ring->l2_accel_priv)
4023 continue;
4024 j = ring->reg_idx;
4025 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4026 vlnctrl &= ~IXGBE_RXDCTL_VME;
4027 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4028 }
4029 break;
4030 default:
4031 break;
4032 }
4033 }
4034
4035 /**
4036 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
4037 * @adapter: driver data
4038 */
4039 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
4040 {
4041 struct ixgbe_hw *hw = &adapter->hw;
4042 u32 vlnctrl;
4043 int i, j;
4044
4045 switch (hw->mac.type) {
4046 case ixgbe_mac_82598EB:
4047 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4048 vlnctrl |= IXGBE_VLNCTRL_VME;
4049 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4050 break;
4051 case ixgbe_mac_82599EB:
4052 case ixgbe_mac_X540:
4053 case ixgbe_mac_X550:
4054 case ixgbe_mac_X550EM_x:
4055 for (i = 0; i < adapter->num_rx_queues; i++) {
4056 struct ixgbe_ring *ring = adapter->rx_ring[i];
4057
4058 if (ring->l2_accel_priv)
4059 continue;
4060 j = ring->reg_idx;
4061 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4062 vlnctrl |= IXGBE_RXDCTL_VME;
4063 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4064 }
4065 break;
4066 default:
4067 break;
4068 }
4069 }
4070
4071 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter)
4072 {
4073 struct ixgbe_hw *hw = &adapter->hw;
4074 u32 vlnctrl, i;
4075
4076 switch (hw->mac.type) {
4077 case ixgbe_mac_82599EB:
4078 case ixgbe_mac_X540:
4079 case ixgbe_mac_X550:
4080 case ixgbe_mac_X550EM_x:
4081 default:
4082 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)
4083 break;
4084 /* fall through */
4085 case ixgbe_mac_82598EB:
4086 /* legacy case, we can just disable VLAN filtering */
4087 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4088 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4089 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4090 return;
4091 }
4092
4093 /* We are already in VLAN promisc, nothing to do */
4094 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
4095 return;
4096
4097 /* Set flag so we don't redo unnecessary work */
4098 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC;
4099
4100 /* Add PF to all active pools */
4101 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4102 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);
4103 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);
4104
4105 vlvfb |= 1 << (VMDQ_P(0) % 32);
4106 IXGBE_WRITE_REG(hw, reg_offset, vlvfb);
4107 }
4108
4109 /* Set all bits in the VLAN filter table array */
4110 for (i = hw->mac.vft_size; i--;)
4111 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U);
4112 }
4113
4114 #define VFTA_BLOCK_SIZE 8
4115 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4116 {
4117 struct ixgbe_hw *hw = &adapter->hw;
4118 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4119 u32 vid_start = vfta_offset * 32;
4120 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4121 u32 i, vid, word, bits;
4122
4123 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4124 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
4125
4126 /* pull VLAN ID from VLVF */
4127 vid = vlvf & VLAN_VID_MASK;
4128
4129 /* only concern outselves with a certain range */
4130 if (vid < vid_start || vid >= vid_end)
4131 continue;
4132
4133 if (vlvf) {
4134 /* record VLAN ID in VFTA */
4135 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32);
4136
4137 /* if PF is part of this then continue */
4138 if (test_bit(vid, adapter->active_vlans))
4139 continue;
4140 }
4141
4142 /* remove PF from the pool */
4143 word = i * 2 + VMDQ_P(0) / 32;
4144 bits = ~(1 << (VMDQ_P(0) % 32));
4145 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4146 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits);
4147 }
4148
4149 /* extract values from active_vlans and write back to VFTA */
4150 for (i = VFTA_BLOCK_SIZE; i--;) {
4151 vid = (vfta_offset + i) * 32;
4152 word = vid / BITS_PER_LONG;
4153 bits = vid % BITS_PER_LONG;
4154
4155 vfta[i] |= adapter->active_vlans[word] >> bits;
4156
4157 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]);
4158 }
4159 }
4160
4161 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter)
4162 {
4163 struct ixgbe_hw *hw = &adapter->hw;
4164 u32 vlnctrl, i;
4165
4166 switch (hw->mac.type) {
4167 case ixgbe_mac_82599EB:
4168 case ixgbe_mac_X540:
4169 case ixgbe_mac_X550:
4170 case ixgbe_mac_X550EM_x:
4171 default:
4172 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)
4173 break;
4174 /* fall through */
4175 case ixgbe_mac_82598EB:
4176 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4177 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
4178 vlnctrl |= IXGBE_VLNCTRL_VFE;
4179 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4180 return;
4181 }
4182
4183 /* We are not in VLAN promisc, nothing to do */
4184 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4185 return;
4186
4187 /* Set flag so we don't redo unnecessary work */
4188 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4189
4190 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE)
4191 ixgbe_scrub_vfta(adapter, i);
4192 }
4193
4194 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
4195 {
4196 u16 vid = 1;
4197
4198 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
4199
4200 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
4201 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
4202 }
4203
4204 /**
4205 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4206 * @netdev: network interface device structure
4207 *
4208 * Writes multicast address list to the MTA hash table.
4209 * Returns: -ENOMEM on failure
4210 * 0 on no addresses written
4211 * X on writing X addresses to MTA
4212 **/
4213 static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4214 {
4215 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4216 struct ixgbe_hw *hw = &adapter->hw;
4217
4218 if (!netif_running(netdev))
4219 return 0;
4220
4221 if (hw->mac.ops.update_mc_addr_list)
4222 hw->mac.ops.update_mc_addr_list(hw, netdev);
4223 else
4224 return -ENOMEM;
4225
4226 #ifdef CONFIG_PCI_IOV
4227 ixgbe_restore_vf_multicasts(adapter);
4228 #endif
4229
4230 return netdev_mc_count(netdev);
4231 }
4232
4233 #ifdef CONFIG_PCI_IOV
4234 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4235 {
4236 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4237 struct ixgbe_hw *hw = &adapter->hw;
4238 int i;
4239
4240 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4241 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4242
4243 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4244 hw->mac.ops.set_rar(hw, i,
4245 mac_table->addr,
4246 mac_table->pool,
4247 IXGBE_RAH_AV);
4248 else
4249 hw->mac.ops.clear_rar(hw, i);
4250 }
4251 }
4252
4253 #endif
4254 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4255 {
4256 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4257 struct ixgbe_hw *hw = &adapter->hw;
4258 int i;
4259
4260 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4261 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4262 continue;
4263
4264 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4265
4266 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4267 hw->mac.ops.set_rar(hw, i,
4268 mac_table->addr,
4269 mac_table->pool,
4270 IXGBE_RAH_AV);
4271 else
4272 hw->mac.ops.clear_rar(hw, i);
4273 }
4274 }
4275
4276 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4277 {
4278 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4279 struct ixgbe_hw *hw = &adapter->hw;
4280 int i;
4281
4282 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4283 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4284 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4285 }
4286
4287 ixgbe_sync_mac_table(adapter);
4288 }
4289
4290 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
4291 {
4292 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4293 struct ixgbe_hw *hw = &adapter->hw;
4294 int i, count = 0;
4295
4296 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4297 /* do not count default RAR as available */
4298 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4299 continue;
4300
4301 /* only count unused and addresses that belong to us */
4302 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4303 if (mac_table->pool != pool)
4304 continue;
4305 }
4306
4307 count++;
4308 }
4309
4310 return count;
4311 }
4312
4313 /* this function destroys the first RAR entry */
4314 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
4315 {
4316 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4317 struct ixgbe_hw *hw = &adapter->hw;
4318
4319 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4320 mac_table->pool = VMDQ_P(0);
4321
4322 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4323
4324 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
4325 IXGBE_RAH_AV);
4326 }
4327
4328 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4329 const u8 *addr, u16 pool)
4330 {
4331 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4332 struct ixgbe_hw *hw = &adapter->hw;
4333 int i;
4334
4335 if (is_zero_ether_addr(addr))
4336 return -EINVAL;
4337
4338 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4339 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4340 continue;
4341
4342 ether_addr_copy(mac_table->addr, addr);
4343 mac_table->pool = pool;
4344
4345 mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4346 IXGBE_MAC_STATE_IN_USE;
4347
4348 ixgbe_sync_mac_table(adapter);
4349
4350 return i;
4351 }
4352
4353 return -ENOMEM;
4354 }
4355
4356 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4357 const u8 *addr, u16 pool)
4358 {
4359 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4360 struct ixgbe_hw *hw = &adapter->hw;
4361 int i;
4362
4363 if (is_zero_ether_addr(addr))
4364 return -EINVAL;
4365
4366 /* search table for addr, if found clear IN_USE flag and sync */
4367 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4368 /* we can only delete an entry if it is in use */
4369 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4370 continue;
4371 /* we only care about entries that belong to the given pool */
4372 if (mac_table->pool != pool)
4373 continue;
4374 /* we only care about a specific MAC address */
4375 if (!ether_addr_equal(addr, mac_table->addr))
4376 continue;
4377
4378 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4379 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4380
4381 ixgbe_sync_mac_table(adapter);
4382
4383 return 0;
4384 }
4385
4386 return -ENOMEM;
4387 }
4388 /**
4389 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4390 * @netdev: network interface device structure
4391 *
4392 * Writes unicast address list to the RAR table.
4393 * Returns: -ENOMEM on failure/insufficient address space
4394 * 0 on no addresses written
4395 * X on writing X addresses to the RAR table
4396 **/
4397 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
4398 {
4399 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4400 int count = 0;
4401
4402 /* return ENOMEM indicating insufficient memory for addresses */
4403 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn))
4404 return -ENOMEM;
4405
4406 if (!netdev_uc_empty(netdev)) {
4407 struct netdev_hw_addr *ha;
4408 netdev_for_each_uc_addr(ha, netdev) {
4409 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4410 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
4411 count++;
4412 }
4413 }
4414 return count;
4415 }
4416
4417 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4418 {
4419 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4420 int ret;
4421
4422 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4423
4424 return min_t(int, ret, 0);
4425 }
4426
4427 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4428 {
4429 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4430
4431 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4432
4433 return 0;
4434 }
4435
4436 /**
4437 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
4438 * @netdev: network interface device structure
4439 *
4440 * The set_rx_method entry point is called whenever the unicast/multicast
4441 * address list or the network interface flags are updated. This routine is
4442 * responsible for configuring the hardware for proper unicast, multicast and
4443 * promiscuous mode.
4444 **/
4445 void ixgbe_set_rx_mode(struct net_device *netdev)
4446 {
4447 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4448 struct ixgbe_hw *hw = &adapter->hw;
4449 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
4450 netdev_features_t features = netdev->features;
4451 int count;
4452
4453 /* Check for Promiscuous and All Multicast modes */
4454 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4455
4456 /* set all bits that we expect to always be set */
4457 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
4458 fctrl |= IXGBE_FCTRL_BAM;
4459 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4460 fctrl |= IXGBE_FCTRL_PMCF;
4461
4462 /* clear the bits we are changing the status of */
4463 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4464 if (netdev->flags & IFF_PROMISC) {
4465 hw->addr_ctrl.user_set_promisc = true;
4466 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4467 vmolr |= IXGBE_VMOLR_MPE;
4468 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4469 } else {
4470 if (netdev->flags & IFF_ALLMULTI) {
4471 fctrl |= IXGBE_FCTRL_MPE;
4472 vmolr |= IXGBE_VMOLR_MPE;
4473 }
4474 hw->addr_ctrl.user_set_promisc = false;
4475 }
4476
4477 /*
4478 * Write addresses to available RAR registers, if there is not
4479 * sufficient space to store all the addresses then enable
4480 * unicast promiscuous mode
4481 */
4482 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
4483 fctrl |= IXGBE_FCTRL_UPE;
4484 vmolr |= IXGBE_VMOLR_ROPE;
4485 }
4486
4487 /* Write addresses to the MTA, if the attempt fails
4488 * then we should just turn on promiscuous mode so
4489 * that we can at least receive multicast traffic
4490 */
4491 count = ixgbe_write_mc_addr_list(netdev);
4492 if (count < 0) {
4493 fctrl |= IXGBE_FCTRL_MPE;
4494 vmolr |= IXGBE_VMOLR_MPE;
4495 } else if (count) {
4496 vmolr |= IXGBE_VMOLR_ROMPE;
4497 }
4498
4499 if (hw->mac.type != ixgbe_mac_82598EB) {
4500 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
4501 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4502 IXGBE_VMOLR_ROPE);
4503 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
4504 }
4505
4506 /* This is useful for sniffing bad packets. */
4507 if (features & NETIF_F_RXALL) {
4508 /* UPE and MPE will be handled by normal PROMISC logic
4509 * in e1000e_set_rx_mode */
4510 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4511 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4512 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4513
4514 fctrl &= ~(IXGBE_FCTRL_DPF);
4515 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4516 }
4517
4518 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4519
4520 if (features & NETIF_F_HW_VLAN_CTAG_RX)
4521 ixgbe_vlan_strip_enable(adapter);
4522 else
4523 ixgbe_vlan_strip_disable(adapter);
4524
4525 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
4526 ixgbe_vlan_promisc_disable(adapter);
4527 else
4528 ixgbe_vlan_promisc_enable(adapter);
4529 }
4530
4531 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4532 {
4533 int q_idx;
4534
4535 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4536 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
4537 napi_enable(&adapter->q_vector[q_idx]->napi);
4538 }
4539 }
4540
4541 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4542 {
4543 int q_idx;
4544
4545 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4546 napi_disable(&adapter->q_vector[q_idx]->napi);
4547 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
4548 pr_info("QV %d locked\n", q_idx);
4549 usleep_range(1000, 20000);
4550 }
4551 }
4552 }
4553
4554 static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter)
4555 {
4556 switch (adapter->hw.mac.type) {
4557 case ixgbe_mac_X550:
4558 case ixgbe_mac_X550EM_x:
4559 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0);
4560 adapter->vxlan_port = 0;
4561 break;
4562 default:
4563 break;
4564 }
4565 }
4566
4567 #ifdef CONFIG_IXGBE_DCB
4568 /**
4569 * ixgbe_configure_dcb - Configure DCB hardware
4570 * @adapter: ixgbe adapter struct
4571 *
4572 * This is called by the driver on open to configure the DCB hardware.
4573 * This is also called by the gennetlink interface when reconfiguring
4574 * the DCB state.
4575 */
4576 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4577 {
4578 struct ixgbe_hw *hw = &adapter->hw;
4579 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4580
4581 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4582 if (hw->mac.type == ixgbe_mac_82598EB)
4583 netif_set_gso_max_size(adapter->netdev, 65536);
4584 return;
4585 }
4586
4587 if (hw->mac.type == ixgbe_mac_82598EB)
4588 netif_set_gso_max_size(adapter->netdev, 32768);
4589
4590 #ifdef IXGBE_FCOE
4591 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4592 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
4593 #endif
4594
4595 /* reconfigure the hardware */
4596 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
4597 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4598 DCB_TX_CONFIG);
4599 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4600 DCB_RX_CONFIG);
4601 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
4602 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4603 ixgbe_dcb_hw_ets(&adapter->hw,
4604 adapter->ixgbe_ieee_ets,
4605 max_frame);
4606 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4607 adapter->ixgbe_ieee_pfc->pfc_en,
4608 adapter->ixgbe_ieee_ets->prio_tc);
4609 }
4610
4611 /* Enable RSS Hash per TC */
4612 if (hw->mac.type != ixgbe_mac_82598EB) {
4613 u32 msb = 0;
4614 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
4615
4616 while (rss_i) {
4617 msb++;
4618 rss_i >>= 1;
4619 }
4620
4621 /* write msb to all 8 TCs in one write */
4622 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
4623 }
4624 }
4625 #endif
4626
4627 /* Additional bittime to account for IXGBE framing */
4628 #define IXGBE_ETH_FRAMING 20
4629
4630 /**
4631 * ixgbe_hpbthresh - calculate high water mark for flow control
4632 *
4633 * @adapter: board private structure to calculate for
4634 * @pb: packet buffer to calculate
4635 */
4636 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4637 {
4638 struct ixgbe_hw *hw = &adapter->hw;
4639 struct net_device *dev = adapter->netdev;
4640 int link, tc, kb, marker;
4641 u32 dv_id, rx_pba;
4642
4643 /* Calculate max LAN frame size */
4644 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4645
4646 #ifdef IXGBE_FCOE
4647 /* FCoE traffic class uses FCOE jumbo frames */
4648 if ((dev->features & NETIF_F_FCOE_MTU) &&
4649 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4650 (pb == ixgbe_fcoe_get_tc(adapter)))
4651 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4652 #endif
4653
4654 /* Calculate delay value for device */
4655 switch (hw->mac.type) {
4656 case ixgbe_mac_X540:
4657 case ixgbe_mac_X550:
4658 case ixgbe_mac_X550EM_x:
4659 dv_id = IXGBE_DV_X540(link, tc);
4660 break;
4661 default:
4662 dv_id = IXGBE_DV(link, tc);
4663 break;
4664 }
4665
4666 /* Loopback switch introduces additional latency */
4667 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4668 dv_id += IXGBE_B2BT(tc);
4669
4670 /* Delay value is calculated in bit times convert to KB */
4671 kb = IXGBE_BT2KB(dv_id);
4672 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4673
4674 marker = rx_pba - kb;
4675
4676 /* It is possible that the packet buffer is not large enough
4677 * to provide required headroom. In this case throw an error
4678 * to user and a do the best we can.
4679 */
4680 if (marker < 0) {
4681 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4682 "headroom to support flow control."
4683 "Decrease MTU or number of traffic classes\n", pb);
4684 marker = tc + 1;
4685 }
4686
4687 return marker;
4688 }
4689
4690 /**
4691 * ixgbe_lpbthresh - calculate low water mark for for flow control
4692 *
4693 * @adapter: board private structure to calculate for
4694 * @pb: packet buffer to calculate
4695 */
4696 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
4697 {
4698 struct ixgbe_hw *hw = &adapter->hw;
4699 struct net_device *dev = adapter->netdev;
4700 int tc;
4701 u32 dv_id;
4702
4703 /* Calculate max LAN frame size */
4704 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4705
4706 #ifdef IXGBE_FCOE
4707 /* FCoE traffic class uses FCOE jumbo frames */
4708 if ((dev->features & NETIF_F_FCOE_MTU) &&
4709 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4710 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4711 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4712 #endif
4713
4714 /* Calculate delay value for device */
4715 switch (hw->mac.type) {
4716 case ixgbe_mac_X540:
4717 case ixgbe_mac_X550:
4718 case ixgbe_mac_X550EM_x:
4719 dv_id = IXGBE_LOW_DV_X540(tc);
4720 break;
4721 default:
4722 dv_id = IXGBE_LOW_DV(tc);
4723 break;
4724 }
4725
4726 /* Delay value is calculated in bit times convert to KB */
4727 return IXGBE_BT2KB(dv_id);
4728 }
4729
4730 /*
4731 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4732 */
4733 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4734 {
4735 struct ixgbe_hw *hw = &adapter->hw;
4736 int num_tc = netdev_get_num_tc(adapter->netdev);
4737 int i;
4738
4739 if (!num_tc)
4740 num_tc = 1;
4741
4742 for (i = 0; i < num_tc; i++) {
4743 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4744 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
4745
4746 /* Low water marks must not be larger than high water marks */
4747 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4748 hw->fc.low_water[i] = 0;
4749 }
4750
4751 for (; i < MAX_TRAFFIC_CLASS; i++)
4752 hw->fc.high_water[i] = 0;
4753 }
4754
4755 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4756 {
4757 struct ixgbe_hw *hw = &adapter->hw;
4758 int hdrm;
4759 u8 tc = netdev_get_num_tc(adapter->netdev);
4760
4761 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4762 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4763 hdrm = 32 << adapter->fdir_pballoc;
4764 else
4765 hdrm = 0;
4766
4767 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
4768 ixgbe_pbthresh_setup(adapter);
4769 }
4770
4771 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4772 {
4773 struct ixgbe_hw *hw = &adapter->hw;
4774 struct hlist_node *node2;
4775 struct ixgbe_fdir_filter *filter;
4776
4777 spin_lock(&adapter->fdir_perfect_lock);
4778
4779 if (!hlist_empty(&adapter->fdir_filter_list))
4780 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4781
4782 hlist_for_each_entry_safe(filter, node2,
4783 &adapter->fdir_filter_list, fdir_node) {
4784 ixgbe_fdir_write_perfect_filter_82599(hw,
4785 &filter->filter,
4786 filter->sw_idx,
4787 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4788 IXGBE_FDIR_DROP_QUEUE :
4789 adapter->rx_ring[filter->action]->reg_idx);
4790 }
4791
4792 spin_unlock(&adapter->fdir_perfect_lock);
4793 }
4794
4795 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4796 struct ixgbe_adapter *adapter)
4797 {
4798 struct ixgbe_hw *hw = &adapter->hw;
4799 u32 vmolr;
4800
4801 /* No unicast promiscuous support for VMDQ devices. */
4802 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4803 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4804
4805 /* clear the affected bit */
4806 vmolr &= ~IXGBE_VMOLR_MPE;
4807
4808 if (dev->flags & IFF_ALLMULTI) {
4809 vmolr |= IXGBE_VMOLR_MPE;
4810 } else {
4811 vmolr |= IXGBE_VMOLR_ROMPE;
4812 hw->mac.ops.update_mc_addr_list(hw, dev);
4813 }
4814 ixgbe_write_uc_addr_list(adapter->netdev, pool);
4815 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4816 }
4817
4818 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4819 {
4820 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4821 int rss_i = adapter->num_rx_queues_per_pool;
4822 struct ixgbe_hw *hw = &adapter->hw;
4823 u16 pool = vadapter->pool;
4824 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4825 IXGBE_PSRTYPE_UDPHDR |
4826 IXGBE_PSRTYPE_IPV4HDR |
4827 IXGBE_PSRTYPE_L2HDR |
4828 IXGBE_PSRTYPE_IPV6HDR;
4829
4830 if (hw->mac.type == ixgbe_mac_82598EB)
4831 return;
4832
4833 if (rss_i > 3)
4834 psrtype |= 2 << 29;
4835 else if (rss_i > 1)
4836 psrtype |= 1 << 29;
4837
4838 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4839 }
4840
4841 /**
4842 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4843 * @rx_ring: ring to free buffers from
4844 **/
4845 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4846 {
4847 struct device *dev = rx_ring->dev;
4848 unsigned long size;
4849 u16 i;
4850
4851 /* ring already cleared, nothing to do */
4852 if (!rx_ring->rx_buffer_info)
4853 return;
4854
4855 /* Free all the Rx ring sk_buffs */
4856 for (i = 0; i < rx_ring->count; i++) {
4857 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
4858
4859 if (rx_buffer->skb) {
4860 struct sk_buff *skb = rx_buffer->skb;
4861 if (IXGBE_CB(skb)->page_released)
4862 dma_unmap_page(dev,
4863 IXGBE_CB(skb)->dma,
4864 ixgbe_rx_bufsz(rx_ring),
4865 DMA_FROM_DEVICE);
4866 dev_kfree_skb(skb);
4867 rx_buffer->skb = NULL;
4868 }
4869
4870 if (!rx_buffer->page)
4871 continue;
4872
4873 dma_unmap_page(dev, rx_buffer->dma,
4874 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4875 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4876
4877 rx_buffer->page = NULL;
4878 }
4879
4880 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4881 memset(rx_ring->rx_buffer_info, 0, size);
4882
4883 /* Zero out the descriptor ring */
4884 memset(rx_ring->desc, 0, rx_ring->size);
4885
4886 rx_ring->next_to_alloc = 0;
4887 rx_ring->next_to_clean = 0;
4888 rx_ring->next_to_use = 0;
4889 }
4890
4891 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4892 struct ixgbe_ring *rx_ring)
4893 {
4894 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4895 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4896
4897 /* shutdown specific queue receive and wait for dma to settle */
4898 ixgbe_disable_rx_queue(adapter, rx_ring);
4899 usleep_range(10000, 20000);
4900 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4901 ixgbe_clean_rx_ring(rx_ring);
4902 rx_ring->l2_accel_priv = NULL;
4903 }
4904
4905 static int ixgbe_fwd_ring_down(struct net_device *vdev,
4906 struct ixgbe_fwd_adapter *accel)
4907 {
4908 struct ixgbe_adapter *adapter = accel->real_adapter;
4909 unsigned int rxbase = accel->rx_base_queue;
4910 unsigned int txbase = accel->tx_base_queue;
4911 int i;
4912
4913 netif_tx_stop_all_queues(vdev);
4914
4915 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4916 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4917 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4918 }
4919
4920 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4921 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4922 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4923 }
4924
4925
4926 return 0;
4927 }
4928
4929 static int ixgbe_fwd_ring_up(struct net_device *vdev,
4930 struct ixgbe_fwd_adapter *accel)
4931 {
4932 struct ixgbe_adapter *adapter = accel->real_adapter;
4933 unsigned int rxbase, txbase, queues;
4934 int i, baseq, err = 0;
4935
4936 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4937 return 0;
4938
4939 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4940 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4941 accel->pool, adapter->num_rx_pools,
4942 baseq, baseq + adapter->num_rx_queues_per_pool,
4943 adapter->fwd_bitmask);
4944
4945 accel->netdev = vdev;
4946 accel->rx_base_queue = rxbase = baseq;
4947 accel->tx_base_queue = txbase = baseq;
4948
4949 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4950 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4951
4952 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4953 adapter->rx_ring[rxbase + i]->netdev = vdev;
4954 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4955 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4956 }
4957
4958 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4959 adapter->tx_ring[txbase + i]->netdev = vdev;
4960 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4961 }
4962
4963 queues = min_t(unsigned int,
4964 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4965 err = netif_set_real_num_tx_queues(vdev, queues);
4966 if (err)
4967 goto fwd_queue_err;
4968
4969 err = netif_set_real_num_rx_queues(vdev, queues);
4970 if (err)
4971 goto fwd_queue_err;
4972
4973 if (is_valid_ether_addr(vdev->dev_addr))
4974 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4975
4976 ixgbe_fwd_psrtype(accel);
4977 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4978 return err;
4979 fwd_queue_err:
4980 ixgbe_fwd_ring_down(vdev, accel);
4981 return err;
4982 }
4983
4984 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4985 {
4986 struct net_device *upper;
4987 struct list_head *iter;
4988 int err;
4989
4990 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4991 if (netif_is_macvlan(upper)) {
4992 struct macvlan_dev *dfwd = netdev_priv(upper);
4993 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4994
4995 if (dfwd->fwd_priv) {
4996 err = ixgbe_fwd_ring_up(upper, vadapter);
4997 if (err)
4998 continue;
4999 }
5000 }
5001 }
5002 }
5003
5004 static void ixgbe_configure(struct ixgbe_adapter *adapter)
5005 {
5006 struct ixgbe_hw *hw = &adapter->hw;
5007
5008 ixgbe_configure_pb(adapter);
5009 #ifdef CONFIG_IXGBE_DCB
5010 ixgbe_configure_dcb(adapter);
5011 #endif
5012 /*
5013 * We must restore virtualization before VLANs or else
5014 * the VLVF registers will not be populated
5015 */
5016 ixgbe_configure_virtualization(adapter);
5017
5018 ixgbe_set_rx_mode(adapter->netdev);
5019 ixgbe_restore_vlan(adapter);
5020
5021 switch (hw->mac.type) {
5022 case ixgbe_mac_82599EB:
5023 case ixgbe_mac_X540:
5024 hw->mac.ops.disable_rx_buff(hw);
5025 break;
5026 default:
5027 break;
5028 }
5029
5030 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5031 ixgbe_init_fdir_signature_82599(&adapter->hw,
5032 adapter->fdir_pballoc);
5033 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
5034 ixgbe_init_fdir_perfect_82599(&adapter->hw,
5035 adapter->fdir_pballoc);
5036 ixgbe_fdir_filter_restore(adapter);
5037 }
5038
5039 switch (hw->mac.type) {
5040 case ixgbe_mac_82599EB:
5041 case ixgbe_mac_X540:
5042 hw->mac.ops.enable_rx_buff(hw);
5043 break;
5044 default:
5045 break;
5046 }
5047
5048 #ifdef CONFIG_IXGBE_DCA
5049 /* configure DCA */
5050 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
5051 ixgbe_setup_dca(adapter);
5052 #endif /* CONFIG_IXGBE_DCA */
5053
5054 #ifdef IXGBE_FCOE
5055 /* configure FCoE L2 filters, redirection table, and Rx control */
5056 ixgbe_configure_fcoe(adapter);
5057
5058 #endif /* IXGBE_FCOE */
5059 ixgbe_configure_tx(adapter);
5060 ixgbe_configure_rx(adapter);
5061 ixgbe_configure_dfwd(adapter);
5062 }
5063
5064 /**
5065 * ixgbe_sfp_link_config - set up SFP+ link
5066 * @adapter: pointer to private adapter struct
5067 **/
5068 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
5069 {
5070 /*
5071 * We are assuming the worst case scenario here, and that
5072 * is that an SFP was inserted/removed after the reset
5073 * but before SFP detection was enabled. As such the best
5074 * solution is to just start searching as soon as we start
5075 */
5076 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5077 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5078
5079 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5080 adapter->sfp_poll_time = 0;
5081 }
5082
5083 /**
5084 * ixgbe_non_sfp_link_config - set up non-SFP+ link
5085 * @hw: pointer to private hardware struct
5086 *
5087 * Returns 0 on success, negative on failure
5088 **/
5089 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
5090 {
5091 u32 speed;
5092 bool autoneg, link_up = false;
5093 int ret = IXGBE_ERR_LINK_SETUP;
5094
5095 if (hw->mac.ops.check_link)
5096 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
5097
5098 if (ret)
5099 return ret;
5100
5101 speed = hw->phy.autoneg_advertised;
5102 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5103 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
5104 &autoneg);
5105 if (ret)
5106 return ret;
5107
5108 if (hw->mac.ops.setup_link)
5109 ret = hw->mac.ops.setup_link(hw, speed, link_up);
5110
5111 return ret;
5112 }
5113
5114 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
5115 {
5116 struct ixgbe_hw *hw = &adapter->hw;
5117 u32 gpie = 0;
5118
5119 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5120 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5121 IXGBE_GPIE_OCD;
5122 gpie |= IXGBE_GPIE_EIAME;
5123 /*
5124 * use EIAM to auto-mask when MSI-X interrupt is asserted
5125 * this saves a register write for every interrupt
5126 */
5127 switch (hw->mac.type) {
5128 case ixgbe_mac_82598EB:
5129 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5130 break;
5131 case ixgbe_mac_82599EB:
5132 case ixgbe_mac_X540:
5133 case ixgbe_mac_X550:
5134 case ixgbe_mac_X550EM_x:
5135 default:
5136 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5137 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5138 break;
5139 }
5140 } else {
5141 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
5142 * specifically only auto mask tx and rx interrupts */
5143 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5144 }
5145
5146 /* XXX: to interrupt immediately for EICS writes, enable this */
5147 /* gpie |= IXGBE_GPIE_EIMEN; */
5148
5149 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
5150 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
5151
5152 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
5153 case IXGBE_82599_VMDQ_8Q_MASK:
5154 gpie |= IXGBE_GPIE_VTMODE_16;
5155 break;
5156 case IXGBE_82599_VMDQ_4Q_MASK:
5157 gpie |= IXGBE_GPIE_VTMODE_32;
5158 break;
5159 default:
5160 gpie |= IXGBE_GPIE_VTMODE_64;
5161 break;
5162 }
5163 }
5164
5165 /* Enable Thermal over heat sensor interrupt */
5166 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
5167 switch (adapter->hw.mac.type) {
5168 case ixgbe_mac_82599EB:
5169 gpie |= IXGBE_SDP0_GPIEN_8259X;
5170 break;
5171 default:
5172 break;
5173 }
5174 }
5175
5176 /* Enable fan failure interrupt */
5177 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
5178 gpie |= IXGBE_SDP1_GPIEN(hw);
5179
5180 switch (hw->mac.type) {
5181 case ixgbe_mac_82599EB:
5182 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
5183 break;
5184 case ixgbe_mac_X550EM_x:
5185 gpie |= IXGBE_SDP0_GPIEN_X540;
5186 break;
5187 default:
5188 break;
5189 }
5190
5191 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5192 }
5193
5194 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
5195 {
5196 struct ixgbe_hw *hw = &adapter->hw;
5197 int err;
5198 u32 ctrl_ext;
5199
5200 ixgbe_get_hw_control(adapter);
5201 ixgbe_setup_gpie(adapter);
5202
5203 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5204 ixgbe_configure_msix(adapter);
5205 else
5206 ixgbe_configure_msi_and_legacy(adapter);
5207
5208 /* enable the optics for 82599 SFP+ fiber */
5209 if (hw->mac.ops.enable_tx_laser)
5210 hw->mac.ops.enable_tx_laser(hw);
5211
5212 if (hw->phy.ops.set_phy_power)
5213 hw->phy.ops.set_phy_power(hw, true);
5214
5215 smp_mb__before_atomic();
5216 clear_bit(__IXGBE_DOWN, &adapter->state);
5217 ixgbe_napi_enable_all(adapter);
5218
5219 if (ixgbe_is_sfp(hw)) {
5220 ixgbe_sfp_link_config(adapter);
5221 } else {
5222 err = ixgbe_non_sfp_link_config(hw);
5223 if (err)
5224 e_err(probe, "link_config FAILED %d\n", err);
5225 }
5226
5227 /* clear any pending interrupts, may auto mask */
5228 IXGBE_READ_REG(hw, IXGBE_EICR);
5229 ixgbe_irq_enable(adapter, true, true);
5230
5231 /*
5232 * If this adapter has a fan, check to see if we had a failure
5233 * before we enabled the interrupt.
5234 */
5235 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5236 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5237 if (esdp & IXGBE_ESDP_SDP1)
5238 e_crit(drv, "Fan has stopped, replace the adapter\n");
5239 }
5240
5241 /* bring the link up in the watchdog, this could race with our first
5242 * link up interrupt but shouldn't be a problem */
5243 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5244 adapter->link_check_timeout = jiffies;
5245 mod_timer(&adapter->service_timer, jiffies);
5246
5247 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5248 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5249 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5250 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
5251 }
5252
5253 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5254 {
5255 WARN_ON(in_interrupt());
5256 /* put off any impending NetWatchDogTimeout */
5257 adapter->netdev->trans_start = jiffies;
5258
5259 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
5260 usleep_range(1000, 2000);
5261 ixgbe_down(adapter);
5262 /*
5263 * If SR-IOV enabled then wait a bit before bringing the adapter
5264 * back up to give the VFs time to respond to the reset. The
5265 * two second wait is based upon the watchdog timer cycle in
5266 * the VF driver.
5267 */
5268 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5269 msleep(2000);
5270 ixgbe_up(adapter);
5271 clear_bit(__IXGBE_RESETTING, &adapter->state);
5272 }
5273
5274 void ixgbe_up(struct ixgbe_adapter *adapter)
5275 {
5276 /* hardware has been reset, we need to reload some things */
5277 ixgbe_configure(adapter);
5278
5279 ixgbe_up_complete(adapter);
5280 }
5281
5282 void ixgbe_reset(struct ixgbe_adapter *adapter)
5283 {
5284 struct ixgbe_hw *hw = &adapter->hw;
5285 struct net_device *netdev = adapter->netdev;
5286 int err;
5287
5288 if (ixgbe_removed(hw->hw_addr))
5289 return;
5290 /* lock SFP init bit to prevent race conditions with the watchdog */
5291 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5292 usleep_range(1000, 2000);
5293
5294 /* clear all SFP and link config related flags while holding SFP_INIT */
5295 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5296 IXGBE_FLAG2_SFP_NEEDS_RESET);
5297 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5298
5299 err = hw->mac.ops.init_hw(hw);
5300 switch (err) {
5301 case 0:
5302 case IXGBE_ERR_SFP_NOT_PRESENT:
5303 case IXGBE_ERR_SFP_NOT_SUPPORTED:
5304 break;
5305 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
5306 e_dev_err("master disable timed out\n");
5307 break;
5308 case IXGBE_ERR_EEPROM_VERSION:
5309 /* We are running on a pre-production device, log a warning */
5310 e_dev_warn("This device is a pre-production adapter/LOM. "
5311 "Please be aware there may be issues associated with "
5312 "your hardware. If you are experiencing problems "
5313 "please contact your Intel or hardware "
5314 "representative who provided you with this "
5315 "hardware.\n");
5316 break;
5317 default:
5318 e_dev_err("Hardware Error: %d\n", err);
5319 }
5320
5321 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5322
5323 /* flush entries out of MAC table */
5324 ixgbe_flush_sw_mac_table(adapter);
5325 __dev_uc_unsync(netdev, NULL);
5326
5327 /* do not flush user set addresses */
5328 ixgbe_mac_set_default_filter(adapter);
5329
5330 /* update SAN MAC vmdq pool selection */
5331 if (hw->mac.san_mac_rar_index)
5332 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
5333
5334 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
5335 ixgbe_ptp_reset(adapter);
5336
5337 if (hw->phy.ops.set_phy_power) {
5338 if (!netif_running(adapter->netdev) && !adapter->wol)
5339 hw->phy.ops.set_phy_power(hw, false);
5340 else
5341 hw->phy.ops.set_phy_power(hw, true);
5342 }
5343 }
5344
5345 /**
5346 * ixgbe_clean_tx_ring - Free Tx Buffers
5347 * @tx_ring: ring to be cleaned
5348 **/
5349 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
5350 {
5351 struct ixgbe_tx_buffer *tx_buffer_info;
5352 unsigned long size;
5353 u16 i;
5354
5355 /* ring already cleared, nothing to do */
5356 if (!tx_ring->tx_buffer_info)
5357 return;
5358
5359 /* Free all the Tx ring sk_buffs */
5360 for (i = 0; i < tx_ring->count; i++) {
5361 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5362 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
5363 }
5364
5365 netdev_tx_reset_queue(txring_txq(tx_ring));
5366
5367 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5368 memset(tx_ring->tx_buffer_info, 0, size);
5369
5370 /* Zero out the descriptor ring */
5371 memset(tx_ring->desc, 0, tx_ring->size);
5372
5373 tx_ring->next_to_use = 0;
5374 tx_ring->next_to_clean = 0;
5375 }
5376
5377 /**
5378 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
5379 * @adapter: board private structure
5380 **/
5381 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
5382 {
5383 int i;
5384
5385 for (i = 0; i < adapter->num_rx_queues; i++)
5386 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
5387 }
5388
5389 /**
5390 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
5391 * @adapter: board private structure
5392 **/
5393 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
5394 {
5395 int i;
5396
5397 for (i = 0; i < adapter->num_tx_queues; i++)
5398 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
5399 }
5400
5401 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5402 {
5403 struct hlist_node *node2;
5404 struct ixgbe_fdir_filter *filter;
5405
5406 spin_lock(&adapter->fdir_perfect_lock);
5407
5408 hlist_for_each_entry_safe(filter, node2,
5409 &adapter->fdir_filter_list, fdir_node) {
5410 hlist_del(&filter->fdir_node);
5411 kfree(filter);
5412 }
5413 adapter->fdir_filter_count = 0;
5414
5415 spin_unlock(&adapter->fdir_perfect_lock);
5416 }
5417
5418 void ixgbe_down(struct ixgbe_adapter *adapter)
5419 {
5420 struct net_device *netdev = adapter->netdev;
5421 struct ixgbe_hw *hw = &adapter->hw;
5422 struct net_device *upper;
5423 struct list_head *iter;
5424 int i;
5425
5426 /* signal that we are down to the interrupt handler */
5427 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5428 return; /* do nothing if already down */
5429
5430 /* disable receives */
5431 hw->mac.ops.disable_rx(hw);
5432
5433 /* disable all enabled rx queues */
5434 for (i = 0; i < adapter->num_rx_queues; i++)
5435 /* this call also flushes the previous write */
5436 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5437
5438 usleep_range(10000, 20000);
5439
5440 netif_tx_stop_all_queues(netdev);
5441
5442 /* call carrier off first to avoid false dev_watchdog timeouts */
5443 netif_carrier_off(netdev);
5444 netif_tx_disable(netdev);
5445
5446 /* disable any upper devices */
5447 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5448 if (netif_is_macvlan(upper)) {
5449 struct macvlan_dev *vlan = netdev_priv(upper);
5450
5451 if (vlan->fwd_priv) {
5452 netif_tx_stop_all_queues(upper);
5453 netif_carrier_off(upper);
5454 netif_tx_disable(upper);
5455 }
5456 }
5457 }
5458
5459 ixgbe_irq_disable(adapter);
5460
5461 ixgbe_napi_disable_all(adapter);
5462
5463 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5464 IXGBE_FLAG2_RESET_REQUESTED);
5465 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5466
5467 del_timer_sync(&adapter->service_timer);
5468
5469 if (adapter->num_vfs) {
5470 /* Clear EITR Select mapping */
5471 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
5472
5473 /* Mark all the VFs as inactive */
5474 for (i = 0 ; i < adapter->num_vfs; i++)
5475 adapter->vfinfo[i].clear_to_send = false;
5476
5477 /* ping all the active vfs to let them know we are going down */
5478 ixgbe_ping_all_vfs(adapter);
5479
5480 /* Disable all VFTE/VFRE TX/RX */
5481 ixgbe_disable_tx_rx(adapter);
5482 }
5483
5484 /* disable transmits in the hardware now that interrupts are off */
5485 for (i = 0; i < adapter->num_tx_queues; i++) {
5486 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
5487 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5488 }
5489
5490 /* Disable the Tx DMA engine on 82599 and later MAC */
5491 switch (hw->mac.type) {
5492 case ixgbe_mac_82599EB:
5493 case ixgbe_mac_X540:
5494 case ixgbe_mac_X550:
5495 case ixgbe_mac_X550EM_x:
5496 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
5497 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5498 ~IXGBE_DMATXCTL_TE));
5499 break;
5500 default:
5501 break;
5502 }
5503
5504 if (!pci_channel_offline(adapter->pdev))
5505 ixgbe_reset(adapter);
5506
5507 /* power down the optics for 82599 SFP+ fiber */
5508 if (hw->mac.ops.disable_tx_laser)
5509 hw->mac.ops.disable_tx_laser(hw);
5510
5511 ixgbe_clean_all_tx_rings(adapter);
5512 ixgbe_clean_all_rx_rings(adapter);
5513 }
5514
5515 /**
5516 * ixgbe_tx_timeout - Respond to a Tx Hang
5517 * @netdev: network interface device structure
5518 **/
5519 static void ixgbe_tx_timeout(struct net_device *netdev)
5520 {
5521 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5522
5523 /* Do the reset outside of interrupt context */
5524 ixgbe_tx_timeout_reset(adapter);
5525 }
5526
5527 /**
5528 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5529 * @adapter: board private structure to initialize
5530 *
5531 * ixgbe_sw_init initializes the Adapter private data structure.
5532 * Fields are initialized based on PCI device information and
5533 * OS network device settings (MTU size).
5534 **/
5535 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
5536 {
5537 struct ixgbe_hw *hw = &adapter->hw;
5538 struct pci_dev *pdev = adapter->pdev;
5539 unsigned int rss, fdir;
5540 u32 fwsm;
5541 #ifdef CONFIG_IXGBE_DCB
5542 int j;
5543 struct tc_configuration *tc;
5544 #endif
5545
5546 /* PCI config space info */
5547
5548 hw->vendor_id = pdev->vendor;
5549 hw->device_id = pdev->device;
5550 hw->revision_id = pdev->revision;
5551 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5552 hw->subsystem_device_id = pdev->subsystem_device;
5553
5554 /* Set common capability flags and settings */
5555 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
5556 adapter->ring_feature[RING_F_RSS].limit = rss;
5557 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5558 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5559 adapter->atr_sample_rate = 20;
5560 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5561 adapter->ring_feature[RING_F_FDIR].limit = fdir;
5562 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5563 #ifdef CONFIG_IXGBE_DCA
5564 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5565 #endif
5566 #ifdef IXGBE_FCOE
5567 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5568 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5569 #ifdef CONFIG_IXGBE_DCB
5570 /* Default traffic class to use for FCoE */
5571 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5572 #endif /* CONFIG_IXGBE_DCB */
5573 #endif /* IXGBE_FCOE */
5574
5575 /* initialize static ixgbe jump table entries */
5576 adapter->jump_tables[0] = ixgbe_ipv4_fields;
5577
5578 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5579 hw->mac.num_rar_entries,
5580 GFP_ATOMIC);
5581 if (!adapter->mac_table)
5582 return -ENOMEM;
5583
5584 /* Set MAC specific capability flags and exceptions */
5585 switch (hw->mac.type) {
5586 case ixgbe_mac_82598EB:
5587 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5588
5589 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5590 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5591
5592 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
5593 adapter->ring_feature[RING_F_FDIR].limit = 0;
5594 adapter->atr_sample_rate = 0;
5595 adapter->fdir_pballoc = 0;
5596 #ifdef IXGBE_FCOE
5597 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5598 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5599 #ifdef CONFIG_IXGBE_DCB
5600 adapter->fcoe.up = 0;
5601 #endif /* IXGBE_DCB */
5602 #endif /* IXGBE_FCOE */
5603 break;
5604 case ixgbe_mac_82599EB:
5605 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5606 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5607 break;
5608 case ixgbe_mac_X540:
5609 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
5610 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5611 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5612 break;
5613 case ixgbe_mac_X550EM_x:
5614 case ixgbe_mac_X550:
5615 #ifdef CONFIG_IXGBE_DCA
5616 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
5617 #endif
5618 #ifdef CONFIG_IXGBE_VXLAN
5619 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
5620 #endif
5621 break;
5622 default:
5623 break;
5624 }
5625
5626 #ifdef IXGBE_FCOE
5627 /* FCoE support exists, always init the FCoE lock */
5628 spin_lock_init(&adapter->fcoe.lock);
5629
5630 #endif
5631 /* n-tuple support exists, always init our spinlock */
5632 spin_lock_init(&adapter->fdir_perfect_lock);
5633
5634 #ifdef CONFIG_IXGBE_DCB
5635 switch (hw->mac.type) {
5636 case ixgbe_mac_X540:
5637 case ixgbe_mac_X550:
5638 case ixgbe_mac_X550EM_x:
5639 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5640 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5641 break;
5642 default:
5643 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5644 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5645 break;
5646 }
5647
5648 /* Configure DCB traffic classes */
5649 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5650 tc = &adapter->dcb_cfg.tc_config[j];
5651 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5652 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5653 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5654 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5655 tc->dcb_pfc = pfc_disabled;
5656 }
5657
5658 /* Initialize default user to priority mapping, UPx->TC0 */
5659 tc = &adapter->dcb_cfg.tc_config[0];
5660 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5661 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5662
5663 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5664 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5665 adapter->dcb_cfg.pfc_mode_enable = false;
5666 adapter->dcb_set_bitmap = 0x00;
5667 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5668 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5669 sizeof(adapter->temp_dcb_cfg));
5670
5671 #endif
5672
5673 /* default flow control settings */
5674 hw->fc.requested_mode = ixgbe_fc_full;
5675 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5676 ixgbe_pbthresh_setup(adapter);
5677 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5678 hw->fc.send_xon = true;
5679 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
5680
5681 #ifdef CONFIG_PCI_IOV
5682 if (max_vfs > 0)
5683 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5684
5685 /* assign number of SR-IOV VFs */
5686 if (hw->mac.type != ixgbe_mac_82598EB) {
5687 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
5688 adapter->num_vfs = 0;
5689 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5690 } else {
5691 adapter->num_vfs = max_vfs;
5692 }
5693 }
5694 #endif /* CONFIG_PCI_IOV */
5695
5696 /* enable itr by default in dynamic mode */
5697 adapter->rx_itr_setting = 1;
5698 adapter->tx_itr_setting = 1;
5699
5700 /* set default ring sizes */
5701 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5702 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5703
5704 /* set default work limits */
5705 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5706
5707 /* initialize eeprom parameters */
5708 if (ixgbe_init_eeprom_params_generic(hw)) {
5709 e_dev_err("EEPROM initialization failed\n");
5710 return -EIO;
5711 }
5712
5713 /* PF holds first pool slot */
5714 set_bit(0, &adapter->fwd_bitmask);
5715 set_bit(__IXGBE_DOWN, &adapter->state);
5716
5717 return 0;
5718 }
5719
5720 /**
5721 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5722 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5723 *
5724 * Return 0 on success, negative on failure
5725 **/
5726 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5727 {
5728 struct device *dev = tx_ring->dev;
5729 int orig_node = dev_to_node(dev);
5730 int ring_node = -1;
5731 int size;
5732
5733 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5734
5735 if (tx_ring->q_vector)
5736 ring_node = tx_ring->q_vector->numa_node;
5737
5738 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
5739 if (!tx_ring->tx_buffer_info)
5740 tx_ring->tx_buffer_info = vzalloc(size);
5741 if (!tx_ring->tx_buffer_info)
5742 goto err;
5743
5744 u64_stats_init(&tx_ring->syncp);
5745
5746 /* round up to nearest 4K */
5747 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5748 tx_ring->size = ALIGN(tx_ring->size, 4096);
5749
5750 set_dev_node(dev, ring_node);
5751 tx_ring->desc = dma_alloc_coherent(dev,
5752 tx_ring->size,
5753 &tx_ring->dma,
5754 GFP_KERNEL);
5755 set_dev_node(dev, orig_node);
5756 if (!tx_ring->desc)
5757 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5758 &tx_ring->dma, GFP_KERNEL);
5759 if (!tx_ring->desc)
5760 goto err;
5761
5762 tx_ring->next_to_use = 0;
5763 tx_ring->next_to_clean = 0;
5764 return 0;
5765
5766 err:
5767 vfree(tx_ring->tx_buffer_info);
5768 tx_ring->tx_buffer_info = NULL;
5769 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5770 return -ENOMEM;
5771 }
5772
5773 /**
5774 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5775 * @adapter: board private structure
5776 *
5777 * If this function returns with an error, then it's possible one or
5778 * more of the rings is populated (while the rest are not). It is the
5779 * callers duty to clean those orphaned rings.
5780 *
5781 * Return 0 on success, negative on failure
5782 **/
5783 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5784 {
5785 int i, err = 0;
5786
5787 for (i = 0; i < adapter->num_tx_queues; i++) {
5788 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5789 if (!err)
5790 continue;
5791
5792 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5793 goto err_setup_tx;
5794 }
5795
5796 return 0;
5797 err_setup_tx:
5798 /* rewind the index freeing the rings as we go */
5799 while (i--)
5800 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5801 return err;
5802 }
5803
5804 /**
5805 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5806 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5807 *
5808 * Returns 0 on success, negative on failure
5809 **/
5810 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5811 {
5812 struct device *dev = rx_ring->dev;
5813 int orig_node = dev_to_node(dev);
5814 int ring_node = -1;
5815 int size;
5816
5817 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5818
5819 if (rx_ring->q_vector)
5820 ring_node = rx_ring->q_vector->numa_node;
5821
5822 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
5823 if (!rx_ring->rx_buffer_info)
5824 rx_ring->rx_buffer_info = vzalloc(size);
5825 if (!rx_ring->rx_buffer_info)
5826 goto err;
5827
5828 u64_stats_init(&rx_ring->syncp);
5829
5830 /* Round up to nearest 4K */
5831 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5832 rx_ring->size = ALIGN(rx_ring->size, 4096);
5833
5834 set_dev_node(dev, ring_node);
5835 rx_ring->desc = dma_alloc_coherent(dev,
5836 rx_ring->size,
5837 &rx_ring->dma,
5838 GFP_KERNEL);
5839 set_dev_node(dev, orig_node);
5840 if (!rx_ring->desc)
5841 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5842 &rx_ring->dma, GFP_KERNEL);
5843 if (!rx_ring->desc)
5844 goto err;
5845
5846 rx_ring->next_to_clean = 0;
5847 rx_ring->next_to_use = 0;
5848
5849 return 0;
5850 err:
5851 vfree(rx_ring->rx_buffer_info);
5852 rx_ring->rx_buffer_info = NULL;
5853 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5854 return -ENOMEM;
5855 }
5856
5857 /**
5858 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5859 * @adapter: board private structure
5860 *
5861 * If this function returns with an error, then it's possible one or
5862 * more of the rings is populated (while the rest are not). It is the
5863 * callers duty to clean those orphaned rings.
5864 *
5865 * Return 0 on success, negative on failure
5866 **/
5867 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5868 {
5869 int i, err = 0;
5870
5871 for (i = 0; i < adapter->num_rx_queues; i++) {
5872 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5873 if (!err)
5874 continue;
5875
5876 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5877 goto err_setup_rx;
5878 }
5879
5880 #ifdef IXGBE_FCOE
5881 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5882 if (!err)
5883 #endif
5884 return 0;
5885 err_setup_rx:
5886 /* rewind the index freeing the rings as we go */
5887 while (i--)
5888 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5889 return err;
5890 }
5891
5892 /**
5893 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5894 * @tx_ring: Tx descriptor ring for a specific queue
5895 *
5896 * Free all transmit software resources
5897 **/
5898 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5899 {
5900 ixgbe_clean_tx_ring(tx_ring);
5901
5902 vfree(tx_ring->tx_buffer_info);
5903 tx_ring->tx_buffer_info = NULL;
5904
5905 /* if not set, then don't free */
5906 if (!tx_ring->desc)
5907 return;
5908
5909 dma_free_coherent(tx_ring->dev, tx_ring->size,
5910 tx_ring->desc, tx_ring->dma);
5911
5912 tx_ring->desc = NULL;
5913 }
5914
5915 /**
5916 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5917 * @adapter: board private structure
5918 *
5919 * Free all transmit software resources
5920 **/
5921 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5922 {
5923 int i;
5924
5925 for (i = 0; i < adapter->num_tx_queues; i++)
5926 if (adapter->tx_ring[i]->desc)
5927 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5928 }
5929
5930 /**
5931 * ixgbe_free_rx_resources - Free Rx Resources
5932 * @rx_ring: ring to clean the resources from
5933 *
5934 * Free all receive software resources
5935 **/
5936 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5937 {
5938 ixgbe_clean_rx_ring(rx_ring);
5939
5940 vfree(rx_ring->rx_buffer_info);
5941 rx_ring->rx_buffer_info = NULL;
5942
5943 /* if not set, then don't free */
5944 if (!rx_ring->desc)
5945 return;
5946
5947 dma_free_coherent(rx_ring->dev, rx_ring->size,
5948 rx_ring->desc, rx_ring->dma);
5949
5950 rx_ring->desc = NULL;
5951 }
5952
5953 /**
5954 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5955 * @adapter: board private structure
5956 *
5957 * Free all receive software resources
5958 **/
5959 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5960 {
5961 int i;
5962
5963 #ifdef IXGBE_FCOE
5964 ixgbe_free_fcoe_ddp_resources(adapter);
5965
5966 #endif
5967 for (i = 0; i < adapter->num_rx_queues; i++)
5968 if (adapter->rx_ring[i]->desc)
5969 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5970 }
5971
5972 /**
5973 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5974 * @netdev: network interface device structure
5975 * @new_mtu: new value for maximum frame size
5976 *
5977 * Returns 0 on success, negative on failure
5978 **/
5979 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5980 {
5981 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5982 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5983
5984 /* MTU < 68 is an error and causes problems on some kernels */
5985 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5986 return -EINVAL;
5987
5988 /*
5989 * For 82599EB we cannot allow legacy VFs to enable their receive
5990 * paths when MTU greater than 1500 is configured. So display a
5991 * warning that legacy VFs will be disabled.
5992 */
5993 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5994 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
5995 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
5996 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
5997
5998 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5999
6000 /* must set new MTU before calling down or up */
6001 netdev->mtu = new_mtu;
6002
6003 if (netif_running(netdev))
6004 ixgbe_reinit_locked(adapter);
6005
6006 return 0;
6007 }
6008
6009 /**
6010 * ixgbe_open - Called when a network interface is made active
6011 * @netdev: network interface device structure
6012 *
6013 * Returns 0 on success, negative value on failure
6014 *
6015 * The open entry point is called when a network interface is made
6016 * active by the system (IFF_UP). At this point all resources needed
6017 * for transmit and receive operations are allocated, the interrupt
6018 * handler is registered with the OS, the watchdog timer is started,
6019 * and the stack is notified that the interface is ready.
6020 **/
6021 int ixgbe_open(struct net_device *netdev)
6022 {
6023 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6024 struct ixgbe_hw *hw = &adapter->hw;
6025 int err, queues;
6026
6027 /* disallow open during test */
6028 if (test_bit(__IXGBE_TESTING, &adapter->state))
6029 return -EBUSY;
6030
6031 netif_carrier_off(netdev);
6032
6033 /* allocate transmit descriptors */
6034 err = ixgbe_setup_all_tx_resources(adapter);
6035 if (err)
6036 goto err_setup_tx;
6037
6038 /* allocate receive descriptors */
6039 err = ixgbe_setup_all_rx_resources(adapter);
6040 if (err)
6041 goto err_setup_rx;
6042
6043 ixgbe_configure(adapter);
6044
6045 err = ixgbe_request_irq(adapter);
6046 if (err)
6047 goto err_req_irq;
6048
6049 /* Notify the stack of the actual queue counts. */
6050 if (adapter->num_rx_pools > 1)
6051 queues = adapter->num_rx_queues_per_pool;
6052 else
6053 queues = adapter->num_tx_queues;
6054
6055 err = netif_set_real_num_tx_queues(netdev, queues);
6056 if (err)
6057 goto err_set_queues;
6058
6059 if (adapter->num_rx_pools > 1 &&
6060 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
6061 queues = IXGBE_MAX_L2A_QUEUES;
6062 else
6063 queues = adapter->num_rx_queues;
6064 err = netif_set_real_num_rx_queues(netdev, queues);
6065 if (err)
6066 goto err_set_queues;
6067
6068 ixgbe_ptp_init(adapter);
6069
6070 ixgbe_up_complete(adapter);
6071
6072 ixgbe_clear_vxlan_port(adapter);
6073 #ifdef CONFIG_IXGBE_VXLAN
6074 vxlan_get_rx_port(netdev);
6075 #endif
6076
6077 return 0;
6078
6079 err_set_queues:
6080 ixgbe_free_irq(adapter);
6081 err_req_irq:
6082 ixgbe_free_all_rx_resources(adapter);
6083 if (hw->phy.ops.set_phy_power && !adapter->wol)
6084 hw->phy.ops.set_phy_power(&adapter->hw, false);
6085 err_setup_rx:
6086 ixgbe_free_all_tx_resources(adapter);
6087 err_setup_tx:
6088 ixgbe_reset(adapter);
6089
6090 return err;
6091 }
6092
6093 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
6094 {
6095 ixgbe_ptp_suspend(adapter);
6096
6097 if (adapter->hw.phy.ops.enter_lplu) {
6098 adapter->hw.phy.reset_disable = true;
6099 ixgbe_down(adapter);
6100 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
6101 adapter->hw.phy.reset_disable = false;
6102 } else {
6103 ixgbe_down(adapter);
6104 }
6105
6106 ixgbe_free_irq(adapter);
6107
6108 ixgbe_free_all_tx_resources(adapter);
6109 ixgbe_free_all_rx_resources(adapter);
6110 }
6111
6112 /**
6113 * ixgbe_close - Disables a network interface
6114 * @netdev: network interface device structure
6115 *
6116 * Returns 0, this is not allowed to fail
6117 *
6118 * The close entry point is called when an interface is de-activated
6119 * by the OS. The hardware is still under the drivers control, but
6120 * needs to be disabled. A global MAC reset is issued to stop the
6121 * hardware, and all transmit and receive resources are freed.
6122 **/
6123 int ixgbe_close(struct net_device *netdev)
6124 {
6125 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6126
6127 ixgbe_ptp_stop(adapter);
6128
6129 ixgbe_close_suspend(adapter);
6130
6131 ixgbe_fdir_filter_exit(adapter);
6132
6133 ixgbe_release_hw_control(adapter);
6134
6135 return 0;
6136 }
6137
6138 #ifdef CONFIG_PM
6139 static int ixgbe_resume(struct pci_dev *pdev)
6140 {
6141 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6142 struct net_device *netdev = adapter->netdev;
6143 u32 err;
6144
6145 adapter->hw.hw_addr = adapter->io_addr;
6146 pci_set_power_state(pdev, PCI_D0);
6147 pci_restore_state(pdev);
6148 /*
6149 * pci_restore_state clears dev->state_saved so call
6150 * pci_save_state to restore it.
6151 */
6152 pci_save_state(pdev);
6153
6154 err = pci_enable_device_mem(pdev);
6155 if (err) {
6156 e_dev_err("Cannot enable PCI device from suspend\n");
6157 return err;
6158 }
6159 smp_mb__before_atomic();
6160 clear_bit(__IXGBE_DISABLED, &adapter->state);
6161 pci_set_master(pdev);
6162
6163 pci_wake_from_d3(pdev, false);
6164
6165 ixgbe_reset(adapter);
6166
6167 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6168
6169 rtnl_lock();
6170 err = ixgbe_init_interrupt_scheme(adapter);
6171 if (!err && netif_running(netdev))
6172 err = ixgbe_open(netdev);
6173
6174 rtnl_unlock();
6175
6176 if (err)
6177 return err;
6178
6179 netif_device_attach(netdev);
6180
6181 return 0;
6182 }
6183 #endif /* CONFIG_PM */
6184
6185 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
6186 {
6187 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6188 struct net_device *netdev = adapter->netdev;
6189 struct ixgbe_hw *hw = &adapter->hw;
6190 u32 ctrl, fctrl;
6191 u32 wufc = adapter->wol;
6192 #ifdef CONFIG_PM
6193 int retval = 0;
6194 #endif
6195
6196 netif_device_detach(netdev);
6197
6198 rtnl_lock();
6199 if (netif_running(netdev))
6200 ixgbe_close_suspend(adapter);
6201 rtnl_unlock();
6202
6203 ixgbe_clear_interrupt_scheme(adapter);
6204
6205 #ifdef CONFIG_PM
6206 retval = pci_save_state(pdev);
6207 if (retval)
6208 return retval;
6209
6210 #endif
6211 if (hw->mac.ops.stop_link_on_d3)
6212 hw->mac.ops.stop_link_on_d3(hw);
6213
6214 if (wufc) {
6215 ixgbe_set_rx_mode(netdev);
6216
6217 /* enable the optics for 82599 SFP+ fiber as we can WoL */
6218 if (hw->mac.ops.enable_tx_laser)
6219 hw->mac.ops.enable_tx_laser(hw);
6220
6221 /* turn on all-multi mode if wake on multicast is enabled */
6222 if (wufc & IXGBE_WUFC_MC) {
6223 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6224 fctrl |= IXGBE_FCTRL_MPE;
6225 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
6226 }
6227
6228 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
6229 ctrl |= IXGBE_CTRL_GIO_DIS;
6230 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
6231
6232 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
6233 } else {
6234 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
6235 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
6236 }
6237
6238 switch (hw->mac.type) {
6239 case ixgbe_mac_82598EB:
6240 pci_wake_from_d3(pdev, false);
6241 break;
6242 case ixgbe_mac_82599EB:
6243 case ixgbe_mac_X540:
6244 case ixgbe_mac_X550:
6245 case ixgbe_mac_X550EM_x:
6246 pci_wake_from_d3(pdev, !!wufc);
6247 break;
6248 default:
6249 break;
6250 }
6251
6252 *enable_wake = !!wufc;
6253 if (hw->phy.ops.set_phy_power && !*enable_wake)
6254 hw->phy.ops.set_phy_power(hw, false);
6255
6256 ixgbe_release_hw_control(adapter);
6257
6258 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6259 pci_disable_device(pdev);
6260
6261 return 0;
6262 }
6263
6264 #ifdef CONFIG_PM
6265 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
6266 {
6267 int retval;
6268 bool wake;
6269
6270 retval = __ixgbe_shutdown(pdev, &wake);
6271 if (retval)
6272 return retval;
6273
6274 if (wake) {
6275 pci_prepare_to_sleep(pdev);
6276 } else {
6277 pci_wake_from_d3(pdev, false);
6278 pci_set_power_state(pdev, PCI_D3hot);
6279 }
6280
6281 return 0;
6282 }
6283 #endif /* CONFIG_PM */
6284
6285 static void ixgbe_shutdown(struct pci_dev *pdev)
6286 {
6287 bool wake;
6288
6289 __ixgbe_shutdown(pdev, &wake);
6290
6291 if (system_state == SYSTEM_POWER_OFF) {
6292 pci_wake_from_d3(pdev, wake);
6293 pci_set_power_state(pdev, PCI_D3hot);
6294 }
6295 }
6296
6297 /**
6298 * ixgbe_update_stats - Update the board statistics counters.
6299 * @adapter: board private structure
6300 **/
6301 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6302 {
6303 struct net_device *netdev = adapter->netdev;
6304 struct ixgbe_hw *hw = &adapter->hw;
6305 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6306 u64 total_mpc = 0;
6307 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
6308 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6309 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
6310 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
6311
6312 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6313 test_bit(__IXGBE_RESETTING, &adapter->state))
6314 return;
6315
6316 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
6317 u64 rsc_count = 0;
6318 u64 rsc_flush = 0;
6319 for (i = 0; i < adapter->num_rx_queues; i++) {
6320 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6321 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
6322 }
6323 adapter->rsc_total_count = rsc_count;
6324 adapter->rsc_total_flush = rsc_flush;
6325 }
6326
6327 for (i = 0; i < adapter->num_rx_queues; i++) {
6328 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6329 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6330 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6331 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
6332 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
6333 bytes += rx_ring->stats.bytes;
6334 packets += rx_ring->stats.packets;
6335 }
6336 adapter->non_eop_descs = non_eop_descs;
6337 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6338 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
6339 adapter->hw_csum_rx_error = hw_csum_rx_error;
6340 netdev->stats.rx_bytes = bytes;
6341 netdev->stats.rx_packets = packets;
6342
6343 bytes = 0;
6344 packets = 0;
6345 /* gather some stats to the adapter struct that are per queue */
6346 for (i = 0; i < adapter->num_tx_queues; i++) {
6347 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6348 restart_queue += tx_ring->tx_stats.restart_queue;
6349 tx_busy += tx_ring->tx_stats.tx_busy;
6350 bytes += tx_ring->stats.bytes;
6351 packets += tx_ring->stats.packets;
6352 }
6353 adapter->restart_queue = restart_queue;
6354 adapter->tx_busy = tx_busy;
6355 netdev->stats.tx_bytes = bytes;
6356 netdev->stats.tx_packets = packets;
6357
6358 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6359
6360 /* 8 register reads */
6361 for (i = 0; i < 8; i++) {
6362 /* for packet buffers not used, the register should read 0 */
6363 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6364 missed_rx += mpc;
6365 hwstats->mpc[i] += mpc;
6366 total_mpc += hwstats->mpc[i];
6367 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6368 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6369 switch (hw->mac.type) {
6370 case ixgbe_mac_82598EB:
6371 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6372 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6373 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
6374 hwstats->pxonrxc[i] +=
6375 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
6376 break;
6377 case ixgbe_mac_82599EB:
6378 case ixgbe_mac_X540:
6379 case ixgbe_mac_X550:
6380 case ixgbe_mac_X550EM_x:
6381 hwstats->pxonrxc[i] +=
6382 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
6383 break;
6384 default:
6385 break;
6386 }
6387 }
6388
6389 /*16 register reads */
6390 for (i = 0; i < 16; i++) {
6391 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6392 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6393 if ((hw->mac.type == ixgbe_mac_82599EB) ||
6394 (hw->mac.type == ixgbe_mac_X540) ||
6395 (hw->mac.type == ixgbe_mac_X550) ||
6396 (hw->mac.type == ixgbe_mac_X550EM_x)) {
6397 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6398 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6399 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6400 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6401 }
6402 }
6403
6404 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6405 /* work around hardware counting issue */
6406 hwstats->gprc -= missed_rx;
6407
6408 ixgbe_update_xoff_received(adapter);
6409
6410 /* 82598 hardware only has a 32 bit counter in the high register */
6411 switch (hw->mac.type) {
6412 case ixgbe_mac_82598EB:
6413 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
6414 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6415 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6416 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6417 break;
6418 case ixgbe_mac_X540:
6419 case ixgbe_mac_X550:
6420 case ixgbe_mac_X550EM_x:
6421 /* OS2BMC stats are X540 and later */
6422 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6423 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6424 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6425 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6426 case ixgbe_mac_82599EB:
6427 for (i = 0; i < 16; i++)
6428 adapter->hw_rx_no_dma_resources +=
6429 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
6430 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
6431 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
6432 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
6433 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
6434 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
6435 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
6436 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
6437 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6438 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6439 #ifdef IXGBE_FCOE
6440 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6441 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6442 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6443 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6444 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6445 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6446 /* Add up per cpu counters for total ddp aloc fail */
6447 if (adapter->fcoe.ddp_pool) {
6448 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6449 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6450 unsigned int cpu;
6451 u64 noddp = 0, noddp_ext_buff = 0;
6452 for_each_possible_cpu(cpu) {
6453 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6454 noddp += ddp_pool->noddp;
6455 noddp_ext_buff += ddp_pool->noddp_ext_buff;
6456 }
6457 hwstats->fcoe_noddp = noddp;
6458 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
6459 }
6460 #endif /* IXGBE_FCOE */
6461 break;
6462 default:
6463 break;
6464 }
6465 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
6466 hwstats->bprc += bprc;
6467 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
6468 if (hw->mac.type == ixgbe_mac_82598EB)
6469 hwstats->mprc -= bprc;
6470 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6471 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6472 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6473 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6474 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6475 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6476 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6477 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6478 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
6479 hwstats->lxontxc += lxon;
6480 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
6481 hwstats->lxofftxc += lxoff;
6482 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6483 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6484 /*
6485 * 82598 errata - tx of flow control packets is included in tx counters
6486 */
6487 xon_off_tot = lxon + lxoff;
6488 hwstats->gptc -= xon_off_tot;
6489 hwstats->mptc -= xon_off_tot;
6490 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6491 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6492 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6493 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6494 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6495 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6496 hwstats->ptc64 -= xon_off_tot;
6497 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6498 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6499 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6500 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6501 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6502 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
6503
6504 /* Fill out the OS statistics structure */
6505 netdev->stats.multicast = hwstats->mprc;
6506
6507 /* Rx Errors */
6508 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
6509 netdev->stats.rx_dropped = 0;
6510 netdev->stats.rx_length_errors = hwstats->rlec;
6511 netdev->stats.rx_crc_errors = hwstats->crcerrs;
6512 netdev->stats.rx_missed_errors = total_mpc;
6513 }
6514
6515 /**
6516 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
6517 * @adapter: pointer to the device adapter structure
6518 **/
6519 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
6520 {
6521 struct ixgbe_hw *hw = &adapter->hw;
6522 int i;
6523
6524 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6525 return;
6526
6527 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
6528
6529 /* if interface is down do nothing */
6530 if (test_bit(__IXGBE_DOWN, &adapter->state))
6531 return;
6532
6533 /* do nothing if we are not using signature filters */
6534 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6535 return;
6536
6537 adapter->fdir_overflow++;
6538
6539 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6540 for (i = 0; i < adapter->num_tx_queues; i++)
6541 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
6542 &(adapter->tx_ring[i]->state));
6543 /* re-enable flow director interrupts */
6544 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
6545 } else {
6546 e_err(probe, "failed to finish FDIR re-initialization, "
6547 "ignored adding FDIR ATR filters\n");
6548 }
6549 }
6550
6551 /**
6552 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
6553 * @adapter: pointer to the device adapter structure
6554 *
6555 * This function serves two purposes. First it strobes the interrupt lines
6556 * in order to make certain interrupts are occurring. Secondly it sets the
6557 * bits needed to check for TX hangs. As a result we should immediately
6558 * determine if a hang has occurred.
6559 */
6560 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
6561 {
6562 struct ixgbe_hw *hw = &adapter->hw;
6563 u64 eics = 0;
6564 int i;
6565
6566 /* If we're down, removing or resetting, just bail */
6567 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6568 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6569 test_bit(__IXGBE_RESETTING, &adapter->state))
6570 return;
6571
6572 /* Force detection of hung controller */
6573 if (netif_carrier_ok(adapter->netdev)) {
6574 for (i = 0; i < adapter->num_tx_queues; i++)
6575 set_check_for_tx_hang(adapter->tx_ring[i]);
6576 }
6577
6578 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6579 /*
6580 * for legacy and MSI interrupts don't set any bits
6581 * that are enabled for EIAM, because this operation
6582 * would set *both* EIMS and EICS for any bit in EIAM
6583 */
6584 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6585 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
6586 } else {
6587 /* get one bit for every active tx/rx interrupt vector */
6588 for (i = 0; i < adapter->num_q_vectors; i++) {
6589 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6590 if (qv->rx.ring || qv->tx.ring)
6591 eics |= ((u64)1 << i);
6592 }
6593 }
6594
6595 /* Cause software interrupt to ensure rings are cleaned */
6596 ixgbe_irq_rearm_queues(adapter, eics);
6597 }
6598
6599 /**
6600 * ixgbe_watchdog_update_link - update the link status
6601 * @adapter: pointer to the device adapter structure
6602 * @link_speed: pointer to a u32 to store the link_speed
6603 **/
6604 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
6605 {
6606 struct ixgbe_hw *hw = &adapter->hw;
6607 u32 link_speed = adapter->link_speed;
6608 bool link_up = adapter->link_up;
6609 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
6610
6611 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6612 return;
6613
6614 if (hw->mac.ops.check_link) {
6615 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6616 } else {
6617 /* always assume link is up, if no check link function */
6618 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6619 link_up = true;
6620 }
6621
6622 if (adapter->ixgbe_ieee_pfc)
6623 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6624
6625 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
6626 hw->mac.ops.fc_enable(hw);
6627 ixgbe_set_rx_drop_en(adapter);
6628 }
6629
6630 if (link_up ||
6631 time_after(jiffies, (adapter->link_check_timeout +
6632 IXGBE_TRY_LINK_TIMEOUT))) {
6633 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6634 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6635 IXGBE_WRITE_FLUSH(hw);
6636 }
6637
6638 adapter->link_up = link_up;
6639 adapter->link_speed = link_speed;
6640 }
6641
6642 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6643 {
6644 #ifdef CONFIG_IXGBE_DCB
6645 struct net_device *netdev = adapter->netdev;
6646 struct dcb_app app = {
6647 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6648 .protocol = 0,
6649 };
6650 u8 up = 0;
6651
6652 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6653 up = dcb_ieee_getapp_mask(netdev, &app);
6654
6655 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6656 #endif
6657 }
6658
6659 /**
6660 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6661 * print link up message
6662 * @adapter: pointer to the device adapter structure
6663 **/
6664 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
6665 {
6666 struct net_device *netdev = adapter->netdev;
6667 struct ixgbe_hw *hw = &adapter->hw;
6668 struct net_device *upper;
6669 struct list_head *iter;
6670 u32 link_speed = adapter->link_speed;
6671 const char *speed_str;
6672 bool flow_rx, flow_tx;
6673
6674 /* only continue if link was previously down */
6675 if (netif_carrier_ok(netdev))
6676 return;
6677
6678 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
6679
6680 switch (hw->mac.type) {
6681 case ixgbe_mac_82598EB: {
6682 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6683 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6684 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6685 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6686 }
6687 break;
6688 case ixgbe_mac_X540:
6689 case ixgbe_mac_X550:
6690 case ixgbe_mac_X550EM_x:
6691 case ixgbe_mac_82599EB: {
6692 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6693 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6694 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6695 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6696 }
6697 break;
6698 default:
6699 flow_tx = false;
6700 flow_rx = false;
6701 break;
6702 }
6703
6704 adapter->last_rx_ptp_check = jiffies;
6705
6706 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6707 ixgbe_ptp_start_cyclecounter(adapter);
6708
6709 switch (link_speed) {
6710 case IXGBE_LINK_SPEED_10GB_FULL:
6711 speed_str = "10 Gbps";
6712 break;
6713 case IXGBE_LINK_SPEED_2_5GB_FULL:
6714 speed_str = "2.5 Gbps";
6715 break;
6716 case IXGBE_LINK_SPEED_1GB_FULL:
6717 speed_str = "1 Gbps";
6718 break;
6719 case IXGBE_LINK_SPEED_100_FULL:
6720 speed_str = "100 Mbps";
6721 break;
6722 default:
6723 speed_str = "unknown speed";
6724 break;
6725 }
6726 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
6727 ((flow_rx && flow_tx) ? "RX/TX" :
6728 (flow_rx ? "RX" :
6729 (flow_tx ? "TX" : "None"))));
6730
6731 netif_carrier_on(netdev);
6732 ixgbe_check_vf_rate_limit(adapter);
6733
6734 /* enable transmits */
6735 netif_tx_wake_all_queues(adapter->netdev);
6736
6737 /* enable any upper devices */
6738 rtnl_lock();
6739 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6740 if (netif_is_macvlan(upper)) {
6741 struct macvlan_dev *vlan = netdev_priv(upper);
6742
6743 if (vlan->fwd_priv)
6744 netif_tx_wake_all_queues(upper);
6745 }
6746 }
6747 rtnl_unlock();
6748
6749 /* update the default user priority for VFs */
6750 ixgbe_update_default_up(adapter);
6751
6752 /* ping all the active vfs to let them know link has changed */
6753 ixgbe_ping_all_vfs(adapter);
6754 }
6755
6756 /**
6757 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6758 * print link down message
6759 * @adapter: pointer to the adapter structure
6760 **/
6761 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
6762 {
6763 struct net_device *netdev = adapter->netdev;
6764 struct ixgbe_hw *hw = &adapter->hw;
6765
6766 adapter->link_up = false;
6767 adapter->link_speed = 0;
6768
6769 /* only continue if link was up previously */
6770 if (!netif_carrier_ok(netdev))
6771 return;
6772
6773 /* poll for SFP+ cable when link is down */
6774 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6775 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6776
6777 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6778 ixgbe_ptp_start_cyclecounter(adapter);
6779
6780 e_info(drv, "NIC Link is Down\n");
6781 netif_carrier_off(netdev);
6782
6783 /* ping all the active vfs to let them know link has changed */
6784 ixgbe_ping_all_vfs(adapter);
6785 }
6786
6787 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6788 {
6789 int i;
6790
6791 for (i = 0; i < adapter->num_tx_queues; i++) {
6792 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6793
6794 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6795 return true;
6796 }
6797
6798 return false;
6799 }
6800
6801 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6802 {
6803 struct ixgbe_hw *hw = &adapter->hw;
6804 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6805 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6806
6807 int i, j;
6808
6809 if (!adapter->num_vfs)
6810 return false;
6811
6812 /* resetting the PF is only needed for MAC before X550 */
6813 if (hw->mac.type >= ixgbe_mac_X550)
6814 return false;
6815
6816 for (i = 0; i < adapter->num_vfs; i++) {
6817 for (j = 0; j < q_per_pool; j++) {
6818 u32 h, t;
6819
6820 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6821 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6822
6823 if (h != t)
6824 return true;
6825 }
6826 }
6827
6828 return false;
6829 }
6830
6831 /**
6832 * ixgbe_watchdog_flush_tx - flush queues on link down
6833 * @adapter: pointer to the device adapter structure
6834 **/
6835 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6836 {
6837 if (!netif_carrier_ok(adapter->netdev)) {
6838 if (ixgbe_ring_tx_pending(adapter) ||
6839 ixgbe_vf_tx_pending(adapter)) {
6840 /* We've lost link, so the controller stops DMA,
6841 * but we've got queued Tx work that's never going
6842 * to get done, so reset controller to flush Tx.
6843 * (Do the reset outside of interrupt context).
6844 */
6845 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
6846 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6847 }
6848 }
6849 }
6850
6851 #ifdef CONFIG_PCI_IOV
6852 static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6853 struct pci_dev *vfdev)
6854 {
6855 if (!pci_wait_for_pending_transaction(vfdev))
6856 e_dev_warn("Issuing VFLR with pending transactions\n");
6857
6858 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6859 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6860
6861 msleep(100);
6862 }
6863
6864 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6865 {
6866 struct ixgbe_hw *hw = &adapter->hw;
6867 struct pci_dev *pdev = adapter->pdev;
6868 unsigned int vf;
6869 u32 gpc;
6870
6871 if (!(netif_carrier_ok(adapter->netdev)))
6872 return;
6873
6874 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6875 if (gpc) /* If incrementing then no need for the check below */
6876 return;
6877 /* Check to see if a bad DMA write target from an errant or
6878 * malicious VF has caused a PCIe error. If so then we can
6879 * issue a VFLR to the offending VF(s) and then resume without
6880 * requesting a full slot reset.
6881 */
6882
6883 if (!pdev)
6884 return;
6885
6886 /* check status reg for all VFs owned by this PF */
6887 for (vf = 0; vf < adapter->num_vfs; ++vf) {
6888 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev;
6889 u16 status_reg;
6890
6891 if (!vfdev)
6892 continue;
6893 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6894 if (status_reg != IXGBE_FAILED_READ_CFG_WORD &&
6895 status_reg & PCI_STATUS_REC_MASTER_ABORT)
6896 ixgbe_issue_vf_flr(adapter, vfdev);
6897 }
6898 }
6899
6900 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6901 {
6902 u32 ssvpc;
6903
6904 /* Do not perform spoof check for 82598 or if not in IOV mode */
6905 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6906 adapter->num_vfs == 0)
6907 return;
6908
6909 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6910
6911 /*
6912 * ssvpc register is cleared on read, if zero then no
6913 * spoofed packets in the last interval.
6914 */
6915 if (!ssvpc)
6916 return;
6917
6918 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
6919 }
6920 #else
6921 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
6922 {
6923 }
6924
6925 static void
6926 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
6927 {
6928 }
6929 #endif /* CONFIG_PCI_IOV */
6930
6931
6932 /**
6933 * ixgbe_watchdog_subtask - check and bring link up
6934 * @adapter: pointer to the device adapter structure
6935 **/
6936 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6937 {
6938 /* if interface is down, removing or resetting, do nothing */
6939 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6940 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6941 test_bit(__IXGBE_RESETTING, &adapter->state))
6942 return;
6943
6944 ixgbe_watchdog_update_link(adapter);
6945
6946 if (adapter->link_up)
6947 ixgbe_watchdog_link_is_up(adapter);
6948 else
6949 ixgbe_watchdog_link_is_down(adapter);
6950
6951 ixgbe_check_for_bad_vf(adapter);
6952 ixgbe_spoof_check(adapter);
6953 ixgbe_update_stats(adapter);
6954
6955 ixgbe_watchdog_flush_tx(adapter);
6956 }
6957
6958 /**
6959 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6960 * @adapter: the ixgbe adapter structure
6961 **/
6962 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6963 {
6964 struct ixgbe_hw *hw = &adapter->hw;
6965 s32 err;
6966
6967 /* not searching for SFP so there is nothing to do here */
6968 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6969 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6970 return;
6971
6972 if (adapter->sfp_poll_time &&
6973 time_after(adapter->sfp_poll_time, jiffies))
6974 return; /* If not yet time to poll for SFP */
6975
6976 /* someone else is in init, wait until next service event */
6977 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6978 return;
6979
6980 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
6981
6982 err = hw->phy.ops.identify_sfp(hw);
6983 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6984 goto sfp_out;
6985
6986 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6987 /* If no cable is present, then we need to reset
6988 * the next time we find a good cable. */
6989 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6990 }
6991
6992 /* exit on error */
6993 if (err)
6994 goto sfp_out;
6995
6996 /* exit if reset not needed */
6997 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6998 goto sfp_out;
6999
7000 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
7001
7002 /*
7003 * A module may be identified correctly, but the EEPROM may not have
7004 * support for that module. setup_sfp() will fail in that case, so
7005 * we should not allow that module to load.
7006 */
7007 if (hw->mac.type == ixgbe_mac_82598EB)
7008 err = hw->phy.ops.reset(hw);
7009 else
7010 err = hw->mac.ops.setup_sfp(hw);
7011
7012 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7013 goto sfp_out;
7014
7015 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
7016 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
7017
7018 sfp_out:
7019 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7020
7021 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
7022 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
7023 e_dev_err("failed to initialize because an unsupported "
7024 "SFP+ module type was detected.\n");
7025 e_dev_err("Reload the driver after installing a "
7026 "supported module.\n");
7027 unregister_netdev(adapter->netdev);
7028 }
7029 }
7030
7031 /**
7032 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
7033 * @adapter: the ixgbe adapter structure
7034 **/
7035 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
7036 {
7037 struct ixgbe_hw *hw = &adapter->hw;
7038 u32 speed;
7039 bool autoneg = false;
7040
7041 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
7042 return;
7043
7044 /* someone else is in init, wait until next service event */
7045 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7046 return;
7047
7048 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
7049
7050 speed = hw->phy.autoneg_advertised;
7051 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
7052 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
7053
7054 /* setup the highest link when no autoneg */
7055 if (!autoneg) {
7056 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
7057 speed = IXGBE_LINK_SPEED_10GB_FULL;
7058 }
7059 }
7060
7061 if (hw->mac.ops.setup_link)
7062 hw->mac.ops.setup_link(hw, speed, true);
7063
7064 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
7065 adapter->link_check_timeout = jiffies;
7066 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7067 }
7068
7069 /**
7070 * ixgbe_service_timer - Timer Call-back
7071 * @data: pointer to adapter cast into an unsigned long
7072 **/
7073 static void ixgbe_service_timer(unsigned long data)
7074 {
7075 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
7076 unsigned long next_event_offset;
7077
7078 /* poll faster when waiting for link */
7079 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
7080 next_event_offset = HZ / 10;
7081 else
7082 next_event_offset = HZ * 2;
7083
7084 /* Reset the timer */
7085 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
7086
7087 ixgbe_service_event_schedule(adapter);
7088 }
7089
7090 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
7091 {
7092 struct ixgbe_hw *hw = &adapter->hw;
7093 u32 status;
7094
7095 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
7096 return;
7097
7098 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
7099
7100 if (!hw->phy.ops.handle_lasi)
7101 return;
7102
7103 status = hw->phy.ops.handle_lasi(&adapter->hw);
7104 if (status != IXGBE_ERR_OVERTEMP)
7105 return;
7106
7107 e_crit(drv, "%s\n", ixgbe_overheat_msg);
7108 }
7109
7110 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
7111 {
7112 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
7113 return;
7114
7115 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
7116
7117 /* If we're already down, removing or resetting, just bail */
7118 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7119 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7120 test_bit(__IXGBE_RESETTING, &adapter->state))
7121 return;
7122
7123 ixgbe_dump(adapter);
7124 netdev_err(adapter->netdev, "Reset adapter\n");
7125 adapter->tx_timeout_count++;
7126
7127 rtnl_lock();
7128 ixgbe_reinit_locked(adapter);
7129 rtnl_unlock();
7130 }
7131
7132 /**
7133 * ixgbe_service_task - manages and runs subtasks
7134 * @work: pointer to work_struct containing our data
7135 **/
7136 static void ixgbe_service_task(struct work_struct *work)
7137 {
7138 struct ixgbe_adapter *adapter = container_of(work,
7139 struct ixgbe_adapter,
7140 service_task);
7141 if (ixgbe_removed(adapter->hw.hw_addr)) {
7142 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
7143 rtnl_lock();
7144 ixgbe_down(adapter);
7145 rtnl_unlock();
7146 }
7147 ixgbe_service_event_complete(adapter);
7148 return;
7149 }
7150 #ifdef CONFIG_IXGBE_VXLAN
7151 if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) {
7152 adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED;
7153 vxlan_get_rx_port(adapter->netdev);
7154 }
7155 #endif /* CONFIG_IXGBE_VXLAN */
7156 ixgbe_reset_subtask(adapter);
7157 ixgbe_phy_interrupt_subtask(adapter);
7158 ixgbe_sfp_detection_subtask(adapter);
7159 ixgbe_sfp_link_config_subtask(adapter);
7160 ixgbe_check_overtemp_subtask(adapter);
7161 ixgbe_watchdog_subtask(adapter);
7162 ixgbe_fdir_reinit_subtask(adapter);
7163 ixgbe_check_hang_subtask(adapter);
7164
7165 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
7166 ixgbe_ptp_overflow_check(adapter);
7167 ixgbe_ptp_rx_hang(adapter);
7168 }
7169
7170 ixgbe_service_event_complete(adapter);
7171 }
7172
7173 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
7174 struct ixgbe_tx_buffer *first,
7175 u8 *hdr_len)
7176 {
7177 struct sk_buff *skb = first->skb;
7178 u32 vlan_macip_lens, type_tucmd;
7179 u32 mss_l4len_idx, l4len;
7180 int err;
7181
7182 if (skb->ip_summed != CHECKSUM_PARTIAL)
7183 return 0;
7184
7185 if (!skb_is_gso(skb))
7186 return 0;
7187
7188 err = skb_cow_head(skb, 0);
7189 if (err < 0)
7190 return err;
7191
7192 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
7193 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7194
7195 if (first->protocol == htons(ETH_P_IP)) {
7196 struct iphdr *iph = ip_hdr(skb);
7197 iph->tot_len = 0;
7198 iph->check = 0;
7199 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7200 iph->daddr, 0,
7201 IPPROTO_TCP,
7202 0);
7203 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
7204 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7205 IXGBE_TX_FLAGS_CSUM |
7206 IXGBE_TX_FLAGS_IPV4;
7207 } else if (skb_is_gso_v6(skb)) {
7208 ipv6_hdr(skb)->payload_len = 0;
7209 tcp_hdr(skb)->check =
7210 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
7211 &ipv6_hdr(skb)->daddr,
7212 0, IPPROTO_TCP, 0);
7213 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7214 IXGBE_TX_FLAGS_CSUM;
7215 }
7216
7217 /* compute header lengths */
7218 l4len = tcp_hdrlen(skb);
7219 *hdr_len = skb_transport_offset(skb) + l4len;
7220
7221 /* update gso size and bytecount with header size */
7222 first->gso_segs = skb_shinfo(skb)->gso_segs;
7223 first->bytecount += (first->gso_segs - 1) * *hdr_len;
7224
7225 /* mss_l4len_id: use 0 as index for TSO */
7226 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
7227 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
7228
7229 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
7230 vlan_macip_lens = skb_network_header_len(skb);
7231 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
7232 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
7233
7234 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
7235 mss_l4len_idx);
7236
7237 return 1;
7238 }
7239
7240 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb)
7241 {
7242 unsigned int offset = 0;
7243
7244 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
7245
7246 return offset == skb_checksum_start_offset(skb);
7247 }
7248
7249 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
7250 struct ixgbe_tx_buffer *first)
7251 {
7252 struct sk_buff *skb = first->skb;
7253 u32 vlan_macip_lens = 0;
7254 u32 type_tucmd = 0;
7255
7256 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7257 csum_failed:
7258 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN |
7259 IXGBE_TX_FLAGS_CC)))
7260 return;
7261 goto no_csum;
7262 }
7263
7264 switch (skb->csum_offset) {
7265 case offsetof(struct tcphdr, check):
7266 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7267 /* fall through */
7268 case offsetof(struct udphdr, check):
7269 break;
7270 case offsetof(struct sctphdr, checksum):
7271 /* validate that this is actually an SCTP request */
7272 if (((first->protocol == htons(ETH_P_IP)) &&
7273 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
7274 ((first->protocol == htons(ETH_P_IPV6)) &&
7275 ixgbe_ipv6_csum_is_sctp(skb))) {
7276 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP;
7277 break;
7278 }
7279 /* fall through */
7280 default:
7281 skb_checksum_help(skb);
7282 goto csum_failed;
7283 }
7284
7285 /* update TX checksum flag */
7286 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7287 vlan_macip_lens = skb_checksum_start_offset(skb) -
7288 skb_network_offset(skb);
7289 no_csum:
7290 /* vlan_macip_lens: MACLEN, VLAN tag */
7291 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
7292 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
7293
7294 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 0);
7295 }
7296
7297 #define IXGBE_SET_FLAG(_input, _flag, _result) \
7298 ((_flag <= _result) ? \
7299 ((u32)(_input & _flag) * (_result / _flag)) : \
7300 ((u32)(_input & _flag) / (_flag / _result)))
7301
7302 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
7303 {
7304 /* set type for advanced descriptor with frame checksum insertion */
7305 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7306 IXGBE_ADVTXD_DCMD_DEXT |
7307 IXGBE_ADVTXD_DCMD_IFCS;
7308
7309 /* set HW vlan bit if vlan is present */
7310 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7311 IXGBE_ADVTXD_DCMD_VLE);
7312
7313 /* set segmentation enable bits for TSO/FSO */
7314 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7315 IXGBE_ADVTXD_DCMD_TSE);
7316
7317 /* set timestamp bit if present */
7318 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7319 IXGBE_ADVTXD_MAC_TSTAMP);
7320
7321 /* insert frame checksum */
7322 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
7323
7324 return cmd_type;
7325 }
7326
7327 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7328 u32 tx_flags, unsigned int paylen)
7329 {
7330 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
7331
7332 /* enable L4 checksum for TSO and TX checksum offload */
7333 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7334 IXGBE_TX_FLAGS_CSUM,
7335 IXGBE_ADVTXD_POPTS_TXSM);
7336
7337 /* enble IPv4 checksum for TSO */
7338 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7339 IXGBE_TX_FLAGS_IPV4,
7340 IXGBE_ADVTXD_POPTS_IXSM);
7341
7342 /*
7343 * Check Context must be set if Tx switch is enabled, which it
7344 * always is for case where virtual functions are running
7345 */
7346 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7347 IXGBE_TX_FLAGS_CC,
7348 IXGBE_ADVTXD_CC);
7349
7350 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
7351 }
7352
7353 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7354 {
7355 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7356
7357 /* Herbert's original patch had:
7358 * smp_mb__after_netif_stop_queue();
7359 * but since that doesn't exist yet, just open code it.
7360 */
7361 smp_mb();
7362
7363 /* We need to check again in a case another CPU has just
7364 * made room available.
7365 */
7366 if (likely(ixgbe_desc_unused(tx_ring) < size))
7367 return -EBUSY;
7368
7369 /* A reprieve! - use start_queue because it doesn't call schedule */
7370 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7371 ++tx_ring->tx_stats.restart_queue;
7372 return 0;
7373 }
7374
7375 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7376 {
7377 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7378 return 0;
7379
7380 return __ixgbe_maybe_stop_tx(tx_ring, size);
7381 }
7382
7383 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7384 IXGBE_TXD_CMD_RS)
7385
7386 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
7387 struct ixgbe_tx_buffer *first,
7388 const u8 hdr_len)
7389 {
7390 struct sk_buff *skb = first->skb;
7391 struct ixgbe_tx_buffer *tx_buffer;
7392 union ixgbe_adv_tx_desc *tx_desc;
7393 struct skb_frag_struct *frag;
7394 dma_addr_t dma;
7395 unsigned int data_len, size;
7396 u32 tx_flags = first->tx_flags;
7397 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
7398 u16 i = tx_ring->next_to_use;
7399
7400 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7401
7402 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7403
7404 size = skb_headlen(skb);
7405 data_len = skb->data_len;
7406
7407 #ifdef IXGBE_FCOE
7408 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
7409 if (data_len < sizeof(struct fcoe_crc_eof)) {
7410 size -= sizeof(struct fcoe_crc_eof) - data_len;
7411 data_len = 0;
7412 } else {
7413 data_len -= sizeof(struct fcoe_crc_eof);
7414 }
7415 }
7416
7417 #endif
7418 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
7419
7420 tx_buffer = first;
7421
7422 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7423 if (dma_mapping_error(tx_ring->dev, dma))
7424 goto dma_error;
7425
7426 /* record length, and DMA address */
7427 dma_unmap_len_set(tx_buffer, len, size);
7428 dma_unmap_addr_set(tx_buffer, dma, dma);
7429
7430 tx_desc->read.buffer_addr = cpu_to_le64(dma);
7431
7432 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
7433 tx_desc->read.cmd_type_len =
7434 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
7435
7436 i++;
7437 tx_desc++;
7438 if (i == tx_ring->count) {
7439 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7440 i = 0;
7441 }
7442 tx_desc->read.olinfo_status = 0;
7443
7444 dma += IXGBE_MAX_DATA_PER_TXD;
7445 size -= IXGBE_MAX_DATA_PER_TXD;
7446
7447 tx_desc->read.buffer_addr = cpu_to_le64(dma);
7448 }
7449
7450 if (likely(!data_len))
7451 break;
7452
7453 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
7454
7455 i++;
7456 tx_desc++;
7457 if (i == tx_ring->count) {
7458 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7459 i = 0;
7460 }
7461 tx_desc->read.olinfo_status = 0;
7462
7463 #ifdef IXGBE_FCOE
7464 size = min_t(unsigned int, data_len, skb_frag_size(frag));
7465 #else
7466 size = skb_frag_size(frag);
7467 #endif
7468 data_len -= size;
7469
7470 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7471 DMA_TO_DEVICE);
7472
7473 tx_buffer = &tx_ring->tx_buffer_info[i];
7474 }
7475
7476 /* write last descriptor with RS and EOP bits */
7477 cmd_type |= size | IXGBE_TXD_CMD;
7478 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
7479
7480 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
7481
7482 /* set the timestamp */
7483 first->time_stamp = jiffies;
7484
7485 /*
7486 * Force memory writes to complete before letting h/w know there
7487 * are new descriptors to fetch. (Only applicable for weak-ordered
7488 * memory model archs, such as IA-64).
7489 *
7490 * We also need this memory barrier to make certain all of the
7491 * status bits have been updated before next_to_watch is written.
7492 */
7493 wmb();
7494
7495 /* set next_to_watch value indicating a packet is present */
7496 first->next_to_watch = tx_desc;
7497
7498 i++;
7499 if (i == tx_ring->count)
7500 i = 0;
7501
7502 tx_ring->next_to_use = i;
7503
7504 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7505
7506 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
7507 writel(i, tx_ring->tail);
7508
7509 /* we need this if more than one processor can write to our tail
7510 * at a time, it synchronizes IO on IA64/Altix systems
7511 */
7512 mmiowb();
7513 }
7514
7515 return;
7516 dma_error:
7517 dev_err(tx_ring->dev, "TX DMA map failed\n");
7518
7519 /* clear dma mappings for failed tx_buffer_info map */
7520 for (;;) {
7521 tx_buffer = &tx_ring->tx_buffer_info[i];
7522 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7523 if (tx_buffer == first)
7524 break;
7525 if (i == 0)
7526 i = tx_ring->count;
7527 i--;
7528 }
7529
7530 tx_ring->next_to_use = i;
7531 }
7532
7533 static void ixgbe_atr(struct ixgbe_ring *ring,
7534 struct ixgbe_tx_buffer *first)
7535 {
7536 struct ixgbe_q_vector *q_vector = ring->q_vector;
7537 union ixgbe_atr_hash_dword input = { .dword = 0 };
7538 union ixgbe_atr_hash_dword common = { .dword = 0 };
7539 union {
7540 unsigned char *network;
7541 struct iphdr *ipv4;
7542 struct ipv6hdr *ipv6;
7543 } hdr;
7544 struct tcphdr *th;
7545 unsigned int hlen;
7546 struct sk_buff *skb;
7547 __be16 vlan_id;
7548 int l4_proto;
7549
7550 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7551 if (!q_vector)
7552 return;
7553
7554 /* do nothing if sampling is disabled */
7555 if (!ring->atr_sample_rate)
7556 return;
7557
7558 ring->atr_count++;
7559
7560 /* currently only IPv4/IPv6 with TCP is supported */
7561 if ((first->protocol != htons(ETH_P_IP)) &&
7562 (first->protocol != htons(ETH_P_IPV6)))
7563 return;
7564
7565 /* snag network header to get L4 type and address */
7566 skb = first->skb;
7567 hdr.network = skb_network_header(skb);
7568 #ifdef CONFIG_IXGBE_VXLAN
7569 if (skb->encapsulation &&
7570 first->protocol == htons(ETH_P_IP) &&
7571 hdr.ipv4->protocol != IPPROTO_UDP) {
7572 struct ixgbe_adapter *adapter = q_vector->adapter;
7573
7574 /* verify the port is recognized as VXLAN */
7575 if (adapter->vxlan_port &&
7576 udp_hdr(skb)->dest == adapter->vxlan_port)
7577 hdr.network = skb_inner_network_header(skb);
7578 }
7579 #endif /* CONFIG_IXGBE_VXLAN */
7580
7581 /* Currently only IPv4/IPv6 with TCP is supported */
7582 switch (hdr.ipv4->version) {
7583 case IPVERSION:
7584 /* access ihl as u8 to avoid unaligned access on ia64 */
7585 hlen = (hdr.network[0] & 0x0F) << 2;
7586 l4_proto = hdr.ipv4->protocol;
7587 break;
7588 case 6:
7589 hlen = hdr.network - skb->data;
7590 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL);
7591 hlen -= hdr.network - skb->data;
7592 break;
7593 default:
7594 return;
7595 }
7596
7597 if (l4_proto != IPPROTO_TCP)
7598 return;
7599
7600 th = (struct tcphdr *)(hdr.network + hlen);
7601
7602 /* skip this packet since the socket is closing */
7603 if (th->fin)
7604 return;
7605
7606 /* sample on all syn packets or once every atr sample count */
7607 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7608 return;
7609
7610 /* reset sample count */
7611 ring->atr_count = 0;
7612
7613 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
7614
7615 /*
7616 * src and dst are inverted, think how the receiver sees them
7617 *
7618 * The input is broken into two sections, a non-compressed section
7619 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7620 * is XORed together and stored in the compressed dword.
7621 */
7622 input.formatted.vlan_id = vlan_id;
7623
7624 /*
7625 * since src port and flex bytes occupy the same word XOR them together
7626 * and write the value to source port portion of compressed dword
7627 */
7628 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
7629 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
7630 else
7631 common.port.src ^= th->dest ^ first->protocol;
7632 common.port.dst ^= th->source;
7633
7634 switch (hdr.ipv4->version) {
7635 case IPVERSION:
7636 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7637 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7638 break;
7639 case 6:
7640 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7641 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7642 hdr.ipv6->saddr.s6_addr32[1] ^
7643 hdr.ipv6->saddr.s6_addr32[2] ^
7644 hdr.ipv6->saddr.s6_addr32[3] ^
7645 hdr.ipv6->daddr.s6_addr32[0] ^
7646 hdr.ipv6->daddr.s6_addr32[1] ^
7647 hdr.ipv6->daddr.s6_addr32[2] ^
7648 hdr.ipv6->daddr.s6_addr32[3];
7649 break;
7650 default:
7651 break;
7652 }
7653
7654 if (hdr.network != skb_network_header(skb))
7655 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
7656
7657 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
7658 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7659 input, common, ring->queue_index);
7660 }
7661
7662 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
7663 void *accel_priv, select_queue_fallback_t fallback)
7664 {
7665 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7666 #ifdef IXGBE_FCOE
7667 struct ixgbe_adapter *adapter;
7668 struct ixgbe_ring_feature *f;
7669 int txq;
7670 #endif
7671
7672 if (fwd_adapter)
7673 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7674
7675 #ifdef IXGBE_FCOE
7676
7677 /*
7678 * only execute the code below if protocol is FCoE
7679 * or FIP and we have FCoE enabled on the adapter
7680 */
7681 switch (vlan_get_protocol(skb)) {
7682 case htons(ETH_P_FCOE):
7683 case htons(ETH_P_FIP):
7684 adapter = netdev_priv(dev);
7685
7686 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7687 break;
7688 default:
7689 return fallback(dev, skb);
7690 }
7691
7692 f = &adapter->ring_feature[RING_F_FCOE];
7693
7694 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7695 smp_processor_id();
7696
7697 while (txq >= f->indices)
7698 txq -= f->indices;
7699
7700 return txq + f->offset;
7701 #else
7702 return fallback(dev, skb);
7703 #endif
7704 }
7705
7706 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
7707 struct ixgbe_adapter *adapter,
7708 struct ixgbe_ring *tx_ring)
7709 {
7710 struct ixgbe_tx_buffer *first;
7711 int tso;
7712 u32 tx_flags = 0;
7713 unsigned short f;
7714 u16 count = TXD_USE_COUNT(skb_headlen(skb));
7715 __be16 protocol = skb->protocol;
7716 u8 hdr_len = 0;
7717
7718 /*
7719 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
7720 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
7721 * + 2 desc gap to keep tail from touching head,
7722 * + 1 desc for context descriptor,
7723 * otherwise try next time
7724 */
7725 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7726 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7727
7728 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7729 tx_ring->tx_stats.tx_busy++;
7730 return NETDEV_TX_BUSY;
7731 }
7732
7733 /* record the location of the first descriptor for this packet */
7734 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7735 first->skb = skb;
7736 first->bytecount = skb->len;
7737 first->gso_segs = 1;
7738
7739 /* if we have a HW VLAN tag being added default to the HW one */
7740 if (skb_vlan_tag_present(skb)) {
7741 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7742 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7743 /* else if it is a SW VLAN check the next protocol and store the tag */
7744 } else if (protocol == htons(ETH_P_8021Q)) {
7745 struct vlan_hdr *vhdr, _vhdr;
7746 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7747 if (!vhdr)
7748 goto out_drop;
7749
7750 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7751 IXGBE_TX_FLAGS_VLAN_SHIFT;
7752 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7753 }
7754 protocol = vlan_get_protocol(skb);
7755
7756 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7757 adapter->ptp_clock &&
7758 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7759 &adapter->state)) {
7760 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7761 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
7762
7763 /* schedule check for Tx timestamp */
7764 adapter->ptp_tx_skb = skb_get(skb);
7765 adapter->ptp_tx_start = jiffies;
7766 schedule_work(&adapter->ptp_tx_work);
7767 }
7768
7769 skb_tx_timestamp(skb);
7770
7771 #ifdef CONFIG_PCI_IOV
7772 /*
7773 * Use the l2switch_enable flag - would be false if the DMA
7774 * Tx switch had been disabled.
7775 */
7776 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7777 tx_flags |= IXGBE_TX_FLAGS_CC;
7778
7779 #endif
7780 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
7781 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7782 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7783 (skb->priority != TC_PRIO_CONTROL))) {
7784 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
7785 tx_flags |= (skb->priority & 0x7) <<
7786 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
7787 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7788 struct vlan_ethhdr *vhdr;
7789
7790 if (skb_cow_head(skb, 0))
7791 goto out_drop;
7792 vhdr = (struct vlan_ethhdr *)skb->data;
7793 vhdr->h_vlan_TCI = htons(tx_flags >>
7794 IXGBE_TX_FLAGS_VLAN_SHIFT);
7795 } else {
7796 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7797 }
7798 }
7799
7800 /* record initial flags and protocol */
7801 first->tx_flags = tx_flags;
7802 first->protocol = protocol;
7803
7804 #ifdef IXGBE_FCOE
7805 /* setup tx offload for FCoE */
7806 if ((protocol == htons(ETH_P_FCOE)) &&
7807 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
7808 tso = ixgbe_fso(tx_ring, first, &hdr_len);
7809 if (tso < 0)
7810 goto out_drop;
7811
7812 goto xmit_fcoe;
7813 }
7814
7815 #endif /* IXGBE_FCOE */
7816 tso = ixgbe_tso(tx_ring, first, &hdr_len);
7817 if (tso < 0)
7818 goto out_drop;
7819 else if (!tso)
7820 ixgbe_tx_csum(tx_ring, first);
7821
7822 /* add the ATR filter if ATR is on */
7823 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7824 ixgbe_atr(tx_ring, first);
7825
7826 #ifdef IXGBE_FCOE
7827 xmit_fcoe:
7828 #endif /* IXGBE_FCOE */
7829 ixgbe_tx_map(tx_ring, first, hdr_len);
7830
7831 return NETDEV_TX_OK;
7832
7833 out_drop:
7834 dev_kfree_skb_any(first->skb);
7835 first->skb = NULL;
7836
7837 return NETDEV_TX_OK;
7838 }
7839
7840 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7841 struct net_device *netdev,
7842 struct ixgbe_ring *ring)
7843 {
7844 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7845 struct ixgbe_ring *tx_ring;
7846
7847 /*
7848 * The minimum packet size for olinfo paylen is 17 so pad the skb
7849 * in order to meet this minimum size requirement.
7850 */
7851 if (skb_put_padto(skb, 17))
7852 return NETDEV_TX_OK;
7853
7854 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7855
7856 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
7857 }
7858
7859 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7860 struct net_device *netdev)
7861 {
7862 return __ixgbe_xmit_frame(skb, netdev, NULL);
7863 }
7864
7865 /**
7866 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7867 * @netdev: network interface device structure
7868 * @p: pointer to an address structure
7869 *
7870 * Returns 0 on success, negative on failure
7871 **/
7872 static int ixgbe_set_mac(struct net_device *netdev, void *p)
7873 {
7874 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7875 struct ixgbe_hw *hw = &adapter->hw;
7876 struct sockaddr *addr = p;
7877
7878 if (!is_valid_ether_addr(addr->sa_data))
7879 return -EADDRNOTAVAIL;
7880
7881 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
7882 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
7883
7884 ixgbe_mac_set_default_filter(adapter);
7885
7886 return 0;
7887 }
7888
7889 static int
7890 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7891 {
7892 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7893 struct ixgbe_hw *hw = &adapter->hw;
7894 u16 value;
7895 int rc;
7896
7897 if (prtad != hw->phy.mdio.prtad)
7898 return -EINVAL;
7899 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7900 if (!rc)
7901 rc = value;
7902 return rc;
7903 }
7904
7905 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7906 u16 addr, u16 value)
7907 {
7908 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7909 struct ixgbe_hw *hw = &adapter->hw;
7910
7911 if (prtad != hw->phy.mdio.prtad)
7912 return -EINVAL;
7913 return hw->phy.ops.write_reg(hw, addr, devad, value);
7914 }
7915
7916 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7917 {
7918 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7919
7920 switch (cmd) {
7921 case SIOCSHWTSTAMP:
7922 return ixgbe_ptp_set_ts_config(adapter, req);
7923 case SIOCGHWTSTAMP:
7924 return ixgbe_ptp_get_ts_config(adapter, req);
7925 default:
7926 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7927 }
7928 }
7929
7930 /**
7931 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
7932 * netdev->dev_addrs
7933 * @netdev: network interface device structure
7934 *
7935 * Returns non-zero on failure
7936 **/
7937 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7938 {
7939 int err = 0;
7940 struct ixgbe_adapter *adapter = netdev_priv(dev);
7941 struct ixgbe_hw *hw = &adapter->hw;
7942
7943 if (is_valid_ether_addr(hw->mac.san_addr)) {
7944 rtnl_lock();
7945 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
7946 rtnl_unlock();
7947
7948 /* update SAN MAC vmdq pool selection */
7949 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
7950 }
7951 return err;
7952 }
7953
7954 /**
7955 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7956 * netdev->dev_addrs
7957 * @netdev: network interface device structure
7958 *
7959 * Returns non-zero on failure
7960 **/
7961 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7962 {
7963 int err = 0;
7964 struct ixgbe_adapter *adapter = netdev_priv(dev);
7965 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7966
7967 if (is_valid_ether_addr(mac->san_addr)) {
7968 rtnl_lock();
7969 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7970 rtnl_unlock();
7971 }
7972 return err;
7973 }
7974
7975 #ifdef CONFIG_NET_POLL_CONTROLLER
7976 /*
7977 * Polling 'interrupt' - used by things like netconsole to send skbs
7978 * without having to re-enable interrupts. It's not called while
7979 * the interrupt routine is executing.
7980 */
7981 static void ixgbe_netpoll(struct net_device *netdev)
7982 {
7983 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7984 int i;
7985
7986 /* if interface is down do nothing */
7987 if (test_bit(__IXGBE_DOWN, &adapter->state))
7988 return;
7989
7990 /* loop through and schedule all active queues */
7991 for (i = 0; i < adapter->num_q_vectors; i++)
7992 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
7993 }
7994
7995 #endif
7996 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7997 struct rtnl_link_stats64 *stats)
7998 {
7999 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8000 int i;
8001
8002 rcu_read_lock();
8003 for (i = 0; i < adapter->num_rx_queues; i++) {
8004 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
8005 u64 bytes, packets;
8006 unsigned int start;
8007
8008 if (ring) {
8009 do {
8010 start = u64_stats_fetch_begin_irq(&ring->syncp);
8011 packets = ring->stats.packets;
8012 bytes = ring->stats.bytes;
8013 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
8014 stats->rx_packets += packets;
8015 stats->rx_bytes += bytes;
8016 }
8017 }
8018
8019 for (i = 0; i < adapter->num_tx_queues; i++) {
8020 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
8021 u64 bytes, packets;
8022 unsigned int start;
8023
8024 if (ring) {
8025 do {
8026 start = u64_stats_fetch_begin_irq(&ring->syncp);
8027 packets = ring->stats.packets;
8028 bytes = ring->stats.bytes;
8029 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
8030 stats->tx_packets += packets;
8031 stats->tx_bytes += bytes;
8032 }
8033 }
8034 rcu_read_unlock();
8035 /* following stats updated by ixgbe_watchdog_task() */
8036 stats->multicast = netdev->stats.multicast;
8037 stats->rx_errors = netdev->stats.rx_errors;
8038 stats->rx_length_errors = netdev->stats.rx_length_errors;
8039 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
8040 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
8041 return stats;
8042 }
8043
8044 #ifdef CONFIG_IXGBE_DCB
8045 /**
8046 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
8047 * @adapter: pointer to ixgbe_adapter
8048 * @tc: number of traffic classes currently enabled
8049 *
8050 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
8051 * 802.1Q priority maps to a packet buffer that exists.
8052 */
8053 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
8054 {
8055 struct ixgbe_hw *hw = &adapter->hw;
8056 u32 reg, rsave;
8057 int i;
8058
8059 /* 82598 have a static priority to TC mapping that can not
8060 * be changed so no validation is needed.
8061 */
8062 if (hw->mac.type == ixgbe_mac_82598EB)
8063 return;
8064
8065 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
8066 rsave = reg;
8067
8068 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
8069 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
8070
8071 /* If up2tc is out of bounds default to zero */
8072 if (up2tc > tc)
8073 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
8074 }
8075
8076 if (reg != rsave)
8077 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
8078
8079 return;
8080 }
8081
8082 /**
8083 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
8084 * @adapter: Pointer to adapter struct
8085 *
8086 * Populate the netdev user priority to tc map
8087 */
8088 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
8089 {
8090 struct net_device *dev = adapter->netdev;
8091 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
8092 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
8093 u8 prio;
8094
8095 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
8096 u8 tc = 0;
8097
8098 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
8099 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
8100 else if (ets)
8101 tc = ets->prio_tc[prio];
8102
8103 netdev_set_prio_tc_map(dev, prio, tc);
8104 }
8105 }
8106
8107 #endif /* CONFIG_IXGBE_DCB */
8108 /**
8109 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8110 *
8111 * @netdev: net device to configure
8112 * @tc: number of traffic classes to enable
8113 */
8114 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
8115 {
8116 struct ixgbe_adapter *adapter = netdev_priv(dev);
8117 struct ixgbe_hw *hw = &adapter->hw;
8118 bool pools;
8119
8120 /* Hardware supports up to 8 traffic classes */
8121 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
8122 return -EINVAL;
8123
8124 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
8125 return -EINVAL;
8126
8127 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
8128 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
8129 return -EBUSY;
8130
8131 /* Hardware has to reinitialize queues and interrupts to
8132 * match packet buffer alignment. Unfortunately, the
8133 * hardware is not flexible enough to do this dynamically.
8134 */
8135 if (netif_running(dev))
8136 ixgbe_close(dev);
8137 else
8138 ixgbe_reset(adapter);
8139
8140 ixgbe_clear_interrupt_scheme(adapter);
8141
8142 #ifdef CONFIG_IXGBE_DCB
8143 if (tc) {
8144 netdev_set_num_tc(dev, tc);
8145 ixgbe_set_prio_tc_map(adapter);
8146
8147 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
8148
8149 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
8150 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
8151 adapter->hw.fc.requested_mode = ixgbe_fc_none;
8152 }
8153 } else {
8154 netdev_reset_tc(dev);
8155
8156 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8157 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
8158
8159 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
8160
8161 adapter->temp_dcb_cfg.pfc_mode_enable = false;
8162 adapter->dcb_cfg.pfc_mode_enable = false;
8163 }
8164
8165 ixgbe_validate_rtr(adapter, tc);
8166
8167 #endif /* CONFIG_IXGBE_DCB */
8168 ixgbe_init_interrupt_scheme(adapter);
8169
8170 if (netif_running(dev))
8171 return ixgbe_open(dev);
8172
8173 return 0;
8174 }
8175
8176 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter,
8177 struct tc_cls_u32_offload *cls)
8178 {
8179 u32 uhtid = TC_U32_USERHTID(cls->knode.handle);
8180 u32 loc;
8181 int err;
8182
8183 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE))
8184 return -EINVAL;
8185
8186 loc = cls->knode.handle & 0xfffff;
8187
8188 spin_lock(&adapter->fdir_perfect_lock);
8189 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc);
8190 spin_unlock(&adapter->fdir_perfect_lock);
8191 return err;
8192 }
8193
8194 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter,
8195 __be16 protocol,
8196 struct tc_cls_u32_offload *cls)
8197 {
8198 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
8199
8200 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8201 return -EINVAL;
8202
8203 /* This ixgbe devices do not support hash tables at the moment
8204 * so abort when given hash tables.
8205 */
8206 if (cls->hnode.divisor > 0)
8207 return -EINVAL;
8208
8209 set_bit(uhtid - 1, &adapter->tables);
8210 return 0;
8211 }
8212
8213 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter,
8214 struct tc_cls_u32_offload *cls)
8215 {
8216 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
8217
8218 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8219 return -EINVAL;
8220
8221 clear_bit(uhtid - 1, &adapter->tables);
8222 return 0;
8223 }
8224
8225 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter,
8226 __be16 protocol,
8227 struct tc_cls_u32_offload *cls)
8228 {
8229 u32 loc = cls->knode.handle & 0xfffff;
8230 struct ixgbe_hw *hw = &adapter->hw;
8231 struct ixgbe_mat_field *field_ptr;
8232 struct ixgbe_fdir_filter *input;
8233 union ixgbe_atr_input mask;
8234 #ifdef CONFIG_NET_CLS_ACT
8235 const struct tc_action *a;
8236 #endif
8237 int i, err = 0;
8238 u8 queue;
8239 u32 uhtid, link_uhtid;
8240
8241 memset(&mask, 0, sizeof(union ixgbe_atr_input));
8242 uhtid = TC_U32_USERHTID(cls->knode.handle);
8243 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle);
8244
8245 /* At the moment cls_u32 jumps to network layer and skips past
8246 * L2 headers. The canonical method to match L2 frames is to use
8247 * negative values. However this is error prone at best but really
8248 * just broken because there is no way to "know" what sort of hdr
8249 * is in front of the network layer. Fix cls_u32 to support L2
8250 * headers when needed.
8251 */
8252 if (protocol != htons(ETH_P_IP))
8253 return -EINVAL;
8254
8255 if (link_uhtid) {
8256 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps;
8257
8258 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE)
8259 return -EINVAL;
8260
8261 if (!test_bit(link_uhtid - 1, &adapter->tables))
8262 return -EINVAL;
8263
8264 for (i = 0; nexthdr[i].jump; i++) {
8265 if (nexthdr[i].o != cls->knode.sel->offoff ||
8266 nexthdr[i].s != cls->knode.sel->offshift ||
8267 nexthdr[i].m != cls->knode.sel->offmask ||
8268 /* do not support multiple key jumps its just mad */
8269 cls->knode.sel->nkeys > 1)
8270 return -EINVAL;
8271
8272 if (nexthdr[i].off == cls->knode.sel->keys[0].off &&
8273 nexthdr[i].val == cls->knode.sel->keys[0].val &&
8274 nexthdr[i].mask == cls->knode.sel->keys[0].mask) {
8275 adapter->jump_tables[link_uhtid] =
8276 nexthdr[i].jump;
8277 break;
8278 }
8279 }
8280 return 0;
8281 }
8282
8283 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) {
8284 e_err(drv, "Location out of range\n");
8285 return -EINVAL;
8286 }
8287
8288 /* cls u32 is a graph starting at root node 0x800. The driver tracks
8289 * links and also the fields used to advance the parser across each
8290 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map
8291 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h
8292 * To add support for new nodes update ixgbe_model.h parse structures
8293 * this function _should_ be generic try not to hardcode values here.
8294 */
8295 if (uhtid == 0x800) {
8296 field_ptr = adapter->jump_tables[0];
8297 } else {
8298 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8299 return -EINVAL;
8300
8301 field_ptr = adapter->jump_tables[uhtid];
8302 }
8303
8304 if (!field_ptr)
8305 return -EINVAL;
8306
8307 input = kzalloc(sizeof(*input), GFP_KERNEL);
8308 if (!input)
8309 return -ENOMEM;
8310
8311 for (i = 0; i < cls->knode.sel->nkeys; i++) {
8312 int off = cls->knode.sel->keys[i].off;
8313 __be32 val = cls->knode.sel->keys[i].val;
8314 __be32 m = cls->knode.sel->keys[i].mask;
8315 bool found_entry = false;
8316 int j;
8317
8318 for (j = 0; field_ptr[j].val; j++) {
8319 if (field_ptr[j].off == off) {
8320 field_ptr[j].val(input, &mask, val, m);
8321 input->filter.formatted.flow_type |=
8322 field_ptr[j].type;
8323 found_entry = true;
8324 break;
8325 }
8326 }
8327
8328 if (!found_entry)
8329 goto err_out;
8330 }
8331
8332 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
8333 IXGBE_ATR_L4TYPE_MASK;
8334
8335 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
8336 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
8337
8338 #ifdef CONFIG_NET_CLS_ACT
8339 if (list_empty(&cls->knode.exts->actions))
8340 goto err_out;
8341
8342 list_for_each_entry(a, &cls->knode.exts->actions, list) {
8343 if (!is_tcf_gact_shot(a))
8344 goto err_out;
8345 }
8346 #endif
8347
8348 input->action = IXGBE_FDIR_DROP_QUEUE;
8349 queue = IXGBE_FDIR_DROP_QUEUE;
8350 input->sw_idx = loc;
8351
8352 spin_lock(&adapter->fdir_perfect_lock);
8353
8354 if (hlist_empty(&adapter->fdir_filter_list)) {
8355 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
8356 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
8357 if (err)
8358 goto err_out_w_lock;
8359 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
8360 err = -EINVAL;
8361 goto err_out_w_lock;
8362 }
8363
8364 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
8365 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter,
8366 input->sw_idx, queue);
8367 if (!err)
8368 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
8369 spin_unlock(&adapter->fdir_perfect_lock);
8370
8371 return err;
8372 err_out_w_lock:
8373 spin_unlock(&adapter->fdir_perfect_lock);
8374 err_out:
8375 kfree(input);
8376 return -EINVAL;
8377 }
8378
8379 static int __ixgbe_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
8380 struct tc_to_netdev *tc)
8381 {
8382 struct ixgbe_adapter *adapter = netdev_priv(dev);
8383
8384 if (TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS) &&
8385 tc->type == TC_SETUP_CLSU32) {
8386 switch (tc->cls_u32->command) {
8387 case TC_CLSU32_NEW_KNODE:
8388 case TC_CLSU32_REPLACE_KNODE:
8389 return ixgbe_configure_clsu32(adapter,
8390 proto, tc->cls_u32);
8391 case TC_CLSU32_DELETE_KNODE:
8392 return ixgbe_delete_clsu32(adapter, tc->cls_u32);
8393 case TC_CLSU32_NEW_HNODE:
8394 case TC_CLSU32_REPLACE_HNODE:
8395 return ixgbe_configure_clsu32_add_hnode(adapter, proto,
8396 tc->cls_u32);
8397 case TC_CLSU32_DELETE_HNODE:
8398 return ixgbe_configure_clsu32_del_hnode(adapter,
8399 tc->cls_u32);
8400 default:
8401 return -EINVAL;
8402 }
8403 }
8404
8405 if (tc->type != TC_SETUP_MQPRIO)
8406 return -EINVAL;
8407
8408 return ixgbe_setup_tc(dev, tc->tc);
8409 }
8410
8411 #ifdef CONFIG_PCI_IOV
8412 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
8413 {
8414 struct net_device *netdev = adapter->netdev;
8415
8416 rtnl_lock();
8417 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
8418 rtnl_unlock();
8419 }
8420
8421 #endif
8422 void ixgbe_do_reset(struct net_device *netdev)
8423 {
8424 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8425
8426 if (netif_running(netdev))
8427 ixgbe_reinit_locked(adapter);
8428 else
8429 ixgbe_reset(adapter);
8430 }
8431
8432 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
8433 netdev_features_t features)
8434 {
8435 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8436
8437 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
8438 if (!(features & NETIF_F_RXCSUM))
8439 features &= ~NETIF_F_LRO;
8440
8441 /* Turn off LRO if not RSC capable */
8442 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
8443 features &= ~NETIF_F_LRO;
8444
8445 return features;
8446 }
8447
8448 static int ixgbe_set_features(struct net_device *netdev,
8449 netdev_features_t features)
8450 {
8451 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8452 netdev_features_t changed = netdev->features ^ features;
8453 bool need_reset = false;
8454
8455 /* Make sure RSC matches LRO, reset if change */
8456 if (!(features & NETIF_F_LRO)) {
8457 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
8458 need_reset = true;
8459 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
8460 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
8461 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
8462 if (adapter->rx_itr_setting == 1 ||
8463 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
8464 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8465 need_reset = true;
8466 } else if ((changed ^ features) & NETIF_F_LRO) {
8467 e_info(probe, "rx-usecs set too low, "
8468 "disabling RSC\n");
8469 }
8470 }
8471
8472 /*
8473 * Check if Flow Director n-tuple support or hw_tc support was
8474 * enabled or disabled. If the state changed, we need to reset.
8475 */
8476 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) {
8477 /* turn off ATR, enable perfect filters and reset */
8478 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
8479 need_reset = true;
8480
8481 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
8482 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8483 } else {
8484 /* turn off perfect filters, enable ATR and reset */
8485 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
8486 need_reset = true;
8487
8488 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8489
8490 /* We cannot enable ATR if SR-IOV is enabled */
8491 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED ||
8492 /* We cannot enable ATR if we have 2 or more tcs */
8493 (netdev_get_num_tc(netdev) > 1) ||
8494 /* We cannot enable ATR if RSS is disabled */
8495 (adapter->ring_feature[RING_F_RSS].limit <= 1) ||
8496 /* A sample rate of 0 indicates ATR disabled */
8497 (!adapter->atr_sample_rate))
8498 ; /* do nothing not supported */
8499 else /* otherwise supported and set the flag */
8500 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
8501 }
8502
8503 if (changed & NETIF_F_RXALL)
8504 need_reset = true;
8505
8506 netdev->features = features;
8507
8508 #ifdef CONFIG_IXGBE_VXLAN
8509 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
8510 if (features & NETIF_F_RXCSUM)
8511 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8512 else
8513 ixgbe_clear_vxlan_port(adapter);
8514 }
8515 #endif /* CONFIG_IXGBE_VXLAN */
8516
8517 if (need_reset)
8518 ixgbe_do_reset(netdev);
8519 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX |
8520 NETIF_F_HW_VLAN_CTAG_FILTER))
8521 ixgbe_set_rx_mode(netdev);
8522
8523 return 0;
8524 }
8525
8526 #ifdef CONFIG_IXGBE_VXLAN
8527 /**
8528 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up
8529 * @dev: The port's netdev
8530 * @sa_family: Socket Family that VXLAN is notifiying us about
8531 * @port: New UDP port number that VXLAN started listening to
8532 **/
8533 static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8534 __be16 port)
8535 {
8536 struct ixgbe_adapter *adapter = netdev_priv(dev);
8537 struct ixgbe_hw *hw = &adapter->hw;
8538
8539 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8540 return;
8541
8542 if (sa_family == AF_INET6)
8543 return;
8544
8545 if (adapter->vxlan_port == port)
8546 return;
8547
8548 if (adapter->vxlan_port) {
8549 netdev_info(dev,
8550 "Hit Max num of VXLAN ports, not adding port %d\n",
8551 ntohs(port));
8552 return;
8553 }
8554
8555 adapter->vxlan_port = port;
8556 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, ntohs(port));
8557 }
8558
8559 /**
8560 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away
8561 * @dev: The port's netdev
8562 * @sa_family: Socket Family that VXLAN is notifying us about
8563 * @port: UDP port number that VXLAN stopped listening to
8564 **/
8565 static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8566 __be16 port)
8567 {
8568 struct ixgbe_adapter *adapter = netdev_priv(dev);
8569
8570 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8571 return;
8572
8573 if (sa_family == AF_INET6)
8574 return;
8575
8576 if (adapter->vxlan_port != port) {
8577 netdev_info(dev, "Port %d was not found, not deleting\n",
8578 ntohs(port));
8579 return;
8580 }
8581
8582 ixgbe_clear_vxlan_port(adapter);
8583 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8584 }
8585 #endif /* CONFIG_IXGBE_VXLAN */
8586
8587 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8588 struct net_device *dev,
8589 const unsigned char *addr, u16 vid,
8590 u16 flags)
8591 {
8592 /* guarantee we can provide a unique filter for the unicast address */
8593 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
8594 struct ixgbe_adapter *adapter = netdev_priv(dev);
8595 u16 pool = VMDQ_P(0);
8596
8597 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool))
8598 return -ENOMEM;
8599 }
8600
8601 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
8602 }
8603
8604 /**
8605 * ixgbe_configure_bridge_mode - set various bridge modes
8606 * @adapter - the private structure
8607 * @mode - requested bridge mode
8608 *
8609 * Configure some settings require for various bridge modes.
8610 **/
8611 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
8612 __u16 mode)
8613 {
8614 struct ixgbe_hw *hw = &adapter->hw;
8615 unsigned int p, num_pools;
8616 u32 vmdctl;
8617
8618 switch (mode) {
8619 case BRIDGE_MODE_VEPA:
8620 /* disable Tx loopback, rely on switch hairpin mode */
8621 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
8622
8623 /* must enable Rx switching replication to allow multicast
8624 * packet reception on all VFs, and to enable source address
8625 * pruning.
8626 */
8627 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8628 vmdctl |= IXGBE_VT_CTL_REPLEN;
8629 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8630
8631 /* enable Rx source address pruning. Note, this requires
8632 * replication to be enabled or else it does nothing.
8633 */
8634 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8635 for (p = 0; p < num_pools; p++) {
8636 if (hw->mac.ops.set_source_address_pruning)
8637 hw->mac.ops.set_source_address_pruning(hw,
8638 true,
8639 p);
8640 }
8641 break;
8642 case BRIDGE_MODE_VEB:
8643 /* enable Tx loopback for internal VF/PF communication */
8644 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
8645 IXGBE_PFDTXGSWC_VT_LBEN);
8646
8647 /* disable Rx switching replication unless we have SR-IOV
8648 * virtual functions
8649 */
8650 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8651 if (!adapter->num_vfs)
8652 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
8653 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8654
8655 /* disable Rx source address pruning, since we don't expect to
8656 * be receiving external loopback of our transmitted frames.
8657 */
8658 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8659 for (p = 0; p < num_pools; p++) {
8660 if (hw->mac.ops.set_source_address_pruning)
8661 hw->mac.ops.set_source_address_pruning(hw,
8662 false,
8663 p);
8664 }
8665 break;
8666 default:
8667 return -EINVAL;
8668 }
8669
8670 adapter->bridge_mode = mode;
8671
8672 e_info(drv, "enabling bridge mode: %s\n",
8673 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
8674
8675 return 0;
8676 }
8677
8678 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
8679 struct nlmsghdr *nlh, u16 flags)
8680 {
8681 struct ixgbe_adapter *adapter = netdev_priv(dev);
8682 struct nlattr *attr, *br_spec;
8683 int rem;
8684
8685 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8686 return -EOPNOTSUPP;
8687
8688 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8689 if (!br_spec)
8690 return -EINVAL;
8691
8692 nla_for_each_nested(attr, br_spec, rem) {
8693 int status;
8694 __u16 mode;
8695
8696 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8697 continue;
8698
8699 if (nla_len(attr) < sizeof(mode))
8700 return -EINVAL;
8701
8702 mode = nla_get_u16(attr);
8703 status = ixgbe_configure_bridge_mode(adapter, mode);
8704 if (status)
8705 return status;
8706
8707 break;
8708 }
8709
8710 return 0;
8711 }
8712
8713 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8714 struct net_device *dev,
8715 u32 filter_mask, int nlflags)
8716 {
8717 struct ixgbe_adapter *adapter = netdev_priv(dev);
8718
8719 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8720 return 0;
8721
8722 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
8723 adapter->bridge_mode, 0, 0, nlflags,
8724 filter_mask, NULL);
8725 }
8726
8727 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
8728 {
8729 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
8730 struct ixgbe_adapter *adapter = netdev_priv(pdev);
8731 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
8732 unsigned int limit;
8733 int pool, err;
8734
8735 /* Hardware has a limited number of available pools. Each VF, and the
8736 * PF require a pool. Check to ensure we don't attempt to use more
8737 * then the available number of pools.
8738 */
8739 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
8740 return ERR_PTR(-EINVAL);
8741
8742 #ifdef CONFIG_RPS
8743 if (vdev->num_rx_queues != vdev->num_tx_queues) {
8744 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
8745 vdev->name);
8746 return ERR_PTR(-EINVAL);
8747 }
8748 #endif
8749 /* Check for hardware restriction on number of rx/tx queues */
8750 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
8751 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
8752 netdev_info(pdev,
8753 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
8754 pdev->name);
8755 return ERR_PTR(-EINVAL);
8756 }
8757
8758 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8759 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
8760 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
8761 return ERR_PTR(-EBUSY);
8762
8763 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL);
8764 if (!fwd_adapter)
8765 return ERR_PTR(-ENOMEM);
8766
8767 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
8768 adapter->num_rx_pools++;
8769 set_bit(pool, &adapter->fwd_bitmask);
8770 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8771
8772 /* Enable VMDq flag so device will be set in VM mode */
8773 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
8774 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
8775 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
8776
8777 /* Force reinit of ring allocation with VMDQ enabled */
8778 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8779 if (err)
8780 goto fwd_add_err;
8781 fwd_adapter->pool = pool;
8782 fwd_adapter->real_adapter = adapter;
8783 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
8784 if (err)
8785 goto fwd_add_err;
8786 netif_tx_start_all_queues(vdev);
8787 return fwd_adapter;
8788 fwd_add_err:
8789 /* unwind counter and free adapter struct */
8790 netdev_info(pdev,
8791 "%s: dfwd hardware acceleration failed\n", vdev->name);
8792 clear_bit(pool, &adapter->fwd_bitmask);
8793 adapter->num_rx_pools--;
8794 kfree(fwd_adapter);
8795 return ERR_PTR(err);
8796 }
8797
8798 static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8799 {
8800 struct ixgbe_fwd_adapter *fwd_adapter = priv;
8801 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
8802 unsigned int limit;
8803
8804 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
8805 adapter->num_rx_pools--;
8806
8807 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8808 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
8809 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
8810 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8811 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
8812 fwd_adapter->pool, adapter->num_rx_pools,
8813 fwd_adapter->rx_base_queue,
8814 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
8815 adapter->fwd_bitmask);
8816 kfree(fwd_adapter);
8817 }
8818
8819 #define IXGBE_MAX_TUNNEL_HDR_LEN 80
8820 static netdev_features_t
8821 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
8822 netdev_features_t features)
8823 {
8824 if (!skb->encapsulation)
8825 return features;
8826
8827 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) >
8828 IXGBE_MAX_TUNNEL_HDR_LEN))
8829 return features & ~NETIF_F_CSUM_MASK;
8830
8831 return features;
8832 }
8833
8834 static const struct net_device_ops ixgbe_netdev_ops = {
8835 .ndo_open = ixgbe_open,
8836 .ndo_stop = ixgbe_close,
8837 .ndo_start_xmit = ixgbe_xmit_frame,
8838 .ndo_select_queue = ixgbe_select_queue,
8839 .ndo_set_rx_mode = ixgbe_set_rx_mode,
8840 .ndo_validate_addr = eth_validate_addr,
8841 .ndo_set_mac_address = ixgbe_set_mac,
8842 .ndo_change_mtu = ixgbe_change_mtu,
8843 .ndo_tx_timeout = ixgbe_tx_timeout,
8844 .ndo_set_tx_maxrate = ixgbe_tx_maxrate,
8845 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
8846 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
8847 .ndo_do_ioctl = ixgbe_ioctl,
8848 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
8849 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
8850 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
8851 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
8852 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
8853 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
8854 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
8855 .ndo_get_stats64 = ixgbe_get_stats64,
8856 .ndo_setup_tc = __ixgbe_setup_tc,
8857 #ifdef CONFIG_NET_POLL_CONTROLLER
8858 .ndo_poll_controller = ixgbe_netpoll,
8859 #endif
8860 #ifdef CONFIG_NET_RX_BUSY_POLL
8861 .ndo_busy_poll = ixgbe_low_latency_recv,
8862 #endif
8863 #ifdef IXGBE_FCOE
8864 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
8865 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
8866 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8867 .ndo_fcoe_enable = ixgbe_fcoe_enable,
8868 .ndo_fcoe_disable = ixgbe_fcoe_disable,
8869 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
8870 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
8871 #endif /* IXGBE_FCOE */
8872 .ndo_set_features = ixgbe_set_features,
8873 .ndo_fix_features = ixgbe_fix_features,
8874 .ndo_fdb_add = ixgbe_ndo_fdb_add,
8875 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
8876 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
8877 .ndo_dfwd_add_station = ixgbe_fwd_add,
8878 .ndo_dfwd_del_station = ixgbe_fwd_del,
8879 #ifdef CONFIG_IXGBE_VXLAN
8880 .ndo_add_vxlan_port = ixgbe_add_vxlan_port,
8881 .ndo_del_vxlan_port = ixgbe_del_vxlan_port,
8882 #endif /* CONFIG_IXGBE_VXLAN */
8883 .ndo_features_check = ixgbe_features_check,
8884 };
8885
8886 /**
8887 * ixgbe_enumerate_functions - Get the number of ports this device has
8888 * @adapter: adapter structure
8889 *
8890 * This function enumerates the phsyical functions co-located on a single slot,
8891 * in order to determine how many ports a device has. This is most useful in
8892 * determining the required GT/s of PCIe bandwidth necessary for optimal
8893 * performance.
8894 **/
8895 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
8896 {
8897 struct pci_dev *entry, *pdev = adapter->pdev;
8898 int physfns = 0;
8899
8900 /* Some cards can not use the generic count PCIe functions method,
8901 * because they are behind a parent switch, so we hardcode these with
8902 * the correct number of functions.
8903 */
8904 if (ixgbe_pcie_from_parent(&adapter->hw))
8905 physfns = 4;
8906
8907 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
8908 /* don't count virtual functions */
8909 if (entry->is_virtfn)
8910 continue;
8911
8912 /* When the devices on the bus don't all match our device ID,
8913 * we can't reliably determine the correct number of
8914 * functions. This can occur if a function has been direct
8915 * attached to a virtual machine using VT-d, for example. In
8916 * this case, simply return -1 to indicate this.
8917 */
8918 if ((entry->vendor != pdev->vendor) ||
8919 (entry->device != pdev->device))
8920 return -1;
8921
8922 physfns++;
8923 }
8924
8925 return physfns;
8926 }
8927
8928 /**
8929 * ixgbe_wol_supported - Check whether device supports WoL
8930 * @hw: hw specific details
8931 * @device_id: the device ID
8932 * @subdev_id: the subsystem device ID
8933 *
8934 * This function is used by probe and ethtool to determine
8935 * which devices have WoL support
8936 *
8937 **/
8938 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8939 u16 subdevice_id)
8940 {
8941 struct ixgbe_hw *hw = &adapter->hw;
8942 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8943 int is_wol_supported = 0;
8944
8945 switch (device_id) {
8946 case IXGBE_DEV_ID_82599_SFP:
8947 /* Only these subdevices could supports WOL */
8948 switch (subdevice_id) {
8949 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8950 case IXGBE_SUBDEV_ID_82599_560FLR:
8951 /* only support first port */
8952 if (hw->bus.func != 0)
8953 break;
8954 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8955 case IXGBE_SUBDEV_ID_82599_SFP:
8956 case IXGBE_SUBDEV_ID_82599_RNDC:
8957 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
8958 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8959 is_wol_supported = 1;
8960 break;
8961 }
8962 break;
8963 case IXGBE_DEV_ID_82599EN_SFP:
8964 /* Only this subdevice supports WOL */
8965 switch (subdevice_id) {
8966 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8967 is_wol_supported = 1;
8968 break;
8969 }
8970 break;
8971 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8972 /* All except this subdevice support WOL */
8973 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8974 is_wol_supported = 1;
8975 break;
8976 case IXGBE_DEV_ID_82599_KX4:
8977 is_wol_supported = 1;
8978 break;
8979 case IXGBE_DEV_ID_X540T:
8980 case IXGBE_DEV_ID_X540T1:
8981 case IXGBE_DEV_ID_X550T:
8982 case IXGBE_DEV_ID_X550EM_X_KX4:
8983 case IXGBE_DEV_ID_X550EM_X_KR:
8984 case IXGBE_DEV_ID_X550EM_X_10G_T:
8985 /* check eeprom to see if enabled wol */
8986 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8987 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8988 (hw->bus.func == 0))) {
8989 is_wol_supported = 1;
8990 }
8991 break;
8992 }
8993
8994 return is_wol_supported;
8995 }
8996
8997 /**
8998 * ixgbe_probe - Device Initialization Routine
8999 * @pdev: PCI device information struct
9000 * @ent: entry in ixgbe_pci_tbl
9001 *
9002 * Returns 0 on success, negative on failure
9003 *
9004 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
9005 * The OS initialization, configuring of the adapter private structure,
9006 * and a hardware reset occur.
9007 **/
9008 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9009 {
9010 struct net_device *netdev;
9011 struct ixgbe_adapter *adapter = NULL;
9012 struct ixgbe_hw *hw;
9013 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9014 int i, err, pci_using_dac, expected_gts;
9015 unsigned int indices = MAX_TX_QUEUES;
9016 u8 part_str[IXGBE_PBANUM_LENGTH];
9017 bool disable_dev = false;
9018 #ifdef IXGBE_FCOE
9019 u16 device_caps;
9020 #endif
9021 u32 eec;
9022
9023 /* Catch broken hardware that put the wrong VF device ID in
9024 * the PCIe SR-IOV capability.
9025 */
9026 if (pdev->is_virtfn) {
9027 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
9028 pci_name(pdev), pdev->vendor, pdev->device);
9029 return -EINVAL;
9030 }
9031
9032 err = pci_enable_device_mem(pdev);
9033 if (err)
9034 return err;
9035
9036 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9037 pci_using_dac = 1;
9038 } else {
9039 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9040 if (err) {
9041 dev_err(&pdev->dev,
9042 "No usable DMA configuration, aborting\n");
9043 goto err_dma;
9044 }
9045 pci_using_dac = 0;
9046 }
9047
9048 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
9049 IORESOURCE_MEM), ixgbe_driver_name);
9050 if (err) {
9051 dev_err(&pdev->dev,
9052 "pci_request_selected_regions failed 0x%x\n", err);
9053 goto err_pci_reg;
9054 }
9055
9056 pci_enable_pcie_error_reporting(pdev);
9057
9058 pci_set_master(pdev);
9059 pci_save_state(pdev);
9060
9061 if (ii->mac == ixgbe_mac_82598EB) {
9062 #ifdef CONFIG_IXGBE_DCB
9063 /* 8 TC w/ 4 queues per TC */
9064 indices = 4 * MAX_TRAFFIC_CLASS;
9065 #else
9066 indices = IXGBE_MAX_RSS_INDICES;
9067 #endif
9068 }
9069
9070 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9071 if (!netdev) {
9072 err = -ENOMEM;
9073 goto err_alloc_etherdev;
9074 }
9075
9076 SET_NETDEV_DEV(netdev, &pdev->dev);
9077
9078 adapter = netdev_priv(netdev);
9079
9080 adapter->netdev = netdev;
9081 adapter->pdev = pdev;
9082 hw = &adapter->hw;
9083 hw->back = adapter;
9084 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9085
9086 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
9087 pci_resource_len(pdev, 0));
9088 adapter->io_addr = hw->hw_addr;
9089 if (!hw->hw_addr) {
9090 err = -EIO;
9091 goto err_ioremap;
9092 }
9093
9094 netdev->netdev_ops = &ixgbe_netdev_ops;
9095 ixgbe_set_ethtool_ops(netdev);
9096 netdev->watchdog_timeo = 5 * HZ;
9097 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9098
9099 /* Setup hw api */
9100 hw->mac.ops = *ii->mac_ops;
9101 hw->mac.type = ii->mac;
9102 hw->mvals = ii->mvals;
9103
9104 /* EEPROM */
9105 hw->eeprom.ops = *ii->eeprom_ops;
9106 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
9107 if (ixgbe_removed(hw->hw_addr)) {
9108 err = -EIO;
9109 goto err_ioremap;
9110 }
9111 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
9112 if (!(eec & (1 << 8)))
9113 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
9114
9115 /* PHY */
9116 hw->phy.ops = *ii->phy_ops;
9117 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
9118 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
9119 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
9120 hw->phy.mdio.mmds = 0;
9121 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9122 hw->phy.mdio.dev = netdev;
9123 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
9124 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
9125
9126 ii->get_invariants(hw);
9127
9128 /* setup the private structure */
9129 err = ixgbe_sw_init(adapter);
9130 if (err)
9131 goto err_sw_init;
9132
9133 /* Make sure the SWFW semaphore is in a valid state */
9134 if (hw->mac.ops.init_swfw_sync)
9135 hw->mac.ops.init_swfw_sync(hw);
9136
9137 /* Make it possible the adapter to be woken up via WOL */
9138 switch (adapter->hw.mac.type) {
9139 case ixgbe_mac_82599EB:
9140 case ixgbe_mac_X540:
9141 case ixgbe_mac_X550:
9142 case ixgbe_mac_X550EM_x:
9143 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
9144 break;
9145 default:
9146 break;
9147 }
9148
9149 /*
9150 * If there is a fan on this device and it has failed log the
9151 * failure.
9152 */
9153 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
9154 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
9155 if (esdp & IXGBE_ESDP_SDP1)
9156 e_crit(probe, "Fan has stopped, replace the adapter\n");
9157 }
9158
9159 if (allow_unsupported_sfp)
9160 hw->allow_unsupported_sfp = allow_unsupported_sfp;
9161
9162 /* reset_hw fills in the perm_addr as well */
9163 hw->phy.reset_if_overtemp = true;
9164 err = hw->mac.ops.reset_hw(hw);
9165 hw->phy.reset_if_overtemp = false;
9166 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
9167 err = 0;
9168 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
9169 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
9170 e_dev_err("Reload the driver after installing a supported module.\n");
9171 goto err_sw_init;
9172 } else if (err) {
9173 e_dev_err("HW Init failed: %d\n", err);
9174 goto err_sw_init;
9175 }
9176
9177 #ifdef CONFIG_PCI_IOV
9178 /* SR-IOV not supported on the 82598 */
9179 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
9180 goto skip_sriov;
9181 /* Mailbox */
9182 ixgbe_init_mbx_params_pf(hw);
9183 hw->mbx.ops = ii->mbx_ops;
9184 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
9185 ixgbe_enable_sriov(adapter);
9186 skip_sriov:
9187
9188 #endif
9189 netdev->features = NETIF_F_SG |
9190 NETIF_F_TSO |
9191 NETIF_F_TSO6 |
9192 NETIF_F_RXHASH |
9193 NETIF_F_RXCSUM |
9194 NETIF_F_HW_CSUM |
9195 NETIF_F_HW_VLAN_CTAG_TX |
9196 NETIF_F_HW_VLAN_CTAG_RX |
9197 NETIF_F_HW_VLAN_CTAG_FILTER;
9198
9199 if (hw->mac.type >= ixgbe_mac_82599EB)
9200 netdev->features |= NETIF_F_SCTP_CRC;
9201
9202 /* copy netdev features into list of user selectable features */
9203 netdev->hw_features |= netdev->features;
9204 netdev->hw_features |= NETIF_F_RXALL |
9205 NETIF_F_HW_L2FW_DOFFLOAD;
9206
9207 if (hw->mac.type >= ixgbe_mac_82599EB)
9208 netdev->hw_features |= NETIF_F_NTUPLE |
9209 NETIF_F_HW_TC;
9210
9211 netdev->vlan_features |= NETIF_F_SG |
9212 NETIF_F_TSO |
9213 NETIF_F_TSO6 |
9214 NETIF_F_HW_CSUM |
9215 NETIF_F_SCTP_CRC;
9216
9217 netdev->mpls_features |= NETIF_F_HW_CSUM;
9218 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
9219
9220 netdev->priv_flags |= IFF_UNICAST_FLT;
9221 netdev->priv_flags |= IFF_SUPP_NOFCS;
9222
9223 #ifdef CONFIG_IXGBE_DCB
9224 netdev->dcbnl_ops = &dcbnl_ops;
9225 #endif
9226
9227 #ifdef IXGBE_FCOE
9228 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
9229 unsigned int fcoe_l;
9230
9231 if (hw->mac.ops.get_device_caps) {
9232 hw->mac.ops.get_device_caps(hw, &device_caps);
9233 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
9234 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
9235 }
9236
9237
9238 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
9239 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
9240
9241 netdev->features |= NETIF_F_FSO |
9242 NETIF_F_FCOE_CRC;
9243
9244 netdev->vlan_features |= NETIF_F_FSO |
9245 NETIF_F_FCOE_CRC |
9246 NETIF_F_FCOE_MTU;
9247 }
9248 #endif /* IXGBE_FCOE */
9249 if (pci_using_dac) {
9250 netdev->features |= NETIF_F_HIGHDMA;
9251 netdev->vlan_features |= NETIF_F_HIGHDMA;
9252 }
9253
9254 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
9255 netdev->hw_features |= NETIF_F_LRO;
9256 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
9257 netdev->features |= NETIF_F_LRO;
9258
9259 /* make sure the EEPROM is good */
9260 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9261 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9262 err = -EIO;
9263 goto err_sw_init;
9264 }
9265
9266 eth_platform_get_mac_address(&adapter->pdev->dev,
9267 adapter->hw.mac.perm_addr);
9268
9269 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9270
9271 if (!is_valid_ether_addr(netdev->dev_addr)) {
9272 e_dev_err("invalid MAC address\n");
9273 err = -EIO;
9274 goto err_sw_init;
9275 }
9276
9277 /* Set hw->mac.addr to permanent MAC address */
9278 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr);
9279 ixgbe_mac_set_default_filter(adapter);
9280
9281 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
9282 (unsigned long) adapter);
9283
9284 if (ixgbe_removed(hw->hw_addr)) {
9285 err = -EIO;
9286 goto err_sw_init;
9287 }
9288 INIT_WORK(&adapter->service_task, ixgbe_service_task);
9289 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
9290 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9291
9292 err = ixgbe_init_interrupt_scheme(adapter);
9293 if (err)
9294 goto err_sw_init;
9295
9296 /* WOL not supported for all devices */
9297 adapter->wol = 0;
9298 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
9299 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
9300 pdev->subsystem_device);
9301 if (hw->wol_enabled)
9302 adapter->wol = IXGBE_WUFC_MAG;
9303
9304 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9305
9306 /* save off EEPROM version number */
9307 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
9308 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
9309
9310 /* pick up the PCI bus settings for reporting later */
9311 if (ixgbe_pcie_from_parent(hw))
9312 ixgbe_get_parent_bus_info(adapter);
9313 else
9314 hw->mac.ops.get_bus_info(hw);
9315
9316 /* calculate the expected PCIe bandwidth required for optimal
9317 * performance. Note that some older parts will never have enough
9318 * bandwidth due to being older generation PCIe parts. We clamp these
9319 * parts to ensure no warning is displayed if it can't be fixed.
9320 */
9321 switch (hw->mac.type) {
9322 case ixgbe_mac_82598EB:
9323 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
9324 break;
9325 default:
9326 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
9327 break;
9328 }
9329
9330 /* don't check link if we failed to enumerate functions */
9331 if (expected_gts > 0)
9332 ixgbe_check_minimum_link(adapter, expected_gts);
9333
9334 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
9335 if (err)
9336 strlcpy(part_str, "Unknown", sizeof(part_str));
9337 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
9338 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
9339 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
9340 part_str);
9341 else
9342 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
9343 hw->mac.type, hw->phy.type, part_str);
9344
9345 e_dev_info("%pM\n", netdev->dev_addr);
9346
9347 /* reset the hardware with the new settings */
9348 err = hw->mac.ops.start_hw(hw);
9349 if (err == IXGBE_ERR_EEPROM_VERSION) {
9350 /* We are running on a pre-production device, log a warning */
9351 e_dev_warn("This device is a pre-production adapter/LOM. "
9352 "Please be aware there may be issues associated "
9353 "with your hardware. If you are experiencing "
9354 "problems please contact your Intel or hardware "
9355 "representative who provided you with this "
9356 "hardware.\n");
9357 }
9358 strcpy(netdev->name, "eth%d");
9359 err = register_netdev(netdev);
9360 if (err)
9361 goto err_register;
9362
9363 pci_set_drvdata(pdev, adapter);
9364
9365 /* power down the optics for 82599 SFP+ fiber */
9366 if (hw->mac.ops.disable_tx_laser)
9367 hw->mac.ops.disable_tx_laser(hw);
9368
9369 /* carrier off reporting is important to ethtool even BEFORE open */
9370 netif_carrier_off(netdev);
9371
9372 #ifdef CONFIG_IXGBE_DCA
9373 if (dca_add_requester(&pdev->dev) == 0) {
9374 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
9375 ixgbe_setup_dca(adapter);
9376 }
9377 #endif
9378 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
9379 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
9380 for (i = 0; i < adapter->num_vfs; i++)
9381 ixgbe_vf_configuration(pdev, (i | 0x10000000));
9382 }
9383
9384 /* firmware requires driver version to be 0xFFFFFFFF
9385 * since os does not support feature
9386 */
9387 if (hw->mac.ops.set_fw_drv_ver)
9388 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
9389 0xFF);
9390
9391 /* add san mac addr to netdev */
9392 ixgbe_add_sanmac_netdev(netdev);
9393
9394 e_dev_info("%s\n", ixgbe_default_device_descr);
9395
9396 #ifdef CONFIG_IXGBE_HWMON
9397 if (ixgbe_sysfs_init(adapter))
9398 e_err(probe, "failed to allocate sysfs resources\n");
9399 #endif /* CONFIG_IXGBE_HWMON */
9400
9401 ixgbe_dbg_adapter_init(adapter);
9402
9403 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
9404 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
9405 hw->mac.ops.setup_link(hw,
9406 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
9407 true);
9408
9409 return 0;
9410
9411 err_register:
9412 ixgbe_release_hw_control(adapter);
9413 ixgbe_clear_interrupt_scheme(adapter);
9414 err_sw_init:
9415 ixgbe_disable_sriov(adapter);
9416 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9417 iounmap(adapter->io_addr);
9418 kfree(adapter->mac_table);
9419 err_ioremap:
9420 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9421 free_netdev(netdev);
9422 err_alloc_etherdev:
9423 pci_release_selected_regions(pdev,
9424 pci_select_bars(pdev, IORESOURCE_MEM));
9425 err_pci_reg:
9426 err_dma:
9427 if (!adapter || disable_dev)
9428 pci_disable_device(pdev);
9429 return err;
9430 }
9431
9432 /**
9433 * ixgbe_remove - Device Removal Routine
9434 * @pdev: PCI device information struct
9435 *
9436 * ixgbe_remove is called by the PCI subsystem to alert the driver
9437 * that it should release a PCI device. The could be caused by a
9438 * Hot-Plug event, or because the driver is going to be removed from
9439 * memory.
9440 **/
9441 static void ixgbe_remove(struct pci_dev *pdev)
9442 {
9443 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9444 struct net_device *netdev;
9445 bool disable_dev;
9446
9447 /* if !adapter then we already cleaned up in probe */
9448 if (!adapter)
9449 return;
9450
9451 netdev = adapter->netdev;
9452 ixgbe_dbg_adapter_exit(adapter);
9453
9454 set_bit(__IXGBE_REMOVING, &adapter->state);
9455 cancel_work_sync(&adapter->service_task);
9456
9457
9458 #ifdef CONFIG_IXGBE_DCA
9459 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
9460 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9461 dca_remove_requester(&pdev->dev);
9462 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
9463 IXGBE_DCA_CTRL_DCA_DISABLE);
9464 }
9465
9466 #endif
9467 #ifdef CONFIG_IXGBE_HWMON
9468 ixgbe_sysfs_exit(adapter);
9469 #endif /* CONFIG_IXGBE_HWMON */
9470
9471 /* remove the added san mac */
9472 ixgbe_del_sanmac_netdev(netdev);
9473
9474 #ifdef CONFIG_PCI_IOV
9475 ixgbe_disable_sriov(adapter);
9476 #endif
9477 if (netdev->reg_state == NETREG_REGISTERED)
9478 unregister_netdev(netdev);
9479
9480 ixgbe_clear_interrupt_scheme(adapter);
9481
9482 ixgbe_release_hw_control(adapter);
9483
9484 #ifdef CONFIG_DCB
9485 kfree(adapter->ixgbe_ieee_pfc);
9486 kfree(adapter->ixgbe_ieee_ets);
9487
9488 #endif
9489 iounmap(adapter->io_addr);
9490 pci_release_selected_regions(pdev, pci_select_bars(pdev,
9491 IORESOURCE_MEM));
9492
9493 e_dev_info("complete\n");
9494
9495 kfree(adapter->mac_table);
9496 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9497 free_netdev(netdev);
9498
9499 pci_disable_pcie_error_reporting(pdev);
9500
9501 if (disable_dev)
9502 pci_disable_device(pdev);
9503 }
9504
9505 /**
9506 * ixgbe_io_error_detected - called when PCI error is detected
9507 * @pdev: Pointer to PCI device
9508 * @state: The current pci connection state
9509 *
9510 * This function is called after a PCI bus error affecting
9511 * this device has been detected.
9512 */
9513 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
9514 pci_channel_state_t state)
9515 {
9516 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9517 struct net_device *netdev = adapter->netdev;
9518
9519 #ifdef CONFIG_PCI_IOV
9520 struct ixgbe_hw *hw = &adapter->hw;
9521 struct pci_dev *bdev, *vfdev;
9522 u32 dw0, dw1, dw2, dw3;
9523 int vf, pos;
9524 u16 req_id, pf_func;
9525
9526 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
9527 adapter->num_vfs == 0)
9528 goto skip_bad_vf_detection;
9529
9530 bdev = pdev->bus->self;
9531 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
9532 bdev = bdev->bus->self;
9533
9534 if (!bdev)
9535 goto skip_bad_vf_detection;
9536
9537 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
9538 if (!pos)
9539 goto skip_bad_vf_detection;
9540
9541 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
9542 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
9543 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
9544 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
9545 if (ixgbe_removed(hw->hw_addr))
9546 goto skip_bad_vf_detection;
9547
9548 req_id = dw1 >> 16;
9549 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
9550 if (!(req_id & 0x0080))
9551 goto skip_bad_vf_detection;
9552
9553 pf_func = req_id & 0x01;
9554 if ((pf_func & 1) == (pdev->devfn & 1)) {
9555 unsigned int device_id;
9556
9557 vf = (req_id & 0x7F) >> 1;
9558 e_dev_err("VF %d has caused a PCIe error\n", vf);
9559 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
9560 "%8.8x\tdw3: %8.8x\n",
9561 dw0, dw1, dw2, dw3);
9562 switch (adapter->hw.mac.type) {
9563 case ixgbe_mac_82599EB:
9564 device_id = IXGBE_82599_VF_DEVICE_ID;
9565 break;
9566 case ixgbe_mac_X540:
9567 device_id = IXGBE_X540_VF_DEVICE_ID;
9568 break;
9569 case ixgbe_mac_X550:
9570 device_id = IXGBE_DEV_ID_X550_VF;
9571 break;
9572 case ixgbe_mac_X550EM_x:
9573 device_id = IXGBE_DEV_ID_X550EM_X_VF;
9574 break;
9575 default:
9576 device_id = 0;
9577 break;
9578 }
9579
9580 /* Find the pci device of the offending VF */
9581 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
9582 while (vfdev) {
9583 if (vfdev->devfn == (req_id & 0xFF))
9584 break;
9585 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
9586 device_id, vfdev);
9587 }
9588 /*
9589 * There's a slim chance the VF could have been hot plugged,
9590 * so if it is no longer present we don't need to issue the
9591 * VFLR. Just clean up the AER in that case.
9592 */
9593 if (vfdev) {
9594 ixgbe_issue_vf_flr(adapter, vfdev);
9595 /* Free device reference count */
9596 pci_dev_put(vfdev);
9597 }
9598
9599 pci_cleanup_aer_uncorrect_error_status(pdev);
9600 }
9601
9602 /*
9603 * Even though the error may have occurred on the other port
9604 * we still need to increment the vf error reference count for
9605 * both ports because the I/O resume function will be called
9606 * for both of them.
9607 */
9608 adapter->vferr_refcount++;
9609
9610 return PCI_ERS_RESULT_RECOVERED;
9611
9612 skip_bad_vf_detection:
9613 #endif /* CONFIG_PCI_IOV */
9614 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
9615 return PCI_ERS_RESULT_DISCONNECT;
9616
9617 rtnl_lock();
9618 netif_device_detach(netdev);
9619
9620 if (state == pci_channel_io_perm_failure) {
9621 rtnl_unlock();
9622 return PCI_ERS_RESULT_DISCONNECT;
9623 }
9624
9625 if (netif_running(netdev))
9626 ixgbe_down(adapter);
9627
9628 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
9629 pci_disable_device(pdev);
9630 rtnl_unlock();
9631
9632 /* Request a slot reset. */
9633 return PCI_ERS_RESULT_NEED_RESET;
9634 }
9635
9636 /**
9637 * ixgbe_io_slot_reset - called after the pci bus has been reset.
9638 * @pdev: Pointer to PCI device
9639 *
9640 * Restart the card from scratch, as if from a cold-boot.
9641 */
9642 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
9643 {
9644 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9645 pci_ers_result_t result;
9646 int err;
9647
9648 if (pci_enable_device_mem(pdev)) {
9649 e_err(probe, "Cannot re-enable PCI device after reset.\n");
9650 result = PCI_ERS_RESULT_DISCONNECT;
9651 } else {
9652 smp_mb__before_atomic();
9653 clear_bit(__IXGBE_DISABLED, &adapter->state);
9654 adapter->hw.hw_addr = adapter->io_addr;
9655 pci_set_master(pdev);
9656 pci_restore_state(pdev);
9657 pci_save_state(pdev);
9658
9659 pci_wake_from_d3(pdev, false);
9660
9661 ixgbe_reset(adapter);
9662 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
9663 result = PCI_ERS_RESULT_RECOVERED;
9664 }
9665
9666 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9667 if (err) {
9668 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
9669 "failed 0x%0x\n", err);
9670 /* non-fatal, continue */
9671 }
9672
9673 return result;
9674 }
9675
9676 /**
9677 * ixgbe_io_resume - called when traffic can start flowing again.
9678 * @pdev: Pointer to PCI device
9679 *
9680 * This callback is called when the error recovery driver tells us that
9681 * its OK to resume normal operation.
9682 */
9683 static void ixgbe_io_resume(struct pci_dev *pdev)
9684 {
9685 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9686 struct net_device *netdev = adapter->netdev;
9687
9688 #ifdef CONFIG_PCI_IOV
9689 if (adapter->vferr_refcount) {
9690 e_info(drv, "Resuming after VF err\n");
9691 adapter->vferr_refcount--;
9692 return;
9693 }
9694
9695 #endif
9696 if (netif_running(netdev))
9697 ixgbe_up(adapter);
9698
9699 netif_device_attach(netdev);
9700 }
9701
9702 static const struct pci_error_handlers ixgbe_err_handler = {
9703 .error_detected = ixgbe_io_error_detected,
9704 .slot_reset = ixgbe_io_slot_reset,
9705 .resume = ixgbe_io_resume,
9706 };
9707
9708 static struct pci_driver ixgbe_driver = {
9709 .name = ixgbe_driver_name,
9710 .id_table = ixgbe_pci_tbl,
9711 .probe = ixgbe_probe,
9712 .remove = ixgbe_remove,
9713 #ifdef CONFIG_PM
9714 .suspend = ixgbe_suspend,
9715 .resume = ixgbe_resume,
9716 #endif
9717 .shutdown = ixgbe_shutdown,
9718 .sriov_configure = ixgbe_pci_sriov_configure,
9719 .err_handler = &ixgbe_err_handler
9720 };
9721
9722 /**
9723 * ixgbe_init_module - Driver Registration Routine
9724 *
9725 * ixgbe_init_module is the first routine called when the driver is
9726 * loaded. All it does is register with the PCI subsystem.
9727 **/
9728 static int __init ixgbe_init_module(void)
9729 {
9730 int ret;
9731 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
9732 pr_info("%s\n", ixgbe_copyright);
9733
9734 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
9735 if (!ixgbe_wq) {
9736 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
9737 return -ENOMEM;
9738 }
9739
9740 ixgbe_dbg_init();
9741
9742 ret = pci_register_driver(&ixgbe_driver);
9743 if (ret) {
9744 ixgbe_dbg_exit();
9745 return ret;
9746 }
9747
9748 #ifdef CONFIG_IXGBE_DCA
9749 dca_register_notify(&dca_notifier);
9750 #endif
9751
9752 return 0;
9753 }
9754
9755 module_init(ixgbe_init_module);
9756
9757 /**
9758 * ixgbe_exit_module - Driver Exit Cleanup Routine
9759 *
9760 * ixgbe_exit_module is called just before the driver is removed
9761 * from memory.
9762 **/
9763 static void __exit ixgbe_exit_module(void)
9764 {
9765 #ifdef CONFIG_IXGBE_DCA
9766 dca_unregister_notify(&dca_notifier);
9767 #endif
9768 pci_unregister_driver(&ixgbe_driver);
9769
9770 ixgbe_dbg_exit();
9771 if (ixgbe_wq) {
9772 destroy_workqueue(ixgbe_wq);
9773 ixgbe_wq = NULL;
9774 }
9775 }
9776
9777 #ifdef CONFIG_IXGBE_DCA
9778 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
9779 void *p)
9780 {
9781 int ret_val;
9782
9783 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
9784 __ixgbe_notify_dca);
9785
9786 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
9787 }
9788
9789 #endif /* CONFIG_IXGBE_DCA */
9790
9791 module_exit(ixgbe_exit_module);
9792
9793 /* ixgbe_main.c */
Linux kernel - Deliverables
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