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[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/prefetch.h>
48 #include <scsi/fc/fc_fcoe.h>
49
50 #include "ixgbe.h"
51 #include "ixgbe_common.h"
52 #include "ixgbe_dcb_82599.h"
53 #include "ixgbe_sriov.h"
54
55 char ixgbe_driver_name[] = "ixgbe";
56 static const char ixgbe_driver_string[] =
57 "Intel(R) 10 Gigabit PCI Express Network Driver";
58 #ifdef IXGBE_FCOE
59 char ixgbe_default_device_descr[] =
60 "Intel(R) 10 Gigabit Network Connection";
61 #else
62 static char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
64 #endif
65 #define MAJ 3
66 #define MIN 8
67 #define BUILD 21
68 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
69 __stringify(BUILD) "-k"
70 const char ixgbe_driver_version[] = DRV_VERSION;
71 static const char ixgbe_copyright[] =
72 "Copyright (c) 1999-2012 Intel Corporation.";
73
74 static const struct ixgbe_info *ixgbe_info_tbl[] = {
75 [board_82598] = &ixgbe_82598_info,
76 [board_82599] = &ixgbe_82599_info,
77 [board_X540] = &ixgbe_X540_info,
78 };
79
80 /* ixgbe_pci_tbl - PCI Device ID Table
81 *
82 * Wildcard entries (PCI_ANY_ID) should come last
83 * Last entry must be all 0s
84 *
85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
86 * Class, Class Mask, private data (not used) }
87 */
88 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
117 /* required last entry */
118 {0, }
119 };
120 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121
122 #ifdef CONFIG_IXGBE_DCA
123 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
124 void *p);
125 static struct notifier_block dca_notifier = {
126 .notifier_call = ixgbe_notify_dca,
127 .next = NULL,
128 .priority = 0
129 };
130 #endif
131
132 #ifdef CONFIG_PCI_IOV
133 static unsigned int max_vfs;
134 module_param(max_vfs, uint, 0);
135 MODULE_PARM_DESC(max_vfs,
136 "Maximum number of virtual functions to allocate per physical function");
137 #endif /* CONFIG_PCI_IOV */
138
139 static unsigned int allow_unsupported_sfp;
140 module_param(allow_unsupported_sfp, uint, 0);
141 MODULE_PARM_DESC(allow_unsupported_sfp,
142 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
143
144 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
145 static int debug = -1;
146 module_param(debug, int, 0);
147 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
148
149 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
150 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
151 MODULE_LICENSE("GPL");
152 MODULE_VERSION(DRV_VERSION);
153
154 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
155 {
156 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
157 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
158 schedule_work(&adapter->service_task);
159 }
160
161 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
162 {
163 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
164
165 /* flush memory to make sure state is correct before next watchdog */
166 smp_mb__before_clear_bit();
167 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
168 }
169
170 struct ixgbe_reg_info {
171 u32 ofs;
172 char *name;
173 };
174
175 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
176
177 /* General Registers */
178 {IXGBE_CTRL, "CTRL"},
179 {IXGBE_STATUS, "STATUS"},
180 {IXGBE_CTRL_EXT, "CTRL_EXT"},
181
182 /* Interrupt Registers */
183 {IXGBE_EICR, "EICR"},
184
185 /* RX Registers */
186 {IXGBE_SRRCTL(0), "SRRCTL"},
187 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
188 {IXGBE_RDLEN(0), "RDLEN"},
189 {IXGBE_RDH(0), "RDH"},
190 {IXGBE_RDT(0), "RDT"},
191 {IXGBE_RXDCTL(0), "RXDCTL"},
192 {IXGBE_RDBAL(0), "RDBAL"},
193 {IXGBE_RDBAH(0), "RDBAH"},
194
195 /* TX Registers */
196 {IXGBE_TDBAL(0), "TDBAL"},
197 {IXGBE_TDBAH(0), "TDBAH"},
198 {IXGBE_TDLEN(0), "TDLEN"},
199 {IXGBE_TDH(0), "TDH"},
200 {IXGBE_TDT(0), "TDT"},
201 {IXGBE_TXDCTL(0), "TXDCTL"},
202
203 /* List Terminator */
204 {}
205 };
206
207
208 /*
209 * ixgbe_regdump - register printout routine
210 */
211 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
212 {
213 int i = 0, j = 0;
214 char rname[16];
215 u32 regs[64];
216
217 switch (reginfo->ofs) {
218 case IXGBE_SRRCTL(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
221 break;
222 case IXGBE_DCA_RXCTRL(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
225 break;
226 case IXGBE_RDLEN(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
229 break;
230 case IXGBE_RDH(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
233 break;
234 case IXGBE_RDT(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
237 break;
238 case IXGBE_RXDCTL(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
241 break;
242 case IXGBE_RDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
245 break;
246 case IXGBE_RDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
249 break;
250 case IXGBE_TDBAL(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
253 break;
254 case IXGBE_TDBAH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
257 break;
258 case IXGBE_TDLEN(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
261 break;
262 case IXGBE_TDH(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
265 break;
266 case IXGBE_TDT(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
269 break;
270 case IXGBE_TXDCTL(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
273 break;
274 default:
275 pr_info("%-15s %08x\n", reginfo->name,
276 IXGBE_READ_REG(hw, reginfo->ofs));
277 return;
278 }
279
280 for (i = 0; i < 8; i++) {
281 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
282 pr_err("%-15s", rname);
283 for (j = 0; j < 8; j++)
284 pr_cont(" %08x", regs[i*8+j]);
285 pr_cont("\n");
286 }
287
288 }
289
290 /*
291 * ixgbe_dump - Print registers, tx-rings and rx-rings
292 */
293 static void ixgbe_dump(struct ixgbe_adapter *adapter)
294 {
295 struct net_device *netdev = adapter->netdev;
296 struct ixgbe_hw *hw = &adapter->hw;
297 struct ixgbe_reg_info *reginfo;
298 int n = 0;
299 struct ixgbe_ring *tx_ring;
300 struct ixgbe_tx_buffer *tx_buffer;
301 union ixgbe_adv_tx_desc *tx_desc;
302 struct my_u0 { u64 a; u64 b; } *u0;
303 struct ixgbe_ring *rx_ring;
304 union ixgbe_adv_rx_desc *rx_desc;
305 struct ixgbe_rx_buffer *rx_buffer_info;
306 u32 staterr;
307 int i = 0;
308
309 if (!netif_msg_hw(adapter))
310 return;
311
312 /* Print netdevice Info */
313 if (netdev) {
314 dev_info(&adapter->pdev->dev, "Net device Info\n");
315 pr_info("Device Name state "
316 "trans_start last_rx\n");
317 pr_info("%-15s %016lX %016lX %016lX\n",
318 netdev->name,
319 netdev->state,
320 netdev->trans_start,
321 netdev->last_rx);
322 }
323
324 /* Print Registers */
325 dev_info(&adapter->pdev->dev, "Register Dump\n");
326 pr_info(" Register Name Value\n");
327 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
328 reginfo->name; reginfo++) {
329 ixgbe_regdump(hw, reginfo);
330 }
331
332 /* Print TX Ring Summary */
333 if (!netdev || !netif_running(netdev))
334 goto exit;
335
336 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
337 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
338 for (n = 0; n < adapter->num_tx_queues; n++) {
339 tx_ring = adapter->tx_ring[n];
340 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
341 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
342 n, tx_ring->next_to_use, tx_ring->next_to_clean,
343 (u64)dma_unmap_addr(tx_buffer, dma),
344 dma_unmap_len(tx_buffer, len),
345 tx_buffer->next_to_watch,
346 (u64)tx_buffer->time_stamp);
347 }
348
349 /* Print TX Rings */
350 if (!netif_msg_tx_done(adapter))
351 goto rx_ring_summary;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
354
355 /* Transmit Descriptor Formats
356 *
357 * Advanced Transmit Descriptor
358 * +--------------------------------------------------------------+
359 * 0 | Buffer Address [63:0] |
360 * +--------------------------------------------------------------+
361 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
362 * +--------------------------------------------------------------+
363 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
364 */
365
366 for (n = 0; n < adapter->num_tx_queues; n++) {
367 tx_ring = adapter->tx_ring[n];
368 pr_info("------------------------------------\n");
369 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
370 pr_info("------------------------------------\n");
371 pr_info("T [desc] [address 63:0 ] "
372 "[PlPOIdStDDt Ln] [bi->dma ] "
373 "leng ntw timestamp bi->skb\n");
374
375 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
376 tx_desc = IXGBE_TX_DESC(tx_ring, i);
377 tx_buffer = &tx_ring->tx_buffer_info[i];
378 u0 = (struct my_u0 *)tx_desc;
379 pr_info("T [0x%03X] %016llX %016llX %016llX"
380 " %04X %p %016llX %p", i,
381 le64_to_cpu(u0->a),
382 le64_to_cpu(u0->b),
383 (u64)dma_unmap_addr(tx_buffer, dma),
384 dma_unmap_len(tx_buffer, len),
385 tx_buffer->next_to_watch,
386 (u64)tx_buffer->time_stamp,
387 tx_buffer->skb);
388 if (i == tx_ring->next_to_use &&
389 i == tx_ring->next_to_clean)
390 pr_cont(" NTC/U\n");
391 else if (i == tx_ring->next_to_use)
392 pr_cont(" NTU\n");
393 else if (i == tx_ring->next_to_clean)
394 pr_cont(" NTC\n");
395 else
396 pr_cont("\n");
397
398 if (netif_msg_pktdata(adapter) &&
399 dma_unmap_len(tx_buffer, len) != 0)
400 print_hex_dump(KERN_INFO, "",
401 DUMP_PREFIX_ADDRESS, 16, 1,
402 phys_to_virt(dma_unmap_addr(tx_buffer,
403 dma)),
404 dma_unmap_len(tx_buffer, len),
405 true);
406 }
407 }
408
409 /* Print RX Rings Summary */
410 rx_ring_summary:
411 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
412 pr_info("Queue [NTU] [NTC]\n");
413 for (n = 0; n < adapter->num_rx_queues; n++) {
414 rx_ring = adapter->rx_ring[n];
415 pr_info("%5d %5X %5X\n",
416 n, rx_ring->next_to_use, rx_ring->next_to_clean);
417 }
418
419 /* Print RX Rings */
420 if (!netif_msg_rx_status(adapter))
421 goto exit;
422
423 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
424
425 /* Advanced Receive Descriptor (Read) Format
426 * 63 1 0
427 * +-----------------------------------------------------+
428 * 0 | Packet Buffer Address [63:1] |A0/NSE|
429 * +----------------------------------------------+------+
430 * 8 | Header Buffer Address [63:1] | DD |
431 * +-----------------------------------------------------+
432 *
433 *
434 * Advanced Receive Descriptor (Write-Back) Format
435 *
436 * 63 48 47 32 31 30 21 20 16 15 4 3 0
437 * +------------------------------------------------------+
438 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
439 * | Checksum Ident | | | | Type | Type |
440 * +------------------------------------------------------+
441 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
442 * +------------------------------------------------------+
443 * 63 48 47 32 31 20 19 0
444 */
445 for (n = 0; n < adapter->num_rx_queues; n++) {
446 rx_ring = adapter->rx_ring[n];
447 pr_info("------------------------------------\n");
448 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
449 pr_info("------------------------------------\n");
450 pr_info("R [desc] [ PktBuf A0] "
451 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
452 "<-- Adv Rx Read format\n");
453 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
454 "[vl er S cks ln] ---------------- [bi->skb] "
455 "<-- Adv Rx Write-Back format\n");
456
457 for (i = 0; i < rx_ring->count; i++) {
458 rx_buffer_info = &rx_ring->rx_buffer_info[i];
459 rx_desc = IXGBE_RX_DESC(rx_ring, i);
460 u0 = (struct my_u0 *)rx_desc;
461 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
462 if (staterr & IXGBE_RXD_STAT_DD) {
463 /* Descriptor Done */
464 pr_info("RWB[0x%03X] %016llX "
465 "%016llX ---------------- %p", i,
466 le64_to_cpu(u0->a),
467 le64_to_cpu(u0->b),
468 rx_buffer_info->skb);
469 } else {
470 pr_info("R [0x%03X] %016llX "
471 "%016llX %016llX %p", i,
472 le64_to_cpu(u0->a),
473 le64_to_cpu(u0->b),
474 (u64)rx_buffer_info->dma,
475 rx_buffer_info->skb);
476
477 if (netif_msg_pktdata(adapter)) {
478 print_hex_dump(KERN_INFO, "",
479 DUMP_PREFIX_ADDRESS, 16, 1,
480 phys_to_virt(rx_buffer_info->dma),
481 ixgbe_rx_bufsz(rx_ring), true);
482 }
483 }
484
485 if (i == rx_ring->next_to_use)
486 pr_cont(" NTU\n");
487 else if (i == rx_ring->next_to_clean)
488 pr_cont(" NTC\n");
489 else
490 pr_cont("\n");
491
492 }
493 }
494
495 exit:
496 return;
497 }
498
499 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
500 {
501 u32 ctrl_ext;
502
503 /* Let firmware take over control of h/w */
504 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
505 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
506 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
507 }
508
509 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
510 {
511 u32 ctrl_ext;
512
513 /* Let firmware know the driver has taken over */
514 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
515 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
516 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
517 }
518
519 /*
520 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
521 * @adapter: pointer to adapter struct
522 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
523 * @queue: queue to map the corresponding interrupt to
524 * @msix_vector: the vector to map to the corresponding queue
525 *
526 */
527 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
528 u8 queue, u8 msix_vector)
529 {
530 u32 ivar, index;
531 struct ixgbe_hw *hw = &adapter->hw;
532 switch (hw->mac.type) {
533 case ixgbe_mac_82598EB:
534 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
535 if (direction == -1)
536 direction = 0;
537 index = (((direction * 64) + queue) >> 2) & 0x1F;
538 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
539 ivar &= ~(0xFF << (8 * (queue & 0x3)));
540 ivar |= (msix_vector << (8 * (queue & 0x3)));
541 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
542 break;
543 case ixgbe_mac_82599EB:
544 case ixgbe_mac_X540:
545 if (direction == -1) {
546 /* other causes */
547 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
548 index = ((queue & 1) * 8);
549 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
550 ivar &= ~(0xFF << index);
551 ivar |= (msix_vector << index);
552 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
553 break;
554 } else {
555 /* tx or rx causes */
556 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
557 index = ((16 * (queue & 1)) + (8 * direction));
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
559 ivar &= ~(0xFF << index);
560 ivar |= (msix_vector << index);
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
562 break;
563 }
564 default:
565 break;
566 }
567 }
568
569 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
570 u64 qmask)
571 {
572 u32 mask;
573
574 switch (adapter->hw.mac.type) {
575 case ixgbe_mac_82598EB:
576 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
577 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
578 break;
579 case ixgbe_mac_82599EB:
580 case ixgbe_mac_X540:
581 mask = (qmask & 0xFFFFFFFF);
582 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
583 mask = (qmask >> 32);
584 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
585 break;
586 default:
587 break;
588 }
589 }
590
591 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
592 struct ixgbe_tx_buffer *tx_buffer)
593 {
594 if (tx_buffer->skb) {
595 dev_kfree_skb_any(tx_buffer->skb);
596 if (dma_unmap_len(tx_buffer, len))
597 dma_unmap_single(ring->dev,
598 dma_unmap_addr(tx_buffer, dma),
599 dma_unmap_len(tx_buffer, len),
600 DMA_TO_DEVICE);
601 } else if (dma_unmap_len(tx_buffer, len)) {
602 dma_unmap_page(ring->dev,
603 dma_unmap_addr(tx_buffer, dma),
604 dma_unmap_len(tx_buffer, len),
605 DMA_TO_DEVICE);
606 }
607 tx_buffer->next_to_watch = NULL;
608 tx_buffer->skb = NULL;
609 dma_unmap_len_set(tx_buffer, len, 0);
610 /* tx_buffer must be completely set up in the transmit path */
611 }
612
613 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
614 {
615 struct ixgbe_hw *hw = &adapter->hw;
616 struct ixgbe_hw_stats *hwstats = &adapter->stats;
617 u32 data = 0;
618 u32 xoff[8] = {0};
619 int i;
620
621 if ((hw->fc.current_mode == ixgbe_fc_full) ||
622 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
623 switch (hw->mac.type) {
624 case ixgbe_mac_82598EB:
625 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
626 break;
627 default:
628 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
629 }
630 hwstats->lxoffrxc += data;
631
632 /* refill credits (no tx hang) if we received xoff */
633 if (!data)
634 return;
635
636 for (i = 0; i < adapter->num_tx_queues; i++)
637 clear_bit(__IXGBE_HANG_CHECK_ARMED,
638 &adapter->tx_ring[i]->state);
639 return;
640 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
641 return;
642
643 /* update stats for each tc, only valid with PFC enabled */
644 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
645 switch (hw->mac.type) {
646 case ixgbe_mac_82598EB:
647 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
648 break;
649 default:
650 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
651 }
652 hwstats->pxoffrxc[i] += xoff[i];
653 }
654
655 /* disarm tx queues that have received xoff frames */
656 for (i = 0; i < adapter->num_tx_queues; i++) {
657 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
658 u8 tc = tx_ring->dcb_tc;
659
660 if (xoff[tc])
661 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
662 }
663 }
664
665 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
666 {
667 return ring->stats.packets;
668 }
669
670 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
671 {
672 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
673 struct ixgbe_hw *hw = &adapter->hw;
674
675 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
676 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
677
678 if (head != tail)
679 return (head < tail) ?
680 tail - head : (tail + ring->count - head);
681
682 return 0;
683 }
684
685 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
686 {
687 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
688 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
689 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
690 bool ret = false;
691
692 clear_check_for_tx_hang(tx_ring);
693
694 /*
695 * Check for a hung queue, but be thorough. This verifies
696 * that a transmit has been completed since the previous
697 * check AND there is at least one packet pending. The
698 * ARMED bit is set to indicate a potential hang. The
699 * bit is cleared if a pause frame is received to remove
700 * false hang detection due to PFC or 802.3x frames. By
701 * requiring this to fail twice we avoid races with
702 * pfc clearing the ARMED bit and conditions where we
703 * run the check_tx_hang logic with a transmit completion
704 * pending but without time to complete it yet.
705 */
706 if ((tx_done_old == tx_done) && tx_pending) {
707 /* make sure it is true for two checks in a row */
708 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
709 &tx_ring->state);
710 } else {
711 /* update completed stats and continue */
712 tx_ring->tx_stats.tx_done_old = tx_done;
713 /* reset the countdown */
714 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
715 }
716
717 return ret;
718 }
719
720 /**
721 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
722 * @adapter: driver private struct
723 **/
724 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
725 {
726
727 /* Do the reset outside of interrupt context */
728 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
729 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
730 ixgbe_service_event_schedule(adapter);
731 }
732 }
733
734 /**
735 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
736 * @q_vector: structure containing interrupt and ring information
737 * @tx_ring: tx ring to clean
738 **/
739 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
740 struct ixgbe_ring *tx_ring)
741 {
742 struct ixgbe_adapter *adapter = q_vector->adapter;
743 struct ixgbe_tx_buffer *tx_buffer;
744 union ixgbe_adv_tx_desc *tx_desc;
745 unsigned int total_bytes = 0, total_packets = 0;
746 unsigned int budget = q_vector->tx.work_limit;
747 unsigned int i = tx_ring->next_to_clean;
748
749 if (test_bit(__IXGBE_DOWN, &adapter->state))
750 return true;
751
752 tx_buffer = &tx_ring->tx_buffer_info[i];
753 tx_desc = IXGBE_TX_DESC(tx_ring, i);
754 i -= tx_ring->count;
755
756 do {
757 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
758
759 /* if next_to_watch is not set then there is no work pending */
760 if (!eop_desc)
761 break;
762
763 /* prevent any other reads prior to eop_desc */
764 rmb();
765
766 /* if DD is not set pending work has not been completed */
767 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
768 break;
769
770 /* clear next_to_watch to prevent false hangs */
771 tx_buffer->next_to_watch = NULL;
772
773 /* update the statistics for this packet */
774 total_bytes += tx_buffer->bytecount;
775 total_packets += tx_buffer->gso_segs;
776
777 /* free the skb */
778 dev_kfree_skb_any(tx_buffer->skb);
779
780 /* unmap skb header data */
781 dma_unmap_single(tx_ring->dev,
782 dma_unmap_addr(tx_buffer, dma),
783 dma_unmap_len(tx_buffer, len),
784 DMA_TO_DEVICE);
785
786 /* clear tx_buffer data */
787 tx_buffer->skb = NULL;
788 dma_unmap_len_set(tx_buffer, len, 0);
789
790 /* unmap remaining buffers */
791 while (tx_desc != eop_desc) {
792 tx_buffer++;
793 tx_desc++;
794 i++;
795 if (unlikely(!i)) {
796 i -= tx_ring->count;
797 tx_buffer = tx_ring->tx_buffer_info;
798 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
799 }
800
801 /* unmap any remaining paged data */
802 if (dma_unmap_len(tx_buffer, len)) {
803 dma_unmap_page(tx_ring->dev,
804 dma_unmap_addr(tx_buffer, dma),
805 dma_unmap_len(tx_buffer, len),
806 DMA_TO_DEVICE);
807 dma_unmap_len_set(tx_buffer, len, 0);
808 }
809 }
810
811 /* move us one more past the eop_desc for start of next pkt */
812 tx_buffer++;
813 tx_desc++;
814 i++;
815 if (unlikely(!i)) {
816 i -= tx_ring->count;
817 tx_buffer = tx_ring->tx_buffer_info;
818 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
819 }
820
821 /* issue prefetch for next Tx descriptor */
822 prefetch(tx_desc);
823
824 /* update budget accounting */
825 budget--;
826 } while (likely(budget));
827
828 i += tx_ring->count;
829 tx_ring->next_to_clean = i;
830 u64_stats_update_begin(&tx_ring->syncp);
831 tx_ring->stats.bytes += total_bytes;
832 tx_ring->stats.packets += total_packets;
833 u64_stats_update_end(&tx_ring->syncp);
834 q_vector->tx.total_bytes += total_bytes;
835 q_vector->tx.total_packets += total_packets;
836
837 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
838 /* schedule immediate reset if we believe we hung */
839 struct ixgbe_hw *hw = &adapter->hw;
840 e_err(drv, "Detected Tx Unit Hang\n"
841 " Tx Queue <%d>\n"
842 " TDH, TDT <%x>, <%x>\n"
843 " next_to_use <%x>\n"
844 " next_to_clean <%x>\n"
845 "tx_buffer_info[next_to_clean]\n"
846 " time_stamp <%lx>\n"
847 " jiffies <%lx>\n",
848 tx_ring->queue_index,
849 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
850 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
851 tx_ring->next_to_use, i,
852 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
853
854 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
855
856 e_info(probe,
857 "tx hang %d detected on queue %d, resetting adapter\n",
858 adapter->tx_timeout_count + 1, tx_ring->queue_index);
859
860 /* schedule immediate reset if we believe we hung */
861 ixgbe_tx_timeout_reset(adapter);
862
863 /* the adapter is about to reset, no point in enabling stuff */
864 return true;
865 }
866
867 netdev_tx_completed_queue(txring_txq(tx_ring),
868 total_packets, total_bytes);
869
870 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
871 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
872 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
873 /* Make sure that anybody stopping the queue after this
874 * sees the new next_to_clean.
875 */
876 smp_mb();
877 if (__netif_subqueue_stopped(tx_ring->netdev,
878 tx_ring->queue_index)
879 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
880 netif_wake_subqueue(tx_ring->netdev,
881 tx_ring->queue_index);
882 ++tx_ring->tx_stats.restart_queue;
883 }
884 }
885
886 return !!budget;
887 }
888
889 #ifdef CONFIG_IXGBE_DCA
890 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
891 struct ixgbe_ring *tx_ring,
892 int cpu)
893 {
894 struct ixgbe_hw *hw = &adapter->hw;
895 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
896 u16 reg_offset;
897
898 switch (hw->mac.type) {
899 case ixgbe_mac_82598EB:
900 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
901 break;
902 case ixgbe_mac_82599EB:
903 case ixgbe_mac_X540:
904 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
905 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
906 break;
907 default:
908 /* for unknown hardware do not write register */
909 return;
910 }
911
912 /*
913 * We can enable relaxed ordering for reads, but not writes when
914 * DCA is enabled. This is due to a known issue in some chipsets
915 * which will cause the DCA tag to be cleared.
916 */
917 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
918 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
919 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
920
921 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
922 }
923
924 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
925 struct ixgbe_ring *rx_ring,
926 int cpu)
927 {
928 struct ixgbe_hw *hw = &adapter->hw;
929 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
930 u8 reg_idx = rx_ring->reg_idx;
931
932
933 switch (hw->mac.type) {
934 case ixgbe_mac_82599EB:
935 case ixgbe_mac_X540:
936 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
937 break;
938 default:
939 break;
940 }
941
942 /*
943 * We can enable relaxed ordering for reads, but not writes when
944 * DCA is enabled. This is due to a known issue in some chipsets
945 * which will cause the DCA tag to be cleared.
946 */
947 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
948 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
949 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
950
951 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
952 }
953
954 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
955 {
956 struct ixgbe_adapter *adapter = q_vector->adapter;
957 struct ixgbe_ring *ring;
958 int cpu = get_cpu();
959
960 if (q_vector->cpu == cpu)
961 goto out_no_update;
962
963 ixgbe_for_each_ring(ring, q_vector->tx)
964 ixgbe_update_tx_dca(adapter, ring, cpu);
965
966 ixgbe_for_each_ring(ring, q_vector->rx)
967 ixgbe_update_rx_dca(adapter, ring, cpu);
968
969 q_vector->cpu = cpu;
970 out_no_update:
971 put_cpu();
972 }
973
974 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
975 {
976 int num_q_vectors;
977 int i;
978
979 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
980 return;
981
982 /* always use CB2 mode, difference is masked in the CB driver */
983 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
984
985 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
986 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
987 else
988 num_q_vectors = 1;
989
990 for (i = 0; i < num_q_vectors; i++) {
991 adapter->q_vector[i]->cpu = -1;
992 ixgbe_update_dca(adapter->q_vector[i]);
993 }
994 }
995
996 static int __ixgbe_notify_dca(struct device *dev, void *data)
997 {
998 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
999 unsigned long event = *(unsigned long *)data;
1000
1001 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1002 return 0;
1003
1004 switch (event) {
1005 case DCA_PROVIDER_ADD:
1006 /* if we're already enabled, don't do it again */
1007 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1008 break;
1009 if (dca_add_requester(dev) == 0) {
1010 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1011 ixgbe_setup_dca(adapter);
1012 break;
1013 }
1014 /* Fall Through since DCA is disabled. */
1015 case DCA_PROVIDER_REMOVE:
1016 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1017 dca_remove_requester(dev);
1018 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1019 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1020 }
1021 break;
1022 }
1023
1024 return 0;
1025 }
1026
1027 #endif /* CONFIG_IXGBE_DCA */
1028 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1029 union ixgbe_adv_rx_desc *rx_desc,
1030 struct sk_buff *skb)
1031 {
1032 if (ring->netdev->features & NETIF_F_RXHASH)
1033 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1034 }
1035
1036 #ifdef IXGBE_FCOE
1037 /**
1038 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1039 * @adapter: address of board private structure
1040 * @rx_desc: advanced rx descriptor
1041 *
1042 * Returns : true if it is FCoE pkt
1043 */
1044 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1045 union ixgbe_adv_rx_desc *rx_desc)
1046 {
1047 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1048
1049 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1050 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1051 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1052 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1053 }
1054
1055 #endif /* IXGBE_FCOE */
1056 /**
1057 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1058 * @ring: structure containing ring specific data
1059 * @rx_desc: current Rx descriptor being processed
1060 * @skb: skb currently being received and modified
1061 **/
1062 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1063 union ixgbe_adv_rx_desc *rx_desc,
1064 struct sk_buff *skb)
1065 {
1066 skb_checksum_none_assert(skb);
1067
1068 /* Rx csum disabled */
1069 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1070 return;
1071
1072 /* if IP and error */
1073 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1074 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1075 ring->rx_stats.csum_err++;
1076 return;
1077 }
1078
1079 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1080 return;
1081
1082 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1083 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1084
1085 /*
1086 * 82599 errata, UDP frames with a 0 checksum can be marked as
1087 * checksum errors.
1088 */
1089 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1090 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1091 return;
1092
1093 ring->rx_stats.csum_err++;
1094 return;
1095 }
1096
1097 /* It must be a TCP or UDP packet with a valid checksum */
1098 skb->ip_summed = CHECKSUM_UNNECESSARY;
1099 }
1100
1101 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1102 {
1103 rx_ring->next_to_use = val;
1104
1105 /* update next to alloc since we have filled the ring */
1106 rx_ring->next_to_alloc = val;
1107 /*
1108 * Force memory writes to complete before letting h/w
1109 * know there are new descriptors to fetch. (Only
1110 * applicable for weak-ordered memory model archs,
1111 * such as IA-64).
1112 */
1113 wmb();
1114 writel(val, rx_ring->tail);
1115 }
1116
1117 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1118 struct ixgbe_rx_buffer *bi)
1119 {
1120 struct page *page = bi->page;
1121 dma_addr_t dma = bi->dma;
1122
1123 /* since we are recycling buffers we should seldom need to alloc */
1124 if (likely(dma))
1125 return true;
1126
1127 /* alloc new page for storage */
1128 if (likely(!page)) {
1129 page = alloc_pages(GFP_ATOMIC | __GFP_COLD,
1130 ixgbe_rx_pg_order(rx_ring));
1131 if (unlikely(!page)) {
1132 rx_ring->rx_stats.alloc_rx_page_failed++;
1133 return false;
1134 }
1135 bi->page = page;
1136 }
1137
1138 /* map page for use */
1139 dma = dma_map_page(rx_ring->dev, page, 0,
1140 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1141
1142 /*
1143 * if mapping failed free memory back to system since
1144 * there isn't much point in holding memory we can't use
1145 */
1146 if (dma_mapping_error(rx_ring->dev, dma)) {
1147 put_page(page);
1148 bi->page = NULL;
1149
1150 rx_ring->rx_stats.alloc_rx_page_failed++;
1151 return false;
1152 }
1153
1154 bi->dma = dma;
1155 bi->page_offset ^= ixgbe_rx_bufsz(rx_ring);
1156
1157 return true;
1158 }
1159
1160 /**
1161 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1162 * @rx_ring: ring to place buffers on
1163 * @cleaned_count: number of buffers to replace
1164 **/
1165 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1166 {
1167 union ixgbe_adv_rx_desc *rx_desc;
1168 struct ixgbe_rx_buffer *bi;
1169 u16 i = rx_ring->next_to_use;
1170
1171 /* nothing to do */
1172 if (!cleaned_count)
1173 return;
1174
1175 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1176 bi = &rx_ring->rx_buffer_info[i];
1177 i -= rx_ring->count;
1178
1179 do {
1180 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1181 break;
1182
1183 /*
1184 * Refresh the desc even if buffer_addrs didn't change
1185 * because each write-back erases this info.
1186 */
1187 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1188
1189 rx_desc++;
1190 bi++;
1191 i++;
1192 if (unlikely(!i)) {
1193 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1194 bi = rx_ring->rx_buffer_info;
1195 i -= rx_ring->count;
1196 }
1197
1198 /* clear the hdr_addr for the next_to_use descriptor */
1199 rx_desc->read.hdr_addr = 0;
1200
1201 cleaned_count--;
1202 } while (cleaned_count);
1203
1204 i += rx_ring->count;
1205
1206 if (rx_ring->next_to_use != i)
1207 ixgbe_release_rx_desc(rx_ring, i);
1208 }
1209
1210 /**
1211 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1212 * @data: pointer to the start of the headers
1213 * @max_len: total length of section to find headers in
1214 *
1215 * This function is meant to determine the length of headers that will
1216 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1217 * motivation of doing this is to only perform one pull for IPv4 TCP
1218 * packets so that we can do basic things like calculating the gso_size
1219 * based on the average data per packet.
1220 **/
1221 static unsigned int ixgbe_get_headlen(unsigned char *data,
1222 unsigned int max_len)
1223 {
1224 union {
1225 unsigned char *network;
1226 /* l2 headers */
1227 struct ethhdr *eth;
1228 struct vlan_hdr *vlan;
1229 /* l3 headers */
1230 struct iphdr *ipv4;
1231 } hdr;
1232 __be16 protocol;
1233 u8 nexthdr = 0; /* default to not TCP */
1234 u8 hlen;
1235
1236 /* this should never happen, but better safe than sorry */
1237 if (max_len < ETH_HLEN)
1238 return max_len;
1239
1240 /* initialize network frame pointer */
1241 hdr.network = data;
1242
1243 /* set first protocol and move network header forward */
1244 protocol = hdr.eth->h_proto;
1245 hdr.network += ETH_HLEN;
1246
1247 /* handle any vlan tag if present */
1248 if (protocol == __constant_htons(ETH_P_8021Q)) {
1249 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1250 return max_len;
1251
1252 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1253 hdr.network += VLAN_HLEN;
1254 }
1255
1256 /* handle L3 protocols */
1257 if (protocol == __constant_htons(ETH_P_IP)) {
1258 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1259 return max_len;
1260
1261 /* access ihl as a u8 to avoid unaligned access on ia64 */
1262 hlen = (hdr.network[0] & 0x0F) << 2;
1263
1264 /* verify hlen meets minimum size requirements */
1265 if (hlen < sizeof(struct iphdr))
1266 return hdr.network - data;
1267
1268 /* record next protocol */
1269 nexthdr = hdr.ipv4->protocol;
1270 hdr.network += hlen;
1271 #ifdef IXGBE_FCOE
1272 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1273 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1274 return max_len;
1275 hdr.network += FCOE_HEADER_LEN;
1276 #endif
1277 } else {
1278 return hdr.network - data;
1279 }
1280
1281 /* finally sort out TCP */
1282 if (nexthdr == IPPROTO_TCP) {
1283 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1284 return max_len;
1285
1286 /* access doff as a u8 to avoid unaligned access on ia64 */
1287 hlen = (hdr.network[12] & 0xF0) >> 2;
1288
1289 /* verify hlen meets minimum size requirements */
1290 if (hlen < sizeof(struct tcphdr))
1291 return hdr.network - data;
1292
1293 hdr.network += hlen;
1294 }
1295
1296 /*
1297 * If everything has gone correctly hdr.network should be the
1298 * data section of the packet and will be the end of the header.
1299 * If not then it probably represents the end of the last recognized
1300 * header.
1301 */
1302 if ((hdr.network - data) < max_len)
1303 return hdr.network - data;
1304 else
1305 return max_len;
1306 }
1307
1308 static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1309 union ixgbe_adv_rx_desc *rx_desc,
1310 struct sk_buff *skb)
1311 {
1312 __le32 rsc_enabled;
1313 u32 rsc_cnt;
1314
1315 if (!ring_is_rsc_enabled(rx_ring))
1316 return;
1317
1318 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1319 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1320
1321 /* If this is an RSC frame rsc_cnt should be non-zero */
1322 if (!rsc_enabled)
1323 return;
1324
1325 rsc_cnt = le32_to_cpu(rsc_enabled);
1326 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1327
1328 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1329 }
1330
1331 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1332 struct sk_buff *skb)
1333 {
1334 u16 hdr_len = skb_headlen(skb);
1335
1336 /* set gso_size to avoid messing up TCP MSS */
1337 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1338 IXGBE_CB(skb)->append_cnt);
1339 }
1340
1341 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1342 struct sk_buff *skb)
1343 {
1344 /* if append_cnt is 0 then frame is not RSC */
1345 if (!IXGBE_CB(skb)->append_cnt)
1346 return;
1347
1348 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1349 rx_ring->rx_stats.rsc_flush++;
1350
1351 ixgbe_set_rsc_gso_size(rx_ring, skb);
1352
1353 /* gso_size is computed using append_cnt so always clear it last */
1354 IXGBE_CB(skb)->append_cnt = 0;
1355 }
1356
1357 /**
1358 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1359 * @rx_ring: rx descriptor ring packet is being transacted on
1360 * @rx_desc: pointer to the EOP Rx descriptor
1361 * @skb: pointer to current skb being populated
1362 *
1363 * This function checks the ring, descriptor, and packet information in
1364 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1365 * other fields within the skb.
1366 **/
1367 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1368 union ixgbe_adv_rx_desc *rx_desc,
1369 struct sk_buff *skb)
1370 {
1371 ixgbe_update_rsc_stats(rx_ring, skb);
1372
1373 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1374
1375 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1376
1377 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1378 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1379 __vlan_hwaccel_put_tag(skb, vid);
1380 }
1381
1382 skb_record_rx_queue(skb, rx_ring->queue_index);
1383
1384 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1385 }
1386
1387 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1388 struct sk_buff *skb)
1389 {
1390 struct ixgbe_adapter *adapter = q_vector->adapter;
1391
1392 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1393 napi_gro_receive(&q_vector->napi, skb);
1394 else
1395 netif_rx(skb);
1396 }
1397
1398 /**
1399 * ixgbe_is_non_eop - process handling of non-EOP buffers
1400 * @rx_ring: Rx ring being processed
1401 * @rx_desc: Rx descriptor for current buffer
1402 * @skb: Current socket buffer containing buffer in progress
1403 *
1404 * This function updates next to clean. If the buffer is an EOP buffer
1405 * this function exits returning false, otherwise it will place the
1406 * sk_buff in the next buffer to be chained and return true indicating
1407 * that this is in fact a non-EOP buffer.
1408 **/
1409 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1410 union ixgbe_adv_rx_desc *rx_desc,
1411 struct sk_buff *skb)
1412 {
1413 u32 ntc = rx_ring->next_to_clean + 1;
1414
1415 /* fetch, update, and store next to clean */
1416 ntc = (ntc < rx_ring->count) ? ntc : 0;
1417 rx_ring->next_to_clean = ntc;
1418
1419 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1420
1421 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1422 return false;
1423
1424 /* append_cnt indicates packet is RSC, if so fetch nextp */
1425 if (IXGBE_CB(skb)->append_cnt) {
1426 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1427 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1428 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1429 }
1430
1431 /* place skb in next buffer to be received */
1432 rx_ring->rx_buffer_info[ntc].skb = skb;
1433 rx_ring->rx_stats.non_eop_descs++;
1434
1435 return true;
1436 }
1437
1438 /**
1439 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1440 * @rx_ring: rx descriptor ring packet is being transacted on
1441 * @rx_desc: pointer to the EOP Rx descriptor
1442 * @skb: pointer to current skb being fixed
1443 *
1444 * Check for corrupted packet headers caused by senders on the local L2
1445 * embedded NIC switch not setting up their Tx Descriptors right. These
1446 * should be very rare.
1447 *
1448 * Also address the case where we are pulling data in on pages only
1449 * and as such no data is present in the skb header.
1450 *
1451 * In addition if skb is not at least 60 bytes we need to pad it so that
1452 * it is large enough to qualify as a valid Ethernet frame.
1453 *
1454 * Returns true if an error was encountered and skb was freed.
1455 **/
1456 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1457 union ixgbe_adv_rx_desc *rx_desc,
1458 struct sk_buff *skb)
1459 {
1460 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1461 struct net_device *netdev = rx_ring->netdev;
1462 unsigned char *va;
1463 unsigned int pull_len;
1464
1465 /* if the page was released unmap it, else just sync our portion */
1466 if (unlikely(IXGBE_CB(skb)->page_released)) {
1467 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1468 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1469 IXGBE_CB(skb)->page_released = false;
1470 } else {
1471 dma_sync_single_range_for_cpu(rx_ring->dev,
1472 IXGBE_CB(skb)->dma,
1473 frag->page_offset,
1474 ixgbe_rx_bufsz(rx_ring),
1475 DMA_FROM_DEVICE);
1476 }
1477 IXGBE_CB(skb)->dma = 0;
1478
1479 /* verify that the packet does not have any known errors */
1480 if (unlikely(ixgbe_test_staterr(rx_desc,
1481 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1482 !(netdev->features & NETIF_F_RXALL))) {
1483 dev_kfree_skb_any(skb);
1484 return true;
1485 }
1486
1487 /*
1488 * it is valid to use page_address instead of kmap since we are
1489 * working with pages allocated out of the lomem pool per
1490 * alloc_page(GFP_ATOMIC)
1491 */
1492 va = skb_frag_address(frag);
1493
1494 /*
1495 * we need the header to contain the greater of either ETH_HLEN or
1496 * 60 bytes if the skb->len is less than 60 for skb_pad.
1497 */
1498 pull_len = skb_frag_size(frag);
1499 if (pull_len > 256)
1500 pull_len = ixgbe_get_headlen(va, pull_len);
1501
1502 /* align pull length to size of long to optimize memcpy performance */
1503 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1504
1505 /* update all of the pointers */
1506 skb_frag_size_sub(frag, pull_len);
1507 frag->page_offset += pull_len;
1508 skb->data_len -= pull_len;
1509 skb->tail += pull_len;
1510
1511 /*
1512 * if we sucked the frag empty then we should free it,
1513 * if there are other frags here something is screwed up in hardware
1514 */
1515 if (skb_frag_size(frag) == 0) {
1516 BUG_ON(skb_shinfo(skb)->nr_frags != 1);
1517 skb_shinfo(skb)->nr_frags = 0;
1518 __skb_frag_unref(frag);
1519 skb->truesize -= ixgbe_rx_bufsz(rx_ring);
1520 }
1521
1522 /* if skb_pad returns an error the skb was freed */
1523 if (unlikely(skb->len < 60)) {
1524 int pad_len = 60 - skb->len;
1525
1526 if (skb_pad(skb, pad_len))
1527 return true;
1528 __skb_put(skb, pad_len);
1529 }
1530
1531 return false;
1532 }
1533
1534 /**
1535 * ixgbe_can_reuse_page - determine if we can reuse a page
1536 * @rx_buffer: pointer to rx_buffer containing the page we want to reuse
1537 *
1538 * Returns true if page can be reused in another Rx buffer
1539 **/
1540 static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer)
1541 {
1542 struct page *page = rx_buffer->page;
1543
1544 /* if we are only owner of page and it is local we can reuse it */
1545 return likely(page_count(page) == 1) &&
1546 likely(page_to_nid(page) == numa_node_id());
1547 }
1548
1549 /**
1550 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1551 * @rx_ring: rx descriptor ring to store buffers on
1552 * @old_buff: donor buffer to have page reused
1553 *
1554 * Syncronizes page for reuse by the adapter
1555 **/
1556 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1557 struct ixgbe_rx_buffer *old_buff)
1558 {
1559 struct ixgbe_rx_buffer *new_buff;
1560 u16 nta = rx_ring->next_to_alloc;
1561 u16 bufsz = ixgbe_rx_bufsz(rx_ring);
1562
1563 new_buff = &rx_ring->rx_buffer_info[nta];
1564
1565 /* update, and store next to alloc */
1566 nta++;
1567 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1568
1569 /* transfer page from old buffer to new buffer */
1570 new_buff->page = old_buff->page;
1571 new_buff->dma = old_buff->dma;
1572
1573 /* flip page offset to other buffer and store to new_buff */
1574 new_buff->page_offset = old_buff->page_offset ^ bufsz;
1575
1576 /* sync the buffer for use by the device */
1577 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1578 new_buff->page_offset, bufsz,
1579 DMA_FROM_DEVICE);
1580
1581 /* bump ref count on page before it is given to the stack */
1582 get_page(new_buff->page);
1583 }
1584
1585 /**
1586 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1587 * @rx_ring: rx descriptor ring to transact packets on
1588 * @rx_buffer: buffer containing page to add
1589 * @rx_desc: descriptor containing length of buffer written by hardware
1590 * @skb: sk_buff to place the data into
1591 *
1592 * This function is based on skb_add_rx_frag. I would have used that
1593 * function however it doesn't handle the truesize case correctly since we
1594 * are allocating more memory than might be used for a single receive.
1595 **/
1596 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1597 struct ixgbe_rx_buffer *rx_buffer,
1598 struct sk_buff *skb, int size)
1599 {
1600 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1601 rx_buffer->page, rx_buffer->page_offset,
1602 size);
1603 skb->len += size;
1604 skb->data_len += size;
1605 skb->truesize += ixgbe_rx_bufsz(rx_ring);
1606 }
1607
1608 /**
1609 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1610 * @q_vector: structure containing interrupt and ring information
1611 * @rx_ring: rx descriptor ring to transact packets on
1612 * @budget: Total limit on number of packets to process
1613 *
1614 * This function provides a "bounce buffer" approach to Rx interrupt
1615 * processing. The advantage to this is that on systems that have
1616 * expensive overhead for IOMMU access this provides a means of avoiding
1617 * it by maintaining the mapping of the page to the syste.
1618 *
1619 * Returns true if all work is completed without reaching budget
1620 **/
1621 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1622 struct ixgbe_ring *rx_ring,
1623 int budget)
1624 {
1625 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1626 #ifdef IXGBE_FCOE
1627 struct ixgbe_adapter *adapter = q_vector->adapter;
1628 int ddp_bytes = 0;
1629 #endif /* IXGBE_FCOE */
1630 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1631
1632 do {
1633 struct ixgbe_rx_buffer *rx_buffer;
1634 union ixgbe_adv_rx_desc *rx_desc;
1635 struct sk_buff *skb;
1636 struct page *page;
1637 u16 ntc;
1638
1639 /* return some buffers to hardware, one at a time is too slow */
1640 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1641 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1642 cleaned_count = 0;
1643 }
1644
1645 ntc = rx_ring->next_to_clean;
1646 rx_desc = IXGBE_RX_DESC(rx_ring, ntc);
1647 rx_buffer = &rx_ring->rx_buffer_info[ntc];
1648
1649 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1650 break;
1651
1652 /*
1653 * This memory barrier is needed to keep us from reading
1654 * any other fields out of the rx_desc until we know the
1655 * RXD_STAT_DD bit is set
1656 */
1657 rmb();
1658
1659 page = rx_buffer->page;
1660 prefetchw(page);
1661
1662 skb = rx_buffer->skb;
1663
1664 if (likely(!skb)) {
1665 void *page_addr = page_address(page) +
1666 rx_buffer->page_offset;
1667
1668 /* prefetch first cache line of first page */
1669 prefetch(page_addr);
1670 #if L1_CACHE_BYTES < 128
1671 prefetch(page_addr + L1_CACHE_BYTES);
1672 #endif
1673
1674 /* allocate a skb to store the frags */
1675 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1676 IXGBE_RX_HDR_SIZE);
1677 if (unlikely(!skb)) {
1678 rx_ring->rx_stats.alloc_rx_buff_failed++;
1679 break;
1680 }
1681
1682 /*
1683 * we will be copying header into skb->data in
1684 * pskb_may_pull so it is in our interest to prefetch
1685 * it now to avoid a possible cache miss
1686 */
1687 prefetchw(skb->data);
1688
1689 /*
1690 * Delay unmapping of the first packet. It carries the
1691 * header information, HW may still access the header
1692 * after the writeback. Only unmap it when EOP is
1693 * reached
1694 */
1695 IXGBE_CB(skb)->dma = rx_buffer->dma;
1696 } else {
1697 /* we are reusing so sync this buffer for CPU use */
1698 dma_sync_single_range_for_cpu(rx_ring->dev,
1699 rx_buffer->dma,
1700 rx_buffer->page_offset,
1701 ixgbe_rx_bufsz(rx_ring),
1702 DMA_FROM_DEVICE);
1703 }
1704
1705 /* pull page into skb */
1706 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb,
1707 le16_to_cpu(rx_desc->wb.upper.length));
1708
1709 if (ixgbe_can_reuse_page(rx_buffer)) {
1710 /* hand second half of page back to the ring */
1711 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1712 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1713 /* the page has been released from the ring */
1714 IXGBE_CB(skb)->page_released = true;
1715 } else {
1716 /* we are not reusing the buffer so unmap it */
1717 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1718 ixgbe_rx_pg_size(rx_ring),
1719 DMA_FROM_DEVICE);
1720 }
1721
1722 /* clear contents of buffer_info */
1723 rx_buffer->skb = NULL;
1724 rx_buffer->dma = 0;
1725 rx_buffer->page = NULL;
1726
1727 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
1728
1729 cleaned_count++;
1730
1731 /* place incomplete frames back on ring for completion */
1732 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1733 continue;
1734
1735 /* verify the packet layout is correct */
1736 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1737 continue;
1738
1739 /* probably a little skewed due to removing CRC */
1740 total_rx_bytes += skb->len;
1741 total_rx_packets++;
1742
1743 /* populate checksum, timestamp, VLAN, and protocol */
1744 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1745
1746 #ifdef IXGBE_FCOE
1747 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1748 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1749 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1750 if (!ddp_bytes) {
1751 dev_kfree_skb_any(skb);
1752 continue;
1753 }
1754 }
1755
1756 #endif /* IXGBE_FCOE */
1757 ixgbe_rx_skb(q_vector, skb);
1758
1759 /* update budget accounting */
1760 budget--;
1761 } while (likely(budget));
1762
1763 #ifdef IXGBE_FCOE
1764 /* include DDPed FCoE data */
1765 if (ddp_bytes > 0) {
1766 unsigned int mss;
1767
1768 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1769 sizeof(struct fc_frame_header) -
1770 sizeof(struct fcoe_crc_eof);
1771 if (mss > 512)
1772 mss &= ~511;
1773 total_rx_bytes += ddp_bytes;
1774 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1775 }
1776
1777 #endif /* IXGBE_FCOE */
1778 u64_stats_update_begin(&rx_ring->syncp);
1779 rx_ring->stats.packets += total_rx_packets;
1780 rx_ring->stats.bytes += total_rx_bytes;
1781 u64_stats_update_end(&rx_ring->syncp);
1782 q_vector->rx.total_packets += total_rx_packets;
1783 q_vector->rx.total_bytes += total_rx_bytes;
1784
1785 if (cleaned_count)
1786 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1787
1788 return !!budget;
1789 }
1790
1791 /**
1792 * ixgbe_configure_msix - Configure MSI-X hardware
1793 * @adapter: board private structure
1794 *
1795 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1796 * interrupts.
1797 **/
1798 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1799 {
1800 struct ixgbe_q_vector *q_vector;
1801 int q_vectors, v_idx;
1802 u32 mask;
1803
1804 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1805
1806 /* Populate MSIX to EITR Select */
1807 if (adapter->num_vfs > 32) {
1808 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1809 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1810 }
1811
1812 /*
1813 * Populate the IVAR table and set the ITR values to the
1814 * corresponding register.
1815 */
1816 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1817 struct ixgbe_ring *ring;
1818 q_vector = adapter->q_vector[v_idx];
1819
1820 ixgbe_for_each_ring(ring, q_vector->rx)
1821 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1822
1823 ixgbe_for_each_ring(ring, q_vector->tx)
1824 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1825
1826 if (q_vector->tx.ring && !q_vector->rx.ring) {
1827 /* tx only vector */
1828 if (adapter->tx_itr_setting == 1)
1829 q_vector->itr = IXGBE_10K_ITR;
1830 else
1831 q_vector->itr = adapter->tx_itr_setting;
1832 } else {
1833 /* rx or rx/tx vector */
1834 if (adapter->rx_itr_setting == 1)
1835 q_vector->itr = IXGBE_20K_ITR;
1836 else
1837 q_vector->itr = adapter->rx_itr_setting;
1838 }
1839
1840 ixgbe_write_eitr(q_vector);
1841 }
1842
1843 switch (adapter->hw.mac.type) {
1844 case ixgbe_mac_82598EB:
1845 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1846 v_idx);
1847 break;
1848 case ixgbe_mac_82599EB:
1849 case ixgbe_mac_X540:
1850 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1851 break;
1852 default:
1853 break;
1854 }
1855 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1856
1857 /* set up to autoclear timer, and the vectors */
1858 mask = IXGBE_EIMS_ENABLE_MASK;
1859 mask &= ~(IXGBE_EIMS_OTHER |
1860 IXGBE_EIMS_MAILBOX |
1861 IXGBE_EIMS_LSC);
1862
1863 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1864 }
1865
1866 enum latency_range {
1867 lowest_latency = 0,
1868 low_latency = 1,
1869 bulk_latency = 2,
1870 latency_invalid = 255
1871 };
1872
1873 /**
1874 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1875 * @q_vector: structure containing interrupt and ring information
1876 * @ring_container: structure containing ring performance data
1877 *
1878 * Stores a new ITR value based on packets and byte
1879 * counts during the last interrupt. The advantage of per interrupt
1880 * computation is faster updates and more accurate ITR for the current
1881 * traffic pattern. Constants in this function were computed
1882 * based on theoretical maximum wire speed and thresholds were set based
1883 * on testing data as well as attempting to minimize response time
1884 * while increasing bulk throughput.
1885 * this functionality is controlled by the InterruptThrottleRate module
1886 * parameter (see ixgbe_param.c)
1887 **/
1888 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1889 struct ixgbe_ring_container *ring_container)
1890 {
1891 int bytes = ring_container->total_bytes;
1892 int packets = ring_container->total_packets;
1893 u32 timepassed_us;
1894 u64 bytes_perint;
1895 u8 itr_setting = ring_container->itr;
1896
1897 if (packets == 0)
1898 return;
1899
1900 /* simple throttlerate management
1901 * 0-10MB/s lowest (100000 ints/s)
1902 * 10-20MB/s low (20000 ints/s)
1903 * 20-1249MB/s bulk (8000 ints/s)
1904 */
1905 /* what was last interrupt timeslice? */
1906 timepassed_us = q_vector->itr >> 2;
1907 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1908
1909 switch (itr_setting) {
1910 case lowest_latency:
1911 if (bytes_perint > 10)
1912 itr_setting = low_latency;
1913 break;
1914 case low_latency:
1915 if (bytes_perint > 20)
1916 itr_setting = bulk_latency;
1917 else if (bytes_perint <= 10)
1918 itr_setting = lowest_latency;
1919 break;
1920 case bulk_latency:
1921 if (bytes_perint <= 20)
1922 itr_setting = low_latency;
1923 break;
1924 }
1925
1926 /* clear work counters since we have the values we need */
1927 ring_container->total_bytes = 0;
1928 ring_container->total_packets = 0;
1929
1930 /* write updated itr to ring container */
1931 ring_container->itr = itr_setting;
1932 }
1933
1934 /**
1935 * ixgbe_write_eitr - write EITR register in hardware specific way
1936 * @q_vector: structure containing interrupt and ring information
1937 *
1938 * This function is made to be called by ethtool and by the driver
1939 * when it needs to update EITR registers at runtime. Hardware
1940 * specific quirks/differences are taken care of here.
1941 */
1942 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1943 {
1944 struct ixgbe_adapter *adapter = q_vector->adapter;
1945 struct ixgbe_hw *hw = &adapter->hw;
1946 int v_idx = q_vector->v_idx;
1947 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
1948
1949 switch (adapter->hw.mac.type) {
1950 case ixgbe_mac_82598EB:
1951 /* must write high and low 16 bits to reset counter */
1952 itr_reg |= (itr_reg << 16);
1953 break;
1954 case ixgbe_mac_82599EB:
1955 case ixgbe_mac_X540:
1956 /*
1957 * set the WDIS bit to not clear the timer bits and cause an
1958 * immediate assertion of the interrupt
1959 */
1960 itr_reg |= IXGBE_EITR_CNT_WDIS;
1961 break;
1962 default:
1963 break;
1964 }
1965 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1966 }
1967
1968 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1969 {
1970 u32 new_itr = q_vector->itr;
1971 u8 current_itr;
1972
1973 ixgbe_update_itr(q_vector, &q_vector->tx);
1974 ixgbe_update_itr(q_vector, &q_vector->rx);
1975
1976 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1977
1978 switch (current_itr) {
1979 /* counts and packets in update_itr are dependent on these numbers */
1980 case lowest_latency:
1981 new_itr = IXGBE_100K_ITR;
1982 break;
1983 case low_latency:
1984 new_itr = IXGBE_20K_ITR;
1985 break;
1986 case bulk_latency:
1987 new_itr = IXGBE_8K_ITR;
1988 break;
1989 default:
1990 break;
1991 }
1992
1993 if (new_itr != q_vector->itr) {
1994 /* do an exponential smoothing */
1995 new_itr = (10 * new_itr * q_vector->itr) /
1996 ((9 * new_itr) + q_vector->itr);
1997
1998 /* save the algorithm value here */
1999 q_vector->itr = new_itr;
2000
2001 ixgbe_write_eitr(q_vector);
2002 }
2003 }
2004
2005 /**
2006 * ixgbe_check_overtemp_subtask - check for over temperature
2007 * @adapter: pointer to adapter
2008 **/
2009 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2010 {
2011 struct ixgbe_hw *hw = &adapter->hw;
2012 u32 eicr = adapter->interrupt_event;
2013
2014 if (test_bit(__IXGBE_DOWN, &adapter->state))
2015 return;
2016
2017 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2018 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2019 return;
2020
2021 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2022
2023 switch (hw->device_id) {
2024 case IXGBE_DEV_ID_82599_T3_LOM:
2025 /*
2026 * Since the warning interrupt is for both ports
2027 * we don't have to check if:
2028 * - This interrupt wasn't for our port.
2029 * - We may have missed the interrupt so always have to
2030 * check if we got a LSC
2031 */
2032 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2033 !(eicr & IXGBE_EICR_LSC))
2034 return;
2035
2036 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2037 u32 autoneg;
2038 bool link_up = false;
2039
2040 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2041
2042 if (link_up)
2043 return;
2044 }
2045
2046 /* Check if this is not due to overtemp */
2047 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2048 return;
2049
2050 break;
2051 default:
2052 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2053 return;
2054 break;
2055 }
2056 e_crit(drv,
2057 "Network adapter has been stopped because it has over heated. "
2058 "Restart the computer. If the problem persists, "
2059 "power off the system and replace the adapter\n");
2060
2061 adapter->interrupt_event = 0;
2062 }
2063
2064 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2065 {
2066 struct ixgbe_hw *hw = &adapter->hw;
2067
2068 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2069 (eicr & IXGBE_EICR_GPI_SDP1)) {
2070 e_crit(probe, "Fan has stopped, replace the adapter\n");
2071 /* write to clear the interrupt */
2072 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2073 }
2074 }
2075
2076 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2077 {
2078 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2079 return;
2080
2081 switch (adapter->hw.mac.type) {
2082 case ixgbe_mac_82599EB:
2083 /*
2084 * Need to check link state so complete overtemp check
2085 * on service task
2086 */
2087 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2088 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2089 adapter->interrupt_event = eicr;
2090 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2091 ixgbe_service_event_schedule(adapter);
2092 return;
2093 }
2094 return;
2095 case ixgbe_mac_X540:
2096 if (!(eicr & IXGBE_EICR_TS))
2097 return;
2098 break;
2099 default:
2100 return;
2101 }
2102
2103 e_crit(drv,
2104 "Network adapter has been stopped because it has over heated. "
2105 "Restart the computer. If the problem persists, "
2106 "power off the system and replace the adapter\n");
2107 }
2108
2109 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2110 {
2111 struct ixgbe_hw *hw = &adapter->hw;
2112
2113 if (eicr & IXGBE_EICR_GPI_SDP2) {
2114 /* Clear the interrupt */
2115 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2116 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2117 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2118 ixgbe_service_event_schedule(adapter);
2119 }
2120 }
2121
2122 if (eicr & IXGBE_EICR_GPI_SDP1) {
2123 /* Clear the interrupt */
2124 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2125 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2126 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2127 ixgbe_service_event_schedule(adapter);
2128 }
2129 }
2130 }
2131
2132 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2133 {
2134 struct ixgbe_hw *hw = &adapter->hw;
2135
2136 adapter->lsc_int++;
2137 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2138 adapter->link_check_timeout = jiffies;
2139 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2140 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2141 IXGBE_WRITE_FLUSH(hw);
2142 ixgbe_service_event_schedule(adapter);
2143 }
2144 }
2145
2146 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2147 u64 qmask)
2148 {
2149 u32 mask;
2150 struct ixgbe_hw *hw = &adapter->hw;
2151
2152 switch (hw->mac.type) {
2153 case ixgbe_mac_82598EB:
2154 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2155 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2156 break;
2157 case ixgbe_mac_82599EB:
2158 case ixgbe_mac_X540:
2159 mask = (qmask & 0xFFFFFFFF);
2160 if (mask)
2161 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2162 mask = (qmask >> 32);
2163 if (mask)
2164 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2165 break;
2166 default:
2167 break;
2168 }
2169 /* skip the flush */
2170 }
2171
2172 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2173 u64 qmask)
2174 {
2175 u32 mask;
2176 struct ixgbe_hw *hw = &adapter->hw;
2177
2178 switch (hw->mac.type) {
2179 case ixgbe_mac_82598EB:
2180 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2181 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2182 break;
2183 case ixgbe_mac_82599EB:
2184 case ixgbe_mac_X540:
2185 mask = (qmask & 0xFFFFFFFF);
2186 if (mask)
2187 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2188 mask = (qmask >> 32);
2189 if (mask)
2190 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2191 break;
2192 default:
2193 break;
2194 }
2195 /* skip the flush */
2196 }
2197
2198 /**
2199 * ixgbe_irq_enable - Enable default interrupt generation settings
2200 * @adapter: board private structure
2201 **/
2202 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2203 bool flush)
2204 {
2205 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2206
2207 /* don't reenable LSC while waiting for link */
2208 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2209 mask &= ~IXGBE_EIMS_LSC;
2210
2211 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2212 switch (adapter->hw.mac.type) {
2213 case ixgbe_mac_82599EB:
2214 mask |= IXGBE_EIMS_GPI_SDP0;
2215 break;
2216 case ixgbe_mac_X540:
2217 mask |= IXGBE_EIMS_TS;
2218 break;
2219 default:
2220 break;
2221 }
2222 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2223 mask |= IXGBE_EIMS_GPI_SDP1;
2224 switch (adapter->hw.mac.type) {
2225 case ixgbe_mac_82599EB:
2226 mask |= IXGBE_EIMS_GPI_SDP1;
2227 mask |= IXGBE_EIMS_GPI_SDP2;
2228 case ixgbe_mac_X540:
2229 mask |= IXGBE_EIMS_ECC;
2230 mask |= IXGBE_EIMS_MAILBOX;
2231 break;
2232 default:
2233 break;
2234 }
2235 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2236 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2237 mask |= IXGBE_EIMS_FLOW_DIR;
2238
2239 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2240 if (queues)
2241 ixgbe_irq_enable_queues(adapter, ~0);
2242 if (flush)
2243 IXGBE_WRITE_FLUSH(&adapter->hw);
2244 }
2245
2246 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2247 {
2248 struct ixgbe_adapter *adapter = data;
2249 struct ixgbe_hw *hw = &adapter->hw;
2250 u32 eicr;
2251
2252 /*
2253 * Workaround for Silicon errata. Use clear-by-write instead
2254 * of clear-by-read. Reading with EICS will return the
2255 * interrupt causes without clearing, which later be done
2256 * with the write to EICR.
2257 */
2258 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2259 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2260
2261 if (eicr & IXGBE_EICR_LSC)
2262 ixgbe_check_lsc(adapter);
2263
2264 if (eicr & IXGBE_EICR_MAILBOX)
2265 ixgbe_msg_task(adapter);
2266
2267 switch (hw->mac.type) {
2268 case ixgbe_mac_82599EB:
2269 case ixgbe_mac_X540:
2270 if (eicr & IXGBE_EICR_ECC)
2271 e_info(link, "Received unrecoverable ECC Err, please "
2272 "reboot\n");
2273 /* Handle Flow Director Full threshold interrupt */
2274 if (eicr & IXGBE_EICR_FLOW_DIR) {
2275 int reinit_count = 0;
2276 int i;
2277 for (i = 0; i < adapter->num_tx_queues; i++) {
2278 struct ixgbe_ring *ring = adapter->tx_ring[i];
2279 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2280 &ring->state))
2281 reinit_count++;
2282 }
2283 if (reinit_count) {
2284 /* no more flow director interrupts until after init */
2285 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2286 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2287 ixgbe_service_event_schedule(adapter);
2288 }
2289 }
2290 ixgbe_check_sfp_event(adapter, eicr);
2291 ixgbe_check_overtemp_event(adapter, eicr);
2292 break;
2293 default:
2294 break;
2295 }
2296
2297 ixgbe_check_fan_failure(adapter, eicr);
2298
2299 /* re-enable the original interrupt state, no lsc, no queues */
2300 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2301 ixgbe_irq_enable(adapter, false, false);
2302
2303 return IRQ_HANDLED;
2304 }
2305
2306 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2307 {
2308 struct ixgbe_q_vector *q_vector = data;
2309
2310 /* EIAM disabled interrupts (on this vector) for us */
2311
2312 if (q_vector->rx.ring || q_vector->tx.ring)
2313 napi_schedule(&q_vector->napi);
2314
2315 return IRQ_HANDLED;
2316 }
2317
2318 /**
2319 * ixgbe_poll - NAPI Rx polling callback
2320 * @napi: structure for representing this polling device
2321 * @budget: how many packets driver is allowed to clean
2322 *
2323 * This function is used for legacy and MSI, NAPI mode
2324 **/
2325 int ixgbe_poll(struct napi_struct *napi, int budget)
2326 {
2327 struct ixgbe_q_vector *q_vector =
2328 container_of(napi, struct ixgbe_q_vector, napi);
2329 struct ixgbe_adapter *adapter = q_vector->adapter;
2330 struct ixgbe_ring *ring;
2331 int per_ring_budget;
2332 bool clean_complete = true;
2333
2334 #ifdef CONFIG_IXGBE_DCA
2335 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2336 ixgbe_update_dca(q_vector);
2337 #endif
2338
2339 ixgbe_for_each_ring(ring, q_vector->tx)
2340 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2341
2342 /* attempt to distribute budget to each queue fairly, but don't allow
2343 * the budget to go below 1 because we'll exit polling */
2344 if (q_vector->rx.count > 1)
2345 per_ring_budget = max(budget/q_vector->rx.count, 1);
2346 else
2347 per_ring_budget = budget;
2348
2349 ixgbe_for_each_ring(ring, q_vector->rx)
2350 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2351 per_ring_budget);
2352
2353 /* If all work not completed, return budget and keep polling */
2354 if (!clean_complete)
2355 return budget;
2356
2357 /* all work done, exit the polling mode */
2358 napi_complete(napi);
2359 if (adapter->rx_itr_setting & 1)
2360 ixgbe_set_itr(q_vector);
2361 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2362 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2363
2364 return 0;
2365 }
2366
2367 /**
2368 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2369 * @adapter: board private structure
2370 *
2371 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2372 * interrupts from the kernel.
2373 **/
2374 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2375 {
2376 struct net_device *netdev = adapter->netdev;
2377 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2378 int vector, err;
2379 int ri = 0, ti = 0;
2380
2381 for (vector = 0; vector < q_vectors; vector++) {
2382 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2383 struct msix_entry *entry = &adapter->msix_entries[vector];
2384
2385 if (q_vector->tx.ring && q_vector->rx.ring) {
2386 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2387 "%s-%s-%d", netdev->name, "TxRx", ri++);
2388 ti++;
2389 } else if (q_vector->rx.ring) {
2390 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2391 "%s-%s-%d", netdev->name, "rx", ri++);
2392 } else if (q_vector->tx.ring) {
2393 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2394 "%s-%s-%d", netdev->name, "tx", ti++);
2395 } else {
2396 /* skip this unused q_vector */
2397 continue;
2398 }
2399 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2400 q_vector->name, q_vector);
2401 if (err) {
2402 e_err(probe, "request_irq failed for MSIX interrupt "
2403 "Error: %d\n", err);
2404 goto free_queue_irqs;
2405 }
2406 /* If Flow Director is enabled, set interrupt affinity */
2407 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2408 /* assign the mask for this irq */
2409 irq_set_affinity_hint(entry->vector,
2410 &q_vector->affinity_mask);
2411 }
2412 }
2413
2414 err = request_irq(adapter->msix_entries[vector].vector,
2415 ixgbe_msix_other, 0, netdev->name, adapter);
2416 if (err) {
2417 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2418 goto free_queue_irqs;
2419 }
2420
2421 return 0;
2422
2423 free_queue_irqs:
2424 while (vector) {
2425 vector--;
2426 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2427 NULL);
2428 free_irq(adapter->msix_entries[vector].vector,
2429 adapter->q_vector[vector]);
2430 }
2431 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2432 pci_disable_msix(adapter->pdev);
2433 kfree(adapter->msix_entries);
2434 adapter->msix_entries = NULL;
2435 return err;
2436 }
2437
2438 /**
2439 * ixgbe_intr - legacy mode Interrupt Handler
2440 * @irq: interrupt number
2441 * @data: pointer to a network interface device structure
2442 **/
2443 static irqreturn_t ixgbe_intr(int irq, void *data)
2444 {
2445 struct ixgbe_adapter *adapter = data;
2446 struct ixgbe_hw *hw = &adapter->hw;
2447 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2448 u32 eicr;
2449
2450 /*
2451 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2452 * before the read of EICR.
2453 */
2454 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2455
2456 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2457 * therefore no explicit interrupt disable is necessary */
2458 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2459 if (!eicr) {
2460 /*
2461 * shared interrupt alert!
2462 * make sure interrupts are enabled because the read will
2463 * have disabled interrupts due to EIAM
2464 * finish the workaround of silicon errata on 82598. Unmask
2465 * the interrupt that we masked before the EICR read.
2466 */
2467 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2468 ixgbe_irq_enable(adapter, true, true);
2469 return IRQ_NONE; /* Not our interrupt */
2470 }
2471
2472 if (eicr & IXGBE_EICR_LSC)
2473 ixgbe_check_lsc(adapter);
2474
2475 switch (hw->mac.type) {
2476 case ixgbe_mac_82599EB:
2477 ixgbe_check_sfp_event(adapter, eicr);
2478 /* Fall through */
2479 case ixgbe_mac_X540:
2480 if (eicr & IXGBE_EICR_ECC)
2481 e_info(link, "Received unrecoverable ECC err, please "
2482 "reboot\n");
2483 ixgbe_check_overtemp_event(adapter, eicr);
2484 break;
2485 default:
2486 break;
2487 }
2488
2489 ixgbe_check_fan_failure(adapter, eicr);
2490
2491 /* would disable interrupts here but EIAM disabled it */
2492 napi_schedule(&q_vector->napi);
2493
2494 /*
2495 * re-enable link(maybe) and non-queue interrupts, no flush.
2496 * ixgbe_poll will re-enable the queue interrupts
2497 */
2498 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2499 ixgbe_irq_enable(adapter, false, false);
2500
2501 return IRQ_HANDLED;
2502 }
2503
2504 /**
2505 * ixgbe_request_irq - initialize interrupts
2506 * @adapter: board private structure
2507 *
2508 * Attempts to configure interrupts using the best available
2509 * capabilities of the hardware and kernel.
2510 **/
2511 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2512 {
2513 struct net_device *netdev = adapter->netdev;
2514 int err;
2515
2516 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2517 err = ixgbe_request_msix_irqs(adapter);
2518 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2519 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2520 netdev->name, adapter);
2521 else
2522 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2523 netdev->name, adapter);
2524
2525 if (err)
2526 e_err(probe, "request_irq failed, Error %d\n", err);
2527
2528 return err;
2529 }
2530
2531 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2532 {
2533 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2534 int i, q_vectors;
2535
2536 q_vectors = adapter->num_msix_vectors;
2537 i = q_vectors - 1;
2538 free_irq(adapter->msix_entries[i].vector, adapter);
2539 i--;
2540
2541 for (; i >= 0; i--) {
2542 /* free only the irqs that were actually requested */
2543 if (!adapter->q_vector[i]->rx.ring &&
2544 !adapter->q_vector[i]->tx.ring)
2545 continue;
2546
2547 /* clear the affinity_mask in the IRQ descriptor */
2548 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2549 NULL);
2550
2551 free_irq(adapter->msix_entries[i].vector,
2552 adapter->q_vector[i]);
2553 }
2554 } else {
2555 free_irq(adapter->pdev->irq, adapter);
2556 }
2557 }
2558
2559 /**
2560 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2561 * @adapter: board private structure
2562 **/
2563 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2564 {
2565 switch (adapter->hw.mac.type) {
2566 case ixgbe_mac_82598EB:
2567 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2568 break;
2569 case ixgbe_mac_82599EB:
2570 case ixgbe_mac_X540:
2571 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2572 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2573 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2574 break;
2575 default:
2576 break;
2577 }
2578 IXGBE_WRITE_FLUSH(&adapter->hw);
2579 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2580 int i;
2581 for (i = 0; i < adapter->num_msix_vectors; i++)
2582 synchronize_irq(adapter->msix_entries[i].vector);
2583 } else {
2584 synchronize_irq(adapter->pdev->irq);
2585 }
2586 }
2587
2588 /**
2589 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2590 *
2591 **/
2592 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2593 {
2594 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2595
2596 /* rx/tx vector */
2597 if (adapter->rx_itr_setting == 1)
2598 q_vector->itr = IXGBE_20K_ITR;
2599 else
2600 q_vector->itr = adapter->rx_itr_setting;
2601
2602 ixgbe_write_eitr(q_vector);
2603
2604 ixgbe_set_ivar(adapter, 0, 0, 0);
2605 ixgbe_set_ivar(adapter, 1, 0, 0);
2606
2607 e_info(hw, "Legacy interrupt IVAR setup done\n");
2608 }
2609
2610 /**
2611 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2612 * @adapter: board private structure
2613 * @ring: structure containing ring specific data
2614 *
2615 * Configure the Tx descriptor ring after a reset.
2616 **/
2617 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2618 struct ixgbe_ring *ring)
2619 {
2620 struct ixgbe_hw *hw = &adapter->hw;
2621 u64 tdba = ring->dma;
2622 int wait_loop = 10;
2623 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2624 u8 reg_idx = ring->reg_idx;
2625
2626 /* disable queue to avoid issues while updating state */
2627 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2628 IXGBE_WRITE_FLUSH(hw);
2629
2630 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2631 (tdba & DMA_BIT_MASK(32)));
2632 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2633 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2634 ring->count * sizeof(union ixgbe_adv_tx_desc));
2635 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2636 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2637 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2638
2639 /*
2640 * set WTHRESH to encourage burst writeback, it should not be set
2641 * higher than 1 when ITR is 0 as it could cause false TX hangs
2642 *
2643 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2644 * to or less than the number of on chip descriptors, which is
2645 * currently 40.
2646 */
2647 if (!ring->q_vector || (ring->q_vector->itr < 8))
2648 txdctl |= (1 << 16); /* WTHRESH = 1 */
2649 else
2650 txdctl |= (8 << 16); /* WTHRESH = 8 */
2651
2652 /*
2653 * Setting PTHRESH to 32 both improves performance
2654 * and avoids a TX hang with DFP enabled
2655 */
2656 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2657 32; /* PTHRESH = 32 */
2658
2659 /* reinitialize flowdirector state */
2660 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2661 adapter->atr_sample_rate) {
2662 ring->atr_sample_rate = adapter->atr_sample_rate;
2663 ring->atr_count = 0;
2664 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2665 } else {
2666 ring->atr_sample_rate = 0;
2667 }
2668
2669 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2670
2671 /* enable queue */
2672 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2673
2674 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2675 if (hw->mac.type == ixgbe_mac_82598EB &&
2676 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2677 return;
2678
2679 /* poll to verify queue is enabled */
2680 do {
2681 usleep_range(1000, 2000);
2682 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2683 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2684 if (!wait_loop)
2685 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2686 }
2687
2688 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2689 {
2690 struct ixgbe_hw *hw = &adapter->hw;
2691 u32 rttdcs;
2692 u32 reg;
2693 u8 tcs = netdev_get_num_tc(adapter->netdev);
2694
2695 if (hw->mac.type == ixgbe_mac_82598EB)
2696 return;
2697
2698 /* disable the arbiter while setting MTQC */
2699 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2700 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2701 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2702
2703 /* set transmit pool layout */
2704 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2705 case (IXGBE_FLAG_SRIOV_ENABLED):
2706 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2707 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2708 break;
2709 default:
2710 if (!tcs)
2711 reg = IXGBE_MTQC_64Q_1PB;
2712 else if (tcs <= 4)
2713 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2714 else
2715 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2716
2717 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2718
2719 /* Enable Security TX Buffer IFG for multiple pb */
2720 if (tcs) {
2721 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2722 reg |= IXGBE_SECTX_DCB;
2723 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2724 }
2725 break;
2726 }
2727
2728 /* re-enable the arbiter */
2729 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2730 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2731 }
2732
2733 /**
2734 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2735 * @adapter: board private structure
2736 *
2737 * Configure the Tx unit of the MAC after a reset.
2738 **/
2739 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2740 {
2741 struct ixgbe_hw *hw = &adapter->hw;
2742 u32 dmatxctl;
2743 u32 i;
2744
2745 ixgbe_setup_mtqc(adapter);
2746
2747 if (hw->mac.type != ixgbe_mac_82598EB) {
2748 /* DMATXCTL.EN must be before Tx queues are enabled */
2749 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2750 dmatxctl |= IXGBE_DMATXCTL_TE;
2751 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2752 }
2753
2754 /* Setup the HW Tx Head and Tail descriptor pointers */
2755 for (i = 0; i < adapter->num_tx_queues; i++)
2756 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2757 }
2758
2759 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2760
2761 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2762 struct ixgbe_ring *rx_ring)
2763 {
2764 u32 srrctl;
2765 u8 reg_idx = rx_ring->reg_idx;
2766
2767 switch (adapter->hw.mac.type) {
2768 case ixgbe_mac_82598EB: {
2769 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2770 const int mask = feature[RING_F_RSS].mask;
2771 reg_idx = reg_idx & mask;
2772 }
2773 break;
2774 case ixgbe_mac_82599EB:
2775 case ixgbe_mac_X540:
2776 default:
2777 break;
2778 }
2779
2780 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2781
2782 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2783 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2784 if (adapter->num_vfs)
2785 srrctl |= IXGBE_SRRCTL_DROP_EN;
2786
2787 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2788 IXGBE_SRRCTL_BSIZEHDR_MASK;
2789
2790 #if PAGE_SIZE > IXGBE_MAX_RXBUFFER
2791 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2792 #else
2793 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2794 #endif
2795 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2796
2797 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2798 }
2799
2800 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2801 {
2802 struct ixgbe_hw *hw = &adapter->hw;
2803 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2804 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2805 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2806 u32 mrqc = 0, reta = 0;
2807 u32 rxcsum;
2808 int i, j;
2809 u8 tcs = netdev_get_num_tc(adapter->netdev);
2810 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2811
2812 if (tcs)
2813 maxq = min(maxq, adapter->num_tx_queues / tcs);
2814
2815 /* Fill out hash function seeds */
2816 for (i = 0; i < 10; i++)
2817 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2818
2819 /* Fill out redirection table */
2820 for (i = 0, j = 0; i < 128; i++, j++) {
2821 if (j == maxq)
2822 j = 0;
2823 /* reta = 4-byte sliding window of
2824 * 0x00..(indices-1)(indices-1)00..etc. */
2825 reta = (reta << 8) | (j * 0x11);
2826 if ((i & 3) == 3)
2827 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2828 }
2829
2830 /* Disable indicating checksum in descriptor, enables RSS hash */
2831 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2832 rxcsum |= IXGBE_RXCSUM_PCSD;
2833 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2834
2835 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2836 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2837 mrqc = IXGBE_MRQC_RSSEN;
2838 } else {
2839 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2840 | IXGBE_FLAG_SRIOV_ENABLED);
2841
2842 switch (mask) {
2843 case (IXGBE_FLAG_RSS_ENABLED):
2844 if (!tcs)
2845 mrqc = IXGBE_MRQC_RSSEN;
2846 else if (tcs <= 4)
2847 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2848 else
2849 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2850 break;
2851 case (IXGBE_FLAG_SRIOV_ENABLED):
2852 mrqc = IXGBE_MRQC_VMDQEN;
2853 break;
2854 default:
2855 break;
2856 }
2857 }
2858
2859 /* Perform hash on these packet types */
2860 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2861 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2862 | IXGBE_MRQC_RSS_FIELD_IPV6
2863 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2864
2865 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2866 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2867 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2868 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2869
2870 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2871 }
2872
2873 /**
2874 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2875 * @adapter: address of board private structure
2876 * @index: index of ring to set
2877 **/
2878 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2879 struct ixgbe_ring *ring)
2880 {
2881 struct ixgbe_hw *hw = &adapter->hw;
2882 u32 rscctrl;
2883 u8 reg_idx = ring->reg_idx;
2884
2885 if (!ring_is_rsc_enabled(ring))
2886 return;
2887
2888 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2889 rscctrl |= IXGBE_RSCCTL_RSCEN;
2890 /*
2891 * we must limit the number of descriptors so that the
2892 * total size of max desc * buf_len is not greater
2893 * than 65536
2894 */
2895 #if (PAGE_SIZE <= 8192)
2896 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2897 #elif (PAGE_SIZE <= 16384)
2898 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2899 #else
2900 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2901 #endif
2902 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2903 }
2904
2905 /**
2906 * ixgbe_set_uta - Set unicast filter table address
2907 * @adapter: board private structure
2908 *
2909 * The unicast table address is a register array of 32-bit registers.
2910 * The table is meant to be used in a way similar to how the MTA is used
2911 * however due to certain limitations in the hardware it is necessary to
2912 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2913 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2914 **/
2915 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2916 {
2917 struct ixgbe_hw *hw = &adapter->hw;
2918 int i;
2919
2920 /* The UTA table only exists on 82599 hardware and newer */
2921 if (hw->mac.type < ixgbe_mac_82599EB)
2922 return;
2923
2924 /* we only need to do this if VMDq is enabled */
2925 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2926 return;
2927
2928 for (i = 0; i < 128; i++)
2929 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2930 }
2931
2932 #define IXGBE_MAX_RX_DESC_POLL 10
2933 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2934 struct ixgbe_ring *ring)
2935 {
2936 struct ixgbe_hw *hw = &adapter->hw;
2937 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2938 u32 rxdctl;
2939 u8 reg_idx = ring->reg_idx;
2940
2941 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2942 if (hw->mac.type == ixgbe_mac_82598EB &&
2943 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2944 return;
2945
2946 do {
2947 usleep_range(1000, 2000);
2948 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2949 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2950
2951 if (!wait_loop) {
2952 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2953 "the polling period\n", reg_idx);
2954 }
2955 }
2956
2957 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2958 struct ixgbe_ring *ring)
2959 {
2960 struct ixgbe_hw *hw = &adapter->hw;
2961 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2962 u32 rxdctl;
2963 u8 reg_idx = ring->reg_idx;
2964
2965 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2966 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2967
2968 /* write value back with RXDCTL.ENABLE bit cleared */
2969 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2970
2971 if (hw->mac.type == ixgbe_mac_82598EB &&
2972 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2973 return;
2974
2975 /* the hardware may take up to 100us to really disable the rx queue */
2976 do {
2977 udelay(10);
2978 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2979 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2980
2981 if (!wait_loop) {
2982 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2983 "the polling period\n", reg_idx);
2984 }
2985 }
2986
2987 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2988 struct ixgbe_ring *ring)
2989 {
2990 struct ixgbe_hw *hw = &adapter->hw;
2991 u64 rdba = ring->dma;
2992 u32 rxdctl;
2993 u8 reg_idx = ring->reg_idx;
2994
2995 /* disable queue to avoid issues while updating state */
2996 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2997 ixgbe_disable_rx_queue(adapter, ring);
2998
2999 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3000 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3001 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3002 ring->count * sizeof(union ixgbe_adv_rx_desc));
3003 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3004 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3005 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3006
3007 ixgbe_configure_srrctl(adapter, ring);
3008 ixgbe_configure_rscctl(adapter, ring);
3009
3010 /* If operating in IOV mode set RLPML for X540 */
3011 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3012 hw->mac.type == ixgbe_mac_X540) {
3013 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3014 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3015 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3016 }
3017
3018 if (hw->mac.type == ixgbe_mac_82598EB) {
3019 /*
3020 * enable cache line friendly hardware writes:
3021 * PTHRESH=32 descriptors (half the internal cache),
3022 * this also removes ugly rx_no_buffer_count increment
3023 * HTHRESH=4 descriptors (to minimize latency on fetch)
3024 * WTHRESH=8 burst writeback up to two cache lines
3025 */
3026 rxdctl &= ~0x3FFFFF;
3027 rxdctl |= 0x080420;
3028 }
3029
3030 /* enable receive descriptor ring */
3031 rxdctl |= IXGBE_RXDCTL_ENABLE;
3032 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3033
3034 ixgbe_rx_desc_queue_enable(adapter, ring);
3035 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3036 }
3037
3038 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3039 {
3040 struct ixgbe_hw *hw = &adapter->hw;
3041 int p;
3042
3043 /* PSRTYPE must be initialized in non 82598 adapters */
3044 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3045 IXGBE_PSRTYPE_UDPHDR |
3046 IXGBE_PSRTYPE_IPV4HDR |
3047 IXGBE_PSRTYPE_L2HDR |
3048 IXGBE_PSRTYPE_IPV6HDR;
3049
3050 if (hw->mac.type == ixgbe_mac_82598EB)
3051 return;
3052
3053 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3054 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3055
3056 for (p = 0; p < adapter->num_rx_pools; p++)
3057 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3058 psrtype);
3059 }
3060
3061 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3062 {
3063 struct ixgbe_hw *hw = &adapter->hw;
3064 u32 gcr_ext;
3065 u32 vt_reg_bits;
3066 u32 reg_offset, vf_shift;
3067 u32 vmdctl;
3068 int i;
3069
3070 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3071 return;
3072
3073 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3074 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3075 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3076 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3077
3078 vf_shift = adapter->num_vfs % 32;
3079 reg_offset = (adapter->num_vfs >= 32) ? 1 : 0;
3080
3081 /* Enable only the PF's pool for Tx/Rx */
3082 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3083 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3084 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3085 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3086 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3087
3088 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3089 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3090
3091 /*
3092 * Set up VF register offsets for selected VT Mode,
3093 * i.e. 32 or 64 VFs for SR-IOV
3094 */
3095 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3096 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3097 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3098 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3099
3100 /* enable Tx loopback for VF/PF communication */
3101 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3102 /* Enable MAC Anti-Spoofing */
3103 hw->mac.ops.set_mac_anti_spoofing(hw,
3104 (adapter->num_vfs != 0),
3105 adapter->num_vfs);
3106 /* For VFs that have spoof checking turned off */
3107 for (i = 0; i < adapter->num_vfs; i++) {
3108 if (!adapter->vfinfo[i].spoofchk_enabled)
3109 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3110 }
3111 }
3112
3113 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3114 {
3115 struct ixgbe_hw *hw = &adapter->hw;
3116 struct net_device *netdev = adapter->netdev;
3117 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3118 struct ixgbe_ring *rx_ring;
3119 int i;
3120 u32 mhadd, hlreg0;
3121
3122 #ifdef IXGBE_FCOE
3123 /* adjust max frame to be able to do baby jumbo for FCoE */
3124 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3125 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3126 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3127
3128 #endif /* IXGBE_FCOE */
3129 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3130 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3131 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3132 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3133
3134 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3135 }
3136
3137 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3138 max_frame += VLAN_HLEN;
3139
3140 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3141 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3142 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3143 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3144
3145 /*
3146 * Setup the HW Rx Head and Tail Descriptor Pointers and
3147 * the Base and Length of the Rx Descriptor Ring
3148 */
3149 for (i = 0; i < adapter->num_rx_queues; i++) {
3150 rx_ring = adapter->rx_ring[i];
3151 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3152 set_ring_rsc_enabled(rx_ring);
3153 else
3154 clear_ring_rsc_enabled(rx_ring);
3155 }
3156 }
3157
3158 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3159 {
3160 struct ixgbe_hw *hw = &adapter->hw;
3161 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3162
3163 switch (hw->mac.type) {
3164 case ixgbe_mac_82598EB:
3165 /*
3166 * For VMDq support of different descriptor types or
3167 * buffer sizes through the use of multiple SRRCTL
3168 * registers, RDRXCTL.MVMEN must be set to 1
3169 *
3170 * also, the manual doesn't mention it clearly but DCA hints
3171 * will only use queue 0's tags unless this bit is set. Side
3172 * effects of setting this bit are only that SRRCTL must be
3173 * fully programmed [0..15]
3174 */
3175 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3176 break;
3177 case ixgbe_mac_82599EB:
3178 case ixgbe_mac_X540:
3179 /* Disable RSC for ACK packets */
3180 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3181 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3182 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3183 /* hardware requires some bits to be set by default */
3184 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3185 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3186 break;
3187 default:
3188 /* We should do nothing since we don't know this hardware */
3189 return;
3190 }
3191
3192 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3193 }
3194
3195 /**
3196 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3197 * @adapter: board private structure
3198 *
3199 * Configure the Rx unit of the MAC after a reset.
3200 **/
3201 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3202 {
3203 struct ixgbe_hw *hw = &adapter->hw;
3204 int i;
3205 u32 rxctrl;
3206
3207 /* disable receives while setting up the descriptors */
3208 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3209 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3210
3211 ixgbe_setup_psrtype(adapter);
3212 ixgbe_setup_rdrxctl(adapter);
3213
3214 /* Program registers for the distribution of queues */
3215 ixgbe_setup_mrqc(adapter);
3216
3217 ixgbe_set_uta(adapter);
3218
3219 /* set_rx_buffer_len must be called before ring initialization */
3220 ixgbe_set_rx_buffer_len(adapter);
3221
3222 /*
3223 * Setup the HW Rx Head and Tail Descriptor Pointers and
3224 * the Base and Length of the Rx Descriptor Ring
3225 */
3226 for (i = 0; i < adapter->num_rx_queues; i++)
3227 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3228
3229 /* disable drop enable for 82598 parts */
3230 if (hw->mac.type == ixgbe_mac_82598EB)
3231 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3232
3233 /* enable all receives */
3234 rxctrl |= IXGBE_RXCTRL_RXEN;
3235 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3236 }
3237
3238 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3239 {
3240 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3241 struct ixgbe_hw *hw = &adapter->hw;
3242 int pool_ndx = adapter->num_vfs;
3243
3244 /* add VID to filter table */
3245 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3246 set_bit(vid, adapter->active_vlans);
3247
3248 return 0;
3249 }
3250
3251 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3252 {
3253 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3254 struct ixgbe_hw *hw = &adapter->hw;
3255 int pool_ndx = adapter->num_vfs;
3256
3257 /* remove VID from filter table */
3258 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3259 clear_bit(vid, adapter->active_vlans);
3260
3261 return 0;
3262 }
3263
3264 /**
3265 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3266 * @adapter: driver data
3267 */
3268 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3269 {
3270 struct ixgbe_hw *hw = &adapter->hw;
3271 u32 vlnctrl;
3272
3273 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3274 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3275 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3276 }
3277
3278 /**
3279 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3280 * @adapter: driver data
3281 */
3282 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3283 {
3284 struct ixgbe_hw *hw = &adapter->hw;
3285 u32 vlnctrl;
3286
3287 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3288 vlnctrl |= IXGBE_VLNCTRL_VFE;
3289 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3290 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3291 }
3292
3293 /**
3294 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3295 * @adapter: driver data
3296 */
3297 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3298 {
3299 struct ixgbe_hw *hw = &adapter->hw;
3300 u32 vlnctrl;
3301 int i, j;
3302
3303 switch (hw->mac.type) {
3304 case ixgbe_mac_82598EB:
3305 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3306 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3307 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3308 break;
3309 case ixgbe_mac_82599EB:
3310 case ixgbe_mac_X540:
3311 for (i = 0; i < adapter->num_rx_queues; i++) {
3312 j = adapter->rx_ring[i]->reg_idx;
3313 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3314 vlnctrl &= ~IXGBE_RXDCTL_VME;
3315 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3316 }
3317 break;
3318 default:
3319 break;
3320 }
3321 }
3322
3323 /**
3324 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3325 * @adapter: driver data
3326 */
3327 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3328 {
3329 struct ixgbe_hw *hw = &adapter->hw;
3330 u32 vlnctrl;
3331 int i, j;
3332
3333 switch (hw->mac.type) {
3334 case ixgbe_mac_82598EB:
3335 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3336 vlnctrl |= IXGBE_VLNCTRL_VME;
3337 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3338 break;
3339 case ixgbe_mac_82599EB:
3340 case ixgbe_mac_X540:
3341 for (i = 0; i < adapter->num_rx_queues; i++) {
3342 j = adapter->rx_ring[i]->reg_idx;
3343 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3344 vlnctrl |= IXGBE_RXDCTL_VME;
3345 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3346 }
3347 break;
3348 default:
3349 break;
3350 }
3351 }
3352
3353 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3354 {
3355 u16 vid;
3356
3357 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3358
3359 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3360 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3361 }
3362
3363 /**
3364 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3365 * @netdev: network interface device structure
3366 *
3367 * Writes unicast address list to the RAR table.
3368 * Returns: -ENOMEM on failure/insufficient address space
3369 * 0 on no addresses written
3370 * X on writing X addresses to the RAR table
3371 **/
3372 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3373 {
3374 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3375 struct ixgbe_hw *hw = &adapter->hw;
3376 unsigned int vfn = adapter->num_vfs;
3377 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3378 int count = 0;
3379
3380 /* return ENOMEM indicating insufficient memory for addresses */
3381 if (netdev_uc_count(netdev) > rar_entries)
3382 return -ENOMEM;
3383
3384 if (!netdev_uc_empty(netdev) && rar_entries) {
3385 struct netdev_hw_addr *ha;
3386 /* return error if we do not support writing to RAR table */
3387 if (!hw->mac.ops.set_rar)
3388 return -ENOMEM;
3389
3390 netdev_for_each_uc_addr(ha, netdev) {
3391 if (!rar_entries)
3392 break;
3393 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3394 vfn, IXGBE_RAH_AV);
3395 count++;
3396 }
3397 }
3398 /* write the addresses in reverse order to avoid write combining */
3399 for (; rar_entries > 0 ; rar_entries--)
3400 hw->mac.ops.clear_rar(hw, rar_entries);
3401
3402 return count;
3403 }
3404
3405 /**
3406 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3407 * @netdev: network interface device structure
3408 *
3409 * The set_rx_method entry point is called whenever the unicast/multicast
3410 * address list or the network interface flags are updated. This routine is
3411 * responsible for configuring the hardware for proper unicast, multicast and
3412 * promiscuous mode.
3413 **/
3414 void ixgbe_set_rx_mode(struct net_device *netdev)
3415 {
3416 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3417 struct ixgbe_hw *hw = &adapter->hw;
3418 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3419 int count;
3420
3421 /* Check for Promiscuous and All Multicast modes */
3422
3423 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3424
3425 /* set all bits that we expect to always be set */
3426 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3427 fctrl |= IXGBE_FCTRL_BAM;
3428 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3429 fctrl |= IXGBE_FCTRL_PMCF;
3430
3431 /* clear the bits we are changing the status of */
3432 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3433
3434 if (netdev->flags & IFF_PROMISC) {
3435 hw->addr_ctrl.user_set_promisc = true;
3436 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3437 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3438 /* don't hardware filter vlans in promisc mode */
3439 ixgbe_vlan_filter_disable(adapter);
3440 } else {
3441 if (netdev->flags & IFF_ALLMULTI) {
3442 fctrl |= IXGBE_FCTRL_MPE;
3443 vmolr |= IXGBE_VMOLR_MPE;
3444 } else {
3445 /*
3446 * Write addresses to the MTA, if the attempt fails
3447 * then we should just turn on promiscuous mode so
3448 * that we can at least receive multicast traffic
3449 */
3450 hw->mac.ops.update_mc_addr_list(hw, netdev);
3451 vmolr |= IXGBE_VMOLR_ROMPE;
3452 }
3453 ixgbe_vlan_filter_enable(adapter);
3454 hw->addr_ctrl.user_set_promisc = false;
3455 /*
3456 * Write addresses to available RAR registers, if there is not
3457 * sufficient space to store all the addresses then enable
3458 * unicast promiscuous mode
3459 */
3460 count = ixgbe_write_uc_addr_list(netdev);
3461 if (count < 0) {
3462 fctrl |= IXGBE_FCTRL_UPE;
3463 vmolr |= IXGBE_VMOLR_ROPE;
3464 }
3465 }
3466
3467 if (adapter->num_vfs) {
3468 ixgbe_restore_vf_multicasts(adapter);
3469 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3470 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3471 IXGBE_VMOLR_ROPE);
3472 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3473 }
3474
3475 /* This is useful for sniffing bad packets. */
3476 if (adapter->netdev->features & NETIF_F_RXALL) {
3477 /* UPE and MPE will be handled by normal PROMISC logic
3478 * in e1000e_set_rx_mode */
3479 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3480 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3481 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3482
3483 fctrl &= ~(IXGBE_FCTRL_DPF);
3484 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3485 }
3486
3487 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3488
3489 if (netdev->features & NETIF_F_HW_VLAN_RX)
3490 ixgbe_vlan_strip_enable(adapter);
3491 else
3492 ixgbe_vlan_strip_disable(adapter);
3493 }
3494
3495 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3496 {
3497 int q_idx;
3498 struct ixgbe_q_vector *q_vector;
3499 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3500
3501 /* legacy and MSI only use one vector */
3502 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3503 q_vectors = 1;
3504
3505 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3506 q_vector = adapter->q_vector[q_idx];
3507 napi_enable(&q_vector->napi);
3508 }
3509 }
3510
3511 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3512 {
3513 int q_idx;
3514 struct ixgbe_q_vector *q_vector;
3515 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3516
3517 /* legacy and MSI only use one vector */
3518 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3519 q_vectors = 1;
3520
3521 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3522 q_vector = adapter->q_vector[q_idx];
3523 napi_disable(&q_vector->napi);
3524 }
3525 }
3526
3527 #ifdef CONFIG_IXGBE_DCB
3528 /*
3529 * ixgbe_configure_dcb - Configure DCB hardware
3530 * @adapter: ixgbe adapter struct
3531 *
3532 * This is called by the driver on open to configure the DCB hardware.
3533 * This is also called by the gennetlink interface when reconfiguring
3534 * the DCB state.
3535 */
3536 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3537 {
3538 struct ixgbe_hw *hw = &adapter->hw;
3539 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3540
3541 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3542 if (hw->mac.type == ixgbe_mac_82598EB)
3543 netif_set_gso_max_size(adapter->netdev, 65536);
3544 return;
3545 }
3546
3547 if (hw->mac.type == ixgbe_mac_82598EB)
3548 netif_set_gso_max_size(adapter->netdev, 32768);
3549
3550
3551 /* Enable VLAN tag insert/strip */
3552 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3553
3554 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3555
3556 #ifdef IXGBE_FCOE
3557 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3558 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3559 #endif
3560
3561 /* reconfigure the hardware */
3562 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3563 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3564 DCB_TX_CONFIG);
3565 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3566 DCB_RX_CONFIG);
3567 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3568 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3569 ixgbe_dcb_hw_ets(&adapter->hw,
3570 adapter->ixgbe_ieee_ets,
3571 max_frame);
3572 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3573 adapter->ixgbe_ieee_pfc->pfc_en,
3574 adapter->ixgbe_ieee_ets->prio_tc);
3575 }
3576
3577 /* Enable RSS Hash per TC */
3578 if (hw->mac.type != ixgbe_mac_82598EB) {
3579 int i;
3580 u32 reg = 0;
3581
3582 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3583 u8 msb = 0;
3584 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3585
3586 while (cnt >>= 1)
3587 msb++;
3588
3589 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3590 }
3591 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3592 }
3593 }
3594 #endif
3595
3596 /* Additional bittime to account for IXGBE framing */
3597 #define IXGBE_ETH_FRAMING 20
3598
3599 /*
3600 * ixgbe_hpbthresh - calculate high water mark for flow control
3601 *
3602 * @adapter: board private structure to calculate for
3603 * @pb - packet buffer to calculate
3604 */
3605 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3606 {
3607 struct ixgbe_hw *hw = &adapter->hw;
3608 struct net_device *dev = adapter->netdev;
3609 int link, tc, kb, marker;
3610 u32 dv_id, rx_pba;
3611
3612 /* Calculate max LAN frame size */
3613 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3614
3615 #ifdef IXGBE_FCOE
3616 /* FCoE traffic class uses FCOE jumbo frames */
3617 if (dev->features & NETIF_F_FCOE_MTU) {
3618 int fcoe_pb = 0;
3619
3620 #ifdef CONFIG_IXGBE_DCB
3621 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3622
3623 #endif
3624 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3625 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3626 }
3627 #endif
3628
3629 /* Calculate delay value for device */
3630 switch (hw->mac.type) {
3631 case ixgbe_mac_X540:
3632 dv_id = IXGBE_DV_X540(link, tc);
3633 break;
3634 default:
3635 dv_id = IXGBE_DV(link, tc);
3636 break;
3637 }
3638
3639 /* Loopback switch introduces additional latency */
3640 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3641 dv_id += IXGBE_B2BT(tc);
3642
3643 /* Delay value is calculated in bit times convert to KB */
3644 kb = IXGBE_BT2KB(dv_id);
3645 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3646
3647 marker = rx_pba - kb;
3648
3649 /* It is possible that the packet buffer is not large enough
3650 * to provide required headroom. In this case throw an error
3651 * to user and a do the best we can.
3652 */
3653 if (marker < 0) {
3654 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3655 "headroom to support flow control."
3656 "Decrease MTU or number of traffic classes\n", pb);
3657 marker = tc + 1;
3658 }
3659
3660 return marker;
3661 }
3662
3663 /*
3664 * ixgbe_lpbthresh - calculate low water mark for for flow control
3665 *
3666 * @adapter: board private structure to calculate for
3667 * @pb - packet buffer to calculate
3668 */
3669 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3670 {
3671 struct ixgbe_hw *hw = &adapter->hw;
3672 struct net_device *dev = adapter->netdev;
3673 int tc;
3674 u32 dv_id;
3675
3676 /* Calculate max LAN frame size */
3677 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3678
3679 /* Calculate delay value for device */
3680 switch (hw->mac.type) {
3681 case ixgbe_mac_X540:
3682 dv_id = IXGBE_LOW_DV_X540(tc);
3683 break;
3684 default:
3685 dv_id = IXGBE_LOW_DV(tc);
3686 break;
3687 }
3688
3689 /* Delay value is calculated in bit times convert to KB */
3690 return IXGBE_BT2KB(dv_id);
3691 }
3692
3693 /*
3694 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3695 */
3696 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3697 {
3698 struct ixgbe_hw *hw = &adapter->hw;
3699 int num_tc = netdev_get_num_tc(adapter->netdev);
3700 int i;
3701
3702 if (!num_tc)
3703 num_tc = 1;
3704
3705 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3706
3707 for (i = 0; i < num_tc; i++) {
3708 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3709
3710 /* Low water marks must not be larger than high water marks */
3711 if (hw->fc.low_water > hw->fc.high_water[i])
3712 hw->fc.low_water = 0;
3713 }
3714 }
3715
3716 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3717 {
3718 struct ixgbe_hw *hw = &adapter->hw;
3719 int hdrm;
3720 u8 tc = netdev_get_num_tc(adapter->netdev);
3721
3722 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3723 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3724 hdrm = 32 << adapter->fdir_pballoc;
3725 else
3726 hdrm = 0;
3727
3728 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3729 ixgbe_pbthresh_setup(adapter);
3730 }
3731
3732 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3733 {
3734 struct ixgbe_hw *hw = &adapter->hw;
3735 struct hlist_node *node, *node2;
3736 struct ixgbe_fdir_filter *filter;
3737
3738 spin_lock(&adapter->fdir_perfect_lock);
3739
3740 if (!hlist_empty(&adapter->fdir_filter_list))
3741 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3742
3743 hlist_for_each_entry_safe(filter, node, node2,
3744 &adapter->fdir_filter_list, fdir_node) {
3745 ixgbe_fdir_write_perfect_filter_82599(hw,
3746 &filter->filter,
3747 filter->sw_idx,
3748 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3749 IXGBE_FDIR_DROP_QUEUE :
3750 adapter->rx_ring[filter->action]->reg_idx);
3751 }
3752
3753 spin_unlock(&adapter->fdir_perfect_lock);
3754 }
3755
3756 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3757 {
3758 struct ixgbe_hw *hw = &adapter->hw;
3759
3760 ixgbe_configure_pb(adapter);
3761 #ifdef CONFIG_IXGBE_DCB
3762 ixgbe_configure_dcb(adapter);
3763 #endif
3764
3765 ixgbe_set_rx_mode(adapter->netdev);
3766 ixgbe_restore_vlan(adapter);
3767
3768 #ifdef IXGBE_FCOE
3769 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3770 ixgbe_configure_fcoe(adapter);
3771
3772 #endif /* IXGBE_FCOE */
3773
3774 switch (hw->mac.type) {
3775 case ixgbe_mac_82599EB:
3776 case ixgbe_mac_X540:
3777 hw->mac.ops.disable_rx_buff(hw);
3778 break;
3779 default:
3780 break;
3781 }
3782
3783 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3784 ixgbe_init_fdir_signature_82599(&adapter->hw,
3785 adapter->fdir_pballoc);
3786 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3787 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3788 adapter->fdir_pballoc);
3789 ixgbe_fdir_filter_restore(adapter);
3790 }
3791
3792 switch (hw->mac.type) {
3793 case ixgbe_mac_82599EB:
3794 case ixgbe_mac_X540:
3795 hw->mac.ops.enable_rx_buff(hw);
3796 break;
3797 default:
3798 break;
3799 }
3800
3801 ixgbe_configure_virtualization(adapter);
3802
3803 ixgbe_configure_tx(adapter);
3804 ixgbe_configure_rx(adapter);
3805 }
3806
3807 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3808 {
3809 switch (hw->phy.type) {
3810 case ixgbe_phy_sfp_avago:
3811 case ixgbe_phy_sfp_ftl:
3812 case ixgbe_phy_sfp_intel:
3813 case ixgbe_phy_sfp_unknown:
3814 case ixgbe_phy_sfp_passive_tyco:
3815 case ixgbe_phy_sfp_passive_unknown:
3816 case ixgbe_phy_sfp_active_unknown:
3817 case ixgbe_phy_sfp_ftl_active:
3818 return true;
3819 case ixgbe_phy_nl:
3820 if (hw->mac.type == ixgbe_mac_82598EB)
3821 return true;
3822 default:
3823 return false;
3824 }
3825 }
3826
3827 /**
3828 * ixgbe_sfp_link_config - set up SFP+ link
3829 * @adapter: pointer to private adapter struct
3830 **/
3831 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3832 {
3833 /*
3834 * We are assuming the worst case scenario here, and that
3835 * is that an SFP was inserted/removed after the reset
3836 * but before SFP detection was enabled. As such the best
3837 * solution is to just start searching as soon as we start
3838 */
3839 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3840 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3841
3842 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3843 }
3844
3845 /**
3846 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3847 * @hw: pointer to private hardware struct
3848 *
3849 * Returns 0 on success, negative on failure
3850 **/
3851 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3852 {
3853 u32 autoneg;
3854 bool negotiation, link_up = false;
3855 u32 ret = IXGBE_ERR_LINK_SETUP;
3856
3857 if (hw->mac.ops.check_link)
3858 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3859
3860 if (ret)
3861 goto link_cfg_out;
3862
3863 autoneg = hw->phy.autoneg_advertised;
3864 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3865 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3866 &negotiation);
3867 if (ret)
3868 goto link_cfg_out;
3869
3870 if (hw->mac.ops.setup_link)
3871 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3872 link_cfg_out:
3873 return ret;
3874 }
3875
3876 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3877 {
3878 struct ixgbe_hw *hw = &adapter->hw;
3879 u32 gpie = 0;
3880
3881 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3882 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3883 IXGBE_GPIE_OCD;
3884 gpie |= IXGBE_GPIE_EIAME;
3885 /*
3886 * use EIAM to auto-mask when MSI-X interrupt is asserted
3887 * this saves a register write for every interrupt
3888 */
3889 switch (hw->mac.type) {
3890 case ixgbe_mac_82598EB:
3891 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3892 break;
3893 case ixgbe_mac_82599EB:
3894 case ixgbe_mac_X540:
3895 default:
3896 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3897 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3898 break;
3899 }
3900 } else {
3901 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3902 * specifically only auto mask tx and rx interrupts */
3903 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3904 }
3905
3906 /* XXX: to interrupt immediately for EICS writes, enable this */
3907 /* gpie |= IXGBE_GPIE_EIMEN; */
3908
3909 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3910 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3911 gpie |= IXGBE_GPIE_VTMODE_64;
3912 }
3913
3914 /* Enable Thermal over heat sensor interrupt */
3915 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3916 switch (adapter->hw.mac.type) {
3917 case ixgbe_mac_82599EB:
3918 gpie |= IXGBE_SDP0_GPIEN;
3919 break;
3920 case ixgbe_mac_X540:
3921 gpie |= IXGBE_EIMS_TS;
3922 break;
3923 default:
3924 break;
3925 }
3926 }
3927
3928 /* Enable fan failure interrupt */
3929 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3930 gpie |= IXGBE_SDP1_GPIEN;
3931
3932 if (hw->mac.type == ixgbe_mac_82599EB) {
3933 gpie |= IXGBE_SDP1_GPIEN;
3934 gpie |= IXGBE_SDP2_GPIEN;
3935 }
3936
3937 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3938 }
3939
3940 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
3941 {
3942 struct ixgbe_hw *hw = &adapter->hw;
3943 int err;
3944 u32 ctrl_ext;
3945
3946 ixgbe_get_hw_control(adapter);
3947 ixgbe_setup_gpie(adapter);
3948
3949 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3950 ixgbe_configure_msix(adapter);
3951 else
3952 ixgbe_configure_msi_and_legacy(adapter);
3953
3954 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3955 if (hw->mac.ops.enable_tx_laser &&
3956 ((hw->phy.multispeed_fiber) ||
3957 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3958 (hw->mac.type == ixgbe_mac_82599EB))))
3959 hw->mac.ops.enable_tx_laser(hw);
3960
3961 clear_bit(__IXGBE_DOWN, &adapter->state);
3962 ixgbe_napi_enable_all(adapter);
3963
3964 if (ixgbe_is_sfp(hw)) {
3965 ixgbe_sfp_link_config(adapter);
3966 } else {
3967 err = ixgbe_non_sfp_link_config(hw);
3968 if (err)
3969 e_err(probe, "link_config FAILED %d\n", err);
3970 }
3971
3972 /* clear any pending interrupts, may auto mask */
3973 IXGBE_READ_REG(hw, IXGBE_EICR);
3974 ixgbe_irq_enable(adapter, true, true);
3975
3976 /*
3977 * If this adapter has a fan, check to see if we had a failure
3978 * before we enabled the interrupt.
3979 */
3980 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3981 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3982 if (esdp & IXGBE_ESDP_SDP1)
3983 e_crit(drv, "Fan has stopped, replace the adapter\n");
3984 }
3985
3986 /* enable transmits */
3987 netif_tx_start_all_queues(adapter->netdev);
3988
3989 /* bring the link up in the watchdog, this could race with our first
3990 * link up interrupt but shouldn't be a problem */
3991 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3992 adapter->link_check_timeout = jiffies;
3993 mod_timer(&adapter->service_timer, jiffies);
3994
3995 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3996 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3997 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3998 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3999 }
4000
4001 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4002 {
4003 WARN_ON(in_interrupt());
4004 /* put off any impending NetWatchDogTimeout */
4005 adapter->netdev->trans_start = jiffies;
4006
4007 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4008 usleep_range(1000, 2000);
4009 ixgbe_down(adapter);
4010 /*
4011 * If SR-IOV enabled then wait a bit before bringing the adapter
4012 * back up to give the VFs time to respond to the reset. The
4013 * two second wait is based upon the watchdog timer cycle in
4014 * the VF driver.
4015 */
4016 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4017 msleep(2000);
4018 ixgbe_up(adapter);
4019 clear_bit(__IXGBE_RESETTING, &adapter->state);
4020 }
4021
4022 void ixgbe_up(struct ixgbe_adapter *adapter)
4023 {
4024 /* hardware has been reset, we need to reload some things */
4025 ixgbe_configure(adapter);
4026
4027 ixgbe_up_complete(adapter);
4028 }
4029
4030 void ixgbe_reset(struct ixgbe_adapter *adapter)
4031 {
4032 struct ixgbe_hw *hw = &adapter->hw;
4033 int err;
4034
4035 /* lock SFP init bit to prevent race conditions with the watchdog */
4036 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4037 usleep_range(1000, 2000);
4038
4039 /* clear all SFP and link config related flags while holding SFP_INIT */
4040 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4041 IXGBE_FLAG2_SFP_NEEDS_RESET);
4042 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4043
4044 err = hw->mac.ops.init_hw(hw);
4045 switch (err) {
4046 case 0:
4047 case IXGBE_ERR_SFP_NOT_PRESENT:
4048 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4049 break;
4050 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4051 e_dev_err("master disable timed out\n");
4052 break;
4053 case IXGBE_ERR_EEPROM_VERSION:
4054 /* We are running on a pre-production device, log a warning */
4055 e_dev_warn("This device is a pre-production adapter/LOM. "
4056 "Please be aware there may be issues associated with "
4057 "your hardware. If you are experiencing problems "
4058 "please contact your Intel or hardware "
4059 "representative who provided you with this "
4060 "hardware.\n");
4061 break;
4062 default:
4063 e_dev_err("Hardware Error: %d\n", err);
4064 }
4065
4066 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4067
4068 /* reprogram the RAR[0] in case user changed it. */
4069 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4070 IXGBE_RAH_AV);
4071 }
4072
4073 /**
4074 * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers
4075 * @rx_ring: ring to setup
4076 *
4077 * On many IA platforms the L1 cache has a critical stride of 4K, this
4078 * results in each receive buffer starting in the same cache set. To help
4079 * reduce the pressure on this cache set we can interleave the offsets so
4080 * that only every other buffer will be in the same cache set.
4081 **/
4082 static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring)
4083 {
4084 struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info;
4085 u16 i;
4086
4087 for (i = 0; i < rx_ring->count; i += 2) {
4088 rx_buffer[0].page_offset = 0;
4089 rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring);
4090 rx_buffer = &rx_buffer[2];
4091 }
4092 }
4093
4094 /**
4095 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4096 * @rx_ring: ring to free buffers from
4097 **/
4098 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4099 {
4100 struct device *dev = rx_ring->dev;
4101 unsigned long size;
4102 u16 i;
4103
4104 /* ring already cleared, nothing to do */
4105 if (!rx_ring->rx_buffer_info)
4106 return;
4107
4108 /* Free all the Rx ring sk_buffs */
4109 for (i = 0; i < rx_ring->count; i++) {
4110 struct ixgbe_rx_buffer *rx_buffer;
4111
4112 rx_buffer = &rx_ring->rx_buffer_info[i];
4113 if (rx_buffer->skb) {
4114 struct sk_buff *skb = rx_buffer->skb;
4115 if (IXGBE_CB(skb)->page_released) {
4116 dma_unmap_page(dev,
4117 IXGBE_CB(skb)->dma,
4118 ixgbe_rx_bufsz(rx_ring),
4119 DMA_FROM_DEVICE);
4120 IXGBE_CB(skb)->page_released = false;
4121 }
4122 dev_kfree_skb(skb);
4123 }
4124 rx_buffer->skb = NULL;
4125 if (rx_buffer->dma)
4126 dma_unmap_page(dev, rx_buffer->dma,
4127 ixgbe_rx_pg_size(rx_ring),
4128 DMA_FROM_DEVICE);
4129 rx_buffer->dma = 0;
4130 if (rx_buffer->page)
4131 put_page(rx_buffer->page);
4132 rx_buffer->page = NULL;
4133 }
4134
4135 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4136 memset(rx_ring->rx_buffer_info, 0, size);
4137
4138 ixgbe_init_rx_page_offset(rx_ring);
4139
4140 /* Zero out the descriptor ring */
4141 memset(rx_ring->desc, 0, rx_ring->size);
4142
4143 rx_ring->next_to_alloc = 0;
4144 rx_ring->next_to_clean = 0;
4145 rx_ring->next_to_use = 0;
4146 }
4147
4148 /**
4149 * ixgbe_clean_tx_ring - Free Tx Buffers
4150 * @tx_ring: ring to be cleaned
4151 **/
4152 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4153 {
4154 struct ixgbe_tx_buffer *tx_buffer_info;
4155 unsigned long size;
4156 u16 i;
4157
4158 /* ring already cleared, nothing to do */
4159 if (!tx_ring->tx_buffer_info)
4160 return;
4161
4162 /* Free all the Tx ring sk_buffs */
4163 for (i = 0; i < tx_ring->count; i++) {
4164 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4165 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4166 }
4167
4168 netdev_tx_reset_queue(txring_txq(tx_ring));
4169
4170 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4171 memset(tx_ring->tx_buffer_info, 0, size);
4172
4173 /* Zero out the descriptor ring */
4174 memset(tx_ring->desc, 0, tx_ring->size);
4175
4176 tx_ring->next_to_use = 0;
4177 tx_ring->next_to_clean = 0;
4178 }
4179
4180 /**
4181 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4182 * @adapter: board private structure
4183 **/
4184 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4185 {
4186 int i;
4187
4188 for (i = 0; i < adapter->num_rx_queues; i++)
4189 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4190 }
4191
4192 /**
4193 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4194 * @adapter: board private structure
4195 **/
4196 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4197 {
4198 int i;
4199
4200 for (i = 0; i < adapter->num_tx_queues; i++)
4201 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4202 }
4203
4204 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4205 {
4206 struct hlist_node *node, *node2;
4207 struct ixgbe_fdir_filter *filter;
4208
4209 spin_lock(&adapter->fdir_perfect_lock);
4210
4211 hlist_for_each_entry_safe(filter, node, node2,
4212 &adapter->fdir_filter_list, fdir_node) {
4213 hlist_del(&filter->fdir_node);
4214 kfree(filter);
4215 }
4216 adapter->fdir_filter_count = 0;
4217
4218 spin_unlock(&adapter->fdir_perfect_lock);
4219 }
4220
4221 void ixgbe_down(struct ixgbe_adapter *adapter)
4222 {
4223 struct net_device *netdev = adapter->netdev;
4224 struct ixgbe_hw *hw = &adapter->hw;
4225 u32 rxctrl;
4226 int i;
4227
4228 /* signal that we are down to the interrupt handler */
4229 set_bit(__IXGBE_DOWN, &adapter->state);
4230
4231 /* disable receives */
4232 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4233 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4234
4235 /* disable all enabled rx queues */
4236 for (i = 0; i < adapter->num_rx_queues; i++)
4237 /* this call also flushes the previous write */
4238 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4239
4240 usleep_range(10000, 20000);
4241
4242 netif_tx_stop_all_queues(netdev);
4243
4244 /* call carrier off first to avoid false dev_watchdog timeouts */
4245 netif_carrier_off(netdev);
4246 netif_tx_disable(netdev);
4247
4248 ixgbe_irq_disable(adapter);
4249
4250 ixgbe_napi_disable_all(adapter);
4251
4252 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4253 IXGBE_FLAG2_RESET_REQUESTED);
4254 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4255
4256 del_timer_sync(&adapter->service_timer);
4257
4258 if (adapter->num_vfs) {
4259 /* Clear EITR Select mapping */
4260 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4261
4262 /* Mark all the VFs as inactive */
4263 for (i = 0 ; i < adapter->num_vfs; i++)
4264 adapter->vfinfo[i].clear_to_send = false;
4265
4266 /* ping all the active vfs to let them know we are going down */
4267 ixgbe_ping_all_vfs(adapter);
4268
4269 /* Disable all VFTE/VFRE TX/RX */
4270 ixgbe_disable_tx_rx(adapter);
4271 }
4272
4273 /* disable transmits in the hardware now that interrupts are off */
4274 for (i = 0; i < adapter->num_tx_queues; i++) {
4275 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4276 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4277 }
4278
4279 /* Disable the Tx DMA engine on 82599 and X540 */
4280 switch (hw->mac.type) {
4281 case ixgbe_mac_82599EB:
4282 case ixgbe_mac_X540:
4283 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4284 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4285 ~IXGBE_DMATXCTL_TE));
4286 break;
4287 default:
4288 break;
4289 }
4290
4291 if (!pci_channel_offline(adapter->pdev))
4292 ixgbe_reset(adapter);
4293
4294 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4295 if (hw->mac.ops.disable_tx_laser &&
4296 ((hw->phy.multispeed_fiber) ||
4297 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4298 (hw->mac.type == ixgbe_mac_82599EB))))
4299 hw->mac.ops.disable_tx_laser(hw);
4300
4301 ixgbe_clean_all_tx_rings(adapter);
4302 ixgbe_clean_all_rx_rings(adapter);
4303
4304 #ifdef CONFIG_IXGBE_DCA
4305 /* since we reset the hardware DCA settings were cleared */
4306 ixgbe_setup_dca(adapter);
4307 #endif
4308 }
4309
4310 /**
4311 * ixgbe_tx_timeout - Respond to a Tx Hang
4312 * @netdev: network interface device structure
4313 **/
4314 static void ixgbe_tx_timeout(struct net_device *netdev)
4315 {
4316 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4317
4318 /* Do the reset outside of interrupt context */
4319 ixgbe_tx_timeout_reset(adapter);
4320 }
4321
4322 /**
4323 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4324 * @adapter: board private structure to initialize
4325 *
4326 * ixgbe_sw_init initializes the Adapter private data structure.
4327 * Fields are initialized based on PCI device information and
4328 * OS network device settings (MTU size).
4329 **/
4330 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4331 {
4332 struct ixgbe_hw *hw = &adapter->hw;
4333 struct pci_dev *pdev = adapter->pdev;
4334 unsigned int rss;
4335 #ifdef CONFIG_IXGBE_DCB
4336 int j;
4337 struct tc_configuration *tc;
4338 #endif
4339
4340 /* PCI config space info */
4341
4342 hw->vendor_id = pdev->vendor;
4343 hw->device_id = pdev->device;
4344 hw->revision_id = pdev->revision;
4345 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4346 hw->subsystem_device_id = pdev->subsystem_device;
4347
4348 /* Set capability flags */
4349 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4350 adapter->ring_feature[RING_F_RSS].indices = rss;
4351 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4352 switch (hw->mac.type) {
4353 case ixgbe_mac_82598EB:
4354 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4355 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4356 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4357 break;
4358 case ixgbe_mac_X540:
4359 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4360 case ixgbe_mac_82599EB:
4361 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4362 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4363 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4364 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4365 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4366 /* Flow Director hash filters enabled */
4367 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4368 adapter->atr_sample_rate = 20;
4369 adapter->ring_feature[RING_F_FDIR].indices =
4370 IXGBE_MAX_FDIR_INDICES;
4371 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4372 #ifdef IXGBE_FCOE
4373 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4374 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4375 adapter->ring_feature[RING_F_FCOE].indices = 0;
4376 #ifdef CONFIG_IXGBE_DCB
4377 /* Default traffic class to use for FCoE */
4378 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4379 #endif
4380 #endif /* IXGBE_FCOE */
4381 break;
4382 default:
4383 break;
4384 }
4385
4386 /* n-tuple support exists, always init our spinlock */
4387 spin_lock_init(&adapter->fdir_perfect_lock);
4388
4389 #ifdef CONFIG_IXGBE_DCB
4390 switch (hw->mac.type) {
4391 case ixgbe_mac_X540:
4392 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4393 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4394 break;
4395 default:
4396 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4397 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4398 break;
4399 }
4400
4401 /* Configure DCB traffic classes */
4402 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4403 tc = &adapter->dcb_cfg.tc_config[j];
4404 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4405 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4406 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4407 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4408 tc->dcb_pfc = pfc_disabled;
4409 }
4410
4411 /* Initialize default user to priority mapping, UPx->TC0 */
4412 tc = &adapter->dcb_cfg.tc_config[0];
4413 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4414 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4415
4416 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4417 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4418 adapter->dcb_cfg.pfc_mode_enable = false;
4419 adapter->dcb_set_bitmap = 0x00;
4420 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4421 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4422 sizeof(adapter->temp_dcb_cfg));
4423
4424 #endif
4425
4426 /* default flow control settings */
4427 hw->fc.requested_mode = ixgbe_fc_full;
4428 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4429 #ifdef CONFIG_DCB
4430 adapter->last_lfc_mode = hw->fc.current_mode;
4431 #endif
4432 ixgbe_pbthresh_setup(adapter);
4433 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4434 hw->fc.send_xon = true;
4435 hw->fc.disable_fc_autoneg = false;
4436
4437 /* enable itr by default in dynamic mode */
4438 adapter->rx_itr_setting = 1;
4439 adapter->tx_itr_setting = 1;
4440
4441 /* set default ring sizes */
4442 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4443 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4444
4445 /* set default work limits */
4446 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4447
4448 /* initialize eeprom parameters */
4449 if (ixgbe_init_eeprom_params_generic(hw)) {
4450 e_dev_err("EEPROM initialization failed\n");
4451 return -EIO;
4452 }
4453
4454 set_bit(__IXGBE_DOWN, &adapter->state);
4455
4456 return 0;
4457 }
4458
4459 /**
4460 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4461 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4462 *
4463 * Return 0 on success, negative on failure
4464 **/
4465 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4466 {
4467 struct device *dev = tx_ring->dev;
4468 int orig_node = dev_to_node(dev);
4469 int numa_node = -1;
4470 int size;
4471
4472 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4473
4474 if (tx_ring->q_vector)
4475 numa_node = tx_ring->q_vector->numa_node;
4476
4477 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4478 if (!tx_ring->tx_buffer_info)
4479 tx_ring->tx_buffer_info = vzalloc(size);
4480 if (!tx_ring->tx_buffer_info)
4481 goto err;
4482
4483 /* round up to nearest 4K */
4484 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4485 tx_ring->size = ALIGN(tx_ring->size, 4096);
4486
4487 set_dev_node(dev, numa_node);
4488 tx_ring->desc = dma_alloc_coherent(dev,
4489 tx_ring->size,
4490 &tx_ring->dma,
4491 GFP_KERNEL);
4492 set_dev_node(dev, orig_node);
4493 if (!tx_ring->desc)
4494 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4495 &tx_ring->dma, GFP_KERNEL);
4496 if (!tx_ring->desc)
4497 goto err;
4498
4499 tx_ring->next_to_use = 0;
4500 tx_ring->next_to_clean = 0;
4501 return 0;
4502
4503 err:
4504 vfree(tx_ring->tx_buffer_info);
4505 tx_ring->tx_buffer_info = NULL;
4506 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4507 return -ENOMEM;
4508 }
4509
4510 /**
4511 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4512 * @adapter: board private structure
4513 *
4514 * If this function returns with an error, then it's possible one or
4515 * more of the rings is populated (while the rest are not). It is the
4516 * callers duty to clean those orphaned rings.
4517 *
4518 * Return 0 on success, negative on failure
4519 **/
4520 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4521 {
4522 int i, err = 0;
4523
4524 for (i = 0; i < adapter->num_tx_queues; i++) {
4525 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4526 if (!err)
4527 continue;
4528 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4529 break;
4530 }
4531
4532 return err;
4533 }
4534
4535 /**
4536 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4537 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4538 *
4539 * Returns 0 on success, negative on failure
4540 **/
4541 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4542 {
4543 struct device *dev = rx_ring->dev;
4544 int orig_node = dev_to_node(dev);
4545 int numa_node = -1;
4546 int size;
4547
4548 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4549
4550 if (rx_ring->q_vector)
4551 numa_node = rx_ring->q_vector->numa_node;
4552
4553 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4554 if (!rx_ring->rx_buffer_info)
4555 rx_ring->rx_buffer_info = vzalloc(size);
4556 if (!rx_ring->rx_buffer_info)
4557 goto err;
4558
4559 /* Round up to nearest 4K */
4560 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4561 rx_ring->size = ALIGN(rx_ring->size, 4096);
4562
4563 set_dev_node(dev, numa_node);
4564 rx_ring->desc = dma_alloc_coherent(dev,
4565 rx_ring->size,
4566 &rx_ring->dma,
4567 GFP_KERNEL);
4568 set_dev_node(dev, orig_node);
4569 if (!rx_ring->desc)
4570 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4571 &rx_ring->dma, GFP_KERNEL);
4572 if (!rx_ring->desc)
4573 goto err;
4574
4575 rx_ring->next_to_clean = 0;
4576 rx_ring->next_to_use = 0;
4577
4578 ixgbe_init_rx_page_offset(rx_ring);
4579
4580 return 0;
4581 err:
4582 vfree(rx_ring->rx_buffer_info);
4583 rx_ring->rx_buffer_info = NULL;
4584 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4585 return -ENOMEM;
4586 }
4587
4588 /**
4589 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4590 * @adapter: board private structure
4591 *
4592 * If this function returns with an error, then it's possible one or
4593 * more of the rings is populated (while the rest are not). It is the
4594 * callers duty to clean those orphaned rings.
4595 *
4596 * Return 0 on success, negative on failure
4597 **/
4598 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4599 {
4600 int i, err = 0;
4601
4602 for (i = 0; i < adapter->num_rx_queues; i++) {
4603 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4604 if (!err)
4605 continue;
4606 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4607 break;
4608 }
4609
4610 return err;
4611 }
4612
4613 /**
4614 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4615 * @tx_ring: Tx descriptor ring for a specific queue
4616 *
4617 * Free all transmit software resources
4618 **/
4619 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
4620 {
4621 ixgbe_clean_tx_ring(tx_ring);
4622
4623 vfree(tx_ring->tx_buffer_info);
4624 tx_ring->tx_buffer_info = NULL;
4625
4626 /* if not set, then don't free */
4627 if (!tx_ring->desc)
4628 return;
4629
4630 dma_free_coherent(tx_ring->dev, tx_ring->size,
4631 tx_ring->desc, tx_ring->dma);
4632
4633 tx_ring->desc = NULL;
4634 }
4635
4636 /**
4637 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4638 * @adapter: board private structure
4639 *
4640 * Free all transmit software resources
4641 **/
4642 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4643 {
4644 int i;
4645
4646 for (i = 0; i < adapter->num_tx_queues; i++)
4647 if (adapter->tx_ring[i]->desc)
4648 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4649 }
4650
4651 /**
4652 * ixgbe_free_rx_resources - Free Rx Resources
4653 * @rx_ring: ring to clean the resources from
4654 *
4655 * Free all receive software resources
4656 **/
4657 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
4658 {
4659 ixgbe_clean_rx_ring(rx_ring);
4660
4661 vfree(rx_ring->rx_buffer_info);
4662 rx_ring->rx_buffer_info = NULL;
4663
4664 /* if not set, then don't free */
4665 if (!rx_ring->desc)
4666 return;
4667
4668 dma_free_coherent(rx_ring->dev, rx_ring->size,
4669 rx_ring->desc, rx_ring->dma);
4670
4671 rx_ring->desc = NULL;
4672 }
4673
4674 /**
4675 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4676 * @adapter: board private structure
4677 *
4678 * Free all receive software resources
4679 **/
4680 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4681 {
4682 int i;
4683
4684 for (i = 0; i < adapter->num_rx_queues; i++)
4685 if (adapter->rx_ring[i]->desc)
4686 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4687 }
4688
4689 /**
4690 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4691 * @netdev: network interface device structure
4692 * @new_mtu: new value for maximum frame size
4693 *
4694 * Returns 0 on success, negative on failure
4695 **/
4696 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4697 {
4698 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4699 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4700
4701 /* MTU < 68 is an error and causes problems on some kernels */
4702 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4703 return -EINVAL;
4704
4705 /*
4706 * For 82599EB we cannot allow PF to change MTU greater than 1500
4707 * in SR-IOV mode as it may cause buffer overruns in guest VFs that
4708 * don't allocate and chain buffers correctly.
4709 */
4710 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4711 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4712 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
4713 return -EINVAL;
4714
4715 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
4716
4717 /* must set new MTU before calling down or up */
4718 netdev->mtu = new_mtu;
4719
4720 if (netif_running(netdev))
4721 ixgbe_reinit_locked(adapter);
4722
4723 return 0;
4724 }
4725
4726 /**
4727 * ixgbe_open - Called when a network interface is made active
4728 * @netdev: network interface device structure
4729 *
4730 * Returns 0 on success, negative value on failure
4731 *
4732 * The open entry point is called when a network interface is made
4733 * active by the system (IFF_UP). At this point all resources needed
4734 * for transmit and receive operations are allocated, the interrupt
4735 * handler is registered with the OS, the watchdog timer is started,
4736 * and the stack is notified that the interface is ready.
4737 **/
4738 static int ixgbe_open(struct net_device *netdev)
4739 {
4740 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4741 int err;
4742
4743 /* disallow open during test */
4744 if (test_bit(__IXGBE_TESTING, &adapter->state))
4745 return -EBUSY;
4746
4747 netif_carrier_off(netdev);
4748
4749 /* allocate transmit descriptors */
4750 err = ixgbe_setup_all_tx_resources(adapter);
4751 if (err)
4752 goto err_setup_tx;
4753
4754 /* allocate receive descriptors */
4755 err = ixgbe_setup_all_rx_resources(adapter);
4756 if (err)
4757 goto err_setup_rx;
4758
4759 ixgbe_configure(adapter);
4760
4761 err = ixgbe_request_irq(adapter);
4762 if (err)
4763 goto err_req_irq;
4764
4765 ixgbe_up_complete(adapter);
4766
4767 return 0;
4768
4769 err_req_irq:
4770 err_setup_rx:
4771 ixgbe_free_all_rx_resources(adapter);
4772 err_setup_tx:
4773 ixgbe_free_all_tx_resources(adapter);
4774 ixgbe_reset(adapter);
4775
4776 return err;
4777 }
4778
4779 /**
4780 * ixgbe_close - Disables a network interface
4781 * @netdev: network interface device structure
4782 *
4783 * Returns 0, this is not allowed to fail
4784 *
4785 * The close entry point is called when an interface is de-activated
4786 * by the OS. The hardware is still under the drivers control, but
4787 * needs to be disabled. A global MAC reset is issued to stop the
4788 * hardware, and all transmit and receive resources are freed.
4789 **/
4790 static int ixgbe_close(struct net_device *netdev)
4791 {
4792 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4793
4794 ixgbe_down(adapter);
4795 ixgbe_free_irq(adapter);
4796
4797 ixgbe_fdir_filter_exit(adapter);
4798
4799 ixgbe_free_all_tx_resources(adapter);
4800 ixgbe_free_all_rx_resources(adapter);
4801
4802 ixgbe_release_hw_control(adapter);
4803
4804 return 0;
4805 }
4806
4807 #ifdef CONFIG_PM
4808 static int ixgbe_resume(struct pci_dev *pdev)
4809 {
4810 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4811 struct net_device *netdev = adapter->netdev;
4812 u32 err;
4813
4814 pci_set_power_state(pdev, PCI_D0);
4815 pci_restore_state(pdev);
4816 /*
4817 * pci_restore_state clears dev->state_saved so call
4818 * pci_save_state to restore it.
4819 */
4820 pci_save_state(pdev);
4821
4822 err = pci_enable_device_mem(pdev);
4823 if (err) {
4824 e_dev_err("Cannot enable PCI device from suspend\n");
4825 return err;
4826 }
4827 pci_set_master(pdev);
4828
4829 pci_wake_from_d3(pdev, false);
4830
4831 rtnl_lock();
4832 err = ixgbe_init_interrupt_scheme(adapter);
4833 rtnl_unlock();
4834 if (err) {
4835 e_dev_err("Cannot initialize interrupts for device\n");
4836 return err;
4837 }
4838
4839 ixgbe_reset(adapter);
4840
4841 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4842
4843 if (netif_running(netdev)) {
4844 err = ixgbe_open(netdev);
4845 if (err)
4846 return err;
4847 }
4848
4849 netif_device_attach(netdev);
4850
4851 return 0;
4852 }
4853 #endif /* CONFIG_PM */
4854
4855 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4856 {
4857 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4858 struct net_device *netdev = adapter->netdev;
4859 struct ixgbe_hw *hw = &adapter->hw;
4860 u32 ctrl, fctrl;
4861 u32 wufc = adapter->wol;
4862 #ifdef CONFIG_PM
4863 int retval = 0;
4864 #endif
4865
4866 netif_device_detach(netdev);
4867
4868 if (netif_running(netdev)) {
4869 rtnl_lock();
4870 ixgbe_down(adapter);
4871 ixgbe_free_irq(adapter);
4872 ixgbe_free_all_tx_resources(adapter);
4873 ixgbe_free_all_rx_resources(adapter);
4874 rtnl_unlock();
4875 }
4876
4877 ixgbe_clear_interrupt_scheme(adapter);
4878
4879 #ifdef CONFIG_PM
4880 retval = pci_save_state(pdev);
4881 if (retval)
4882 return retval;
4883
4884 #endif
4885 if (wufc) {
4886 ixgbe_set_rx_mode(netdev);
4887
4888 /*
4889 * enable the optics for both mult-speed fiber and
4890 * 82599 SFP+ fiber as we can WoL.
4891 */
4892 if (hw->mac.ops.enable_tx_laser &&
4893 (hw->phy.multispeed_fiber ||
4894 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber &&
4895 hw->mac.type == ixgbe_mac_82599EB)))
4896 hw->mac.ops.enable_tx_laser(hw);
4897
4898 /* turn on all-multi mode if wake on multicast is enabled */
4899 if (wufc & IXGBE_WUFC_MC) {
4900 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4901 fctrl |= IXGBE_FCTRL_MPE;
4902 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4903 }
4904
4905 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4906 ctrl |= IXGBE_CTRL_GIO_DIS;
4907 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4908
4909 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4910 } else {
4911 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4912 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4913 }
4914
4915 switch (hw->mac.type) {
4916 case ixgbe_mac_82598EB:
4917 pci_wake_from_d3(pdev, false);
4918 break;
4919 case ixgbe_mac_82599EB:
4920 case ixgbe_mac_X540:
4921 pci_wake_from_d3(pdev, !!wufc);
4922 break;
4923 default:
4924 break;
4925 }
4926
4927 *enable_wake = !!wufc;
4928
4929 ixgbe_release_hw_control(adapter);
4930
4931 pci_disable_device(pdev);
4932
4933 return 0;
4934 }
4935
4936 #ifdef CONFIG_PM
4937 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4938 {
4939 int retval;
4940 bool wake;
4941
4942 retval = __ixgbe_shutdown(pdev, &wake);
4943 if (retval)
4944 return retval;
4945
4946 if (wake) {
4947 pci_prepare_to_sleep(pdev);
4948 } else {
4949 pci_wake_from_d3(pdev, false);
4950 pci_set_power_state(pdev, PCI_D3hot);
4951 }
4952
4953 return 0;
4954 }
4955 #endif /* CONFIG_PM */
4956
4957 static void ixgbe_shutdown(struct pci_dev *pdev)
4958 {
4959 bool wake;
4960
4961 __ixgbe_shutdown(pdev, &wake);
4962
4963 if (system_state == SYSTEM_POWER_OFF) {
4964 pci_wake_from_d3(pdev, wake);
4965 pci_set_power_state(pdev, PCI_D3hot);
4966 }
4967 }
4968
4969 /**
4970 * ixgbe_update_stats - Update the board statistics counters.
4971 * @adapter: board private structure
4972 **/
4973 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4974 {
4975 struct net_device *netdev = adapter->netdev;
4976 struct ixgbe_hw *hw = &adapter->hw;
4977 struct ixgbe_hw_stats *hwstats = &adapter->stats;
4978 u64 total_mpc = 0;
4979 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4980 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
4981 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
4982 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
4983 #ifdef IXGBE_FCOE
4984 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4985 unsigned int cpu;
4986 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
4987 #endif /* IXGBE_FCOE */
4988
4989 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4990 test_bit(__IXGBE_RESETTING, &adapter->state))
4991 return;
4992
4993 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
4994 u64 rsc_count = 0;
4995 u64 rsc_flush = 0;
4996 for (i = 0; i < 16; i++)
4997 adapter->hw_rx_no_dma_resources +=
4998 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4999 for (i = 0; i < adapter->num_rx_queues; i++) {
5000 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5001 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5002 }
5003 adapter->rsc_total_count = rsc_count;
5004 adapter->rsc_total_flush = rsc_flush;
5005 }
5006
5007 for (i = 0; i < adapter->num_rx_queues; i++) {
5008 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5009 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5010 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5011 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5012 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5013 bytes += rx_ring->stats.bytes;
5014 packets += rx_ring->stats.packets;
5015 }
5016 adapter->non_eop_descs = non_eop_descs;
5017 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5018 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5019 adapter->hw_csum_rx_error = hw_csum_rx_error;
5020 netdev->stats.rx_bytes = bytes;
5021 netdev->stats.rx_packets = packets;
5022
5023 bytes = 0;
5024 packets = 0;
5025 /* gather some stats to the adapter struct that are per queue */
5026 for (i = 0; i < adapter->num_tx_queues; i++) {
5027 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5028 restart_queue += tx_ring->tx_stats.restart_queue;
5029 tx_busy += tx_ring->tx_stats.tx_busy;
5030 bytes += tx_ring->stats.bytes;
5031 packets += tx_ring->stats.packets;
5032 }
5033 adapter->restart_queue = restart_queue;
5034 adapter->tx_busy = tx_busy;
5035 netdev->stats.tx_bytes = bytes;
5036 netdev->stats.tx_packets = packets;
5037
5038 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5039
5040 /* 8 register reads */
5041 for (i = 0; i < 8; i++) {
5042 /* for packet buffers not used, the register should read 0 */
5043 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5044 missed_rx += mpc;
5045 hwstats->mpc[i] += mpc;
5046 total_mpc += hwstats->mpc[i];
5047 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5048 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5049 switch (hw->mac.type) {
5050 case ixgbe_mac_82598EB:
5051 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5052 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5053 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5054 hwstats->pxonrxc[i] +=
5055 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5056 break;
5057 case ixgbe_mac_82599EB:
5058 case ixgbe_mac_X540:
5059 hwstats->pxonrxc[i] +=
5060 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5061 break;
5062 default:
5063 break;
5064 }
5065 }
5066
5067 /*16 register reads */
5068 for (i = 0; i < 16; i++) {
5069 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5070 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5071 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5072 (hw->mac.type == ixgbe_mac_X540)) {
5073 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5074 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5075 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5076 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5077 }
5078 }
5079
5080 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5081 /* work around hardware counting issue */
5082 hwstats->gprc -= missed_rx;
5083
5084 ixgbe_update_xoff_received(adapter);
5085
5086 /* 82598 hardware only has a 32 bit counter in the high register */
5087 switch (hw->mac.type) {
5088 case ixgbe_mac_82598EB:
5089 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5090 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5091 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5092 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5093 break;
5094 case ixgbe_mac_X540:
5095 /* OS2BMC stats are X540 only*/
5096 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5097 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5098 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5099 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5100 case ixgbe_mac_82599EB:
5101 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5102 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5103 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5104 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5105 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5106 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5107 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5108 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5109 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5110 #ifdef IXGBE_FCOE
5111 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5112 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5113 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5114 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5115 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5116 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5117 /* Add up per cpu counters for total ddp aloc fail */
5118 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5119 for_each_possible_cpu(cpu) {
5120 fcoe_noddp_counts_sum +=
5121 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5122 fcoe_noddp_ext_buff_counts_sum +=
5123 *per_cpu_ptr(fcoe->
5124 pcpu_noddp_ext_buff, cpu);
5125 }
5126 }
5127 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5128 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
5129 #endif /* IXGBE_FCOE */
5130 break;
5131 default:
5132 break;
5133 }
5134 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5135 hwstats->bprc += bprc;
5136 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5137 if (hw->mac.type == ixgbe_mac_82598EB)
5138 hwstats->mprc -= bprc;
5139 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5140 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5141 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5142 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5143 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5144 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5145 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5146 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5147 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5148 hwstats->lxontxc += lxon;
5149 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5150 hwstats->lxofftxc += lxoff;
5151 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5152 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5153 /*
5154 * 82598 errata - tx of flow control packets is included in tx counters
5155 */
5156 xon_off_tot = lxon + lxoff;
5157 hwstats->gptc -= xon_off_tot;
5158 hwstats->mptc -= xon_off_tot;
5159 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5160 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5161 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5162 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5163 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5164 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5165 hwstats->ptc64 -= xon_off_tot;
5166 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5167 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5168 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5169 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5170 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5171 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5172
5173 /* Fill out the OS statistics structure */
5174 netdev->stats.multicast = hwstats->mprc;
5175
5176 /* Rx Errors */
5177 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5178 netdev->stats.rx_dropped = 0;
5179 netdev->stats.rx_length_errors = hwstats->rlec;
5180 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5181 netdev->stats.rx_missed_errors = total_mpc;
5182 }
5183
5184 /**
5185 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5186 * @adapter - pointer to the device adapter structure
5187 **/
5188 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5189 {
5190 struct ixgbe_hw *hw = &adapter->hw;
5191 int i;
5192
5193 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5194 return;
5195
5196 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5197
5198 /* if interface is down do nothing */
5199 if (test_bit(__IXGBE_DOWN, &adapter->state))
5200 return;
5201
5202 /* do nothing if we are not using signature filters */
5203 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5204 return;
5205
5206 adapter->fdir_overflow++;
5207
5208 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5209 for (i = 0; i < adapter->num_tx_queues; i++)
5210 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5211 &(adapter->tx_ring[i]->state));
5212 /* re-enable flow director interrupts */
5213 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5214 } else {
5215 e_err(probe, "failed to finish FDIR re-initialization, "
5216 "ignored adding FDIR ATR filters\n");
5217 }
5218 }
5219
5220 /**
5221 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5222 * @adapter - pointer to the device adapter structure
5223 *
5224 * This function serves two purposes. First it strobes the interrupt lines
5225 * in order to make certain interrupts are occurring. Secondly it sets the
5226 * bits needed to check for TX hangs. As a result we should immediately
5227 * determine if a hang has occurred.
5228 */
5229 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5230 {
5231 struct ixgbe_hw *hw = &adapter->hw;
5232 u64 eics = 0;
5233 int i;
5234
5235 /* If we're down or resetting, just bail */
5236 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5237 test_bit(__IXGBE_RESETTING, &adapter->state))
5238 return;
5239
5240 /* Force detection of hung controller */
5241 if (netif_carrier_ok(adapter->netdev)) {
5242 for (i = 0; i < adapter->num_tx_queues; i++)
5243 set_check_for_tx_hang(adapter->tx_ring[i]);
5244 }
5245
5246 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5247 /*
5248 * for legacy and MSI interrupts don't set any bits
5249 * that are enabled for EIAM, because this operation
5250 * would set *both* EIMS and EICS for any bit in EIAM
5251 */
5252 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5253 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5254 } else {
5255 /* get one bit for every active tx/rx interrupt vector */
5256 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5257 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5258 if (qv->rx.ring || qv->tx.ring)
5259 eics |= ((u64)1 << i);
5260 }
5261 }
5262
5263 /* Cause software interrupt to ensure rings are cleaned */
5264 ixgbe_irq_rearm_queues(adapter, eics);
5265
5266 }
5267
5268 /**
5269 * ixgbe_watchdog_update_link - update the link status
5270 * @adapter - pointer to the device adapter structure
5271 * @link_speed - pointer to a u32 to store the link_speed
5272 **/
5273 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5274 {
5275 struct ixgbe_hw *hw = &adapter->hw;
5276 u32 link_speed = adapter->link_speed;
5277 bool link_up = adapter->link_up;
5278 int i;
5279
5280 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5281 return;
5282
5283 if (hw->mac.ops.check_link) {
5284 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5285 } else {
5286 /* always assume link is up, if no check link function */
5287 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5288 link_up = true;
5289 }
5290 if (link_up) {
5291 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5292 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5293 hw->mac.ops.fc_enable(hw, i);
5294 } else {
5295 hw->mac.ops.fc_enable(hw, 0);
5296 }
5297 }
5298
5299 if (link_up ||
5300 time_after(jiffies, (adapter->link_check_timeout +
5301 IXGBE_TRY_LINK_TIMEOUT))) {
5302 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5303 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5304 IXGBE_WRITE_FLUSH(hw);
5305 }
5306
5307 adapter->link_up = link_up;
5308 adapter->link_speed = link_speed;
5309 }
5310
5311 /**
5312 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5313 * print link up message
5314 * @adapter - pointer to the device adapter structure
5315 **/
5316 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5317 {
5318 struct net_device *netdev = adapter->netdev;
5319 struct ixgbe_hw *hw = &adapter->hw;
5320 u32 link_speed = adapter->link_speed;
5321 bool flow_rx, flow_tx;
5322
5323 /* only continue if link was previously down */
5324 if (netif_carrier_ok(netdev))
5325 return;
5326
5327 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5328
5329 switch (hw->mac.type) {
5330 case ixgbe_mac_82598EB: {
5331 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5332 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5333 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5334 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5335 }
5336 break;
5337 case ixgbe_mac_X540:
5338 case ixgbe_mac_82599EB: {
5339 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5340 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5341 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5342 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5343 }
5344 break;
5345 default:
5346 flow_tx = false;
5347 flow_rx = false;
5348 break;
5349 }
5350 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5351 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5352 "10 Gbps" :
5353 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5354 "1 Gbps" :
5355 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5356 "100 Mbps" :
5357 "unknown speed"))),
5358 ((flow_rx && flow_tx) ? "RX/TX" :
5359 (flow_rx ? "RX" :
5360 (flow_tx ? "TX" : "None"))));
5361
5362 netif_carrier_on(netdev);
5363 ixgbe_check_vf_rate_limit(adapter);
5364 }
5365
5366 /**
5367 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5368 * print link down message
5369 * @adapter - pointer to the adapter structure
5370 **/
5371 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5372 {
5373 struct net_device *netdev = adapter->netdev;
5374 struct ixgbe_hw *hw = &adapter->hw;
5375
5376 adapter->link_up = false;
5377 adapter->link_speed = 0;
5378
5379 /* only continue if link was up previously */
5380 if (!netif_carrier_ok(netdev))
5381 return;
5382
5383 /* poll for SFP+ cable when link is down */
5384 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5385 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5386
5387 e_info(drv, "NIC Link is Down\n");
5388 netif_carrier_off(netdev);
5389 }
5390
5391 /**
5392 * ixgbe_watchdog_flush_tx - flush queues on link down
5393 * @adapter - pointer to the device adapter structure
5394 **/
5395 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5396 {
5397 int i;
5398 int some_tx_pending = 0;
5399
5400 if (!netif_carrier_ok(adapter->netdev)) {
5401 for (i = 0; i < adapter->num_tx_queues; i++) {
5402 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5403 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5404 some_tx_pending = 1;
5405 break;
5406 }
5407 }
5408
5409 if (some_tx_pending) {
5410 /* We've lost link, so the controller stops DMA,
5411 * but we've got queued Tx work that's never going
5412 * to get done, so reset controller to flush Tx.
5413 * (Do the reset outside of interrupt context).
5414 */
5415 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5416 }
5417 }
5418 }
5419
5420 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5421 {
5422 u32 ssvpc;
5423
5424 /* Do not perform spoof check for 82598 */
5425 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5426 return;
5427
5428 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5429
5430 /*
5431 * ssvpc register is cleared on read, if zero then no
5432 * spoofed packets in the last interval.
5433 */
5434 if (!ssvpc)
5435 return;
5436
5437 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5438 }
5439
5440 /**
5441 * ixgbe_watchdog_subtask - check and bring link up
5442 * @adapter - pointer to the device adapter structure
5443 **/
5444 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5445 {
5446 /* if interface is down do nothing */
5447 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5448 test_bit(__IXGBE_RESETTING, &adapter->state))
5449 return;
5450
5451 ixgbe_watchdog_update_link(adapter);
5452
5453 if (adapter->link_up)
5454 ixgbe_watchdog_link_is_up(adapter);
5455 else
5456 ixgbe_watchdog_link_is_down(adapter);
5457
5458 ixgbe_spoof_check(adapter);
5459 ixgbe_update_stats(adapter);
5460
5461 ixgbe_watchdog_flush_tx(adapter);
5462 }
5463
5464 /**
5465 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5466 * @adapter - the ixgbe adapter structure
5467 **/
5468 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5469 {
5470 struct ixgbe_hw *hw = &adapter->hw;
5471 s32 err;
5472
5473 /* not searching for SFP so there is nothing to do here */
5474 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5475 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5476 return;
5477
5478 /* someone else is in init, wait until next service event */
5479 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5480 return;
5481
5482 err = hw->phy.ops.identify_sfp(hw);
5483 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5484 goto sfp_out;
5485
5486 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5487 /* If no cable is present, then we need to reset
5488 * the next time we find a good cable. */
5489 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5490 }
5491
5492 /* exit on error */
5493 if (err)
5494 goto sfp_out;
5495
5496 /* exit if reset not needed */
5497 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5498 goto sfp_out;
5499
5500 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5501
5502 /*
5503 * A module may be identified correctly, but the EEPROM may not have
5504 * support for that module. setup_sfp() will fail in that case, so
5505 * we should not allow that module to load.
5506 */
5507 if (hw->mac.type == ixgbe_mac_82598EB)
5508 err = hw->phy.ops.reset(hw);
5509 else
5510 err = hw->mac.ops.setup_sfp(hw);
5511
5512 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5513 goto sfp_out;
5514
5515 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5516 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5517
5518 sfp_out:
5519 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5520
5521 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5522 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5523 e_dev_err("failed to initialize because an unsupported "
5524 "SFP+ module type was detected.\n");
5525 e_dev_err("Reload the driver after installing a "
5526 "supported module.\n");
5527 unregister_netdev(adapter->netdev);
5528 }
5529 }
5530
5531 /**
5532 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5533 * @adapter - the ixgbe adapter structure
5534 **/
5535 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5536 {
5537 struct ixgbe_hw *hw = &adapter->hw;
5538 u32 autoneg;
5539 bool negotiation;
5540
5541 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5542 return;
5543
5544 /* someone else is in init, wait until next service event */
5545 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5546 return;
5547
5548 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5549
5550 autoneg = hw->phy.autoneg_advertised;
5551 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5552 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5553 if (hw->mac.ops.setup_link)
5554 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5555
5556 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5557 adapter->link_check_timeout = jiffies;
5558 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5559 }
5560
5561 #ifdef CONFIG_PCI_IOV
5562 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5563 {
5564 int vf;
5565 struct ixgbe_hw *hw = &adapter->hw;
5566 struct net_device *netdev = adapter->netdev;
5567 u32 gpc;
5568 u32 ciaa, ciad;
5569
5570 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5571 if (gpc) /* If incrementing then no need for the check below */
5572 return;
5573 /*
5574 * Check to see if a bad DMA write target from an errant or
5575 * malicious VF has caused a PCIe error. If so then we can
5576 * issue a VFLR to the offending VF(s) and then resume without
5577 * requesting a full slot reset.
5578 */
5579
5580 for (vf = 0; vf < adapter->num_vfs; vf++) {
5581 ciaa = (vf << 16) | 0x80000000;
5582 /* 32 bit read so align, we really want status at offset 6 */
5583 ciaa |= PCI_COMMAND;
5584 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5585 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5586 ciaa &= 0x7FFFFFFF;
5587 /* disable debug mode asap after reading data */
5588 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5589 /* Get the upper 16 bits which will be the PCI status reg */
5590 ciad >>= 16;
5591 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5592 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5593 /* Issue VFLR */
5594 ciaa = (vf << 16) | 0x80000000;
5595 ciaa |= 0xA8;
5596 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5597 ciad = 0x00008000; /* VFLR */
5598 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5599 ciaa &= 0x7FFFFFFF;
5600 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5601 }
5602 }
5603 }
5604
5605 #endif
5606 /**
5607 * ixgbe_service_timer - Timer Call-back
5608 * @data: pointer to adapter cast into an unsigned long
5609 **/
5610 static void ixgbe_service_timer(unsigned long data)
5611 {
5612 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5613 unsigned long next_event_offset;
5614 bool ready = true;
5615
5616 /* poll faster when waiting for link */
5617 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5618 next_event_offset = HZ / 10;
5619 else
5620 next_event_offset = HZ * 2;
5621
5622 #ifdef CONFIG_PCI_IOV
5623 /*
5624 * don't bother with SR-IOV VF DMA hang check if there are
5625 * no VFs or the link is down
5626 */
5627 if (!adapter->num_vfs ||
5628 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5629 goto normal_timer_service;
5630
5631 /* If we have VFs allocated then we must check for DMA hangs */
5632 ixgbe_check_for_bad_vf(adapter);
5633 next_event_offset = HZ / 50;
5634 adapter->timer_event_accumulator++;
5635
5636 if (adapter->timer_event_accumulator >= 100)
5637 adapter->timer_event_accumulator = 0;
5638 else
5639 ready = false;
5640
5641 normal_timer_service:
5642 #endif
5643 /* Reset the timer */
5644 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5645
5646 if (ready)
5647 ixgbe_service_event_schedule(adapter);
5648 }
5649
5650 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5651 {
5652 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5653 return;
5654
5655 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5656
5657 /* If we're already down or resetting, just bail */
5658 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5659 test_bit(__IXGBE_RESETTING, &adapter->state))
5660 return;
5661
5662 ixgbe_dump(adapter);
5663 netdev_err(adapter->netdev, "Reset adapter\n");
5664 adapter->tx_timeout_count++;
5665
5666 ixgbe_reinit_locked(adapter);
5667 }
5668
5669 /**
5670 * ixgbe_service_task - manages and runs subtasks
5671 * @work: pointer to work_struct containing our data
5672 **/
5673 static void ixgbe_service_task(struct work_struct *work)
5674 {
5675 struct ixgbe_adapter *adapter = container_of(work,
5676 struct ixgbe_adapter,
5677 service_task);
5678
5679 ixgbe_reset_subtask(adapter);
5680 ixgbe_sfp_detection_subtask(adapter);
5681 ixgbe_sfp_link_config_subtask(adapter);
5682 ixgbe_check_overtemp_subtask(adapter);
5683 ixgbe_watchdog_subtask(adapter);
5684 ixgbe_fdir_reinit_subtask(adapter);
5685 ixgbe_check_hang_subtask(adapter);
5686
5687 ixgbe_service_event_complete(adapter);
5688 }
5689
5690 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5691 struct ixgbe_tx_buffer *first,
5692 u8 *hdr_len)
5693 {
5694 struct sk_buff *skb = first->skb;
5695 u32 vlan_macip_lens, type_tucmd;
5696 u32 mss_l4len_idx, l4len;
5697
5698 if (!skb_is_gso(skb))
5699 return 0;
5700
5701 if (skb_header_cloned(skb)) {
5702 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5703 if (err)
5704 return err;
5705 }
5706
5707 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5708 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5709
5710 if (first->protocol == __constant_htons(ETH_P_IP)) {
5711 struct iphdr *iph = ip_hdr(skb);
5712 iph->tot_len = 0;
5713 iph->check = 0;
5714 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5715 iph->daddr, 0,
5716 IPPROTO_TCP,
5717 0);
5718 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5719 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5720 IXGBE_TX_FLAGS_CSUM |
5721 IXGBE_TX_FLAGS_IPV4;
5722 } else if (skb_is_gso_v6(skb)) {
5723 ipv6_hdr(skb)->payload_len = 0;
5724 tcp_hdr(skb)->check =
5725 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5726 &ipv6_hdr(skb)->daddr,
5727 0, IPPROTO_TCP, 0);
5728 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5729 IXGBE_TX_FLAGS_CSUM;
5730 }
5731
5732 /* compute header lengths */
5733 l4len = tcp_hdrlen(skb);
5734 *hdr_len = skb_transport_offset(skb) + l4len;
5735
5736 /* update gso size and bytecount with header size */
5737 first->gso_segs = skb_shinfo(skb)->gso_segs;
5738 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5739
5740 /* mss_l4len_id: use 1 as index for TSO */
5741 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5742 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5743 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5744
5745 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5746 vlan_macip_lens = skb_network_header_len(skb);
5747 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5748 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5749
5750 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
5751 mss_l4len_idx);
5752
5753 return 1;
5754 }
5755
5756 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5757 struct ixgbe_tx_buffer *first)
5758 {
5759 struct sk_buff *skb = first->skb;
5760 u32 vlan_macip_lens = 0;
5761 u32 mss_l4len_idx = 0;
5762 u32 type_tucmd = 0;
5763
5764 if (skb->ip_summed != CHECKSUM_PARTIAL) {
5765 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
5766 !(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5767 return;
5768 } else {
5769 u8 l4_hdr = 0;
5770 switch (first->protocol) {
5771 case __constant_htons(ETH_P_IP):
5772 vlan_macip_lens |= skb_network_header_len(skb);
5773 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5774 l4_hdr = ip_hdr(skb)->protocol;
5775 break;
5776 case __constant_htons(ETH_P_IPV6):
5777 vlan_macip_lens |= skb_network_header_len(skb);
5778 l4_hdr = ipv6_hdr(skb)->nexthdr;
5779 break;
5780 default:
5781 if (unlikely(net_ratelimit())) {
5782 dev_warn(tx_ring->dev,
5783 "partial checksum but proto=%x!\n",
5784 first->protocol);
5785 }
5786 break;
5787 }
5788
5789 switch (l4_hdr) {
5790 case IPPROTO_TCP:
5791 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5792 mss_l4len_idx = tcp_hdrlen(skb) <<
5793 IXGBE_ADVTXD_L4LEN_SHIFT;
5794 break;
5795 case IPPROTO_SCTP:
5796 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5797 mss_l4len_idx = sizeof(struct sctphdr) <<
5798 IXGBE_ADVTXD_L4LEN_SHIFT;
5799 break;
5800 case IPPROTO_UDP:
5801 mss_l4len_idx = sizeof(struct udphdr) <<
5802 IXGBE_ADVTXD_L4LEN_SHIFT;
5803 break;
5804 default:
5805 if (unlikely(net_ratelimit())) {
5806 dev_warn(tx_ring->dev,
5807 "partial checksum but l4 proto=%x!\n",
5808 l4_hdr);
5809 }
5810 break;
5811 }
5812
5813 /* update TX checksum flag */
5814 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
5815 }
5816
5817 /* vlan_macip_lens: MACLEN, VLAN tag */
5818 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5819 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5820
5821 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
5822 type_tucmd, mss_l4len_idx);
5823 }
5824
5825 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
5826 {
5827 /* set type for advanced descriptor with frame checksum insertion */
5828 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
5829 IXGBE_ADVTXD_DCMD_IFCS |
5830 IXGBE_ADVTXD_DCMD_DEXT);
5831
5832 /* set HW vlan bit if vlan is present */
5833 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
5834 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
5835
5836 /* set segmentation enable bits for TSO/FSO */
5837 #ifdef IXGBE_FCOE
5838 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
5839 #else
5840 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5841 #endif
5842 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
5843
5844 return cmd_type;
5845 }
5846
5847 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
5848 u32 tx_flags, unsigned int paylen)
5849 {
5850 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
5851
5852 /* enable L4 checksum for TSO and TX checksum offload */
5853 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5854 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
5855
5856 /* enble IPv4 checksum for TSO */
5857 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5858 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
5859
5860 /* use index 1 context for TSO/FSO/FCOE */
5861 #ifdef IXGBE_FCOE
5862 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
5863 #else
5864 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5865 #endif
5866 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
5867
5868 /*
5869 * Check Context must be set if Tx switch is enabled, which it
5870 * always is for case where virtual functions are running
5871 */
5872 #ifdef IXGBE_FCOE
5873 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
5874 #else
5875 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
5876 #endif
5877 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
5878
5879 tx_desc->read.olinfo_status = olinfo_status;
5880 }
5881
5882 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
5883 IXGBE_TXD_CMD_RS)
5884
5885 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
5886 struct ixgbe_tx_buffer *first,
5887 const u8 hdr_len)
5888 {
5889 dma_addr_t dma;
5890 struct sk_buff *skb = first->skb;
5891 struct ixgbe_tx_buffer *tx_buffer;
5892 union ixgbe_adv_tx_desc *tx_desc;
5893 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
5894 unsigned int data_len = skb->data_len;
5895 unsigned int size = skb_headlen(skb);
5896 unsigned int paylen = skb->len - hdr_len;
5897 u32 tx_flags = first->tx_flags;
5898 __le32 cmd_type;
5899 u16 i = tx_ring->next_to_use;
5900
5901 tx_desc = IXGBE_TX_DESC(tx_ring, i);
5902
5903 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
5904 cmd_type = ixgbe_tx_cmd_type(tx_flags);
5905
5906 #ifdef IXGBE_FCOE
5907 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5908 if (data_len < sizeof(struct fcoe_crc_eof)) {
5909 size -= sizeof(struct fcoe_crc_eof) - data_len;
5910 data_len = 0;
5911 } else {
5912 data_len -= sizeof(struct fcoe_crc_eof);
5913 }
5914 }
5915
5916 #endif
5917 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
5918 if (dma_mapping_error(tx_ring->dev, dma))
5919 goto dma_error;
5920
5921 /* record length, and DMA address */
5922 dma_unmap_len_set(first, len, size);
5923 dma_unmap_addr_set(first, dma, dma);
5924
5925 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5926
5927 for (;;) {
5928 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
5929 tx_desc->read.cmd_type_len =
5930 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
5931
5932 i++;
5933 tx_desc++;
5934 if (i == tx_ring->count) {
5935 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
5936 i = 0;
5937 }
5938
5939 dma += IXGBE_MAX_DATA_PER_TXD;
5940 size -= IXGBE_MAX_DATA_PER_TXD;
5941
5942 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5943 tx_desc->read.olinfo_status = 0;
5944 }
5945
5946 if (likely(!data_len))
5947 break;
5948
5949 if (unlikely(skb->no_fcs))
5950 cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS));
5951 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
5952
5953 i++;
5954 tx_desc++;
5955 if (i == tx_ring->count) {
5956 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
5957 i = 0;
5958 }
5959
5960 #ifdef IXGBE_FCOE
5961 size = min_t(unsigned int, data_len, skb_frag_size(frag));
5962 #else
5963 size = skb_frag_size(frag);
5964 #endif
5965 data_len -= size;
5966
5967 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
5968 DMA_TO_DEVICE);
5969 if (dma_mapping_error(tx_ring->dev, dma))
5970 goto dma_error;
5971
5972 tx_buffer = &tx_ring->tx_buffer_info[i];
5973 dma_unmap_len_set(tx_buffer, len, size);
5974 dma_unmap_addr_set(tx_buffer, dma, dma);
5975
5976 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5977 tx_desc->read.olinfo_status = 0;
5978
5979 frag++;
5980 }
5981
5982 /* write last descriptor with RS and EOP bits */
5983 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
5984 tx_desc->read.cmd_type_len = cmd_type;
5985
5986 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
5987
5988 /* set the timestamp */
5989 first->time_stamp = jiffies;
5990
5991 /*
5992 * Force memory writes to complete before letting h/w know there
5993 * are new descriptors to fetch. (Only applicable for weak-ordered
5994 * memory model archs, such as IA-64).
5995 *
5996 * We also need this memory barrier to make certain all of the
5997 * status bits have been updated before next_to_watch is written.
5998 */
5999 wmb();
6000
6001 /* set next_to_watch value indicating a packet is present */
6002 first->next_to_watch = tx_desc;
6003
6004 i++;
6005 if (i == tx_ring->count)
6006 i = 0;
6007
6008 tx_ring->next_to_use = i;
6009
6010 /* notify HW of packet */
6011 writel(i, tx_ring->tail);
6012
6013 return;
6014 dma_error:
6015 dev_err(tx_ring->dev, "TX DMA map failed\n");
6016
6017 /* clear dma mappings for failed tx_buffer_info map */
6018 for (;;) {
6019 tx_buffer = &tx_ring->tx_buffer_info[i];
6020 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6021 if (tx_buffer == first)
6022 break;
6023 if (i == 0)
6024 i = tx_ring->count;
6025 i--;
6026 }
6027
6028 tx_ring->next_to_use = i;
6029 }
6030
6031 static void ixgbe_atr(struct ixgbe_ring *ring,
6032 struct ixgbe_tx_buffer *first)
6033 {
6034 struct ixgbe_q_vector *q_vector = ring->q_vector;
6035 union ixgbe_atr_hash_dword input = { .dword = 0 };
6036 union ixgbe_atr_hash_dword common = { .dword = 0 };
6037 union {
6038 unsigned char *network;
6039 struct iphdr *ipv4;
6040 struct ipv6hdr *ipv6;
6041 } hdr;
6042 struct tcphdr *th;
6043 __be16 vlan_id;
6044
6045 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6046 if (!q_vector)
6047 return;
6048
6049 /* do nothing if sampling is disabled */
6050 if (!ring->atr_sample_rate)
6051 return;
6052
6053 ring->atr_count++;
6054
6055 /* snag network header to get L4 type and address */
6056 hdr.network = skb_network_header(first->skb);
6057
6058 /* Currently only IPv4/IPv6 with TCP is supported */
6059 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6060 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6061 (first->protocol != __constant_htons(ETH_P_IP) ||
6062 hdr.ipv4->protocol != IPPROTO_TCP))
6063 return;
6064
6065 th = tcp_hdr(first->skb);
6066
6067 /* skip this packet since it is invalid or the socket is closing */
6068 if (!th || th->fin)
6069 return;
6070
6071 /* sample on all syn packets or once every atr sample count */
6072 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6073 return;
6074
6075 /* reset sample count */
6076 ring->atr_count = 0;
6077
6078 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6079
6080 /*
6081 * src and dst are inverted, think how the receiver sees them
6082 *
6083 * The input is broken into two sections, a non-compressed section
6084 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6085 * is XORed together and stored in the compressed dword.
6086 */
6087 input.formatted.vlan_id = vlan_id;
6088
6089 /*
6090 * since src port and flex bytes occupy the same word XOR them together
6091 * and write the value to source port portion of compressed dword
6092 */
6093 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6094 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6095 else
6096 common.port.src ^= th->dest ^ first->protocol;
6097 common.port.dst ^= th->source;
6098
6099 if (first->protocol == __constant_htons(ETH_P_IP)) {
6100 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6101 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6102 } else {
6103 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6104 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6105 hdr.ipv6->saddr.s6_addr32[1] ^
6106 hdr.ipv6->saddr.s6_addr32[2] ^
6107 hdr.ipv6->saddr.s6_addr32[3] ^
6108 hdr.ipv6->daddr.s6_addr32[0] ^
6109 hdr.ipv6->daddr.s6_addr32[1] ^
6110 hdr.ipv6->daddr.s6_addr32[2] ^
6111 hdr.ipv6->daddr.s6_addr32[3];
6112 }
6113
6114 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6115 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6116 input, common, ring->queue_index);
6117 }
6118
6119 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6120 {
6121 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6122 /* Herbert's original patch had:
6123 * smp_mb__after_netif_stop_queue();
6124 * but since that doesn't exist yet, just open code it. */
6125 smp_mb();
6126
6127 /* We need to check again in a case another CPU has just
6128 * made room available. */
6129 if (likely(ixgbe_desc_unused(tx_ring) < size))
6130 return -EBUSY;
6131
6132 /* A reprieve! - use start_queue because it doesn't call schedule */
6133 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6134 ++tx_ring->tx_stats.restart_queue;
6135 return 0;
6136 }
6137
6138 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6139 {
6140 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6141 return 0;
6142 return __ixgbe_maybe_stop_tx(tx_ring, size);
6143 }
6144
6145 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6146 {
6147 struct ixgbe_adapter *adapter = netdev_priv(dev);
6148 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6149 smp_processor_id();
6150 #ifdef IXGBE_FCOE
6151 __be16 protocol = vlan_get_protocol(skb);
6152
6153 if (((protocol == htons(ETH_P_FCOE)) ||
6154 (protocol == htons(ETH_P_FIP))) &&
6155 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6156 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6157 txq += adapter->ring_feature[RING_F_FCOE].mask;
6158 return txq;
6159 }
6160 #endif
6161
6162 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6163 while (unlikely(txq >= dev->real_num_tx_queues))
6164 txq -= dev->real_num_tx_queues;
6165 return txq;
6166 }
6167
6168 return skb_tx_hash(dev, skb);
6169 }
6170
6171 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6172 struct ixgbe_adapter *adapter,
6173 struct ixgbe_ring *tx_ring)
6174 {
6175 struct ixgbe_tx_buffer *first;
6176 int tso;
6177 u32 tx_flags = 0;
6178 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6179 unsigned short f;
6180 #endif
6181 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6182 __be16 protocol = skb->protocol;
6183 u8 hdr_len = 0;
6184
6185 /*
6186 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6187 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6188 * + 2 desc gap to keep tail from touching head,
6189 * + 1 desc for context descriptor,
6190 * otherwise try next time
6191 */
6192 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6193 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6194 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6195 #else
6196 count += skb_shinfo(skb)->nr_frags;
6197 #endif
6198 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6199 tx_ring->tx_stats.tx_busy++;
6200 return NETDEV_TX_BUSY;
6201 }
6202
6203 /* record the location of the first descriptor for this packet */
6204 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6205 first->skb = skb;
6206 first->bytecount = skb->len;
6207 first->gso_segs = 1;
6208
6209 /* if we have a HW VLAN tag being added default to the HW one */
6210 if (vlan_tx_tag_present(skb)) {
6211 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6212 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6213 /* else if it is a SW VLAN check the next protocol and store the tag */
6214 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6215 struct vlan_hdr *vhdr, _vhdr;
6216 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6217 if (!vhdr)
6218 goto out_drop;
6219
6220 protocol = vhdr->h_vlan_encapsulated_proto;
6221 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6222 IXGBE_TX_FLAGS_VLAN_SHIFT;
6223 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6224 }
6225
6226 #ifdef CONFIG_PCI_IOV
6227 /*
6228 * Use the l2switch_enable flag - would be false if the DMA
6229 * Tx switch had been disabled.
6230 */
6231 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6232 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6233
6234 #endif
6235 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6236 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6237 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6238 (skb->priority != TC_PRIO_CONTROL))) {
6239 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6240 tx_flags |= (skb->priority & 0x7) <<
6241 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6242 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6243 struct vlan_ethhdr *vhdr;
6244 if (skb_header_cloned(skb) &&
6245 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6246 goto out_drop;
6247 vhdr = (struct vlan_ethhdr *)skb->data;
6248 vhdr->h_vlan_TCI = htons(tx_flags >>
6249 IXGBE_TX_FLAGS_VLAN_SHIFT);
6250 } else {
6251 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6252 }
6253 }
6254
6255 /* record initial flags and protocol */
6256 first->tx_flags = tx_flags;
6257 first->protocol = protocol;
6258
6259 #ifdef IXGBE_FCOE
6260 /* setup tx offload for FCoE */
6261 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6262 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6263 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6264 if (tso < 0)
6265 goto out_drop;
6266
6267 goto xmit_fcoe;
6268 }
6269
6270 #endif /* IXGBE_FCOE */
6271 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6272 if (tso < 0)
6273 goto out_drop;
6274 else if (!tso)
6275 ixgbe_tx_csum(tx_ring, first);
6276
6277 /* add the ATR filter if ATR is on */
6278 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6279 ixgbe_atr(tx_ring, first);
6280
6281 #ifdef IXGBE_FCOE
6282 xmit_fcoe:
6283 #endif /* IXGBE_FCOE */
6284 ixgbe_tx_map(tx_ring, first, hdr_len);
6285
6286 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6287
6288 return NETDEV_TX_OK;
6289
6290 out_drop:
6291 dev_kfree_skb_any(first->skb);
6292 first->skb = NULL;
6293
6294 return NETDEV_TX_OK;
6295 }
6296
6297 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6298 struct net_device *netdev)
6299 {
6300 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6301 struct ixgbe_ring *tx_ring;
6302
6303 if (skb->len <= 0) {
6304 dev_kfree_skb_any(skb);
6305 return NETDEV_TX_OK;
6306 }
6307
6308 /*
6309 * The minimum packet size for olinfo paylen is 17 so pad the skb
6310 * in order to meet this minimum size requirement.
6311 */
6312 if (skb->len < 17) {
6313 if (skb_padto(skb, 17))
6314 return NETDEV_TX_OK;
6315 skb->len = 17;
6316 }
6317
6318 tx_ring = adapter->tx_ring[skb->queue_mapping];
6319 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6320 }
6321
6322 /**
6323 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6324 * @netdev: network interface device structure
6325 * @p: pointer to an address structure
6326 *
6327 * Returns 0 on success, negative on failure
6328 **/
6329 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6330 {
6331 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6332 struct ixgbe_hw *hw = &adapter->hw;
6333 struct sockaddr *addr = p;
6334
6335 if (!is_valid_ether_addr(addr->sa_data))
6336 return -EADDRNOTAVAIL;
6337
6338 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6339 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6340
6341 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6342 IXGBE_RAH_AV);
6343
6344 return 0;
6345 }
6346
6347 static int
6348 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6349 {
6350 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6351 struct ixgbe_hw *hw = &adapter->hw;
6352 u16 value;
6353 int rc;
6354
6355 if (prtad != hw->phy.mdio.prtad)
6356 return -EINVAL;
6357 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6358 if (!rc)
6359 rc = value;
6360 return rc;
6361 }
6362
6363 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6364 u16 addr, u16 value)
6365 {
6366 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6367 struct ixgbe_hw *hw = &adapter->hw;
6368
6369 if (prtad != hw->phy.mdio.prtad)
6370 return -EINVAL;
6371 return hw->phy.ops.write_reg(hw, addr, devad, value);
6372 }
6373
6374 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6375 {
6376 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6377
6378 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6379 }
6380
6381 /**
6382 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6383 * netdev->dev_addrs
6384 * @netdev: network interface device structure
6385 *
6386 * Returns non-zero on failure
6387 **/
6388 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6389 {
6390 int err = 0;
6391 struct ixgbe_adapter *adapter = netdev_priv(dev);
6392 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6393
6394 if (is_valid_ether_addr(mac->san_addr)) {
6395 rtnl_lock();
6396 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6397 rtnl_unlock();
6398 }
6399 return err;
6400 }
6401
6402 /**
6403 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6404 * netdev->dev_addrs
6405 * @netdev: network interface device structure
6406 *
6407 * Returns non-zero on failure
6408 **/
6409 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6410 {
6411 int err = 0;
6412 struct ixgbe_adapter *adapter = netdev_priv(dev);
6413 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6414
6415 if (is_valid_ether_addr(mac->san_addr)) {
6416 rtnl_lock();
6417 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6418 rtnl_unlock();
6419 }
6420 return err;
6421 }
6422
6423 #ifdef CONFIG_NET_POLL_CONTROLLER
6424 /*
6425 * Polling 'interrupt' - used by things like netconsole to send skbs
6426 * without having to re-enable interrupts. It's not called while
6427 * the interrupt routine is executing.
6428 */
6429 static void ixgbe_netpoll(struct net_device *netdev)
6430 {
6431 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6432 int i;
6433
6434 /* if interface is down do nothing */
6435 if (test_bit(__IXGBE_DOWN, &adapter->state))
6436 return;
6437
6438 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6439 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6440 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6441 for (i = 0; i < num_q_vectors; i++) {
6442 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6443 ixgbe_msix_clean_rings(0, q_vector);
6444 }
6445 } else {
6446 ixgbe_intr(adapter->pdev->irq, netdev);
6447 }
6448 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6449 }
6450
6451 #endif
6452 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6453 struct rtnl_link_stats64 *stats)
6454 {
6455 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6456 int i;
6457
6458 rcu_read_lock();
6459 for (i = 0; i < adapter->num_rx_queues; i++) {
6460 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6461 u64 bytes, packets;
6462 unsigned int start;
6463
6464 if (ring) {
6465 do {
6466 start = u64_stats_fetch_begin_bh(&ring->syncp);
6467 packets = ring->stats.packets;
6468 bytes = ring->stats.bytes;
6469 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6470 stats->rx_packets += packets;
6471 stats->rx_bytes += bytes;
6472 }
6473 }
6474
6475 for (i = 0; i < adapter->num_tx_queues; i++) {
6476 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6477 u64 bytes, packets;
6478 unsigned int start;
6479
6480 if (ring) {
6481 do {
6482 start = u64_stats_fetch_begin_bh(&ring->syncp);
6483 packets = ring->stats.packets;
6484 bytes = ring->stats.bytes;
6485 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6486 stats->tx_packets += packets;
6487 stats->tx_bytes += bytes;
6488 }
6489 }
6490 rcu_read_unlock();
6491 /* following stats updated by ixgbe_watchdog_task() */
6492 stats->multicast = netdev->stats.multicast;
6493 stats->rx_errors = netdev->stats.rx_errors;
6494 stats->rx_length_errors = netdev->stats.rx_length_errors;
6495 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6496 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6497 return stats;
6498 }
6499
6500 #ifdef CONFIG_IXGBE_DCB
6501 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6502 * #adapter: pointer to ixgbe_adapter
6503 * @tc: number of traffic classes currently enabled
6504 *
6505 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6506 * 802.1Q priority maps to a packet buffer that exists.
6507 */
6508 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6509 {
6510 struct ixgbe_hw *hw = &adapter->hw;
6511 u32 reg, rsave;
6512 int i;
6513
6514 /* 82598 have a static priority to TC mapping that can not
6515 * be changed so no validation is needed.
6516 */
6517 if (hw->mac.type == ixgbe_mac_82598EB)
6518 return;
6519
6520 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6521 rsave = reg;
6522
6523 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6524 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6525
6526 /* If up2tc is out of bounds default to zero */
6527 if (up2tc > tc)
6528 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6529 }
6530
6531 if (reg != rsave)
6532 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6533
6534 return;
6535 }
6536
6537 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
6538 * classes.
6539 *
6540 * @netdev: net device to configure
6541 * @tc: number of traffic classes to enable
6542 */
6543 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6544 {
6545 struct ixgbe_adapter *adapter = netdev_priv(dev);
6546 struct ixgbe_hw *hw = &adapter->hw;
6547
6548 /* Multiple traffic classes requires multiple queues */
6549 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6550 e_err(drv, "Enable failed, needs MSI-X\n");
6551 return -EINVAL;
6552 }
6553
6554 /* Hardware supports up to 8 traffic classes */
6555 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
6556 (hw->mac.type == ixgbe_mac_82598EB &&
6557 tc < MAX_TRAFFIC_CLASS))
6558 return -EINVAL;
6559
6560 /* Hardware has to reinitialize queues and interrupts to
6561 * match packet buffer alignment. Unfortunately, the
6562 * hardware is not flexible enough to do this dynamically.
6563 */
6564 if (netif_running(dev))
6565 ixgbe_close(dev);
6566 ixgbe_clear_interrupt_scheme(adapter);
6567
6568 if (tc) {
6569 netdev_set_num_tc(dev, tc);
6570 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
6571 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6572 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6573
6574 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6575 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6576 } else {
6577 netdev_reset_tc(dev);
6578 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6579
6580 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6581 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6582
6583 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6584 adapter->dcb_cfg.pfc_mode_enable = false;
6585 }
6586
6587 ixgbe_init_interrupt_scheme(adapter);
6588 ixgbe_validate_rtr(adapter, tc);
6589 if (netif_running(dev))
6590 ixgbe_open(dev);
6591
6592 return 0;
6593 }
6594
6595 #endif /* CONFIG_IXGBE_DCB */
6596 void ixgbe_do_reset(struct net_device *netdev)
6597 {
6598 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6599
6600 if (netif_running(netdev))
6601 ixgbe_reinit_locked(adapter);
6602 else
6603 ixgbe_reset(adapter);
6604 }
6605
6606 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
6607 netdev_features_t features)
6608 {
6609 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6610
6611 #ifdef CONFIG_DCB
6612 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6613 features &= ~NETIF_F_HW_VLAN_RX;
6614 #endif
6615
6616 /* return error if RXHASH is being enabled when RSS is not supported */
6617 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
6618 features &= ~NETIF_F_RXHASH;
6619
6620 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6621 if (!(features & NETIF_F_RXCSUM))
6622 features &= ~NETIF_F_LRO;
6623
6624 /* Turn off LRO if not RSC capable */
6625 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6626 features &= ~NETIF_F_LRO;
6627
6628
6629 return features;
6630 }
6631
6632 static int ixgbe_set_features(struct net_device *netdev,
6633 netdev_features_t features)
6634 {
6635 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6636 netdev_features_t changed = netdev->features ^ features;
6637 bool need_reset = false;
6638
6639 /* Make sure RSC matches LRO, reset if change */
6640 if (!(features & NETIF_F_LRO)) {
6641 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6642 need_reset = true;
6643 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6644 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6645 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6646 if (adapter->rx_itr_setting == 1 ||
6647 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6648 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6649 need_reset = true;
6650 } else if ((changed ^ features) & NETIF_F_LRO) {
6651 e_info(probe, "rx-usecs set too low, "
6652 "disabling RSC\n");
6653 }
6654 }
6655
6656 /*
6657 * Check if Flow Director n-tuple support was enabled or disabled. If
6658 * the state changed, we need to reset.
6659 */
6660 if (!(features & NETIF_F_NTUPLE)) {
6661 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
6662 /* turn off Flow Director, set ATR and reset */
6663 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
6664 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
6665 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6666 need_reset = true;
6667 }
6668 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6669 } else if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
6670 /* turn off ATR, enable perfect filters and reset */
6671 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6672 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6673 need_reset = true;
6674 }
6675
6676 if (changed & NETIF_F_RXALL)
6677 need_reset = true;
6678
6679 netdev->features = features;
6680 if (need_reset)
6681 ixgbe_do_reset(netdev);
6682
6683 return 0;
6684 }
6685
6686 static const struct net_device_ops ixgbe_netdev_ops = {
6687 .ndo_open = ixgbe_open,
6688 .ndo_stop = ixgbe_close,
6689 .ndo_start_xmit = ixgbe_xmit_frame,
6690 .ndo_select_queue = ixgbe_select_queue,
6691 .ndo_set_rx_mode = ixgbe_set_rx_mode,
6692 .ndo_validate_addr = eth_validate_addr,
6693 .ndo_set_mac_address = ixgbe_set_mac,
6694 .ndo_change_mtu = ixgbe_change_mtu,
6695 .ndo_tx_timeout = ixgbe_tx_timeout,
6696 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6697 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6698 .ndo_do_ioctl = ixgbe_ioctl,
6699 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6700 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6701 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6702 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
6703 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
6704 .ndo_get_stats64 = ixgbe_get_stats64,
6705 #ifdef CONFIG_IXGBE_DCB
6706 .ndo_setup_tc = ixgbe_setup_tc,
6707 #endif
6708 #ifdef CONFIG_NET_POLL_CONTROLLER
6709 .ndo_poll_controller = ixgbe_netpoll,
6710 #endif
6711 #ifdef IXGBE_FCOE
6712 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6713 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
6714 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6715 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6716 .ndo_fcoe_disable = ixgbe_fcoe_disable,
6717 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6718 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
6719 #endif /* IXGBE_FCOE */
6720 .ndo_set_features = ixgbe_set_features,
6721 .ndo_fix_features = ixgbe_fix_features,
6722 };
6723
6724 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6725 const struct ixgbe_info *ii)
6726 {
6727 #ifdef CONFIG_PCI_IOV
6728 struct ixgbe_hw *hw = &adapter->hw;
6729
6730 if (hw->mac.type == ixgbe_mac_82598EB)
6731 return;
6732
6733 /* The 82599 supports up to 64 VFs per physical function
6734 * but this implementation limits allocation to 63 so that
6735 * basic networking resources are still available to the
6736 * physical function
6737 */
6738 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6739 ixgbe_enable_sriov(adapter, ii);
6740 #endif /* CONFIG_PCI_IOV */
6741 }
6742
6743 /**
6744 * ixgbe_probe - Device Initialization Routine
6745 * @pdev: PCI device information struct
6746 * @ent: entry in ixgbe_pci_tbl
6747 *
6748 * Returns 0 on success, negative on failure
6749 *
6750 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6751 * The OS initialization, configuring of the adapter private structure,
6752 * and a hardware reset occur.
6753 **/
6754 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6755 const struct pci_device_id *ent)
6756 {
6757 struct net_device *netdev;
6758 struct ixgbe_adapter *adapter = NULL;
6759 struct ixgbe_hw *hw;
6760 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6761 static int cards_found;
6762 int i, err, pci_using_dac;
6763 u8 part_str[IXGBE_PBANUM_LENGTH];
6764 unsigned int indices = num_possible_cpus();
6765 #ifdef IXGBE_FCOE
6766 u16 device_caps;
6767 #endif
6768 u32 eec;
6769 u16 wol_cap;
6770
6771 /* Catch broken hardware that put the wrong VF device ID in
6772 * the PCIe SR-IOV capability.
6773 */
6774 if (pdev->is_virtfn) {
6775 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6776 pci_name(pdev), pdev->vendor, pdev->device);
6777 return -EINVAL;
6778 }
6779
6780 err = pci_enable_device_mem(pdev);
6781 if (err)
6782 return err;
6783
6784 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6785 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6786 pci_using_dac = 1;
6787 } else {
6788 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6789 if (err) {
6790 err = dma_set_coherent_mask(&pdev->dev,
6791 DMA_BIT_MASK(32));
6792 if (err) {
6793 dev_err(&pdev->dev,
6794 "No usable DMA configuration, aborting\n");
6795 goto err_dma;
6796 }
6797 }
6798 pci_using_dac = 0;
6799 }
6800
6801 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6802 IORESOURCE_MEM), ixgbe_driver_name);
6803 if (err) {
6804 dev_err(&pdev->dev,
6805 "pci_request_selected_regions failed 0x%x\n", err);
6806 goto err_pci_reg;
6807 }
6808
6809 pci_enable_pcie_error_reporting(pdev);
6810
6811 pci_set_master(pdev);
6812 pci_save_state(pdev);
6813
6814 #ifdef CONFIG_IXGBE_DCB
6815 indices *= MAX_TRAFFIC_CLASS;
6816 #endif
6817
6818 if (ii->mac == ixgbe_mac_82598EB)
6819 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6820 else
6821 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6822
6823 #ifdef IXGBE_FCOE
6824 indices += min_t(unsigned int, num_possible_cpus(),
6825 IXGBE_MAX_FCOE_INDICES);
6826 #endif
6827 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6828 if (!netdev) {
6829 err = -ENOMEM;
6830 goto err_alloc_etherdev;
6831 }
6832
6833 SET_NETDEV_DEV(netdev, &pdev->dev);
6834
6835 adapter = netdev_priv(netdev);
6836 pci_set_drvdata(pdev, adapter);
6837
6838 adapter->netdev = netdev;
6839 adapter->pdev = pdev;
6840 hw = &adapter->hw;
6841 hw->back = adapter;
6842 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
6843
6844 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6845 pci_resource_len(pdev, 0));
6846 if (!hw->hw_addr) {
6847 err = -EIO;
6848 goto err_ioremap;
6849 }
6850
6851 for (i = 1; i <= 5; i++) {
6852 if (pci_resource_len(pdev, i) == 0)
6853 continue;
6854 }
6855
6856 netdev->netdev_ops = &ixgbe_netdev_ops;
6857 ixgbe_set_ethtool_ops(netdev);
6858 netdev->watchdog_timeo = 5 * HZ;
6859 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
6860
6861 adapter->bd_number = cards_found;
6862
6863 /* Setup hw api */
6864 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6865 hw->mac.type = ii->mac;
6866
6867 /* EEPROM */
6868 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6869 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6870 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6871 if (!(eec & (1 << 8)))
6872 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6873
6874 /* PHY */
6875 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6876 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6877 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6878 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6879 hw->phy.mdio.mmds = 0;
6880 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6881 hw->phy.mdio.dev = netdev;
6882 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6883 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6884
6885 ii->get_invariants(hw);
6886
6887 /* setup the private structure */
6888 err = ixgbe_sw_init(adapter);
6889 if (err)
6890 goto err_sw_init;
6891
6892 /* Make it possible the adapter to be woken up via WOL */
6893 switch (adapter->hw.mac.type) {
6894 case ixgbe_mac_82599EB:
6895 case ixgbe_mac_X540:
6896 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6897 break;
6898 default:
6899 break;
6900 }
6901
6902 /*
6903 * If there is a fan on this device and it has failed log the
6904 * failure.
6905 */
6906 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6907 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6908 if (esdp & IXGBE_ESDP_SDP1)
6909 e_crit(probe, "Fan has stopped, replace the adapter\n");
6910 }
6911
6912 if (allow_unsupported_sfp)
6913 hw->allow_unsupported_sfp = allow_unsupported_sfp;
6914
6915 /* reset_hw fills in the perm_addr as well */
6916 hw->phy.reset_if_overtemp = true;
6917 err = hw->mac.ops.reset_hw(hw);
6918 hw->phy.reset_if_overtemp = false;
6919 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6920 hw->mac.type == ixgbe_mac_82598EB) {
6921 err = 0;
6922 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6923 e_dev_err("failed to load because an unsupported SFP+ "
6924 "module type was detected.\n");
6925 e_dev_err("Reload the driver after installing a supported "
6926 "module.\n");
6927 goto err_sw_init;
6928 } else if (err) {
6929 e_dev_err("HW Init failed: %d\n", err);
6930 goto err_sw_init;
6931 }
6932
6933 ixgbe_probe_vf(adapter, ii);
6934
6935 netdev->features = NETIF_F_SG |
6936 NETIF_F_IP_CSUM |
6937 NETIF_F_IPV6_CSUM |
6938 NETIF_F_HW_VLAN_TX |
6939 NETIF_F_HW_VLAN_RX |
6940 NETIF_F_HW_VLAN_FILTER |
6941 NETIF_F_TSO |
6942 NETIF_F_TSO6 |
6943 NETIF_F_RXHASH |
6944 NETIF_F_RXCSUM;
6945
6946 netdev->hw_features = netdev->features;
6947
6948 switch (adapter->hw.mac.type) {
6949 case ixgbe_mac_82599EB:
6950 case ixgbe_mac_X540:
6951 netdev->features |= NETIF_F_SCTP_CSUM;
6952 netdev->hw_features |= NETIF_F_SCTP_CSUM |
6953 NETIF_F_NTUPLE;
6954 break;
6955 default:
6956 break;
6957 }
6958
6959 netdev->hw_features |= NETIF_F_RXALL;
6960
6961 netdev->vlan_features |= NETIF_F_TSO;
6962 netdev->vlan_features |= NETIF_F_TSO6;
6963 netdev->vlan_features |= NETIF_F_IP_CSUM;
6964 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6965 netdev->vlan_features |= NETIF_F_SG;
6966
6967 netdev->priv_flags |= IFF_UNICAST_FLT;
6968 netdev->priv_flags |= IFF_SUPP_NOFCS;
6969
6970 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6971 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6972 IXGBE_FLAG_DCB_ENABLED);
6973
6974 #ifdef CONFIG_IXGBE_DCB
6975 netdev->dcbnl_ops = &dcbnl_ops;
6976 #endif
6977
6978 #ifdef IXGBE_FCOE
6979 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6980 if (hw->mac.ops.get_device_caps) {
6981 hw->mac.ops.get_device_caps(hw, &device_caps);
6982 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6983 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6984 }
6985 }
6986 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6987 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6988 netdev->vlan_features |= NETIF_F_FSO;
6989 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6990 }
6991 #endif /* IXGBE_FCOE */
6992 if (pci_using_dac) {
6993 netdev->features |= NETIF_F_HIGHDMA;
6994 netdev->vlan_features |= NETIF_F_HIGHDMA;
6995 }
6996
6997 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
6998 netdev->hw_features |= NETIF_F_LRO;
6999 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7000 netdev->features |= NETIF_F_LRO;
7001
7002 /* make sure the EEPROM is good */
7003 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7004 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7005 err = -EIO;
7006 goto err_sw_init;
7007 }
7008
7009 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7010 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7011
7012 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7013 e_dev_err("invalid MAC address\n");
7014 err = -EIO;
7015 goto err_sw_init;
7016 }
7017
7018 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7019 (unsigned long) adapter);
7020
7021 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7022 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7023
7024 err = ixgbe_init_interrupt_scheme(adapter);
7025 if (err)
7026 goto err_sw_init;
7027
7028 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7029 netdev->hw_features &= ~NETIF_F_RXHASH;
7030 netdev->features &= ~NETIF_F_RXHASH;
7031 }
7032
7033 /* WOL not supported for all but the following */
7034 adapter->wol = 0;
7035 switch (pdev->device) {
7036 case IXGBE_DEV_ID_82599_SFP:
7037 /* Only these subdevice supports WOL */
7038 switch (pdev->subsystem_device) {
7039 case IXGBE_SUBDEV_ID_82599_560FLR:
7040 /* only support first port */
7041 if (hw->bus.func != 0)
7042 break;
7043 case IXGBE_SUBDEV_ID_82599_SFP:
7044 adapter->wol = IXGBE_WUFC_MAG;
7045 break;
7046 }
7047 break;
7048 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7049 /* All except this subdevice support WOL */
7050 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7051 adapter->wol = IXGBE_WUFC_MAG;
7052 break;
7053 case IXGBE_DEV_ID_82599_KX4:
7054 adapter->wol = IXGBE_WUFC_MAG;
7055 break;
7056 case IXGBE_DEV_ID_X540T:
7057 /* Check eeprom to see if it is enabled */
7058 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7059 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7060
7061 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7062 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7063 (hw->bus.func == 0)))
7064 adapter->wol = IXGBE_WUFC_MAG;
7065 break;
7066 }
7067 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7068
7069 /* save off EEPROM version number */
7070 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7071 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7072
7073 /* pick up the PCI bus settings for reporting later */
7074 hw->mac.ops.get_bus_info(hw);
7075
7076 /* print bus type/speed/width info */
7077 e_dev_info("(PCI Express:%s:%s) %pM\n",
7078 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7079 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7080 "Unknown"),
7081 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7082 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7083 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7084 "Unknown"),
7085 netdev->dev_addr);
7086
7087 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7088 if (err)
7089 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7090 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7091 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7092 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7093 part_str);
7094 else
7095 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7096 hw->mac.type, hw->phy.type, part_str);
7097
7098 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7099 e_dev_warn("PCI-Express bandwidth available for this card is "
7100 "not sufficient for optimal performance.\n");
7101 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7102 "is required.\n");
7103 }
7104
7105 /* reset the hardware with the new settings */
7106 err = hw->mac.ops.start_hw(hw);
7107 if (err == IXGBE_ERR_EEPROM_VERSION) {
7108 /* We are running on a pre-production device, log a warning */
7109 e_dev_warn("This device is a pre-production adapter/LOM. "
7110 "Please be aware there may be issues associated "
7111 "with your hardware. If you are experiencing "
7112 "problems please contact your Intel or hardware "
7113 "representative who provided you with this "
7114 "hardware.\n");
7115 }
7116 strcpy(netdev->name, "eth%d");
7117 err = register_netdev(netdev);
7118 if (err)
7119 goto err_register;
7120
7121 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7122 if (hw->mac.ops.disable_tx_laser &&
7123 ((hw->phy.multispeed_fiber) ||
7124 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7125 (hw->mac.type == ixgbe_mac_82599EB))))
7126 hw->mac.ops.disable_tx_laser(hw);
7127
7128 /* carrier off reporting is important to ethtool even BEFORE open */
7129 netif_carrier_off(netdev);
7130
7131 #ifdef CONFIG_IXGBE_DCA
7132 if (dca_add_requester(&pdev->dev) == 0) {
7133 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7134 ixgbe_setup_dca(adapter);
7135 }
7136 #endif
7137 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7138 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7139 for (i = 0; i < adapter->num_vfs; i++)
7140 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7141 }
7142
7143 /* firmware requires driver version to be 0xFFFFFFFF
7144 * since os does not support feature
7145 */
7146 if (hw->mac.ops.set_fw_drv_ver)
7147 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7148 0xFF);
7149
7150 /* add san mac addr to netdev */
7151 ixgbe_add_sanmac_netdev(netdev);
7152
7153 e_dev_info("%s\n", ixgbe_default_device_descr);
7154 cards_found++;
7155 return 0;
7156
7157 err_register:
7158 ixgbe_release_hw_control(adapter);
7159 ixgbe_clear_interrupt_scheme(adapter);
7160 err_sw_init:
7161 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7162 ixgbe_disable_sriov(adapter);
7163 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7164 iounmap(hw->hw_addr);
7165 err_ioremap:
7166 free_netdev(netdev);
7167 err_alloc_etherdev:
7168 pci_release_selected_regions(pdev,
7169 pci_select_bars(pdev, IORESOURCE_MEM));
7170 err_pci_reg:
7171 err_dma:
7172 pci_disable_device(pdev);
7173 return err;
7174 }
7175
7176 /**
7177 * ixgbe_remove - Device Removal Routine
7178 * @pdev: PCI device information struct
7179 *
7180 * ixgbe_remove is called by the PCI subsystem to alert the driver
7181 * that it should release a PCI device. The could be caused by a
7182 * Hot-Plug event, or because the driver is going to be removed from
7183 * memory.
7184 **/
7185 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7186 {
7187 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7188 struct net_device *netdev = adapter->netdev;
7189
7190 set_bit(__IXGBE_DOWN, &adapter->state);
7191 cancel_work_sync(&adapter->service_task);
7192
7193 #ifdef CONFIG_IXGBE_DCA
7194 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7195 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7196 dca_remove_requester(&pdev->dev);
7197 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7198 }
7199
7200 #endif
7201 #ifdef IXGBE_FCOE
7202 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7203 ixgbe_cleanup_fcoe(adapter);
7204
7205 #endif /* IXGBE_FCOE */
7206
7207 /* remove the added san mac */
7208 ixgbe_del_sanmac_netdev(netdev);
7209
7210 if (netdev->reg_state == NETREG_REGISTERED)
7211 unregister_netdev(netdev);
7212
7213 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7214 if (!(ixgbe_check_vf_assignment(adapter)))
7215 ixgbe_disable_sriov(adapter);
7216 else
7217 e_dev_warn("Unloading driver while VFs are assigned "
7218 "- VFs will not be deallocated\n");
7219 }
7220
7221 ixgbe_clear_interrupt_scheme(adapter);
7222
7223 ixgbe_release_hw_control(adapter);
7224
7225 #ifdef CONFIG_DCB
7226 kfree(adapter->ixgbe_ieee_pfc);
7227 kfree(adapter->ixgbe_ieee_ets);
7228
7229 #endif
7230 iounmap(adapter->hw.hw_addr);
7231 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7232 IORESOURCE_MEM));
7233
7234 e_dev_info("complete\n");
7235
7236 free_netdev(netdev);
7237
7238 pci_disable_pcie_error_reporting(pdev);
7239
7240 pci_disable_device(pdev);
7241 }
7242
7243 /**
7244 * ixgbe_io_error_detected - called when PCI error is detected
7245 * @pdev: Pointer to PCI device
7246 * @state: The current pci connection state
7247 *
7248 * This function is called after a PCI bus error affecting
7249 * this device has been detected.
7250 */
7251 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7252 pci_channel_state_t state)
7253 {
7254 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7255 struct net_device *netdev = adapter->netdev;
7256
7257 #ifdef CONFIG_PCI_IOV
7258 struct pci_dev *bdev, *vfdev;
7259 u32 dw0, dw1, dw2, dw3;
7260 int vf, pos;
7261 u16 req_id, pf_func;
7262
7263 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7264 adapter->num_vfs == 0)
7265 goto skip_bad_vf_detection;
7266
7267 bdev = pdev->bus->self;
7268 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7269 bdev = bdev->bus->self;
7270
7271 if (!bdev)
7272 goto skip_bad_vf_detection;
7273
7274 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7275 if (!pos)
7276 goto skip_bad_vf_detection;
7277
7278 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7279 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7280 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7281 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7282
7283 req_id = dw1 >> 16;
7284 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7285 if (!(req_id & 0x0080))
7286 goto skip_bad_vf_detection;
7287
7288 pf_func = req_id & 0x01;
7289 if ((pf_func & 1) == (pdev->devfn & 1)) {
7290 unsigned int device_id;
7291
7292 vf = (req_id & 0x7F) >> 1;
7293 e_dev_err("VF %d has caused a PCIe error\n", vf);
7294 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7295 "%8.8x\tdw3: %8.8x\n",
7296 dw0, dw1, dw2, dw3);
7297 switch (adapter->hw.mac.type) {
7298 case ixgbe_mac_82599EB:
7299 device_id = IXGBE_82599_VF_DEVICE_ID;
7300 break;
7301 case ixgbe_mac_X540:
7302 device_id = IXGBE_X540_VF_DEVICE_ID;
7303 break;
7304 default:
7305 device_id = 0;
7306 break;
7307 }
7308
7309 /* Find the pci device of the offending VF */
7310 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
7311 while (vfdev) {
7312 if (vfdev->devfn == (req_id & 0xFF))
7313 break;
7314 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
7315 device_id, vfdev);
7316 }
7317 /*
7318 * There's a slim chance the VF could have been hot plugged,
7319 * so if it is no longer present we don't need to issue the
7320 * VFLR. Just clean up the AER in that case.
7321 */
7322 if (vfdev) {
7323 e_dev_err("Issuing VFLR to VF %d\n", vf);
7324 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7325 }
7326
7327 pci_cleanup_aer_uncorrect_error_status(pdev);
7328 }
7329
7330 /*
7331 * Even though the error may have occurred on the other port
7332 * we still need to increment the vf error reference count for
7333 * both ports because the I/O resume function will be called
7334 * for both of them.
7335 */
7336 adapter->vferr_refcount++;
7337
7338 return PCI_ERS_RESULT_RECOVERED;
7339
7340 skip_bad_vf_detection:
7341 #endif /* CONFIG_PCI_IOV */
7342 netif_device_detach(netdev);
7343
7344 if (state == pci_channel_io_perm_failure)
7345 return PCI_ERS_RESULT_DISCONNECT;
7346
7347 if (netif_running(netdev))
7348 ixgbe_down(adapter);
7349 pci_disable_device(pdev);
7350
7351 /* Request a slot reset. */
7352 return PCI_ERS_RESULT_NEED_RESET;
7353 }
7354
7355 /**
7356 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7357 * @pdev: Pointer to PCI device
7358 *
7359 * Restart the card from scratch, as if from a cold-boot.
7360 */
7361 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7362 {
7363 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7364 pci_ers_result_t result;
7365 int err;
7366
7367 if (pci_enable_device_mem(pdev)) {
7368 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7369 result = PCI_ERS_RESULT_DISCONNECT;
7370 } else {
7371 pci_set_master(pdev);
7372 pci_restore_state(pdev);
7373 pci_save_state(pdev);
7374
7375 pci_wake_from_d3(pdev, false);
7376
7377 ixgbe_reset(adapter);
7378 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7379 result = PCI_ERS_RESULT_RECOVERED;
7380 }
7381
7382 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7383 if (err) {
7384 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7385 "failed 0x%0x\n", err);
7386 /* non-fatal, continue */
7387 }
7388
7389 return result;
7390 }
7391
7392 /**
7393 * ixgbe_io_resume - called when traffic can start flowing again.
7394 * @pdev: Pointer to PCI device
7395 *
7396 * This callback is called when the error recovery driver tells us that
7397 * its OK to resume normal operation.
7398 */
7399 static void ixgbe_io_resume(struct pci_dev *pdev)
7400 {
7401 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7402 struct net_device *netdev = adapter->netdev;
7403
7404 #ifdef CONFIG_PCI_IOV
7405 if (adapter->vferr_refcount) {
7406 e_info(drv, "Resuming after VF err\n");
7407 adapter->vferr_refcount--;
7408 return;
7409 }
7410
7411 #endif
7412 if (netif_running(netdev))
7413 ixgbe_up(adapter);
7414
7415 netif_device_attach(netdev);
7416 }
7417
7418 static struct pci_error_handlers ixgbe_err_handler = {
7419 .error_detected = ixgbe_io_error_detected,
7420 .slot_reset = ixgbe_io_slot_reset,
7421 .resume = ixgbe_io_resume,
7422 };
7423
7424 static struct pci_driver ixgbe_driver = {
7425 .name = ixgbe_driver_name,
7426 .id_table = ixgbe_pci_tbl,
7427 .probe = ixgbe_probe,
7428 .remove = __devexit_p(ixgbe_remove),
7429 #ifdef CONFIG_PM
7430 .suspend = ixgbe_suspend,
7431 .resume = ixgbe_resume,
7432 #endif
7433 .shutdown = ixgbe_shutdown,
7434 .err_handler = &ixgbe_err_handler
7435 };
7436
7437 /**
7438 * ixgbe_init_module - Driver Registration Routine
7439 *
7440 * ixgbe_init_module is the first routine called when the driver is
7441 * loaded. All it does is register with the PCI subsystem.
7442 **/
7443 static int __init ixgbe_init_module(void)
7444 {
7445 int ret;
7446 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7447 pr_info("%s\n", ixgbe_copyright);
7448
7449 #ifdef CONFIG_IXGBE_DCA
7450 dca_register_notify(&dca_notifier);
7451 #endif
7452
7453 ret = pci_register_driver(&ixgbe_driver);
7454 return ret;
7455 }
7456
7457 module_init(ixgbe_init_module);
7458
7459 /**
7460 * ixgbe_exit_module - Driver Exit Cleanup Routine
7461 *
7462 * ixgbe_exit_module is called just before the driver is removed
7463 * from memory.
7464 **/
7465 static void __exit ixgbe_exit_module(void)
7466 {
7467 #ifdef CONFIG_IXGBE_DCA
7468 dca_unregister_notify(&dca_notifier);
7469 #endif
7470 pci_unregister_driver(&ixgbe_driver);
7471 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7472 }
7473
7474 #ifdef CONFIG_IXGBE_DCA
7475 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7476 void *p)
7477 {
7478 int ret_val;
7479
7480 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7481 __ixgbe_notify_dca);
7482
7483 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7484 }
7485
7486 #endif /* CONFIG_IXGBE_DCA */
7487
7488 module_exit(ixgbe_exit_module);
7489
7490 /* ixgbe_main.c */
Linux kernel - Deliverables
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