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ixgbe: Add support for SFPs with retimer
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2016 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/types.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/vmalloc.h>
34 #include <linux/string.h>
35 #include <linux/in.h>
36 #include <linux/interrupt.h>
37 #include <linux/ip.h>
38 #include <linux/tcp.h>
39 #include <linux/sctp.h>
40 #include <linux/pkt_sched.h>
41 #include <linux/ipv6.h>
42 #include <linux/slab.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/etherdevice.h>
46 #include <linux/ethtool.h>
47 #include <linux/if.h>
48 #include <linux/if_vlan.h>
49 #include <linux/if_macvlan.h>
50 #include <linux/if_bridge.h>
51 #include <linux/prefetch.h>
52 #include <scsi/fc/fc_fcoe.h>
53 #include <net/vxlan.h>
54 #include <net/pkt_cls.h>
55 #include <net/tc_act/tc_gact.h>
56
57 #include "ixgbe.h"
58 #include "ixgbe_common.h"
59 #include "ixgbe_dcb_82599.h"
60 #include "ixgbe_sriov.h"
61 #include "ixgbe_model.h"
62
63 char ixgbe_driver_name[] = "ixgbe";
64 static const char ixgbe_driver_string[] =
65 "Intel(R) 10 Gigabit PCI Express Network Driver";
66 #ifdef IXGBE_FCOE
67 char ixgbe_default_device_descr[] =
68 "Intel(R) 10 Gigabit Network Connection";
69 #else
70 static char ixgbe_default_device_descr[] =
71 "Intel(R) 10 Gigabit Network Connection";
72 #endif
73 #define DRV_VERSION "4.2.1-k"
74 const char ixgbe_driver_version[] = DRV_VERSION;
75 static const char ixgbe_copyright[] =
76 "Copyright (c) 1999-2016 Intel Corporation.";
77
78 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
79
80 static const struct ixgbe_info *ixgbe_info_tbl[] = {
81 [board_82598] = &ixgbe_82598_info,
82 [board_82599] = &ixgbe_82599_info,
83 [board_X540] = &ixgbe_X540_info,
84 [board_X550] = &ixgbe_X550_info,
85 [board_X550EM_x] = &ixgbe_X550EM_x_info,
86 [board_x550em_a] = &ixgbe_x550em_a_info,
87 };
88
89 /* ixgbe_pci_tbl - PCI Device ID Table
90 *
91 * Wildcard entries (PCI_ANY_ID) should come last
92 * Last entry must be all 0s
93 *
94 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
95 * Class, Class Mask, private data (not used) }
96 */
97 static const struct pci_device_id ixgbe_pci_tbl[] = {
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550},
130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a },
135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a },
136 /* required last entry */
137 {0, }
138 };
139 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
140
141 #ifdef CONFIG_IXGBE_DCA
142 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
143 void *p);
144 static struct notifier_block dca_notifier = {
145 .notifier_call = ixgbe_notify_dca,
146 .next = NULL,
147 .priority = 0
148 };
149 #endif
150
151 #ifdef CONFIG_PCI_IOV
152 static unsigned int max_vfs;
153 module_param(max_vfs, uint, 0);
154 MODULE_PARM_DESC(max_vfs,
155 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
156 #endif /* CONFIG_PCI_IOV */
157
158 static unsigned int allow_unsupported_sfp;
159 module_param(allow_unsupported_sfp, uint, 0);
160 MODULE_PARM_DESC(allow_unsupported_sfp,
161 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
162
163 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
164 static int debug = -1;
165 module_param(debug, int, 0);
166 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
167
168 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
169 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
170 MODULE_LICENSE("GPL");
171 MODULE_VERSION(DRV_VERSION);
172
173 static struct workqueue_struct *ixgbe_wq;
174
175 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
176
177 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
178 u32 reg, u16 *value)
179 {
180 struct pci_dev *parent_dev;
181 struct pci_bus *parent_bus;
182
183 parent_bus = adapter->pdev->bus->parent;
184 if (!parent_bus)
185 return -1;
186
187 parent_dev = parent_bus->self;
188 if (!parent_dev)
189 return -1;
190
191 if (!pci_is_pcie(parent_dev))
192 return -1;
193
194 pcie_capability_read_word(parent_dev, reg, value);
195 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
196 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
197 return -1;
198 return 0;
199 }
200
201 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
202 {
203 struct ixgbe_hw *hw = &adapter->hw;
204 u16 link_status = 0;
205 int err;
206
207 hw->bus.type = ixgbe_bus_type_pci_express;
208
209 /* Get the negotiated link width and speed from PCI config space of the
210 * parent, as this device is behind a switch
211 */
212 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
213
214 /* assume caller will handle error case */
215 if (err)
216 return err;
217
218 hw->bus.width = ixgbe_convert_bus_width(link_status);
219 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
220
221 return 0;
222 }
223
224 /**
225 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
226 * @hw: hw specific details
227 *
228 * This function is used by probe to determine whether a device's PCI-Express
229 * bandwidth details should be gathered from the parent bus instead of from the
230 * device. Used to ensure that various locations all have the correct device ID
231 * checks.
232 */
233 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
234 {
235 switch (hw->device_id) {
236 case IXGBE_DEV_ID_82599_SFP_SF_QP:
237 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
238 return true;
239 default:
240 return false;
241 }
242 }
243
244 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
245 int expected_gts)
246 {
247 struct ixgbe_hw *hw = &adapter->hw;
248 int max_gts = 0;
249 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
250 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
251 struct pci_dev *pdev;
252
253 /* Some devices are not connected over PCIe and thus do not negotiate
254 * speed. These devices do not have valid bus info, and thus any report
255 * we generate may not be correct.
256 */
257 if (hw->bus.type == ixgbe_bus_type_internal)
258 return;
259
260 /* determine whether to use the parent device */
261 if (ixgbe_pcie_from_parent(&adapter->hw))
262 pdev = adapter->pdev->bus->parent->self;
263 else
264 pdev = adapter->pdev;
265
266 if (pcie_get_minimum_link(pdev, &speed, &width) ||
267 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
268 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
269 return;
270 }
271
272 switch (speed) {
273 case PCIE_SPEED_2_5GT:
274 /* 8b/10b encoding reduces max throughput by 20% */
275 max_gts = 2 * width;
276 break;
277 case PCIE_SPEED_5_0GT:
278 /* 8b/10b encoding reduces max throughput by 20% */
279 max_gts = 4 * width;
280 break;
281 case PCIE_SPEED_8_0GT:
282 /* 128b/130b encoding reduces throughput by less than 2% */
283 max_gts = 8 * width;
284 break;
285 default:
286 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
287 return;
288 }
289
290 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
291 max_gts);
292 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
293 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
294 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
295 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
296 "Unknown"),
297 width,
298 (speed == PCIE_SPEED_2_5GT ? "20%" :
299 speed == PCIE_SPEED_5_0GT ? "20%" :
300 speed == PCIE_SPEED_8_0GT ? "<2%" :
301 "Unknown"));
302
303 if (max_gts < expected_gts) {
304 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
305 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
306 expected_gts);
307 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
308 }
309 }
310
311 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
312 {
313 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
314 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
315 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
316 queue_work(ixgbe_wq, &adapter->service_task);
317 }
318
319 static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
320 {
321 struct ixgbe_adapter *adapter = hw->back;
322
323 if (!hw->hw_addr)
324 return;
325 hw->hw_addr = NULL;
326 e_dev_err("Adapter removed\n");
327 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
328 ixgbe_service_event_schedule(adapter);
329 }
330
331 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
332 {
333 u32 value;
334
335 /* The following check not only optimizes a bit by not
336 * performing a read on the status register when the
337 * register just read was a status register read that
338 * returned IXGBE_FAILED_READ_REG. It also blocks any
339 * potential recursion.
340 */
341 if (reg == IXGBE_STATUS) {
342 ixgbe_remove_adapter(hw);
343 return;
344 }
345 value = ixgbe_read_reg(hw, IXGBE_STATUS);
346 if (value == IXGBE_FAILED_READ_REG)
347 ixgbe_remove_adapter(hw);
348 }
349
350 /**
351 * ixgbe_read_reg - Read from device register
352 * @hw: hw specific details
353 * @reg: offset of register to read
354 *
355 * Returns : value read or IXGBE_FAILED_READ_REG if removed
356 *
357 * This function is used to read device registers. It checks for device
358 * removal by confirming any read that returns all ones by checking the
359 * status register value for all ones. This function avoids reading from
360 * the hardware if a removal was previously detected in which case it
361 * returns IXGBE_FAILED_READ_REG (all ones).
362 */
363 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
364 {
365 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
366 u32 value;
367
368 if (ixgbe_removed(reg_addr))
369 return IXGBE_FAILED_READ_REG;
370 value = readl(reg_addr + reg);
371 if (unlikely(value == IXGBE_FAILED_READ_REG))
372 ixgbe_check_remove(hw, reg);
373 return value;
374 }
375
376 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
377 {
378 u16 value;
379
380 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
381 if (value == IXGBE_FAILED_READ_CFG_WORD) {
382 ixgbe_remove_adapter(hw);
383 return true;
384 }
385 return false;
386 }
387
388 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
389 {
390 struct ixgbe_adapter *adapter = hw->back;
391 u16 value;
392
393 if (ixgbe_removed(hw->hw_addr))
394 return IXGBE_FAILED_READ_CFG_WORD;
395 pci_read_config_word(adapter->pdev, reg, &value);
396 if (value == IXGBE_FAILED_READ_CFG_WORD &&
397 ixgbe_check_cfg_remove(hw, adapter->pdev))
398 return IXGBE_FAILED_READ_CFG_WORD;
399 return value;
400 }
401
402 #ifdef CONFIG_PCI_IOV
403 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
404 {
405 struct ixgbe_adapter *adapter = hw->back;
406 u32 value;
407
408 if (ixgbe_removed(hw->hw_addr))
409 return IXGBE_FAILED_READ_CFG_DWORD;
410 pci_read_config_dword(adapter->pdev, reg, &value);
411 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
412 ixgbe_check_cfg_remove(hw, adapter->pdev))
413 return IXGBE_FAILED_READ_CFG_DWORD;
414 return value;
415 }
416 #endif /* CONFIG_PCI_IOV */
417
418 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
419 {
420 struct ixgbe_adapter *adapter = hw->back;
421
422 if (ixgbe_removed(hw->hw_addr))
423 return;
424 pci_write_config_word(adapter->pdev, reg, value);
425 }
426
427 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
428 {
429 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
430
431 /* flush memory to make sure state is correct before next watchdog */
432 smp_mb__before_atomic();
433 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
434 }
435
436 struct ixgbe_reg_info {
437 u32 ofs;
438 char *name;
439 };
440
441 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
442
443 /* General Registers */
444 {IXGBE_CTRL, "CTRL"},
445 {IXGBE_STATUS, "STATUS"},
446 {IXGBE_CTRL_EXT, "CTRL_EXT"},
447
448 /* Interrupt Registers */
449 {IXGBE_EICR, "EICR"},
450
451 /* RX Registers */
452 {IXGBE_SRRCTL(0), "SRRCTL"},
453 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
454 {IXGBE_RDLEN(0), "RDLEN"},
455 {IXGBE_RDH(0), "RDH"},
456 {IXGBE_RDT(0), "RDT"},
457 {IXGBE_RXDCTL(0), "RXDCTL"},
458 {IXGBE_RDBAL(0), "RDBAL"},
459 {IXGBE_RDBAH(0), "RDBAH"},
460
461 /* TX Registers */
462 {IXGBE_TDBAL(0), "TDBAL"},
463 {IXGBE_TDBAH(0), "TDBAH"},
464 {IXGBE_TDLEN(0), "TDLEN"},
465 {IXGBE_TDH(0), "TDH"},
466 {IXGBE_TDT(0), "TDT"},
467 {IXGBE_TXDCTL(0), "TXDCTL"},
468
469 /* List Terminator */
470 { .name = NULL }
471 };
472
473
474 /*
475 * ixgbe_regdump - register printout routine
476 */
477 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
478 {
479 int i = 0, j = 0;
480 char rname[16];
481 u32 regs[64];
482
483 switch (reginfo->ofs) {
484 case IXGBE_SRRCTL(0):
485 for (i = 0; i < 64; i++)
486 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
487 break;
488 case IXGBE_DCA_RXCTRL(0):
489 for (i = 0; i < 64; i++)
490 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
491 break;
492 case IXGBE_RDLEN(0):
493 for (i = 0; i < 64; i++)
494 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
495 break;
496 case IXGBE_RDH(0):
497 for (i = 0; i < 64; i++)
498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
499 break;
500 case IXGBE_RDT(0):
501 for (i = 0; i < 64; i++)
502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
503 break;
504 case IXGBE_RXDCTL(0):
505 for (i = 0; i < 64; i++)
506 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
507 break;
508 case IXGBE_RDBAL(0):
509 for (i = 0; i < 64; i++)
510 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
511 break;
512 case IXGBE_RDBAH(0):
513 for (i = 0; i < 64; i++)
514 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
515 break;
516 case IXGBE_TDBAL(0):
517 for (i = 0; i < 64; i++)
518 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
519 break;
520 case IXGBE_TDBAH(0):
521 for (i = 0; i < 64; i++)
522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
523 break;
524 case IXGBE_TDLEN(0):
525 for (i = 0; i < 64; i++)
526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
527 break;
528 case IXGBE_TDH(0):
529 for (i = 0; i < 64; i++)
530 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
531 break;
532 case IXGBE_TDT(0):
533 for (i = 0; i < 64; i++)
534 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
535 break;
536 case IXGBE_TXDCTL(0):
537 for (i = 0; i < 64; i++)
538 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
539 break;
540 default:
541 pr_info("%-15s %08x\n", reginfo->name,
542 IXGBE_READ_REG(hw, reginfo->ofs));
543 return;
544 }
545
546 for (i = 0; i < 8; i++) {
547 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
548 pr_err("%-15s", rname);
549 for (j = 0; j < 8; j++)
550 pr_cont(" %08x", regs[i*8+j]);
551 pr_cont("\n");
552 }
553
554 }
555
556 /*
557 * ixgbe_dump - Print registers, tx-rings and rx-rings
558 */
559 static void ixgbe_dump(struct ixgbe_adapter *adapter)
560 {
561 struct net_device *netdev = adapter->netdev;
562 struct ixgbe_hw *hw = &adapter->hw;
563 struct ixgbe_reg_info *reginfo;
564 int n = 0;
565 struct ixgbe_ring *tx_ring;
566 struct ixgbe_tx_buffer *tx_buffer;
567 union ixgbe_adv_tx_desc *tx_desc;
568 struct my_u0 { u64 a; u64 b; } *u0;
569 struct ixgbe_ring *rx_ring;
570 union ixgbe_adv_rx_desc *rx_desc;
571 struct ixgbe_rx_buffer *rx_buffer_info;
572 u32 staterr;
573 int i = 0;
574
575 if (!netif_msg_hw(adapter))
576 return;
577
578 /* Print netdevice Info */
579 if (netdev) {
580 dev_info(&adapter->pdev->dev, "Net device Info\n");
581 pr_info("Device Name state "
582 "trans_start last_rx\n");
583 pr_info("%-15s %016lX %016lX %016lX\n",
584 netdev->name,
585 netdev->state,
586 netdev->trans_start,
587 netdev->last_rx);
588 }
589
590 /* Print Registers */
591 dev_info(&adapter->pdev->dev, "Register Dump\n");
592 pr_info(" Register Name Value\n");
593 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
594 reginfo->name; reginfo++) {
595 ixgbe_regdump(hw, reginfo);
596 }
597
598 /* Print TX Ring Summary */
599 if (!netdev || !netif_running(netdev))
600 return;
601
602 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
603 pr_info(" %s %s %s %s\n",
604 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
605 "leng", "ntw", "timestamp");
606 for (n = 0; n < adapter->num_tx_queues; n++) {
607 tx_ring = adapter->tx_ring[n];
608 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
609 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
610 n, tx_ring->next_to_use, tx_ring->next_to_clean,
611 (u64)dma_unmap_addr(tx_buffer, dma),
612 dma_unmap_len(tx_buffer, len),
613 tx_buffer->next_to_watch,
614 (u64)tx_buffer->time_stamp);
615 }
616
617 /* Print TX Rings */
618 if (!netif_msg_tx_done(adapter))
619 goto rx_ring_summary;
620
621 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
622
623 /* Transmit Descriptor Formats
624 *
625 * 82598 Advanced Transmit Descriptor
626 * +--------------------------------------------------------------+
627 * 0 | Buffer Address [63:0] |
628 * +--------------------------------------------------------------+
629 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
630 * +--------------------------------------------------------------+
631 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
632 *
633 * 82598 Advanced Transmit Descriptor (Write-Back Format)
634 * +--------------------------------------------------------------+
635 * 0 | RSV [63:0] |
636 * +--------------------------------------------------------------+
637 * 8 | RSV | STA | NXTSEQ |
638 * +--------------------------------------------------------------+
639 * 63 36 35 32 31 0
640 *
641 * 82599+ Advanced Transmit Descriptor
642 * +--------------------------------------------------------------+
643 * 0 | Buffer Address [63:0] |
644 * +--------------------------------------------------------------+
645 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
646 * +--------------------------------------------------------------+
647 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
648 *
649 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
650 * +--------------------------------------------------------------+
651 * 0 | RSV [63:0] |
652 * +--------------------------------------------------------------+
653 * 8 | RSV | STA | RSV |
654 * +--------------------------------------------------------------+
655 * 63 36 35 32 31 0
656 */
657
658 for (n = 0; n < adapter->num_tx_queues; n++) {
659 tx_ring = adapter->tx_ring[n];
660 pr_info("------------------------------------\n");
661 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
662 pr_info("------------------------------------\n");
663 pr_info("%s%s %s %s %s %s\n",
664 "T [desc] [address 63:0 ] ",
665 "[PlPOIdStDDt Ln] [bi->dma ] ",
666 "leng", "ntw", "timestamp", "bi->skb");
667
668 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
669 tx_desc = IXGBE_TX_DESC(tx_ring, i);
670 tx_buffer = &tx_ring->tx_buffer_info[i];
671 u0 = (struct my_u0 *)tx_desc;
672 if (dma_unmap_len(tx_buffer, len) > 0) {
673 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
674 i,
675 le64_to_cpu(u0->a),
676 le64_to_cpu(u0->b),
677 (u64)dma_unmap_addr(tx_buffer, dma),
678 dma_unmap_len(tx_buffer, len),
679 tx_buffer->next_to_watch,
680 (u64)tx_buffer->time_stamp,
681 tx_buffer->skb);
682 if (i == tx_ring->next_to_use &&
683 i == tx_ring->next_to_clean)
684 pr_cont(" NTC/U\n");
685 else if (i == tx_ring->next_to_use)
686 pr_cont(" NTU\n");
687 else if (i == tx_ring->next_to_clean)
688 pr_cont(" NTC\n");
689 else
690 pr_cont("\n");
691
692 if (netif_msg_pktdata(adapter) &&
693 tx_buffer->skb)
694 print_hex_dump(KERN_INFO, "",
695 DUMP_PREFIX_ADDRESS, 16, 1,
696 tx_buffer->skb->data,
697 dma_unmap_len(tx_buffer, len),
698 true);
699 }
700 }
701 }
702
703 /* Print RX Rings Summary */
704 rx_ring_summary:
705 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
706 pr_info("Queue [NTU] [NTC]\n");
707 for (n = 0; n < adapter->num_rx_queues; n++) {
708 rx_ring = adapter->rx_ring[n];
709 pr_info("%5d %5X %5X\n",
710 n, rx_ring->next_to_use, rx_ring->next_to_clean);
711 }
712
713 /* Print RX Rings */
714 if (!netif_msg_rx_status(adapter))
715 return;
716
717 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
718
719 /* Receive Descriptor Formats
720 *
721 * 82598 Advanced Receive Descriptor (Read) Format
722 * 63 1 0
723 * +-----------------------------------------------------+
724 * 0 | Packet Buffer Address [63:1] |A0/NSE|
725 * +----------------------------------------------+------+
726 * 8 | Header Buffer Address [63:1] | DD |
727 * +-----------------------------------------------------+
728 *
729 *
730 * 82598 Advanced Receive Descriptor (Write-Back) Format
731 *
732 * 63 48 47 32 31 30 21 20 16 15 4 3 0
733 * +------------------------------------------------------+
734 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
735 * | Packet | IP | | | | Type | Type |
736 * | Checksum | Ident | | | | | |
737 * +------------------------------------------------------+
738 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
739 * +------------------------------------------------------+
740 * 63 48 47 32 31 20 19 0
741 *
742 * 82599+ Advanced Receive Descriptor (Read) Format
743 * 63 1 0
744 * +-----------------------------------------------------+
745 * 0 | Packet Buffer Address [63:1] |A0/NSE|
746 * +----------------------------------------------+------+
747 * 8 | Header Buffer Address [63:1] | DD |
748 * +-----------------------------------------------------+
749 *
750 *
751 * 82599+ Advanced Receive Descriptor (Write-Back) Format
752 *
753 * 63 48 47 32 31 30 21 20 17 16 4 3 0
754 * +------------------------------------------------------+
755 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
756 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
757 * |/ Flow Dir Flt ID | | | | | |
758 * +------------------------------------------------------+
759 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
760 * +------------------------------------------------------+
761 * 63 48 47 32 31 20 19 0
762 */
763
764 for (n = 0; n < adapter->num_rx_queues; n++) {
765 rx_ring = adapter->rx_ring[n];
766 pr_info("------------------------------------\n");
767 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
768 pr_info("------------------------------------\n");
769 pr_info("%s%s%s",
770 "R [desc] [ PktBuf A0] ",
771 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
772 "<-- Adv Rx Read format\n");
773 pr_info("%s%s%s",
774 "RWB[desc] [PcsmIpSHl PtRs] ",
775 "[vl er S cks ln] ---------------- [bi->skb ] ",
776 "<-- Adv Rx Write-Back format\n");
777
778 for (i = 0; i < rx_ring->count; i++) {
779 rx_buffer_info = &rx_ring->rx_buffer_info[i];
780 rx_desc = IXGBE_RX_DESC(rx_ring, i);
781 u0 = (struct my_u0 *)rx_desc;
782 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
783 if (staterr & IXGBE_RXD_STAT_DD) {
784 /* Descriptor Done */
785 pr_info("RWB[0x%03X] %016llX "
786 "%016llX ---------------- %p", i,
787 le64_to_cpu(u0->a),
788 le64_to_cpu(u0->b),
789 rx_buffer_info->skb);
790 } else {
791 pr_info("R [0x%03X] %016llX "
792 "%016llX %016llX %p", i,
793 le64_to_cpu(u0->a),
794 le64_to_cpu(u0->b),
795 (u64)rx_buffer_info->dma,
796 rx_buffer_info->skb);
797
798 if (netif_msg_pktdata(adapter) &&
799 rx_buffer_info->dma) {
800 print_hex_dump(KERN_INFO, "",
801 DUMP_PREFIX_ADDRESS, 16, 1,
802 page_address(rx_buffer_info->page) +
803 rx_buffer_info->page_offset,
804 ixgbe_rx_bufsz(rx_ring), true);
805 }
806 }
807
808 if (i == rx_ring->next_to_use)
809 pr_cont(" NTU\n");
810 else if (i == rx_ring->next_to_clean)
811 pr_cont(" NTC\n");
812 else
813 pr_cont("\n");
814
815 }
816 }
817 }
818
819 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
820 {
821 u32 ctrl_ext;
822
823 /* Let firmware take over control of h/w */
824 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
825 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
826 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
827 }
828
829 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
830 {
831 u32 ctrl_ext;
832
833 /* Let firmware know the driver has taken over */
834 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
835 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
836 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
837 }
838
839 /**
840 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
841 * @adapter: pointer to adapter struct
842 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
843 * @queue: queue to map the corresponding interrupt to
844 * @msix_vector: the vector to map to the corresponding queue
845 *
846 */
847 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
848 u8 queue, u8 msix_vector)
849 {
850 u32 ivar, index;
851 struct ixgbe_hw *hw = &adapter->hw;
852 switch (hw->mac.type) {
853 case ixgbe_mac_82598EB:
854 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
855 if (direction == -1)
856 direction = 0;
857 index = (((direction * 64) + queue) >> 2) & 0x1F;
858 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
859 ivar &= ~(0xFF << (8 * (queue & 0x3)));
860 ivar |= (msix_vector << (8 * (queue & 0x3)));
861 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
862 break;
863 case ixgbe_mac_82599EB:
864 case ixgbe_mac_X540:
865 case ixgbe_mac_X550:
866 case ixgbe_mac_X550EM_x:
867 case ixgbe_mac_x550em_a:
868 if (direction == -1) {
869 /* other causes */
870 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
871 index = ((queue & 1) * 8);
872 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
873 ivar &= ~(0xFF << index);
874 ivar |= (msix_vector << index);
875 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
876 break;
877 } else {
878 /* tx or rx causes */
879 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
880 index = ((16 * (queue & 1)) + (8 * direction));
881 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
882 ivar &= ~(0xFF << index);
883 ivar |= (msix_vector << index);
884 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
885 break;
886 }
887 default:
888 break;
889 }
890 }
891
892 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
893 u64 qmask)
894 {
895 u32 mask;
896
897 switch (adapter->hw.mac.type) {
898 case ixgbe_mac_82598EB:
899 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
900 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
901 break;
902 case ixgbe_mac_82599EB:
903 case ixgbe_mac_X540:
904 case ixgbe_mac_X550:
905 case ixgbe_mac_X550EM_x:
906 case ixgbe_mac_x550em_a:
907 mask = (qmask & 0xFFFFFFFF);
908 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
909 mask = (qmask >> 32);
910 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
911 break;
912 default:
913 break;
914 }
915 }
916
917 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
918 struct ixgbe_tx_buffer *tx_buffer)
919 {
920 if (tx_buffer->skb) {
921 dev_kfree_skb_any(tx_buffer->skb);
922 if (dma_unmap_len(tx_buffer, len))
923 dma_unmap_single(ring->dev,
924 dma_unmap_addr(tx_buffer, dma),
925 dma_unmap_len(tx_buffer, len),
926 DMA_TO_DEVICE);
927 } else if (dma_unmap_len(tx_buffer, len)) {
928 dma_unmap_page(ring->dev,
929 dma_unmap_addr(tx_buffer, dma),
930 dma_unmap_len(tx_buffer, len),
931 DMA_TO_DEVICE);
932 }
933 tx_buffer->next_to_watch = NULL;
934 tx_buffer->skb = NULL;
935 dma_unmap_len_set(tx_buffer, len, 0);
936 /* tx_buffer must be completely set up in the transmit path */
937 }
938
939 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
940 {
941 struct ixgbe_hw *hw = &adapter->hw;
942 struct ixgbe_hw_stats *hwstats = &adapter->stats;
943 int i;
944 u32 data;
945
946 if ((hw->fc.current_mode != ixgbe_fc_full) &&
947 (hw->fc.current_mode != ixgbe_fc_rx_pause))
948 return;
949
950 switch (hw->mac.type) {
951 case ixgbe_mac_82598EB:
952 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
953 break;
954 default:
955 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
956 }
957 hwstats->lxoffrxc += data;
958
959 /* refill credits (no tx hang) if we received xoff */
960 if (!data)
961 return;
962
963 for (i = 0; i < adapter->num_tx_queues; i++)
964 clear_bit(__IXGBE_HANG_CHECK_ARMED,
965 &adapter->tx_ring[i]->state);
966 }
967
968 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
969 {
970 struct ixgbe_hw *hw = &adapter->hw;
971 struct ixgbe_hw_stats *hwstats = &adapter->stats;
972 u32 xoff[8] = {0};
973 u8 tc;
974 int i;
975 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
976
977 if (adapter->ixgbe_ieee_pfc)
978 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
979
980 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
981 ixgbe_update_xoff_rx_lfc(adapter);
982 return;
983 }
984
985 /* update stats for each tc, only valid with PFC enabled */
986 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
987 u32 pxoffrxc;
988
989 switch (hw->mac.type) {
990 case ixgbe_mac_82598EB:
991 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
992 break;
993 default:
994 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
995 }
996 hwstats->pxoffrxc[i] += pxoffrxc;
997 /* Get the TC for given UP */
998 tc = netdev_get_prio_tc_map(adapter->netdev, i);
999 xoff[tc] += pxoffrxc;
1000 }
1001
1002 /* disarm tx queues that have received xoff frames */
1003 for (i = 0; i < adapter->num_tx_queues; i++) {
1004 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
1005
1006 tc = tx_ring->dcb_tc;
1007 if (xoff[tc])
1008 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1009 }
1010 }
1011
1012 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
1013 {
1014 return ring->stats.packets;
1015 }
1016
1017 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1018 {
1019 struct ixgbe_adapter *adapter;
1020 struct ixgbe_hw *hw;
1021 u32 head, tail;
1022
1023 if (ring->l2_accel_priv)
1024 adapter = ring->l2_accel_priv->real_adapter;
1025 else
1026 adapter = netdev_priv(ring->netdev);
1027
1028 hw = &adapter->hw;
1029 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1030 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
1031
1032 if (head != tail)
1033 return (head < tail) ?
1034 tail - head : (tail + ring->count - head);
1035
1036 return 0;
1037 }
1038
1039 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1040 {
1041 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1042 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1043 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1044
1045 clear_check_for_tx_hang(tx_ring);
1046
1047 /*
1048 * Check for a hung queue, but be thorough. This verifies
1049 * that a transmit has been completed since the previous
1050 * check AND there is at least one packet pending. The
1051 * ARMED bit is set to indicate a potential hang. The
1052 * bit is cleared if a pause frame is received to remove
1053 * false hang detection due to PFC or 802.3x frames. By
1054 * requiring this to fail twice we avoid races with
1055 * pfc clearing the ARMED bit and conditions where we
1056 * run the check_tx_hang logic with a transmit completion
1057 * pending but without time to complete it yet.
1058 */
1059 if (tx_done_old == tx_done && tx_pending)
1060 /* make sure it is true for two checks in a row */
1061 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1062 &tx_ring->state);
1063 /* update completed stats and continue */
1064 tx_ring->tx_stats.tx_done_old = tx_done;
1065 /* reset the countdown */
1066 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1067
1068 return false;
1069 }
1070
1071 /**
1072 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1073 * @adapter: driver private struct
1074 **/
1075 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1076 {
1077
1078 /* Do the reset outside of interrupt context */
1079 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1080 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
1081 e_warn(drv, "initiating reset due to tx timeout\n");
1082 ixgbe_service_event_schedule(adapter);
1083 }
1084 }
1085
1086 /**
1087 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate
1088 **/
1089 static int ixgbe_tx_maxrate(struct net_device *netdev,
1090 int queue_index, u32 maxrate)
1091 {
1092 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1093 struct ixgbe_hw *hw = &adapter->hw;
1094 u32 bcnrc_val = ixgbe_link_mbps(adapter);
1095
1096 if (!maxrate)
1097 return 0;
1098
1099 /* Calculate the rate factor values to set */
1100 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT;
1101 bcnrc_val /= maxrate;
1102
1103 /* clear everything but the rate factor */
1104 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK |
1105 IXGBE_RTTBCNRC_RF_DEC_MASK;
1106
1107 /* enable the rate scheduler */
1108 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA;
1109
1110 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index);
1111 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
1112
1113 return 0;
1114 }
1115
1116 /**
1117 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
1118 * @q_vector: structure containing interrupt and ring information
1119 * @tx_ring: tx ring to clean
1120 * @napi_budget: Used to determine if we are in netpoll
1121 **/
1122 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
1123 struct ixgbe_ring *tx_ring, int napi_budget)
1124 {
1125 struct ixgbe_adapter *adapter = q_vector->adapter;
1126 struct ixgbe_tx_buffer *tx_buffer;
1127 union ixgbe_adv_tx_desc *tx_desc;
1128 unsigned int total_bytes = 0, total_packets = 0;
1129 unsigned int budget = q_vector->tx.work_limit;
1130 unsigned int i = tx_ring->next_to_clean;
1131
1132 if (test_bit(__IXGBE_DOWN, &adapter->state))
1133 return true;
1134
1135 tx_buffer = &tx_ring->tx_buffer_info[i];
1136 tx_desc = IXGBE_TX_DESC(tx_ring, i);
1137 i -= tx_ring->count;
1138
1139 do {
1140 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1141
1142 /* if next_to_watch is not set then there is no work pending */
1143 if (!eop_desc)
1144 break;
1145
1146 /* prevent any other reads prior to eop_desc */
1147 read_barrier_depends();
1148
1149 /* if DD is not set pending work has not been completed */
1150 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1151 break;
1152
1153 /* clear next_to_watch to prevent false hangs */
1154 tx_buffer->next_to_watch = NULL;
1155
1156 /* update the statistics for this packet */
1157 total_bytes += tx_buffer->bytecount;
1158 total_packets += tx_buffer->gso_segs;
1159
1160 /* free the skb */
1161 napi_consume_skb(tx_buffer->skb, napi_budget);
1162
1163 /* unmap skb header data */
1164 dma_unmap_single(tx_ring->dev,
1165 dma_unmap_addr(tx_buffer, dma),
1166 dma_unmap_len(tx_buffer, len),
1167 DMA_TO_DEVICE);
1168
1169 /* clear tx_buffer data */
1170 tx_buffer->skb = NULL;
1171 dma_unmap_len_set(tx_buffer, len, 0);
1172
1173 /* unmap remaining buffers */
1174 while (tx_desc != eop_desc) {
1175 tx_buffer++;
1176 tx_desc++;
1177 i++;
1178 if (unlikely(!i)) {
1179 i -= tx_ring->count;
1180 tx_buffer = tx_ring->tx_buffer_info;
1181 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1182 }
1183
1184 /* unmap any remaining paged data */
1185 if (dma_unmap_len(tx_buffer, len)) {
1186 dma_unmap_page(tx_ring->dev,
1187 dma_unmap_addr(tx_buffer, dma),
1188 dma_unmap_len(tx_buffer, len),
1189 DMA_TO_DEVICE);
1190 dma_unmap_len_set(tx_buffer, len, 0);
1191 }
1192 }
1193
1194 /* move us one more past the eop_desc for start of next pkt */
1195 tx_buffer++;
1196 tx_desc++;
1197 i++;
1198 if (unlikely(!i)) {
1199 i -= tx_ring->count;
1200 tx_buffer = tx_ring->tx_buffer_info;
1201 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1202 }
1203
1204 /* issue prefetch for next Tx descriptor */
1205 prefetch(tx_desc);
1206
1207 /* update budget accounting */
1208 budget--;
1209 } while (likely(budget));
1210
1211 i += tx_ring->count;
1212 tx_ring->next_to_clean = i;
1213 u64_stats_update_begin(&tx_ring->syncp);
1214 tx_ring->stats.bytes += total_bytes;
1215 tx_ring->stats.packets += total_packets;
1216 u64_stats_update_end(&tx_ring->syncp);
1217 q_vector->tx.total_bytes += total_bytes;
1218 q_vector->tx.total_packets += total_packets;
1219
1220 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1221 /* schedule immediate reset if we believe we hung */
1222 struct ixgbe_hw *hw = &adapter->hw;
1223 e_err(drv, "Detected Tx Unit Hang\n"
1224 " Tx Queue <%d>\n"
1225 " TDH, TDT <%x>, <%x>\n"
1226 " next_to_use <%x>\n"
1227 " next_to_clean <%x>\n"
1228 "tx_buffer_info[next_to_clean]\n"
1229 " time_stamp <%lx>\n"
1230 " jiffies <%lx>\n",
1231 tx_ring->queue_index,
1232 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1233 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1234 tx_ring->next_to_use, i,
1235 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1236
1237 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1238
1239 e_info(probe,
1240 "tx hang %d detected on queue %d, resetting adapter\n",
1241 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1242
1243 /* schedule immediate reset if we believe we hung */
1244 ixgbe_tx_timeout_reset(adapter);
1245
1246 /* the adapter is about to reset, no point in enabling stuff */
1247 return true;
1248 }
1249
1250 netdev_tx_completed_queue(txring_txq(tx_ring),
1251 total_packets, total_bytes);
1252
1253 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1254 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1255 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1256 /* Make sure that anybody stopping the queue after this
1257 * sees the new next_to_clean.
1258 */
1259 smp_mb();
1260 if (__netif_subqueue_stopped(tx_ring->netdev,
1261 tx_ring->queue_index)
1262 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1263 netif_wake_subqueue(tx_ring->netdev,
1264 tx_ring->queue_index);
1265 ++tx_ring->tx_stats.restart_queue;
1266 }
1267 }
1268
1269 return !!budget;
1270 }
1271
1272 #ifdef CONFIG_IXGBE_DCA
1273 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1274 struct ixgbe_ring *tx_ring,
1275 int cpu)
1276 {
1277 struct ixgbe_hw *hw = &adapter->hw;
1278 u32 txctrl = 0;
1279 u16 reg_offset;
1280
1281 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1282 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1283
1284 switch (hw->mac.type) {
1285 case ixgbe_mac_82598EB:
1286 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1287 break;
1288 case ixgbe_mac_82599EB:
1289 case ixgbe_mac_X540:
1290 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1291 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1292 break;
1293 default:
1294 /* for unknown hardware do not write register */
1295 return;
1296 }
1297
1298 /*
1299 * We can enable relaxed ordering for reads, but not writes when
1300 * DCA is enabled. This is due to a known issue in some chipsets
1301 * which will cause the DCA tag to be cleared.
1302 */
1303 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1304 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1305 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1306
1307 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1308 }
1309
1310 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1311 struct ixgbe_ring *rx_ring,
1312 int cpu)
1313 {
1314 struct ixgbe_hw *hw = &adapter->hw;
1315 u32 rxctrl = 0;
1316 u8 reg_idx = rx_ring->reg_idx;
1317
1318 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1319 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1320
1321 switch (hw->mac.type) {
1322 case ixgbe_mac_82599EB:
1323 case ixgbe_mac_X540:
1324 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1325 break;
1326 default:
1327 break;
1328 }
1329
1330 /*
1331 * We can enable relaxed ordering for reads, but not writes when
1332 * DCA is enabled. This is due to a known issue in some chipsets
1333 * which will cause the DCA tag to be cleared.
1334 */
1335 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1336 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
1337 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1338
1339 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1340 }
1341
1342 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1343 {
1344 struct ixgbe_adapter *adapter = q_vector->adapter;
1345 struct ixgbe_ring *ring;
1346 int cpu = get_cpu();
1347
1348 if (q_vector->cpu == cpu)
1349 goto out_no_update;
1350
1351 ixgbe_for_each_ring(ring, q_vector->tx)
1352 ixgbe_update_tx_dca(adapter, ring, cpu);
1353
1354 ixgbe_for_each_ring(ring, q_vector->rx)
1355 ixgbe_update_rx_dca(adapter, ring, cpu);
1356
1357 q_vector->cpu = cpu;
1358 out_no_update:
1359 put_cpu();
1360 }
1361
1362 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1363 {
1364 int i;
1365
1366 /* always use CB2 mode, difference is masked in the CB driver */
1367 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1368 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1369 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1370 else
1371 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1372 IXGBE_DCA_CTRL_DCA_DISABLE);
1373
1374 for (i = 0; i < adapter->num_q_vectors; i++) {
1375 adapter->q_vector[i]->cpu = -1;
1376 ixgbe_update_dca(adapter->q_vector[i]);
1377 }
1378 }
1379
1380 static int __ixgbe_notify_dca(struct device *dev, void *data)
1381 {
1382 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1383 unsigned long event = *(unsigned long *)data;
1384
1385 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1386 return 0;
1387
1388 switch (event) {
1389 case DCA_PROVIDER_ADD:
1390 /* if we're already enabled, don't do it again */
1391 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1392 break;
1393 if (dca_add_requester(dev) == 0) {
1394 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1395 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1396 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1397 break;
1398 }
1399 /* Fall Through since DCA is disabled. */
1400 case DCA_PROVIDER_REMOVE:
1401 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1402 dca_remove_requester(dev);
1403 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1404 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1405 IXGBE_DCA_CTRL_DCA_DISABLE);
1406 }
1407 break;
1408 }
1409
1410 return 0;
1411 }
1412
1413 #endif /* CONFIG_IXGBE_DCA */
1414
1415 #define IXGBE_RSS_L4_TYPES_MASK \
1416 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1417 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1418 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1419 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1420
1421 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1422 union ixgbe_adv_rx_desc *rx_desc,
1423 struct sk_buff *skb)
1424 {
1425 u16 rss_type;
1426
1427 if (!(ring->netdev->features & NETIF_F_RXHASH))
1428 return;
1429
1430 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1431 IXGBE_RXDADV_RSSTYPE_MASK;
1432
1433 if (!rss_type)
1434 return;
1435
1436 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1437 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1438 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
1439 }
1440
1441 #ifdef IXGBE_FCOE
1442 /**
1443 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1444 * @ring: structure containing ring specific data
1445 * @rx_desc: advanced rx descriptor
1446 *
1447 * Returns : true if it is FCoE pkt
1448 */
1449 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1450 union ixgbe_adv_rx_desc *rx_desc)
1451 {
1452 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1453
1454 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1455 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1456 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1457 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1458 }
1459
1460 #endif /* IXGBE_FCOE */
1461 /**
1462 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1463 * @ring: structure containing ring specific data
1464 * @rx_desc: current Rx descriptor being processed
1465 * @skb: skb currently being received and modified
1466 **/
1467 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1468 union ixgbe_adv_rx_desc *rx_desc,
1469 struct sk_buff *skb)
1470 {
1471 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1472 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1473 bool encap_pkt = false;
1474
1475 skb_checksum_none_assert(skb);
1476
1477 /* Rx csum disabled */
1478 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1479 return;
1480
1481 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1482 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1483 encap_pkt = true;
1484 skb->encapsulation = 1;
1485 }
1486
1487 /* if IP and error */
1488 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1489 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1490 ring->rx_stats.csum_err++;
1491 return;
1492 }
1493
1494 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1495 return;
1496
1497 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1498 /*
1499 * 82599 errata, UDP frames with a 0 checksum can be marked as
1500 * checksum errors.
1501 */
1502 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1503 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1504 return;
1505
1506 ring->rx_stats.csum_err++;
1507 return;
1508 }
1509
1510 /* It must be a TCP or UDP packet with a valid checksum */
1511 skb->ip_summed = CHECKSUM_UNNECESSARY;
1512 if (encap_pkt) {
1513 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1514 return;
1515
1516 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1517 skb->ip_summed = CHECKSUM_NONE;
1518 return;
1519 }
1520 /* If we checked the outer header let the stack know */
1521 skb->csum_level = 1;
1522 }
1523 }
1524
1525 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1526 struct ixgbe_rx_buffer *bi)
1527 {
1528 struct page *page = bi->page;
1529 dma_addr_t dma;
1530
1531 /* since we are recycling buffers we should seldom need to alloc */
1532 if (likely(page))
1533 return true;
1534
1535 /* alloc new page for storage */
1536 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1537 if (unlikely(!page)) {
1538 rx_ring->rx_stats.alloc_rx_page_failed++;
1539 return false;
1540 }
1541
1542 /* map page for use */
1543 dma = dma_map_page(rx_ring->dev, page, 0,
1544 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1545
1546 /*
1547 * if mapping failed free memory back to system since
1548 * there isn't much point in holding memory we can't use
1549 */
1550 if (dma_mapping_error(rx_ring->dev, dma)) {
1551 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1552
1553 rx_ring->rx_stats.alloc_rx_page_failed++;
1554 return false;
1555 }
1556
1557 bi->dma = dma;
1558 bi->page = page;
1559 bi->page_offset = 0;
1560
1561 return true;
1562 }
1563
1564 /**
1565 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1566 * @rx_ring: ring to place buffers on
1567 * @cleaned_count: number of buffers to replace
1568 **/
1569 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1570 {
1571 union ixgbe_adv_rx_desc *rx_desc;
1572 struct ixgbe_rx_buffer *bi;
1573 u16 i = rx_ring->next_to_use;
1574
1575 /* nothing to do */
1576 if (!cleaned_count)
1577 return;
1578
1579 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1580 bi = &rx_ring->rx_buffer_info[i];
1581 i -= rx_ring->count;
1582
1583 do {
1584 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1585 break;
1586
1587 /*
1588 * Refresh the desc even if buffer_addrs didn't change
1589 * because each write-back erases this info.
1590 */
1591 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1592
1593 rx_desc++;
1594 bi++;
1595 i++;
1596 if (unlikely(!i)) {
1597 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1598 bi = rx_ring->rx_buffer_info;
1599 i -= rx_ring->count;
1600 }
1601
1602 /* clear the status bits for the next_to_use descriptor */
1603 rx_desc->wb.upper.status_error = 0;
1604
1605 cleaned_count--;
1606 } while (cleaned_count);
1607
1608 i += rx_ring->count;
1609
1610 if (rx_ring->next_to_use != i) {
1611 rx_ring->next_to_use = i;
1612
1613 /* update next to alloc since we have filled the ring */
1614 rx_ring->next_to_alloc = i;
1615
1616 /* Force memory writes to complete before letting h/w
1617 * know there are new descriptors to fetch. (Only
1618 * applicable for weak-ordered memory model archs,
1619 * such as IA-64).
1620 */
1621 wmb();
1622 writel(i, rx_ring->tail);
1623 }
1624 }
1625
1626 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1627 struct sk_buff *skb)
1628 {
1629 u16 hdr_len = skb_headlen(skb);
1630
1631 /* set gso_size to avoid messing up TCP MSS */
1632 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1633 IXGBE_CB(skb)->append_cnt);
1634 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1635 }
1636
1637 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1638 struct sk_buff *skb)
1639 {
1640 /* if append_cnt is 0 then frame is not RSC */
1641 if (!IXGBE_CB(skb)->append_cnt)
1642 return;
1643
1644 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1645 rx_ring->rx_stats.rsc_flush++;
1646
1647 ixgbe_set_rsc_gso_size(rx_ring, skb);
1648
1649 /* gso_size is computed using append_cnt so always clear it last */
1650 IXGBE_CB(skb)->append_cnt = 0;
1651 }
1652
1653 /**
1654 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1655 * @rx_ring: rx descriptor ring packet is being transacted on
1656 * @rx_desc: pointer to the EOP Rx descriptor
1657 * @skb: pointer to current skb being populated
1658 *
1659 * This function checks the ring, descriptor, and packet information in
1660 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1661 * other fields within the skb.
1662 **/
1663 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1664 union ixgbe_adv_rx_desc *rx_desc,
1665 struct sk_buff *skb)
1666 {
1667 struct net_device *dev = rx_ring->netdev;
1668 u32 flags = rx_ring->q_vector->adapter->flags;
1669
1670 ixgbe_update_rsc_stats(rx_ring, skb);
1671
1672 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1673
1674 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1675
1676 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED))
1677 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1678
1679 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1680 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1681 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1682 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1683 }
1684
1685 skb_record_rx_queue(skb, rx_ring->queue_index);
1686
1687 skb->protocol = eth_type_trans(skb, dev);
1688 }
1689
1690 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1691 struct sk_buff *skb)
1692 {
1693 skb_mark_napi_id(skb, &q_vector->napi);
1694 if (ixgbe_qv_busy_polling(q_vector))
1695 netif_receive_skb(skb);
1696 else
1697 napi_gro_receive(&q_vector->napi, skb);
1698 }
1699
1700 /**
1701 * ixgbe_is_non_eop - process handling of non-EOP buffers
1702 * @rx_ring: Rx ring being processed
1703 * @rx_desc: Rx descriptor for current buffer
1704 * @skb: Current socket buffer containing buffer in progress
1705 *
1706 * This function updates next to clean. If the buffer is an EOP buffer
1707 * this function exits returning false, otherwise it will place the
1708 * sk_buff in the next buffer to be chained and return true indicating
1709 * that this is in fact a non-EOP buffer.
1710 **/
1711 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1712 union ixgbe_adv_rx_desc *rx_desc,
1713 struct sk_buff *skb)
1714 {
1715 u32 ntc = rx_ring->next_to_clean + 1;
1716
1717 /* fetch, update, and store next to clean */
1718 ntc = (ntc < rx_ring->count) ? ntc : 0;
1719 rx_ring->next_to_clean = ntc;
1720
1721 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1722
1723 /* update RSC append count if present */
1724 if (ring_is_rsc_enabled(rx_ring)) {
1725 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1726 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1727
1728 if (unlikely(rsc_enabled)) {
1729 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1730
1731 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1732 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1733
1734 /* update ntc based on RSC value */
1735 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1736 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1737 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1738 }
1739 }
1740
1741 /* if we are the last buffer then there is nothing else to do */
1742 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1743 return false;
1744
1745 /* place skb in next buffer to be received */
1746 rx_ring->rx_buffer_info[ntc].skb = skb;
1747 rx_ring->rx_stats.non_eop_descs++;
1748
1749 return true;
1750 }
1751
1752 /**
1753 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1754 * @rx_ring: rx descriptor ring packet is being transacted on
1755 * @skb: pointer to current skb being adjusted
1756 *
1757 * This function is an ixgbe specific version of __pskb_pull_tail. The
1758 * main difference between this version and the original function is that
1759 * this function can make several assumptions about the state of things
1760 * that allow for significant optimizations versus the standard function.
1761 * As a result we can do things like drop a frag and maintain an accurate
1762 * truesize for the skb.
1763 */
1764 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1765 struct sk_buff *skb)
1766 {
1767 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1768 unsigned char *va;
1769 unsigned int pull_len;
1770
1771 /*
1772 * it is valid to use page_address instead of kmap since we are
1773 * working with pages allocated out of the lomem pool per
1774 * alloc_page(GFP_ATOMIC)
1775 */
1776 va = skb_frag_address(frag);
1777
1778 /*
1779 * we need the header to contain the greater of either ETH_HLEN or
1780 * 60 bytes if the skb->len is less than 60 for skb_pad.
1781 */
1782 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
1783
1784 /* align pull length to size of long to optimize memcpy performance */
1785 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1786
1787 /* update all of the pointers */
1788 skb_frag_size_sub(frag, pull_len);
1789 frag->page_offset += pull_len;
1790 skb->data_len -= pull_len;
1791 skb->tail += pull_len;
1792 }
1793
1794 /**
1795 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1796 * @rx_ring: rx descriptor ring packet is being transacted on
1797 * @skb: pointer to current skb being updated
1798 *
1799 * This function provides a basic DMA sync up for the first fragment of an
1800 * skb. The reason for doing this is that the first fragment cannot be
1801 * unmapped until we have reached the end of packet descriptor for a buffer
1802 * chain.
1803 */
1804 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1805 struct sk_buff *skb)
1806 {
1807 /* if the page was released unmap it, else just sync our portion */
1808 if (unlikely(IXGBE_CB(skb)->page_released)) {
1809 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1810 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1811 IXGBE_CB(skb)->page_released = false;
1812 } else {
1813 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1814
1815 dma_sync_single_range_for_cpu(rx_ring->dev,
1816 IXGBE_CB(skb)->dma,
1817 frag->page_offset,
1818 ixgbe_rx_bufsz(rx_ring),
1819 DMA_FROM_DEVICE);
1820 }
1821 IXGBE_CB(skb)->dma = 0;
1822 }
1823
1824 /**
1825 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1826 * @rx_ring: rx descriptor ring packet is being transacted on
1827 * @rx_desc: pointer to the EOP Rx descriptor
1828 * @skb: pointer to current skb being fixed
1829 *
1830 * Check for corrupted packet headers caused by senders on the local L2
1831 * embedded NIC switch not setting up their Tx Descriptors right. These
1832 * should be very rare.
1833 *
1834 * Also address the case where we are pulling data in on pages only
1835 * and as such no data is present in the skb header.
1836 *
1837 * In addition if skb is not at least 60 bytes we need to pad it so that
1838 * it is large enough to qualify as a valid Ethernet frame.
1839 *
1840 * Returns true if an error was encountered and skb was freed.
1841 **/
1842 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1843 union ixgbe_adv_rx_desc *rx_desc,
1844 struct sk_buff *skb)
1845 {
1846 struct net_device *netdev = rx_ring->netdev;
1847
1848 /* verify that the packet does not have any known errors */
1849 if (unlikely(ixgbe_test_staterr(rx_desc,
1850 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1851 !(netdev->features & NETIF_F_RXALL))) {
1852 dev_kfree_skb_any(skb);
1853 return true;
1854 }
1855
1856 /* place header in linear portion of buffer */
1857 if (skb_is_nonlinear(skb))
1858 ixgbe_pull_tail(rx_ring, skb);
1859
1860 #ifdef IXGBE_FCOE
1861 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1862 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1863 return false;
1864
1865 #endif
1866 /* if eth_skb_pad returns an error the skb was freed */
1867 if (eth_skb_pad(skb))
1868 return true;
1869
1870 return false;
1871 }
1872
1873 /**
1874 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1875 * @rx_ring: rx descriptor ring to store buffers on
1876 * @old_buff: donor buffer to have page reused
1877 *
1878 * Synchronizes page for reuse by the adapter
1879 **/
1880 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1881 struct ixgbe_rx_buffer *old_buff)
1882 {
1883 struct ixgbe_rx_buffer *new_buff;
1884 u16 nta = rx_ring->next_to_alloc;
1885
1886 new_buff = &rx_ring->rx_buffer_info[nta];
1887
1888 /* update, and store next to alloc */
1889 nta++;
1890 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1891
1892 /* transfer page from old buffer to new buffer */
1893 *new_buff = *old_buff;
1894
1895 /* sync the buffer for use by the device */
1896 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1897 new_buff->page_offset,
1898 ixgbe_rx_bufsz(rx_ring),
1899 DMA_FROM_DEVICE);
1900 }
1901
1902 static inline bool ixgbe_page_is_reserved(struct page *page)
1903 {
1904 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
1905 }
1906
1907 /**
1908 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1909 * @rx_ring: rx descriptor ring to transact packets on
1910 * @rx_buffer: buffer containing page to add
1911 * @rx_desc: descriptor containing length of buffer written by hardware
1912 * @skb: sk_buff to place the data into
1913 *
1914 * This function will add the data contained in rx_buffer->page to the skb.
1915 * This is done either through a direct copy if the data in the buffer is
1916 * less than the skb header size, otherwise it will just attach the page as
1917 * a frag to the skb.
1918 *
1919 * The function will then update the page offset if necessary and return
1920 * true if the buffer can be reused by the adapter.
1921 **/
1922 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1923 struct ixgbe_rx_buffer *rx_buffer,
1924 union ixgbe_adv_rx_desc *rx_desc,
1925 struct sk_buff *skb)
1926 {
1927 struct page *page = rx_buffer->page;
1928 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1929 #if (PAGE_SIZE < 8192)
1930 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1931 #else
1932 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1933 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1934 ixgbe_rx_bufsz(rx_ring);
1935 #endif
1936
1937 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1938 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1939
1940 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1941
1942 /* page is not reserved, we can reuse buffer as-is */
1943 if (likely(!ixgbe_page_is_reserved(page)))
1944 return true;
1945
1946 /* this page cannot be reused so discard it */
1947 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1948 return false;
1949 }
1950
1951 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1952 rx_buffer->page_offset, size, truesize);
1953
1954 /* avoid re-using remote pages */
1955 if (unlikely(ixgbe_page_is_reserved(page)))
1956 return false;
1957
1958 #if (PAGE_SIZE < 8192)
1959 /* if we are only owner of page we can reuse it */
1960 if (unlikely(page_count(page) != 1))
1961 return false;
1962
1963 /* flip page offset to other buffer */
1964 rx_buffer->page_offset ^= truesize;
1965 #else
1966 /* move offset up to the next cache line */
1967 rx_buffer->page_offset += truesize;
1968
1969 if (rx_buffer->page_offset > last_offset)
1970 return false;
1971 #endif
1972
1973 /* Even if we own the page, we are not allowed to use atomic_set()
1974 * This would break get_page_unless_zero() users.
1975 */
1976 page_ref_inc(page);
1977
1978 return true;
1979 }
1980
1981 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1982 union ixgbe_adv_rx_desc *rx_desc)
1983 {
1984 struct ixgbe_rx_buffer *rx_buffer;
1985 struct sk_buff *skb;
1986 struct page *page;
1987
1988 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1989 page = rx_buffer->page;
1990 prefetchw(page);
1991
1992 skb = rx_buffer->skb;
1993
1994 if (likely(!skb)) {
1995 void *page_addr = page_address(page) +
1996 rx_buffer->page_offset;
1997
1998 /* prefetch first cache line of first page */
1999 prefetch(page_addr);
2000 #if L1_CACHE_BYTES < 128
2001 prefetch(page_addr + L1_CACHE_BYTES);
2002 #endif
2003
2004 /* allocate a skb to store the frags */
2005 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
2006 IXGBE_RX_HDR_SIZE);
2007 if (unlikely(!skb)) {
2008 rx_ring->rx_stats.alloc_rx_buff_failed++;
2009 return NULL;
2010 }
2011
2012 /*
2013 * we will be copying header into skb->data in
2014 * pskb_may_pull so it is in our interest to prefetch
2015 * it now to avoid a possible cache miss
2016 */
2017 prefetchw(skb->data);
2018
2019 /*
2020 * Delay unmapping of the first packet. It carries the
2021 * header information, HW may still access the header
2022 * after the writeback. Only unmap it when EOP is
2023 * reached
2024 */
2025 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
2026 goto dma_sync;
2027
2028 IXGBE_CB(skb)->dma = rx_buffer->dma;
2029 } else {
2030 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2031 ixgbe_dma_sync_frag(rx_ring, skb);
2032
2033 dma_sync:
2034 /* we are reusing so sync this buffer for CPU use */
2035 dma_sync_single_range_for_cpu(rx_ring->dev,
2036 rx_buffer->dma,
2037 rx_buffer->page_offset,
2038 ixgbe_rx_bufsz(rx_ring),
2039 DMA_FROM_DEVICE);
2040
2041 rx_buffer->skb = NULL;
2042 }
2043
2044 /* pull page into skb */
2045 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2046 /* hand second half of page back to the ring */
2047 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2048 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2049 /* the page has been released from the ring */
2050 IXGBE_CB(skb)->page_released = true;
2051 } else {
2052 /* we are not reusing the buffer so unmap it */
2053 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2054 ixgbe_rx_pg_size(rx_ring),
2055 DMA_FROM_DEVICE);
2056 }
2057
2058 /* clear contents of buffer_info */
2059 rx_buffer->page = NULL;
2060
2061 return skb;
2062 }
2063
2064 /**
2065 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2066 * @q_vector: structure containing interrupt and ring information
2067 * @rx_ring: rx descriptor ring to transact packets on
2068 * @budget: Total limit on number of packets to process
2069 *
2070 * This function provides a "bounce buffer" approach to Rx interrupt
2071 * processing. The advantage to this is that on systems that have
2072 * expensive overhead for IOMMU access this provides a means of avoiding
2073 * it by maintaining the mapping of the page to the syste.
2074 *
2075 * Returns amount of work completed
2076 **/
2077 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
2078 struct ixgbe_ring *rx_ring,
2079 const int budget)
2080 {
2081 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2082 #ifdef IXGBE_FCOE
2083 struct ixgbe_adapter *adapter = q_vector->adapter;
2084 int ddp_bytes;
2085 unsigned int mss = 0;
2086 #endif /* IXGBE_FCOE */
2087 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
2088
2089 while (likely(total_rx_packets < budget)) {
2090 union ixgbe_adv_rx_desc *rx_desc;
2091 struct sk_buff *skb;
2092
2093 /* return some buffers to hardware, one at a time is too slow */
2094 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2095 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2096 cleaned_count = 0;
2097 }
2098
2099 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2100
2101 if (!rx_desc->wb.upper.status_error)
2102 break;
2103
2104 /* This memory barrier is needed to keep us from reading
2105 * any other fields out of the rx_desc until we know the
2106 * descriptor has been written back
2107 */
2108 dma_rmb();
2109
2110 /* retrieve a buffer from the ring */
2111 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
2112
2113 /* exit if we failed to retrieve a buffer */
2114 if (!skb)
2115 break;
2116
2117 cleaned_count++;
2118
2119 /* place incomplete frames back on ring for completion */
2120 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2121 continue;
2122
2123 /* verify the packet layout is correct */
2124 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2125 continue;
2126
2127 /* probably a little skewed due to removing CRC */
2128 total_rx_bytes += skb->len;
2129
2130 /* populate checksum, timestamp, VLAN, and protocol */
2131 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2132
2133 #ifdef IXGBE_FCOE
2134 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2135 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2136 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2137 /* include DDPed FCoE data */
2138 if (ddp_bytes > 0) {
2139 if (!mss) {
2140 mss = rx_ring->netdev->mtu -
2141 sizeof(struct fcoe_hdr) -
2142 sizeof(struct fc_frame_header) -
2143 sizeof(struct fcoe_crc_eof);
2144 if (mss > 512)
2145 mss &= ~511;
2146 }
2147 total_rx_bytes += ddp_bytes;
2148 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2149 mss);
2150 }
2151 if (!ddp_bytes) {
2152 dev_kfree_skb_any(skb);
2153 continue;
2154 }
2155 }
2156
2157 #endif /* IXGBE_FCOE */
2158 ixgbe_rx_skb(q_vector, skb);
2159
2160 /* update budget accounting */
2161 total_rx_packets++;
2162 }
2163
2164 u64_stats_update_begin(&rx_ring->syncp);
2165 rx_ring->stats.packets += total_rx_packets;
2166 rx_ring->stats.bytes += total_rx_bytes;
2167 u64_stats_update_end(&rx_ring->syncp);
2168 q_vector->rx.total_packets += total_rx_packets;
2169 q_vector->rx.total_bytes += total_rx_bytes;
2170
2171 return total_rx_packets;
2172 }
2173
2174 #ifdef CONFIG_NET_RX_BUSY_POLL
2175 /* must be called with local_bh_disable()d */
2176 static int ixgbe_low_latency_recv(struct napi_struct *napi)
2177 {
2178 struct ixgbe_q_vector *q_vector =
2179 container_of(napi, struct ixgbe_q_vector, napi);
2180 struct ixgbe_adapter *adapter = q_vector->adapter;
2181 struct ixgbe_ring *ring;
2182 int found = 0;
2183
2184 if (test_bit(__IXGBE_DOWN, &adapter->state))
2185 return LL_FLUSH_FAILED;
2186
2187 if (!ixgbe_qv_lock_poll(q_vector))
2188 return LL_FLUSH_BUSY;
2189
2190 ixgbe_for_each_ring(ring, q_vector->rx) {
2191 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
2192 #ifdef BP_EXTENDED_STATS
2193 if (found)
2194 ring->stats.cleaned += found;
2195 else
2196 ring->stats.misses++;
2197 #endif
2198 if (found)
2199 break;
2200 }
2201
2202 ixgbe_qv_unlock_poll(q_vector);
2203
2204 return found;
2205 }
2206 #endif /* CONFIG_NET_RX_BUSY_POLL */
2207
2208 /**
2209 * ixgbe_configure_msix - Configure MSI-X hardware
2210 * @adapter: board private structure
2211 *
2212 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2213 * interrupts.
2214 **/
2215 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2216 {
2217 struct ixgbe_q_vector *q_vector;
2218 int v_idx;
2219 u32 mask;
2220
2221 /* Populate MSIX to EITR Select */
2222 if (adapter->num_vfs > 32) {
2223 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2224 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2225 }
2226
2227 /*
2228 * Populate the IVAR table and set the ITR values to the
2229 * corresponding register.
2230 */
2231 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2232 struct ixgbe_ring *ring;
2233 q_vector = adapter->q_vector[v_idx];
2234
2235 ixgbe_for_each_ring(ring, q_vector->rx)
2236 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2237
2238 ixgbe_for_each_ring(ring, q_vector->tx)
2239 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2240
2241 ixgbe_write_eitr(q_vector);
2242 }
2243
2244 switch (adapter->hw.mac.type) {
2245 case ixgbe_mac_82598EB:
2246 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2247 v_idx);
2248 break;
2249 case ixgbe_mac_82599EB:
2250 case ixgbe_mac_X540:
2251 case ixgbe_mac_X550:
2252 case ixgbe_mac_X550EM_x:
2253 case ixgbe_mac_x550em_a:
2254 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2255 break;
2256 default:
2257 break;
2258 }
2259 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2260
2261 /* set up to autoclear timer, and the vectors */
2262 mask = IXGBE_EIMS_ENABLE_MASK;
2263 mask &= ~(IXGBE_EIMS_OTHER |
2264 IXGBE_EIMS_MAILBOX |
2265 IXGBE_EIMS_LSC);
2266
2267 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2268 }
2269
2270 enum latency_range {
2271 lowest_latency = 0,
2272 low_latency = 1,
2273 bulk_latency = 2,
2274 latency_invalid = 255
2275 };
2276
2277 /**
2278 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2279 * @q_vector: structure containing interrupt and ring information
2280 * @ring_container: structure containing ring performance data
2281 *
2282 * Stores a new ITR value based on packets and byte
2283 * counts during the last interrupt. The advantage of per interrupt
2284 * computation is faster updates and more accurate ITR for the current
2285 * traffic pattern. Constants in this function were computed
2286 * based on theoretical maximum wire speed and thresholds were set based
2287 * on testing data as well as attempting to minimize response time
2288 * while increasing bulk throughput.
2289 * this functionality is controlled by the InterruptThrottleRate module
2290 * parameter (see ixgbe_param.c)
2291 **/
2292 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2293 struct ixgbe_ring_container *ring_container)
2294 {
2295 int bytes = ring_container->total_bytes;
2296 int packets = ring_container->total_packets;
2297 u32 timepassed_us;
2298 u64 bytes_perint;
2299 u8 itr_setting = ring_container->itr;
2300
2301 if (packets == 0)
2302 return;
2303
2304 /* simple throttlerate management
2305 * 0-10MB/s lowest (100000 ints/s)
2306 * 10-20MB/s low (20000 ints/s)
2307 * 20-1249MB/s bulk (12000 ints/s)
2308 */
2309 /* what was last interrupt timeslice? */
2310 timepassed_us = q_vector->itr >> 2;
2311 if (timepassed_us == 0)
2312 return;
2313
2314 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2315
2316 switch (itr_setting) {
2317 case lowest_latency:
2318 if (bytes_perint > 10)
2319 itr_setting = low_latency;
2320 break;
2321 case low_latency:
2322 if (bytes_perint > 20)
2323 itr_setting = bulk_latency;
2324 else if (bytes_perint <= 10)
2325 itr_setting = lowest_latency;
2326 break;
2327 case bulk_latency:
2328 if (bytes_perint <= 20)
2329 itr_setting = low_latency;
2330 break;
2331 }
2332
2333 /* clear work counters since we have the values we need */
2334 ring_container->total_bytes = 0;
2335 ring_container->total_packets = 0;
2336
2337 /* write updated itr to ring container */
2338 ring_container->itr = itr_setting;
2339 }
2340
2341 /**
2342 * ixgbe_write_eitr - write EITR register in hardware specific way
2343 * @q_vector: structure containing interrupt and ring information
2344 *
2345 * This function is made to be called by ethtool and by the driver
2346 * when it needs to update EITR registers at runtime. Hardware
2347 * specific quirks/differences are taken care of here.
2348 */
2349 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2350 {
2351 struct ixgbe_adapter *adapter = q_vector->adapter;
2352 struct ixgbe_hw *hw = &adapter->hw;
2353 int v_idx = q_vector->v_idx;
2354 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2355
2356 switch (adapter->hw.mac.type) {
2357 case ixgbe_mac_82598EB:
2358 /* must write high and low 16 bits to reset counter */
2359 itr_reg |= (itr_reg << 16);
2360 break;
2361 case ixgbe_mac_82599EB:
2362 case ixgbe_mac_X540:
2363 case ixgbe_mac_X550:
2364 case ixgbe_mac_X550EM_x:
2365 case ixgbe_mac_x550em_a:
2366 /*
2367 * set the WDIS bit to not clear the timer bits and cause an
2368 * immediate assertion of the interrupt
2369 */
2370 itr_reg |= IXGBE_EITR_CNT_WDIS;
2371 break;
2372 default:
2373 break;
2374 }
2375 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2376 }
2377
2378 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2379 {
2380 u32 new_itr = q_vector->itr;
2381 u8 current_itr;
2382
2383 ixgbe_update_itr(q_vector, &q_vector->tx);
2384 ixgbe_update_itr(q_vector, &q_vector->rx);
2385
2386 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2387
2388 switch (current_itr) {
2389 /* counts and packets in update_itr are dependent on these numbers */
2390 case lowest_latency:
2391 new_itr = IXGBE_100K_ITR;
2392 break;
2393 case low_latency:
2394 new_itr = IXGBE_20K_ITR;
2395 break;
2396 case bulk_latency:
2397 new_itr = IXGBE_12K_ITR;
2398 break;
2399 default:
2400 break;
2401 }
2402
2403 if (new_itr != q_vector->itr) {
2404 /* do an exponential smoothing */
2405 new_itr = (10 * new_itr * q_vector->itr) /
2406 ((9 * new_itr) + q_vector->itr);
2407
2408 /* save the algorithm value here */
2409 q_vector->itr = new_itr;
2410
2411 ixgbe_write_eitr(q_vector);
2412 }
2413 }
2414
2415 /**
2416 * ixgbe_check_overtemp_subtask - check for over temperature
2417 * @adapter: pointer to adapter
2418 **/
2419 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2420 {
2421 struct ixgbe_hw *hw = &adapter->hw;
2422 u32 eicr = adapter->interrupt_event;
2423
2424 if (test_bit(__IXGBE_DOWN, &adapter->state))
2425 return;
2426
2427 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2428 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2429 return;
2430
2431 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2432
2433 switch (hw->device_id) {
2434 case IXGBE_DEV_ID_82599_T3_LOM:
2435 /*
2436 * Since the warning interrupt is for both ports
2437 * we don't have to check if:
2438 * - This interrupt wasn't for our port.
2439 * - We may have missed the interrupt so always have to
2440 * check if we got a LSC
2441 */
2442 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
2443 !(eicr & IXGBE_EICR_LSC))
2444 return;
2445
2446 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2447 u32 speed;
2448 bool link_up = false;
2449
2450 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2451
2452 if (link_up)
2453 return;
2454 }
2455
2456 /* Check if this is not due to overtemp */
2457 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2458 return;
2459
2460 break;
2461 default:
2462 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2463 return;
2464 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
2465 return;
2466 break;
2467 }
2468 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2469
2470 adapter->interrupt_event = 0;
2471 }
2472
2473 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2474 {
2475 struct ixgbe_hw *hw = &adapter->hw;
2476
2477 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2478 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2479 e_crit(probe, "Fan has stopped, replace the adapter\n");
2480 /* write to clear the interrupt */
2481 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2482 }
2483 }
2484
2485 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2486 {
2487 struct ixgbe_hw *hw = &adapter->hw;
2488
2489 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2490 return;
2491
2492 switch (adapter->hw.mac.type) {
2493 case ixgbe_mac_82599EB:
2494 /*
2495 * Need to check link state so complete overtemp check
2496 * on service task
2497 */
2498 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2499 (eicr & IXGBE_EICR_LSC)) &&
2500 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2501 adapter->interrupt_event = eicr;
2502 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2503 ixgbe_service_event_schedule(adapter);
2504 return;
2505 }
2506 return;
2507 case ixgbe_mac_X540:
2508 if (!(eicr & IXGBE_EICR_TS))
2509 return;
2510 break;
2511 default:
2512 return;
2513 }
2514
2515 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2516 }
2517
2518 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2519 {
2520 switch (hw->mac.type) {
2521 case ixgbe_mac_82598EB:
2522 if (hw->phy.type == ixgbe_phy_nl)
2523 return true;
2524 return false;
2525 case ixgbe_mac_82599EB:
2526 case ixgbe_mac_X550EM_x:
2527 case ixgbe_mac_x550em_a:
2528 switch (hw->mac.ops.get_media_type(hw)) {
2529 case ixgbe_media_type_fiber:
2530 case ixgbe_media_type_fiber_qsfp:
2531 return true;
2532 default:
2533 return false;
2534 }
2535 default:
2536 return false;
2537 }
2538 }
2539
2540 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2541 {
2542 struct ixgbe_hw *hw = &adapter->hw;
2543 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
2544
2545 if (!ixgbe_is_sfp(hw))
2546 return;
2547
2548 /* Later MAC's use different SDP */
2549 if (hw->mac.type >= ixgbe_mac_X540)
2550 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2551
2552 if (eicr & eicr_mask) {
2553 /* Clear the interrupt */
2554 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
2555 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2556 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2557 adapter->sfp_poll_time = 0;
2558 ixgbe_service_event_schedule(adapter);
2559 }
2560 }
2561
2562 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2563 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2564 /* Clear the interrupt */
2565 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2566 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2567 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2568 ixgbe_service_event_schedule(adapter);
2569 }
2570 }
2571 }
2572
2573 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2574 {
2575 struct ixgbe_hw *hw = &adapter->hw;
2576
2577 adapter->lsc_int++;
2578 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2579 adapter->link_check_timeout = jiffies;
2580 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2581 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2582 IXGBE_WRITE_FLUSH(hw);
2583 ixgbe_service_event_schedule(adapter);
2584 }
2585 }
2586
2587 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2588 u64 qmask)
2589 {
2590 u32 mask;
2591 struct ixgbe_hw *hw = &adapter->hw;
2592
2593 switch (hw->mac.type) {
2594 case ixgbe_mac_82598EB:
2595 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2596 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2597 break;
2598 case ixgbe_mac_82599EB:
2599 case ixgbe_mac_X540:
2600 case ixgbe_mac_X550:
2601 case ixgbe_mac_X550EM_x:
2602 case ixgbe_mac_x550em_a:
2603 mask = (qmask & 0xFFFFFFFF);
2604 if (mask)
2605 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2606 mask = (qmask >> 32);
2607 if (mask)
2608 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2609 break;
2610 default:
2611 break;
2612 }
2613 /* skip the flush */
2614 }
2615
2616 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2617 u64 qmask)
2618 {
2619 u32 mask;
2620 struct ixgbe_hw *hw = &adapter->hw;
2621
2622 switch (hw->mac.type) {
2623 case ixgbe_mac_82598EB:
2624 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2625 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2626 break;
2627 case ixgbe_mac_82599EB:
2628 case ixgbe_mac_X540:
2629 case ixgbe_mac_X550:
2630 case ixgbe_mac_X550EM_x:
2631 case ixgbe_mac_x550em_a:
2632 mask = (qmask & 0xFFFFFFFF);
2633 if (mask)
2634 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2635 mask = (qmask >> 32);
2636 if (mask)
2637 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2638 break;
2639 default:
2640 break;
2641 }
2642 /* skip the flush */
2643 }
2644
2645 /**
2646 * ixgbe_irq_enable - Enable default interrupt generation settings
2647 * @adapter: board private structure
2648 **/
2649 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2650 bool flush)
2651 {
2652 struct ixgbe_hw *hw = &adapter->hw;
2653 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2654
2655 /* don't reenable LSC while waiting for link */
2656 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2657 mask &= ~IXGBE_EIMS_LSC;
2658
2659 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2660 switch (adapter->hw.mac.type) {
2661 case ixgbe_mac_82599EB:
2662 mask |= IXGBE_EIMS_GPI_SDP0(hw);
2663 break;
2664 case ixgbe_mac_X540:
2665 case ixgbe_mac_X550:
2666 case ixgbe_mac_X550EM_x:
2667 case ixgbe_mac_x550em_a:
2668 mask |= IXGBE_EIMS_TS;
2669 break;
2670 default:
2671 break;
2672 }
2673 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2674 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2675 switch (adapter->hw.mac.type) {
2676 case ixgbe_mac_82599EB:
2677 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2678 mask |= IXGBE_EIMS_GPI_SDP2(hw);
2679 /* fall through */
2680 case ixgbe_mac_X540:
2681 case ixgbe_mac_X550:
2682 case ixgbe_mac_X550EM_x:
2683 case ixgbe_mac_x550em_a:
2684 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP ||
2685 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP ||
2686 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N)
2687 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
2688 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2689 mask |= IXGBE_EICR_GPI_SDP0_X540;
2690 mask |= IXGBE_EIMS_ECC;
2691 mask |= IXGBE_EIMS_MAILBOX;
2692 break;
2693 default:
2694 break;
2695 }
2696
2697 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2698 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2699 mask |= IXGBE_EIMS_FLOW_DIR;
2700
2701 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2702 if (queues)
2703 ixgbe_irq_enable_queues(adapter, ~0);
2704 if (flush)
2705 IXGBE_WRITE_FLUSH(&adapter->hw);
2706 }
2707
2708 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2709 {
2710 struct ixgbe_adapter *adapter = data;
2711 struct ixgbe_hw *hw = &adapter->hw;
2712 u32 eicr;
2713
2714 /*
2715 * Workaround for Silicon errata. Use clear-by-write instead
2716 * of clear-by-read. Reading with EICS will return the
2717 * interrupt causes without clearing, which later be done
2718 * with the write to EICR.
2719 */
2720 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2721
2722 /* The lower 16bits of the EICR register are for the queue interrupts
2723 * which should be masked here in order to not accidentally clear them if
2724 * the bits are high when ixgbe_msix_other is called. There is a race
2725 * condition otherwise which results in possible performance loss
2726 * especially if the ixgbe_msix_other interrupt is triggering
2727 * consistently (as it would when PPS is turned on for the X540 device)
2728 */
2729 eicr &= 0xFFFF0000;
2730
2731 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2732
2733 if (eicr & IXGBE_EICR_LSC)
2734 ixgbe_check_lsc(adapter);
2735
2736 if (eicr & IXGBE_EICR_MAILBOX)
2737 ixgbe_msg_task(adapter);
2738
2739 switch (hw->mac.type) {
2740 case ixgbe_mac_82599EB:
2741 case ixgbe_mac_X540:
2742 case ixgbe_mac_X550:
2743 case ixgbe_mac_X550EM_x:
2744 case ixgbe_mac_x550em_a:
2745 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2746 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2747 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2748 ixgbe_service_event_schedule(adapter);
2749 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2750 IXGBE_EICR_GPI_SDP0_X540);
2751 }
2752 if (eicr & IXGBE_EICR_ECC) {
2753 e_info(link, "Received ECC Err, initiating reset\n");
2754 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2755 ixgbe_service_event_schedule(adapter);
2756 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2757 }
2758 /* Handle Flow Director Full threshold interrupt */
2759 if (eicr & IXGBE_EICR_FLOW_DIR) {
2760 int reinit_count = 0;
2761 int i;
2762 for (i = 0; i < adapter->num_tx_queues; i++) {
2763 struct ixgbe_ring *ring = adapter->tx_ring[i];
2764 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2765 &ring->state))
2766 reinit_count++;
2767 }
2768 if (reinit_count) {
2769 /* no more flow director interrupts until after init */
2770 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2771 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2772 ixgbe_service_event_schedule(adapter);
2773 }
2774 }
2775 ixgbe_check_sfp_event(adapter, eicr);
2776 ixgbe_check_overtemp_event(adapter, eicr);
2777 break;
2778 default:
2779 break;
2780 }
2781
2782 ixgbe_check_fan_failure(adapter, eicr);
2783
2784 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2785 ixgbe_ptp_check_pps_event(adapter);
2786
2787 /* re-enable the original interrupt state, no lsc, no queues */
2788 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2789 ixgbe_irq_enable(adapter, false, false);
2790
2791 return IRQ_HANDLED;
2792 }
2793
2794 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2795 {
2796 struct ixgbe_q_vector *q_vector = data;
2797
2798 /* EIAM disabled interrupts (on this vector) for us */
2799
2800 if (q_vector->rx.ring || q_vector->tx.ring)
2801 napi_schedule_irqoff(&q_vector->napi);
2802
2803 return IRQ_HANDLED;
2804 }
2805
2806 /**
2807 * ixgbe_poll - NAPI Rx polling callback
2808 * @napi: structure for representing this polling device
2809 * @budget: how many packets driver is allowed to clean
2810 *
2811 * This function is used for legacy and MSI, NAPI mode
2812 **/
2813 int ixgbe_poll(struct napi_struct *napi, int budget)
2814 {
2815 struct ixgbe_q_vector *q_vector =
2816 container_of(napi, struct ixgbe_q_vector, napi);
2817 struct ixgbe_adapter *adapter = q_vector->adapter;
2818 struct ixgbe_ring *ring;
2819 int per_ring_budget, work_done = 0;
2820 bool clean_complete = true;
2821
2822 #ifdef CONFIG_IXGBE_DCA
2823 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2824 ixgbe_update_dca(q_vector);
2825 #endif
2826
2827 ixgbe_for_each_ring(ring, q_vector->tx) {
2828 if (!ixgbe_clean_tx_irq(q_vector, ring, budget))
2829 clean_complete = false;
2830 }
2831
2832 /* Exit if we are called by netpoll or busy polling is active */
2833 if ((budget <= 0) || !ixgbe_qv_lock_napi(q_vector))
2834 return budget;
2835
2836 /* attempt to distribute budget to each queue fairly, but don't allow
2837 * the budget to go below 1 because we'll exit polling */
2838 if (q_vector->rx.count > 1)
2839 per_ring_budget = max(budget/q_vector->rx.count, 1);
2840 else
2841 per_ring_budget = budget;
2842
2843 ixgbe_for_each_ring(ring, q_vector->rx) {
2844 int cleaned = ixgbe_clean_rx_irq(q_vector, ring,
2845 per_ring_budget);
2846
2847 work_done += cleaned;
2848 if (cleaned >= per_ring_budget)
2849 clean_complete = false;
2850 }
2851
2852 ixgbe_qv_unlock_napi(q_vector);
2853 /* If all work not completed, return budget and keep polling */
2854 if (!clean_complete)
2855 return budget;
2856
2857 /* all work done, exit the polling mode */
2858 napi_complete_done(napi, work_done);
2859 if (adapter->rx_itr_setting & 1)
2860 ixgbe_set_itr(q_vector);
2861 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2862 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2863
2864 return 0;
2865 }
2866
2867 /**
2868 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2869 * @adapter: board private structure
2870 *
2871 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2872 * interrupts from the kernel.
2873 **/
2874 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2875 {
2876 struct net_device *netdev = adapter->netdev;
2877 int vector, err;
2878 int ri = 0, ti = 0;
2879
2880 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2881 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2882 struct msix_entry *entry = &adapter->msix_entries[vector];
2883
2884 if (q_vector->tx.ring && q_vector->rx.ring) {
2885 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2886 "%s-%s-%d", netdev->name, "TxRx", ri++);
2887 ti++;
2888 } else if (q_vector->rx.ring) {
2889 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2890 "%s-%s-%d", netdev->name, "rx", ri++);
2891 } else if (q_vector->tx.ring) {
2892 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2893 "%s-%s-%d", netdev->name, "tx", ti++);
2894 } else {
2895 /* skip this unused q_vector */
2896 continue;
2897 }
2898 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2899 q_vector->name, q_vector);
2900 if (err) {
2901 e_err(probe, "request_irq failed for MSIX interrupt "
2902 "Error: %d\n", err);
2903 goto free_queue_irqs;
2904 }
2905 /* If Flow Director is enabled, set interrupt affinity */
2906 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2907 /* assign the mask for this irq */
2908 irq_set_affinity_hint(entry->vector,
2909 &q_vector->affinity_mask);
2910 }
2911 }
2912
2913 err = request_irq(adapter->msix_entries[vector].vector,
2914 ixgbe_msix_other, 0, netdev->name, adapter);
2915 if (err) {
2916 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2917 goto free_queue_irqs;
2918 }
2919
2920 return 0;
2921
2922 free_queue_irqs:
2923 while (vector) {
2924 vector--;
2925 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2926 NULL);
2927 free_irq(adapter->msix_entries[vector].vector,
2928 adapter->q_vector[vector]);
2929 }
2930 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2931 pci_disable_msix(adapter->pdev);
2932 kfree(adapter->msix_entries);
2933 adapter->msix_entries = NULL;
2934 return err;
2935 }
2936
2937 /**
2938 * ixgbe_intr - legacy mode Interrupt Handler
2939 * @irq: interrupt number
2940 * @data: pointer to a network interface device structure
2941 **/
2942 static irqreturn_t ixgbe_intr(int irq, void *data)
2943 {
2944 struct ixgbe_adapter *adapter = data;
2945 struct ixgbe_hw *hw = &adapter->hw;
2946 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2947 u32 eicr;
2948
2949 /*
2950 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2951 * before the read of EICR.
2952 */
2953 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2954
2955 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2956 * therefore no explicit interrupt disable is necessary */
2957 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2958 if (!eicr) {
2959 /*
2960 * shared interrupt alert!
2961 * make sure interrupts are enabled because the read will
2962 * have disabled interrupts due to EIAM
2963 * finish the workaround of silicon errata on 82598. Unmask
2964 * the interrupt that we masked before the EICR read.
2965 */
2966 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2967 ixgbe_irq_enable(adapter, true, true);
2968 return IRQ_NONE; /* Not our interrupt */
2969 }
2970
2971 if (eicr & IXGBE_EICR_LSC)
2972 ixgbe_check_lsc(adapter);
2973
2974 switch (hw->mac.type) {
2975 case ixgbe_mac_82599EB:
2976 ixgbe_check_sfp_event(adapter, eicr);
2977 /* Fall through */
2978 case ixgbe_mac_X540:
2979 case ixgbe_mac_X550:
2980 case ixgbe_mac_X550EM_x:
2981 case ixgbe_mac_x550em_a:
2982 if (eicr & IXGBE_EICR_ECC) {
2983 e_info(link, "Received ECC Err, initiating reset\n");
2984 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2985 ixgbe_service_event_schedule(adapter);
2986 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2987 }
2988 ixgbe_check_overtemp_event(adapter, eicr);
2989 break;
2990 default:
2991 break;
2992 }
2993
2994 ixgbe_check_fan_failure(adapter, eicr);
2995 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2996 ixgbe_ptp_check_pps_event(adapter);
2997
2998 /* would disable interrupts here but EIAM disabled it */
2999 napi_schedule_irqoff(&q_vector->napi);
3000
3001 /*
3002 * re-enable link(maybe) and non-queue interrupts, no flush.
3003 * ixgbe_poll will re-enable the queue interrupts
3004 */
3005 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3006 ixgbe_irq_enable(adapter, false, false);
3007
3008 return IRQ_HANDLED;
3009 }
3010
3011 /**
3012 * ixgbe_request_irq - initialize interrupts
3013 * @adapter: board private structure
3014 *
3015 * Attempts to configure interrupts using the best available
3016 * capabilities of the hardware and kernel.
3017 **/
3018 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
3019 {
3020 struct net_device *netdev = adapter->netdev;
3021 int err;
3022
3023 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3024 err = ixgbe_request_msix_irqs(adapter);
3025 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
3026 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
3027 netdev->name, adapter);
3028 else
3029 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
3030 netdev->name, adapter);
3031
3032 if (err)
3033 e_err(probe, "request_irq failed, Error %d\n", err);
3034
3035 return err;
3036 }
3037
3038 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
3039 {
3040 int vector;
3041
3042 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3043 free_irq(adapter->pdev->irq, adapter);
3044 return;
3045 }
3046
3047 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3048 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3049 struct msix_entry *entry = &adapter->msix_entries[vector];
3050
3051 /* free only the irqs that were actually requested */
3052 if (!q_vector->rx.ring && !q_vector->tx.ring)
3053 continue;
3054
3055 /* clear the affinity_mask in the IRQ descriptor */
3056 irq_set_affinity_hint(entry->vector, NULL);
3057
3058 free_irq(entry->vector, q_vector);
3059 }
3060
3061 free_irq(adapter->msix_entries[vector++].vector, adapter);
3062 }
3063
3064 /**
3065 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3066 * @adapter: board private structure
3067 **/
3068 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3069 {
3070 switch (adapter->hw.mac.type) {
3071 case ixgbe_mac_82598EB:
3072 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
3073 break;
3074 case ixgbe_mac_82599EB:
3075 case ixgbe_mac_X540:
3076 case ixgbe_mac_X550:
3077 case ixgbe_mac_X550EM_x:
3078 case ixgbe_mac_x550em_a:
3079 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3080 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
3081 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
3082 break;
3083 default:
3084 break;
3085 }
3086 IXGBE_WRITE_FLUSH(&adapter->hw);
3087 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3088 int vector;
3089
3090 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3091 synchronize_irq(adapter->msix_entries[vector].vector);
3092
3093 synchronize_irq(adapter->msix_entries[vector++].vector);
3094 } else {
3095 synchronize_irq(adapter->pdev->irq);
3096 }
3097 }
3098
3099 /**
3100 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3101 *
3102 **/
3103 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3104 {
3105 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3106
3107 ixgbe_write_eitr(q_vector);
3108
3109 ixgbe_set_ivar(adapter, 0, 0, 0);
3110 ixgbe_set_ivar(adapter, 1, 0, 0);
3111
3112 e_info(hw, "Legacy interrupt IVAR setup done\n");
3113 }
3114
3115 /**
3116 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3117 * @adapter: board private structure
3118 * @ring: structure containing ring specific data
3119 *
3120 * Configure the Tx descriptor ring after a reset.
3121 **/
3122 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3123 struct ixgbe_ring *ring)
3124 {
3125 struct ixgbe_hw *hw = &adapter->hw;
3126 u64 tdba = ring->dma;
3127 int wait_loop = 10;
3128 u32 txdctl = IXGBE_TXDCTL_ENABLE;
3129 u8 reg_idx = ring->reg_idx;
3130
3131 /* disable queue to avoid issues while updating state */
3132 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
3133 IXGBE_WRITE_FLUSH(hw);
3134
3135 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
3136 (tdba & DMA_BIT_MASK(32)));
3137 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3138 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3139 ring->count * sizeof(union ixgbe_adv_tx_desc));
3140 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3141 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
3142 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
3143
3144 /*
3145 * set WTHRESH to encourage burst writeback, it should not be set
3146 * higher than 1 when:
3147 * - ITR is 0 as it could cause false TX hangs
3148 * - ITR is set to > 100k int/sec and BQL is enabled
3149 *
3150 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3151 * to or less than the number of on chip descriptors, which is
3152 * currently 40.
3153 */
3154 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3155 txdctl |= (1 << 16); /* WTHRESH = 1 */
3156 else
3157 txdctl |= (8 << 16); /* WTHRESH = 8 */
3158
3159 /*
3160 * Setting PTHRESH to 32 both improves performance
3161 * and avoids a TX hang with DFP enabled
3162 */
3163 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3164 32; /* PTHRESH = 32 */
3165
3166 /* reinitialize flowdirector state */
3167 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3168 ring->atr_sample_rate = adapter->atr_sample_rate;
3169 ring->atr_count = 0;
3170 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3171 } else {
3172 ring->atr_sample_rate = 0;
3173 }
3174
3175 /* initialize XPS */
3176 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3177 struct ixgbe_q_vector *q_vector = ring->q_vector;
3178
3179 if (q_vector)
3180 netif_set_xps_queue(ring->netdev,
3181 &q_vector->affinity_mask,
3182 ring->queue_index);
3183 }
3184
3185 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3186
3187 /* enable queue */
3188 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3189
3190 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3191 if (hw->mac.type == ixgbe_mac_82598EB &&
3192 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3193 return;
3194
3195 /* poll to verify queue is enabled */
3196 do {
3197 usleep_range(1000, 2000);
3198 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3199 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3200 if (!wait_loop)
3201 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
3202 }
3203
3204 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3205 {
3206 struct ixgbe_hw *hw = &adapter->hw;
3207 u32 rttdcs, mtqc;
3208 u8 tcs = netdev_get_num_tc(adapter->netdev);
3209
3210 if (hw->mac.type == ixgbe_mac_82598EB)
3211 return;
3212
3213 /* disable the arbiter while setting MTQC */
3214 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3215 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3216 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3217
3218 /* set transmit pool layout */
3219 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3220 mtqc = IXGBE_MTQC_VT_ENA;
3221 if (tcs > 4)
3222 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3223 else if (tcs > 1)
3224 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3225 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3226 mtqc |= IXGBE_MTQC_32VF;
3227 else
3228 mtqc |= IXGBE_MTQC_64VF;
3229 } else {
3230 if (tcs > 4)
3231 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3232 else if (tcs > 1)
3233 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3234 else
3235 mtqc = IXGBE_MTQC_64Q_1PB;
3236 }
3237
3238 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3239
3240 /* Enable Security TX Buffer IFG for multiple pb */
3241 if (tcs) {
3242 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3243 sectx |= IXGBE_SECTX_DCB;
3244 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3245 }
3246
3247 /* re-enable the arbiter */
3248 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3249 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3250 }
3251
3252 /**
3253 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3254 * @adapter: board private structure
3255 *
3256 * Configure the Tx unit of the MAC after a reset.
3257 **/
3258 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3259 {
3260 struct ixgbe_hw *hw = &adapter->hw;
3261 u32 dmatxctl;
3262 u32 i;
3263
3264 ixgbe_setup_mtqc(adapter);
3265
3266 if (hw->mac.type != ixgbe_mac_82598EB) {
3267 /* DMATXCTL.EN must be before Tx queues are enabled */
3268 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3269 dmatxctl |= IXGBE_DMATXCTL_TE;
3270 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3271 }
3272
3273 /* Setup the HW Tx Head and Tail descriptor pointers */
3274 for (i = 0; i < adapter->num_tx_queues; i++)
3275 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3276 }
3277
3278 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3279 struct ixgbe_ring *ring)
3280 {
3281 struct ixgbe_hw *hw = &adapter->hw;
3282 u8 reg_idx = ring->reg_idx;
3283 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3284
3285 srrctl |= IXGBE_SRRCTL_DROP_EN;
3286
3287 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3288 }
3289
3290 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3291 struct ixgbe_ring *ring)
3292 {
3293 struct ixgbe_hw *hw = &adapter->hw;
3294 u8 reg_idx = ring->reg_idx;
3295 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3296
3297 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3298
3299 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3300 }
3301
3302 #ifdef CONFIG_IXGBE_DCB
3303 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3304 #else
3305 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3306 #endif
3307 {
3308 int i;
3309 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3310
3311 if (adapter->ixgbe_ieee_pfc)
3312 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3313
3314 /*
3315 * We should set the drop enable bit if:
3316 * SR-IOV is enabled
3317 * or
3318 * Number of Rx queues > 1 and flow control is disabled
3319 *
3320 * This allows us to avoid head of line blocking for security
3321 * and performance reasons.
3322 */
3323 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3324 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3325 for (i = 0; i < adapter->num_rx_queues; i++)
3326 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3327 } else {
3328 for (i = 0; i < adapter->num_rx_queues; i++)
3329 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3330 }
3331 }
3332
3333 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3334
3335 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3336 struct ixgbe_ring *rx_ring)
3337 {
3338 struct ixgbe_hw *hw = &adapter->hw;
3339 u32 srrctl;
3340 u8 reg_idx = rx_ring->reg_idx;
3341
3342 if (hw->mac.type == ixgbe_mac_82598EB) {
3343 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3344
3345 /*
3346 * if VMDq is not active we must program one srrctl register
3347 * per RSS queue since we have enabled RDRXCTL.MVMEN
3348 */
3349 reg_idx &= mask;
3350 }
3351
3352 /* configure header buffer length, needed for RSC */
3353 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3354
3355 /* configure the packet buffer length */
3356 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3357
3358 /* configure descriptor type */
3359 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3360
3361 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3362 }
3363
3364 /**
3365 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
3366 * @adapter: device handle
3367 *
3368 * - 82598/82599/X540: 128
3369 * - X550(non-SRIOV mode): 512
3370 * - X550(SRIOV mode): 64
3371 */
3372 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
3373 {
3374 if (adapter->hw.mac.type < ixgbe_mac_X550)
3375 return 128;
3376 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3377 return 64;
3378 else
3379 return 512;
3380 }
3381
3382 /**
3383 * ixgbe_store_reta - Write the RETA table to HW
3384 * @adapter: device handle
3385 *
3386 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3387 */
3388 void ixgbe_store_reta(struct ixgbe_adapter *adapter)
3389 {
3390 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3391 struct ixgbe_hw *hw = &adapter->hw;
3392 u32 reta = 0;
3393 u32 indices_multi;
3394 u8 *indir_tbl = adapter->rss_indir_tbl;
3395
3396 /* Fill out the redirection table as follows:
3397 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3398 * indices.
3399 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3400 * - X550: 8 bit wide entries containing 6 bit RSS index
3401 */
3402 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3403 indices_multi = 0x11;
3404 else
3405 indices_multi = 0x1;
3406
3407 /* Write redirection table to HW */
3408 for (i = 0; i < reta_entries; i++) {
3409 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
3410 if ((i & 3) == 3) {
3411 if (i < 128)
3412 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3413 else
3414 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3415 reta);
3416 reta = 0;
3417 }
3418 }
3419 }
3420
3421 /**
3422 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
3423 * @adapter: device handle
3424 *
3425 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3426 */
3427 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
3428 {
3429 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3430 struct ixgbe_hw *hw = &adapter->hw;
3431 u32 vfreta = 0;
3432 unsigned int pf_pool = adapter->num_vfs;
3433
3434 /* Write redirection table to HW */
3435 for (i = 0; i < reta_entries; i++) {
3436 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3437 if ((i & 3) == 3) {
3438 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3439 vfreta);
3440 vfreta = 0;
3441 }
3442 }
3443 }
3444
3445 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3446 {
3447 struct ixgbe_hw *hw = &adapter->hw;
3448 u32 i, j;
3449 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3450 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3451
3452 /* Program table for at least 2 queues w/ SR-IOV so that VFs can
3453 * make full use of any rings they may have. We will use the
3454 * PSRTYPE register to control how many rings we use within the PF.
3455 */
3456 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3457 rss_i = 2;
3458
3459 /* Fill out hash function seeds */
3460 for (i = 0; i < 10; i++)
3461 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3462
3463 /* Fill out redirection table */
3464 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3465
3466 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3467 if (j == rss_i)
3468 j = 0;
3469
3470 adapter->rss_indir_tbl[i] = j;
3471 }
3472
3473 ixgbe_store_reta(adapter);
3474 }
3475
3476 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3477 {
3478 struct ixgbe_hw *hw = &adapter->hw;
3479 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3480 unsigned int pf_pool = adapter->num_vfs;
3481 int i, j;
3482
3483 /* Fill out hash function seeds */
3484 for (i = 0; i < 10; i++)
3485 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3486 adapter->rss_key[i]);
3487
3488 /* Fill out the redirection table */
3489 for (i = 0, j = 0; i < 64; i++, j++) {
3490 if (j == rss_i)
3491 j = 0;
3492
3493 adapter->rss_indir_tbl[i] = j;
3494 }
3495
3496 ixgbe_store_vfreta(adapter);
3497 }
3498
3499 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3500 {
3501 struct ixgbe_hw *hw = &adapter->hw;
3502 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
3503 u32 rxcsum;
3504
3505 /* Disable indicating checksum in descriptor, enables RSS hash */
3506 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3507 rxcsum |= IXGBE_RXCSUM_PCSD;
3508 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3509
3510 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3511 if (adapter->ring_feature[RING_F_RSS].mask)
3512 mrqc = IXGBE_MRQC_RSSEN;
3513 } else {
3514 u8 tcs = netdev_get_num_tc(adapter->netdev);
3515
3516 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3517 if (tcs > 4)
3518 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3519 else if (tcs > 1)
3520 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3521 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3522 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3523 else
3524 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3525 } else {
3526 if (tcs > 4)
3527 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3528 else if (tcs > 1)
3529 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3530 else
3531 mrqc = IXGBE_MRQC_RSSEN;
3532 }
3533 }
3534
3535 /* Perform hash on these packet types */
3536 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3537 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3538 IXGBE_MRQC_RSS_FIELD_IPV6 |
3539 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3540
3541 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3542 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3543 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3544 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3545
3546 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
3547 if ((hw->mac.type >= ixgbe_mac_X550) &&
3548 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3549 unsigned int pf_pool = adapter->num_vfs;
3550
3551 /* Enable VF RSS mode */
3552 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3553 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3554
3555 /* Setup RSS through the VF registers */
3556 ixgbe_setup_vfreta(adapter);
3557 vfmrqc = IXGBE_MRQC_RSSEN;
3558 vfmrqc |= rss_field;
3559 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3560 } else {
3561 ixgbe_setup_reta(adapter);
3562 mrqc |= rss_field;
3563 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3564 }
3565 }
3566
3567 /**
3568 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3569 * @adapter: address of board private structure
3570 * @index: index of ring to set
3571 **/
3572 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3573 struct ixgbe_ring *ring)
3574 {
3575 struct ixgbe_hw *hw = &adapter->hw;
3576 u32 rscctrl;
3577 u8 reg_idx = ring->reg_idx;
3578
3579 if (!ring_is_rsc_enabled(ring))
3580 return;
3581
3582 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3583 rscctrl |= IXGBE_RSCCTL_RSCEN;
3584 /*
3585 * we must limit the number of descriptors so that the
3586 * total size of max desc * buf_len is not greater
3587 * than 65536
3588 */
3589 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3590 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3591 }
3592
3593 #define IXGBE_MAX_RX_DESC_POLL 10
3594 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3595 struct ixgbe_ring *ring)
3596 {
3597 struct ixgbe_hw *hw = &adapter->hw;
3598 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3599 u32 rxdctl;
3600 u8 reg_idx = ring->reg_idx;
3601
3602 if (ixgbe_removed(hw->hw_addr))
3603 return;
3604 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3605 if (hw->mac.type == ixgbe_mac_82598EB &&
3606 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3607 return;
3608
3609 do {
3610 usleep_range(1000, 2000);
3611 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3612 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3613
3614 if (!wait_loop) {
3615 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3616 "the polling period\n", reg_idx);
3617 }
3618 }
3619
3620 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3621 struct ixgbe_ring *ring)
3622 {
3623 struct ixgbe_hw *hw = &adapter->hw;
3624 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3625 u32 rxdctl;
3626 u8 reg_idx = ring->reg_idx;
3627
3628 if (ixgbe_removed(hw->hw_addr))
3629 return;
3630 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3631 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3632
3633 /* write value back with RXDCTL.ENABLE bit cleared */
3634 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3635
3636 if (hw->mac.type == ixgbe_mac_82598EB &&
3637 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3638 return;
3639
3640 /* the hardware may take up to 100us to really disable the rx queue */
3641 do {
3642 udelay(10);
3643 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3644 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3645
3646 if (!wait_loop) {
3647 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3648 "the polling period\n", reg_idx);
3649 }
3650 }
3651
3652 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3653 struct ixgbe_ring *ring)
3654 {
3655 struct ixgbe_hw *hw = &adapter->hw;
3656 u64 rdba = ring->dma;
3657 u32 rxdctl;
3658 u8 reg_idx = ring->reg_idx;
3659
3660 /* disable queue to avoid issues while updating state */
3661 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3662 ixgbe_disable_rx_queue(adapter, ring);
3663
3664 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3665 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3666 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3667 ring->count * sizeof(union ixgbe_adv_rx_desc));
3668 /* Force flushing of IXGBE_RDLEN to prevent MDD */
3669 IXGBE_WRITE_FLUSH(hw);
3670
3671 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3672 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3673 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
3674
3675 ixgbe_configure_srrctl(adapter, ring);
3676 ixgbe_configure_rscctl(adapter, ring);
3677
3678 if (hw->mac.type == ixgbe_mac_82598EB) {
3679 /*
3680 * enable cache line friendly hardware writes:
3681 * PTHRESH=32 descriptors (half the internal cache),
3682 * this also removes ugly rx_no_buffer_count increment
3683 * HTHRESH=4 descriptors (to minimize latency on fetch)
3684 * WTHRESH=8 burst writeback up to two cache lines
3685 */
3686 rxdctl &= ~0x3FFFFF;
3687 rxdctl |= 0x080420;
3688 }
3689
3690 /* enable receive descriptor ring */
3691 rxdctl |= IXGBE_RXDCTL_ENABLE;
3692 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3693
3694 ixgbe_rx_desc_queue_enable(adapter, ring);
3695 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3696 }
3697
3698 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3699 {
3700 struct ixgbe_hw *hw = &adapter->hw;
3701 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3702 u16 pool;
3703
3704 /* PSRTYPE must be initialized in non 82598 adapters */
3705 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3706 IXGBE_PSRTYPE_UDPHDR |
3707 IXGBE_PSRTYPE_IPV4HDR |
3708 IXGBE_PSRTYPE_L2HDR |
3709 IXGBE_PSRTYPE_IPV6HDR;
3710
3711 if (hw->mac.type == ixgbe_mac_82598EB)
3712 return;
3713
3714 if (rss_i > 3)
3715 psrtype |= 2 << 29;
3716 else if (rss_i > 1)
3717 psrtype |= 1 << 29;
3718
3719 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3720 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
3721 }
3722
3723 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3724 {
3725 struct ixgbe_hw *hw = &adapter->hw;
3726 u32 reg_offset, vf_shift;
3727 u32 gcr_ext, vmdctl;
3728 int i;
3729
3730 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3731 return;
3732
3733 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3734 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3735 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3736 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3737 vmdctl |= IXGBE_VT_CTL_REPLEN;
3738 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3739
3740 vf_shift = VMDQ_P(0) % 32;
3741 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3742
3743 /* Enable only the PF's pool for Tx/Rx */
3744 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3745 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3746 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3747 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3748 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
3749 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3750
3751 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3752 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3753
3754 /* clear VLAN promisc flag so VFTA will be updated if necessary */
3755 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
3756
3757 /*
3758 * Set up VF register offsets for selected VT Mode,
3759 * i.e. 32 or 64 VFs for SR-IOV
3760 */
3761 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3762 case IXGBE_82599_VMDQ_8Q_MASK:
3763 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3764 break;
3765 case IXGBE_82599_VMDQ_4Q_MASK:
3766 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3767 break;
3768 default:
3769 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3770 break;
3771 }
3772
3773 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3774
3775
3776 /* Enable MAC Anti-Spoofing */
3777 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3778 adapter->num_vfs);
3779
3780 /* Ensure LLDP and FC is set for Ethertype Antispoofing if we will be
3781 * calling set_ethertype_anti_spoofing for each VF in loop below
3782 */
3783 if (hw->mac.ops.set_ethertype_anti_spoofing) {
3784 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
3785 (IXGBE_ETQF_FILTER_EN |
3786 IXGBE_ETQF_TX_ANTISPOOF |
3787 IXGBE_ETH_P_LLDP));
3788
3789 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FC),
3790 (IXGBE_ETQF_FILTER_EN |
3791 IXGBE_ETQF_TX_ANTISPOOF |
3792 ETH_P_PAUSE));
3793 }
3794
3795 /* For VFs that have spoof checking turned off */
3796 for (i = 0; i < adapter->num_vfs; i++) {
3797 if (!adapter->vfinfo[i].spoofchk_enabled)
3798 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3799
3800 /* enable ethertype anti spoofing if hw supports it */
3801 if (hw->mac.ops.set_ethertype_anti_spoofing)
3802 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
3803
3804 /* Enable/Disable RSS query feature */
3805 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
3806 adapter->vfinfo[i].rss_query_enabled);
3807 }
3808 }
3809
3810 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3811 {
3812 struct ixgbe_hw *hw = &adapter->hw;
3813 struct net_device *netdev = adapter->netdev;
3814 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3815 struct ixgbe_ring *rx_ring;
3816 int i;
3817 u32 mhadd, hlreg0;
3818
3819 #ifdef IXGBE_FCOE
3820 /* adjust max frame to be able to do baby jumbo for FCoE */
3821 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3822 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3823 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3824
3825 #endif /* IXGBE_FCOE */
3826
3827 /* adjust max frame to be at least the size of a standard frame */
3828 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3829 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3830
3831 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3832 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3833 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3834 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3835
3836 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3837 }
3838
3839 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3840 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3841 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3842 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3843
3844 /*
3845 * Setup the HW Rx Head and Tail Descriptor Pointers and
3846 * the Base and Length of the Rx Descriptor Ring
3847 */
3848 for (i = 0; i < adapter->num_rx_queues; i++) {
3849 rx_ring = adapter->rx_ring[i];
3850 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3851 set_ring_rsc_enabled(rx_ring);
3852 else
3853 clear_ring_rsc_enabled(rx_ring);
3854 }
3855 }
3856
3857 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3858 {
3859 struct ixgbe_hw *hw = &adapter->hw;
3860 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3861
3862 switch (hw->mac.type) {
3863 case ixgbe_mac_82598EB:
3864 /*
3865 * For VMDq support of different descriptor types or
3866 * buffer sizes through the use of multiple SRRCTL
3867 * registers, RDRXCTL.MVMEN must be set to 1
3868 *
3869 * also, the manual doesn't mention it clearly but DCA hints
3870 * will only use queue 0's tags unless this bit is set. Side
3871 * effects of setting this bit are only that SRRCTL must be
3872 * fully programmed [0..15]
3873 */
3874 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3875 break;
3876 case ixgbe_mac_X550:
3877 case ixgbe_mac_X550EM_x:
3878 case ixgbe_mac_x550em_a:
3879 if (adapter->num_vfs)
3880 rdrxctl |= IXGBE_RDRXCTL_PSP;
3881 /* fall through for older HW */
3882 case ixgbe_mac_82599EB:
3883 case ixgbe_mac_X540:
3884 /* Disable RSC for ACK packets */
3885 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3886 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3887 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3888 /* hardware requires some bits to be set by default */
3889 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3890 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3891 break;
3892 default:
3893 /* We should do nothing since we don't know this hardware */
3894 return;
3895 }
3896
3897 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3898 }
3899
3900 /**
3901 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3902 * @adapter: board private structure
3903 *
3904 * Configure the Rx unit of the MAC after a reset.
3905 **/
3906 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3907 {
3908 struct ixgbe_hw *hw = &adapter->hw;
3909 int i;
3910 u32 rxctrl, rfctl;
3911
3912 /* disable receives while setting up the descriptors */
3913 hw->mac.ops.disable_rx(hw);
3914
3915 ixgbe_setup_psrtype(adapter);
3916 ixgbe_setup_rdrxctl(adapter);
3917
3918 /* RSC Setup */
3919 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3920 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3921 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3922 rfctl |= IXGBE_RFCTL_RSC_DIS;
3923 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3924
3925 /* Program registers for the distribution of queues */
3926 ixgbe_setup_mrqc(adapter);
3927
3928 /* set_rx_buffer_len must be called before ring initialization */
3929 ixgbe_set_rx_buffer_len(adapter);
3930
3931 /*
3932 * Setup the HW Rx Head and Tail Descriptor Pointers and
3933 * the Base and Length of the Rx Descriptor Ring
3934 */
3935 for (i = 0; i < adapter->num_rx_queues; i++)
3936 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3937
3938 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3939 /* disable drop enable for 82598 parts */
3940 if (hw->mac.type == ixgbe_mac_82598EB)
3941 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3942
3943 /* enable all receives */
3944 rxctrl |= IXGBE_RXCTRL_RXEN;
3945 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3946 }
3947
3948 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3949 __be16 proto, u16 vid)
3950 {
3951 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3952 struct ixgbe_hw *hw = &adapter->hw;
3953
3954 /* add VID to filter table */
3955 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
3956 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid);
3957
3958 set_bit(vid, adapter->active_vlans);
3959
3960 return 0;
3961 }
3962
3963 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan)
3964 {
3965 u32 vlvf;
3966 int idx;
3967
3968 /* short cut the special case */
3969 if (vlan == 0)
3970 return 0;
3971
3972 /* Search for the vlan id in the VLVF entries */
3973 for (idx = IXGBE_VLVF_ENTRIES; --idx;) {
3974 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx));
3975 if ((vlvf & VLAN_VID_MASK) == vlan)
3976 break;
3977 }
3978
3979 return idx;
3980 }
3981
3982 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid)
3983 {
3984 struct ixgbe_hw *hw = &adapter->hw;
3985 u32 bits, word;
3986 int idx;
3987
3988 idx = ixgbe_find_vlvf_entry(hw, vid);
3989 if (!idx)
3990 return;
3991
3992 /* See if any other pools are set for this VLAN filter
3993 * entry other than the PF.
3994 */
3995 word = idx * 2 + (VMDQ_P(0) / 32);
3996 bits = ~(1 << (VMDQ_P(0)) % 32);
3997 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
3998
3999 /* Disable the filter so this falls into the default pool. */
4000 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) {
4001 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4002 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0);
4003 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0);
4004 }
4005 }
4006
4007 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
4008 __be16 proto, u16 vid)
4009 {
4010 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4011 struct ixgbe_hw *hw = &adapter->hw;
4012
4013 /* remove VID from filter table */
4014 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4015 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true);
4016
4017 clear_bit(vid, adapter->active_vlans);
4018
4019 return 0;
4020 }
4021
4022 /**
4023 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
4024 * @adapter: driver data
4025 */
4026 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
4027 {
4028 struct ixgbe_hw *hw = &adapter->hw;
4029 u32 vlnctrl;
4030 int i, j;
4031
4032 switch (hw->mac.type) {
4033 case ixgbe_mac_82598EB:
4034 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4035 vlnctrl &= ~IXGBE_VLNCTRL_VME;
4036 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4037 break;
4038 case ixgbe_mac_82599EB:
4039 case ixgbe_mac_X540:
4040 case ixgbe_mac_X550:
4041 case ixgbe_mac_X550EM_x:
4042 case ixgbe_mac_x550em_a:
4043 for (i = 0; i < adapter->num_rx_queues; i++) {
4044 struct ixgbe_ring *ring = adapter->rx_ring[i];
4045
4046 if (ring->l2_accel_priv)
4047 continue;
4048 j = ring->reg_idx;
4049 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4050 vlnctrl &= ~IXGBE_RXDCTL_VME;
4051 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4052 }
4053 break;
4054 default:
4055 break;
4056 }
4057 }
4058
4059 /**
4060 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
4061 * @adapter: driver data
4062 */
4063 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
4064 {
4065 struct ixgbe_hw *hw = &adapter->hw;
4066 u32 vlnctrl;
4067 int i, j;
4068
4069 switch (hw->mac.type) {
4070 case ixgbe_mac_82598EB:
4071 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4072 vlnctrl |= IXGBE_VLNCTRL_VME;
4073 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4074 break;
4075 case ixgbe_mac_82599EB:
4076 case ixgbe_mac_X540:
4077 case ixgbe_mac_X550:
4078 case ixgbe_mac_X550EM_x:
4079 case ixgbe_mac_x550em_a:
4080 for (i = 0; i < adapter->num_rx_queues; i++) {
4081 struct ixgbe_ring *ring = adapter->rx_ring[i];
4082
4083 if (ring->l2_accel_priv)
4084 continue;
4085 j = ring->reg_idx;
4086 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4087 vlnctrl |= IXGBE_RXDCTL_VME;
4088 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4089 }
4090 break;
4091 default:
4092 break;
4093 }
4094 }
4095
4096 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter)
4097 {
4098 struct ixgbe_hw *hw = &adapter->hw;
4099 u32 vlnctrl, i;
4100
4101 switch (hw->mac.type) {
4102 case ixgbe_mac_82599EB:
4103 case ixgbe_mac_X540:
4104 case ixgbe_mac_X550:
4105 case ixgbe_mac_X550EM_x:
4106 case ixgbe_mac_x550em_a:
4107 default:
4108 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)
4109 break;
4110 /* fall through */
4111 case ixgbe_mac_82598EB:
4112 /* legacy case, we can just disable VLAN filtering */
4113 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4114 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4115 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4116 return;
4117 }
4118
4119 /* We are already in VLAN promisc, nothing to do */
4120 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
4121 return;
4122
4123 /* Set flag so we don't redo unnecessary work */
4124 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC;
4125
4126 /* Add PF to all active pools */
4127 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4128 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);
4129 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);
4130
4131 vlvfb |= 1 << (VMDQ_P(0) % 32);
4132 IXGBE_WRITE_REG(hw, reg_offset, vlvfb);
4133 }
4134
4135 /* Set all bits in the VLAN filter table array */
4136 for (i = hw->mac.vft_size; i--;)
4137 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U);
4138 }
4139
4140 #define VFTA_BLOCK_SIZE 8
4141 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4142 {
4143 struct ixgbe_hw *hw = &adapter->hw;
4144 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4145 u32 vid_start = vfta_offset * 32;
4146 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4147 u32 i, vid, word, bits;
4148
4149 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4150 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
4151
4152 /* pull VLAN ID from VLVF */
4153 vid = vlvf & VLAN_VID_MASK;
4154
4155 /* only concern outselves with a certain range */
4156 if (vid < vid_start || vid >= vid_end)
4157 continue;
4158
4159 if (vlvf) {
4160 /* record VLAN ID in VFTA */
4161 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32);
4162
4163 /* if PF is part of this then continue */
4164 if (test_bit(vid, adapter->active_vlans))
4165 continue;
4166 }
4167
4168 /* remove PF from the pool */
4169 word = i * 2 + VMDQ_P(0) / 32;
4170 bits = ~(1 << (VMDQ_P(0) % 32));
4171 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4172 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits);
4173 }
4174
4175 /* extract values from active_vlans and write back to VFTA */
4176 for (i = VFTA_BLOCK_SIZE; i--;) {
4177 vid = (vfta_offset + i) * 32;
4178 word = vid / BITS_PER_LONG;
4179 bits = vid % BITS_PER_LONG;
4180
4181 vfta[i] |= adapter->active_vlans[word] >> bits;
4182
4183 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]);
4184 }
4185 }
4186
4187 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter)
4188 {
4189 struct ixgbe_hw *hw = &adapter->hw;
4190 u32 vlnctrl, i;
4191
4192 switch (hw->mac.type) {
4193 case ixgbe_mac_82599EB:
4194 case ixgbe_mac_X540:
4195 case ixgbe_mac_X550:
4196 case ixgbe_mac_X550EM_x:
4197 case ixgbe_mac_x550em_a:
4198 default:
4199 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)
4200 break;
4201 /* fall through */
4202 case ixgbe_mac_82598EB:
4203 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4204 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
4205 vlnctrl |= IXGBE_VLNCTRL_VFE;
4206 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4207 return;
4208 }
4209
4210 /* We are not in VLAN promisc, nothing to do */
4211 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4212 return;
4213
4214 /* Set flag so we don't redo unnecessary work */
4215 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4216
4217 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE)
4218 ixgbe_scrub_vfta(adapter, i);
4219 }
4220
4221 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
4222 {
4223 u16 vid = 1;
4224
4225 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
4226
4227 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
4228 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
4229 }
4230
4231 /**
4232 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4233 * @netdev: network interface device structure
4234 *
4235 * Writes multicast address list to the MTA hash table.
4236 * Returns: -ENOMEM on failure
4237 * 0 on no addresses written
4238 * X on writing X addresses to MTA
4239 **/
4240 static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4241 {
4242 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4243 struct ixgbe_hw *hw = &adapter->hw;
4244
4245 if (!netif_running(netdev))
4246 return 0;
4247
4248 if (hw->mac.ops.update_mc_addr_list)
4249 hw->mac.ops.update_mc_addr_list(hw, netdev);
4250 else
4251 return -ENOMEM;
4252
4253 #ifdef CONFIG_PCI_IOV
4254 ixgbe_restore_vf_multicasts(adapter);
4255 #endif
4256
4257 return netdev_mc_count(netdev);
4258 }
4259
4260 #ifdef CONFIG_PCI_IOV
4261 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4262 {
4263 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4264 struct ixgbe_hw *hw = &adapter->hw;
4265 int i;
4266
4267 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4268 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4269
4270 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4271 hw->mac.ops.set_rar(hw, i,
4272 mac_table->addr,
4273 mac_table->pool,
4274 IXGBE_RAH_AV);
4275 else
4276 hw->mac.ops.clear_rar(hw, i);
4277 }
4278 }
4279
4280 #endif
4281 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4282 {
4283 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4284 struct ixgbe_hw *hw = &adapter->hw;
4285 int i;
4286
4287 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4288 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4289 continue;
4290
4291 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4292
4293 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4294 hw->mac.ops.set_rar(hw, i,
4295 mac_table->addr,
4296 mac_table->pool,
4297 IXGBE_RAH_AV);
4298 else
4299 hw->mac.ops.clear_rar(hw, i);
4300 }
4301 }
4302
4303 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4304 {
4305 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4306 struct ixgbe_hw *hw = &adapter->hw;
4307 int i;
4308
4309 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4310 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4311 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4312 }
4313
4314 ixgbe_sync_mac_table(adapter);
4315 }
4316
4317 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
4318 {
4319 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4320 struct ixgbe_hw *hw = &adapter->hw;
4321 int i, count = 0;
4322
4323 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4324 /* do not count default RAR as available */
4325 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4326 continue;
4327
4328 /* only count unused and addresses that belong to us */
4329 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4330 if (mac_table->pool != pool)
4331 continue;
4332 }
4333
4334 count++;
4335 }
4336
4337 return count;
4338 }
4339
4340 /* this function destroys the first RAR entry */
4341 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
4342 {
4343 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4344 struct ixgbe_hw *hw = &adapter->hw;
4345
4346 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4347 mac_table->pool = VMDQ_P(0);
4348
4349 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4350
4351 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
4352 IXGBE_RAH_AV);
4353 }
4354
4355 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4356 const u8 *addr, u16 pool)
4357 {
4358 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4359 struct ixgbe_hw *hw = &adapter->hw;
4360 int i;
4361
4362 if (is_zero_ether_addr(addr))
4363 return -EINVAL;
4364
4365 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4366 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4367 continue;
4368
4369 ether_addr_copy(mac_table->addr, addr);
4370 mac_table->pool = pool;
4371
4372 mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4373 IXGBE_MAC_STATE_IN_USE;
4374
4375 ixgbe_sync_mac_table(adapter);
4376
4377 return i;
4378 }
4379
4380 return -ENOMEM;
4381 }
4382
4383 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4384 const u8 *addr, u16 pool)
4385 {
4386 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4387 struct ixgbe_hw *hw = &adapter->hw;
4388 int i;
4389
4390 if (is_zero_ether_addr(addr))
4391 return -EINVAL;
4392
4393 /* search table for addr, if found clear IN_USE flag and sync */
4394 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4395 /* we can only delete an entry if it is in use */
4396 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4397 continue;
4398 /* we only care about entries that belong to the given pool */
4399 if (mac_table->pool != pool)
4400 continue;
4401 /* we only care about a specific MAC address */
4402 if (!ether_addr_equal(addr, mac_table->addr))
4403 continue;
4404
4405 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4406 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4407
4408 ixgbe_sync_mac_table(adapter);
4409
4410 return 0;
4411 }
4412
4413 return -ENOMEM;
4414 }
4415 /**
4416 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4417 * @netdev: network interface device structure
4418 *
4419 * Writes unicast address list to the RAR table.
4420 * Returns: -ENOMEM on failure/insufficient address space
4421 * 0 on no addresses written
4422 * X on writing X addresses to the RAR table
4423 **/
4424 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
4425 {
4426 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4427 int count = 0;
4428
4429 /* return ENOMEM indicating insufficient memory for addresses */
4430 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn))
4431 return -ENOMEM;
4432
4433 if (!netdev_uc_empty(netdev)) {
4434 struct netdev_hw_addr *ha;
4435 netdev_for_each_uc_addr(ha, netdev) {
4436 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4437 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
4438 count++;
4439 }
4440 }
4441 return count;
4442 }
4443
4444 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4445 {
4446 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4447 int ret;
4448
4449 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4450
4451 return min_t(int, ret, 0);
4452 }
4453
4454 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4455 {
4456 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4457
4458 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4459
4460 return 0;
4461 }
4462
4463 /**
4464 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
4465 * @netdev: network interface device structure
4466 *
4467 * The set_rx_method entry point is called whenever the unicast/multicast
4468 * address list or the network interface flags are updated. This routine is
4469 * responsible for configuring the hardware for proper unicast, multicast and
4470 * promiscuous mode.
4471 **/
4472 void ixgbe_set_rx_mode(struct net_device *netdev)
4473 {
4474 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4475 struct ixgbe_hw *hw = &adapter->hw;
4476 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
4477 netdev_features_t features = netdev->features;
4478 int count;
4479
4480 /* Check for Promiscuous and All Multicast modes */
4481 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4482
4483 /* set all bits that we expect to always be set */
4484 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
4485 fctrl |= IXGBE_FCTRL_BAM;
4486 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4487 fctrl |= IXGBE_FCTRL_PMCF;
4488
4489 /* clear the bits we are changing the status of */
4490 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4491 if (netdev->flags & IFF_PROMISC) {
4492 hw->addr_ctrl.user_set_promisc = true;
4493 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4494 vmolr |= IXGBE_VMOLR_MPE;
4495 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4496 } else {
4497 if (netdev->flags & IFF_ALLMULTI) {
4498 fctrl |= IXGBE_FCTRL_MPE;
4499 vmolr |= IXGBE_VMOLR_MPE;
4500 }
4501 hw->addr_ctrl.user_set_promisc = false;
4502 }
4503
4504 /*
4505 * Write addresses to available RAR registers, if there is not
4506 * sufficient space to store all the addresses then enable
4507 * unicast promiscuous mode
4508 */
4509 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
4510 fctrl |= IXGBE_FCTRL_UPE;
4511 vmolr |= IXGBE_VMOLR_ROPE;
4512 }
4513
4514 /* Write addresses to the MTA, if the attempt fails
4515 * then we should just turn on promiscuous mode so
4516 * that we can at least receive multicast traffic
4517 */
4518 count = ixgbe_write_mc_addr_list(netdev);
4519 if (count < 0) {
4520 fctrl |= IXGBE_FCTRL_MPE;
4521 vmolr |= IXGBE_VMOLR_MPE;
4522 } else if (count) {
4523 vmolr |= IXGBE_VMOLR_ROMPE;
4524 }
4525
4526 if (hw->mac.type != ixgbe_mac_82598EB) {
4527 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
4528 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4529 IXGBE_VMOLR_ROPE);
4530 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
4531 }
4532
4533 /* This is useful for sniffing bad packets. */
4534 if (features & NETIF_F_RXALL) {
4535 /* UPE and MPE will be handled by normal PROMISC logic
4536 * in e1000e_set_rx_mode */
4537 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4538 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4539 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4540
4541 fctrl &= ~(IXGBE_FCTRL_DPF);
4542 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4543 }
4544
4545 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4546
4547 if (features & NETIF_F_HW_VLAN_CTAG_RX)
4548 ixgbe_vlan_strip_enable(adapter);
4549 else
4550 ixgbe_vlan_strip_disable(adapter);
4551
4552 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
4553 ixgbe_vlan_promisc_disable(adapter);
4554 else
4555 ixgbe_vlan_promisc_enable(adapter);
4556 }
4557
4558 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4559 {
4560 int q_idx;
4561
4562 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4563 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
4564 napi_enable(&adapter->q_vector[q_idx]->napi);
4565 }
4566 }
4567
4568 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4569 {
4570 int q_idx;
4571
4572 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4573 napi_disable(&adapter->q_vector[q_idx]->napi);
4574 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
4575 pr_info("QV %d locked\n", q_idx);
4576 usleep_range(1000, 20000);
4577 }
4578 }
4579 }
4580
4581 static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter)
4582 {
4583 switch (adapter->hw.mac.type) {
4584 case ixgbe_mac_X550:
4585 case ixgbe_mac_X550EM_x:
4586 case ixgbe_mac_x550em_a:
4587 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0);
4588 adapter->vxlan_port = 0;
4589 break;
4590 default:
4591 break;
4592 }
4593 }
4594
4595 #ifdef CONFIG_IXGBE_DCB
4596 /**
4597 * ixgbe_configure_dcb - Configure DCB hardware
4598 * @adapter: ixgbe adapter struct
4599 *
4600 * This is called by the driver on open to configure the DCB hardware.
4601 * This is also called by the gennetlink interface when reconfiguring
4602 * the DCB state.
4603 */
4604 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4605 {
4606 struct ixgbe_hw *hw = &adapter->hw;
4607 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4608
4609 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4610 if (hw->mac.type == ixgbe_mac_82598EB)
4611 netif_set_gso_max_size(adapter->netdev, 65536);
4612 return;
4613 }
4614
4615 if (hw->mac.type == ixgbe_mac_82598EB)
4616 netif_set_gso_max_size(adapter->netdev, 32768);
4617
4618 #ifdef IXGBE_FCOE
4619 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4620 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
4621 #endif
4622
4623 /* reconfigure the hardware */
4624 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
4625 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4626 DCB_TX_CONFIG);
4627 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4628 DCB_RX_CONFIG);
4629 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
4630 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4631 ixgbe_dcb_hw_ets(&adapter->hw,
4632 adapter->ixgbe_ieee_ets,
4633 max_frame);
4634 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4635 adapter->ixgbe_ieee_pfc->pfc_en,
4636 adapter->ixgbe_ieee_ets->prio_tc);
4637 }
4638
4639 /* Enable RSS Hash per TC */
4640 if (hw->mac.type != ixgbe_mac_82598EB) {
4641 u32 msb = 0;
4642 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
4643
4644 while (rss_i) {
4645 msb++;
4646 rss_i >>= 1;
4647 }
4648
4649 /* write msb to all 8 TCs in one write */
4650 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
4651 }
4652 }
4653 #endif
4654
4655 /* Additional bittime to account for IXGBE framing */
4656 #define IXGBE_ETH_FRAMING 20
4657
4658 /**
4659 * ixgbe_hpbthresh - calculate high water mark for flow control
4660 *
4661 * @adapter: board private structure to calculate for
4662 * @pb: packet buffer to calculate
4663 */
4664 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4665 {
4666 struct ixgbe_hw *hw = &adapter->hw;
4667 struct net_device *dev = adapter->netdev;
4668 int link, tc, kb, marker;
4669 u32 dv_id, rx_pba;
4670
4671 /* Calculate max LAN frame size */
4672 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4673
4674 #ifdef IXGBE_FCOE
4675 /* FCoE traffic class uses FCOE jumbo frames */
4676 if ((dev->features & NETIF_F_FCOE_MTU) &&
4677 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4678 (pb == ixgbe_fcoe_get_tc(adapter)))
4679 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4680 #endif
4681
4682 /* Calculate delay value for device */
4683 switch (hw->mac.type) {
4684 case ixgbe_mac_X540:
4685 case ixgbe_mac_X550:
4686 case ixgbe_mac_X550EM_x:
4687 case ixgbe_mac_x550em_a:
4688 dv_id = IXGBE_DV_X540(link, tc);
4689 break;
4690 default:
4691 dv_id = IXGBE_DV(link, tc);
4692 break;
4693 }
4694
4695 /* Loopback switch introduces additional latency */
4696 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4697 dv_id += IXGBE_B2BT(tc);
4698
4699 /* Delay value is calculated in bit times convert to KB */
4700 kb = IXGBE_BT2KB(dv_id);
4701 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4702
4703 marker = rx_pba - kb;
4704
4705 /* It is possible that the packet buffer is not large enough
4706 * to provide required headroom. In this case throw an error
4707 * to user and a do the best we can.
4708 */
4709 if (marker < 0) {
4710 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4711 "headroom to support flow control."
4712 "Decrease MTU or number of traffic classes\n", pb);
4713 marker = tc + 1;
4714 }
4715
4716 return marker;
4717 }
4718
4719 /**
4720 * ixgbe_lpbthresh - calculate low water mark for for flow control
4721 *
4722 * @adapter: board private structure to calculate for
4723 * @pb: packet buffer to calculate
4724 */
4725 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
4726 {
4727 struct ixgbe_hw *hw = &adapter->hw;
4728 struct net_device *dev = adapter->netdev;
4729 int tc;
4730 u32 dv_id;
4731
4732 /* Calculate max LAN frame size */
4733 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4734
4735 #ifdef IXGBE_FCOE
4736 /* FCoE traffic class uses FCOE jumbo frames */
4737 if ((dev->features & NETIF_F_FCOE_MTU) &&
4738 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4739 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4740 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4741 #endif
4742
4743 /* Calculate delay value for device */
4744 switch (hw->mac.type) {
4745 case ixgbe_mac_X540:
4746 case ixgbe_mac_X550:
4747 case ixgbe_mac_X550EM_x:
4748 case ixgbe_mac_x550em_a:
4749 dv_id = IXGBE_LOW_DV_X540(tc);
4750 break;
4751 default:
4752 dv_id = IXGBE_LOW_DV(tc);
4753 break;
4754 }
4755
4756 /* Delay value is calculated in bit times convert to KB */
4757 return IXGBE_BT2KB(dv_id);
4758 }
4759
4760 /*
4761 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4762 */
4763 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4764 {
4765 struct ixgbe_hw *hw = &adapter->hw;
4766 int num_tc = netdev_get_num_tc(adapter->netdev);
4767 int i;
4768
4769 if (!num_tc)
4770 num_tc = 1;
4771
4772 for (i = 0; i < num_tc; i++) {
4773 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4774 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
4775
4776 /* Low water marks must not be larger than high water marks */
4777 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4778 hw->fc.low_water[i] = 0;
4779 }
4780
4781 for (; i < MAX_TRAFFIC_CLASS; i++)
4782 hw->fc.high_water[i] = 0;
4783 }
4784
4785 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4786 {
4787 struct ixgbe_hw *hw = &adapter->hw;
4788 int hdrm;
4789 u8 tc = netdev_get_num_tc(adapter->netdev);
4790
4791 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4792 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4793 hdrm = 32 << adapter->fdir_pballoc;
4794 else
4795 hdrm = 0;
4796
4797 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
4798 ixgbe_pbthresh_setup(adapter);
4799 }
4800
4801 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4802 {
4803 struct ixgbe_hw *hw = &adapter->hw;
4804 struct hlist_node *node2;
4805 struct ixgbe_fdir_filter *filter;
4806
4807 spin_lock(&adapter->fdir_perfect_lock);
4808
4809 if (!hlist_empty(&adapter->fdir_filter_list))
4810 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4811
4812 hlist_for_each_entry_safe(filter, node2,
4813 &adapter->fdir_filter_list, fdir_node) {
4814 ixgbe_fdir_write_perfect_filter_82599(hw,
4815 &filter->filter,
4816 filter->sw_idx,
4817 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4818 IXGBE_FDIR_DROP_QUEUE :
4819 adapter->rx_ring[filter->action]->reg_idx);
4820 }
4821
4822 spin_unlock(&adapter->fdir_perfect_lock);
4823 }
4824
4825 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4826 struct ixgbe_adapter *adapter)
4827 {
4828 struct ixgbe_hw *hw = &adapter->hw;
4829 u32 vmolr;
4830
4831 /* No unicast promiscuous support for VMDQ devices. */
4832 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4833 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4834
4835 /* clear the affected bit */
4836 vmolr &= ~IXGBE_VMOLR_MPE;
4837
4838 if (dev->flags & IFF_ALLMULTI) {
4839 vmolr |= IXGBE_VMOLR_MPE;
4840 } else {
4841 vmolr |= IXGBE_VMOLR_ROMPE;
4842 hw->mac.ops.update_mc_addr_list(hw, dev);
4843 }
4844 ixgbe_write_uc_addr_list(adapter->netdev, pool);
4845 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4846 }
4847
4848 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4849 {
4850 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4851 int rss_i = adapter->num_rx_queues_per_pool;
4852 struct ixgbe_hw *hw = &adapter->hw;
4853 u16 pool = vadapter->pool;
4854 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4855 IXGBE_PSRTYPE_UDPHDR |
4856 IXGBE_PSRTYPE_IPV4HDR |
4857 IXGBE_PSRTYPE_L2HDR |
4858 IXGBE_PSRTYPE_IPV6HDR;
4859
4860 if (hw->mac.type == ixgbe_mac_82598EB)
4861 return;
4862
4863 if (rss_i > 3)
4864 psrtype |= 2 << 29;
4865 else if (rss_i > 1)
4866 psrtype |= 1 << 29;
4867
4868 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4869 }
4870
4871 /**
4872 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4873 * @rx_ring: ring to free buffers from
4874 **/
4875 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4876 {
4877 struct device *dev = rx_ring->dev;
4878 unsigned long size;
4879 u16 i;
4880
4881 /* ring already cleared, nothing to do */
4882 if (!rx_ring->rx_buffer_info)
4883 return;
4884
4885 /* Free all the Rx ring sk_buffs */
4886 for (i = 0; i < rx_ring->count; i++) {
4887 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
4888
4889 if (rx_buffer->skb) {
4890 struct sk_buff *skb = rx_buffer->skb;
4891 if (IXGBE_CB(skb)->page_released)
4892 dma_unmap_page(dev,
4893 IXGBE_CB(skb)->dma,
4894 ixgbe_rx_bufsz(rx_ring),
4895 DMA_FROM_DEVICE);
4896 dev_kfree_skb(skb);
4897 rx_buffer->skb = NULL;
4898 }
4899
4900 if (!rx_buffer->page)
4901 continue;
4902
4903 dma_unmap_page(dev, rx_buffer->dma,
4904 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4905 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4906
4907 rx_buffer->page = NULL;
4908 }
4909
4910 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4911 memset(rx_ring->rx_buffer_info, 0, size);
4912
4913 /* Zero out the descriptor ring */
4914 memset(rx_ring->desc, 0, rx_ring->size);
4915
4916 rx_ring->next_to_alloc = 0;
4917 rx_ring->next_to_clean = 0;
4918 rx_ring->next_to_use = 0;
4919 }
4920
4921 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4922 struct ixgbe_ring *rx_ring)
4923 {
4924 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4925 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4926
4927 /* shutdown specific queue receive and wait for dma to settle */
4928 ixgbe_disable_rx_queue(adapter, rx_ring);
4929 usleep_range(10000, 20000);
4930 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4931 ixgbe_clean_rx_ring(rx_ring);
4932 rx_ring->l2_accel_priv = NULL;
4933 }
4934
4935 static int ixgbe_fwd_ring_down(struct net_device *vdev,
4936 struct ixgbe_fwd_adapter *accel)
4937 {
4938 struct ixgbe_adapter *adapter = accel->real_adapter;
4939 unsigned int rxbase = accel->rx_base_queue;
4940 unsigned int txbase = accel->tx_base_queue;
4941 int i;
4942
4943 netif_tx_stop_all_queues(vdev);
4944
4945 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4946 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4947 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4948 }
4949
4950 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4951 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4952 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4953 }
4954
4955
4956 return 0;
4957 }
4958
4959 static int ixgbe_fwd_ring_up(struct net_device *vdev,
4960 struct ixgbe_fwd_adapter *accel)
4961 {
4962 struct ixgbe_adapter *adapter = accel->real_adapter;
4963 unsigned int rxbase, txbase, queues;
4964 int i, baseq, err = 0;
4965
4966 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4967 return 0;
4968
4969 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4970 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4971 accel->pool, adapter->num_rx_pools,
4972 baseq, baseq + adapter->num_rx_queues_per_pool,
4973 adapter->fwd_bitmask);
4974
4975 accel->netdev = vdev;
4976 accel->rx_base_queue = rxbase = baseq;
4977 accel->tx_base_queue = txbase = baseq;
4978
4979 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4980 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4981
4982 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4983 adapter->rx_ring[rxbase + i]->netdev = vdev;
4984 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4985 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4986 }
4987
4988 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4989 adapter->tx_ring[txbase + i]->netdev = vdev;
4990 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4991 }
4992
4993 queues = min_t(unsigned int,
4994 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4995 err = netif_set_real_num_tx_queues(vdev, queues);
4996 if (err)
4997 goto fwd_queue_err;
4998
4999 err = netif_set_real_num_rx_queues(vdev, queues);
5000 if (err)
5001 goto fwd_queue_err;
5002
5003 if (is_valid_ether_addr(vdev->dev_addr))
5004 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
5005
5006 ixgbe_fwd_psrtype(accel);
5007 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
5008 return err;
5009 fwd_queue_err:
5010 ixgbe_fwd_ring_down(vdev, accel);
5011 return err;
5012 }
5013
5014 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
5015 {
5016 struct net_device *upper;
5017 struct list_head *iter;
5018 int err;
5019
5020 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5021 if (netif_is_macvlan(upper)) {
5022 struct macvlan_dev *dfwd = netdev_priv(upper);
5023 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
5024
5025 if (dfwd->fwd_priv) {
5026 err = ixgbe_fwd_ring_up(upper, vadapter);
5027 if (err)
5028 continue;
5029 }
5030 }
5031 }
5032 }
5033
5034 static void ixgbe_configure(struct ixgbe_adapter *adapter)
5035 {
5036 struct ixgbe_hw *hw = &adapter->hw;
5037
5038 ixgbe_configure_pb(adapter);
5039 #ifdef CONFIG_IXGBE_DCB
5040 ixgbe_configure_dcb(adapter);
5041 #endif
5042 /*
5043 * We must restore virtualization before VLANs or else
5044 * the VLVF registers will not be populated
5045 */
5046 ixgbe_configure_virtualization(adapter);
5047
5048 ixgbe_set_rx_mode(adapter->netdev);
5049 ixgbe_restore_vlan(adapter);
5050
5051 switch (hw->mac.type) {
5052 case ixgbe_mac_82599EB:
5053 case ixgbe_mac_X540:
5054 hw->mac.ops.disable_rx_buff(hw);
5055 break;
5056 default:
5057 break;
5058 }
5059
5060 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5061 ixgbe_init_fdir_signature_82599(&adapter->hw,
5062 adapter->fdir_pballoc);
5063 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
5064 ixgbe_init_fdir_perfect_82599(&adapter->hw,
5065 adapter->fdir_pballoc);
5066 ixgbe_fdir_filter_restore(adapter);
5067 }
5068
5069 switch (hw->mac.type) {
5070 case ixgbe_mac_82599EB:
5071 case ixgbe_mac_X540:
5072 hw->mac.ops.enable_rx_buff(hw);
5073 break;
5074 default:
5075 break;
5076 }
5077
5078 #ifdef CONFIG_IXGBE_DCA
5079 /* configure DCA */
5080 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
5081 ixgbe_setup_dca(adapter);
5082 #endif /* CONFIG_IXGBE_DCA */
5083
5084 #ifdef IXGBE_FCOE
5085 /* configure FCoE L2 filters, redirection table, and Rx control */
5086 ixgbe_configure_fcoe(adapter);
5087
5088 #endif /* IXGBE_FCOE */
5089 ixgbe_configure_tx(adapter);
5090 ixgbe_configure_rx(adapter);
5091 ixgbe_configure_dfwd(adapter);
5092 }
5093
5094 /**
5095 * ixgbe_sfp_link_config - set up SFP+ link
5096 * @adapter: pointer to private adapter struct
5097 **/
5098 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
5099 {
5100 /*
5101 * We are assuming the worst case scenario here, and that
5102 * is that an SFP was inserted/removed after the reset
5103 * but before SFP detection was enabled. As such the best
5104 * solution is to just start searching as soon as we start
5105 */
5106 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5107 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5108
5109 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5110 adapter->sfp_poll_time = 0;
5111 }
5112
5113 /**
5114 * ixgbe_non_sfp_link_config - set up non-SFP+ link
5115 * @hw: pointer to private hardware struct
5116 *
5117 * Returns 0 on success, negative on failure
5118 **/
5119 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
5120 {
5121 u32 speed;
5122 bool autoneg, link_up = false;
5123 int ret = IXGBE_ERR_LINK_SETUP;
5124
5125 if (hw->mac.ops.check_link)
5126 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
5127
5128 if (ret)
5129 return ret;
5130
5131 speed = hw->phy.autoneg_advertised;
5132 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5133 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
5134 &autoneg);
5135 if (ret)
5136 return ret;
5137
5138 if (hw->mac.ops.setup_link)
5139 ret = hw->mac.ops.setup_link(hw, speed, link_up);
5140
5141 return ret;
5142 }
5143
5144 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
5145 {
5146 struct ixgbe_hw *hw = &adapter->hw;
5147 u32 gpie = 0;
5148
5149 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5150 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5151 IXGBE_GPIE_OCD;
5152 gpie |= IXGBE_GPIE_EIAME;
5153 /*
5154 * use EIAM to auto-mask when MSI-X interrupt is asserted
5155 * this saves a register write for every interrupt
5156 */
5157 switch (hw->mac.type) {
5158 case ixgbe_mac_82598EB:
5159 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5160 break;
5161 case ixgbe_mac_82599EB:
5162 case ixgbe_mac_X540:
5163 case ixgbe_mac_X550:
5164 case ixgbe_mac_X550EM_x:
5165 case ixgbe_mac_x550em_a:
5166 default:
5167 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5168 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5169 break;
5170 }
5171 } else {
5172 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
5173 * specifically only auto mask tx and rx interrupts */
5174 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5175 }
5176
5177 /* XXX: to interrupt immediately for EICS writes, enable this */
5178 /* gpie |= IXGBE_GPIE_EIMEN; */
5179
5180 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
5181 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
5182
5183 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
5184 case IXGBE_82599_VMDQ_8Q_MASK:
5185 gpie |= IXGBE_GPIE_VTMODE_16;
5186 break;
5187 case IXGBE_82599_VMDQ_4Q_MASK:
5188 gpie |= IXGBE_GPIE_VTMODE_32;
5189 break;
5190 default:
5191 gpie |= IXGBE_GPIE_VTMODE_64;
5192 break;
5193 }
5194 }
5195
5196 /* Enable Thermal over heat sensor interrupt */
5197 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
5198 switch (adapter->hw.mac.type) {
5199 case ixgbe_mac_82599EB:
5200 gpie |= IXGBE_SDP0_GPIEN_8259X;
5201 break;
5202 default:
5203 break;
5204 }
5205 }
5206
5207 /* Enable fan failure interrupt */
5208 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
5209 gpie |= IXGBE_SDP1_GPIEN(hw);
5210
5211 switch (hw->mac.type) {
5212 case ixgbe_mac_82599EB:
5213 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
5214 break;
5215 case ixgbe_mac_X550EM_x:
5216 case ixgbe_mac_x550em_a:
5217 gpie |= IXGBE_SDP0_GPIEN_X540;
5218 break;
5219 default:
5220 break;
5221 }
5222
5223 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5224 }
5225
5226 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
5227 {
5228 struct ixgbe_hw *hw = &adapter->hw;
5229 int err;
5230 u32 ctrl_ext;
5231
5232 ixgbe_get_hw_control(adapter);
5233 ixgbe_setup_gpie(adapter);
5234
5235 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5236 ixgbe_configure_msix(adapter);
5237 else
5238 ixgbe_configure_msi_and_legacy(adapter);
5239
5240 /* enable the optics for 82599 SFP+ fiber */
5241 if (hw->mac.ops.enable_tx_laser)
5242 hw->mac.ops.enable_tx_laser(hw);
5243
5244 if (hw->phy.ops.set_phy_power)
5245 hw->phy.ops.set_phy_power(hw, true);
5246
5247 smp_mb__before_atomic();
5248 clear_bit(__IXGBE_DOWN, &adapter->state);
5249 ixgbe_napi_enable_all(adapter);
5250
5251 if (ixgbe_is_sfp(hw)) {
5252 ixgbe_sfp_link_config(adapter);
5253 } else {
5254 err = ixgbe_non_sfp_link_config(hw);
5255 if (err)
5256 e_err(probe, "link_config FAILED %d\n", err);
5257 }
5258
5259 /* clear any pending interrupts, may auto mask */
5260 IXGBE_READ_REG(hw, IXGBE_EICR);
5261 ixgbe_irq_enable(adapter, true, true);
5262
5263 /*
5264 * If this adapter has a fan, check to see if we had a failure
5265 * before we enabled the interrupt.
5266 */
5267 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5268 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5269 if (esdp & IXGBE_ESDP_SDP1)
5270 e_crit(drv, "Fan has stopped, replace the adapter\n");
5271 }
5272
5273 /* bring the link up in the watchdog, this could race with our first
5274 * link up interrupt but shouldn't be a problem */
5275 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5276 adapter->link_check_timeout = jiffies;
5277 mod_timer(&adapter->service_timer, jiffies);
5278
5279 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5280 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5281 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5282 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
5283 }
5284
5285 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5286 {
5287 WARN_ON(in_interrupt());
5288 /* put off any impending NetWatchDogTimeout */
5289 adapter->netdev->trans_start = jiffies;
5290
5291 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
5292 usleep_range(1000, 2000);
5293 ixgbe_down(adapter);
5294 /*
5295 * If SR-IOV enabled then wait a bit before bringing the adapter
5296 * back up to give the VFs time to respond to the reset. The
5297 * two second wait is based upon the watchdog timer cycle in
5298 * the VF driver.
5299 */
5300 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5301 msleep(2000);
5302 ixgbe_up(adapter);
5303 clear_bit(__IXGBE_RESETTING, &adapter->state);
5304 }
5305
5306 void ixgbe_up(struct ixgbe_adapter *adapter)
5307 {
5308 /* hardware has been reset, we need to reload some things */
5309 ixgbe_configure(adapter);
5310
5311 ixgbe_up_complete(adapter);
5312 }
5313
5314 void ixgbe_reset(struct ixgbe_adapter *adapter)
5315 {
5316 struct ixgbe_hw *hw = &adapter->hw;
5317 struct net_device *netdev = adapter->netdev;
5318 int err;
5319
5320 if (ixgbe_removed(hw->hw_addr))
5321 return;
5322 /* lock SFP init bit to prevent race conditions with the watchdog */
5323 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5324 usleep_range(1000, 2000);
5325
5326 /* clear all SFP and link config related flags while holding SFP_INIT */
5327 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5328 IXGBE_FLAG2_SFP_NEEDS_RESET);
5329 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5330
5331 err = hw->mac.ops.init_hw(hw);
5332 switch (err) {
5333 case 0:
5334 case IXGBE_ERR_SFP_NOT_PRESENT:
5335 case IXGBE_ERR_SFP_NOT_SUPPORTED:
5336 break;
5337 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
5338 e_dev_err("master disable timed out\n");
5339 break;
5340 case IXGBE_ERR_EEPROM_VERSION:
5341 /* We are running on a pre-production device, log a warning */
5342 e_dev_warn("This device is a pre-production adapter/LOM. "
5343 "Please be aware there may be issues associated with "
5344 "your hardware. If you are experiencing problems "
5345 "please contact your Intel or hardware "
5346 "representative who provided you with this "
5347 "hardware.\n");
5348 break;
5349 default:
5350 e_dev_err("Hardware Error: %d\n", err);
5351 }
5352
5353 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5354
5355 /* flush entries out of MAC table */
5356 ixgbe_flush_sw_mac_table(adapter);
5357 __dev_uc_unsync(netdev, NULL);
5358
5359 /* do not flush user set addresses */
5360 ixgbe_mac_set_default_filter(adapter);
5361
5362 /* update SAN MAC vmdq pool selection */
5363 if (hw->mac.san_mac_rar_index)
5364 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
5365
5366 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
5367 ixgbe_ptp_reset(adapter);
5368
5369 if (hw->phy.ops.set_phy_power) {
5370 if (!netif_running(adapter->netdev) && !adapter->wol)
5371 hw->phy.ops.set_phy_power(hw, false);
5372 else
5373 hw->phy.ops.set_phy_power(hw, true);
5374 }
5375 }
5376
5377 /**
5378 * ixgbe_clean_tx_ring - Free Tx Buffers
5379 * @tx_ring: ring to be cleaned
5380 **/
5381 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
5382 {
5383 struct ixgbe_tx_buffer *tx_buffer_info;
5384 unsigned long size;
5385 u16 i;
5386
5387 /* ring already cleared, nothing to do */
5388 if (!tx_ring->tx_buffer_info)
5389 return;
5390
5391 /* Free all the Tx ring sk_buffs */
5392 for (i = 0; i < tx_ring->count; i++) {
5393 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5394 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
5395 }
5396
5397 netdev_tx_reset_queue(txring_txq(tx_ring));
5398
5399 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5400 memset(tx_ring->tx_buffer_info, 0, size);
5401
5402 /* Zero out the descriptor ring */
5403 memset(tx_ring->desc, 0, tx_ring->size);
5404
5405 tx_ring->next_to_use = 0;
5406 tx_ring->next_to_clean = 0;
5407 }
5408
5409 /**
5410 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
5411 * @adapter: board private structure
5412 **/
5413 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
5414 {
5415 int i;
5416
5417 for (i = 0; i < adapter->num_rx_queues; i++)
5418 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
5419 }
5420
5421 /**
5422 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
5423 * @adapter: board private structure
5424 **/
5425 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
5426 {
5427 int i;
5428
5429 for (i = 0; i < adapter->num_tx_queues; i++)
5430 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
5431 }
5432
5433 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5434 {
5435 struct hlist_node *node2;
5436 struct ixgbe_fdir_filter *filter;
5437
5438 spin_lock(&adapter->fdir_perfect_lock);
5439
5440 hlist_for_each_entry_safe(filter, node2,
5441 &adapter->fdir_filter_list, fdir_node) {
5442 hlist_del(&filter->fdir_node);
5443 kfree(filter);
5444 }
5445 adapter->fdir_filter_count = 0;
5446
5447 spin_unlock(&adapter->fdir_perfect_lock);
5448 }
5449
5450 void ixgbe_down(struct ixgbe_adapter *adapter)
5451 {
5452 struct net_device *netdev = adapter->netdev;
5453 struct ixgbe_hw *hw = &adapter->hw;
5454 struct net_device *upper;
5455 struct list_head *iter;
5456 int i;
5457
5458 /* signal that we are down to the interrupt handler */
5459 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5460 return; /* do nothing if already down */
5461
5462 /* disable receives */
5463 hw->mac.ops.disable_rx(hw);
5464
5465 /* disable all enabled rx queues */
5466 for (i = 0; i < adapter->num_rx_queues; i++)
5467 /* this call also flushes the previous write */
5468 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5469
5470 usleep_range(10000, 20000);
5471
5472 netif_tx_stop_all_queues(netdev);
5473
5474 /* call carrier off first to avoid false dev_watchdog timeouts */
5475 netif_carrier_off(netdev);
5476 netif_tx_disable(netdev);
5477
5478 /* disable any upper devices */
5479 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5480 if (netif_is_macvlan(upper)) {
5481 struct macvlan_dev *vlan = netdev_priv(upper);
5482
5483 if (vlan->fwd_priv) {
5484 netif_tx_stop_all_queues(upper);
5485 netif_carrier_off(upper);
5486 netif_tx_disable(upper);
5487 }
5488 }
5489 }
5490
5491 ixgbe_irq_disable(adapter);
5492
5493 ixgbe_napi_disable_all(adapter);
5494
5495 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5496 IXGBE_FLAG2_RESET_REQUESTED);
5497 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5498
5499 del_timer_sync(&adapter->service_timer);
5500
5501 if (adapter->num_vfs) {
5502 /* Clear EITR Select mapping */
5503 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
5504
5505 /* Mark all the VFs as inactive */
5506 for (i = 0 ; i < adapter->num_vfs; i++)
5507 adapter->vfinfo[i].clear_to_send = false;
5508
5509 /* ping all the active vfs to let them know we are going down */
5510 ixgbe_ping_all_vfs(adapter);
5511
5512 /* Disable all VFTE/VFRE TX/RX */
5513 ixgbe_disable_tx_rx(adapter);
5514 }
5515
5516 /* disable transmits in the hardware now that interrupts are off */
5517 for (i = 0; i < adapter->num_tx_queues; i++) {
5518 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
5519 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5520 }
5521
5522 /* Disable the Tx DMA engine on 82599 and later MAC */
5523 switch (hw->mac.type) {
5524 case ixgbe_mac_82599EB:
5525 case ixgbe_mac_X540:
5526 case ixgbe_mac_X550:
5527 case ixgbe_mac_X550EM_x:
5528 case ixgbe_mac_x550em_a:
5529 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
5530 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5531 ~IXGBE_DMATXCTL_TE));
5532 break;
5533 default:
5534 break;
5535 }
5536
5537 if (!pci_channel_offline(adapter->pdev))
5538 ixgbe_reset(adapter);
5539
5540 /* power down the optics for 82599 SFP+ fiber */
5541 if (hw->mac.ops.disable_tx_laser)
5542 hw->mac.ops.disable_tx_laser(hw);
5543
5544 ixgbe_clean_all_tx_rings(adapter);
5545 ixgbe_clean_all_rx_rings(adapter);
5546 }
5547
5548 /**
5549 * ixgbe_tx_timeout - Respond to a Tx Hang
5550 * @netdev: network interface device structure
5551 **/
5552 static void ixgbe_tx_timeout(struct net_device *netdev)
5553 {
5554 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5555
5556 /* Do the reset outside of interrupt context */
5557 ixgbe_tx_timeout_reset(adapter);
5558 }
5559
5560 /**
5561 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5562 * @adapter: board private structure to initialize
5563 *
5564 * ixgbe_sw_init initializes the Adapter private data structure.
5565 * Fields are initialized based on PCI device information and
5566 * OS network device settings (MTU size).
5567 **/
5568 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
5569 {
5570 struct ixgbe_hw *hw = &adapter->hw;
5571 struct pci_dev *pdev = adapter->pdev;
5572 unsigned int rss, fdir;
5573 u32 fwsm;
5574 #ifdef CONFIG_IXGBE_DCB
5575 int j;
5576 struct tc_configuration *tc;
5577 #endif
5578
5579 /* PCI config space info */
5580
5581 hw->vendor_id = pdev->vendor;
5582 hw->device_id = pdev->device;
5583 hw->revision_id = pdev->revision;
5584 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5585 hw->subsystem_device_id = pdev->subsystem_device;
5586
5587 /* Set common capability flags and settings */
5588 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
5589 adapter->ring_feature[RING_F_RSS].limit = rss;
5590 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5591 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5592 adapter->atr_sample_rate = 20;
5593 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5594 adapter->ring_feature[RING_F_FDIR].limit = fdir;
5595 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5596 #ifdef CONFIG_IXGBE_DCA
5597 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5598 #endif
5599 #ifdef IXGBE_FCOE
5600 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5601 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5602 #ifdef CONFIG_IXGBE_DCB
5603 /* Default traffic class to use for FCoE */
5604 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5605 #endif /* CONFIG_IXGBE_DCB */
5606 #endif /* IXGBE_FCOE */
5607
5608 /* initialize static ixgbe jump table entries */
5609 adapter->jump_tables[0] = ixgbe_ipv4_fields;
5610
5611 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5612 hw->mac.num_rar_entries,
5613 GFP_ATOMIC);
5614 if (!adapter->mac_table)
5615 return -ENOMEM;
5616
5617 /* Set MAC specific capability flags and exceptions */
5618 switch (hw->mac.type) {
5619 case ixgbe_mac_82598EB:
5620 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5621
5622 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5623 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5624
5625 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
5626 adapter->ring_feature[RING_F_FDIR].limit = 0;
5627 adapter->atr_sample_rate = 0;
5628 adapter->fdir_pballoc = 0;
5629 #ifdef IXGBE_FCOE
5630 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5631 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5632 #ifdef CONFIG_IXGBE_DCB
5633 adapter->fcoe.up = 0;
5634 #endif /* IXGBE_DCB */
5635 #endif /* IXGBE_FCOE */
5636 break;
5637 case ixgbe_mac_82599EB:
5638 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5639 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5640 break;
5641 case ixgbe_mac_X540:
5642 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
5643 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5644 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5645 break;
5646 case ixgbe_mac_X550EM_x:
5647 case ixgbe_mac_x550em_a:
5648 case ixgbe_mac_X550:
5649 #ifdef CONFIG_IXGBE_DCA
5650 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
5651 #endif
5652 #ifdef CONFIG_IXGBE_VXLAN
5653 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
5654 #endif
5655 break;
5656 default:
5657 break;
5658 }
5659
5660 #ifdef IXGBE_FCOE
5661 /* FCoE support exists, always init the FCoE lock */
5662 spin_lock_init(&adapter->fcoe.lock);
5663
5664 #endif
5665 /* n-tuple support exists, always init our spinlock */
5666 spin_lock_init(&adapter->fdir_perfect_lock);
5667
5668 #ifdef CONFIG_IXGBE_DCB
5669 switch (hw->mac.type) {
5670 case ixgbe_mac_X540:
5671 case ixgbe_mac_X550:
5672 case ixgbe_mac_X550EM_x:
5673 case ixgbe_mac_x550em_a:
5674 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5675 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5676 break;
5677 default:
5678 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5679 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5680 break;
5681 }
5682
5683 /* Configure DCB traffic classes */
5684 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5685 tc = &adapter->dcb_cfg.tc_config[j];
5686 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5687 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5688 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5689 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5690 tc->dcb_pfc = pfc_disabled;
5691 }
5692
5693 /* Initialize default user to priority mapping, UPx->TC0 */
5694 tc = &adapter->dcb_cfg.tc_config[0];
5695 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5696 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5697
5698 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5699 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5700 adapter->dcb_cfg.pfc_mode_enable = false;
5701 adapter->dcb_set_bitmap = 0x00;
5702 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5703 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5704 sizeof(adapter->temp_dcb_cfg));
5705
5706 #endif
5707
5708 /* default flow control settings */
5709 hw->fc.requested_mode = ixgbe_fc_full;
5710 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5711 ixgbe_pbthresh_setup(adapter);
5712 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5713 hw->fc.send_xon = true;
5714 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
5715
5716 #ifdef CONFIG_PCI_IOV
5717 if (max_vfs > 0)
5718 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5719
5720 /* assign number of SR-IOV VFs */
5721 if (hw->mac.type != ixgbe_mac_82598EB) {
5722 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
5723 adapter->num_vfs = 0;
5724 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5725 } else {
5726 adapter->num_vfs = max_vfs;
5727 }
5728 }
5729 #endif /* CONFIG_PCI_IOV */
5730
5731 /* enable itr by default in dynamic mode */
5732 adapter->rx_itr_setting = 1;
5733 adapter->tx_itr_setting = 1;
5734
5735 /* set default ring sizes */
5736 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5737 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5738
5739 /* set default work limits */
5740 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5741
5742 /* initialize eeprom parameters */
5743 if (ixgbe_init_eeprom_params_generic(hw)) {
5744 e_dev_err("EEPROM initialization failed\n");
5745 return -EIO;
5746 }
5747
5748 /* PF holds first pool slot */
5749 set_bit(0, &adapter->fwd_bitmask);
5750 set_bit(__IXGBE_DOWN, &adapter->state);
5751
5752 return 0;
5753 }
5754
5755 /**
5756 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5757 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5758 *
5759 * Return 0 on success, negative on failure
5760 **/
5761 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5762 {
5763 struct device *dev = tx_ring->dev;
5764 int orig_node = dev_to_node(dev);
5765 int ring_node = -1;
5766 int size;
5767
5768 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5769
5770 if (tx_ring->q_vector)
5771 ring_node = tx_ring->q_vector->numa_node;
5772
5773 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
5774 if (!tx_ring->tx_buffer_info)
5775 tx_ring->tx_buffer_info = vzalloc(size);
5776 if (!tx_ring->tx_buffer_info)
5777 goto err;
5778
5779 u64_stats_init(&tx_ring->syncp);
5780
5781 /* round up to nearest 4K */
5782 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5783 tx_ring->size = ALIGN(tx_ring->size, 4096);
5784
5785 set_dev_node(dev, ring_node);
5786 tx_ring->desc = dma_alloc_coherent(dev,
5787 tx_ring->size,
5788 &tx_ring->dma,
5789 GFP_KERNEL);
5790 set_dev_node(dev, orig_node);
5791 if (!tx_ring->desc)
5792 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5793 &tx_ring->dma, GFP_KERNEL);
5794 if (!tx_ring->desc)
5795 goto err;
5796
5797 tx_ring->next_to_use = 0;
5798 tx_ring->next_to_clean = 0;
5799 return 0;
5800
5801 err:
5802 vfree(tx_ring->tx_buffer_info);
5803 tx_ring->tx_buffer_info = NULL;
5804 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5805 return -ENOMEM;
5806 }
5807
5808 /**
5809 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5810 * @adapter: board private structure
5811 *
5812 * If this function returns with an error, then it's possible one or
5813 * more of the rings is populated (while the rest are not). It is the
5814 * callers duty to clean those orphaned rings.
5815 *
5816 * Return 0 on success, negative on failure
5817 **/
5818 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5819 {
5820 int i, err = 0;
5821
5822 for (i = 0; i < adapter->num_tx_queues; i++) {
5823 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5824 if (!err)
5825 continue;
5826
5827 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5828 goto err_setup_tx;
5829 }
5830
5831 return 0;
5832 err_setup_tx:
5833 /* rewind the index freeing the rings as we go */
5834 while (i--)
5835 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5836 return err;
5837 }
5838
5839 /**
5840 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5841 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5842 *
5843 * Returns 0 on success, negative on failure
5844 **/
5845 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5846 {
5847 struct device *dev = rx_ring->dev;
5848 int orig_node = dev_to_node(dev);
5849 int ring_node = -1;
5850 int size;
5851
5852 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5853
5854 if (rx_ring->q_vector)
5855 ring_node = rx_ring->q_vector->numa_node;
5856
5857 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
5858 if (!rx_ring->rx_buffer_info)
5859 rx_ring->rx_buffer_info = vzalloc(size);
5860 if (!rx_ring->rx_buffer_info)
5861 goto err;
5862
5863 u64_stats_init(&rx_ring->syncp);
5864
5865 /* Round up to nearest 4K */
5866 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5867 rx_ring->size = ALIGN(rx_ring->size, 4096);
5868
5869 set_dev_node(dev, ring_node);
5870 rx_ring->desc = dma_alloc_coherent(dev,
5871 rx_ring->size,
5872 &rx_ring->dma,
5873 GFP_KERNEL);
5874 set_dev_node(dev, orig_node);
5875 if (!rx_ring->desc)
5876 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5877 &rx_ring->dma, GFP_KERNEL);
5878 if (!rx_ring->desc)
5879 goto err;
5880
5881 rx_ring->next_to_clean = 0;
5882 rx_ring->next_to_use = 0;
5883
5884 return 0;
5885 err:
5886 vfree(rx_ring->rx_buffer_info);
5887 rx_ring->rx_buffer_info = NULL;
5888 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5889 return -ENOMEM;
5890 }
5891
5892 /**
5893 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5894 * @adapter: board private structure
5895 *
5896 * If this function returns with an error, then it's possible one or
5897 * more of the rings is populated (while the rest are not). It is the
5898 * callers duty to clean those orphaned rings.
5899 *
5900 * Return 0 on success, negative on failure
5901 **/
5902 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5903 {
5904 int i, err = 0;
5905
5906 for (i = 0; i < adapter->num_rx_queues; i++) {
5907 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5908 if (!err)
5909 continue;
5910
5911 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5912 goto err_setup_rx;
5913 }
5914
5915 #ifdef IXGBE_FCOE
5916 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5917 if (!err)
5918 #endif
5919 return 0;
5920 err_setup_rx:
5921 /* rewind the index freeing the rings as we go */
5922 while (i--)
5923 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5924 return err;
5925 }
5926
5927 /**
5928 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5929 * @tx_ring: Tx descriptor ring for a specific queue
5930 *
5931 * Free all transmit software resources
5932 **/
5933 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5934 {
5935 ixgbe_clean_tx_ring(tx_ring);
5936
5937 vfree(tx_ring->tx_buffer_info);
5938 tx_ring->tx_buffer_info = NULL;
5939
5940 /* if not set, then don't free */
5941 if (!tx_ring->desc)
5942 return;
5943
5944 dma_free_coherent(tx_ring->dev, tx_ring->size,
5945 tx_ring->desc, tx_ring->dma);
5946
5947 tx_ring->desc = NULL;
5948 }
5949
5950 /**
5951 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5952 * @adapter: board private structure
5953 *
5954 * Free all transmit software resources
5955 **/
5956 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5957 {
5958 int i;
5959
5960 for (i = 0; i < adapter->num_tx_queues; i++)
5961 if (adapter->tx_ring[i]->desc)
5962 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5963 }
5964
5965 /**
5966 * ixgbe_free_rx_resources - Free Rx Resources
5967 * @rx_ring: ring to clean the resources from
5968 *
5969 * Free all receive software resources
5970 **/
5971 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5972 {
5973 ixgbe_clean_rx_ring(rx_ring);
5974
5975 vfree(rx_ring->rx_buffer_info);
5976 rx_ring->rx_buffer_info = NULL;
5977
5978 /* if not set, then don't free */
5979 if (!rx_ring->desc)
5980 return;
5981
5982 dma_free_coherent(rx_ring->dev, rx_ring->size,
5983 rx_ring->desc, rx_ring->dma);
5984
5985 rx_ring->desc = NULL;
5986 }
5987
5988 /**
5989 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5990 * @adapter: board private structure
5991 *
5992 * Free all receive software resources
5993 **/
5994 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5995 {
5996 int i;
5997
5998 #ifdef IXGBE_FCOE
5999 ixgbe_free_fcoe_ddp_resources(adapter);
6000
6001 #endif
6002 for (i = 0; i < adapter->num_rx_queues; i++)
6003 if (adapter->rx_ring[i]->desc)
6004 ixgbe_free_rx_resources(adapter->rx_ring[i]);
6005 }
6006
6007 /**
6008 * ixgbe_change_mtu - Change the Maximum Transfer Unit
6009 * @netdev: network interface device structure
6010 * @new_mtu: new value for maximum frame size
6011 *
6012 * Returns 0 on success, negative on failure
6013 **/
6014 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
6015 {
6016 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6017 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
6018
6019 /* MTU < 68 is an error and causes problems on some kernels */
6020 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
6021 return -EINVAL;
6022
6023 /*
6024 * For 82599EB we cannot allow legacy VFs to enable their receive
6025 * paths when MTU greater than 1500 is configured. So display a
6026 * warning that legacy VFs will be disabled.
6027 */
6028 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
6029 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
6030 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
6031 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
6032
6033 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
6034
6035 /* must set new MTU before calling down or up */
6036 netdev->mtu = new_mtu;
6037
6038 if (netif_running(netdev))
6039 ixgbe_reinit_locked(adapter);
6040
6041 return 0;
6042 }
6043
6044 /**
6045 * ixgbe_open - Called when a network interface is made active
6046 * @netdev: network interface device structure
6047 *
6048 * Returns 0 on success, negative value on failure
6049 *
6050 * The open entry point is called when a network interface is made
6051 * active by the system (IFF_UP). At this point all resources needed
6052 * for transmit and receive operations are allocated, the interrupt
6053 * handler is registered with the OS, the watchdog timer is started,
6054 * and the stack is notified that the interface is ready.
6055 **/
6056 int ixgbe_open(struct net_device *netdev)
6057 {
6058 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6059 struct ixgbe_hw *hw = &adapter->hw;
6060 int err, queues;
6061
6062 /* disallow open during test */
6063 if (test_bit(__IXGBE_TESTING, &adapter->state))
6064 return -EBUSY;
6065
6066 netif_carrier_off(netdev);
6067
6068 /* allocate transmit descriptors */
6069 err = ixgbe_setup_all_tx_resources(adapter);
6070 if (err)
6071 goto err_setup_tx;
6072
6073 /* allocate receive descriptors */
6074 err = ixgbe_setup_all_rx_resources(adapter);
6075 if (err)
6076 goto err_setup_rx;
6077
6078 ixgbe_configure(adapter);
6079
6080 err = ixgbe_request_irq(adapter);
6081 if (err)
6082 goto err_req_irq;
6083
6084 /* Notify the stack of the actual queue counts. */
6085 if (adapter->num_rx_pools > 1)
6086 queues = adapter->num_rx_queues_per_pool;
6087 else
6088 queues = adapter->num_tx_queues;
6089
6090 err = netif_set_real_num_tx_queues(netdev, queues);
6091 if (err)
6092 goto err_set_queues;
6093
6094 if (adapter->num_rx_pools > 1 &&
6095 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
6096 queues = IXGBE_MAX_L2A_QUEUES;
6097 else
6098 queues = adapter->num_rx_queues;
6099 err = netif_set_real_num_rx_queues(netdev, queues);
6100 if (err)
6101 goto err_set_queues;
6102
6103 ixgbe_ptp_init(adapter);
6104
6105 ixgbe_up_complete(adapter);
6106
6107 ixgbe_clear_vxlan_port(adapter);
6108 #ifdef CONFIG_IXGBE_VXLAN
6109 vxlan_get_rx_port(netdev);
6110 #endif
6111
6112 return 0;
6113
6114 err_set_queues:
6115 ixgbe_free_irq(adapter);
6116 err_req_irq:
6117 ixgbe_free_all_rx_resources(adapter);
6118 if (hw->phy.ops.set_phy_power && !adapter->wol)
6119 hw->phy.ops.set_phy_power(&adapter->hw, false);
6120 err_setup_rx:
6121 ixgbe_free_all_tx_resources(adapter);
6122 err_setup_tx:
6123 ixgbe_reset(adapter);
6124
6125 return err;
6126 }
6127
6128 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
6129 {
6130 ixgbe_ptp_suspend(adapter);
6131
6132 if (adapter->hw.phy.ops.enter_lplu) {
6133 adapter->hw.phy.reset_disable = true;
6134 ixgbe_down(adapter);
6135 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
6136 adapter->hw.phy.reset_disable = false;
6137 } else {
6138 ixgbe_down(adapter);
6139 }
6140
6141 ixgbe_free_irq(adapter);
6142
6143 ixgbe_free_all_tx_resources(adapter);
6144 ixgbe_free_all_rx_resources(adapter);
6145 }
6146
6147 /**
6148 * ixgbe_close - Disables a network interface
6149 * @netdev: network interface device structure
6150 *
6151 * Returns 0, this is not allowed to fail
6152 *
6153 * The close entry point is called when an interface is de-activated
6154 * by the OS. The hardware is still under the drivers control, but
6155 * needs to be disabled. A global MAC reset is issued to stop the
6156 * hardware, and all transmit and receive resources are freed.
6157 **/
6158 int ixgbe_close(struct net_device *netdev)
6159 {
6160 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6161
6162 ixgbe_ptp_stop(adapter);
6163
6164 ixgbe_close_suspend(adapter);
6165
6166 ixgbe_fdir_filter_exit(adapter);
6167
6168 ixgbe_release_hw_control(adapter);
6169
6170 return 0;
6171 }
6172
6173 #ifdef CONFIG_PM
6174 static int ixgbe_resume(struct pci_dev *pdev)
6175 {
6176 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6177 struct net_device *netdev = adapter->netdev;
6178 u32 err;
6179
6180 adapter->hw.hw_addr = adapter->io_addr;
6181 pci_set_power_state(pdev, PCI_D0);
6182 pci_restore_state(pdev);
6183 /*
6184 * pci_restore_state clears dev->state_saved so call
6185 * pci_save_state to restore it.
6186 */
6187 pci_save_state(pdev);
6188
6189 err = pci_enable_device_mem(pdev);
6190 if (err) {
6191 e_dev_err("Cannot enable PCI device from suspend\n");
6192 return err;
6193 }
6194 smp_mb__before_atomic();
6195 clear_bit(__IXGBE_DISABLED, &adapter->state);
6196 pci_set_master(pdev);
6197
6198 pci_wake_from_d3(pdev, false);
6199
6200 ixgbe_reset(adapter);
6201
6202 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6203
6204 rtnl_lock();
6205 err = ixgbe_init_interrupt_scheme(adapter);
6206 if (!err && netif_running(netdev))
6207 err = ixgbe_open(netdev);
6208
6209 rtnl_unlock();
6210
6211 if (err)
6212 return err;
6213
6214 netif_device_attach(netdev);
6215
6216 return 0;
6217 }
6218 #endif /* CONFIG_PM */
6219
6220 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
6221 {
6222 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6223 struct net_device *netdev = adapter->netdev;
6224 struct ixgbe_hw *hw = &adapter->hw;
6225 u32 ctrl, fctrl;
6226 u32 wufc = adapter->wol;
6227 #ifdef CONFIG_PM
6228 int retval = 0;
6229 #endif
6230
6231 netif_device_detach(netdev);
6232
6233 rtnl_lock();
6234 if (netif_running(netdev))
6235 ixgbe_close_suspend(adapter);
6236 rtnl_unlock();
6237
6238 ixgbe_clear_interrupt_scheme(adapter);
6239
6240 #ifdef CONFIG_PM
6241 retval = pci_save_state(pdev);
6242 if (retval)
6243 return retval;
6244
6245 #endif
6246 if (hw->mac.ops.stop_link_on_d3)
6247 hw->mac.ops.stop_link_on_d3(hw);
6248
6249 if (wufc) {
6250 ixgbe_set_rx_mode(netdev);
6251
6252 /* enable the optics for 82599 SFP+ fiber as we can WoL */
6253 if (hw->mac.ops.enable_tx_laser)
6254 hw->mac.ops.enable_tx_laser(hw);
6255
6256 /* turn on all-multi mode if wake on multicast is enabled */
6257 if (wufc & IXGBE_WUFC_MC) {
6258 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6259 fctrl |= IXGBE_FCTRL_MPE;
6260 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
6261 }
6262
6263 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
6264 ctrl |= IXGBE_CTRL_GIO_DIS;
6265 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
6266
6267 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
6268 } else {
6269 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
6270 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
6271 }
6272
6273 switch (hw->mac.type) {
6274 case ixgbe_mac_82598EB:
6275 pci_wake_from_d3(pdev, false);
6276 break;
6277 case ixgbe_mac_82599EB:
6278 case ixgbe_mac_X540:
6279 case ixgbe_mac_X550:
6280 case ixgbe_mac_X550EM_x:
6281 case ixgbe_mac_x550em_a:
6282 pci_wake_from_d3(pdev, !!wufc);
6283 break;
6284 default:
6285 break;
6286 }
6287
6288 *enable_wake = !!wufc;
6289 if (hw->phy.ops.set_phy_power && !*enable_wake)
6290 hw->phy.ops.set_phy_power(hw, false);
6291
6292 ixgbe_release_hw_control(adapter);
6293
6294 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6295 pci_disable_device(pdev);
6296
6297 return 0;
6298 }
6299
6300 #ifdef CONFIG_PM
6301 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
6302 {
6303 int retval;
6304 bool wake;
6305
6306 retval = __ixgbe_shutdown(pdev, &wake);
6307 if (retval)
6308 return retval;
6309
6310 if (wake) {
6311 pci_prepare_to_sleep(pdev);
6312 } else {
6313 pci_wake_from_d3(pdev, false);
6314 pci_set_power_state(pdev, PCI_D3hot);
6315 }
6316
6317 return 0;
6318 }
6319 #endif /* CONFIG_PM */
6320
6321 static void ixgbe_shutdown(struct pci_dev *pdev)
6322 {
6323 bool wake;
6324
6325 __ixgbe_shutdown(pdev, &wake);
6326
6327 if (system_state == SYSTEM_POWER_OFF) {
6328 pci_wake_from_d3(pdev, wake);
6329 pci_set_power_state(pdev, PCI_D3hot);
6330 }
6331 }
6332
6333 /**
6334 * ixgbe_update_stats - Update the board statistics counters.
6335 * @adapter: board private structure
6336 **/
6337 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6338 {
6339 struct net_device *netdev = adapter->netdev;
6340 struct ixgbe_hw *hw = &adapter->hw;
6341 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6342 u64 total_mpc = 0;
6343 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
6344 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6345 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
6346 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
6347
6348 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6349 test_bit(__IXGBE_RESETTING, &adapter->state))
6350 return;
6351
6352 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
6353 u64 rsc_count = 0;
6354 u64 rsc_flush = 0;
6355 for (i = 0; i < adapter->num_rx_queues; i++) {
6356 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6357 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
6358 }
6359 adapter->rsc_total_count = rsc_count;
6360 adapter->rsc_total_flush = rsc_flush;
6361 }
6362
6363 for (i = 0; i < adapter->num_rx_queues; i++) {
6364 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6365 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6366 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6367 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
6368 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
6369 bytes += rx_ring->stats.bytes;
6370 packets += rx_ring->stats.packets;
6371 }
6372 adapter->non_eop_descs = non_eop_descs;
6373 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6374 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
6375 adapter->hw_csum_rx_error = hw_csum_rx_error;
6376 netdev->stats.rx_bytes = bytes;
6377 netdev->stats.rx_packets = packets;
6378
6379 bytes = 0;
6380 packets = 0;
6381 /* gather some stats to the adapter struct that are per queue */
6382 for (i = 0; i < adapter->num_tx_queues; i++) {
6383 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6384 restart_queue += tx_ring->tx_stats.restart_queue;
6385 tx_busy += tx_ring->tx_stats.tx_busy;
6386 bytes += tx_ring->stats.bytes;
6387 packets += tx_ring->stats.packets;
6388 }
6389 adapter->restart_queue = restart_queue;
6390 adapter->tx_busy = tx_busy;
6391 netdev->stats.tx_bytes = bytes;
6392 netdev->stats.tx_packets = packets;
6393
6394 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6395
6396 /* 8 register reads */
6397 for (i = 0; i < 8; i++) {
6398 /* for packet buffers not used, the register should read 0 */
6399 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6400 missed_rx += mpc;
6401 hwstats->mpc[i] += mpc;
6402 total_mpc += hwstats->mpc[i];
6403 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6404 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6405 switch (hw->mac.type) {
6406 case ixgbe_mac_82598EB:
6407 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6408 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6409 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
6410 hwstats->pxonrxc[i] +=
6411 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
6412 break;
6413 case ixgbe_mac_82599EB:
6414 case ixgbe_mac_X540:
6415 case ixgbe_mac_X550:
6416 case ixgbe_mac_X550EM_x:
6417 case ixgbe_mac_x550em_a:
6418 hwstats->pxonrxc[i] +=
6419 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
6420 break;
6421 default:
6422 break;
6423 }
6424 }
6425
6426 /*16 register reads */
6427 for (i = 0; i < 16; i++) {
6428 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6429 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6430 if ((hw->mac.type == ixgbe_mac_82599EB) ||
6431 (hw->mac.type == ixgbe_mac_X540) ||
6432 (hw->mac.type == ixgbe_mac_X550) ||
6433 (hw->mac.type == ixgbe_mac_X550EM_x) ||
6434 (hw->mac.type == ixgbe_mac_x550em_a)) {
6435 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6436 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6437 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6438 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6439 }
6440 }
6441
6442 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6443 /* work around hardware counting issue */
6444 hwstats->gprc -= missed_rx;
6445
6446 ixgbe_update_xoff_received(adapter);
6447
6448 /* 82598 hardware only has a 32 bit counter in the high register */
6449 switch (hw->mac.type) {
6450 case ixgbe_mac_82598EB:
6451 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
6452 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6453 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6454 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6455 break;
6456 case ixgbe_mac_X540:
6457 case ixgbe_mac_X550:
6458 case ixgbe_mac_X550EM_x:
6459 case ixgbe_mac_x550em_a:
6460 /* OS2BMC stats are X540 and later */
6461 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6462 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6463 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6464 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6465 case ixgbe_mac_82599EB:
6466 for (i = 0; i < 16; i++)
6467 adapter->hw_rx_no_dma_resources +=
6468 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
6469 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
6470 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
6471 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
6472 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
6473 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
6474 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
6475 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
6476 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6477 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6478 #ifdef IXGBE_FCOE
6479 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6480 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6481 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6482 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6483 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6484 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6485 /* Add up per cpu counters for total ddp aloc fail */
6486 if (adapter->fcoe.ddp_pool) {
6487 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6488 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6489 unsigned int cpu;
6490 u64 noddp = 0, noddp_ext_buff = 0;
6491 for_each_possible_cpu(cpu) {
6492 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6493 noddp += ddp_pool->noddp;
6494 noddp_ext_buff += ddp_pool->noddp_ext_buff;
6495 }
6496 hwstats->fcoe_noddp = noddp;
6497 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
6498 }
6499 #endif /* IXGBE_FCOE */
6500 break;
6501 default:
6502 break;
6503 }
6504 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
6505 hwstats->bprc += bprc;
6506 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
6507 if (hw->mac.type == ixgbe_mac_82598EB)
6508 hwstats->mprc -= bprc;
6509 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6510 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6511 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6512 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6513 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6514 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6515 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6516 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6517 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
6518 hwstats->lxontxc += lxon;
6519 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
6520 hwstats->lxofftxc += lxoff;
6521 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6522 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6523 /*
6524 * 82598 errata - tx of flow control packets is included in tx counters
6525 */
6526 xon_off_tot = lxon + lxoff;
6527 hwstats->gptc -= xon_off_tot;
6528 hwstats->mptc -= xon_off_tot;
6529 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6530 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6531 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6532 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6533 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6534 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6535 hwstats->ptc64 -= xon_off_tot;
6536 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6537 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6538 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6539 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6540 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6541 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
6542
6543 /* Fill out the OS statistics structure */
6544 netdev->stats.multicast = hwstats->mprc;
6545
6546 /* Rx Errors */
6547 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
6548 netdev->stats.rx_dropped = 0;
6549 netdev->stats.rx_length_errors = hwstats->rlec;
6550 netdev->stats.rx_crc_errors = hwstats->crcerrs;
6551 netdev->stats.rx_missed_errors = total_mpc;
6552 }
6553
6554 /**
6555 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
6556 * @adapter: pointer to the device adapter structure
6557 **/
6558 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
6559 {
6560 struct ixgbe_hw *hw = &adapter->hw;
6561 int i;
6562
6563 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6564 return;
6565
6566 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
6567
6568 /* if interface is down do nothing */
6569 if (test_bit(__IXGBE_DOWN, &adapter->state))
6570 return;
6571
6572 /* do nothing if we are not using signature filters */
6573 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6574 return;
6575
6576 adapter->fdir_overflow++;
6577
6578 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6579 for (i = 0; i < adapter->num_tx_queues; i++)
6580 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
6581 &(adapter->tx_ring[i]->state));
6582 /* re-enable flow director interrupts */
6583 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
6584 } else {
6585 e_err(probe, "failed to finish FDIR re-initialization, "
6586 "ignored adding FDIR ATR filters\n");
6587 }
6588 }
6589
6590 /**
6591 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
6592 * @adapter: pointer to the device adapter structure
6593 *
6594 * This function serves two purposes. First it strobes the interrupt lines
6595 * in order to make certain interrupts are occurring. Secondly it sets the
6596 * bits needed to check for TX hangs. As a result we should immediately
6597 * determine if a hang has occurred.
6598 */
6599 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
6600 {
6601 struct ixgbe_hw *hw = &adapter->hw;
6602 u64 eics = 0;
6603 int i;
6604
6605 /* If we're down, removing or resetting, just bail */
6606 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6607 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6608 test_bit(__IXGBE_RESETTING, &adapter->state))
6609 return;
6610
6611 /* Force detection of hung controller */
6612 if (netif_carrier_ok(adapter->netdev)) {
6613 for (i = 0; i < adapter->num_tx_queues; i++)
6614 set_check_for_tx_hang(adapter->tx_ring[i]);
6615 }
6616
6617 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6618 /*
6619 * for legacy and MSI interrupts don't set any bits
6620 * that are enabled for EIAM, because this operation
6621 * would set *both* EIMS and EICS for any bit in EIAM
6622 */
6623 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6624 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
6625 } else {
6626 /* get one bit for every active tx/rx interrupt vector */
6627 for (i = 0; i < adapter->num_q_vectors; i++) {
6628 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6629 if (qv->rx.ring || qv->tx.ring)
6630 eics |= ((u64)1 << i);
6631 }
6632 }
6633
6634 /* Cause software interrupt to ensure rings are cleaned */
6635 ixgbe_irq_rearm_queues(adapter, eics);
6636 }
6637
6638 /**
6639 * ixgbe_watchdog_update_link - update the link status
6640 * @adapter: pointer to the device adapter structure
6641 * @link_speed: pointer to a u32 to store the link_speed
6642 **/
6643 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
6644 {
6645 struct ixgbe_hw *hw = &adapter->hw;
6646 u32 link_speed = adapter->link_speed;
6647 bool link_up = adapter->link_up;
6648 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
6649
6650 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6651 return;
6652
6653 if (hw->mac.ops.check_link) {
6654 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6655 } else {
6656 /* always assume link is up, if no check link function */
6657 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6658 link_up = true;
6659 }
6660
6661 if (adapter->ixgbe_ieee_pfc)
6662 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6663
6664 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
6665 hw->mac.ops.fc_enable(hw);
6666 ixgbe_set_rx_drop_en(adapter);
6667 }
6668
6669 if (link_up ||
6670 time_after(jiffies, (adapter->link_check_timeout +
6671 IXGBE_TRY_LINK_TIMEOUT))) {
6672 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6673 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6674 IXGBE_WRITE_FLUSH(hw);
6675 }
6676
6677 adapter->link_up = link_up;
6678 adapter->link_speed = link_speed;
6679 }
6680
6681 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6682 {
6683 #ifdef CONFIG_IXGBE_DCB
6684 struct net_device *netdev = adapter->netdev;
6685 struct dcb_app app = {
6686 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6687 .protocol = 0,
6688 };
6689 u8 up = 0;
6690
6691 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6692 up = dcb_ieee_getapp_mask(netdev, &app);
6693
6694 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6695 #endif
6696 }
6697
6698 /**
6699 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6700 * print link up message
6701 * @adapter: pointer to the device adapter structure
6702 **/
6703 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
6704 {
6705 struct net_device *netdev = adapter->netdev;
6706 struct ixgbe_hw *hw = &adapter->hw;
6707 struct net_device *upper;
6708 struct list_head *iter;
6709 u32 link_speed = adapter->link_speed;
6710 const char *speed_str;
6711 bool flow_rx, flow_tx;
6712
6713 /* only continue if link was previously down */
6714 if (netif_carrier_ok(netdev))
6715 return;
6716
6717 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
6718
6719 switch (hw->mac.type) {
6720 case ixgbe_mac_82598EB: {
6721 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6722 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6723 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6724 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6725 }
6726 break;
6727 case ixgbe_mac_X540:
6728 case ixgbe_mac_X550:
6729 case ixgbe_mac_X550EM_x:
6730 case ixgbe_mac_x550em_a:
6731 case ixgbe_mac_82599EB: {
6732 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6733 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6734 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6735 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6736 }
6737 break;
6738 default:
6739 flow_tx = false;
6740 flow_rx = false;
6741 break;
6742 }
6743
6744 adapter->last_rx_ptp_check = jiffies;
6745
6746 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6747 ixgbe_ptp_start_cyclecounter(adapter);
6748
6749 switch (link_speed) {
6750 case IXGBE_LINK_SPEED_10GB_FULL:
6751 speed_str = "10 Gbps";
6752 break;
6753 case IXGBE_LINK_SPEED_2_5GB_FULL:
6754 speed_str = "2.5 Gbps";
6755 break;
6756 case IXGBE_LINK_SPEED_1GB_FULL:
6757 speed_str = "1 Gbps";
6758 break;
6759 case IXGBE_LINK_SPEED_100_FULL:
6760 speed_str = "100 Mbps";
6761 break;
6762 default:
6763 speed_str = "unknown speed";
6764 break;
6765 }
6766 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
6767 ((flow_rx && flow_tx) ? "RX/TX" :
6768 (flow_rx ? "RX" :
6769 (flow_tx ? "TX" : "None"))));
6770
6771 netif_carrier_on(netdev);
6772 ixgbe_check_vf_rate_limit(adapter);
6773
6774 /* enable transmits */
6775 netif_tx_wake_all_queues(adapter->netdev);
6776
6777 /* enable any upper devices */
6778 rtnl_lock();
6779 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6780 if (netif_is_macvlan(upper)) {
6781 struct macvlan_dev *vlan = netdev_priv(upper);
6782
6783 if (vlan->fwd_priv)
6784 netif_tx_wake_all_queues(upper);
6785 }
6786 }
6787 rtnl_unlock();
6788
6789 /* update the default user priority for VFs */
6790 ixgbe_update_default_up(adapter);
6791
6792 /* ping all the active vfs to let them know link has changed */
6793 ixgbe_ping_all_vfs(adapter);
6794 }
6795
6796 /**
6797 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6798 * print link down message
6799 * @adapter: pointer to the adapter structure
6800 **/
6801 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
6802 {
6803 struct net_device *netdev = adapter->netdev;
6804 struct ixgbe_hw *hw = &adapter->hw;
6805
6806 adapter->link_up = false;
6807 adapter->link_speed = 0;
6808
6809 /* only continue if link was up previously */
6810 if (!netif_carrier_ok(netdev))
6811 return;
6812
6813 /* poll for SFP+ cable when link is down */
6814 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6815 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6816
6817 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6818 ixgbe_ptp_start_cyclecounter(adapter);
6819
6820 e_info(drv, "NIC Link is Down\n");
6821 netif_carrier_off(netdev);
6822
6823 /* ping all the active vfs to let them know link has changed */
6824 ixgbe_ping_all_vfs(adapter);
6825 }
6826
6827 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6828 {
6829 int i;
6830
6831 for (i = 0; i < adapter->num_tx_queues; i++) {
6832 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6833
6834 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6835 return true;
6836 }
6837
6838 return false;
6839 }
6840
6841 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6842 {
6843 struct ixgbe_hw *hw = &adapter->hw;
6844 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6845 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6846
6847 int i, j;
6848
6849 if (!adapter->num_vfs)
6850 return false;
6851
6852 /* resetting the PF is only needed for MAC before X550 */
6853 if (hw->mac.type >= ixgbe_mac_X550)
6854 return false;
6855
6856 for (i = 0; i < adapter->num_vfs; i++) {
6857 for (j = 0; j < q_per_pool; j++) {
6858 u32 h, t;
6859
6860 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6861 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6862
6863 if (h != t)
6864 return true;
6865 }
6866 }
6867
6868 return false;
6869 }
6870
6871 /**
6872 * ixgbe_watchdog_flush_tx - flush queues on link down
6873 * @adapter: pointer to the device adapter structure
6874 **/
6875 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6876 {
6877 if (!netif_carrier_ok(adapter->netdev)) {
6878 if (ixgbe_ring_tx_pending(adapter) ||
6879 ixgbe_vf_tx_pending(adapter)) {
6880 /* We've lost link, so the controller stops DMA,
6881 * but we've got queued Tx work that's never going
6882 * to get done, so reset controller to flush Tx.
6883 * (Do the reset outside of interrupt context).
6884 */
6885 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
6886 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6887 }
6888 }
6889 }
6890
6891 #ifdef CONFIG_PCI_IOV
6892 static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6893 struct pci_dev *vfdev)
6894 {
6895 if (!pci_wait_for_pending_transaction(vfdev))
6896 e_dev_warn("Issuing VFLR with pending transactions\n");
6897
6898 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6899 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6900
6901 msleep(100);
6902 }
6903
6904 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6905 {
6906 struct ixgbe_hw *hw = &adapter->hw;
6907 struct pci_dev *pdev = adapter->pdev;
6908 unsigned int vf;
6909 u32 gpc;
6910
6911 if (!(netif_carrier_ok(adapter->netdev)))
6912 return;
6913
6914 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6915 if (gpc) /* If incrementing then no need for the check below */
6916 return;
6917 /* Check to see if a bad DMA write target from an errant or
6918 * malicious VF has caused a PCIe error. If so then we can
6919 * issue a VFLR to the offending VF(s) and then resume without
6920 * requesting a full slot reset.
6921 */
6922
6923 if (!pdev)
6924 return;
6925
6926 /* check status reg for all VFs owned by this PF */
6927 for (vf = 0; vf < adapter->num_vfs; ++vf) {
6928 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev;
6929 u16 status_reg;
6930
6931 if (!vfdev)
6932 continue;
6933 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6934 if (status_reg != IXGBE_FAILED_READ_CFG_WORD &&
6935 status_reg & PCI_STATUS_REC_MASTER_ABORT)
6936 ixgbe_issue_vf_flr(adapter, vfdev);
6937 }
6938 }
6939
6940 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6941 {
6942 u32 ssvpc;
6943
6944 /* Do not perform spoof check for 82598 or if not in IOV mode */
6945 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6946 adapter->num_vfs == 0)
6947 return;
6948
6949 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6950
6951 /*
6952 * ssvpc register is cleared on read, if zero then no
6953 * spoofed packets in the last interval.
6954 */
6955 if (!ssvpc)
6956 return;
6957
6958 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
6959 }
6960 #else
6961 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
6962 {
6963 }
6964
6965 static void
6966 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
6967 {
6968 }
6969 #endif /* CONFIG_PCI_IOV */
6970
6971
6972 /**
6973 * ixgbe_watchdog_subtask - check and bring link up
6974 * @adapter: pointer to the device adapter structure
6975 **/
6976 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6977 {
6978 /* if interface is down, removing or resetting, do nothing */
6979 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6980 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6981 test_bit(__IXGBE_RESETTING, &adapter->state))
6982 return;
6983
6984 ixgbe_watchdog_update_link(adapter);
6985
6986 if (adapter->link_up)
6987 ixgbe_watchdog_link_is_up(adapter);
6988 else
6989 ixgbe_watchdog_link_is_down(adapter);
6990
6991 ixgbe_check_for_bad_vf(adapter);
6992 ixgbe_spoof_check(adapter);
6993 ixgbe_update_stats(adapter);
6994
6995 ixgbe_watchdog_flush_tx(adapter);
6996 }
6997
6998 /**
6999 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
7000 * @adapter: the ixgbe adapter structure
7001 **/
7002 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
7003 {
7004 struct ixgbe_hw *hw = &adapter->hw;
7005 s32 err;
7006
7007 /* not searching for SFP so there is nothing to do here */
7008 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
7009 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7010 return;
7011
7012 if (adapter->sfp_poll_time &&
7013 time_after(adapter->sfp_poll_time, jiffies))
7014 return; /* If not yet time to poll for SFP */
7015
7016 /* someone else is in init, wait until next service event */
7017 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7018 return;
7019
7020 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
7021
7022 err = hw->phy.ops.identify_sfp(hw);
7023 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7024 goto sfp_out;
7025
7026 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
7027 /* If no cable is present, then we need to reset
7028 * the next time we find a good cable. */
7029 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
7030 }
7031
7032 /* exit on error */
7033 if (err)
7034 goto sfp_out;
7035
7036 /* exit if reset not needed */
7037 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7038 goto sfp_out;
7039
7040 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
7041
7042 /*
7043 * A module may be identified correctly, but the EEPROM may not have
7044 * support for that module. setup_sfp() will fail in that case, so
7045 * we should not allow that module to load.
7046 */
7047 if (hw->mac.type == ixgbe_mac_82598EB)
7048 err = hw->phy.ops.reset(hw);
7049 else
7050 err = hw->mac.ops.setup_sfp(hw);
7051
7052 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7053 goto sfp_out;
7054
7055 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
7056 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
7057
7058 sfp_out:
7059 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7060
7061 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
7062 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
7063 e_dev_err("failed to initialize because an unsupported "
7064 "SFP+ module type was detected.\n");
7065 e_dev_err("Reload the driver after installing a "
7066 "supported module.\n");
7067 unregister_netdev(adapter->netdev);
7068 }
7069 }
7070
7071 /**
7072 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
7073 * @adapter: the ixgbe adapter structure
7074 **/
7075 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
7076 {
7077 struct ixgbe_hw *hw = &adapter->hw;
7078 u32 speed;
7079 bool autoneg = false;
7080
7081 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
7082 return;
7083
7084 /* someone else is in init, wait until next service event */
7085 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7086 return;
7087
7088 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
7089
7090 speed = hw->phy.autoneg_advertised;
7091 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
7092 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
7093
7094 /* setup the highest link when no autoneg */
7095 if (!autoneg) {
7096 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
7097 speed = IXGBE_LINK_SPEED_10GB_FULL;
7098 }
7099 }
7100
7101 if (hw->mac.ops.setup_link)
7102 hw->mac.ops.setup_link(hw, speed, true);
7103
7104 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
7105 adapter->link_check_timeout = jiffies;
7106 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7107 }
7108
7109 /**
7110 * ixgbe_service_timer - Timer Call-back
7111 * @data: pointer to adapter cast into an unsigned long
7112 **/
7113 static void ixgbe_service_timer(unsigned long data)
7114 {
7115 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
7116 unsigned long next_event_offset;
7117
7118 /* poll faster when waiting for link */
7119 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
7120 next_event_offset = HZ / 10;
7121 else
7122 next_event_offset = HZ * 2;
7123
7124 /* Reset the timer */
7125 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
7126
7127 ixgbe_service_event_schedule(adapter);
7128 }
7129
7130 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
7131 {
7132 struct ixgbe_hw *hw = &adapter->hw;
7133 u32 status;
7134
7135 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
7136 return;
7137
7138 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
7139
7140 if (!hw->phy.ops.handle_lasi)
7141 return;
7142
7143 status = hw->phy.ops.handle_lasi(&adapter->hw);
7144 if (status != IXGBE_ERR_OVERTEMP)
7145 return;
7146
7147 e_crit(drv, "%s\n", ixgbe_overheat_msg);
7148 }
7149
7150 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
7151 {
7152 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
7153 return;
7154
7155 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
7156
7157 /* If we're already down, removing or resetting, just bail */
7158 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7159 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7160 test_bit(__IXGBE_RESETTING, &adapter->state))
7161 return;
7162
7163 ixgbe_dump(adapter);
7164 netdev_err(adapter->netdev, "Reset adapter\n");
7165 adapter->tx_timeout_count++;
7166
7167 rtnl_lock();
7168 ixgbe_reinit_locked(adapter);
7169 rtnl_unlock();
7170 }
7171
7172 /**
7173 * ixgbe_service_task - manages and runs subtasks
7174 * @work: pointer to work_struct containing our data
7175 **/
7176 static void ixgbe_service_task(struct work_struct *work)
7177 {
7178 struct ixgbe_adapter *adapter = container_of(work,
7179 struct ixgbe_adapter,
7180 service_task);
7181 if (ixgbe_removed(adapter->hw.hw_addr)) {
7182 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
7183 rtnl_lock();
7184 ixgbe_down(adapter);
7185 rtnl_unlock();
7186 }
7187 ixgbe_service_event_complete(adapter);
7188 return;
7189 }
7190 #ifdef CONFIG_IXGBE_VXLAN
7191 if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) {
7192 adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED;
7193 vxlan_get_rx_port(adapter->netdev);
7194 }
7195 #endif /* CONFIG_IXGBE_VXLAN */
7196 ixgbe_reset_subtask(adapter);
7197 ixgbe_phy_interrupt_subtask(adapter);
7198 ixgbe_sfp_detection_subtask(adapter);
7199 ixgbe_sfp_link_config_subtask(adapter);
7200 ixgbe_check_overtemp_subtask(adapter);
7201 ixgbe_watchdog_subtask(adapter);
7202 ixgbe_fdir_reinit_subtask(adapter);
7203 ixgbe_check_hang_subtask(adapter);
7204
7205 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
7206 ixgbe_ptp_overflow_check(adapter);
7207 ixgbe_ptp_rx_hang(adapter);
7208 }
7209
7210 ixgbe_service_event_complete(adapter);
7211 }
7212
7213 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
7214 struct ixgbe_tx_buffer *first,
7215 u8 *hdr_len)
7216 {
7217 struct sk_buff *skb = first->skb;
7218 u32 vlan_macip_lens, type_tucmd;
7219 u32 mss_l4len_idx, l4len;
7220 int err;
7221
7222 if (skb->ip_summed != CHECKSUM_PARTIAL)
7223 return 0;
7224
7225 if (!skb_is_gso(skb))
7226 return 0;
7227
7228 err = skb_cow_head(skb, 0);
7229 if (err < 0)
7230 return err;
7231
7232 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
7233 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7234
7235 if (first->protocol == htons(ETH_P_IP)) {
7236 struct iphdr *iph = ip_hdr(skb);
7237 iph->tot_len = 0;
7238 iph->check = 0;
7239 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7240 iph->daddr, 0,
7241 IPPROTO_TCP,
7242 0);
7243 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
7244 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7245 IXGBE_TX_FLAGS_CSUM |
7246 IXGBE_TX_FLAGS_IPV4;
7247 } else if (skb_is_gso_v6(skb)) {
7248 ipv6_hdr(skb)->payload_len = 0;
7249 tcp_hdr(skb)->check =
7250 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
7251 &ipv6_hdr(skb)->daddr,
7252 0, IPPROTO_TCP, 0);
7253 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7254 IXGBE_TX_FLAGS_CSUM;
7255 }
7256
7257 /* compute header lengths */
7258 l4len = tcp_hdrlen(skb);
7259 *hdr_len = skb_transport_offset(skb) + l4len;
7260
7261 /* update gso size and bytecount with header size */
7262 first->gso_segs = skb_shinfo(skb)->gso_segs;
7263 first->bytecount += (first->gso_segs - 1) * *hdr_len;
7264
7265 /* mss_l4len_id: use 0 as index for TSO */
7266 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
7267 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
7268
7269 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
7270 vlan_macip_lens = skb_network_header_len(skb);
7271 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
7272 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
7273
7274 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
7275 mss_l4len_idx);
7276
7277 return 1;
7278 }
7279
7280 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb)
7281 {
7282 unsigned int offset = 0;
7283
7284 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
7285
7286 return offset == skb_checksum_start_offset(skb);
7287 }
7288
7289 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
7290 struct ixgbe_tx_buffer *first)
7291 {
7292 struct sk_buff *skb = first->skb;
7293 u32 vlan_macip_lens = 0;
7294 u32 type_tucmd = 0;
7295
7296 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7297 csum_failed:
7298 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN |
7299 IXGBE_TX_FLAGS_CC)))
7300 return;
7301 goto no_csum;
7302 }
7303
7304 switch (skb->csum_offset) {
7305 case offsetof(struct tcphdr, check):
7306 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7307 /* fall through */
7308 case offsetof(struct udphdr, check):
7309 break;
7310 case offsetof(struct sctphdr, checksum):
7311 /* validate that this is actually an SCTP request */
7312 if (((first->protocol == htons(ETH_P_IP)) &&
7313 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
7314 ((first->protocol == htons(ETH_P_IPV6)) &&
7315 ixgbe_ipv6_csum_is_sctp(skb))) {
7316 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP;
7317 break;
7318 }
7319 /* fall through */
7320 default:
7321 skb_checksum_help(skb);
7322 goto csum_failed;
7323 }
7324
7325 /* update TX checksum flag */
7326 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7327 vlan_macip_lens = skb_checksum_start_offset(skb) -
7328 skb_network_offset(skb);
7329 no_csum:
7330 /* vlan_macip_lens: MACLEN, VLAN tag */
7331 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
7332 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
7333
7334 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 0);
7335 }
7336
7337 #define IXGBE_SET_FLAG(_input, _flag, _result) \
7338 ((_flag <= _result) ? \
7339 ((u32)(_input & _flag) * (_result / _flag)) : \
7340 ((u32)(_input & _flag) / (_flag / _result)))
7341
7342 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
7343 {
7344 /* set type for advanced descriptor with frame checksum insertion */
7345 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7346 IXGBE_ADVTXD_DCMD_DEXT |
7347 IXGBE_ADVTXD_DCMD_IFCS;
7348
7349 /* set HW vlan bit if vlan is present */
7350 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7351 IXGBE_ADVTXD_DCMD_VLE);
7352
7353 /* set segmentation enable bits for TSO/FSO */
7354 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7355 IXGBE_ADVTXD_DCMD_TSE);
7356
7357 /* set timestamp bit if present */
7358 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7359 IXGBE_ADVTXD_MAC_TSTAMP);
7360
7361 /* insert frame checksum */
7362 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
7363
7364 return cmd_type;
7365 }
7366
7367 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7368 u32 tx_flags, unsigned int paylen)
7369 {
7370 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
7371
7372 /* enable L4 checksum for TSO and TX checksum offload */
7373 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7374 IXGBE_TX_FLAGS_CSUM,
7375 IXGBE_ADVTXD_POPTS_TXSM);
7376
7377 /* enble IPv4 checksum for TSO */
7378 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7379 IXGBE_TX_FLAGS_IPV4,
7380 IXGBE_ADVTXD_POPTS_IXSM);
7381
7382 /*
7383 * Check Context must be set if Tx switch is enabled, which it
7384 * always is for case where virtual functions are running
7385 */
7386 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7387 IXGBE_TX_FLAGS_CC,
7388 IXGBE_ADVTXD_CC);
7389
7390 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
7391 }
7392
7393 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7394 {
7395 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7396
7397 /* Herbert's original patch had:
7398 * smp_mb__after_netif_stop_queue();
7399 * but since that doesn't exist yet, just open code it.
7400 */
7401 smp_mb();
7402
7403 /* We need to check again in a case another CPU has just
7404 * made room available.
7405 */
7406 if (likely(ixgbe_desc_unused(tx_ring) < size))
7407 return -EBUSY;
7408
7409 /* A reprieve! - use start_queue because it doesn't call schedule */
7410 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7411 ++tx_ring->tx_stats.restart_queue;
7412 return 0;
7413 }
7414
7415 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7416 {
7417 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7418 return 0;
7419
7420 return __ixgbe_maybe_stop_tx(tx_ring, size);
7421 }
7422
7423 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7424 IXGBE_TXD_CMD_RS)
7425
7426 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
7427 struct ixgbe_tx_buffer *first,
7428 const u8 hdr_len)
7429 {
7430 struct sk_buff *skb = first->skb;
7431 struct ixgbe_tx_buffer *tx_buffer;
7432 union ixgbe_adv_tx_desc *tx_desc;
7433 struct skb_frag_struct *frag;
7434 dma_addr_t dma;
7435 unsigned int data_len, size;
7436 u32 tx_flags = first->tx_flags;
7437 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
7438 u16 i = tx_ring->next_to_use;
7439
7440 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7441
7442 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7443
7444 size = skb_headlen(skb);
7445 data_len = skb->data_len;
7446
7447 #ifdef IXGBE_FCOE
7448 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
7449 if (data_len < sizeof(struct fcoe_crc_eof)) {
7450 size -= sizeof(struct fcoe_crc_eof) - data_len;
7451 data_len = 0;
7452 } else {
7453 data_len -= sizeof(struct fcoe_crc_eof);
7454 }
7455 }
7456
7457 #endif
7458 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
7459
7460 tx_buffer = first;
7461
7462 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7463 if (dma_mapping_error(tx_ring->dev, dma))
7464 goto dma_error;
7465
7466 /* record length, and DMA address */
7467 dma_unmap_len_set(tx_buffer, len, size);
7468 dma_unmap_addr_set(tx_buffer, dma, dma);
7469
7470 tx_desc->read.buffer_addr = cpu_to_le64(dma);
7471
7472 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
7473 tx_desc->read.cmd_type_len =
7474 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
7475
7476 i++;
7477 tx_desc++;
7478 if (i == tx_ring->count) {
7479 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7480 i = 0;
7481 }
7482 tx_desc->read.olinfo_status = 0;
7483
7484 dma += IXGBE_MAX_DATA_PER_TXD;
7485 size -= IXGBE_MAX_DATA_PER_TXD;
7486
7487 tx_desc->read.buffer_addr = cpu_to_le64(dma);
7488 }
7489
7490 if (likely(!data_len))
7491 break;
7492
7493 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
7494
7495 i++;
7496 tx_desc++;
7497 if (i == tx_ring->count) {
7498 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7499 i = 0;
7500 }
7501 tx_desc->read.olinfo_status = 0;
7502
7503 #ifdef IXGBE_FCOE
7504 size = min_t(unsigned int, data_len, skb_frag_size(frag));
7505 #else
7506 size = skb_frag_size(frag);
7507 #endif
7508 data_len -= size;
7509
7510 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7511 DMA_TO_DEVICE);
7512
7513 tx_buffer = &tx_ring->tx_buffer_info[i];
7514 }
7515
7516 /* write last descriptor with RS and EOP bits */
7517 cmd_type |= size | IXGBE_TXD_CMD;
7518 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
7519
7520 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
7521
7522 /* set the timestamp */
7523 first->time_stamp = jiffies;
7524
7525 /*
7526 * Force memory writes to complete before letting h/w know there
7527 * are new descriptors to fetch. (Only applicable for weak-ordered
7528 * memory model archs, such as IA-64).
7529 *
7530 * We also need this memory barrier to make certain all of the
7531 * status bits have been updated before next_to_watch is written.
7532 */
7533 wmb();
7534
7535 /* set next_to_watch value indicating a packet is present */
7536 first->next_to_watch = tx_desc;
7537
7538 i++;
7539 if (i == tx_ring->count)
7540 i = 0;
7541
7542 tx_ring->next_to_use = i;
7543
7544 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7545
7546 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
7547 writel(i, tx_ring->tail);
7548
7549 /* we need this if more than one processor can write to our tail
7550 * at a time, it synchronizes IO on IA64/Altix systems
7551 */
7552 mmiowb();
7553 }
7554
7555 return;
7556 dma_error:
7557 dev_err(tx_ring->dev, "TX DMA map failed\n");
7558
7559 /* clear dma mappings for failed tx_buffer_info map */
7560 for (;;) {
7561 tx_buffer = &tx_ring->tx_buffer_info[i];
7562 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7563 if (tx_buffer == first)
7564 break;
7565 if (i == 0)
7566 i = tx_ring->count;
7567 i--;
7568 }
7569
7570 tx_ring->next_to_use = i;
7571 }
7572
7573 static void ixgbe_atr(struct ixgbe_ring *ring,
7574 struct ixgbe_tx_buffer *first)
7575 {
7576 struct ixgbe_q_vector *q_vector = ring->q_vector;
7577 union ixgbe_atr_hash_dword input = { .dword = 0 };
7578 union ixgbe_atr_hash_dword common = { .dword = 0 };
7579 union {
7580 unsigned char *network;
7581 struct iphdr *ipv4;
7582 struct ipv6hdr *ipv6;
7583 } hdr;
7584 struct tcphdr *th;
7585 unsigned int hlen;
7586 struct sk_buff *skb;
7587 __be16 vlan_id;
7588 int l4_proto;
7589
7590 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7591 if (!q_vector)
7592 return;
7593
7594 /* do nothing if sampling is disabled */
7595 if (!ring->atr_sample_rate)
7596 return;
7597
7598 ring->atr_count++;
7599
7600 /* currently only IPv4/IPv6 with TCP is supported */
7601 if ((first->protocol != htons(ETH_P_IP)) &&
7602 (first->protocol != htons(ETH_P_IPV6)))
7603 return;
7604
7605 /* snag network header to get L4 type and address */
7606 skb = first->skb;
7607 hdr.network = skb_network_header(skb);
7608 #ifdef CONFIG_IXGBE_VXLAN
7609 if (skb->encapsulation &&
7610 first->protocol == htons(ETH_P_IP) &&
7611 hdr.ipv4->protocol != IPPROTO_UDP) {
7612 struct ixgbe_adapter *adapter = q_vector->adapter;
7613
7614 /* verify the port is recognized as VXLAN */
7615 if (adapter->vxlan_port &&
7616 udp_hdr(skb)->dest == adapter->vxlan_port)
7617 hdr.network = skb_inner_network_header(skb);
7618 }
7619 #endif /* CONFIG_IXGBE_VXLAN */
7620
7621 /* Currently only IPv4/IPv6 with TCP is supported */
7622 switch (hdr.ipv4->version) {
7623 case IPVERSION:
7624 /* access ihl as u8 to avoid unaligned access on ia64 */
7625 hlen = (hdr.network[0] & 0x0F) << 2;
7626 l4_proto = hdr.ipv4->protocol;
7627 break;
7628 case 6:
7629 hlen = hdr.network - skb->data;
7630 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL);
7631 hlen -= hdr.network - skb->data;
7632 break;
7633 default:
7634 return;
7635 }
7636
7637 if (l4_proto != IPPROTO_TCP)
7638 return;
7639
7640 th = (struct tcphdr *)(hdr.network + hlen);
7641
7642 /* skip this packet since the socket is closing */
7643 if (th->fin)
7644 return;
7645
7646 /* sample on all syn packets or once every atr sample count */
7647 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7648 return;
7649
7650 /* reset sample count */
7651 ring->atr_count = 0;
7652
7653 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
7654
7655 /*
7656 * src and dst are inverted, think how the receiver sees them
7657 *
7658 * The input is broken into two sections, a non-compressed section
7659 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7660 * is XORed together and stored in the compressed dword.
7661 */
7662 input.formatted.vlan_id = vlan_id;
7663
7664 /*
7665 * since src port and flex bytes occupy the same word XOR them together
7666 * and write the value to source port portion of compressed dword
7667 */
7668 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
7669 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
7670 else
7671 common.port.src ^= th->dest ^ first->protocol;
7672 common.port.dst ^= th->source;
7673
7674 switch (hdr.ipv4->version) {
7675 case IPVERSION:
7676 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7677 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7678 break;
7679 case 6:
7680 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7681 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7682 hdr.ipv6->saddr.s6_addr32[1] ^
7683 hdr.ipv6->saddr.s6_addr32[2] ^
7684 hdr.ipv6->saddr.s6_addr32[3] ^
7685 hdr.ipv6->daddr.s6_addr32[0] ^
7686 hdr.ipv6->daddr.s6_addr32[1] ^
7687 hdr.ipv6->daddr.s6_addr32[2] ^
7688 hdr.ipv6->daddr.s6_addr32[3];
7689 break;
7690 default:
7691 break;
7692 }
7693
7694 if (hdr.network != skb_network_header(skb))
7695 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
7696
7697 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
7698 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7699 input, common, ring->queue_index);
7700 }
7701
7702 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
7703 void *accel_priv, select_queue_fallback_t fallback)
7704 {
7705 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7706 #ifdef IXGBE_FCOE
7707 struct ixgbe_adapter *adapter;
7708 struct ixgbe_ring_feature *f;
7709 int txq;
7710 #endif
7711
7712 if (fwd_adapter)
7713 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7714
7715 #ifdef IXGBE_FCOE
7716
7717 /*
7718 * only execute the code below if protocol is FCoE
7719 * or FIP and we have FCoE enabled on the adapter
7720 */
7721 switch (vlan_get_protocol(skb)) {
7722 case htons(ETH_P_FCOE):
7723 case htons(ETH_P_FIP):
7724 adapter = netdev_priv(dev);
7725
7726 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7727 break;
7728 default:
7729 return fallback(dev, skb);
7730 }
7731
7732 f = &adapter->ring_feature[RING_F_FCOE];
7733
7734 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7735 smp_processor_id();
7736
7737 while (txq >= f->indices)
7738 txq -= f->indices;
7739
7740 return txq + f->offset;
7741 #else
7742 return fallback(dev, skb);
7743 #endif
7744 }
7745
7746 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
7747 struct ixgbe_adapter *adapter,
7748 struct ixgbe_ring *tx_ring)
7749 {
7750 struct ixgbe_tx_buffer *first;
7751 int tso;
7752 u32 tx_flags = 0;
7753 unsigned short f;
7754 u16 count = TXD_USE_COUNT(skb_headlen(skb));
7755 __be16 protocol = skb->protocol;
7756 u8 hdr_len = 0;
7757
7758 /*
7759 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
7760 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
7761 * + 2 desc gap to keep tail from touching head,
7762 * + 1 desc for context descriptor,
7763 * otherwise try next time
7764 */
7765 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7766 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7767
7768 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7769 tx_ring->tx_stats.tx_busy++;
7770 return NETDEV_TX_BUSY;
7771 }
7772
7773 /* record the location of the first descriptor for this packet */
7774 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7775 first->skb = skb;
7776 first->bytecount = skb->len;
7777 first->gso_segs = 1;
7778
7779 /* if we have a HW VLAN tag being added default to the HW one */
7780 if (skb_vlan_tag_present(skb)) {
7781 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7782 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7783 /* else if it is a SW VLAN check the next protocol and store the tag */
7784 } else if (protocol == htons(ETH_P_8021Q)) {
7785 struct vlan_hdr *vhdr, _vhdr;
7786 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7787 if (!vhdr)
7788 goto out_drop;
7789
7790 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7791 IXGBE_TX_FLAGS_VLAN_SHIFT;
7792 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7793 }
7794 protocol = vlan_get_protocol(skb);
7795
7796 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7797 adapter->ptp_clock &&
7798 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7799 &adapter->state)) {
7800 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7801 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
7802
7803 /* schedule check for Tx timestamp */
7804 adapter->ptp_tx_skb = skb_get(skb);
7805 adapter->ptp_tx_start = jiffies;
7806 schedule_work(&adapter->ptp_tx_work);
7807 }
7808
7809 skb_tx_timestamp(skb);
7810
7811 #ifdef CONFIG_PCI_IOV
7812 /*
7813 * Use the l2switch_enable flag - would be false if the DMA
7814 * Tx switch had been disabled.
7815 */
7816 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7817 tx_flags |= IXGBE_TX_FLAGS_CC;
7818
7819 #endif
7820 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
7821 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7822 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7823 (skb->priority != TC_PRIO_CONTROL))) {
7824 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
7825 tx_flags |= (skb->priority & 0x7) <<
7826 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
7827 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7828 struct vlan_ethhdr *vhdr;
7829
7830 if (skb_cow_head(skb, 0))
7831 goto out_drop;
7832 vhdr = (struct vlan_ethhdr *)skb->data;
7833 vhdr->h_vlan_TCI = htons(tx_flags >>
7834 IXGBE_TX_FLAGS_VLAN_SHIFT);
7835 } else {
7836 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7837 }
7838 }
7839
7840 /* record initial flags and protocol */
7841 first->tx_flags = tx_flags;
7842 first->protocol = protocol;
7843
7844 #ifdef IXGBE_FCOE
7845 /* setup tx offload for FCoE */
7846 if ((protocol == htons(ETH_P_FCOE)) &&
7847 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
7848 tso = ixgbe_fso(tx_ring, first, &hdr_len);
7849 if (tso < 0)
7850 goto out_drop;
7851
7852 goto xmit_fcoe;
7853 }
7854
7855 #endif /* IXGBE_FCOE */
7856 tso = ixgbe_tso(tx_ring, first, &hdr_len);
7857 if (tso < 0)
7858 goto out_drop;
7859 else if (!tso)
7860 ixgbe_tx_csum(tx_ring, first);
7861
7862 /* add the ATR filter if ATR is on */
7863 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7864 ixgbe_atr(tx_ring, first);
7865
7866 #ifdef IXGBE_FCOE
7867 xmit_fcoe:
7868 #endif /* IXGBE_FCOE */
7869 ixgbe_tx_map(tx_ring, first, hdr_len);
7870
7871 return NETDEV_TX_OK;
7872
7873 out_drop:
7874 dev_kfree_skb_any(first->skb);
7875 first->skb = NULL;
7876
7877 return NETDEV_TX_OK;
7878 }
7879
7880 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7881 struct net_device *netdev,
7882 struct ixgbe_ring *ring)
7883 {
7884 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7885 struct ixgbe_ring *tx_ring;
7886
7887 /*
7888 * The minimum packet size for olinfo paylen is 17 so pad the skb
7889 * in order to meet this minimum size requirement.
7890 */
7891 if (skb_put_padto(skb, 17))
7892 return NETDEV_TX_OK;
7893
7894 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7895
7896 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
7897 }
7898
7899 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7900 struct net_device *netdev)
7901 {
7902 return __ixgbe_xmit_frame(skb, netdev, NULL);
7903 }
7904
7905 /**
7906 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7907 * @netdev: network interface device structure
7908 * @p: pointer to an address structure
7909 *
7910 * Returns 0 on success, negative on failure
7911 **/
7912 static int ixgbe_set_mac(struct net_device *netdev, void *p)
7913 {
7914 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7915 struct ixgbe_hw *hw = &adapter->hw;
7916 struct sockaddr *addr = p;
7917
7918 if (!is_valid_ether_addr(addr->sa_data))
7919 return -EADDRNOTAVAIL;
7920
7921 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
7922 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
7923
7924 ixgbe_mac_set_default_filter(adapter);
7925
7926 return 0;
7927 }
7928
7929 static int
7930 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7931 {
7932 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7933 struct ixgbe_hw *hw = &adapter->hw;
7934 u16 value;
7935 int rc;
7936
7937 if (prtad != hw->phy.mdio.prtad)
7938 return -EINVAL;
7939 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7940 if (!rc)
7941 rc = value;
7942 return rc;
7943 }
7944
7945 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7946 u16 addr, u16 value)
7947 {
7948 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7949 struct ixgbe_hw *hw = &adapter->hw;
7950
7951 if (prtad != hw->phy.mdio.prtad)
7952 return -EINVAL;
7953 return hw->phy.ops.write_reg(hw, addr, devad, value);
7954 }
7955
7956 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7957 {
7958 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7959
7960 switch (cmd) {
7961 case SIOCSHWTSTAMP:
7962 return ixgbe_ptp_set_ts_config(adapter, req);
7963 case SIOCGHWTSTAMP:
7964 return ixgbe_ptp_get_ts_config(adapter, req);
7965 default:
7966 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7967 }
7968 }
7969
7970 /**
7971 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
7972 * netdev->dev_addrs
7973 * @netdev: network interface device structure
7974 *
7975 * Returns non-zero on failure
7976 **/
7977 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7978 {
7979 int err = 0;
7980 struct ixgbe_adapter *adapter = netdev_priv(dev);
7981 struct ixgbe_hw *hw = &adapter->hw;
7982
7983 if (is_valid_ether_addr(hw->mac.san_addr)) {
7984 rtnl_lock();
7985 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
7986 rtnl_unlock();
7987
7988 /* update SAN MAC vmdq pool selection */
7989 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
7990 }
7991 return err;
7992 }
7993
7994 /**
7995 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7996 * netdev->dev_addrs
7997 * @netdev: network interface device structure
7998 *
7999 * Returns non-zero on failure
8000 **/
8001 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
8002 {
8003 int err = 0;
8004 struct ixgbe_adapter *adapter = netdev_priv(dev);
8005 struct ixgbe_mac_info *mac = &adapter->hw.mac;
8006
8007 if (is_valid_ether_addr(mac->san_addr)) {
8008 rtnl_lock();
8009 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
8010 rtnl_unlock();
8011 }
8012 return err;
8013 }
8014
8015 #ifdef CONFIG_NET_POLL_CONTROLLER
8016 /*
8017 * Polling 'interrupt' - used by things like netconsole to send skbs
8018 * without having to re-enable interrupts. It's not called while
8019 * the interrupt routine is executing.
8020 */
8021 static void ixgbe_netpoll(struct net_device *netdev)
8022 {
8023 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8024 int i;
8025
8026 /* if interface is down do nothing */
8027 if (test_bit(__IXGBE_DOWN, &adapter->state))
8028 return;
8029
8030 /* loop through and schedule all active queues */
8031 for (i = 0; i < adapter->num_q_vectors; i++)
8032 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8033 }
8034
8035 #endif
8036 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
8037 struct rtnl_link_stats64 *stats)
8038 {
8039 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8040 int i;
8041
8042 rcu_read_lock();
8043 for (i = 0; i < adapter->num_rx_queues; i++) {
8044 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
8045 u64 bytes, packets;
8046 unsigned int start;
8047
8048 if (ring) {
8049 do {
8050 start = u64_stats_fetch_begin_irq(&ring->syncp);
8051 packets = ring->stats.packets;
8052 bytes = ring->stats.bytes;
8053 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
8054 stats->rx_packets += packets;
8055 stats->rx_bytes += bytes;
8056 }
8057 }
8058
8059 for (i = 0; i < adapter->num_tx_queues; i++) {
8060 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
8061 u64 bytes, packets;
8062 unsigned int start;
8063
8064 if (ring) {
8065 do {
8066 start = u64_stats_fetch_begin_irq(&ring->syncp);
8067 packets = ring->stats.packets;
8068 bytes = ring->stats.bytes;
8069 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
8070 stats->tx_packets += packets;
8071 stats->tx_bytes += bytes;
8072 }
8073 }
8074 rcu_read_unlock();
8075 /* following stats updated by ixgbe_watchdog_task() */
8076 stats->multicast = netdev->stats.multicast;
8077 stats->rx_errors = netdev->stats.rx_errors;
8078 stats->rx_length_errors = netdev->stats.rx_length_errors;
8079 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
8080 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
8081 return stats;
8082 }
8083
8084 #ifdef CONFIG_IXGBE_DCB
8085 /**
8086 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
8087 * @adapter: pointer to ixgbe_adapter
8088 * @tc: number of traffic classes currently enabled
8089 *
8090 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
8091 * 802.1Q priority maps to a packet buffer that exists.
8092 */
8093 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
8094 {
8095 struct ixgbe_hw *hw = &adapter->hw;
8096 u32 reg, rsave;
8097 int i;
8098
8099 /* 82598 have a static priority to TC mapping that can not
8100 * be changed so no validation is needed.
8101 */
8102 if (hw->mac.type == ixgbe_mac_82598EB)
8103 return;
8104
8105 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
8106 rsave = reg;
8107
8108 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
8109 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
8110
8111 /* If up2tc is out of bounds default to zero */
8112 if (up2tc > tc)
8113 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
8114 }
8115
8116 if (reg != rsave)
8117 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
8118
8119 return;
8120 }
8121
8122 /**
8123 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
8124 * @adapter: Pointer to adapter struct
8125 *
8126 * Populate the netdev user priority to tc map
8127 */
8128 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
8129 {
8130 struct net_device *dev = adapter->netdev;
8131 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
8132 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
8133 u8 prio;
8134
8135 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
8136 u8 tc = 0;
8137
8138 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
8139 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
8140 else if (ets)
8141 tc = ets->prio_tc[prio];
8142
8143 netdev_set_prio_tc_map(dev, prio, tc);
8144 }
8145 }
8146
8147 #endif /* CONFIG_IXGBE_DCB */
8148 /**
8149 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8150 *
8151 * @netdev: net device to configure
8152 * @tc: number of traffic classes to enable
8153 */
8154 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
8155 {
8156 struct ixgbe_adapter *adapter = netdev_priv(dev);
8157 struct ixgbe_hw *hw = &adapter->hw;
8158 bool pools;
8159
8160 /* Hardware supports up to 8 traffic classes */
8161 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
8162 return -EINVAL;
8163
8164 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
8165 return -EINVAL;
8166
8167 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
8168 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
8169 return -EBUSY;
8170
8171 /* Hardware has to reinitialize queues and interrupts to
8172 * match packet buffer alignment. Unfortunately, the
8173 * hardware is not flexible enough to do this dynamically.
8174 */
8175 if (netif_running(dev))
8176 ixgbe_close(dev);
8177 else
8178 ixgbe_reset(adapter);
8179
8180 ixgbe_clear_interrupt_scheme(adapter);
8181
8182 #ifdef CONFIG_IXGBE_DCB
8183 if (tc) {
8184 netdev_set_num_tc(dev, tc);
8185 ixgbe_set_prio_tc_map(adapter);
8186
8187 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
8188
8189 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
8190 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
8191 adapter->hw.fc.requested_mode = ixgbe_fc_none;
8192 }
8193 } else {
8194 netdev_reset_tc(dev);
8195
8196 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8197 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
8198
8199 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
8200
8201 adapter->temp_dcb_cfg.pfc_mode_enable = false;
8202 adapter->dcb_cfg.pfc_mode_enable = false;
8203 }
8204
8205 ixgbe_validate_rtr(adapter, tc);
8206
8207 #endif /* CONFIG_IXGBE_DCB */
8208 ixgbe_init_interrupt_scheme(adapter);
8209
8210 if (netif_running(dev))
8211 return ixgbe_open(dev);
8212
8213 return 0;
8214 }
8215
8216 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter,
8217 struct tc_cls_u32_offload *cls)
8218 {
8219 u32 uhtid = TC_U32_USERHTID(cls->knode.handle);
8220 u32 loc;
8221 int err;
8222
8223 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE))
8224 return -EINVAL;
8225
8226 loc = cls->knode.handle & 0xfffff;
8227
8228 spin_lock(&adapter->fdir_perfect_lock);
8229 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc);
8230 spin_unlock(&adapter->fdir_perfect_lock);
8231 return err;
8232 }
8233
8234 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter,
8235 __be16 protocol,
8236 struct tc_cls_u32_offload *cls)
8237 {
8238 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
8239
8240 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8241 return -EINVAL;
8242
8243 /* This ixgbe devices do not support hash tables at the moment
8244 * so abort when given hash tables.
8245 */
8246 if (cls->hnode.divisor > 0)
8247 return -EINVAL;
8248
8249 set_bit(uhtid - 1, &adapter->tables);
8250 return 0;
8251 }
8252
8253 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter,
8254 struct tc_cls_u32_offload *cls)
8255 {
8256 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
8257
8258 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8259 return -EINVAL;
8260
8261 clear_bit(uhtid - 1, &adapter->tables);
8262 return 0;
8263 }
8264
8265 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter,
8266 __be16 protocol,
8267 struct tc_cls_u32_offload *cls)
8268 {
8269 u32 loc = cls->knode.handle & 0xfffff;
8270 struct ixgbe_hw *hw = &adapter->hw;
8271 struct ixgbe_mat_field *field_ptr;
8272 struct ixgbe_fdir_filter *input;
8273 union ixgbe_atr_input mask;
8274 #ifdef CONFIG_NET_CLS_ACT
8275 const struct tc_action *a;
8276 #endif
8277 int i, err = 0;
8278 u8 queue;
8279 u32 uhtid, link_uhtid;
8280
8281 memset(&mask, 0, sizeof(union ixgbe_atr_input));
8282 uhtid = TC_U32_USERHTID(cls->knode.handle);
8283 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle);
8284
8285 /* At the moment cls_u32 jumps to network layer and skips past
8286 * L2 headers. The canonical method to match L2 frames is to use
8287 * negative values. However this is error prone at best but really
8288 * just broken because there is no way to "know" what sort of hdr
8289 * is in front of the network layer. Fix cls_u32 to support L2
8290 * headers when needed.
8291 */
8292 if (protocol != htons(ETH_P_IP))
8293 return -EINVAL;
8294
8295 if (link_uhtid) {
8296 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps;
8297
8298 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE)
8299 return -EINVAL;
8300
8301 if (!test_bit(link_uhtid - 1, &adapter->tables))
8302 return -EINVAL;
8303
8304 for (i = 0; nexthdr[i].jump; i++) {
8305 if (nexthdr[i].o != cls->knode.sel->offoff ||
8306 nexthdr[i].s != cls->knode.sel->offshift ||
8307 nexthdr[i].m != cls->knode.sel->offmask ||
8308 /* do not support multiple key jumps its just mad */
8309 cls->knode.sel->nkeys > 1)
8310 return -EINVAL;
8311
8312 if (nexthdr[i].off == cls->knode.sel->keys[0].off &&
8313 nexthdr[i].val == cls->knode.sel->keys[0].val &&
8314 nexthdr[i].mask == cls->knode.sel->keys[0].mask) {
8315 adapter->jump_tables[link_uhtid] =
8316 nexthdr[i].jump;
8317 break;
8318 }
8319 }
8320 return 0;
8321 }
8322
8323 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) {
8324 e_err(drv, "Location out of range\n");
8325 return -EINVAL;
8326 }
8327
8328 /* cls u32 is a graph starting at root node 0x800. The driver tracks
8329 * links and also the fields used to advance the parser across each
8330 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map
8331 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h
8332 * To add support for new nodes update ixgbe_model.h parse structures
8333 * this function _should_ be generic try not to hardcode values here.
8334 */
8335 if (uhtid == 0x800) {
8336 field_ptr = adapter->jump_tables[0];
8337 } else {
8338 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8339 return -EINVAL;
8340
8341 field_ptr = adapter->jump_tables[uhtid];
8342 }
8343
8344 if (!field_ptr)
8345 return -EINVAL;
8346
8347 input = kzalloc(sizeof(*input), GFP_KERNEL);
8348 if (!input)
8349 return -ENOMEM;
8350
8351 for (i = 0; i < cls->knode.sel->nkeys; i++) {
8352 int off = cls->knode.sel->keys[i].off;
8353 __be32 val = cls->knode.sel->keys[i].val;
8354 __be32 m = cls->knode.sel->keys[i].mask;
8355 bool found_entry = false;
8356 int j;
8357
8358 for (j = 0; field_ptr[j].val; j++) {
8359 if (field_ptr[j].off == off) {
8360 field_ptr[j].val(input, &mask, val, m);
8361 input->filter.formatted.flow_type |=
8362 field_ptr[j].type;
8363 found_entry = true;
8364 break;
8365 }
8366 }
8367
8368 if (!found_entry)
8369 goto err_out;
8370 }
8371
8372 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
8373 IXGBE_ATR_L4TYPE_MASK;
8374
8375 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
8376 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
8377
8378 #ifdef CONFIG_NET_CLS_ACT
8379 if (list_empty(&cls->knode.exts->actions))
8380 goto err_out;
8381
8382 list_for_each_entry(a, &cls->knode.exts->actions, list) {
8383 if (!is_tcf_gact_shot(a))
8384 goto err_out;
8385 }
8386 #endif
8387
8388 input->action = IXGBE_FDIR_DROP_QUEUE;
8389 queue = IXGBE_FDIR_DROP_QUEUE;
8390 input->sw_idx = loc;
8391
8392 spin_lock(&adapter->fdir_perfect_lock);
8393
8394 if (hlist_empty(&adapter->fdir_filter_list)) {
8395 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
8396 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
8397 if (err)
8398 goto err_out_w_lock;
8399 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
8400 err = -EINVAL;
8401 goto err_out_w_lock;
8402 }
8403
8404 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
8405 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter,
8406 input->sw_idx, queue);
8407 if (!err)
8408 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
8409 spin_unlock(&adapter->fdir_perfect_lock);
8410
8411 return err;
8412 err_out_w_lock:
8413 spin_unlock(&adapter->fdir_perfect_lock);
8414 err_out:
8415 kfree(input);
8416 return -EINVAL;
8417 }
8418
8419 static int __ixgbe_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
8420 struct tc_to_netdev *tc)
8421 {
8422 struct ixgbe_adapter *adapter = netdev_priv(dev);
8423
8424 if (TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS) &&
8425 tc->type == TC_SETUP_CLSU32) {
8426 switch (tc->cls_u32->command) {
8427 case TC_CLSU32_NEW_KNODE:
8428 case TC_CLSU32_REPLACE_KNODE:
8429 return ixgbe_configure_clsu32(adapter,
8430 proto, tc->cls_u32);
8431 case TC_CLSU32_DELETE_KNODE:
8432 return ixgbe_delete_clsu32(adapter, tc->cls_u32);
8433 case TC_CLSU32_NEW_HNODE:
8434 case TC_CLSU32_REPLACE_HNODE:
8435 return ixgbe_configure_clsu32_add_hnode(adapter, proto,
8436 tc->cls_u32);
8437 case TC_CLSU32_DELETE_HNODE:
8438 return ixgbe_configure_clsu32_del_hnode(adapter,
8439 tc->cls_u32);
8440 default:
8441 return -EINVAL;
8442 }
8443 }
8444
8445 if (tc->type != TC_SETUP_MQPRIO)
8446 return -EINVAL;
8447
8448 return ixgbe_setup_tc(dev, tc->tc);
8449 }
8450
8451 #ifdef CONFIG_PCI_IOV
8452 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
8453 {
8454 struct net_device *netdev = adapter->netdev;
8455
8456 rtnl_lock();
8457 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
8458 rtnl_unlock();
8459 }
8460
8461 #endif
8462 void ixgbe_do_reset(struct net_device *netdev)
8463 {
8464 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8465
8466 if (netif_running(netdev))
8467 ixgbe_reinit_locked(adapter);
8468 else
8469 ixgbe_reset(adapter);
8470 }
8471
8472 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
8473 netdev_features_t features)
8474 {
8475 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8476
8477 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
8478 if (!(features & NETIF_F_RXCSUM))
8479 features &= ~NETIF_F_LRO;
8480
8481 /* Turn off LRO if not RSC capable */
8482 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
8483 features &= ~NETIF_F_LRO;
8484
8485 return features;
8486 }
8487
8488 static int ixgbe_set_features(struct net_device *netdev,
8489 netdev_features_t features)
8490 {
8491 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8492 netdev_features_t changed = netdev->features ^ features;
8493 bool need_reset = false;
8494
8495 /* Make sure RSC matches LRO, reset if change */
8496 if (!(features & NETIF_F_LRO)) {
8497 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
8498 need_reset = true;
8499 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
8500 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
8501 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
8502 if (adapter->rx_itr_setting == 1 ||
8503 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
8504 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8505 need_reset = true;
8506 } else if ((changed ^ features) & NETIF_F_LRO) {
8507 e_info(probe, "rx-usecs set too low, "
8508 "disabling RSC\n");
8509 }
8510 }
8511
8512 /*
8513 * Check if Flow Director n-tuple support or hw_tc support was
8514 * enabled or disabled. If the state changed, we need to reset.
8515 */
8516 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) {
8517 /* turn off ATR, enable perfect filters and reset */
8518 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
8519 need_reset = true;
8520
8521 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
8522 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8523 } else {
8524 /* turn off perfect filters, enable ATR and reset */
8525 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
8526 need_reset = true;
8527
8528 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8529
8530 /* We cannot enable ATR if SR-IOV is enabled */
8531 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED ||
8532 /* We cannot enable ATR if we have 2 or more tcs */
8533 (netdev_get_num_tc(netdev) > 1) ||
8534 /* We cannot enable ATR if RSS is disabled */
8535 (adapter->ring_feature[RING_F_RSS].limit <= 1) ||
8536 /* A sample rate of 0 indicates ATR disabled */
8537 (!adapter->atr_sample_rate))
8538 ; /* do nothing not supported */
8539 else /* otherwise supported and set the flag */
8540 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
8541 }
8542
8543 if (changed & NETIF_F_RXALL)
8544 need_reset = true;
8545
8546 netdev->features = features;
8547
8548 #ifdef CONFIG_IXGBE_VXLAN
8549 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
8550 if (features & NETIF_F_RXCSUM)
8551 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8552 else
8553 ixgbe_clear_vxlan_port(adapter);
8554 }
8555 #endif /* CONFIG_IXGBE_VXLAN */
8556
8557 if (need_reset)
8558 ixgbe_do_reset(netdev);
8559 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX |
8560 NETIF_F_HW_VLAN_CTAG_FILTER))
8561 ixgbe_set_rx_mode(netdev);
8562
8563 return 0;
8564 }
8565
8566 #ifdef CONFIG_IXGBE_VXLAN
8567 /**
8568 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up
8569 * @dev: The port's netdev
8570 * @sa_family: Socket Family that VXLAN is notifiying us about
8571 * @port: New UDP port number that VXLAN started listening to
8572 **/
8573 static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8574 __be16 port)
8575 {
8576 struct ixgbe_adapter *adapter = netdev_priv(dev);
8577 struct ixgbe_hw *hw = &adapter->hw;
8578
8579 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8580 return;
8581
8582 if (sa_family == AF_INET6)
8583 return;
8584
8585 if (adapter->vxlan_port == port)
8586 return;
8587
8588 if (adapter->vxlan_port) {
8589 netdev_info(dev,
8590 "Hit Max num of VXLAN ports, not adding port %d\n",
8591 ntohs(port));
8592 return;
8593 }
8594
8595 adapter->vxlan_port = port;
8596 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, ntohs(port));
8597 }
8598
8599 /**
8600 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away
8601 * @dev: The port's netdev
8602 * @sa_family: Socket Family that VXLAN is notifying us about
8603 * @port: UDP port number that VXLAN stopped listening to
8604 **/
8605 static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8606 __be16 port)
8607 {
8608 struct ixgbe_adapter *adapter = netdev_priv(dev);
8609
8610 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8611 return;
8612
8613 if (sa_family == AF_INET6)
8614 return;
8615
8616 if (adapter->vxlan_port != port) {
8617 netdev_info(dev, "Port %d was not found, not deleting\n",
8618 ntohs(port));
8619 return;
8620 }
8621
8622 ixgbe_clear_vxlan_port(adapter);
8623 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8624 }
8625 #endif /* CONFIG_IXGBE_VXLAN */
8626
8627 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8628 struct net_device *dev,
8629 const unsigned char *addr, u16 vid,
8630 u16 flags)
8631 {
8632 /* guarantee we can provide a unique filter for the unicast address */
8633 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
8634 struct ixgbe_adapter *adapter = netdev_priv(dev);
8635 u16 pool = VMDQ_P(0);
8636
8637 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool))
8638 return -ENOMEM;
8639 }
8640
8641 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
8642 }
8643
8644 /**
8645 * ixgbe_configure_bridge_mode - set various bridge modes
8646 * @adapter - the private structure
8647 * @mode - requested bridge mode
8648 *
8649 * Configure some settings require for various bridge modes.
8650 **/
8651 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
8652 __u16 mode)
8653 {
8654 struct ixgbe_hw *hw = &adapter->hw;
8655 unsigned int p, num_pools;
8656 u32 vmdctl;
8657
8658 switch (mode) {
8659 case BRIDGE_MODE_VEPA:
8660 /* disable Tx loopback, rely on switch hairpin mode */
8661 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
8662
8663 /* must enable Rx switching replication to allow multicast
8664 * packet reception on all VFs, and to enable source address
8665 * pruning.
8666 */
8667 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8668 vmdctl |= IXGBE_VT_CTL_REPLEN;
8669 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8670
8671 /* enable Rx source address pruning. Note, this requires
8672 * replication to be enabled or else it does nothing.
8673 */
8674 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8675 for (p = 0; p < num_pools; p++) {
8676 if (hw->mac.ops.set_source_address_pruning)
8677 hw->mac.ops.set_source_address_pruning(hw,
8678 true,
8679 p);
8680 }
8681 break;
8682 case BRIDGE_MODE_VEB:
8683 /* enable Tx loopback for internal VF/PF communication */
8684 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
8685 IXGBE_PFDTXGSWC_VT_LBEN);
8686
8687 /* disable Rx switching replication unless we have SR-IOV
8688 * virtual functions
8689 */
8690 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8691 if (!adapter->num_vfs)
8692 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
8693 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8694
8695 /* disable Rx source address pruning, since we don't expect to
8696 * be receiving external loopback of our transmitted frames.
8697 */
8698 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8699 for (p = 0; p < num_pools; p++) {
8700 if (hw->mac.ops.set_source_address_pruning)
8701 hw->mac.ops.set_source_address_pruning(hw,
8702 false,
8703 p);
8704 }
8705 break;
8706 default:
8707 return -EINVAL;
8708 }
8709
8710 adapter->bridge_mode = mode;
8711
8712 e_info(drv, "enabling bridge mode: %s\n",
8713 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
8714
8715 return 0;
8716 }
8717
8718 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
8719 struct nlmsghdr *nlh, u16 flags)
8720 {
8721 struct ixgbe_adapter *adapter = netdev_priv(dev);
8722 struct nlattr *attr, *br_spec;
8723 int rem;
8724
8725 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8726 return -EOPNOTSUPP;
8727
8728 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8729 if (!br_spec)
8730 return -EINVAL;
8731
8732 nla_for_each_nested(attr, br_spec, rem) {
8733 int status;
8734 __u16 mode;
8735
8736 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8737 continue;
8738
8739 if (nla_len(attr) < sizeof(mode))
8740 return -EINVAL;
8741
8742 mode = nla_get_u16(attr);
8743 status = ixgbe_configure_bridge_mode(adapter, mode);
8744 if (status)
8745 return status;
8746
8747 break;
8748 }
8749
8750 return 0;
8751 }
8752
8753 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8754 struct net_device *dev,
8755 u32 filter_mask, int nlflags)
8756 {
8757 struct ixgbe_adapter *adapter = netdev_priv(dev);
8758
8759 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8760 return 0;
8761
8762 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
8763 adapter->bridge_mode, 0, 0, nlflags,
8764 filter_mask, NULL);
8765 }
8766
8767 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
8768 {
8769 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
8770 struct ixgbe_adapter *adapter = netdev_priv(pdev);
8771 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
8772 unsigned int limit;
8773 int pool, err;
8774
8775 /* Hardware has a limited number of available pools. Each VF, and the
8776 * PF require a pool. Check to ensure we don't attempt to use more
8777 * then the available number of pools.
8778 */
8779 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
8780 return ERR_PTR(-EINVAL);
8781
8782 #ifdef CONFIG_RPS
8783 if (vdev->num_rx_queues != vdev->num_tx_queues) {
8784 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
8785 vdev->name);
8786 return ERR_PTR(-EINVAL);
8787 }
8788 #endif
8789 /* Check for hardware restriction on number of rx/tx queues */
8790 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
8791 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
8792 netdev_info(pdev,
8793 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
8794 pdev->name);
8795 return ERR_PTR(-EINVAL);
8796 }
8797
8798 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8799 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
8800 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
8801 return ERR_PTR(-EBUSY);
8802
8803 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL);
8804 if (!fwd_adapter)
8805 return ERR_PTR(-ENOMEM);
8806
8807 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
8808 adapter->num_rx_pools++;
8809 set_bit(pool, &adapter->fwd_bitmask);
8810 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8811
8812 /* Enable VMDq flag so device will be set in VM mode */
8813 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
8814 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
8815 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
8816
8817 /* Force reinit of ring allocation with VMDQ enabled */
8818 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8819 if (err)
8820 goto fwd_add_err;
8821 fwd_adapter->pool = pool;
8822 fwd_adapter->real_adapter = adapter;
8823 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
8824 if (err)
8825 goto fwd_add_err;
8826 netif_tx_start_all_queues(vdev);
8827 return fwd_adapter;
8828 fwd_add_err:
8829 /* unwind counter and free adapter struct */
8830 netdev_info(pdev,
8831 "%s: dfwd hardware acceleration failed\n", vdev->name);
8832 clear_bit(pool, &adapter->fwd_bitmask);
8833 adapter->num_rx_pools--;
8834 kfree(fwd_adapter);
8835 return ERR_PTR(err);
8836 }
8837
8838 static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8839 {
8840 struct ixgbe_fwd_adapter *fwd_adapter = priv;
8841 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
8842 unsigned int limit;
8843
8844 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
8845 adapter->num_rx_pools--;
8846
8847 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8848 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
8849 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
8850 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8851 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
8852 fwd_adapter->pool, adapter->num_rx_pools,
8853 fwd_adapter->rx_base_queue,
8854 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
8855 adapter->fwd_bitmask);
8856 kfree(fwd_adapter);
8857 }
8858
8859 #define IXGBE_MAX_TUNNEL_HDR_LEN 80
8860 static netdev_features_t
8861 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
8862 netdev_features_t features)
8863 {
8864 if (!skb->encapsulation)
8865 return features;
8866
8867 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) >
8868 IXGBE_MAX_TUNNEL_HDR_LEN))
8869 return features & ~NETIF_F_CSUM_MASK;
8870
8871 return features;
8872 }
8873
8874 static const struct net_device_ops ixgbe_netdev_ops = {
8875 .ndo_open = ixgbe_open,
8876 .ndo_stop = ixgbe_close,
8877 .ndo_start_xmit = ixgbe_xmit_frame,
8878 .ndo_select_queue = ixgbe_select_queue,
8879 .ndo_set_rx_mode = ixgbe_set_rx_mode,
8880 .ndo_validate_addr = eth_validate_addr,
8881 .ndo_set_mac_address = ixgbe_set_mac,
8882 .ndo_change_mtu = ixgbe_change_mtu,
8883 .ndo_tx_timeout = ixgbe_tx_timeout,
8884 .ndo_set_tx_maxrate = ixgbe_tx_maxrate,
8885 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
8886 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
8887 .ndo_do_ioctl = ixgbe_ioctl,
8888 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
8889 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
8890 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
8891 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
8892 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
8893 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
8894 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
8895 .ndo_get_stats64 = ixgbe_get_stats64,
8896 .ndo_setup_tc = __ixgbe_setup_tc,
8897 #ifdef CONFIG_NET_POLL_CONTROLLER
8898 .ndo_poll_controller = ixgbe_netpoll,
8899 #endif
8900 #ifdef CONFIG_NET_RX_BUSY_POLL
8901 .ndo_busy_poll = ixgbe_low_latency_recv,
8902 #endif
8903 #ifdef IXGBE_FCOE
8904 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
8905 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
8906 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8907 .ndo_fcoe_enable = ixgbe_fcoe_enable,
8908 .ndo_fcoe_disable = ixgbe_fcoe_disable,
8909 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
8910 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
8911 #endif /* IXGBE_FCOE */
8912 .ndo_set_features = ixgbe_set_features,
8913 .ndo_fix_features = ixgbe_fix_features,
8914 .ndo_fdb_add = ixgbe_ndo_fdb_add,
8915 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
8916 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
8917 .ndo_dfwd_add_station = ixgbe_fwd_add,
8918 .ndo_dfwd_del_station = ixgbe_fwd_del,
8919 #ifdef CONFIG_IXGBE_VXLAN
8920 .ndo_add_vxlan_port = ixgbe_add_vxlan_port,
8921 .ndo_del_vxlan_port = ixgbe_del_vxlan_port,
8922 #endif /* CONFIG_IXGBE_VXLAN */
8923 .ndo_features_check = ixgbe_features_check,
8924 };
8925
8926 /**
8927 * ixgbe_enumerate_functions - Get the number of ports this device has
8928 * @adapter: adapter structure
8929 *
8930 * This function enumerates the phsyical functions co-located on a single slot,
8931 * in order to determine how many ports a device has. This is most useful in
8932 * determining the required GT/s of PCIe bandwidth necessary for optimal
8933 * performance.
8934 **/
8935 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
8936 {
8937 struct pci_dev *entry, *pdev = adapter->pdev;
8938 int physfns = 0;
8939
8940 /* Some cards can not use the generic count PCIe functions method,
8941 * because they are behind a parent switch, so we hardcode these with
8942 * the correct number of functions.
8943 */
8944 if (ixgbe_pcie_from_parent(&adapter->hw))
8945 physfns = 4;
8946
8947 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
8948 /* don't count virtual functions */
8949 if (entry->is_virtfn)
8950 continue;
8951
8952 /* When the devices on the bus don't all match our device ID,
8953 * we can't reliably determine the correct number of
8954 * functions. This can occur if a function has been direct
8955 * attached to a virtual machine using VT-d, for example. In
8956 * this case, simply return -1 to indicate this.
8957 */
8958 if ((entry->vendor != pdev->vendor) ||
8959 (entry->device != pdev->device))
8960 return -1;
8961
8962 physfns++;
8963 }
8964
8965 return physfns;
8966 }
8967
8968 /**
8969 * ixgbe_wol_supported - Check whether device supports WoL
8970 * @hw: hw specific details
8971 * @device_id: the device ID
8972 * @subdev_id: the subsystem device ID
8973 *
8974 * This function is used by probe and ethtool to determine
8975 * which devices have WoL support
8976 *
8977 **/
8978 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8979 u16 subdevice_id)
8980 {
8981 struct ixgbe_hw *hw = &adapter->hw;
8982 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8983 int is_wol_supported = 0;
8984
8985 switch (device_id) {
8986 case IXGBE_DEV_ID_82599_SFP:
8987 /* Only these subdevices could supports WOL */
8988 switch (subdevice_id) {
8989 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8990 case IXGBE_SUBDEV_ID_82599_560FLR:
8991 /* only support first port */
8992 if (hw->bus.func != 0)
8993 break;
8994 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8995 case IXGBE_SUBDEV_ID_82599_SFP:
8996 case IXGBE_SUBDEV_ID_82599_RNDC:
8997 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
8998 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8999 is_wol_supported = 1;
9000 break;
9001 }
9002 break;
9003 case IXGBE_DEV_ID_82599EN_SFP:
9004 /* Only this subdevice supports WOL */
9005 switch (subdevice_id) {
9006 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
9007 is_wol_supported = 1;
9008 break;
9009 }
9010 break;
9011 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
9012 /* All except this subdevice support WOL */
9013 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
9014 is_wol_supported = 1;
9015 break;
9016 case IXGBE_DEV_ID_82599_KX4:
9017 is_wol_supported = 1;
9018 break;
9019 case IXGBE_DEV_ID_X540T:
9020 case IXGBE_DEV_ID_X540T1:
9021 case IXGBE_DEV_ID_X550T:
9022 case IXGBE_DEV_ID_X550T1:
9023 case IXGBE_DEV_ID_X550EM_X_KX4:
9024 case IXGBE_DEV_ID_X550EM_X_KR:
9025 case IXGBE_DEV_ID_X550EM_X_10G_T:
9026 /* check eeprom to see if enabled wol */
9027 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
9028 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
9029 (hw->bus.func == 0))) {
9030 is_wol_supported = 1;
9031 }
9032 break;
9033 }
9034
9035 return is_wol_supported;
9036 }
9037
9038 /**
9039 * ixgbe_probe - Device Initialization Routine
9040 * @pdev: PCI device information struct
9041 * @ent: entry in ixgbe_pci_tbl
9042 *
9043 * Returns 0 on success, negative on failure
9044 *
9045 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
9046 * The OS initialization, configuring of the adapter private structure,
9047 * and a hardware reset occur.
9048 **/
9049 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9050 {
9051 struct net_device *netdev;
9052 struct ixgbe_adapter *adapter = NULL;
9053 struct ixgbe_hw *hw;
9054 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9055 int i, err, pci_using_dac, expected_gts;
9056 unsigned int indices = MAX_TX_QUEUES;
9057 u8 part_str[IXGBE_PBANUM_LENGTH];
9058 bool disable_dev = false;
9059 #ifdef IXGBE_FCOE
9060 u16 device_caps;
9061 #endif
9062 u32 eec;
9063
9064 /* Catch broken hardware that put the wrong VF device ID in
9065 * the PCIe SR-IOV capability.
9066 */
9067 if (pdev->is_virtfn) {
9068 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
9069 pci_name(pdev), pdev->vendor, pdev->device);
9070 return -EINVAL;
9071 }
9072
9073 err = pci_enable_device_mem(pdev);
9074 if (err)
9075 return err;
9076
9077 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9078 pci_using_dac = 1;
9079 } else {
9080 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9081 if (err) {
9082 dev_err(&pdev->dev,
9083 "No usable DMA configuration, aborting\n");
9084 goto err_dma;
9085 }
9086 pci_using_dac = 0;
9087 }
9088
9089 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
9090 IORESOURCE_MEM), ixgbe_driver_name);
9091 if (err) {
9092 dev_err(&pdev->dev,
9093 "pci_request_selected_regions failed 0x%x\n", err);
9094 goto err_pci_reg;
9095 }
9096
9097 pci_enable_pcie_error_reporting(pdev);
9098
9099 pci_set_master(pdev);
9100 pci_save_state(pdev);
9101
9102 if (ii->mac == ixgbe_mac_82598EB) {
9103 #ifdef CONFIG_IXGBE_DCB
9104 /* 8 TC w/ 4 queues per TC */
9105 indices = 4 * MAX_TRAFFIC_CLASS;
9106 #else
9107 indices = IXGBE_MAX_RSS_INDICES;
9108 #endif
9109 }
9110
9111 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9112 if (!netdev) {
9113 err = -ENOMEM;
9114 goto err_alloc_etherdev;
9115 }
9116
9117 SET_NETDEV_DEV(netdev, &pdev->dev);
9118
9119 adapter = netdev_priv(netdev);
9120
9121 adapter->netdev = netdev;
9122 adapter->pdev = pdev;
9123 hw = &adapter->hw;
9124 hw->back = adapter;
9125 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9126
9127 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
9128 pci_resource_len(pdev, 0));
9129 adapter->io_addr = hw->hw_addr;
9130 if (!hw->hw_addr) {
9131 err = -EIO;
9132 goto err_ioremap;
9133 }
9134
9135 netdev->netdev_ops = &ixgbe_netdev_ops;
9136 ixgbe_set_ethtool_ops(netdev);
9137 netdev->watchdog_timeo = 5 * HZ;
9138 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9139
9140 /* Setup hw api */
9141 hw->mac.ops = *ii->mac_ops;
9142 hw->mac.type = ii->mac;
9143 hw->mvals = ii->mvals;
9144
9145 /* EEPROM */
9146 hw->eeprom.ops = *ii->eeprom_ops;
9147 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
9148 if (ixgbe_removed(hw->hw_addr)) {
9149 err = -EIO;
9150 goto err_ioremap;
9151 }
9152 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
9153 if (!(eec & (1 << 8)))
9154 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
9155
9156 /* PHY */
9157 hw->phy.ops = *ii->phy_ops;
9158 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
9159 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
9160 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
9161 hw->phy.mdio.mmds = 0;
9162 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9163 hw->phy.mdio.dev = netdev;
9164 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
9165 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
9166
9167 ii->get_invariants(hw);
9168
9169 /* setup the private structure */
9170 err = ixgbe_sw_init(adapter);
9171 if (err)
9172 goto err_sw_init;
9173
9174 /* Make sure the SWFW semaphore is in a valid state */
9175 if (hw->mac.ops.init_swfw_sync)
9176 hw->mac.ops.init_swfw_sync(hw);
9177
9178 /* Make it possible the adapter to be woken up via WOL */
9179 switch (adapter->hw.mac.type) {
9180 case ixgbe_mac_82599EB:
9181 case ixgbe_mac_X540:
9182 case ixgbe_mac_X550:
9183 case ixgbe_mac_X550EM_x:
9184 case ixgbe_mac_x550em_a:
9185 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
9186 break;
9187 default:
9188 break;
9189 }
9190
9191 /*
9192 * If there is a fan on this device and it has failed log the
9193 * failure.
9194 */
9195 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
9196 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
9197 if (esdp & IXGBE_ESDP_SDP1)
9198 e_crit(probe, "Fan has stopped, replace the adapter\n");
9199 }
9200
9201 if (allow_unsupported_sfp)
9202 hw->allow_unsupported_sfp = allow_unsupported_sfp;
9203
9204 /* reset_hw fills in the perm_addr as well */
9205 hw->phy.reset_if_overtemp = true;
9206 err = hw->mac.ops.reset_hw(hw);
9207 hw->phy.reset_if_overtemp = false;
9208 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
9209 err = 0;
9210 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
9211 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
9212 e_dev_err("Reload the driver after installing a supported module.\n");
9213 goto err_sw_init;
9214 } else if (err) {
9215 e_dev_err("HW Init failed: %d\n", err);
9216 goto err_sw_init;
9217 }
9218
9219 #ifdef CONFIG_PCI_IOV
9220 /* SR-IOV not supported on the 82598 */
9221 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
9222 goto skip_sriov;
9223 /* Mailbox */
9224 ixgbe_init_mbx_params_pf(hw);
9225 hw->mbx.ops = ii->mbx_ops;
9226 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
9227 ixgbe_enable_sriov(adapter);
9228 skip_sriov:
9229
9230 #endif
9231 netdev->features = NETIF_F_SG |
9232 NETIF_F_TSO |
9233 NETIF_F_TSO6 |
9234 NETIF_F_RXHASH |
9235 NETIF_F_RXCSUM |
9236 NETIF_F_HW_CSUM |
9237 NETIF_F_HW_VLAN_CTAG_TX |
9238 NETIF_F_HW_VLAN_CTAG_RX |
9239 NETIF_F_HW_VLAN_CTAG_FILTER;
9240
9241 if (hw->mac.type >= ixgbe_mac_82599EB)
9242 netdev->features |= NETIF_F_SCTP_CRC;
9243
9244 /* copy netdev features into list of user selectable features */
9245 netdev->hw_features |= netdev->features;
9246 netdev->hw_features |= NETIF_F_RXALL |
9247 NETIF_F_HW_L2FW_DOFFLOAD;
9248
9249 if (hw->mac.type >= ixgbe_mac_82599EB)
9250 netdev->hw_features |= NETIF_F_NTUPLE |
9251 NETIF_F_HW_TC;
9252
9253 netdev->vlan_features |= NETIF_F_SG |
9254 NETIF_F_TSO |
9255 NETIF_F_TSO6 |
9256 NETIF_F_HW_CSUM |
9257 NETIF_F_SCTP_CRC;
9258
9259 netdev->mpls_features |= NETIF_F_HW_CSUM;
9260 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
9261
9262 netdev->priv_flags |= IFF_UNICAST_FLT;
9263 netdev->priv_flags |= IFF_SUPP_NOFCS;
9264
9265 #ifdef CONFIG_IXGBE_DCB
9266 netdev->dcbnl_ops = &dcbnl_ops;
9267 #endif
9268
9269 #ifdef IXGBE_FCOE
9270 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
9271 unsigned int fcoe_l;
9272
9273 if (hw->mac.ops.get_device_caps) {
9274 hw->mac.ops.get_device_caps(hw, &device_caps);
9275 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
9276 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
9277 }
9278
9279
9280 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
9281 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
9282
9283 netdev->features |= NETIF_F_FSO |
9284 NETIF_F_FCOE_CRC;
9285
9286 netdev->vlan_features |= NETIF_F_FSO |
9287 NETIF_F_FCOE_CRC |
9288 NETIF_F_FCOE_MTU;
9289 }
9290 #endif /* IXGBE_FCOE */
9291 if (pci_using_dac) {
9292 netdev->features |= NETIF_F_HIGHDMA;
9293 netdev->vlan_features |= NETIF_F_HIGHDMA;
9294 }
9295
9296 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
9297 netdev->hw_features |= NETIF_F_LRO;
9298 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
9299 netdev->features |= NETIF_F_LRO;
9300
9301 /* make sure the EEPROM is good */
9302 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9303 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9304 err = -EIO;
9305 goto err_sw_init;
9306 }
9307
9308 eth_platform_get_mac_address(&adapter->pdev->dev,
9309 adapter->hw.mac.perm_addr);
9310
9311 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9312
9313 if (!is_valid_ether_addr(netdev->dev_addr)) {
9314 e_dev_err("invalid MAC address\n");
9315 err = -EIO;
9316 goto err_sw_init;
9317 }
9318
9319 /* Set hw->mac.addr to permanent MAC address */
9320 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr);
9321 ixgbe_mac_set_default_filter(adapter);
9322
9323 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
9324 (unsigned long) adapter);
9325
9326 if (ixgbe_removed(hw->hw_addr)) {
9327 err = -EIO;
9328 goto err_sw_init;
9329 }
9330 INIT_WORK(&adapter->service_task, ixgbe_service_task);
9331 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
9332 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9333
9334 err = ixgbe_init_interrupt_scheme(adapter);
9335 if (err)
9336 goto err_sw_init;
9337
9338 /* WOL not supported for all devices */
9339 adapter->wol = 0;
9340 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
9341 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
9342 pdev->subsystem_device);
9343 if (hw->wol_enabled)
9344 adapter->wol = IXGBE_WUFC_MAG;
9345
9346 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9347
9348 /* save off EEPROM version number */
9349 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
9350 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
9351
9352 /* pick up the PCI bus settings for reporting later */
9353 if (ixgbe_pcie_from_parent(hw))
9354 ixgbe_get_parent_bus_info(adapter);
9355 else
9356 hw->mac.ops.get_bus_info(hw);
9357
9358 /* calculate the expected PCIe bandwidth required for optimal
9359 * performance. Note that some older parts will never have enough
9360 * bandwidth due to being older generation PCIe parts. We clamp these
9361 * parts to ensure no warning is displayed if it can't be fixed.
9362 */
9363 switch (hw->mac.type) {
9364 case ixgbe_mac_82598EB:
9365 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
9366 break;
9367 default:
9368 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
9369 break;
9370 }
9371
9372 /* don't check link if we failed to enumerate functions */
9373 if (expected_gts > 0)
9374 ixgbe_check_minimum_link(adapter, expected_gts);
9375
9376 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
9377 if (err)
9378 strlcpy(part_str, "Unknown", sizeof(part_str));
9379 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
9380 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
9381 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
9382 part_str);
9383 else
9384 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
9385 hw->mac.type, hw->phy.type, part_str);
9386
9387 e_dev_info("%pM\n", netdev->dev_addr);
9388
9389 /* reset the hardware with the new settings */
9390 err = hw->mac.ops.start_hw(hw);
9391 if (err == IXGBE_ERR_EEPROM_VERSION) {
9392 /* We are running on a pre-production device, log a warning */
9393 e_dev_warn("This device is a pre-production adapter/LOM. "
9394 "Please be aware there may be issues associated "
9395 "with your hardware. If you are experiencing "
9396 "problems please contact your Intel or hardware "
9397 "representative who provided you with this "
9398 "hardware.\n");
9399 }
9400 strcpy(netdev->name, "eth%d");
9401 err = register_netdev(netdev);
9402 if (err)
9403 goto err_register;
9404
9405 pci_set_drvdata(pdev, adapter);
9406
9407 /* power down the optics for 82599 SFP+ fiber */
9408 if (hw->mac.ops.disable_tx_laser)
9409 hw->mac.ops.disable_tx_laser(hw);
9410
9411 /* carrier off reporting is important to ethtool even BEFORE open */
9412 netif_carrier_off(netdev);
9413
9414 #ifdef CONFIG_IXGBE_DCA
9415 if (dca_add_requester(&pdev->dev) == 0) {
9416 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
9417 ixgbe_setup_dca(adapter);
9418 }
9419 #endif
9420 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
9421 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
9422 for (i = 0; i < adapter->num_vfs; i++)
9423 ixgbe_vf_configuration(pdev, (i | 0x10000000));
9424 }
9425
9426 /* firmware requires driver version to be 0xFFFFFFFF
9427 * since os does not support feature
9428 */
9429 if (hw->mac.ops.set_fw_drv_ver)
9430 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
9431 0xFF);
9432
9433 /* add san mac addr to netdev */
9434 ixgbe_add_sanmac_netdev(netdev);
9435
9436 e_dev_info("%s\n", ixgbe_default_device_descr);
9437
9438 #ifdef CONFIG_IXGBE_HWMON
9439 if (ixgbe_sysfs_init(adapter))
9440 e_err(probe, "failed to allocate sysfs resources\n");
9441 #endif /* CONFIG_IXGBE_HWMON */
9442
9443 ixgbe_dbg_adapter_init(adapter);
9444
9445 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
9446 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
9447 hw->mac.ops.setup_link(hw,
9448 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
9449 true);
9450
9451 return 0;
9452
9453 err_register:
9454 ixgbe_release_hw_control(adapter);
9455 ixgbe_clear_interrupt_scheme(adapter);
9456 err_sw_init:
9457 ixgbe_disable_sriov(adapter);
9458 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9459 iounmap(adapter->io_addr);
9460 kfree(adapter->mac_table);
9461 err_ioremap:
9462 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9463 free_netdev(netdev);
9464 err_alloc_etherdev:
9465 pci_release_selected_regions(pdev,
9466 pci_select_bars(pdev, IORESOURCE_MEM));
9467 err_pci_reg:
9468 err_dma:
9469 if (!adapter || disable_dev)
9470 pci_disable_device(pdev);
9471 return err;
9472 }
9473
9474 /**
9475 * ixgbe_remove - Device Removal Routine
9476 * @pdev: PCI device information struct
9477 *
9478 * ixgbe_remove is called by the PCI subsystem to alert the driver
9479 * that it should release a PCI device. The could be caused by a
9480 * Hot-Plug event, or because the driver is going to be removed from
9481 * memory.
9482 **/
9483 static void ixgbe_remove(struct pci_dev *pdev)
9484 {
9485 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9486 struct net_device *netdev;
9487 bool disable_dev;
9488
9489 /* if !adapter then we already cleaned up in probe */
9490 if (!adapter)
9491 return;
9492
9493 netdev = adapter->netdev;
9494 ixgbe_dbg_adapter_exit(adapter);
9495
9496 set_bit(__IXGBE_REMOVING, &adapter->state);
9497 cancel_work_sync(&adapter->service_task);
9498
9499
9500 #ifdef CONFIG_IXGBE_DCA
9501 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
9502 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9503 dca_remove_requester(&pdev->dev);
9504 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
9505 IXGBE_DCA_CTRL_DCA_DISABLE);
9506 }
9507
9508 #endif
9509 #ifdef CONFIG_IXGBE_HWMON
9510 ixgbe_sysfs_exit(adapter);
9511 #endif /* CONFIG_IXGBE_HWMON */
9512
9513 /* remove the added san mac */
9514 ixgbe_del_sanmac_netdev(netdev);
9515
9516 #ifdef CONFIG_PCI_IOV
9517 ixgbe_disable_sriov(adapter);
9518 #endif
9519 if (netdev->reg_state == NETREG_REGISTERED)
9520 unregister_netdev(netdev);
9521
9522 ixgbe_clear_interrupt_scheme(adapter);
9523
9524 ixgbe_release_hw_control(adapter);
9525
9526 #ifdef CONFIG_DCB
9527 kfree(adapter->ixgbe_ieee_pfc);
9528 kfree(adapter->ixgbe_ieee_ets);
9529
9530 #endif
9531 iounmap(adapter->io_addr);
9532 pci_release_selected_regions(pdev, pci_select_bars(pdev,
9533 IORESOURCE_MEM));
9534
9535 e_dev_info("complete\n");
9536
9537 kfree(adapter->mac_table);
9538 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9539 free_netdev(netdev);
9540
9541 pci_disable_pcie_error_reporting(pdev);
9542
9543 if (disable_dev)
9544 pci_disable_device(pdev);
9545 }
9546
9547 /**
9548 * ixgbe_io_error_detected - called when PCI error is detected
9549 * @pdev: Pointer to PCI device
9550 * @state: The current pci connection state
9551 *
9552 * This function is called after a PCI bus error affecting
9553 * this device has been detected.
9554 */
9555 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
9556 pci_channel_state_t state)
9557 {
9558 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9559 struct net_device *netdev = adapter->netdev;
9560
9561 #ifdef CONFIG_PCI_IOV
9562 struct ixgbe_hw *hw = &adapter->hw;
9563 struct pci_dev *bdev, *vfdev;
9564 u32 dw0, dw1, dw2, dw3;
9565 int vf, pos;
9566 u16 req_id, pf_func;
9567
9568 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
9569 adapter->num_vfs == 0)
9570 goto skip_bad_vf_detection;
9571
9572 bdev = pdev->bus->self;
9573 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
9574 bdev = bdev->bus->self;
9575
9576 if (!bdev)
9577 goto skip_bad_vf_detection;
9578
9579 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
9580 if (!pos)
9581 goto skip_bad_vf_detection;
9582
9583 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
9584 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
9585 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
9586 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
9587 if (ixgbe_removed(hw->hw_addr))
9588 goto skip_bad_vf_detection;
9589
9590 req_id = dw1 >> 16;
9591 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
9592 if (!(req_id & 0x0080))
9593 goto skip_bad_vf_detection;
9594
9595 pf_func = req_id & 0x01;
9596 if ((pf_func & 1) == (pdev->devfn & 1)) {
9597 unsigned int device_id;
9598
9599 vf = (req_id & 0x7F) >> 1;
9600 e_dev_err("VF %d has caused a PCIe error\n", vf);
9601 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
9602 "%8.8x\tdw3: %8.8x\n",
9603 dw0, dw1, dw2, dw3);
9604 switch (adapter->hw.mac.type) {
9605 case ixgbe_mac_82599EB:
9606 device_id = IXGBE_82599_VF_DEVICE_ID;
9607 break;
9608 case ixgbe_mac_X540:
9609 device_id = IXGBE_X540_VF_DEVICE_ID;
9610 break;
9611 case ixgbe_mac_X550:
9612 device_id = IXGBE_DEV_ID_X550_VF;
9613 break;
9614 case ixgbe_mac_X550EM_x:
9615 device_id = IXGBE_DEV_ID_X550EM_X_VF;
9616 break;
9617 case ixgbe_mac_x550em_a:
9618 device_id = IXGBE_DEV_ID_X550EM_A_VF;
9619 break;
9620 default:
9621 device_id = 0;
9622 break;
9623 }
9624
9625 /* Find the pci device of the offending VF */
9626 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
9627 while (vfdev) {
9628 if (vfdev->devfn == (req_id & 0xFF))
9629 break;
9630 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
9631 device_id, vfdev);
9632 }
9633 /*
9634 * There's a slim chance the VF could have been hot plugged,
9635 * so if it is no longer present we don't need to issue the
9636 * VFLR. Just clean up the AER in that case.
9637 */
9638 if (vfdev) {
9639 ixgbe_issue_vf_flr(adapter, vfdev);
9640 /* Free device reference count */
9641 pci_dev_put(vfdev);
9642 }
9643
9644 pci_cleanup_aer_uncorrect_error_status(pdev);
9645 }
9646
9647 /*
9648 * Even though the error may have occurred on the other port
9649 * we still need to increment the vf error reference count for
9650 * both ports because the I/O resume function will be called
9651 * for both of them.
9652 */
9653 adapter->vferr_refcount++;
9654
9655 return PCI_ERS_RESULT_RECOVERED;
9656
9657 skip_bad_vf_detection:
9658 #endif /* CONFIG_PCI_IOV */
9659 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
9660 return PCI_ERS_RESULT_DISCONNECT;
9661
9662 rtnl_lock();
9663 netif_device_detach(netdev);
9664
9665 if (state == pci_channel_io_perm_failure) {
9666 rtnl_unlock();
9667 return PCI_ERS_RESULT_DISCONNECT;
9668 }
9669
9670 if (netif_running(netdev))
9671 ixgbe_down(adapter);
9672
9673 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
9674 pci_disable_device(pdev);
9675 rtnl_unlock();
9676
9677 /* Request a slot reset. */
9678 return PCI_ERS_RESULT_NEED_RESET;
9679 }
9680
9681 /**
9682 * ixgbe_io_slot_reset - called after the pci bus has been reset.
9683 * @pdev: Pointer to PCI device
9684 *
9685 * Restart the card from scratch, as if from a cold-boot.
9686 */
9687 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
9688 {
9689 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9690 pci_ers_result_t result;
9691 int err;
9692
9693 if (pci_enable_device_mem(pdev)) {
9694 e_err(probe, "Cannot re-enable PCI device after reset.\n");
9695 result = PCI_ERS_RESULT_DISCONNECT;
9696 } else {
9697 smp_mb__before_atomic();
9698 clear_bit(__IXGBE_DISABLED, &adapter->state);
9699 adapter->hw.hw_addr = adapter->io_addr;
9700 pci_set_master(pdev);
9701 pci_restore_state(pdev);
9702 pci_save_state(pdev);
9703
9704 pci_wake_from_d3(pdev, false);
9705
9706 ixgbe_reset(adapter);
9707 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
9708 result = PCI_ERS_RESULT_RECOVERED;
9709 }
9710
9711 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9712 if (err) {
9713 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
9714 "failed 0x%0x\n", err);
9715 /* non-fatal, continue */
9716 }
9717
9718 return result;
9719 }
9720
9721 /**
9722 * ixgbe_io_resume - called when traffic can start flowing again.
9723 * @pdev: Pointer to PCI device
9724 *
9725 * This callback is called when the error recovery driver tells us that
9726 * its OK to resume normal operation.
9727 */
9728 static void ixgbe_io_resume(struct pci_dev *pdev)
9729 {
9730 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9731 struct net_device *netdev = adapter->netdev;
9732
9733 #ifdef CONFIG_PCI_IOV
9734 if (adapter->vferr_refcount) {
9735 e_info(drv, "Resuming after VF err\n");
9736 adapter->vferr_refcount--;
9737 return;
9738 }
9739
9740 #endif
9741 if (netif_running(netdev))
9742 ixgbe_up(adapter);
9743
9744 netif_device_attach(netdev);
9745 }
9746
9747 static const struct pci_error_handlers ixgbe_err_handler = {
9748 .error_detected = ixgbe_io_error_detected,
9749 .slot_reset = ixgbe_io_slot_reset,
9750 .resume = ixgbe_io_resume,
9751 };
9752
9753 static struct pci_driver ixgbe_driver = {
9754 .name = ixgbe_driver_name,
9755 .id_table = ixgbe_pci_tbl,
9756 .probe = ixgbe_probe,
9757 .remove = ixgbe_remove,
9758 #ifdef CONFIG_PM
9759 .suspend = ixgbe_suspend,
9760 .resume = ixgbe_resume,
9761 #endif
9762 .shutdown = ixgbe_shutdown,
9763 .sriov_configure = ixgbe_pci_sriov_configure,
9764 .err_handler = &ixgbe_err_handler
9765 };
9766
9767 /**
9768 * ixgbe_init_module - Driver Registration Routine
9769 *
9770 * ixgbe_init_module is the first routine called when the driver is
9771 * loaded. All it does is register with the PCI subsystem.
9772 **/
9773 static int __init ixgbe_init_module(void)
9774 {
9775 int ret;
9776 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
9777 pr_info("%s\n", ixgbe_copyright);
9778
9779 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
9780 if (!ixgbe_wq) {
9781 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
9782 return -ENOMEM;
9783 }
9784
9785 ixgbe_dbg_init();
9786
9787 ret = pci_register_driver(&ixgbe_driver);
9788 if (ret) {
9789 ixgbe_dbg_exit();
9790 return ret;
9791 }
9792
9793 #ifdef CONFIG_IXGBE_DCA
9794 dca_register_notify(&dca_notifier);
9795 #endif
9796
9797 return 0;
9798 }
9799
9800 module_init(ixgbe_init_module);
9801
9802 /**
9803 * ixgbe_exit_module - Driver Exit Cleanup Routine
9804 *
9805 * ixgbe_exit_module is called just before the driver is removed
9806 * from memory.
9807 **/
9808 static void __exit ixgbe_exit_module(void)
9809 {
9810 #ifdef CONFIG_IXGBE_DCA
9811 dca_unregister_notify(&dca_notifier);
9812 #endif
9813 pci_unregister_driver(&ixgbe_driver);
9814
9815 ixgbe_dbg_exit();
9816 if (ixgbe_wq) {
9817 destroy_workqueue(ixgbe_wq);
9818 ixgbe_wq = NULL;
9819 }
9820 }
9821
9822 #ifdef CONFIG_IXGBE_DCA
9823 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
9824 void *p)
9825 {
9826 int ret_val;
9827
9828 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
9829 __ixgbe_notify_dca);
9830
9831 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
9832 }
9833
9834 #endif /* CONFIG_IXGBE_DCA */
9835
9836 module_exit(ixgbe_exit_module);
9837
9838 /* ixgbe_main.c */
Linux kernel - Deliverables
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