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Merge branch 'davem-next.r8169' of git://violet.fr.zoreil.com/romieu/linux
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/prefetch.h>
48 #include <scsi/fc/fc_fcoe.h>
49
50 #include "ixgbe.h"
51 #include "ixgbe_common.h"
52 #include "ixgbe_dcb_82599.h"
53 #include "ixgbe_sriov.h"
54
55 char ixgbe_driver_name[] = "ixgbe";
56 static const char ixgbe_driver_string[] =
57 "Intel(R) 10 Gigabit PCI Express Network Driver";
58 #ifdef IXGBE_FCOE
59 char ixgbe_default_device_descr[] =
60 "Intel(R) 10 Gigabit Network Connection";
61 #else
62 static char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
64 #endif
65 #define MAJ 3
66 #define MIN 9
67 #define BUILD 15
68 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
69 __stringify(BUILD) "-k"
70 const char ixgbe_driver_version[] = DRV_VERSION;
71 static const char ixgbe_copyright[] =
72 "Copyright (c) 1999-2012 Intel Corporation.";
73
74 static const struct ixgbe_info *ixgbe_info_tbl[] = {
75 [board_82598] = &ixgbe_82598_info,
76 [board_82599] = &ixgbe_82599_info,
77 [board_X540] = &ixgbe_X540_info,
78 };
79
80 /* ixgbe_pci_tbl - PCI Device ID Table
81 *
82 * Wildcard entries (PCI_ANY_ID) should come last
83 * Last entry must be all 0s
84 *
85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
86 * Class, Class Mask, private data (not used) }
87 */
88 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
117 /* required last entry */
118 {0, }
119 };
120 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121
122 #ifdef CONFIG_IXGBE_DCA
123 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
124 void *p);
125 static struct notifier_block dca_notifier = {
126 .notifier_call = ixgbe_notify_dca,
127 .next = NULL,
128 .priority = 0
129 };
130 #endif
131
132 #ifdef CONFIG_PCI_IOV
133 static unsigned int max_vfs;
134 module_param(max_vfs, uint, 0);
135 MODULE_PARM_DESC(max_vfs,
136 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
137 #endif /* CONFIG_PCI_IOV */
138
139 static unsigned int allow_unsupported_sfp;
140 module_param(allow_unsupported_sfp, uint, 0);
141 MODULE_PARM_DESC(allow_unsupported_sfp,
142 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
143
144 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
145 static int debug = -1;
146 module_param(debug, int, 0);
147 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
148
149 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
150 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
151 MODULE_LICENSE("GPL");
152 MODULE_VERSION(DRV_VERSION);
153
154 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
155 {
156 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
157 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
158 schedule_work(&adapter->service_task);
159 }
160
161 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
162 {
163 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
164
165 /* flush memory to make sure state is correct before next watchdog */
166 smp_mb__before_clear_bit();
167 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
168 }
169
170 struct ixgbe_reg_info {
171 u32 ofs;
172 char *name;
173 };
174
175 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
176
177 /* General Registers */
178 {IXGBE_CTRL, "CTRL"},
179 {IXGBE_STATUS, "STATUS"},
180 {IXGBE_CTRL_EXT, "CTRL_EXT"},
181
182 /* Interrupt Registers */
183 {IXGBE_EICR, "EICR"},
184
185 /* RX Registers */
186 {IXGBE_SRRCTL(0), "SRRCTL"},
187 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
188 {IXGBE_RDLEN(0), "RDLEN"},
189 {IXGBE_RDH(0), "RDH"},
190 {IXGBE_RDT(0), "RDT"},
191 {IXGBE_RXDCTL(0), "RXDCTL"},
192 {IXGBE_RDBAL(0), "RDBAL"},
193 {IXGBE_RDBAH(0), "RDBAH"},
194
195 /* TX Registers */
196 {IXGBE_TDBAL(0), "TDBAL"},
197 {IXGBE_TDBAH(0), "TDBAH"},
198 {IXGBE_TDLEN(0), "TDLEN"},
199 {IXGBE_TDH(0), "TDH"},
200 {IXGBE_TDT(0), "TDT"},
201 {IXGBE_TXDCTL(0), "TXDCTL"},
202
203 /* List Terminator */
204 {}
205 };
206
207
208 /*
209 * ixgbe_regdump - register printout routine
210 */
211 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
212 {
213 int i = 0, j = 0;
214 char rname[16];
215 u32 regs[64];
216
217 switch (reginfo->ofs) {
218 case IXGBE_SRRCTL(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
221 break;
222 case IXGBE_DCA_RXCTRL(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
225 break;
226 case IXGBE_RDLEN(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
229 break;
230 case IXGBE_RDH(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
233 break;
234 case IXGBE_RDT(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
237 break;
238 case IXGBE_RXDCTL(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
241 break;
242 case IXGBE_RDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
245 break;
246 case IXGBE_RDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
249 break;
250 case IXGBE_TDBAL(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
253 break;
254 case IXGBE_TDBAH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
257 break;
258 case IXGBE_TDLEN(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
261 break;
262 case IXGBE_TDH(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
265 break;
266 case IXGBE_TDT(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
269 break;
270 case IXGBE_TXDCTL(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
273 break;
274 default:
275 pr_info("%-15s %08x\n", reginfo->name,
276 IXGBE_READ_REG(hw, reginfo->ofs));
277 return;
278 }
279
280 for (i = 0; i < 8; i++) {
281 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
282 pr_err("%-15s", rname);
283 for (j = 0; j < 8; j++)
284 pr_cont(" %08x", regs[i*8+j]);
285 pr_cont("\n");
286 }
287
288 }
289
290 /*
291 * ixgbe_dump - Print registers, tx-rings and rx-rings
292 */
293 static void ixgbe_dump(struct ixgbe_adapter *adapter)
294 {
295 struct net_device *netdev = adapter->netdev;
296 struct ixgbe_hw *hw = &adapter->hw;
297 struct ixgbe_reg_info *reginfo;
298 int n = 0;
299 struct ixgbe_ring *tx_ring;
300 struct ixgbe_tx_buffer *tx_buffer;
301 union ixgbe_adv_tx_desc *tx_desc;
302 struct my_u0 { u64 a; u64 b; } *u0;
303 struct ixgbe_ring *rx_ring;
304 union ixgbe_adv_rx_desc *rx_desc;
305 struct ixgbe_rx_buffer *rx_buffer_info;
306 u32 staterr;
307 int i = 0;
308
309 if (!netif_msg_hw(adapter))
310 return;
311
312 /* Print netdevice Info */
313 if (netdev) {
314 dev_info(&adapter->pdev->dev, "Net device Info\n");
315 pr_info("Device Name state "
316 "trans_start last_rx\n");
317 pr_info("%-15s %016lX %016lX %016lX\n",
318 netdev->name,
319 netdev->state,
320 netdev->trans_start,
321 netdev->last_rx);
322 }
323
324 /* Print Registers */
325 dev_info(&adapter->pdev->dev, "Register Dump\n");
326 pr_info(" Register Name Value\n");
327 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
328 reginfo->name; reginfo++) {
329 ixgbe_regdump(hw, reginfo);
330 }
331
332 /* Print TX Ring Summary */
333 if (!netdev || !netif_running(netdev))
334 goto exit;
335
336 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
337 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
338 for (n = 0; n < adapter->num_tx_queues; n++) {
339 tx_ring = adapter->tx_ring[n];
340 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
341 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
342 n, tx_ring->next_to_use, tx_ring->next_to_clean,
343 (u64)dma_unmap_addr(tx_buffer, dma),
344 dma_unmap_len(tx_buffer, len),
345 tx_buffer->next_to_watch,
346 (u64)tx_buffer->time_stamp);
347 }
348
349 /* Print TX Rings */
350 if (!netif_msg_tx_done(adapter))
351 goto rx_ring_summary;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
354
355 /* Transmit Descriptor Formats
356 *
357 * Advanced Transmit Descriptor
358 * +--------------------------------------------------------------+
359 * 0 | Buffer Address [63:0] |
360 * +--------------------------------------------------------------+
361 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
362 * +--------------------------------------------------------------+
363 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
364 */
365
366 for (n = 0; n < adapter->num_tx_queues; n++) {
367 tx_ring = adapter->tx_ring[n];
368 pr_info("------------------------------------\n");
369 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
370 pr_info("------------------------------------\n");
371 pr_info("T [desc] [address 63:0 ] "
372 "[PlPOIdStDDt Ln] [bi->dma ] "
373 "leng ntw timestamp bi->skb\n");
374
375 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
376 tx_desc = IXGBE_TX_DESC(tx_ring, i);
377 tx_buffer = &tx_ring->tx_buffer_info[i];
378 u0 = (struct my_u0 *)tx_desc;
379 pr_info("T [0x%03X] %016llX %016llX %016llX"
380 " %04X %p %016llX %p", i,
381 le64_to_cpu(u0->a),
382 le64_to_cpu(u0->b),
383 (u64)dma_unmap_addr(tx_buffer, dma),
384 dma_unmap_len(tx_buffer, len),
385 tx_buffer->next_to_watch,
386 (u64)tx_buffer->time_stamp,
387 tx_buffer->skb);
388 if (i == tx_ring->next_to_use &&
389 i == tx_ring->next_to_clean)
390 pr_cont(" NTC/U\n");
391 else if (i == tx_ring->next_to_use)
392 pr_cont(" NTU\n");
393 else if (i == tx_ring->next_to_clean)
394 pr_cont(" NTC\n");
395 else
396 pr_cont("\n");
397
398 if (netif_msg_pktdata(adapter) &&
399 dma_unmap_len(tx_buffer, len) != 0)
400 print_hex_dump(KERN_INFO, "",
401 DUMP_PREFIX_ADDRESS, 16, 1,
402 phys_to_virt(dma_unmap_addr(tx_buffer,
403 dma)),
404 dma_unmap_len(tx_buffer, len),
405 true);
406 }
407 }
408
409 /* Print RX Rings Summary */
410 rx_ring_summary:
411 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
412 pr_info("Queue [NTU] [NTC]\n");
413 for (n = 0; n < adapter->num_rx_queues; n++) {
414 rx_ring = adapter->rx_ring[n];
415 pr_info("%5d %5X %5X\n",
416 n, rx_ring->next_to_use, rx_ring->next_to_clean);
417 }
418
419 /* Print RX Rings */
420 if (!netif_msg_rx_status(adapter))
421 goto exit;
422
423 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
424
425 /* Advanced Receive Descriptor (Read) Format
426 * 63 1 0
427 * +-----------------------------------------------------+
428 * 0 | Packet Buffer Address [63:1] |A0/NSE|
429 * +----------------------------------------------+------+
430 * 8 | Header Buffer Address [63:1] | DD |
431 * +-----------------------------------------------------+
432 *
433 *
434 * Advanced Receive Descriptor (Write-Back) Format
435 *
436 * 63 48 47 32 31 30 21 20 16 15 4 3 0
437 * +------------------------------------------------------+
438 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
439 * | Checksum Ident | | | | Type | Type |
440 * +------------------------------------------------------+
441 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
442 * +------------------------------------------------------+
443 * 63 48 47 32 31 20 19 0
444 */
445 for (n = 0; n < adapter->num_rx_queues; n++) {
446 rx_ring = adapter->rx_ring[n];
447 pr_info("------------------------------------\n");
448 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
449 pr_info("------------------------------------\n");
450 pr_info("R [desc] [ PktBuf A0] "
451 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
452 "<-- Adv Rx Read format\n");
453 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
454 "[vl er S cks ln] ---------------- [bi->skb] "
455 "<-- Adv Rx Write-Back format\n");
456
457 for (i = 0; i < rx_ring->count; i++) {
458 rx_buffer_info = &rx_ring->rx_buffer_info[i];
459 rx_desc = IXGBE_RX_DESC(rx_ring, i);
460 u0 = (struct my_u0 *)rx_desc;
461 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
462 if (staterr & IXGBE_RXD_STAT_DD) {
463 /* Descriptor Done */
464 pr_info("RWB[0x%03X] %016llX "
465 "%016llX ---------------- %p", i,
466 le64_to_cpu(u0->a),
467 le64_to_cpu(u0->b),
468 rx_buffer_info->skb);
469 } else {
470 pr_info("R [0x%03X] %016llX "
471 "%016llX %016llX %p", i,
472 le64_to_cpu(u0->a),
473 le64_to_cpu(u0->b),
474 (u64)rx_buffer_info->dma,
475 rx_buffer_info->skb);
476
477 if (netif_msg_pktdata(adapter)) {
478 print_hex_dump(KERN_INFO, "",
479 DUMP_PREFIX_ADDRESS, 16, 1,
480 phys_to_virt(rx_buffer_info->dma),
481 ixgbe_rx_bufsz(rx_ring), true);
482 }
483 }
484
485 if (i == rx_ring->next_to_use)
486 pr_cont(" NTU\n");
487 else if (i == rx_ring->next_to_clean)
488 pr_cont(" NTC\n");
489 else
490 pr_cont("\n");
491
492 }
493 }
494
495 exit:
496 return;
497 }
498
499 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
500 {
501 u32 ctrl_ext;
502
503 /* Let firmware take over control of h/w */
504 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
505 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
506 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
507 }
508
509 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
510 {
511 u32 ctrl_ext;
512
513 /* Let firmware know the driver has taken over */
514 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
515 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
516 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
517 }
518
519 /**
520 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
521 * @adapter: pointer to adapter struct
522 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
523 * @queue: queue to map the corresponding interrupt to
524 * @msix_vector: the vector to map to the corresponding queue
525 *
526 */
527 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
528 u8 queue, u8 msix_vector)
529 {
530 u32 ivar, index;
531 struct ixgbe_hw *hw = &adapter->hw;
532 switch (hw->mac.type) {
533 case ixgbe_mac_82598EB:
534 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
535 if (direction == -1)
536 direction = 0;
537 index = (((direction * 64) + queue) >> 2) & 0x1F;
538 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
539 ivar &= ~(0xFF << (8 * (queue & 0x3)));
540 ivar |= (msix_vector << (8 * (queue & 0x3)));
541 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
542 break;
543 case ixgbe_mac_82599EB:
544 case ixgbe_mac_X540:
545 if (direction == -1) {
546 /* other causes */
547 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
548 index = ((queue & 1) * 8);
549 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
550 ivar &= ~(0xFF << index);
551 ivar |= (msix_vector << index);
552 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
553 break;
554 } else {
555 /* tx or rx causes */
556 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
557 index = ((16 * (queue & 1)) + (8 * direction));
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
559 ivar &= ~(0xFF << index);
560 ivar |= (msix_vector << index);
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
562 break;
563 }
564 default:
565 break;
566 }
567 }
568
569 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
570 u64 qmask)
571 {
572 u32 mask;
573
574 switch (adapter->hw.mac.type) {
575 case ixgbe_mac_82598EB:
576 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
577 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
578 break;
579 case ixgbe_mac_82599EB:
580 case ixgbe_mac_X540:
581 mask = (qmask & 0xFFFFFFFF);
582 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
583 mask = (qmask >> 32);
584 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
585 break;
586 default:
587 break;
588 }
589 }
590
591 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
592 struct ixgbe_tx_buffer *tx_buffer)
593 {
594 if (tx_buffer->skb) {
595 dev_kfree_skb_any(tx_buffer->skb);
596 if (dma_unmap_len(tx_buffer, len))
597 dma_unmap_single(ring->dev,
598 dma_unmap_addr(tx_buffer, dma),
599 dma_unmap_len(tx_buffer, len),
600 DMA_TO_DEVICE);
601 } else if (dma_unmap_len(tx_buffer, len)) {
602 dma_unmap_page(ring->dev,
603 dma_unmap_addr(tx_buffer, dma),
604 dma_unmap_len(tx_buffer, len),
605 DMA_TO_DEVICE);
606 }
607 tx_buffer->next_to_watch = NULL;
608 tx_buffer->skb = NULL;
609 dma_unmap_len_set(tx_buffer, len, 0);
610 /* tx_buffer must be completely set up in the transmit path */
611 }
612
613 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
614 {
615 struct ixgbe_hw *hw = &adapter->hw;
616 struct ixgbe_hw_stats *hwstats = &adapter->stats;
617 int i;
618 u32 data;
619
620 if ((hw->fc.current_mode != ixgbe_fc_full) &&
621 (hw->fc.current_mode != ixgbe_fc_rx_pause))
622 return;
623
624 switch (hw->mac.type) {
625 case ixgbe_mac_82598EB:
626 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
627 break;
628 default:
629 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
630 }
631 hwstats->lxoffrxc += data;
632
633 /* refill credits (no tx hang) if we received xoff */
634 if (!data)
635 return;
636
637 for (i = 0; i < adapter->num_tx_queues; i++)
638 clear_bit(__IXGBE_HANG_CHECK_ARMED,
639 &adapter->tx_ring[i]->state);
640 }
641
642 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
643 {
644 struct ixgbe_hw *hw = &adapter->hw;
645 struct ixgbe_hw_stats *hwstats = &adapter->stats;
646 u32 xoff[8] = {0};
647 int i;
648 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
649
650 if (adapter->ixgbe_ieee_pfc)
651 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
652
653 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
654 ixgbe_update_xoff_rx_lfc(adapter);
655 return;
656 }
657
658 /* update stats for each tc, only valid with PFC enabled */
659 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
660 switch (hw->mac.type) {
661 case ixgbe_mac_82598EB:
662 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
663 break;
664 default:
665 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
666 }
667 hwstats->pxoffrxc[i] += xoff[i];
668 }
669
670 /* disarm tx queues that have received xoff frames */
671 for (i = 0; i < adapter->num_tx_queues; i++) {
672 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
673 u8 tc = tx_ring->dcb_tc;
674
675 if (xoff[tc])
676 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
677 }
678 }
679
680 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
681 {
682 return ring->stats.packets;
683 }
684
685 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
686 {
687 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
688 struct ixgbe_hw *hw = &adapter->hw;
689
690 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
691 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
692
693 if (head != tail)
694 return (head < tail) ?
695 tail - head : (tail + ring->count - head);
696
697 return 0;
698 }
699
700 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
701 {
702 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
703 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
704 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
705 bool ret = false;
706
707 clear_check_for_tx_hang(tx_ring);
708
709 /*
710 * Check for a hung queue, but be thorough. This verifies
711 * that a transmit has been completed since the previous
712 * check AND there is at least one packet pending. The
713 * ARMED bit is set to indicate a potential hang. The
714 * bit is cleared if a pause frame is received to remove
715 * false hang detection due to PFC or 802.3x frames. By
716 * requiring this to fail twice we avoid races with
717 * pfc clearing the ARMED bit and conditions where we
718 * run the check_tx_hang logic with a transmit completion
719 * pending but without time to complete it yet.
720 */
721 if ((tx_done_old == tx_done) && tx_pending) {
722 /* make sure it is true for two checks in a row */
723 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
724 &tx_ring->state);
725 } else {
726 /* update completed stats and continue */
727 tx_ring->tx_stats.tx_done_old = tx_done;
728 /* reset the countdown */
729 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
730 }
731
732 return ret;
733 }
734
735 /**
736 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
737 * @adapter: driver private struct
738 **/
739 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
740 {
741
742 /* Do the reset outside of interrupt context */
743 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
744 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
745 ixgbe_service_event_schedule(adapter);
746 }
747 }
748
749 /**
750 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
751 * @q_vector: structure containing interrupt and ring information
752 * @tx_ring: tx ring to clean
753 **/
754 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
755 struct ixgbe_ring *tx_ring)
756 {
757 struct ixgbe_adapter *adapter = q_vector->adapter;
758 struct ixgbe_tx_buffer *tx_buffer;
759 union ixgbe_adv_tx_desc *tx_desc;
760 unsigned int total_bytes = 0, total_packets = 0;
761 unsigned int budget = q_vector->tx.work_limit;
762 unsigned int i = tx_ring->next_to_clean;
763
764 if (test_bit(__IXGBE_DOWN, &adapter->state))
765 return true;
766
767 tx_buffer = &tx_ring->tx_buffer_info[i];
768 tx_desc = IXGBE_TX_DESC(tx_ring, i);
769 i -= tx_ring->count;
770
771 do {
772 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
773
774 /* if next_to_watch is not set then there is no work pending */
775 if (!eop_desc)
776 break;
777
778 /* prevent any other reads prior to eop_desc */
779 rmb();
780
781 /* if DD is not set pending work has not been completed */
782 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
783 break;
784
785 /* clear next_to_watch to prevent false hangs */
786 tx_buffer->next_to_watch = NULL;
787
788 /* update the statistics for this packet */
789 total_bytes += tx_buffer->bytecount;
790 total_packets += tx_buffer->gso_segs;
791
792 #ifdef CONFIG_IXGBE_PTP
793 if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP))
794 ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb);
795 #endif
796
797 /* free the skb */
798 dev_kfree_skb_any(tx_buffer->skb);
799
800 /* unmap skb header data */
801 dma_unmap_single(tx_ring->dev,
802 dma_unmap_addr(tx_buffer, dma),
803 dma_unmap_len(tx_buffer, len),
804 DMA_TO_DEVICE);
805
806 /* clear tx_buffer data */
807 tx_buffer->skb = NULL;
808 dma_unmap_len_set(tx_buffer, len, 0);
809
810 /* unmap remaining buffers */
811 while (tx_desc != eop_desc) {
812 tx_buffer++;
813 tx_desc++;
814 i++;
815 if (unlikely(!i)) {
816 i -= tx_ring->count;
817 tx_buffer = tx_ring->tx_buffer_info;
818 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
819 }
820
821 /* unmap any remaining paged data */
822 if (dma_unmap_len(tx_buffer, len)) {
823 dma_unmap_page(tx_ring->dev,
824 dma_unmap_addr(tx_buffer, dma),
825 dma_unmap_len(tx_buffer, len),
826 DMA_TO_DEVICE);
827 dma_unmap_len_set(tx_buffer, len, 0);
828 }
829 }
830
831 /* move us one more past the eop_desc for start of next pkt */
832 tx_buffer++;
833 tx_desc++;
834 i++;
835 if (unlikely(!i)) {
836 i -= tx_ring->count;
837 tx_buffer = tx_ring->tx_buffer_info;
838 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
839 }
840
841 /* issue prefetch for next Tx descriptor */
842 prefetch(tx_desc);
843
844 /* update budget accounting */
845 budget--;
846 } while (likely(budget));
847
848 i += tx_ring->count;
849 tx_ring->next_to_clean = i;
850 u64_stats_update_begin(&tx_ring->syncp);
851 tx_ring->stats.bytes += total_bytes;
852 tx_ring->stats.packets += total_packets;
853 u64_stats_update_end(&tx_ring->syncp);
854 q_vector->tx.total_bytes += total_bytes;
855 q_vector->tx.total_packets += total_packets;
856
857 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
858 /* schedule immediate reset if we believe we hung */
859 struct ixgbe_hw *hw = &adapter->hw;
860 e_err(drv, "Detected Tx Unit Hang\n"
861 " Tx Queue <%d>\n"
862 " TDH, TDT <%x>, <%x>\n"
863 " next_to_use <%x>\n"
864 " next_to_clean <%x>\n"
865 "tx_buffer_info[next_to_clean]\n"
866 " time_stamp <%lx>\n"
867 " jiffies <%lx>\n",
868 tx_ring->queue_index,
869 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
870 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
871 tx_ring->next_to_use, i,
872 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
873
874 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
875
876 e_info(probe,
877 "tx hang %d detected on queue %d, resetting adapter\n",
878 adapter->tx_timeout_count + 1, tx_ring->queue_index);
879
880 /* schedule immediate reset if we believe we hung */
881 ixgbe_tx_timeout_reset(adapter);
882
883 /* the adapter is about to reset, no point in enabling stuff */
884 return true;
885 }
886
887 netdev_tx_completed_queue(txring_txq(tx_ring),
888 total_packets, total_bytes);
889
890 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
891 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
892 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
893 /* Make sure that anybody stopping the queue after this
894 * sees the new next_to_clean.
895 */
896 smp_mb();
897 if (__netif_subqueue_stopped(tx_ring->netdev,
898 tx_ring->queue_index)
899 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
900 netif_wake_subqueue(tx_ring->netdev,
901 tx_ring->queue_index);
902 ++tx_ring->tx_stats.restart_queue;
903 }
904 }
905
906 return !!budget;
907 }
908
909 #ifdef CONFIG_IXGBE_DCA
910 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
911 struct ixgbe_ring *tx_ring,
912 int cpu)
913 {
914 struct ixgbe_hw *hw = &adapter->hw;
915 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
916 u16 reg_offset;
917
918 switch (hw->mac.type) {
919 case ixgbe_mac_82598EB:
920 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
921 break;
922 case ixgbe_mac_82599EB:
923 case ixgbe_mac_X540:
924 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
925 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
926 break;
927 default:
928 /* for unknown hardware do not write register */
929 return;
930 }
931
932 /*
933 * We can enable relaxed ordering for reads, but not writes when
934 * DCA is enabled. This is due to a known issue in some chipsets
935 * which will cause the DCA tag to be cleared.
936 */
937 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
938 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
939 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
940
941 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
942 }
943
944 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
945 struct ixgbe_ring *rx_ring,
946 int cpu)
947 {
948 struct ixgbe_hw *hw = &adapter->hw;
949 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
950 u8 reg_idx = rx_ring->reg_idx;
951
952
953 switch (hw->mac.type) {
954 case ixgbe_mac_82599EB:
955 case ixgbe_mac_X540:
956 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
957 break;
958 default:
959 break;
960 }
961
962 /*
963 * We can enable relaxed ordering for reads, but not writes when
964 * DCA is enabled. This is due to a known issue in some chipsets
965 * which will cause the DCA tag to be cleared.
966 */
967 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
968 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
969 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
970
971 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
972 }
973
974 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
975 {
976 struct ixgbe_adapter *adapter = q_vector->adapter;
977 struct ixgbe_ring *ring;
978 int cpu = get_cpu();
979
980 if (q_vector->cpu == cpu)
981 goto out_no_update;
982
983 ixgbe_for_each_ring(ring, q_vector->tx)
984 ixgbe_update_tx_dca(adapter, ring, cpu);
985
986 ixgbe_for_each_ring(ring, q_vector->rx)
987 ixgbe_update_rx_dca(adapter, ring, cpu);
988
989 q_vector->cpu = cpu;
990 out_no_update:
991 put_cpu();
992 }
993
994 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
995 {
996 int num_q_vectors;
997 int i;
998
999 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1000 return;
1001
1002 /* always use CB2 mode, difference is masked in the CB driver */
1003 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1004
1005 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1006 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1007 else
1008 num_q_vectors = 1;
1009
1010 for (i = 0; i < num_q_vectors; i++) {
1011 adapter->q_vector[i]->cpu = -1;
1012 ixgbe_update_dca(adapter->q_vector[i]);
1013 }
1014 }
1015
1016 static int __ixgbe_notify_dca(struct device *dev, void *data)
1017 {
1018 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1019 unsigned long event = *(unsigned long *)data;
1020
1021 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1022 return 0;
1023
1024 switch (event) {
1025 case DCA_PROVIDER_ADD:
1026 /* if we're already enabled, don't do it again */
1027 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1028 break;
1029 if (dca_add_requester(dev) == 0) {
1030 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1031 ixgbe_setup_dca(adapter);
1032 break;
1033 }
1034 /* Fall Through since DCA is disabled. */
1035 case DCA_PROVIDER_REMOVE:
1036 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1037 dca_remove_requester(dev);
1038 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1039 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1040 }
1041 break;
1042 }
1043
1044 return 0;
1045 }
1046
1047 #endif /* CONFIG_IXGBE_DCA */
1048 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1049 union ixgbe_adv_rx_desc *rx_desc,
1050 struct sk_buff *skb)
1051 {
1052 if (ring->netdev->features & NETIF_F_RXHASH)
1053 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1054 }
1055
1056 #ifdef IXGBE_FCOE
1057 /**
1058 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1059 * @ring: structure containing ring specific data
1060 * @rx_desc: advanced rx descriptor
1061 *
1062 * Returns : true if it is FCoE pkt
1063 */
1064 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1065 union ixgbe_adv_rx_desc *rx_desc)
1066 {
1067 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1068
1069 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1070 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1071 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1072 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1073 }
1074
1075 #endif /* IXGBE_FCOE */
1076 /**
1077 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1078 * @ring: structure containing ring specific data
1079 * @rx_desc: current Rx descriptor being processed
1080 * @skb: skb currently being received and modified
1081 **/
1082 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1083 union ixgbe_adv_rx_desc *rx_desc,
1084 struct sk_buff *skb)
1085 {
1086 skb_checksum_none_assert(skb);
1087
1088 /* Rx csum disabled */
1089 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1090 return;
1091
1092 /* if IP and error */
1093 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1094 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1095 ring->rx_stats.csum_err++;
1096 return;
1097 }
1098
1099 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1100 return;
1101
1102 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1103 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1104
1105 /*
1106 * 82599 errata, UDP frames with a 0 checksum can be marked as
1107 * checksum errors.
1108 */
1109 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1110 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1111 return;
1112
1113 ring->rx_stats.csum_err++;
1114 return;
1115 }
1116
1117 /* It must be a TCP or UDP packet with a valid checksum */
1118 skb->ip_summed = CHECKSUM_UNNECESSARY;
1119 }
1120
1121 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1122 {
1123 rx_ring->next_to_use = val;
1124
1125 /* update next to alloc since we have filled the ring */
1126 rx_ring->next_to_alloc = val;
1127 /*
1128 * Force memory writes to complete before letting h/w
1129 * know there are new descriptors to fetch. (Only
1130 * applicable for weak-ordered memory model archs,
1131 * such as IA-64).
1132 */
1133 wmb();
1134 writel(val, rx_ring->tail);
1135 }
1136
1137 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1138 struct ixgbe_rx_buffer *bi)
1139 {
1140 struct page *page = bi->page;
1141 dma_addr_t dma = bi->dma;
1142
1143 /* since we are recycling buffers we should seldom need to alloc */
1144 if (likely(dma))
1145 return true;
1146
1147 /* alloc new page for storage */
1148 if (likely(!page)) {
1149 page = alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1150 ixgbe_rx_pg_order(rx_ring));
1151 if (unlikely(!page)) {
1152 rx_ring->rx_stats.alloc_rx_page_failed++;
1153 return false;
1154 }
1155 bi->page = page;
1156 }
1157
1158 /* map page for use */
1159 dma = dma_map_page(rx_ring->dev, page, 0,
1160 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1161
1162 /*
1163 * if mapping failed free memory back to system since
1164 * there isn't much point in holding memory we can't use
1165 */
1166 if (dma_mapping_error(rx_ring->dev, dma)) {
1167 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1168 bi->page = NULL;
1169
1170 rx_ring->rx_stats.alloc_rx_page_failed++;
1171 return false;
1172 }
1173
1174 bi->dma = dma;
1175 bi->page_offset ^= ixgbe_rx_bufsz(rx_ring);
1176
1177 return true;
1178 }
1179
1180 /**
1181 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1182 * @rx_ring: ring to place buffers on
1183 * @cleaned_count: number of buffers to replace
1184 **/
1185 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1186 {
1187 union ixgbe_adv_rx_desc *rx_desc;
1188 struct ixgbe_rx_buffer *bi;
1189 u16 i = rx_ring->next_to_use;
1190
1191 /* nothing to do */
1192 if (!cleaned_count)
1193 return;
1194
1195 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1196 bi = &rx_ring->rx_buffer_info[i];
1197 i -= rx_ring->count;
1198
1199 do {
1200 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1201 break;
1202
1203 /*
1204 * Refresh the desc even if buffer_addrs didn't change
1205 * because each write-back erases this info.
1206 */
1207 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1208
1209 rx_desc++;
1210 bi++;
1211 i++;
1212 if (unlikely(!i)) {
1213 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1214 bi = rx_ring->rx_buffer_info;
1215 i -= rx_ring->count;
1216 }
1217
1218 /* clear the hdr_addr for the next_to_use descriptor */
1219 rx_desc->read.hdr_addr = 0;
1220
1221 cleaned_count--;
1222 } while (cleaned_count);
1223
1224 i += rx_ring->count;
1225
1226 if (rx_ring->next_to_use != i)
1227 ixgbe_release_rx_desc(rx_ring, i);
1228 }
1229
1230 /**
1231 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1232 * @data: pointer to the start of the headers
1233 * @max_len: total length of section to find headers in
1234 *
1235 * This function is meant to determine the length of headers that will
1236 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1237 * motivation of doing this is to only perform one pull for IPv4 TCP
1238 * packets so that we can do basic things like calculating the gso_size
1239 * based on the average data per packet.
1240 **/
1241 static unsigned int ixgbe_get_headlen(unsigned char *data,
1242 unsigned int max_len)
1243 {
1244 union {
1245 unsigned char *network;
1246 /* l2 headers */
1247 struct ethhdr *eth;
1248 struct vlan_hdr *vlan;
1249 /* l3 headers */
1250 struct iphdr *ipv4;
1251 } hdr;
1252 __be16 protocol;
1253 u8 nexthdr = 0; /* default to not TCP */
1254 u8 hlen;
1255
1256 /* this should never happen, but better safe than sorry */
1257 if (max_len < ETH_HLEN)
1258 return max_len;
1259
1260 /* initialize network frame pointer */
1261 hdr.network = data;
1262
1263 /* set first protocol and move network header forward */
1264 protocol = hdr.eth->h_proto;
1265 hdr.network += ETH_HLEN;
1266
1267 /* handle any vlan tag if present */
1268 if (protocol == __constant_htons(ETH_P_8021Q)) {
1269 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1270 return max_len;
1271
1272 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1273 hdr.network += VLAN_HLEN;
1274 }
1275
1276 /* handle L3 protocols */
1277 if (protocol == __constant_htons(ETH_P_IP)) {
1278 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1279 return max_len;
1280
1281 /* access ihl as a u8 to avoid unaligned access on ia64 */
1282 hlen = (hdr.network[0] & 0x0F) << 2;
1283
1284 /* verify hlen meets minimum size requirements */
1285 if (hlen < sizeof(struct iphdr))
1286 return hdr.network - data;
1287
1288 /* record next protocol */
1289 nexthdr = hdr.ipv4->protocol;
1290 hdr.network += hlen;
1291 #ifdef IXGBE_FCOE
1292 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1293 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1294 return max_len;
1295 hdr.network += FCOE_HEADER_LEN;
1296 #endif
1297 } else {
1298 return hdr.network - data;
1299 }
1300
1301 /* finally sort out TCP */
1302 if (nexthdr == IPPROTO_TCP) {
1303 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1304 return max_len;
1305
1306 /* access doff as a u8 to avoid unaligned access on ia64 */
1307 hlen = (hdr.network[12] & 0xF0) >> 2;
1308
1309 /* verify hlen meets minimum size requirements */
1310 if (hlen < sizeof(struct tcphdr))
1311 return hdr.network - data;
1312
1313 hdr.network += hlen;
1314 }
1315
1316 /*
1317 * If everything has gone correctly hdr.network should be the
1318 * data section of the packet and will be the end of the header.
1319 * If not then it probably represents the end of the last recognized
1320 * header.
1321 */
1322 if ((hdr.network - data) < max_len)
1323 return hdr.network - data;
1324 else
1325 return max_len;
1326 }
1327
1328 static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1329 union ixgbe_adv_rx_desc *rx_desc,
1330 struct sk_buff *skb)
1331 {
1332 __le32 rsc_enabled;
1333 u32 rsc_cnt;
1334
1335 if (!ring_is_rsc_enabled(rx_ring))
1336 return;
1337
1338 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1339 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1340
1341 /* If this is an RSC frame rsc_cnt should be non-zero */
1342 if (!rsc_enabled)
1343 return;
1344
1345 rsc_cnt = le32_to_cpu(rsc_enabled);
1346 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1347
1348 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1349 }
1350
1351 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1352 struct sk_buff *skb)
1353 {
1354 u16 hdr_len = skb_headlen(skb);
1355
1356 /* set gso_size to avoid messing up TCP MSS */
1357 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1358 IXGBE_CB(skb)->append_cnt);
1359 }
1360
1361 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1362 struct sk_buff *skb)
1363 {
1364 /* if append_cnt is 0 then frame is not RSC */
1365 if (!IXGBE_CB(skb)->append_cnt)
1366 return;
1367
1368 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1369 rx_ring->rx_stats.rsc_flush++;
1370
1371 ixgbe_set_rsc_gso_size(rx_ring, skb);
1372
1373 /* gso_size is computed using append_cnt so always clear it last */
1374 IXGBE_CB(skb)->append_cnt = 0;
1375 }
1376
1377 /**
1378 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1379 * @rx_ring: rx descriptor ring packet is being transacted on
1380 * @rx_desc: pointer to the EOP Rx descriptor
1381 * @skb: pointer to current skb being populated
1382 *
1383 * This function checks the ring, descriptor, and packet information in
1384 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1385 * other fields within the skb.
1386 **/
1387 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1388 union ixgbe_adv_rx_desc *rx_desc,
1389 struct sk_buff *skb)
1390 {
1391 struct net_device *dev = rx_ring->netdev;
1392
1393 ixgbe_update_rsc_stats(rx_ring, skb);
1394
1395 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1396
1397 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1398
1399 #ifdef CONFIG_IXGBE_PTP
1400 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
1401 #endif
1402
1403 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1404 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1405 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1406 __vlan_hwaccel_put_tag(skb, vid);
1407 }
1408
1409 skb_record_rx_queue(skb, rx_ring->queue_index);
1410
1411 skb->protocol = eth_type_trans(skb, dev);
1412 }
1413
1414 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1415 struct sk_buff *skb)
1416 {
1417 struct ixgbe_adapter *adapter = q_vector->adapter;
1418
1419 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1420 napi_gro_receive(&q_vector->napi, skb);
1421 else
1422 netif_rx(skb);
1423 }
1424
1425 /**
1426 * ixgbe_is_non_eop - process handling of non-EOP buffers
1427 * @rx_ring: Rx ring being processed
1428 * @rx_desc: Rx descriptor for current buffer
1429 * @skb: Current socket buffer containing buffer in progress
1430 *
1431 * This function updates next to clean. If the buffer is an EOP buffer
1432 * this function exits returning false, otherwise it will place the
1433 * sk_buff in the next buffer to be chained and return true indicating
1434 * that this is in fact a non-EOP buffer.
1435 **/
1436 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1437 union ixgbe_adv_rx_desc *rx_desc,
1438 struct sk_buff *skb)
1439 {
1440 u32 ntc = rx_ring->next_to_clean + 1;
1441
1442 /* fetch, update, and store next to clean */
1443 ntc = (ntc < rx_ring->count) ? ntc : 0;
1444 rx_ring->next_to_clean = ntc;
1445
1446 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1447
1448 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1449 return false;
1450
1451 /* append_cnt indicates packet is RSC, if so fetch nextp */
1452 if (IXGBE_CB(skb)->append_cnt) {
1453 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1454 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1455 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1456 }
1457
1458 /* place skb in next buffer to be received */
1459 rx_ring->rx_buffer_info[ntc].skb = skb;
1460 rx_ring->rx_stats.non_eop_descs++;
1461
1462 return true;
1463 }
1464
1465 /**
1466 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1467 * @rx_ring: rx descriptor ring packet is being transacted on
1468 * @rx_desc: pointer to the EOP Rx descriptor
1469 * @skb: pointer to current skb being fixed
1470 *
1471 * Check for corrupted packet headers caused by senders on the local L2
1472 * embedded NIC switch not setting up their Tx Descriptors right. These
1473 * should be very rare.
1474 *
1475 * Also address the case where we are pulling data in on pages only
1476 * and as such no data is present in the skb header.
1477 *
1478 * In addition if skb is not at least 60 bytes we need to pad it so that
1479 * it is large enough to qualify as a valid Ethernet frame.
1480 *
1481 * Returns true if an error was encountered and skb was freed.
1482 **/
1483 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1484 union ixgbe_adv_rx_desc *rx_desc,
1485 struct sk_buff *skb)
1486 {
1487 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1488 struct net_device *netdev = rx_ring->netdev;
1489 unsigned char *va;
1490 unsigned int pull_len;
1491
1492 /* if the page was released unmap it, else just sync our portion */
1493 if (unlikely(IXGBE_CB(skb)->page_released)) {
1494 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1495 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1496 IXGBE_CB(skb)->page_released = false;
1497 } else {
1498 dma_sync_single_range_for_cpu(rx_ring->dev,
1499 IXGBE_CB(skb)->dma,
1500 frag->page_offset,
1501 ixgbe_rx_bufsz(rx_ring),
1502 DMA_FROM_DEVICE);
1503 }
1504 IXGBE_CB(skb)->dma = 0;
1505
1506 /* verify that the packet does not have any known errors */
1507 if (unlikely(ixgbe_test_staterr(rx_desc,
1508 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1509 !(netdev->features & NETIF_F_RXALL))) {
1510 dev_kfree_skb_any(skb);
1511 return true;
1512 }
1513
1514 /*
1515 * it is valid to use page_address instead of kmap since we are
1516 * working with pages allocated out of the lomem pool per
1517 * alloc_page(GFP_ATOMIC)
1518 */
1519 va = skb_frag_address(frag);
1520
1521 /*
1522 * we need the header to contain the greater of either ETH_HLEN or
1523 * 60 bytes if the skb->len is less than 60 for skb_pad.
1524 */
1525 pull_len = skb_frag_size(frag);
1526 if (pull_len > 256)
1527 pull_len = ixgbe_get_headlen(va, pull_len);
1528
1529 /* align pull length to size of long to optimize memcpy performance */
1530 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1531
1532 /* update all of the pointers */
1533 skb_frag_size_sub(frag, pull_len);
1534 frag->page_offset += pull_len;
1535 skb->data_len -= pull_len;
1536 skb->tail += pull_len;
1537
1538 /*
1539 * if we sucked the frag empty then we should free it,
1540 * if there are other frags here something is screwed up in hardware
1541 */
1542 if (skb_frag_size(frag) == 0) {
1543 BUG_ON(skb_shinfo(skb)->nr_frags != 1);
1544 skb_shinfo(skb)->nr_frags = 0;
1545 __skb_frag_unref(frag);
1546 skb->truesize -= ixgbe_rx_bufsz(rx_ring);
1547 }
1548
1549 #ifdef IXGBE_FCOE
1550 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1551 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1552 return false;
1553
1554 #endif
1555 /* if skb_pad returns an error the skb was freed */
1556 if (unlikely(skb->len < 60)) {
1557 int pad_len = 60 - skb->len;
1558
1559 if (skb_pad(skb, pad_len))
1560 return true;
1561 __skb_put(skb, pad_len);
1562 }
1563
1564 return false;
1565 }
1566
1567 /**
1568 * ixgbe_can_reuse_page - determine if we can reuse a page
1569 * @rx_buffer: pointer to rx_buffer containing the page we want to reuse
1570 *
1571 * Returns true if page can be reused in another Rx buffer
1572 **/
1573 static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer)
1574 {
1575 struct page *page = rx_buffer->page;
1576
1577 /* if we are only owner of page and it is local we can reuse it */
1578 return likely(page_count(page) == 1) &&
1579 likely(page_to_nid(page) == numa_node_id());
1580 }
1581
1582 /**
1583 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1584 * @rx_ring: rx descriptor ring to store buffers on
1585 * @old_buff: donor buffer to have page reused
1586 *
1587 * Syncronizes page for reuse by the adapter
1588 **/
1589 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1590 struct ixgbe_rx_buffer *old_buff)
1591 {
1592 struct ixgbe_rx_buffer *new_buff;
1593 u16 nta = rx_ring->next_to_alloc;
1594 u16 bufsz = ixgbe_rx_bufsz(rx_ring);
1595
1596 new_buff = &rx_ring->rx_buffer_info[nta];
1597
1598 /* update, and store next to alloc */
1599 nta++;
1600 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1601
1602 /* transfer page from old buffer to new buffer */
1603 new_buff->page = old_buff->page;
1604 new_buff->dma = old_buff->dma;
1605
1606 /* flip page offset to other buffer and store to new_buff */
1607 new_buff->page_offset = old_buff->page_offset ^ bufsz;
1608
1609 /* sync the buffer for use by the device */
1610 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1611 new_buff->page_offset, bufsz,
1612 DMA_FROM_DEVICE);
1613
1614 /* bump ref count on page before it is given to the stack */
1615 get_page(new_buff->page);
1616 }
1617
1618 /**
1619 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1620 * @rx_ring: rx descriptor ring to transact packets on
1621 * @rx_buffer: buffer containing page to add
1622 * @rx_desc: descriptor containing length of buffer written by hardware
1623 * @skb: sk_buff to place the data into
1624 *
1625 * This function is based on skb_add_rx_frag. I would have used that
1626 * function however it doesn't handle the truesize case correctly since we
1627 * are allocating more memory than might be used for a single receive.
1628 **/
1629 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1630 struct ixgbe_rx_buffer *rx_buffer,
1631 struct sk_buff *skb, int size)
1632 {
1633 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1634 rx_buffer->page, rx_buffer->page_offset,
1635 size);
1636 skb->len += size;
1637 skb->data_len += size;
1638 skb->truesize += ixgbe_rx_bufsz(rx_ring);
1639 }
1640
1641 /**
1642 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1643 * @q_vector: structure containing interrupt and ring information
1644 * @rx_ring: rx descriptor ring to transact packets on
1645 * @budget: Total limit on number of packets to process
1646 *
1647 * This function provides a "bounce buffer" approach to Rx interrupt
1648 * processing. The advantage to this is that on systems that have
1649 * expensive overhead for IOMMU access this provides a means of avoiding
1650 * it by maintaining the mapping of the page to the syste.
1651 *
1652 * Returns true if all work is completed without reaching budget
1653 **/
1654 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1655 struct ixgbe_ring *rx_ring,
1656 int budget)
1657 {
1658 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1659 #ifdef IXGBE_FCOE
1660 struct ixgbe_adapter *adapter = q_vector->adapter;
1661 int ddp_bytes = 0;
1662 #endif /* IXGBE_FCOE */
1663 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1664
1665 do {
1666 struct ixgbe_rx_buffer *rx_buffer;
1667 union ixgbe_adv_rx_desc *rx_desc;
1668 struct sk_buff *skb;
1669 struct page *page;
1670 u16 ntc;
1671
1672 /* return some buffers to hardware, one at a time is too slow */
1673 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1674 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1675 cleaned_count = 0;
1676 }
1677
1678 ntc = rx_ring->next_to_clean;
1679 rx_desc = IXGBE_RX_DESC(rx_ring, ntc);
1680 rx_buffer = &rx_ring->rx_buffer_info[ntc];
1681
1682 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1683 break;
1684
1685 /*
1686 * This memory barrier is needed to keep us from reading
1687 * any other fields out of the rx_desc until we know the
1688 * RXD_STAT_DD bit is set
1689 */
1690 rmb();
1691
1692 page = rx_buffer->page;
1693 prefetchw(page);
1694
1695 skb = rx_buffer->skb;
1696
1697 if (likely(!skb)) {
1698 void *page_addr = page_address(page) +
1699 rx_buffer->page_offset;
1700
1701 /* prefetch first cache line of first page */
1702 prefetch(page_addr);
1703 #if L1_CACHE_BYTES < 128
1704 prefetch(page_addr + L1_CACHE_BYTES);
1705 #endif
1706
1707 /* allocate a skb to store the frags */
1708 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1709 IXGBE_RX_HDR_SIZE);
1710 if (unlikely(!skb)) {
1711 rx_ring->rx_stats.alloc_rx_buff_failed++;
1712 break;
1713 }
1714
1715 /*
1716 * we will be copying header into skb->data in
1717 * pskb_may_pull so it is in our interest to prefetch
1718 * it now to avoid a possible cache miss
1719 */
1720 prefetchw(skb->data);
1721
1722 /*
1723 * Delay unmapping of the first packet. It carries the
1724 * header information, HW may still access the header
1725 * after the writeback. Only unmap it when EOP is
1726 * reached
1727 */
1728 IXGBE_CB(skb)->dma = rx_buffer->dma;
1729 } else {
1730 /* we are reusing so sync this buffer for CPU use */
1731 dma_sync_single_range_for_cpu(rx_ring->dev,
1732 rx_buffer->dma,
1733 rx_buffer->page_offset,
1734 ixgbe_rx_bufsz(rx_ring),
1735 DMA_FROM_DEVICE);
1736 }
1737
1738 /* pull page into skb */
1739 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb,
1740 le16_to_cpu(rx_desc->wb.upper.length));
1741
1742 if (ixgbe_can_reuse_page(rx_buffer)) {
1743 /* hand second half of page back to the ring */
1744 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1745 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1746 /* the page has been released from the ring */
1747 IXGBE_CB(skb)->page_released = true;
1748 } else {
1749 /* we are not reusing the buffer so unmap it */
1750 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1751 ixgbe_rx_pg_size(rx_ring),
1752 DMA_FROM_DEVICE);
1753 }
1754
1755 /* clear contents of buffer_info */
1756 rx_buffer->skb = NULL;
1757 rx_buffer->dma = 0;
1758 rx_buffer->page = NULL;
1759
1760 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
1761
1762 cleaned_count++;
1763
1764 /* place incomplete frames back on ring for completion */
1765 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1766 continue;
1767
1768 /* verify the packet layout is correct */
1769 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1770 continue;
1771
1772 /* probably a little skewed due to removing CRC */
1773 total_rx_bytes += skb->len;
1774 total_rx_packets++;
1775
1776 /* populate checksum, timestamp, VLAN, and protocol */
1777 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1778
1779 #ifdef IXGBE_FCOE
1780 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1781 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
1782 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1783 if (!ddp_bytes) {
1784 dev_kfree_skb_any(skb);
1785 continue;
1786 }
1787 }
1788
1789 #endif /* IXGBE_FCOE */
1790 ixgbe_rx_skb(q_vector, skb);
1791
1792 /* update budget accounting */
1793 budget--;
1794 } while (likely(budget));
1795
1796 #ifdef IXGBE_FCOE
1797 /* include DDPed FCoE data */
1798 if (ddp_bytes > 0) {
1799 unsigned int mss;
1800
1801 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1802 sizeof(struct fc_frame_header) -
1803 sizeof(struct fcoe_crc_eof);
1804 if (mss > 512)
1805 mss &= ~511;
1806 total_rx_bytes += ddp_bytes;
1807 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1808 }
1809
1810 #endif /* IXGBE_FCOE */
1811 u64_stats_update_begin(&rx_ring->syncp);
1812 rx_ring->stats.packets += total_rx_packets;
1813 rx_ring->stats.bytes += total_rx_bytes;
1814 u64_stats_update_end(&rx_ring->syncp);
1815 q_vector->rx.total_packets += total_rx_packets;
1816 q_vector->rx.total_bytes += total_rx_bytes;
1817
1818 if (cleaned_count)
1819 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1820
1821 return !!budget;
1822 }
1823
1824 /**
1825 * ixgbe_configure_msix - Configure MSI-X hardware
1826 * @adapter: board private structure
1827 *
1828 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1829 * interrupts.
1830 **/
1831 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1832 {
1833 struct ixgbe_q_vector *q_vector;
1834 int q_vectors, v_idx;
1835 u32 mask;
1836
1837 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1838
1839 /* Populate MSIX to EITR Select */
1840 if (adapter->num_vfs > 32) {
1841 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1842 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1843 }
1844
1845 /*
1846 * Populate the IVAR table and set the ITR values to the
1847 * corresponding register.
1848 */
1849 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1850 struct ixgbe_ring *ring;
1851 q_vector = adapter->q_vector[v_idx];
1852
1853 ixgbe_for_each_ring(ring, q_vector->rx)
1854 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1855
1856 ixgbe_for_each_ring(ring, q_vector->tx)
1857 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1858
1859 if (q_vector->tx.ring && !q_vector->rx.ring) {
1860 /* tx only vector */
1861 if (adapter->tx_itr_setting == 1)
1862 q_vector->itr = IXGBE_10K_ITR;
1863 else
1864 q_vector->itr = adapter->tx_itr_setting;
1865 } else {
1866 /* rx or rx/tx vector */
1867 if (adapter->rx_itr_setting == 1)
1868 q_vector->itr = IXGBE_20K_ITR;
1869 else
1870 q_vector->itr = adapter->rx_itr_setting;
1871 }
1872
1873 ixgbe_write_eitr(q_vector);
1874 }
1875
1876 switch (adapter->hw.mac.type) {
1877 case ixgbe_mac_82598EB:
1878 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1879 v_idx);
1880 break;
1881 case ixgbe_mac_82599EB:
1882 case ixgbe_mac_X540:
1883 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1884 break;
1885 default:
1886 break;
1887 }
1888 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1889
1890 /* set up to autoclear timer, and the vectors */
1891 mask = IXGBE_EIMS_ENABLE_MASK;
1892 mask &= ~(IXGBE_EIMS_OTHER |
1893 IXGBE_EIMS_MAILBOX |
1894 IXGBE_EIMS_LSC);
1895
1896 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1897 }
1898
1899 enum latency_range {
1900 lowest_latency = 0,
1901 low_latency = 1,
1902 bulk_latency = 2,
1903 latency_invalid = 255
1904 };
1905
1906 /**
1907 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1908 * @q_vector: structure containing interrupt and ring information
1909 * @ring_container: structure containing ring performance data
1910 *
1911 * Stores a new ITR value based on packets and byte
1912 * counts during the last interrupt. The advantage of per interrupt
1913 * computation is faster updates and more accurate ITR for the current
1914 * traffic pattern. Constants in this function were computed
1915 * based on theoretical maximum wire speed and thresholds were set based
1916 * on testing data as well as attempting to minimize response time
1917 * while increasing bulk throughput.
1918 * this functionality is controlled by the InterruptThrottleRate module
1919 * parameter (see ixgbe_param.c)
1920 **/
1921 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1922 struct ixgbe_ring_container *ring_container)
1923 {
1924 int bytes = ring_container->total_bytes;
1925 int packets = ring_container->total_packets;
1926 u32 timepassed_us;
1927 u64 bytes_perint;
1928 u8 itr_setting = ring_container->itr;
1929
1930 if (packets == 0)
1931 return;
1932
1933 /* simple throttlerate management
1934 * 0-10MB/s lowest (100000 ints/s)
1935 * 10-20MB/s low (20000 ints/s)
1936 * 20-1249MB/s bulk (8000 ints/s)
1937 */
1938 /* what was last interrupt timeslice? */
1939 timepassed_us = q_vector->itr >> 2;
1940 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1941
1942 switch (itr_setting) {
1943 case lowest_latency:
1944 if (bytes_perint > 10)
1945 itr_setting = low_latency;
1946 break;
1947 case low_latency:
1948 if (bytes_perint > 20)
1949 itr_setting = bulk_latency;
1950 else if (bytes_perint <= 10)
1951 itr_setting = lowest_latency;
1952 break;
1953 case bulk_latency:
1954 if (bytes_perint <= 20)
1955 itr_setting = low_latency;
1956 break;
1957 }
1958
1959 /* clear work counters since we have the values we need */
1960 ring_container->total_bytes = 0;
1961 ring_container->total_packets = 0;
1962
1963 /* write updated itr to ring container */
1964 ring_container->itr = itr_setting;
1965 }
1966
1967 /**
1968 * ixgbe_write_eitr - write EITR register in hardware specific way
1969 * @q_vector: structure containing interrupt and ring information
1970 *
1971 * This function is made to be called by ethtool and by the driver
1972 * when it needs to update EITR registers at runtime. Hardware
1973 * specific quirks/differences are taken care of here.
1974 */
1975 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1976 {
1977 struct ixgbe_adapter *adapter = q_vector->adapter;
1978 struct ixgbe_hw *hw = &adapter->hw;
1979 int v_idx = q_vector->v_idx;
1980 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
1981
1982 switch (adapter->hw.mac.type) {
1983 case ixgbe_mac_82598EB:
1984 /* must write high and low 16 bits to reset counter */
1985 itr_reg |= (itr_reg << 16);
1986 break;
1987 case ixgbe_mac_82599EB:
1988 case ixgbe_mac_X540:
1989 /*
1990 * set the WDIS bit to not clear the timer bits and cause an
1991 * immediate assertion of the interrupt
1992 */
1993 itr_reg |= IXGBE_EITR_CNT_WDIS;
1994 break;
1995 default:
1996 break;
1997 }
1998 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1999 }
2000
2001 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2002 {
2003 u32 new_itr = q_vector->itr;
2004 u8 current_itr;
2005
2006 ixgbe_update_itr(q_vector, &q_vector->tx);
2007 ixgbe_update_itr(q_vector, &q_vector->rx);
2008
2009 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2010
2011 switch (current_itr) {
2012 /* counts and packets in update_itr are dependent on these numbers */
2013 case lowest_latency:
2014 new_itr = IXGBE_100K_ITR;
2015 break;
2016 case low_latency:
2017 new_itr = IXGBE_20K_ITR;
2018 break;
2019 case bulk_latency:
2020 new_itr = IXGBE_8K_ITR;
2021 break;
2022 default:
2023 break;
2024 }
2025
2026 if (new_itr != q_vector->itr) {
2027 /* do an exponential smoothing */
2028 new_itr = (10 * new_itr * q_vector->itr) /
2029 ((9 * new_itr) + q_vector->itr);
2030
2031 /* save the algorithm value here */
2032 q_vector->itr = new_itr;
2033
2034 ixgbe_write_eitr(q_vector);
2035 }
2036 }
2037
2038 /**
2039 * ixgbe_check_overtemp_subtask - check for over temperature
2040 * @adapter: pointer to adapter
2041 **/
2042 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2043 {
2044 struct ixgbe_hw *hw = &adapter->hw;
2045 u32 eicr = adapter->interrupt_event;
2046
2047 if (test_bit(__IXGBE_DOWN, &adapter->state))
2048 return;
2049
2050 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2051 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2052 return;
2053
2054 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2055
2056 switch (hw->device_id) {
2057 case IXGBE_DEV_ID_82599_T3_LOM:
2058 /*
2059 * Since the warning interrupt is for both ports
2060 * we don't have to check if:
2061 * - This interrupt wasn't for our port.
2062 * - We may have missed the interrupt so always have to
2063 * check if we got a LSC
2064 */
2065 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2066 !(eicr & IXGBE_EICR_LSC))
2067 return;
2068
2069 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2070 u32 autoneg;
2071 bool link_up = false;
2072
2073 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2074
2075 if (link_up)
2076 return;
2077 }
2078
2079 /* Check if this is not due to overtemp */
2080 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2081 return;
2082
2083 break;
2084 default:
2085 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2086 return;
2087 break;
2088 }
2089 e_crit(drv,
2090 "Network adapter has been stopped because it has over heated. "
2091 "Restart the computer. If the problem persists, "
2092 "power off the system and replace the adapter\n");
2093
2094 adapter->interrupt_event = 0;
2095 }
2096
2097 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2098 {
2099 struct ixgbe_hw *hw = &adapter->hw;
2100
2101 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2102 (eicr & IXGBE_EICR_GPI_SDP1)) {
2103 e_crit(probe, "Fan has stopped, replace the adapter\n");
2104 /* write to clear the interrupt */
2105 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2106 }
2107 }
2108
2109 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2110 {
2111 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2112 return;
2113
2114 switch (adapter->hw.mac.type) {
2115 case ixgbe_mac_82599EB:
2116 /*
2117 * Need to check link state so complete overtemp check
2118 * on service task
2119 */
2120 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2121 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2122 adapter->interrupt_event = eicr;
2123 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2124 ixgbe_service_event_schedule(adapter);
2125 return;
2126 }
2127 return;
2128 case ixgbe_mac_X540:
2129 if (!(eicr & IXGBE_EICR_TS))
2130 return;
2131 break;
2132 default:
2133 return;
2134 }
2135
2136 e_crit(drv,
2137 "Network adapter has been stopped because it has over heated. "
2138 "Restart the computer. If the problem persists, "
2139 "power off the system and replace the adapter\n");
2140 }
2141
2142 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2143 {
2144 struct ixgbe_hw *hw = &adapter->hw;
2145
2146 if (eicr & IXGBE_EICR_GPI_SDP2) {
2147 /* Clear the interrupt */
2148 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2149 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2150 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2151 ixgbe_service_event_schedule(adapter);
2152 }
2153 }
2154
2155 if (eicr & IXGBE_EICR_GPI_SDP1) {
2156 /* Clear the interrupt */
2157 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2158 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2159 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2160 ixgbe_service_event_schedule(adapter);
2161 }
2162 }
2163 }
2164
2165 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2166 {
2167 struct ixgbe_hw *hw = &adapter->hw;
2168
2169 adapter->lsc_int++;
2170 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2171 adapter->link_check_timeout = jiffies;
2172 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2173 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2174 IXGBE_WRITE_FLUSH(hw);
2175 ixgbe_service_event_schedule(adapter);
2176 }
2177 }
2178
2179 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2180 u64 qmask)
2181 {
2182 u32 mask;
2183 struct ixgbe_hw *hw = &adapter->hw;
2184
2185 switch (hw->mac.type) {
2186 case ixgbe_mac_82598EB:
2187 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2188 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2189 break;
2190 case ixgbe_mac_82599EB:
2191 case ixgbe_mac_X540:
2192 mask = (qmask & 0xFFFFFFFF);
2193 if (mask)
2194 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2195 mask = (qmask >> 32);
2196 if (mask)
2197 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2198 break;
2199 default:
2200 break;
2201 }
2202 /* skip the flush */
2203 }
2204
2205 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2206 u64 qmask)
2207 {
2208 u32 mask;
2209 struct ixgbe_hw *hw = &adapter->hw;
2210
2211 switch (hw->mac.type) {
2212 case ixgbe_mac_82598EB:
2213 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2214 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2215 break;
2216 case ixgbe_mac_82599EB:
2217 case ixgbe_mac_X540:
2218 mask = (qmask & 0xFFFFFFFF);
2219 if (mask)
2220 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2221 mask = (qmask >> 32);
2222 if (mask)
2223 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2224 break;
2225 default:
2226 break;
2227 }
2228 /* skip the flush */
2229 }
2230
2231 /**
2232 * ixgbe_irq_enable - Enable default interrupt generation settings
2233 * @adapter: board private structure
2234 **/
2235 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2236 bool flush)
2237 {
2238 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2239
2240 /* don't reenable LSC while waiting for link */
2241 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2242 mask &= ~IXGBE_EIMS_LSC;
2243
2244 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2245 switch (adapter->hw.mac.type) {
2246 case ixgbe_mac_82599EB:
2247 mask |= IXGBE_EIMS_GPI_SDP0;
2248 break;
2249 case ixgbe_mac_X540:
2250 mask |= IXGBE_EIMS_TS;
2251 break;
2252 default:
2253 break;
2254 }
2255 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2256 mask |= IXGBE_EIMS_GPI_SDP1;
2257 switch (adapter->hw.mac.type) {
2258 case ixgbe_mac_82599EB:
2259 mask |= IXGBE_EIMS_GPI_SDP1;
2260 mask |= IXGBE_EIMS_GPI_SDP2;
2261 case ixgbe_mac_X540:
2262 mask |= IXGBE_EIMS_ECC;
2263 mask |= IXGBE_EIMS_MAILBOX;
2264 break;
2265 default:
2266 break;
2267 }
2268 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2269 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2270 mask |= IXGBE_EIMS_FLOW_DIR;
2271
2272 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2273 if (queues)
2274 ixgbe_irq_enable_queues(adapter, ~0);
2275 if (flush)
2276 IXGBE_WRITE_FLUSH(&adapter->hw);
2277 }
2278
2279 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2280 {
2281 struct ixgbe_adapter *adapter = data;
2282 struct ixgbe_hw *hw = &adapter->hw;
2283 u32 eicr;
2284
2285 /*
2286 * Workaround for Silicon errata. Use clear-by-write instead
2287 * of clear-by-read. Reading with EICS will return the
2288 * interrupt causes without clearing, which later be done
2289 * with the write to EICR.
2290 */
2291 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2292 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2293
2294 if (eicr & IXGBE_EICR_LSC)
2295 ixgbe_check_lsc(adapter);
2296
2297 if (eicr & IXGBE_EICR_MAILBOX)
2298 ixgbe_msg_task(adapter);
2299
2300 switch (hw->mac.type) {
2301 case ixgbe_mac_82599EB:
2302 case ixgbe_mac_X540:
2303 if (eicr & IXGBE_EICR_ECC)
2304 e_info(link, "Received unrecoverable ECC Err, please "
2305 "reboot\n");
2306 /* Handle Flow Director Full threshold interrupt */
2307 if (eicr & IXGBE_EICR_FLOW_DIR) {
2308 int reinit_count = 0;
2309 int i;
2310 for (i = 0; i < adapter->num_tx_queues; i++) {
2311 struct ixgbe_ring *ring = adapter->tx_ring[i];
2312 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2313 &ring->state))
2314 reinit_count++;
2315 }
2316 if (reinit_count) {
2317 /* no more flow director interrupts until after init */
2318 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2319 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2320 ixgbe_service_event_schedule(adapter);
2321 }
2322 }
2323 ixgbe_check_sfp_event(adapter, eicr);
2324 ixgbe_check_overtemp_event(adapter, eicr);
2325 break;
2326 default:
2327 break;
2328 }
2329
2330 ixgbe_check_fan_failure(adapter, eicr);
2331 #ifdef CONFIG_IXGBE_PTP
2332 ixgbe_ptp_check_pps_event(adapter, eicr);
2333 #endif
2334
2335 /* re-enable the original interrupt state, no lsc, no queues */
2336 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2337 ixgbe_irq_enable(adapter, false, false);
2338
2339 return IRQ_HANDLED;
2340 }
2341
2342 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2343 {
2344 struct ixgbe_q_vector *q_vector = data;
2345
2346 /* EIAM disabled interrupts (on this vector) for us */
2347
2348 if (q_vector->rx.ring || q_vector->tx.ring)
2349 napi_schedule(&q_vector->napi);
2350
2351 return IRQ_HANDLED;
2352 }
2353
2354 /**
2355 * ixgbe_poll - NAPI Rx polling callback
2356 * @napi: structure for representing this polling device
2357 * @budget: how many packets driver is allowed to clean
2358 *
2359 * This function is used for legacy and MSI, NAPI mode
2360 **/
2361 int ixgbe_poll(struct napi_struct *napi, int budget)
2362 {
2363 struct ixgbe_q_vector *q_vector =
2364 container_of(napi, struct ixgbe_q_vector, napi);
2365 struct ixgbe_adapter *adapter = q_vector->adapter;
2366 struct ixgbe_ring *ring;
2367 int per_ring_budget;
2368 bool clean_complete = true;
2369
2370 #ifdef CONFIG_IXGBE_DCA
2371 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2372 ixgbe_update_dca(q_vector);
2373 #endif
2374
2375 ixgbe_for_each_ring(ring, q_vector->tx)
2376 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2377
2378 /* attempt to distribute budget to each queue fairly, but don't allow
2379 * the budget to go below 1 because we'll exit polling */
2380 if (q_vector->rx.count > 1)
2381 per_ring_budget = max(budget/q_vector->rx.count, 1);
2382 else
2383 per_ring_budget = budget;
2384
2385 ixgbe_for_each_ring(ring, q_vector->rx)
2386 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2387 per_ring_budget);
2388
2389 /* If all work not completed, return budget and keep polling */
2390 if (!clean_complete)
2391 return budget;
2392
2393 /* all work done, exit the polling mode */
2394 napi_complete(napi);
2395 if (adapter->rx_itr_setting & 1)
2396 ixgbe_set_itr(q_vector);
2397 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2398 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2399
2400 return 0;
2401 }
2402
2403 /**
2404 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2405 * @adapter: board private structure
2406 *
2407 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2408 * interrupts from the kernel.
2409 **/
2410 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2411 {
2412 struct net_device *netdev = adapter->netdev;
2413 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2414 int vector, err;
2415 int ri = 0, ti = 0;
2416
2417 for (vector = 0; vector < q_vectors; vector++) {
2418 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2419 struct msix_entry *entry = &adapter->msix_entries[vector];
2420
2421 if (q_vector->tx.ring && q_vector->rx.ring) {
2422 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2423 "%s-%s-%d", netdev->name, "TxRx", ri++);
2424 ti++;
2425 } else if (q_vector->rx.ring) {
2426 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2427 "%s-%s-%d", netdev->name, "rx", ri++);
2428 } else if (q_vector->tx.ring) {
2429 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2430 "%s-%s-%d", netdev->name, "tx", ti++);
2431 } else {
2432 /* skip this unused q_vector */
2433 continue;
2434 }
2435 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2436 q_vector->name, q_vector);
2437 if (err) {
2438 e_err(probe, "request_irq failed for MSIX interrupt "
2439 "Error: %d\n", err);
2440 goto free_queue_irqs;
2441 }
2442 /* If Flow Director is enabled, set interrupt affinity */
2443 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2444 /* assign the mask for this irq */
2445 irq_set_affinity_hint(entry->vector,
2446 &q_vector->affinity_mask);
2447 }
2448 }
2449
2450 err = request_irq(adapter->msix_entries[vector].vector,
2451 ixgbe_msix_other, 0, netdev->name, adapter);
2452 if (err) {
2453 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2454 goto free_queue_irqs;
2455 }
2456
2457 return 0;
2458
2459 free_queue_irqs:
2460 while (vector) {
2461 vector--;
2462 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2463 NULL);
2464 free_irq(adapter->msix_entries[vector].vector,
2465 adapter->q_vector[vector]);
2466 }
2467 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2468 pci_disable_msix(adapter->pdev);
2469 kfree(adapter->msix_entries);
2470 adapter->msix_entries = NULL;
2471 return err;
2472 }
2473
2474 /**
2475 * ixgbe_intr - legacy mode Interrupt Handler
2476 * @irq: interrupt number
2477 * @data: pointer to a network interface device structure
2478 **/
2479 static irqreturn_t ixgbe_intr(int irq, void *data)
2480 {
2481 struct ixgbe_adapter *adapter = data;
2482 struct ixgbe_hw *hw = &adapter->hw;
2483 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2484 u32 eicr;
2485
2486 /*
2487 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2488 * before the read of EICR.
2489 */
2490 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2491
2492 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2493 * therefore no explicit interrupt disable is necessary */
2494 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2495 if (!eicr) {
2496 /*
2497 * shared interrupt alert!
2498 * make sure interrupts are enabled because the read will
2499 * have disabled interrupts due to EIAM
2500 * finish the workaround of silicon errata on 82598. Unmask
2501 * the interrupt that we masked before the EICR read.
2502 */
2503 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2504 ixgbe_irq_enable(adapter, true, true);
2505 return IRQ_NONE; /* Not our interrupt */
2506 }
2507
2508 if (eicr & IXGBE_EICR_LSC)
2509 ixgbe_check_lsc(adapter);
2510
2511 switch (hw->mac.type) {
2512 case ixgbe_mac_82599EB:
2513 ixgbe_check_sfp_event(adapter, eicr);
2514 /* Fall through */
2515 case ixgbe_mac_X540:
2516 if (eicr & IXGBE_EICR_ECC)
2517 e_info(link, "Received unrecoverable ECC err, please "
2518 "reboot\n");
2519 ixgbe_check_overtemp_event(adapter, eicr);
2520 break;
2521 default:
2522 break;
2523 }
2524
2525 ixgbe_check_fan_failure(adapter, eicr);
2526 #ifdef CONFIG_IXGBE_PTP
2527 ixgbe_ptp_check_pps_event(adapter, eicr);
2528 #endif
2529
2530 /* would disable interrupts here but EIAM disabled it */
2531 napi_schedule(&q_vector->napi);
2532
2533 /*
2534 * re-enable link(maybe) and non-queue interrupts, no flush.
2535 * ixgbe_poll will re-enable the queue interrupts
2536 */
2537 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2538 ixgbe_irq_enable(adapter, false, false);
2539
2540 return IRQ_HANDLED;
2541 }
2542
2543 /**
2544 * ixgbe_request_irq - initialize interrupts
2545 * @adapter: board private structure
2546 *
2547 * Attempts to configure interrupts using the best available
2548 * capabilities of the hardware and kernel.
2549 **/
2550 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2551 {
2552 struct net_device *netdev = adapter->netdev;
2553 int err;
2554
2555 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2556 err = ixgbe_request_msix_irqs(adapter);
2557 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2558 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2559 netdev->name, adapter);
2560 else
2561 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2562 netdev->name, adapter);
2563
2564 if (err)
2565 e_err(probe, "request_irq failed, Error %d\n", err);
2566
2567 return err;
2568 }
2569
2570 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2571 {
2572 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2573 int i, q_vectors;
2574
2575 q_vectors = adapter->num_msix_vectors;
2576 i = q_vectors - 1;
2577 free_irq(adapter->msix_entries[i].vector, adapter);
2578 i--;
2579
2580 for (; i >= 0; i--) {
2581 /* free only the irqs that were actually requested */
2582 if (!adapter->q_vector[i]->rx.ring &&
2583 !adapter->q_vector[i]->tx.ring)
2584 continue;
2585
2586 /* clear the affinity_mask in the IRQ descriptor */
2587 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2588 NULL);
2589
2590 free_irq(adapter->msix_entries[i].vector,
2591 adapter->q_vector[i]);
2592 }
2593 } else {
2594 free_irq(adapter->pdev->irq, adapter);
2595 }
2596 }
2597
2598 /**
2599 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2600 * @adapter: board private structure
2601 **/
2602 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2603 {
2604 switch (adapter->hw.mac.type) {
2605 case ixgbe_mac_82598EB:
2606 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2607 break;
2608 case ixgbe_mac_82599EB:
2609 case ixgbe_mac_X540:
2610 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2611 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2612 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2613 break;
2614 default:
2615 break;
2616 }
2617 IXGBE_WRITE_FLUSH(&adapter->hw);
2618 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2619 int i;
2620 for (i = 0; i < adapter->num_msix_vectors; i++)
2621 synchronize_irq(adapter->msix_entries[i].vector);
2622 } else {
2623 synchronize_irq(adapter->pdev->irq);
2624 }
2625 }
2626
2627 /**
2628 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2629 *
2630 **/
2631 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2632 {
2633 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2634
2635 /* rx/tx vector */
2636 if (adapter->rx_itr_setting == 1)
2637 q_vector->itr = IXGBE_20K_ITR;
2638 else
2639 q_vector->itr = adapter->rx_itr_setting;
2640
2641 ixgbe_write_eitr(q_vector);
2642
2643 ixgbe_set_ivar(adapter, 0, 0, 0);
2644 ixgbe_set_ivar(adapter, 1, 0, 0);
2645
2646 e_info(hw, "Legacy interrupt IVAR setup done\n");
2647 }
2648
2649 /**
2650 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2651 * @adapter: board private structure
2652 * @ring: structure containing ring specific data
2653 *
2654 * Configure the Tx descriptor ring after a reset.
2655 **/
2656 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2657 struct ixgbe_ring *ring)
2658 {
2659 struct ixgbe_hw *hw = &adapter->hw;
2660 u64 tdba = ring->dma;
2661 int wait_loop = 10;
2662 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2663 u8 reg_idx = ring->reg_idx;
2664
2665 /* disable queue to avoid issues while updating state */
2666 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2667 IXGBE_WRITE_FLUSH(hw);
2668
2669 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2670 (tdba & DMA_BIT_MASK(32)));
2671 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2672 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2673 ring->count * sizeof(union ixgbe_adv_tx_desc));
2674 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2675 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2676 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2677
2678 /*
2679 * set WTHRESH to encourage burst writeback, it should not be set
2680 * higher than 1 when ITR is 0 as it could cause false TX hangs
2681 *
2682 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2683 * to or less than the number of on chip descriptors, which is
2684 * currently 40.
2685 */
2686 if (!ring->q_vector || (ring->q_vector->itr < 8))
2687 txdctl |= (1 << 16); /* WTHRESH = 1 */
2688 else
2689 txdctl |= (8 << 16); /* WTHRESH = 8 */
2690
2691 /*
2692 * Setting PTHRESH to 32 both improves performance
2693 * and avoids a TX hang with DFP enabled
2694 */
2695 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2696 32; /* PTHRESH = 32 */
2697
2698 /* reinitialize flowdirector state */
2699 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2700 adapter->atr_sample_rate) {
2701 ring->atr_sample_rate = adapter->atr_sample_rate;
2702 ring->atr_count = 0;
2703 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2704 } else {
2705 ring->atr_sample_rate = 0;
2706 }
2707
2708 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2709
2710 /* enable queue */
2711 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2712
2713 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2714 if (hw->mac.type == ixgbe_mac_82598EB &&
2715 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2716 return;
2717
2718 /* poll to verify queue is enabled */
2719 do {
2720 usleep_range(1000, 2000);
2721 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2722 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2723 if (!wait_loop)
2724 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2725 }
2726
2727 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2728 {
2729 struct ixgbe_hw *hw = &adapter->hw;
2730 u32 rttdcs;
2731 u32 reg;
2732 u8 tcs = netdev_get_num_tc(adapter->netdev);
2733
2734 if (hw->mac.type == ixgbe_mac_82598EB)
2735 return;
2736
2737 /* disable the arbiter while setting MTQC */
2738 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2739 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2740 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2741
2742 /* set transmit pool layout */
2743 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2744 case (IXGBE_FLAG_SRIOV_ENABLED):
2745 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2746 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2747 break;
2748 default:
2749 if (!tcs)
2750 reg = IXGBE_MTQC_64Q_1PB;
2751 else if (tcs <= 4)
2752 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2753 else
2754 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2755
2756 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2757
2758 /* Enable Security TX Buffer IFG for multiple pb */
2759 if (tcs) {
2760 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2761 reg |= IXGBE_SECTX_DCB;
2762 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2763 }
2764 break;
2765 }
2766
2767 /* re-enable the arbiter */
2768 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2769 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2770 }
2771
2772 /**
2773 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2774 * @adapter: board private structure
2775 *
2776 * Configure the Tx unit of the MAC after a reset.
2777 **/
2778 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2779 {
2780 struct ixgbe_hw *hw = &adapter->hw;
2781 u32 dmatxctl;
2782 u32 i;
2783
2784 ixgbe_setup_mtqc(adapter);
2785
2786 if (hw->mac.type != ixgbe_mac_82598EB) {
2787 /* DMATXCTL.EN must be before Tx queues are enabled */
2788 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2789 dmatxctl |= IXGBE_DMATXCTL_TE;
2790 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2791 }
2792
2793 /* Setup the HW Tx Head and Tail descriptor pointers */
2794 for (i = 0; i < adapter->num_tx_queues; i++)
2795 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2796 }
2797
2798 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2799 struct ixgbe_ring *ring)
2800 {
2801 struct ixgbe_hw *hw = &adapter->hw;
2802 u8 reg_idx = ring->reg_idx;
2803 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2804
2805 srrctl |= IXGBE_SRRCTL_DROP_EN;
2806
2807 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2808 }
2809
2810 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2811 struct ixgbe_ring *ring)
2812 {
2813 struct ixgbe_hw *hw = &adapter->hw;
2814 u8 reg_idx = ring->reg_idx;
2815 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2816
2817 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2818
2819 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2820 }
2821
2822 #ifdef CONFIG_IXGBE_DCB
2823 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2824 #else
2825 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2826 #endif
2827 {
2828 int i;
2829 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2830
2831 if (adapter->ixgbe_ieee_pfc)
2832 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2833
2834 /*
2835 * We should set the drop enable bit if:
2836 * SR-IOV is enabled
2837 * or
2838 * Number of Rx queues > 1 and flow control is disabled
2839 *
2840 * This allows us to avoid head of line blocking for security
2841 * and performance reasons.
2842 */
2843 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2844 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2845 for (i = 0; i < adapter->num_rx_queues; i++)
2846 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2847 } else {
2848 for (i = 0; i < adapter->num_rx_queues; i++)
2849 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2850 }
2851 }
2852
2853 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2854
2855 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2856 struct ixgbe_ring *rx_ring)
2857 {
2858 u32 srrctl;
2859 u8 reg_idx = rx_ring->reg_idx;
2860
2861 switch (adapter->hw.mac.type) {
2862 case ixgbe_mac_82598EB: {
2863 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2864 const int mask = feature[RING_F_RSS].mask;
2865 reg_idx = reg_idx & mask;
2866 }
2867 break;
2868 case ixgbe_mac_82599EB:
2869 case ixgbe_mac_X540:
2870 default:
2871 break;
2872 }
2873
2874 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2875
2876 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2877 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2878 if (adapter->num_vfs)
2879 srrctl |= IXGBE_SRRCTL_DROP_EN;
2880
2881 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2882 IXGBE_SRRCTL_BSIZEHDR_MASK;
2883
2884 #if PAGE_SIZE > IXGBE_MAX_RXBUFFER
2885 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2886 #else
2887 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2888 #endif
2889 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2890
2891 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2892 }
2893
2894 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2895 {
2896 struct ixgbe_hw *hw = &adapter->hw;
2897 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2898 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2899 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2900 u32 mrqc = 0, reta = 0;
2901 u32 rxcsum;
2902 int i, j;
2903 u8 tcs = netdev_get_num_tc(adapter->netdev);
2904 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2905
2906 if (tcs)
2907 maxq = min(maxq, adapter->num_tx_queues / tcs);
2908
2909 /* Fill out hash function seeds */
2910 for (i = 0; i < 10; i++)
2911 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2912
2913 /* Fill out redirection table */
2914 for (i = 0, j = 0; i < 128; i++, j++) {
2915 if (j == maxq)
2916 j = 0;
2917 /* reta = 4-byte sliding window of
2918 * 0x00..(indices-1)(indices-1)00..etc. */
2919 reta = (reta << 8) | (j * 0x11);
2920 if ((i & 3) == 3)
2921 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2922 }
2923
2924 /* Disable indicating checksum in descriptor, enables RSS hash */
2925 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2926 rxcsum |= IXGBE_RXCSUM_PCSD;
2927 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2928
2929 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2930 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2931 mrqc = IXGBE_MRQC_RSSEN;
2932 } else {
2933 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2934 | IXGBE_FLAG_SRIOV_ENABLED);
2935
2936 switch (mask) {
2937 case (IXGBE_FLAG_RSS_ENABLED):
2938 if (!tcs)
2939 mrqc = IXGBE_MRQC_RSSEN;
2940 else if (tcs <= 4)
2941 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2942 else
2943 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2944 break;
2945 case (IXGBE_FLAG_SRIOV_ENABLED):
2946 mrqc = IXGBE_MRQC_VMDQEN;
2947 break;
2948 default:
2949 break;
2950 }
2951 }
2952
2953 /* Perform hash on these packet types */
2954 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2955 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2956 | IXGBE_MRQC_RSS_FIELD_IPV6
2957 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2958
2959 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2960 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2961 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2962 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2963
2964 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2965 }
2966
2967 /**
2968 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2969 * @adapter: address of board private structure
2970 * @index: index of ring to set
2971 **/
2972 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2973 struct ixgbe_ring *ring)
2974 {
2975 struct ixgbe_hw *hw = &adapter->hw;
2976 u32 rscctrl;
2977 u8 reg_idx = ring->reg_idx;
2978
2979 if (!ring_is_rsc_enabled(ring))
2980 return;
2981
2982 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2983 rscctrl |= IXGBE_RSCCTL_RSCEN;
2984 /*
2985 * we must limit the number of descriptors so that the
2986 * total size of max desc * buf_len is not greater
2987 * than 65536
2988 */
2989 #if (PAGE_SIZE <= 8192)
2990 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2991 #elif (PAGE_SIZE <= 16384)
2992 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2993 #else
2994 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2995 #endif
2996 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2997 }
2998
2999 #define IXGBE_MAX_RX_DESC_POLL 10
3000 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3001 struct ixgbe_ring *ring)
3002 {
3003 struct ixgbe_hw *hw = &adapter->hw;
3004 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3005 u32 rxdctl;
3006 u8 reg_idx = ring->reg_idx;
3007
3008 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3009 if (hw->mac.type == ixgbe_mac_82598EB &&
3010 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3011 return;
3012
3013 do {
3014 usleep_range(1000, 2000);
3015 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3016 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3017
3018 if (!wait_loop) {
3019 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3020 "the polling period\n", reg_idx);
3021 }
3022 }
3023
3024 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3025 struct ixgbe_ring *ring)
3026 {
3027 struct ixgbe_hw *hw = &adapter->hw;
3028 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3029 u32 rxdctl;
3030 u8 reg_idx = ring->reg_idx;
3031
3032 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3033 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3034
3035 /* write value back with RXDCTL.ENABLE bit cleared */
3036 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3037
3038 if (hw->mac.type == ixgbe_mac_82598EB &&
3039 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3040 return;
3041
3042 /* the hardware may take up to 100us to really disable the rx queue */
3043 do {
3044 udelay(10);
3045 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3046 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3047
3048 if (!wait_loop) {
3049 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3050 "the polling period\n", reg_idx);
3051 }
3052 }
3053
3054 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3055 struct ixgbe_ring *ring)
3056 {
3057 struct ixgbe_hw *hw = &adapter->hw;
3058 u64 rdba = ring->dma;
3059 u32 rxdctl;
3060 u8 reg_idx = ring->reg_idx;
3061
3062 /* disable queue to avoid issues while updating state */
3063 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3064 ixgbe_disable_rx_queue(adapter, ring);
3065
3066 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3067 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3068 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3069 ring->count * sizeof(union ixgbe_adv_rx_desc));
3070 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3071 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3072 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3073
3074 ixgbe_configure_srrctl(adapter, ring);
3075 ixgbe_configure_rscctl(adapter, ring);
3076
3077 /* If operating in IOV mode set RLPML for X540 */
3078 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3079 hw->mac.type == ixgbe_mac_X540) {
3080 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3081 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3082 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3083 }
3084
3085 if (hw->mac.type == ixgbe_mac_82598EB) {
3086 /*
3087 * enable cache line friendly hardware writes:
3088 * PTHRESH=32 descriptors (half the internal cache),
3089 * this also removes ugly rx_no_buffer_count increment
3090 * HTHRESH=4 descriptors (to minimize latency on fetch)
3091 * WTHRESH=8 burst writeback up to two cache lines
3092 */
3093 rxdctl &= ~0x3FFFFF;
3094 rxdctl |= 0x080420;
3095 }
3096
3097 /* enable receive descriptor ring */
3098 rxdctl |= IXGBE_RXDCTL_ENABLE;
3099 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3100
3101 ixgbe_rx_desc_queue_enable(adapter, ring);
3102 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3103 }
3104
3105 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3106 {
3107 struct ixgbe_hw *hw = &adapter->hw;
3108 int p;
3109
3110 /* PSRTYPE must be initialized in non 82598 adapters */
3111 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3112 IXGBE_PSRTYPE_UDPHDR |
3113 IXGBE_PSRTYPE_IPV4HDR |
3114 IXGBE_PSRTYPE_L2HDR |
3115 IXGBE_PSRTYPE_IPV6HDR;
3116
3117 if (hw->mac.type == ixgbe_mac_82598EB)
3118 return;
3119
3120 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3121 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3122
3123 for (p = 0; p < adapter->num_rx_pools; p++)
3124 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3125 psrtype);
3126 }
3127
3128 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3129 {
3130 struct ixgbe_hw *hw = &adapter->hw;
3131 u32 gcr_ext;
3132 u32 vt_reg_bits;
3133 u32 reg_offset, vf_shift;
3134 u32 vmdctl;
3135 int i;
3136
3137 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3138 return;
3139
3140 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3141 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3142 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3143 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3144
3145 vf_shift = adapter->num_vfs % 32;
3146 reg_offset = (adapter->num_vfs >= 32) ? 1 : 0;
3147
3148 /* Enable only the PF's pool for Tx/Rx */
3149 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3150 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3151 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3152 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3153 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3154
3155 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3156 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3157
3158 /*
3159 * Set up VF register offsets for selected VT Mode,
3160 * i.e. 32 or 64 VFs for SR-IOV
3161 */
3162 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3163 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3164 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3165 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3166
3167 /* enable Tx loopback for VF/PF communication */
3168 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3169 /* Enable MAC Anti-Spoofing */
3170 hw->mac.ops.set_mac_anti_spoofing(hw,
3171 (adapter->num_vfs != 0),
3172 adapter->num_vfs);
3173 /* For VFs that have spoof checking turned off */
3174 for (i = 0; i < adapter->num_vfs; i++) {
3175 if (!adapter->vfinfo[i].spoofchk_enabled)
3176 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3177 }
3178 }
3179
3180 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3181 {
3182 struct ixgbe_hw *hw = &adapter->hw;
3183 struct net_device *netdev = adapter->netdev;
3184 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3185 struct ixgbe_ring *rx_ring;
3186 int i;
3187 u32 mhadd, hlreg0;
3188
3189 #ifdef IXGBE_FCOE
3190 /* adjust max frame to be able to do baby jumbo for FCoE */
3191 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3192 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3193 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3194
3195 #endif /* IXGBE_FCOE */
3196 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3197 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3198 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3199 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3200
3201 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3202 }
3203
3204 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3205 max_frame += VLAN_HLEN;
3206
3207 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3208 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3209 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3210 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3211
3212 /*
3213 * Setup the HW Rx Head and Tail Descriptor Pointers and
3214 * the Base and Length of the Rx Descriptor Ring
3215 */
3216 for (i = 0; i < adapter->num_rx_queues; i++) {
3217 rx_ring = adapter->rx_ring[i];
3218 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3219 set_ring_rsc_enabled(rx_ring);
3220 else
3221 clear_ring_rsc_enabled(rx_ring);
3222 }
3223 }
3224
3225 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3226 {
3227 struct ixgbe_hw *hw = &adapter->hw;
3228 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3229
3230 switch (hw->mac.type) {
3231 case ixgbe_mac_82598EB:
3232 /*
3233 * For VMDq support of different descriptor types or
3234 * buffer sizes through the use of multiple SRRCTL
3235 * registers, RDRXCTL.MVMEN must be set to 1
3236 *
3237 * also, the manual doesn't mention it clearly but DCA hints
3238 * will only use queue 0's tags unless this bit is set. Side
3239 * effects of setting this bit are only that SRRCTL must be
3240 * fully programmed [0..15]
3241 */
3242 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3243 break;
3244 case ixgbe_mac_82599EB:
3245 case ixgbe_mac_X540:
3246 /* Disable RSC for ACK packets */
3247 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3248 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3249 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3250 /* hardware requires some bits to be set by default */
3251 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3252 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3253 break;
3254 default:
3255 /* We should do nothing since we don't know this hardware */
3256 return;
3257 }
3258
3259 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3260 }
3261
3262 /**
3263 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3264 * @adapter: board private structure
3265 *
3266 * Configure the Rx unit of the MAC after a reset.
3267 **/
3268 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3269 {
3270 struct ixgbe_hw *hw = &adapter->hw;
3271 int i;
3272 u32 rxctrl;
3273
3274 /* disable receives while setting up the descriptors */
3275 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3276 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3277
3278 ixgbe_setup_psrtype(adapter);
3279 ixgbe_setup_rdrxctl(adapter);
3280
3281 /* Program registers for the distribution of queues */
3282 ixgbe_setup_mrqc(adapter);
3283
3284 /* set_rx_buffer_len must be called before ring initialization */
3285 ixgbe_set_rx_buffer_len(adapter);
3286
3287 /*
3288 * Setup the HW Rx Head and Tail Descriptor Pointers and
3289 * the Base and Length of the Rx Descriptor Ring
3290 */
3291 for (i = 0; i < adapter->num_rx_queues; i++)
3292 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3293
3294 /* disable drop enable for 82598 parts */
3295 if (hw->mac.type == ixgbe_mac_82598EB)
3296 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3297
3298 /* enable all receives */
3299 rxctrl |= IXGBE_RXCTRL_RXEN;
3300 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3301 }
3302
3303 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3304 {
3305 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3306 struct ixgbe_hw *hw = &adapter->hw;
3307 int pool_ndx = adapter->num_vfs;
3308
3309 /* add VID to filter table */
3310 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3311 set_bit(vid, adapter->active_vlans);
3312
3313 return 0;
3314 }
3315
3316 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3317 {
3318 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3319 struct ixgbe_hw *hw = &adapter->hw;
3320 int pool_ndx = adapter->num_vfs;
3321
3322 /* remove VID from filter table */
3323 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3324 clear_bit(vid, adapter->active_vlans);
3325
3326 return 0;
3327 }
3328
3329 /**
3330 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3331 * @adapter: driver data
3332 */
3333 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3334 {
3335 struct ixgbe_hw *hw = &adapter->hw;
3336 u32 vlnctrl;
3337
3338 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3339 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3340 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3341 }
3342
3343 /**
3344 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3345 * @adapter: driver data
3346 */
3347 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3348 {
3349 struct ixgbe_hw *hw = &adapter->hw;
3350 u32 vlnctrl;
3351
3352 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3353 vlnctrl |= IXGBE_VLNCTRL_VFE;
3354 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3355 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3356 }
3357
3358 /**
3359 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3360 * @adapter: driver data
3361 */
3362 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3363 {
3364 struct ixgbe_hw *hw = &adapter->hw;
3365 u32 vlnctrl;
3366 int i, j;
3367
3368 switch (hw->mac.type) {
3369 case ixgbe_mac_82598EB:
3370 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3371 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3372 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3373 break;
3374 case ixgbe_mac_82599EB:
3375 case ixgbe_mac_X540:
3376 for (i = 0; i < adapter->num_rx_queues; i++) {
3377 j = adapter->rx_ring[i]->reg_idx;
3378 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3379 vlnctrl &= ~IXGBE_RXDCTL_VME;
3380 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3381 }
3382 break;
3383 default:
3384 break;
3385 }
3386 }
3387
3388 /**
3389 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3390 * @adapter: driver data
3391 */
3392 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3393 {
3394 struct ixgbe_hw *hw = &adapter->hw;
3395 u32 vlnctrl;
3396 int i, j;
3397
3398 switch (hw->mac.type) {
3399 case ixgbe_mac_82598EB:
3400 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3401 vlnctrl |= IXGBE_VLNCTRL_VME;
3402 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3403 break;
3404 case ixgbe_mac_82599EB:
3405 case ixgbe_mac_X540:
3406 for (i = 0; i < adapter->num_rx_queues; i++) {
3407 j = adapter->rx_ring[i]->reg_idx;
3408 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3409 vlnctrl |= IXGBE_RXDCTL_VME;
3410 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3411 }
3412 break;
3413 default:
3414 break;
3415 }
3416 }
3417
3418 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3419 {
3420 u16 vid;
3421
3422 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3423
3424 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3425 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3426 }
3427
3428 /**
3429 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3430 * @netdev: network interface device structure
3431 *
3432 * Writes unicast address list to the RAR table.
3433 * Returns: -ENOMEM on failure/insufficient address space
3434 * 0 on no addresses written
3435 * X on writing X addresses to the RAR table
3436 **/
3437 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3438 {
3439 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3440 struct ixgbe_hw *hw = &adapter->hw;
3441 unsigned int vfn = adapter->num_vfs;
3442 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3443 int count = 0;
3444
3445 /* return ENOMEM indicating insufficient memory for addresses */
3446 if (netdev_uc_count(netdev) > rar_entries)
3447 return -ENOMEM;
3448
3449 if (!netdev_uc_empty(netdev) && rar_entries) {
3450 struct netdev_hw_addr *ha;
3451 /* return error if we do not support writing to RAR table */
3452 if (!hw->mac.ops.set_rar)
3453 return -ENOMEM;
3454
3455 netdev_for_each_uc_addr(ha, netdev) {
3456 if (!rar_entries)
3457 break;
3458 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3459 vfn, IXGBE_RAH_AV);
3460 count++;
3461 }
3462 }
3463 /* write the addresses in reverse order to avoid write combining */
3464 for (; rar_entries > 0 ; rar_entries--)
3465 hw->mac.ops.clear_rar(hw, rar_entries);
3466
3467 return count;
3468 }
3469
3470 /**
3471 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3472 * @netdev: network interface device structure
3473 *
3474 * The set_rx_method entry point is called whenever the unicast/multicast
3475 * address list or the network interface flags are updated. This routine is
3476 * responsible for configuring the hardware for proper unicast, multicast and
3477 * promiscuous mode.
3478 **/
3479 void ixgbe_set_rx_mode(struct net_device *netdev)
3480 {
3481 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3482 struct ixgbe_hw *hw = &adapter->hw;
3483 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3484 int count;
3485
3486 /* Check for Promiscuous and All Multicast modes */
3487
3488 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3489
3490 /* set all bits that we expect to always be set */
3491 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3492 fctrl |= IXGBE_FCTRL_BAM;
3493 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3494 fctrl |= IXGBE_FCTRL_PMCF;
3495
3496 /* clear the bits we are changing the status of */
3497 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3498
3499 if (netdev->flags & IFF_PROMISC) {
3500 hw->addr_ctrl.user_set_promisc = true;
3501 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3502 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3503 /* don't hardware filter vlans in promisc mode */
3504 ixgbe_vlan_filter_disable(adapter);
3505 } else {
3506 if (netdev->flags & IFF_ALLMULTI) {
3507 fctrl |= IXGBE_FCTRL_MPE;
3508 vmolr |= IXGBE_VMOLR_MPE;
3509 } else {
3510 /*
3511 * Write addresses to the MTA, if the attempt fails
3512 * then we should just turn on promiscuous mode so
3513 * that we can at least receive multicast traffic
3514 */
3515 hw->mac.ops.update_mc_addr_list(hw, netdev);
3516 vmolr |= IXGBE_VMOLR_ROMPE;
3517 }
3518 ixgbe_vlan_filter_enable(adapter);
3519 hw->addr_ctrl.user_set_promisc = false;
3520 }
3521
3522 /*
3523 * Write addresses to available RAR registers, if there is not
3524 * sufficient space to store all the addresses then enable
3525 * unicast promiscuous mode
3526 */
3527 count = ixgbe_write_uc_addr_list(netdev);
3528 if (count < 0) {
3529 fctrl |= IXGBE_FCTRL_UPE;
3530 vmolr |= IXGBE_VMOLR_ROPE;
3531 }
3532
3533 if (adapter->num_vfs) {
3534 ixgbe_restore_vf_multicasts(adapter);
3535 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3536 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3537 IXGBE_VMOLR_ROPE);
3538 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3539 }
3540
3541 /* This is useful for sniffing bad packets. */
3542 if (adapter->netdev->features & NETIF_F_RXALL) {
3543 /* UPE and MPE will be handled by normal PROMISC logic
3544 * in e1000e_set_rx_mode */
3545 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3546 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3547 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3548
3549 fctrl &= ~(IXGBE_FCTRL_DPF);
3550 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3551 }
3552
3553 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3554
3555 if (netdev->features & NETIF_F_HW_VLAN_RX)
3556 ixgbe_vlan_strip_enable(adapter);
3557 else
3558 ixgbe_vlan_strip_disable(adapter);
3559 }
3560
3561 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3562 {
3563 int q_idx;
3564 struct ixgbe_q_vector *q_vector;
3565 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3566
3567 /* legacy and MSI only use one vector */
3568 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3569 q_vectors = 1;
3570
3571 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3572 q_vector = adapter->q_vector[q_idx];
3573 napi_enable(&q_vector->napi);
3574 }
3575 }
3576
3577 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3578 {
3579 int q_idx;
3580 struct ixgbe_q_vector *q_vector;
3581 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3582
3583 /* legacy and MSI only use one vector */
3584 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3585 q_vectors = 1;
3586
3587 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3588 q_vector = adapter->q_vector[q_idx];
3589 napi_disable(&q_vector->napi);
3590 }
3591 }
3592
3593 #ifdef CONFIG_IXGBE_DCB
3594 /**
3595 * ixgbe_configure_dcb - Configure DCB hardware
3596 * @adapter: ixgbe adapter struct
3597 *
3598 * This is called by the driver on open to configure the DCB hardware.
3599 * This is also called by the gennetlink interface when reconfiguring
3600 * the DCB state.
3601 */
3602 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3603 {
3604 struct ixgbe_hw *hw = &adapter->hw;
3605 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3606
3607 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3608 if (hw->mac.type == ixgbe_mac_82598EB)
3609 netif_set_gso_max_size(adapter->netdev, 65536);
3610 return;
3611 }
3612
3613 if (hw->mac.type == ixgbe_mac_82598EB)
3614 netif_set_gso_max_size(adapter->netdev, 32768);
3615
3616 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3617
3618 #ifdef IXGBE_FCOE
3619 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3620 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3621 #endif
3622
3623 /* reconfigure the hardware */
3624 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3625 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3626 DCB_TX_CONFIG);
3627 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3628 DCB_RX_CONFIG);
3629 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3630 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3631 ixgbe_dcb_hw_ets(&adapter->hw,
3632 adapter->ixgbe_ieee_ets,
3633 max_frame);
3634 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3635 adapter->ixgbe_ieee_pfc->pfc_en,
3636 adapter->ixgbe_ieee_ets->prio_tc);
3637 }
3638
3639 /* Enable RSS Hash per TC */
3640 if (hw->mac.type != ixgbe_mac_82598EB) {
3641 int i;
3642 u32 reg = 0;
3643
3644 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3645 u8 msb = 0;
3646 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3647
3648 while (cnt >>= 1)
3649 msb++;
3650
3651 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3652 }
3653 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3654 }
3655 }
3656 #endif
3657
3658 /* Additional bittime to account for IXGBE framing */
3659 #define IXGBE_ETH_FRAMING 20
3660
3661 /**
3662 * ixgbe_hpbthresh - calculate high water mark for flow control
3663 *
3664 * @adapter: board private structure to calculate for
3665 * @pb: packet buffer to calculate
3666 */
3667 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3668 {
3669 struct ixgbe_hw *hw = &adapter->hw;
3670 struct net_device *dev = adapter->netdev;
3671 int link, tc, kb, marker;
3672 u32 dv_id, rx_pba;
3673
3674 /* Calculate max LAN frame size */
3675 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3676
3677 #ifdef IXGBE_FCOE
3678 /* FCoE traffic class uses FCOE jumbo frames */
3679 if (dev->features & NETIF_F_FCOE_MTU) {
3680 int fcoe_pb = 0;
3681
3682 #ifdef CONFIG_IXGBE_DCB
3683 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3684
3685 #endif
3686 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3687 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3688 }
3689 #endif
3690
3691 /* Calculate delay value for device */
3692 switch (hw->mac.type) {
3693 case ixgbe_mac_X540:
3694 dv_id = IXGBE_DV_X540(link, tc);
3695 break;
3696 default:
3697 dv_id = IXGBE_DV(link, tc);
3698 break;
3699 }
3700
3701 /* Loopback switch introduces additional latency */
3702 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3703 dv_id += IXGBE_B2BT(tc);
3704
3705 /* Delay value is calculated in bit times convert to KB */
3706 kb = IXGBE_BT2KB(dv_id);
3707 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3708
3709 marker = rx_pba - kb;
3710
3711 /* It is possible that the packet buffer is not large enough
3712 * to provide required headroom. In this case throw an error
3713 * to user and a do the best we can.
3714 */
3715 if (marker < 0) {
3716 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3717 "headroom to support flow control."
3718 "Decrease MTU or number of traffic classes\n", pb);
3719 marker = tc + 1;
3720 }
3721
3722 return marker;
3723 }
3724
3725 /**
3726 * ixgbe_lpbthresh - calculate low water mark for for flow control
3727 *
3728 * @adapter: board private structure to calculate for
3729 * @pb: packet buffer to calculate
3730 */
3731 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3732 {
3733 struct ixgbe_hw *hw = &adapter->hw;
3734 struct net_device *dev = adapter->netdev;
3735 int tc;
3736 u32 dv_id;
3737
3738 /* Calculate max LAN frame size */
3739 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3740
3741 /* Calculate delay value for device */
3742 switch (hw->mac.type) {
3743 case ixgbe_mac_X540:
3744 dv_id = IXGBE_LOW_DV_X540(tc);
3745 break;
3746 default:
3747 dv_id = IXGBE_LOW_DV(tc);
3748 break;
3749 }
3750
3751 /* Delay value is calculated in bit times convert to KB */
3752 return IXGBE_BT2KB(dv_id);
3753 }
3754
3755 /*
3756 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3757 */
3758 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3759 {
3760 struct ixgbe_hw *hw = &adapter->hw;
3761 int num_tc = netdev_get_num_tc(adapter->netdev);
3762 int i;
3763
3764 if (!num_tc)
3765 num_tc = 1;
3766
3767 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3768
3769 for (i = 0; i < num_tc; i++) {
3770 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3771
3772 /* Low water marks must not be larger than high water marks */
3773 if (hw->fc.low_water > hw->fc.high_water[i])
3774 hw->fc.low_water = 0;
3775 }
3776 }
3777
3778 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3779 {
3780 struct ixgbe_hw *hw = &adapter->hw;
3781 int hdrm;
3782 u8 tc = netdev_get_num_tc(adapter->netdev);
3783
3784 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3785 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3786 hdrm = 32 << adapter->fdir_pballoc;
3787 else
3788 hdrm = 0;
3789
3790 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3791 ixgbe_pbthresh_setup(adapter);
3792 }
3793
3794 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3795 {
3796 struct ixgbe_hw *hw = &adapter->hw;
3797 struct hlist_node *node, *node2;
3798 struct ixgbe_fdir_filter *filter;
3799
3800 spin_lock(&adapter->fdir_perfect_lock);
3801
3802 if (!hlist_empty(&adapter->fdir_filter_list))
3803 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3804
3805 hlist_for_each_entry_safe(filter, node, node2,
3806 &adapter->fdir_filter_list, fdir_node) {
3807 ixgbe_fdir_write_perfect_filter_82599(hw,
3808 &filter->filter,
3809 filter->sw_idx,
3810 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3811 IXGBE_FDIR_DROP_QUEUE :
3812 adapter->rx_ring[filter->action]->reg_idx);
3813 }
3814
3815 spin_unlock(&adapter->fdir_perfect_lock);
3816 }
3817
3818 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3819 {
3820 struct ixgbe_hw *hw = &adapter->hw;
3821
3822 ixgbe_configure_pb(adapter);
3823 #ifdef CONFIG_IXGBE_DCB
3824 ixgbe_configure_dcb(adapter);
3825 #endif
3826
3827 ixgbe_set_rx_mode(adapter->netdev);
3828 ixgbe_restore_vlan(adapter);
3829
3830 #ifdef IXGBE_FCOE
3831 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3832 ixgbe_configure_fcoe(adapter);
3833
3834 #endif /* IXGBE_FCOE */
3835
3836 switch (hw->mac.type) {
3837 case ixgbe_mac_82599EB:
3838 case ixgbe_mac_X540:
3839 hw->mac.ops.disable_rx_buff(hw);
3840 break;
3841 default:
3842 break;
3843 }
3844
3845 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3846 ixgbe_init_fdir_signature_82599(&adapter->hw,
3847 adapter->fdir_pballoc);
3848 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3849 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3850 adapter->fdir_pballoc);
3851 ixgbe_fdir_filter_restore(adapter);
3852 }
3853
3854 switch (hw->mac.type) {
3855 case ixgbe_mac_82599EB:
3856 case ixgbe_mac_X540:
3857 hw->mac.ops.enable_rx_buff(hw);
3858 break;
3859 default:
3860 break;
3861 }
3862
3863 ixgbe_configure_virtualization(adapter);
3864
3865 ixgbe_configure_tx(adapter);
3866 ixgbe_configure_rx(adapter);
3867 }
3868
3869 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3870 {
3871 switch (hw->phy.type) {
3872 case ixgbe_phy_sfp_avago:
3873 case ixgbe_phy_sfp_ftl:
3874 case ixgbe_phy_sfp_intel:
3875 case ixgbe_phy_sfp_unknown:
3876 case ixgbe_phy_sfp_passive_tyco:
3877 case ixgbe_phy_sfp_passive_unknown:
3878 case ixgbe_phy_sfp_active_unknown:
3879 case ixgbe_phy_sfp_ftl_active:
3880 return true;
3881 case ixgbe_phy_nl:
3882 if (hw->mac.type == ixgbe_mac_82598EB)
3883 return true;
3884 default:
3885 return false;
3886 }
3887 }
3888
3889 /**
3890 * ixgbe_sfp_link_config - set up SFP+ link
3891 * @adapter: pointer to private adapter struct
3892 **/
3893 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3894 {
3895 /*
3896 * We are assuming the worst case scenario here, and that
3897 * is that an SFP was inserted/removed after the reset
3898 * but before SFP detection was enabled. As such the best
3899 * solution is to just start searching as soon as we start
3900 */
3901 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3902 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3903
3904 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3905 }
3906
3907 /**
3908 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3909 * @hw: pointer to private hardware struct
3910 *
3911 * Returns 0 on success, negative on failure
3912 **/
3913 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3914 {
3915 u32 autoneg;
3916 bool negotiation, link_up = false;
3917 u32 ret = IXGBE_ERR_LINK_SETUP;
3918
3919 if (hw->mac.ops.check_link)
3920 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3921
3922 if (ret)
3923 goto link_cfg_out;
3924
3925 autoneg = hw->phy.autoneg_advertised;
3926 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3927 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3928 &negotiation);
3929 if (ret)
3930 goto link_cfg_out;
3931
3932 if (hw->mac.ops.setup_link)
3933 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3934 link_cfg_out:
3935 return ret;
3936 }
3937
3938 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3939 {
3940 struct ixgbe_hw *hw = &adapter->hw;
3941 u32 gpie = 0;
3942
3943 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3944 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3945 IXGBE_GPIE_OCD;
3946 gpie |= IXGBE_GPIE_EIAME;
3947 /*
3948 * use EIAM to auto-mask when MSI-X interrupt is asserted
3949 * this saves a register write for every interrupt
3950 */
3951 switch (hw->mac.type) {
3952 case ixgbe_mac_82598EB:
3953 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3954 break;
3955 case ixgbe_mac_82599EB:
3956 case ixgbe_mac_X540:
3957 default:
3958 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3959 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3960 break;
3961 }
3962 } else {
3963 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3964 * specifically only auto mask tx and rx interrupts */
3965 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3966 }
3967
3968 /* XXX: to interrupt immediately for EICS writes, enable this */
3969 /* gpie |= IXGBE_GPIE_EIMEN; */
3970
3971 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3972 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3973 gpie |= IXGBE_GPIE_VTMODE_64;
3974 }
3975
3976 /* Enable Thermal over heat sensor interrupt */
3977 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3978 switch (adapter->hw.mac.type) {
3979 case ixgbe_mac_82599EB:
3980 gpie |= IXGBE_SDP0_GPIEN;
3981 break;
3982 case ixgbe_mac_X540:
3983 gpie |= IXGBE_EIMS_TS;
3984 break;
3985 default:
3986 break;
3987 }
3988 }
3989
3990 /* Enable fan failure interrupt */
3991 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3992 gpie |= IXGBE_SDP1_GPIEN;
3993
3994 if (hw->mac.type == ixgbe_mac_82599EB) {
3995 gpie |= IXGBE_SDP1_GPIEN;
3996 gpie |= IXGBE_SDP2_GPIEN;
3997 }
3998
3999 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4000 }
4001
4002 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4003 {
4004 struct ixgbe_hw *hw = &adapter->hw;
4005 int err;
4006 u32 ctrl_ext;
4007
4008 ixgbe_get_hw_control(adapter);
4009 ixgbe_setup_gpie(adapter);
4010
4011 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4012 ixgbe_configure_msix(adapter);
4013 else
4014 ixgbe_configure_msi_and_legacy(adapter);
4015
4016 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
4017 if (hw->mac.ops.enable_tx_laser &&
4018 ((hw->phy.multispeed_fiber) ||
4019 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4020 (hw->mac.type == ixgbe_mac_82599EB))))
4021 hw->mac.ops.enable_tx_laser(hw);
4022
4023 clear_bit(__IXGBE_DOWN, &adapter->state);
4024 ixgbe_napi_enable_all(adapter);
4025
4026 if (ixgbe_is_sfp(hw)) {
4027 ixgbe_sfp_link_config(adapter);
4028 } else {
4029 err = ixgbe_non_sfp_link_config(hw);
4030 if (err)
4031 e_err(probe, "link_config FAILED %d\n", err);
4032 }
4033
4034 /* clear any pending interrupts, may auto mask */
4035 IXGBE_READ_REG(hw, IXGBE_EICR);
4036 ixgbe_irq_enable(adapter, true, true);
4037
4038 /*
4039 * If this adapter has a fan, check to see if we had a failure
4040 * before we enabled the interrupt.
4041 */
4042 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4043 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4044 if (esdp & IXGBE_ESDP_SDP1)
4045 e_crit(drv, "Fan has stopped, replace the adapter\n");
4046 }
4047
4048 /* enable transmits */
4049 netif_tx_start_all_queues(adapter->netdev);
4050
4051 /* bring the link up in the watchdog, this could race with our first
4052 * link up interrupt but shouldn't be a problem */
4053 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4054 adapter->link_check_timeout = jiffies;
4055 mod_timer(&adapter->service_timer, jiffies);
4056
4057 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4058 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4059 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4060 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4061 }
4062
4063 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4064 {
4065 WARN_ON(in_interrupt());
4066 /* put off any impending NetWatchDogTimeout */
4067 adapter->netdev->trans_start = jiffies;
4068
4069 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4070 usleep_range(1000, 2000);
4071 ixgbe_down(adapter);
4072 /*
4073 * If SR-IOV enabled then wait a bit before bringing the adapter
4074 * back up to give the VFs time to respond to the reset. The
4075 * two second wait is based upon the watchdog timer cycle in
4076 * the VF driver.
4077 */
4078 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4079 msleep(2000);
4080 ixgbe_up(adapter);
4081 clear_bit(__IXGBE_RESETTING, &adapter->state);
4082 }
4083
4084 void ixgbe_up(struct ixgbe_adapter *adapter)
4085 {
4086 /* hardware has been reset, we need to reload some things */
4087 ixgbe_configure(adapter);
4088
4089 ixgbe_up_complete(adapter);
4090 }
4091
4092 void ixgbe_reset(struct ixgbe_adapter *adapter)
4093 {
4094 struct ixgbe_hw *hw = &adapter->hw;
4095 int err;
4096
4097 /* lock SFP init bit to prevent race conditions with the watchdog */
4098 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4099 usleep_range(1000, 2000);
4100
4101 /* clear all SFP and link config related flags while holding SFP_INIT */
4102 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4103 IXGBE_FLAG2_SFP_NEEDS_RESET);
4104 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4105
4106 err = hw->mac.ops.init_hw(hw);
4107 switch (err) {
4108 case 0:
4109 case IXGBE_ERR_SFP_NOT_PRESENT:
4110 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4111 break;
4112 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4113 e_dev_err("master disable timed out\n");
4114 break;
4115 case IXGBE_ERR_EEPROM_VERSION:
4116 /* We are running on a pre-production device, log a warning */
4117 e_dev_warn("This device is a pre-production adapter/LOM. "
4118 "Please be aware there may be issues associated with "
4119 "your hardware. If you are experiencing problems "
4120 "please contact your Intel or hardware "
4121 "representative who provided you with this "
4122 "hardware.\n");
4123 break;
4124 default:
4125 e_dev_err("Hardware Error: %d\n", err);
4126 }
4127
4128 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4129
4130 /* reprogram the RAR[0] in case user changed it. */
4131 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4132 IXGBE_RAH_AV);
4133 }
4134
4135 /**
4136 * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers
4137 * @rx_ring: ring to setup
4138 *
4139 * On many IA platforms the L1 cache has a critical stride of 4K, this
4140 * results in each receive buffer starting in the same cache set. To help
4141 * reduce the pressure on this cache set we can interleave the offsets so
4142 * that only every other buffer will be in the same cache set.
4143 **/
4144 static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring)
4145 {
4146 struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info;
4147 u16 i;
4148
4149 for (i = 0; i < rx_ring->count; i += 2) {
4150 rx_buffer[0].page_offset = 0;
4151 rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring);
4152 rx_buffer = &rx_buffer[2];
4153 }
4154 }
4155
4156 /**
4157 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4158 * @rx_ring: ring to free buffers from
4159 **/
4160 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4161 {
4162 struct device *dev = rx_ring->dev;
4163 unsigned long size;
4164 u16 i;
4165
4166 /* ring already cleared, nothing to do */
4167 if (!rx_ring->rx_buffer_info)
4168 return;
4169
4170 /* Free all the Rx ring sk_buffs */
4171 for (i = 0; i < rx_ring->count; i++) {
4172 struct ixgbe_rx_buffer *rx_buffer;
4173
4174 rx_buffer = &rx_ring->rx_buffer_info[i];
4175 if (rx_buffer->skb) {
4176 struct sk_buff *skb = rx_buffer->skb;
4177 if (IXGBE_CB(skb)->page_released) {
4178 dma_unmap_page(dev,
4179 IXGBE_CB(skb)->dma,
4180 ixgbe_rx_bufsz(rx_ring),
4181 DMA_FROM_DEVICE);
4182 IXGBE_CB(skb)->page_released = false;
4183 }
4184 dev_kfree_skb(skb);
4185 }
4186 rx_buffer->skb = NULL;
4187 if (rx_buffer->dma)
4188 dma_unmap_page(dev, rx_buffer->dma,
4189 ixgbe_rx_pg_size(rx_ring),
4190 DMA_FROM_DEVICE);
4191 rx_buffer->dma = 0;
4192 if (rx_buffer->page)
4193 __free_pages(rx_buffer->page,
4194 ixgbe_rx_pg_order(rx_ring));
4195 rx_buffer->page = NULL;
4196 }
4197
4198 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4199 memset(rx_ring->rx_buffer_info, 0, size);
4200
4201 ixgbe_init_rx_page_offset(rx_ring);
4202
4203 /* Zero out the descriptor ring */
4204 memset(rx_ring->desc, 0, rx_ring->size);
4205
4206 rx_ring->next_to_alloc = 0;
4207 rx_ring->next_to_clean = 0;
4208 rx_ring->next_to_use = 0;
4209 }
4210
4211 /**
4212 * ixgbe_clean_tx_ring - Free Tx Buffers
4213 * @tx_ring: ring to be cleaned
4214 **/
4215 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4216 {
4217 struct ixgbe_tx_buffer *tx_buffer_info;
4218 unsigned long size;
4219 u16 i;
4220
4221 /* ring already cleared, nothing to do */
4222 if (!tx_ring->tx_buffer_info)
4223 return;
4224
4225 /* Free all the Tx ring sk_buffs */
4226 for (i = 0; i < tx_ring->count; i++) {
4227 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4228 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4229 }
4230
4231 netdev_tx_reset_queue(txring_txq(tx_ring));
4232
4233 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4234 memset(tx_ring->tx_buffer_info, 0, size);
4235
4236 /* Zero out the descriptor ring */
4237 memset(tx_ring->desc, 0, tx_ring->size);
4238
4239 tx_ring->next_to_use = 0;
4240 tx_ring->next_to_clean = 0;
4241 }
4242
4243 /**
4244 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4245 * @adapter: board private structure
4246 **/
4247 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4248 {
4249 int i;
4250
4251 for (i = 0; i < adapter->num_rx_queues; i++)
4252 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4253 }
4254
4255 /**
4256 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4257 * @adapter: board private structure
4258 **/
4259 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4260 {
4261 int i;
4262
4263 for (i = 0; i < adapter->num_tx_queues; i++)
4264 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4265 }
4266
4267 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4268 {
4269 struct hlist_node *node, *node2;
4270 struct ixgbe_fdir_filter *filter;
4271
4272 spin_lock(&adapter->fdir_perfect_lock);
4273
4274 hlist_for_each_entry_safe(filter, node, node2,
4275 &adapter->fdir_filter_list, fdir_node) {
4276 hlist_del(&filter->fdir_node);
4277 kfree(filter);
4278 }
4279 adapter->fdir_filter_count = 0;
4280
4281 spin_unlock(&adapter->fdir_perfect_lock);
4282 }
4283
4284 void ixgbe_down(struct ixgbe_adapter *adapter)
4285 {
4286 struct net_device *netdev = adapter->netdev;
4287 struct ixgbe_hw *hw = &adapter->hw;
4288 u32 rxctrl;
4289 int i;
4290
4291 /* signal that we are down to the interrupt handler */
4292 set_bit(__IXGBE_DOWN, &adapter->state);
4293
4294 /* disable receives */
4295 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4296 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4297
4298 /* disable all enabled rx queues */
4299 for (i = 0; i < adapter->num_rx_queues; i++)
4300 /* this call also flushes the previous write */
4301 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4302
4303 usleep_range(10000, 20000);
4304
4305 netif_tx_stop_all_queues(netdev);
4306
4307 /* call carrier off first to avoid false dev_watchdog timeouts */
4308 netif_carrier_off(netdev);
4309 netif_tx_disable(netdev);
4310
4311 ixgbe_irq_disable(adapter);
4312
4313 ixgbe_napi_disable_all(adapter);
4314
4315 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4316 IXGBE_FLAG2_RESET_REQUESTED);
4317 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4318
4319 del_timer_sync(&adapter->service_timer);
4320
4321 if (adapter->num_vfs) {
4322 /* Clear EITR Select mapping */
4323 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4324
4325 /* Mark all the VFs as inactive */
4326 for (i = 0 ; i < adapter->num_vfs; i++)
4327 adapter->vfinfo[i].clear_to_send = false;
4328
4329 /* ping all the active vfs to let them know we are going down */
4330 ixgbe_ping_all_vfs(adapter);
4331
4332 /* Disable all VFTE/VFRE TX/RX */
4333 ixgbe_disable_tx_rx(adapter);
4334 }
4335
4336 /* disable transmits in the hardware now that interrupts are off */
4337 for (i = 0; i < adapter->num_tx_queues; i++) {
4338 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4339 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4340 }
4341
4342 /* Disable the Tx DMA engine on 82599 and X540 */
4343 switch (hw->mac.type) {
4344 case ixgbe_mac_82599EB:
4345 case ixgbe_mac_X540:
4346 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4347 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4348 ~IXGBE_DMATXCTL_TE));
4349 break;
4350 default:
4351 break;
4352 }
4353
4354 if (!pci_channel_offline(adapter->pdev))
4355 ixgbe_reset(adapter);
4356
4357 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4358 if (hw->mac.ops.disable_tx_laser &&
4359 ((hw->phy.multispeed_fiber) ||
4360 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4361 (hw->mac.type == ixgbe_mac_82599EB))))
4362 hw->mac.ops.disable_tx_laser(hw);
4363
4364 ixgbe_clean_all_tx_rings(adapter);
4365 ixgbe_clean_all_rx_rings(adapter);
4366
4367 #ifdef CONFIG_IXGBE_DCA
4368 /* since we reset the hardware DCA settings were cleared */
4369 ixgbe_setup_dca(adapter);
4370 #endif
4371 }
4372
4373 /**
4374 * ixgbe_tx_timeout - Respond to a Tx Hang
4375 * @netdev: network interface device structure
4376 **/
4377 static void ixgbe_tx_timeout(struct net_device *netdev)
4378 {
4379 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4380
4381 /* Do the reset outside of interrupt context */
4382 ixgbe_tx_timeout_reset(adapter);
4383 }
4384
4385 /**
4386 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4387 * @adapter: board private structure to initialize
4388 *
4389 * ixgbe_sw_init initializes the Adapter private data structure.
4390 * Fields are initialized based on PCI device information and
4391 * OS network device settings (MTU size).
4392 **/
4393 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4394 {
4395 struct ixgbe_hw *hw = &adapter->hw;
4396 struct pci_dev *pdev = adapter->pdev;
4397 unsigned int rss;
4398 #ifdef CONFIG_IXGBE_DCB
4399 int j;
4400 struct tc_configuration *tc;
4401 #endif
4402
4403 /* PCI config space info */
4404
4405 hw->vendor_id = pdev->vendor;
4406 hw->device_id = pdev->device;
4407 hw->revision_id = pdev->revision;
4408 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4409 hw->subsystem_device_id = pdev->subsystem_device;
4410
4411 /* Set capability flags */
4412 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4413 adapter->ring_feature[RING_F_RSS].indices = rss;
4414 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4415 switch (hw->mac.type) {
4416 case ixgbe_mac_82598EB:
4417 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4418 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4419 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4420 break;
4421 case ixgbe_mac_X540:
4422 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4423 case ixgbe_mac_82599EB:
4424 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4425 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4426 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4427 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4428 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4429 /* Flow Director hash filters enabled */
4430 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4431 adapter->atr_sample_rate = 20;
4432 adapter->ring_feature[RING_F_FDIR].indices =
4433 IXGBE_MAX_FDIR_INDICES;
4434 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4435 #ifdef IXGBE_FCOE
4436 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4437 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4438 adapter->ring_feature[RING_F_FCOE].indices = 0;
4439 #ifdef CONFIG_IXGBE_DCB
4440 /* Default traffic class to use for FCoE */
4441 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4442 #endif
4443 #endif /* IXGBE_FCOE */
4444 break;
4445 default:
4446 break;
4447 }
4448
4449 /* n-tuple support exists, always init our spinlock */
4450 spin_lock_init(&adapter->fdir_perfect_lock);
4451
4452 #ifdef CONFIG_IXGBE_DCB
4453 switch (hw->mac.type) {
4454 case ixgbe_mac_X540:
4455 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4456 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4457 break;
4458 default:
4459 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4460 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4461 break;
4462 }
4463
4464 /* Configure DCB traffic classes */
4465 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4466 tc = &adapter->dcb_cfg.tc_config[j];
4467 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4468 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4469 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4470 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4471 tc->dcb_pfc = pfc_disabled;
4472 }
4473
4474 /* Initialize default user to priority mapping, UPx->TC0 */
4475 tc = &adapter->dcb_cfg.tc_config[0];
4476 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4477 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4478
4479 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4480 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4481 adapter->dcb_cfg.pfc_mode_enable = false;
4482 adapter->dcb_set_bitmap = 0x00;
4483 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4484 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4485 sizeof(adapter->temp_dcb_cfg));
4486
4487 #endif
4488
4489 /* default flow control settings */
4490 hw->fc.requested_mode = ixgbe_fc_full;
4491 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4492 ixgbe_pbthresh_setup(adapter);
4493 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4494 hw->fc.send_xon = true;
4495 hw->fc.disable_fc_autoneg = false;
4496
4497 /* enable itr by default in dynamic mode */
4498 adapter->rx_itr_setting = 1;
4499 adapter->tx_itr_setting = 1;
4500
4501 /* set default ring sizes */
4502 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4503 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4504
4505 /* set default work limits */
4506 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4507
4508 /* initialize eeprom parameters */
4509 if (ixgbe_init_eeprom_params_generic(hw)) {
4510 e_dev_err("EEPROM initialization failed\n");
4511 return -EIO;
4512 }
4513
4514 set_bit(__IXGBE_DOWN, &adapter->state);
4515
4516 return 0;
4517 }
4518
4519 /**
4520 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4521 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4522 *
4523 * Return 0 on success, negative on failure
4524 **/
4525 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4526 {
4527 struct device *dev = tx_ring->dev;
4528 int orig_node = dev_to_node(dev);
4529 int numa_node = -1;
4530 int size;
4531
4532 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4533
4534 if (tx_ring->q_vector)
4535 numa_node = tx_ring->q_vector->numa_node;
4536
4537 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4538 if (!tx_ring->tx_buffer_info)
4539 tx_ring->tx_buffer_info = vzalloc(size);
4540 if (!tx_ring->tx_buffer_info)
4541 goto err;
4542
4543 /* round up to nearest 4K */
4544 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4545 tx_ring->size = ALIGN(tx_ring->size, 4096);
4546
4547 set_dev_node(dev, numa_node);
4548 tx_ring->desc = dma_alloc_coherent(dev,
4549 tx_ring->size,
4550 &tx_ring->dma,
4551 GFP_KERNEL);
4552 set_dev_node(dev, orig_node);
4553 if (!tx_ring->desc)
4554 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4555 &tx_ring->dma, GFP_KERNEL);
4556 if (!tx_ring->desc)
4557 goto err;
4558
4559 tx_ring->next_to_use = 0;
4560 tx_ring->next_to_clean = 0;
4561 return 0;
4562
4563 err:
4564 vfree(tx_ring->tx_buffer_info);
4565 tx_ring->tx_buffer_info = NULL;
4566 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4567 return -ENOMEM;
4568 }
4569
4570 /**
4571 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4572 * @adapter: board private structure
4573 *
4574 * If this function returns with an error, then it's possible one or
4575 * more of the rings is populated (while the rest are not). It is the
4576 * callers duty to clean those orphaned rings.
4577 *
4578 * Return 0 on success, negative on failure
4579 **/
4580 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4581 {
4582 int i, err = 0;
4583
4584 for (i = 0; i < adapter->num_tx_queues; i++) {
4585 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4586 if (!err)
4587 continue;
4588 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4589 break;
4590 }
4591
4592 return err;
4593 }
4594
4595 /**
4596 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4597 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4598 *
4599 * Returns 0 on success, negative on failure
4600 **/
4601 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4602 {
4603 struct device *dev = rx_ring->dev;
4604 int orig_node = dev_to_node(dev);
4605 int numa_node = -1;
4606 int size;
4607
4608 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4609
4610 if (rx_ring->q_vector)
4611 numa_node = rx_ring->q_vector->numa_node;
4612
4613 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4614 if (!rx_ring->rx_buffer_info)
4615 rx_ring->rx_buffer_info = vzalloc(size);
4616 if (!rx_ring->rx_buffer_info)
4617 goto err;
4618
4619 /* Round up to nearest 4K */
4620 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4621 rx_ring->size = ALIGN(rx_ring->size, 4096);
4622
4623 set_dev_node(dev, numa_node);
4624 rx_ring->desc = dma_alloc_coherent(dev,
4625 rx_ring->size,
4626 &rx_ring->dma,
4627 GFP_KERNEL);
4628 set_dev_node(dev, orig_node);
4629 if (!rx_ring->desc)
4630 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4631 &rx_ring->dma, GFP_KERNEL);
4632 if (!rx_ring->desc)
4633 goto err;
4634
4635 rx_ring->next_to_clean = 0;
4636 rx_ring->next_to_use = 0;
4637
4638 ixgbe_init_rx_page_offset(rx_ring);
4639
4640 return 0;
4641 err:
4642 vfree(rx_ring->rx_buffer_info);
4643 rx_ring->rx_buffer_info = NULL;
4644 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4645 return -ENOMEM;
4646 }
4647
4648 /**
4649 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4650 * @adapter: board private structure
4651 *
4652 * If this function returns with an error, then it's possible one or
4653 * more of the rings is populated (while the rest are not). It is the
4654 * callers duty to clean those orphaned rings.
4655 *
4656 * Return 0 on success, negative on failure
4657 **/
4658 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4659 {
4660 int i, err = 0;
4661
4662 for (i = 0; i < adapter->num_rx_queues; i++) {
4663 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4664 if (!err)
4665 continue;
4666 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4667 break;
4668 }
4669
4670 return err;
4671 }
4672
4673 /**
4674 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4675 * @tx_ring: Tx descriptor ring for a specific queue
4676 *
4677 * Free all transmit software resources
4678 **/
4679 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
4680 {
4681 ixgbe_clean_tx_ring(tx_ring);
4682
4683 vfree(tx_ring->tx_buffer_info);
4684 tx_ring->tx_buffer_info = NULL;
4685
4686 /* if not set, then don't free */
4687 if (!tx_ring->desc)
4688 return;
4689
4690 dma_free_coherent(tx_ring->dev, tx_ring->size,
4691 tx_ring->desc, tx_ring->dma);
4692
4693 tx_ring->desc = NULL;
4694 }
4695
4696 /**
4697 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4698 * @adapter: board private structure
4699 *
4700 * Free all transmit software resources
4701 **/
4702 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4703 {
4704 int i;
4705
4706 for (i = 0; i < adapter->num_tx_queues; i++)
4707 if (adapter->tx_ring[i]->desc)
4708 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4709 }
4710
4711 /**
4712 * ixgbe_free_rx_resources - Free Rx Resources
4713 * @rx_ring: ring to clean the resources from
4714 *
4715 * Free all receive software resources
4716 **/
4717 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
4718 {
4719 ixgbe_clean_rx_ring(rx_ring);
4720
4721 vfree(rx_ring->rx_buffer_info);
4722 rx_ring->rx_buffer_info = NULL;
4723
4724 /* if not set, then don't free */
4725 if (!rx_ring->desc)
4726 return;
4727
4728 dma_free_coherent(rx_ring->dev, rx_ring->size,
4729 rx_ring->desc, rx_ring->dma);
4730
4731 rx_ring->desc = NULL;
4732 }
4733
4734 /**
4735 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4736 * @adapter: board private structure
4737 *
4738 * Free all receive software resources
4739 **/
4740 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4741 {
4742 int i;
4743
4744 for (i = 0; i < adapter->num_rx_queues; i++)
4745 if (adapter->rx_ring[i]->desc)
4746 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4747 }
4748
4749 /**
4750 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4751 * @netdev: network interface device structure
4752 * @new_mtu: new value for maximum frame size
4753 *
4754 * Returns 0 on success, negative on failure
4755 **/
4756 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4757 {
4758 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4759 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4760
4761 /* MTU < 68 is an error and causes problems on some kernels */
4762 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4763 return -EINVAL;
4764
4765 /*
4766 * For 82599EB we cannot allow PF to change MTU greater than 1500
4767 * in SR-IOV mode as it may cause buffer overruns in guest VFs that
4768 * don't allocate and chain buffers correctly.
4769 */
4770 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4771 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4772 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
4773 return -EINVAL;
4774
4775 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
4776
4777 /* must set new MTU before calling down or up */
4778 netdev->mtu = new_mtu;
4779
4780 if (netif_running(netdev))
4781 ixgbe_reinit_locked(adapter);
4782
4783 return 0;
4784 }
4785
4786 /**
4787 * ixgbe_open - Called when a network interface is made active
4788 * @netdev: network interface device structure
4789 *
4790 * Returns 0 on success, negative value on failure
4791 *
4792 * The open entry point is called when a network interface is made
4793 * active by the system (IFF_UP). At this point all resources needed
4794 * for transmit and receive operations are allocated, the interrupt
4795 * handler is registered with the OS, the watchdog timer is started,
4796 * and the stack is notified that the interface is ready.
4797 **/
4798 static int ixgbe_open(struct net_device *netdev)
4799 {
4800 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4801 int err;
4802
4803 /* disallow open during test */
4804 if (test_bit(__IXGBE_TESTING, &adapter->state))
4805 return -EBUSY;
4806
4807 netif_carrier_off(netdev);
4808
4809 /* allocate transmit descriptors */
4810 err = ixgbe_setup_all_tx_resources(adapter);
4811 if (err)
4812 goto err_setup_tx;
4813
4814 /* allocate receive descriptors */
4815 err = ixgbe_setup_all_rx_resources(adapter);
4816 if (err)
4817 goto err_setup_rx;
4818
4819 ixgbe_configure(adapter);
4820
4821 err = ixgbe_request_irq(adapter);
4822 if (err)
4823 goto err_req_irq;
4824
4825 ixgbe_up_complete(adapter);
4826
4827 return 0;
4828
4829 err_req_irq:
4830 err_setup_rx:
4831 ixgbe_free_all_rx_resources(adapter);
4832 err_setup_tx:
4833 ixgbe_free_all_tx_resources(adapter);
4834 ixgbe_reset(adapter);
4835
4836 return err;
4837 }
4838
4839 /**
4840 * ixgbe_close - Disables a network interface
4841 * @netdev: network interface device structure
4842 *
4843 * Returns 0, this is not allowed to fail
4844 *
4845 * The close entry point is called when an interface is de-activated
4846 * by the OS. The hardware is still under the drivers control, but
4847 * needs to be disabled. A global MAC reset is issued to stop the
4848 * hardware, and all transmit and receive resources are freed.
4849 **/
4850 static int ixgbe_close(struct net_device *netdev)
4851 {
4852 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4853
4854 ixgbe_down(adapter);
4855 ixgbe_free_irq(adapter);
4856
4857 ixgbe_fdir_filter_exit(adapter);
4858
4859 ixgbe_free_all_tx_resources(adapter);
4860 ixgbe_free_all_rx_resources(adapter);
4861
4862 ixgbe_release_hw_control(adapter);
4863
4864 return 0;
4865 }
4866
4867 #ifdef CONFIG_PM
4868 static int ixgbe_resume(struct pci_dev *pdev)
4869 {
4870 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4871 struct net_device *netdev = adapter->netdev;
4872 u32 err;
4873
4874 pci_set_power_state(pdev, PCI_D0);
4875 pci_restore_state(pdev);
4876 /*
4877 * pci_restore_state clears dev->state_saved so call
4878 * pci_save_state to restore it.
4879 */
4880 pci_save_state(pdev);
4881
4882 err = pci_enable_device_mem(pdev);
4883 if (err) {
4884 e_dev_err("Cannot enable PCI device from suspend\n");
4885 return err;
4886 }
4887 pci_set_master(pdev);
4888
4889 pci_wake_from_d3(pdev, false);
4890
4891 rtnl_lock();
4892 err = ixgbe_init_interrupt_scheme(adapter);
4893 rtnl_unlock();
4894 if (err) {
4895 e_dev_err("Cannot initialize interrupts for device\n");
4896 return err;
4897 }
4898
4899 ixgbe_reset(adapter);
4900
4901 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4902
4903 if (netif_running(netdev)) {
4904 err = ixgbe_open(netdev);
4905 if (err)
4906 return err;
4907 }
4908
4909 netif_device_attach(netdev);
4910
4911 return 0;
4912 }
4913 #endif /* CONFIG_PM */
4914
4915 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4916 {
4917 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4918 struct net_device *netdev = adapter->netdev;
4919 struct ixgbe_hw *hw = &adapter->hw;
4920 u32 ctrl, fctrl;
4921 u32 wufc = adapter->wol;
4922 #ifdef CONFIG_PM
4923 int retval = 0;
4924 #endif
4925
4926 netif_device_detach(netdev);
4927
4928 if (netif_running(netdev)) {
4929 rtnl_lock();
4930 ixgbe_down(adapter);
4931 ixgbe_free_irq(adapter);
4932 ixgbe_free_all_tx_resources(adapter);
4933 ixgbe_free_all_rx_resources(adapter);
4934 rtnl_unlock();
4935 }
4936
4937 ixgbe_clear_interrupt_scheme(adapter);
4938
4939 #ifdef CONFIG_PM
4940 retval = pci_save_state(pdev);
4941 if (retval)
4942 return retval;
4943
4944 #endif
4945 if (wufc) {
4946 ixgbe_set_rx_mode(netdev);
4947
4948 /*
4949 * enable the optics for both mult-speed fiber and
4950 * 82599 SFP+ fiber as we can WoL.
4951 */
4952 if (hw->mac.ops.enable_tx_laser &&
4953 (hw->phy.multispeed_fiber ||
4954 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber &&
4955 hw->mac.type == ixgbe_mac_82599EB)))
4956 hw->mac.ops.enable_tx_laser(hw);
4957
4958 /* turn on all-multi mode if wake on multicast is enabled */
4959 if (wufc & IXGBE_WUFC_MC) {
4960 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4961 fctrl |= IXGBE_FCTRL_MPE;
4962 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4963 }
4964
4965 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4966 ctrl |= IXGBE_CTRL_GIO_DIS;
4967 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4968
4969 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4970 } else {
4971 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4972 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4973 }
4974
4975 switch (hw->mac.type) {
4976 case ixgbe_mac_82598EB:
4977 pci_wake_from_d3(pdev, false);
4978 break;
4979 case ixgbe_mac_82599EB:
4980 case ixgbe_mac_X540:
4981 pci_wake_from_d3(pdev, !!wufc);
4982 break;
4983 default:
4984 break;
4985 }
4986
4987 *enable_wake = !!wufc;
4988
4989 ixgbe_release_hw_control(adapter);
4990
4991 pci_disable_device(pdev);
4992
4993 return 0;
4994 }
4995
4996 #ifdef CONFIG_PM
4997 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4998 {
4999 int retval;
5000 bool wake;
5001
5002 retval = __ixgbe_shutdown(pdev, &wake);
5003 if (retval)
5004 return retval;
5005
5006 if (wake) {
5007 pci_prepare_to_sleep(pdev);
5008 } else {
5009 pci_wake_from_d3(pdev, false);
5010 pci_set_power_state(pdev, PCI_D3hot);
5011 }
5012
5013 return 0;
5014 }
5015 #endif /* CONFIG_PM */
5016
5017 static void ixgbe_shutdown(struct pci_dev *pdev)
5018 {
5019 bool wake;
5020
5021 __ixgbe_shutdown(pdev, &wake);
5022
5023 if (system_state == SYSTEM_POWER_OFF) {
5024 pci_wake_from_d3(pdev, wake);
5025 pci_set_power_state(pdev, PCI_D3hot);
5026 }
5027 }
5028
5029 /**
5030 * ixgbe_update_stats - Update the board statistics counters.
5031 * @adapter: board private structure
5032 **/
5033 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5034 {
5035 struct net_device *netdev = adapter->netdev;
5036 struct ixgbe_hw *hw = &adapter->hw;
5037 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5038 u64 total_mpc = 0;
5039 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5040 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5041 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5042 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5043 #ifdef IXGBE_FCOE
5044 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5045 unsigned int cpu;
5046 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5047 #endif /* IXGBE_FCOE */
5048
5049 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5050 test_bit(__IXGBE_RESETTING, &adapter->state))
5051 return;
5052
5053 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5054 u64 rsc_count = 0;
5055 u64 rsc_flush = 0;
5056 for (i = 0; i < adapter->num_rx_queues; i++) {
5057 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5058 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5059 }
5060 adapter->rsc_total_count = rsc_count;
5061 adapter->rsc_total_flush = rsc_flush;
5062 }
5063
5064 for (i = 0; i < adapter->num_rx_queues; i++) {
5065 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5066 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5067 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5068 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5069 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5070 bytes += rx_ring->stats.bytes;
5071 packets += rx_ring->stats.packets;
5072 }
5073 adapter->non_eop_descs = non_eop_descs;
5074 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5075 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5076 adapter->hw_csum_rx_error = hw_csum_rx_error;
5077 netdev->stats.rx_bytes = bytes;
5078 netdev->stats.rx_packets = packets;
5079
5080 bytes = 0;
5081 packets = 0;
5082 /* gather some stats to the adapter struct that are per queue */
5083 for (i = 0; i < adapter->num_tx_queues; i++) {
5084 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5085 restart_queue += tx_ring->tx_stats.restart_queue;
5086 tx_busy += tx_ring->tx_stats.tx_busy;
5087 bytes += tx_ring->stats.bytes;
5088 packets += tx_ring->stats.packets;
5089 }
5090 adapter->restart_queue = restart_queue;
5091 adapter->tx_busy = tx_busy;
5092 netdev->stats.tx_bytes = bytes;
5093 netdev->stats.tx_packets = packets;
5094
5095 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5096
5097 /* 8 register reads */
5098 for (i = 0; i < 8; i++) {
5099 /* for packet buffers not used, the register should read 0 */
5100 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5101 missed_rx += mpc;
5102 hwstats->mpc[i] += mpc;
5103 total_mpc += hwstats->mpc[i];
5104 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5105 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5106 switch (hw->mac.type) {
5107 case ixgbe_mac_82598EB:
5108 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5109 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5110 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5111 hwstats->pxonrxc[i] +=
5112 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5113 break;
5114 case ixgbe_mac_82599EB:
5115 case ixgbe_mac_X540:
5116 hwstats->pxonrxc[i] +=
5117 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5118 break;
5119 default:
5120 break;
5121 }
5122 }
5123
5124 /*16 register reads */
5125 for (i = 0; i < 16; i++) {
5126 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5127 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5128 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5129 (hw->mac.type == ixgbe_mac_X540)) {
5130 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5131 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5132 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5133 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5134 }
5135 }
5136
5137 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5138 /* work around hardware counting issue */
5139 hwstats->gprc -= missed_rx;
5140
5141 ixgbe_update_xoff_received(adapter);
5142
5143 /* 82598 hardware only has a 32 bit counter in the high register */
5144 switch (hw->mac.type) {
5145 case ixgbe_mac_82598EB:
5146 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5147 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5148 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5149 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5150 break;
5151 case ixgbe_mac_X540:
5152 /* OS2BMC stats are X540 only*/
5153 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5154 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5155 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5156 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5157 case ixgbe_mac_82599EB:
5158 for (i = 0; i < 16; i++)
5159 adapter->hw_rx_no_dma_resources +=
5160 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5161 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5162 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5163 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5164 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5165 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5166 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5167 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5168 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5169 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5170 #ifdef IXGBE_FCOE
5171 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5172 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5173 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5174 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5175 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5176 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5177 /* Add up per cpu counters for total ddp aloc fail */
5178 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5179 for_each_possible_cpu(cpu) {
5180 fcoe_noddp_counts_sum +=
5181 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5182 fcoe_noddp_ext_buff_counts_sum +=
5183 *per_cpu_ptr(fcoe->
5184 pcpu_noddp_ext_buff, cpu);
5185 }
5186 }
5187 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5188 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
5189 #endif /* IXGBE_FCOE */
5190 break;
5191 default:
5192 break;
5193 }
5194 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5195 hwstats->bprc += bprc;
5196 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5197 if (hw->mac.type == ixgbe_mac_82598EB)
5198 hwstats->mprc -= bprc;
5199 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5200 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5201 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5202 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5203 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5204 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5205 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5206 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5207 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5208 hwstats->lxontxc += lxon;
5209 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5210 hwstats->lxofftxc += lxoff;
5211 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5212 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5213 /*
5214 * 82598 errata - tx of flow control packets is included in tx counters
5215 */
5216 xon_off_tot = lxon + lxoff;
5217 hwstats->gptc -= xon_off_tot;
5218 hwstats->mptc -= xon_off_tot;
5219 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5220 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5221 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5222 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5223 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5224 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5225 hwstats->ptc64 -= xon_off_tot;
5226 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5227 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5228 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5229 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5230 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5231 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5232
5233 /* Fill out the OS statistics structure */
5234 netdev->stats.multicast = hwstats->mprc;
5235
5236 /* Rx Errors */
5237 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5238 netdev->stats.rx_dropped = 0;
5239 netdev->stats.rx_length_errors = hwstats->rlec;
5240 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5241 netdev->stats.rx_missed_errors = total_mpc;
5242 }
5243
5244 /**
5245 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5246 * @adapter: pointer to the device adapter structure
5247 **/
5248 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5249 {
5250 struct ixgbe_hw *hw = &adapter->hw;
5251 int i;
5252
5253 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5254 return;
5255
5256 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5257
5258 /* if interface is down do nothing */
5259 if (test_bit(__IXGBE_DOWN, &adapter->state))
5260 return;
5261
5262 /* do nothing if we are not using signature filters */
5263 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5264 return;
5265
5266 adapter->fdir_overflow++;
5267
5268 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5269 for (i = 0; i < adapter->num_tx_queues; i++)
5270 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5271 &(adapter->tx_ring[i]->state));
5272 /* re-enable flow director interrupts */
5273 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5274 } else {
5275 e_err(probe, "failed to finish FDIR re-initialization, "
5276 "ignored adding FDIR ATR filters\n");
5277 }
5278 }
5279
5280 /**
5281 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5282 * @adapter: pointer to the device adapter structure
5283 *
5284 * This function serves two purposes. First it strobes the interrupt lines
5285 * in order to make certain interrupts are occurring. Secondly it sets the
5286 * bits needed to check for TX hangs. As a result we should immediately
5287 * determine if a hang has occurred.
5288 */
5289 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5290 {
5291 struct ixgbe_hw *hw = &adapter->hw;
5292 u64 eics = 0;
5293 int i;
5294
5295 /* If we're down or resetting, just bail */
5296 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5297 test_bit(__IXGBE_RESETTING, &adapter->state))
5298 return;
5299
5300 /* Force detection of hung controller */
5301 if (netif_carrier_ok(adapter->netdev)) {
5302 for (i = 0; i < adapter->num_tx_queues; i++)
5303 set_check_for_tx_hang(adapter->tx_ring[i]);
5304 }
5305
5306 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5307 /*
5308 * for legacy and MSI interrupts don't set any bits
5309 * that are enabled for EIAM, because this operation
5310 * would set *both* EIMS and EICS for any bit in EIAM
5311 */
5312 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5313 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5314 } else {
5315 /* get one bit for every active tx/rx interrupt vector */
5316 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5317 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5318 if (qv->rx.ring || qv->tx.ring)
5319 eics |= ((u64)1 << i);
5320 }
5321 }
5322
5323 /* Cause software interrupt to ensure rings are cleaned */
5324 ixgbe_irq_rearm_queues(adapter, eics);
5325
5326 }
5327
5328 /**
5329 * ixgbe_watchdog_update_link - update the link status
5330 * @adapter: pointer to the device adapter structure
5331 * @link_speed: pointer to a u32 to store the link_speed
5332 **/
5333 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5334 {
5335 struct ixgbe_hw *hw = &adapter->hw;
5336 u32 link_speed = adapter->link_speed;
5337 bool link_up = adapter->link_up;
5338 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
5339
5340 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5341 return;
5342
5343 if (hw->mac.ops.check_link) {
5344 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5345 } else {
5346 /* always assume link is up, if no check link function */
5347 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5348 link_up = true;
5349 }
5350
5351 if (adapter->ixgbe_ieee_pfc)
5352 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5353
5354 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
5355 hw->mac.ops.fc_enable(hw);
5356 ixgbe_set_rx_drop_en(adapter);
5357 }
5358
5359 if (link_up ||
5360 time_after(jiffies, (adapter->link_check_timeout +
5361 IXGBE_TRY_LINK_TIMEOUT))) {
5362 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5363 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5364 IXGBE_WRITE_FLUSH(hw);
5365 }
5366
5367 adapter->link_up = link_up;
5368 adapter->link_speed = link_speed;
5369 }
5370
5371 /**
5372 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5373 * print link up message
5374 * @adapter: pointer to the device adapter structure
5375 **/
5376 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5377 {
5378 struct net_device *netdev = adapter->netdev;
5379 struct ixgbe_hw *hw = &adapter->hw;
5380 u32 link_speed = adapter->link_speed;
5381 bool flow_rx, flow_tx;
5382
5383 /* only continue if link was previously down */
5384 if (netif_carrier_ok(netdev))
5385 return;
5386
5387 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5388
5389 switch (hw->mac.type) {
5390 case ixgbe_mac_82598EB: {
5391 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5392 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5393 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5394 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5395 }
5396 break;
5397 case ixgbe_mac_X540:
5398 case ixgbe_mac_82599EB: {
5399 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5400 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5401 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5402 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5403 }
5404 break;
5405 default:
5406 flow_tx = false;
5407 flow_rx = false;
5408 break;
5409 }
5410
5411 #ifdef CONFIG_IXGBE_PTP
5412 ixgbe_ptp_start_cyclecounter(adapter);
5413 #endif
5414
5415 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5416 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5417 "10 Gbps" :
5418 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5419 "1 Gbps" :
5420 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5421 "100 Mbps" :
5422 "unknown speed"))),
5423 ((flow_rx && flow_tx) ? "RX/TX" :
5424 (flow_rx ? "RX" :
5425 (flow_tx ? "TX" : "None"))));
5426
5427 netif_carrier_on(netdev);
5428 ixgbe_check_vf_rate_limit(adapter);
5429 }
5430
5431 /**
5432 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5433 * print link down message
5434 * @adapter: pointer to the adapter structure
5435 **/
5436 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5437 {
5438 struct net_device *netdev = adapter->netdev;
5439 struct ixgbe_hw *hw = &adapter->hw;
5440
5441 adapter->link_up = false;
5442 adapter->link_speed = 0;
5443
5444 /* only continue if link was up previously */
5445 if (!netif_carrier_ok(netdev))
5446 return;
5447
5448 /* poll for SFP+ cable when link is down */
5449 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5450 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5451
5452 #ifdef CONFIG_IXGBE_PTP
5453 ixgbe_ptp_start_cyclecounter(adapter);
5454 #endif
5455
5456 e_info(drv, "NIC Link is Down\n");
5457 netif_carrier_off(netdev);
5458 }
5459
5460 /**
5461 * ixgbe_watchdog_flush_tx - flush queues on link down
5462 * @adapter: pointer to the device adapter structure
5463 **/
5464 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5465 {
5466 int i;
5467 int some_tx_pending = 0;
5468
5469 if (!netif_carrier_ok(adapter->netdev)) {
5470 for (i = 0; i < adapter->num_tx_queues; i++) {
5471 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5472 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5473 some_tx_pending = 1;
5474 break;
5475 }
5476 }
5477
5478 if (some_tx_pending) {
5479 /* We've lost link, so the controller stops DMA,
5480 * but we've got queued Tx work that's never going
5481 * to get done, so reset controller to flush Tx.
5482 * (Do the reset outside of interrupt context).
5483 */
5484 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5485 }
5486 }
5487 }
5488
5489 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5490 {
5491 u32 ssvpc;
5492
5493 /* Do not perform spoof check for 82598 */
5494 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5495 return;
5496
5497 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5498
5499 /*
5500 * ssvpc register is cleared on read, if zero then no
5501 * spoofed packets in the last interval.
5502 */
5503 if (!ssvpc)
5504 return;
5505
5506 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5507 }
5508
5509 /**
5510 * ixgbe_watchdog_subtask - check and bring link up
5511 * @adapter: pointer to the device adapter structure
5512 **/
5513 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5514 {
5515 /* if interface is down do nothing */
5516 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5517 test_bit(__IXGBE_RESETTING, &adapter->state))
5518 return;
5519
5520 ixgbe_watchdog_update_link(adapter);
5521
5522 if (adapter->link_up)
5523 ixgbe_watchdog_link_is_up(adapter);
5524 else
5525 ixgbe_watchdog_link_is_down(adapter);
5526
5527 ixgbe_spoof_check(adapter);
5528 ixgbe_update_stats(adapter);
5529
5530 ixgbe_watchdog_flush_tx(adapter);
5531 }
5532
5533 /**
5534 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5535 * @adapter: the ixgbe adapter structure
5536 **/
5537 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5538 {
5539 struct ixgbe_hw *hw = &adapter->hw;
5540 s32 err;
5541
5542 /* not searching for SFP so there is nothing to do here */
5543 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5544 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5545 return;
5546
5547 /* someone else is in init, wait until next service event */
5548 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5549 return;
5550
5551 err = hw->phy.ops.identify_sfp(hw);
5552 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5553 goto sfp_out;
5554
5555 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5556 /* If no cable is present, then we need to reset
5557 * the next time we find a good cable. */
5558 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5559 }
5560
5561 /* exit on error */
5562 if (err)
5563 goto sfp_out;
5564
5565 /* exit if reset not needed */
5566 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5567 goto sfp_out;
5568
5569 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5570
5571 /*
5572 * A module may be identified correctly, but the EEPROM may not have
5573 * support for that module. setup_sfp() will fail in that case, so
5574 * we should not allow that module to load.
5575 */
5576 if (hw->mac.type == ixgbe_mac_82598EB)
5577 err = hw->phy.ops.reset(hw);
5578 else
5579 err = hw->mac.ops.setup_sfp(hw);
5580
5581 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5582 goto sfp_out;
5583
5584 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5585 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5586
5587 sfp_out:
5588 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5589
5590 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5591 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5592 e_dev_err("failed to initialize because an unsupported "
5593 "SFP+ module type was detected.\n");
5594 e_dev_err("Reload the driver after installing a "
5595 "supported module.\n");
5596 unregister_netdev(adapter->netdev);
5597 }
5598 }
5599
5600 /**
5601 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5602 * @adapter: the ixgbe adapter structure
5603 **/
5604 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5605 {
5606 struct ixgbe_hw *hw = &adapter->hw;
5607 u32 autoneg;
5608 bool negotiation;
5609
5610 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5611 return;
5612
5613 /* someone else is in init, wait until next service event */
5614 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5615 return;
5616
5617 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5618
5619 autoneg = hw->phy.autoneg_advertised;
5620 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5621 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5622 if (hw->mac.ops.setup_link)
5623 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5624
5625 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5626 adapter->link_check_timeout = jiffies;
5627 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5628 }
5629
5630 #ifdef CONFIG_PCI_IOV
5631 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5632 {
5633 int vf;
5634 struct ixgbe_hw *hw = &adapter->hw;
5635 struct net_device *netdev = adapter->netdev;
5636 u32 gpc;
5637 u32 ciaa, ciad;
5638
5639 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5640 if (gpc) /* If incrementing then no need for the check below */
5641 return;
5642 /*
5643 * Check to see if a bad DMA write target from an errant or
5644 * malicious VF has caused a PCIe error. If so then we can
5645 * issue a VFLR to the offending VF(s) and then resume without
5646 * requesting a full slot reset.
5647 */
5648
5649 for (vf = 0; vf < adapter->num_vfs; vf++) {
5650 ciaa = (vf << 16) | 0x80000000;
5651 /* 32 bit read so align, we really want status at offset 6 */
5652 ciaa |= PCI_COMMAND;
5653 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5654 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5655 ciaa &= 0x7FFFFFFF;
5656 /* disable debug mode asap after reading data */
5657 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5658 /* Get the upper 16 bits which will be the PCI status reg */
5659 ciad >>= 16;
5660 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5661 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5662 /* Issue VFLR */
5663 ciaa = (vf << 16) | 0x80000000;
5664 ciaa |= 0xA8;
5665 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5666 ciad = 0x00008000; /* VFLR */
5667 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5668 ciaa &= 0x7FFFFFFF;
5669 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5670 }
5671 }
5672 }
5673
5674 #endif
5675 /**
5676 * ixgbe_service_timer - Timer Call-back
5677 * @data: pointer to adapter cast into an unsigned long
5678 **/
5679 static void ixgbe_service_timer(unsigned long data)
5680 {
5681 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5682 unsigned long next_event_offset;
5683 bool ready = true;
5684
5685 /* poll faster when waiting for link */
5686 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5687 next_event_offset = HZ / 10;
5688 else
5689 next_event_offset = HZ * 2;
5690
5691 #ifdef CONFIG_PCI_IOV
5692 /*
5693 * don't bother with SR-IOV VF DMA hang check if there are
5694 * no VFs or the link is down
5695 */
5696 if (!adapter->num_vfs ||
5697 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5698 goto normal_timer_service;
5699
5700 /* If we have VFs allocated then we must check for DMA hangs */
5701 ixgbe_check_for_bad_vf(adapter);
5702 next_event_offset = HZ / 50;
5703 adapter->timer_event_accumulator++;
5704
5705 if (adapter->timer_event_accumulator >= 100)
5706 adapter->timer_event_accumulator = 0;
5707 else
5708 ready = false;
5709
5710 normal_timer_service:
5711 #endif
5712 /* Reset the timer */
5713 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5714
5715 if (ready)
5716 ixgbe_service_event_schedule(adapter);
5717 }
5718
5719 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5720 {
5721 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5722 return;
5723
5724 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5725
5726 /* If we're already down or resetting, just bail */
5727 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5728 test_bit(__IXGBE_RESETTING, &adapter->state))
5729 return;
5730
5731 ixgbe_dump(adapter);
5732 netdev_err(adapter->netdev, "Reset adapter\n");
5733 adapter->tx_timeout_count++;
5734
5735 ixgbe_reinit_locked(adapter);
5736 }
5737
5738 /**
5739 * ixgbe_service_task - manages and runs subtasks
5740 * @work: pointer to work_struct containing our data
5741 **/
5742 static void ixgbe_service_task(struct work_struct *work)
5743 {
5744 struct ixgbe_adapter *adapter = container_of(work,
5745 struct ixgbe_adapter,
5746 service_task);
5747
5748 ixgbe_reset_subtask(adapter);
5749 ixgbe_sfp_detection_subtask(adapter);
5750 ixgbe_sfp_link_config_subtask(adapter);
5751 ixgbe_check_overtemp_subtask(adapter);
5752 ixgbe_watchdog_subtask(adapter);
5753 ixgbe_fdir_reinit_subtask(adapter);
5754 ixgbe_check_hang_subtask(adapter);
5755 #ifdef CONFIG_IXGBE_PTP
5756 ixgbe_ptp_overflow_check(adapter);
5757 #endif
5758
5759 ixgbe_service_event_complete(adapter);
5760 }
5761
5762 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5763 struct ixgbe_tx_buffer *first,
5764 u8 *hdr_len)
5765 {
5766 struct sk_buff *skb = first->skb;
5767 u32 vlan_macip_lens, type_tucmd;
5768 u32 mss_l4len_idx, l4len;
5769
5770 if (!skb_is_gso(skb))
5771 return 0;
5772
5773 if (skb_header_cloned(skb)) {
5774 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5775 if (err)
5776 return err;
5777 }
5778
5779 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5780 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5781
5782 if (first->protocol == __constant_htons(ETH_P_IP)) {
5783 struct iphdr *iph = ip_hdr(skb);
5784 iph->tot_len = 0;
5785 iph->check = 0;
5786 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5787 iph->daddr, 0,
5788 IPPROTO_TCP,
5789 0);
5790 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5791 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5792 IXGBE_TX_FLAGS_CSUM |
5793 IXGBE_TX_FLAGS_IPV4;
5794 } else if (skb_is_gso_v6(skb)) {
5795 ipv6_hdr(skb)->payload_len = 0;
5796 tcp_hdr(skb)->check =
5797 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5798 &ipv6_hdr(skb)->daddr,
5799 0, IPPROTO_TCP, 0);
5800 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5801 IXGBE_TX_FLAGS_CSUM;
5802 }
5803
5804 /* compute header lengths */
5805 l4len = tcp_hdrlen(skb);
5806 *hdr_len = skb_transport_offset(skb) + l4len;
5807
5808 /* update gso size and bytecount with header size */
5809 first->gso_segs = skb_shinfo(skb)->gso_segs;
5810 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5811
5812 /* mss_l4len_id: use 1 as index for TSO */
5813 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5814 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5815 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5816
5817 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5818 vlan_macip_lens = skb_network_header_len(skb);
5819 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5820 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5821
5822 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
5823 mss_l4len_idx);
5824
5825 return 1;
5826 }
5827
5828 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5829 struct ixgbe_tx_buffer *first)
5830 {
5831 struct sk_buff *skb = first->skb;
5832 u32 vlan_macip_lens = 0;
5833 u32 mss_l4len_idx = 0;
5834 u32 type_tucmd = 0;
5835
5836 if (skb->ip_summed != CHECKSUM_PARTIAL) {
5837 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
5838 !(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5839 return;
5840 } else {
5841 u8 l4_hdr = 0;
5842 switch (first->protocol) {
5843 case __constant_htons(ETH_P_IP):
5844 vlan_macip_lens |= skb_network_header_len(skb);
5845 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5846 l4_hdr = ip_hdr(skb)->protocol;
5847 break;
5848 case __constant_htons(ETH_P_IPV6):
5849 vlan_macip_lens |= skb_network_header_len(skb);
5850 l4_hdr = ipv6_hdr(skb)->nexthdr;
5851 break;
5852 default:
5853 if (unlikely(net_ratelimit())) {
5854 dev_warn(tx_ring->dev,
5855 "partial checksum but proto=%x!\n",
5856 first->protocol);
5857 }
5858 break;
5859 }
5860
5861 switch (l4_hdr) {
5862 case IPPROTO_TCP:
5863 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5864 mss_l4len_idx = tcp_hdrlen(skb) <<
5865 IXGBE_ADVTXD_L4LEN_SHIFT;
5866 break;
5867 case IPPROTO_SCTP:
5868 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5869 mss_l4len_idx = sizeof(struct sctphdr) <<
5870 IXGBE_ADVTXD_L4LEN_SHIFT;
5871 break;
5872 case IPPROTO_UDP:
5873 mss_l4len_idx = sizeof(struct udphdr) <<
5874 IXGBE_ADVTXD_L4LEN_SHIFT;
5875 break;
5876 default:
5877 if (unlikely(net_ratelimit())) {
5878 dev_warn(tx_ring->dev,
5879 "partial checksum but l4 proto=%x!\n",
5880 l4_hdr);
5881 }
5882 break;
5883 }
5884
5885 /* update TX checksum flag */
5886 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
5887 }
5888
5889 /* vlan_macip_lens: MACLEN, VLAN tag */
5890 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5891 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5892
5893 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
5894 type_tucmd, mss_l4len_idx);
5895 }
5896
5897 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
5898 {
5899 /* set type for advanced descriptor with frame checksum insertion */
5900 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
5901 IXGBE_ADVTXD_DCMD_IFCS |
5902 IXGBE_ADVTXD_DCMD_DEXT);
5903
5904 /* set HW vlan bit if vlan is present */
5905 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
5906 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
5907
5908 #ifdef CONFIG_IXGBE_PTP
5909 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP)
5910 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP);
5911 #endif
5912
5913 /* set segmentation enable bits for TSO/FSO */
5914 #ifdef IXGBE_FCOE
5915 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
5916 #else
5917 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5918 #endif
5919 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
5920
5921 return cmd_type;
5922 }
5923
5924 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
5925 u32 tx_flags, unsigned int paylen)
5926 {
5927 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
5928
5929 /* enable L4 checksum for TSO and TX checksum offload */
5930 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5931 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
5932
5933 /* enble IPv4 checksum for TSO */
5934 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5935 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
5936
5937 /* use index 1 context for TSO/FSO/FCOE */
5938 #ifdef IXGBE_FCOE
5939 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
5940 #else
5941 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5942 #endif
5943 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
5944
5945 /*
5946 * Check Context must be set if Tx switch is enabled, which it
5947 * always is for case where virtual functions are running
5948 */
5949 #ifdef IXGBE_FCOE
5950 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
5951 #else
5952 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
5953 #endif
5954 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
5955
5956 tx_desc->read.olinfo_status = olinfo_status;
5957 }
5958
5959 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
5960 IXGBE_TXD_CMD_RS)
5961
5962 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
5963 struct ixgbe_tx_buffer *first,
5964 const u8 hdr_len)
5965 {
5966 dma_addr_t dma;
5967 struct sk_buff *skb = first->skb;
5968 struct ixgbe_tx_buffer *tx_buffer;
5969 union ixgbe_adv_tx_desc *tx_desc;
5970 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
5971 unsigned int data_len = skb->data_len;
5972 unsigned int size = skb_headlen(skb);
5973 unsigned int paylen = skb->len - hdr_len;
5974 u32 tx_flags = first->tx_flags;
5975 __le32 cmd_type;
5976 u16 i = tx_ring->next_to_use;
5977
5978 tx_desc = IXGBE_TX_DESC(tx_ring, i);
5979
5980 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
5981 cmd_type = ixgbe_tx_cmd_type(tx_flags);
5982
5983 #ifdef IXGBE_FCOE
5984 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5985 if (data_len < sizeof(struct fcoe_crc_eof)) {
5986 size -= sizeof(struct fcoe_crc_eof) - data_len;
5987 data_len = 0;
5988 } else {
5989 data_len -= sizeof(struct fcoe_crc_eof);
5990 }
5991 }
5992
5993 #endif
5994 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
5995 if (dma_mapping_error(tx_ring->dev, dma))
5996 goto dma_error;
5997
5998 /* record length, and DMA address */
5999 dma_unmap_len_set(first, len, size);
6000 dma_unmap_addr_set(first, dma, dma);
6001
6002 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6003
6004 for (;;) {
6005 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6006 tx_desc->read.cmd_type_len =
6007 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6008
6009 i++;
6010 tx_desc++;
6011 if (i == tx_ring->count) {
6012 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6013 i = 0;
6014 }
6015
6016 dma += IXGBE_MAX_DATA_PER_TXD;
6017 size -= IXGBE_MAX_DATA_PER_TXD;
6018
6019 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6020 tx_desc->read.olinfo_status = 0;
6021 }
6022
6023 if (likely(!data_len))
6024 break;
6025
6026 if (unlikely(skb->no_fcs))
6027 cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS));
6028 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6029
6030 i++;
6031 tx_desc++;
6032 if (i == tx_ring->count) {
6033 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6034 i = 0;
6035 }
6036
6037 #ifdef IXGBE_FCOE
6038 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6039 #else
6040 size = skb_frag_size(frag);
6041 #endif
6042 data_len -= size;
6043
6044 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6045 DMA_TO_DEVICE);
6046 if (dma_mapping_error(tx_ring->dev, dma))
6047 goto dma_error;
6048
6049 tx_buffer = &tx_ring->tx_buffer_info[i];
6050 dma_unmap_len_set(tx_buffer, len, size);
6051 dma_unmap_addr_set(tx_buffer, dma, dma);
6052
6053 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6054 tx_desc->read.olinfo_status = 0;
6055
6056 frag++;
6057 }
6058
6059 /* write last descriptor with RS and EOP bits */
6060 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6061 tx_desc->read.cmd_type_len = cmd_type;
6062
6063 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6064
6065 /* set the timestamp */
6066 first->time_stamp = jiffies;
6067
6068 /*
6069 * Force memory writes to complete before letting h/w know there
6070 * are new descriptors to fetch. (Only applicable for weak-ordered
6071 * memory model archs, such as IA-64).
6072 *
6073 * We also need this memory barrier to make certain all of the
6074 * status bits have been updated before next_to_watch is written.
6075 */
6076 wmb();
6077
6078 /* set next_to_watch value indicating a packet is present */
6079 first->next_to_watch = tx_desc;
6080
6081 i++;
6082 if (i == tx_ring->count)
6083 i = 0;
6084
6085 tx_ring->next_to_use = i;
6086
6087 /* notify HW of packet */
6088 writel(i, tx_ring->tail);
6089
6090 return;
6091 dma_error:
6092 dev_err(tx_ring->dev, "TX DMA map failed\n");
6093
6094 /* clear dma mappings for failed tx_buffer_info map */
6095 for (;;) {
6096 tx_buffer = &tx_ring->tx_buffer_info[i];
6097 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6098 if (tx_buffer == first)
6099 break;
6100 if (i == 0)
6101 i = tx_ring->count;
6102 i--;
6103 }
6104
6105 tx_ring->next_to_use = i;
6106 }
6107
6108 static void ixgbe_atr(struct ixgbe_ring *ring,
6109 struct ixgbe_tx_buffer *first)
6110 {
6111 struct ixgbe_q_vector *q_vector = ring->q_vector;
6112 union ixgbe_atr_hash_dword input = { .dword = 0 };
6113 union ixgbe_atr_hash_dword common = { .dword = 0 };
6114 union {
6115 unsigned char *network;
6116 struct iphdr *ipv4;
6117 struct ipv6hdr *ipv6;
6118 } hdr;
6119 struct tcphdr *th;
6120 __be16 vlan_id;
6121
6122 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6123 if (!q_vector)
6124 return;
6125
6126 /* do nothing if sampling is disabled */
6127 if (!ring->atr_sample_rate)
6128 return;
6129
6130 ring->atr_count++;
6131
6132 /* snag network header to get L4 type and address */
6133 hdr.network = skb_network_header(first->skb);
6134
6135 /* Currently only IPv4/IPv6 with TCP is supported */
6136 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6137 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6138 (first->protocol != __constant_htons(ETH_P_IP) ||
6139 hdr.ipv4->protocol != IPPROTO_TCP))
6140 return;
6141
6142 th = tcp_hdr(first->skb);
6143
6144 /* skip this packet since it is invalid or the socket is closing */
6145 if (!th || th->fin)
6146 return;
6147
6148 /* sample on all syn packets or once every atr sample count */
6149 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6150 return;
6151
6152 /* reset sample count */
6153 ring->atr_count = 0;
6154
6155 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6156
6157 /*
6158 * src and dst are inverted, think how the receiver sees them
6159 *
6160 * The input is broken into two sections, a non-compressed section
6161 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6162 * is XORed together and stored in the compressed dword.
6163 */
6164 input.formatted.vlan_id = vlan_id;
6165
6166 /*
6167 * since src port and flex bytes occupy the same word XOR them together
6168 * and write the value to source port portion of compressed dword
6169 */
6170 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6171 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6172 else
6173 common.port.src ^= th->dest ^ first->protocol;
6174 common.port.dst ^= th->source;
6175
6176 if (first->protocol == __constant_htons(ETH_P_IP)) {
6177 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6178 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6179 } else {
6180 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6181 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6182 hdr.ipv6->saddr.s6_addr32[1] ^
6183 hdr.ipv6->saddr.s6_addr32[2] ^
6184 hdr.ipv6->saddr.s6_addr32[3] ^
6185 hdr.ipv6->daddr.s6_addr32[0] ^
6186 hdr.ipv6->daddr.s6_addr32[1] ^
6187 hdr.ipv6->daddr.s6_addr32[2] ^
6188 hdr.ipv6->daddr.s6_addr32[3];
6189 }
6190
6191 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6192 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6193 input, common, ring->queue_index);
6194 }
6195
6196 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6197 {
6198 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6199 /* Herbert's original patch had:
6200 * smp_mb__after_netif_stop_queue();
6201 * but since that doesn't exist yet, just open code it. */
6202 smp_mb();
6203
6204 /* We need to check again in a case another CPU has just
6205 * made room available. */
6206 if (likely(ixgbe_desc_unused(tx_ring) < size))
6207 return -EBUSY;
6208
6209 /* A reprieve! - use start_queue because it doesn't call schedule */
6210 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6211 ++tx_ring->tx_stats.restart_queue;
6212 return 0;
6213 }
6214
6215 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6216 {
6217 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6218 return 0;
6219 return __ixgbe_maybe_stop_tx(tx_ring, size);
6220 }
6221
6222 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6223 {
6224 struct ixgbe_adapter *adapter = netdev_priv(dev);
6225 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6226 smp_processor_id();
6227 #ifdef IXGBE_FCOE
6228 __be16 protocol = vlan_get_protocol(skb);
6229
6230 if (((protocol == htons(ETH_P_FCOE)) ||
6231 (protocol == htons(ETH_P_FIP))) &&
6232 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6233 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6234 txq += adapter->ring_feature[RING_F_FCOE].mask;
6235 return txq;
6236 }
6237 #endif
6238
6239 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6240 while (unlikely(txq >= dev->real_num_tx_queues))
6241 txq -= dev->real_num_tx_queues;
6242 return txq;
6243 }
6244
6245 return skb_tx_hash(dev, skb);
6246 }
6247
6248 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6249 struct ixgbe_adapter *adapter,
6250 struct ixgbe_ring *tx_ring)
6251 {
6252 struct ixgbe_tx_buffer *first;
6253 int tso;
6254 u32 tx_flags = 0;
6255 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6256 unsigned short f;
6257 #endif
6258 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6259 __be16 protocol = skb->protocol;
6260 u8 hdr_len = 0;
6261
6262 /*
6263 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6264 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6265 * + 2 desc gap to keep tail from touching head,
6266 * + 1 desc for context descriptor,
6267 * otherwise try next time
6268 */
6269 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6270 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6271 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6272 #else
6273 count += skb_shinfo(skb)->nr_frags;
6274 #endif
6275 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6276 tx_ring->tx_stats.tx_busy++;
6277 return NETDEV_TX_BUSY;
6278 }
6279
6280 /* record the location of the first descriptor for this packet */
6281 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6282 first->skb = skb;
6283 first->bytecount = skb->len;
6284 first->gso_segs = 1;
6285
6286 /* if we have a HW VLAN tag being added default to the HW one */
6287 if (vlan_tx_tag_present(skb)) {
6288 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6289 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6290 /* else if it is a SW VLAN check the next protocol and store the tag */
6291 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6292 struct vlan_hdr *vhdr, _vhdr;
6293 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6294 if (!vhdr)
6295 goto out_drop;
6296
6297 protocol = vhdr->h_vlan_encapsulated_proto;
6298 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6299 IXGBE_TX_FLAGS_VLAN_SHIFT;
6300 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6301 }
6302
6303 skb_tx_timestamp(skb);
6304
6305 #ifdef CONFIG_IXGBE_PTP
6306 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6307 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6308 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6309 }
6310 #endif
6311
6312 #ifdef CONFIG_PCI_IOV
6313 /*
6314 * Use the l2switch_enable flag - would be false if the DMA
6315 * Tx switch had been disabled.
6316 */
6317 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6318 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6319
6320 #endif
6321 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6322 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6323 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6324 (skb->priority != TC_PRIO_CONTROL))) {
6325 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6326 tx_flags |= (skb->priority & 0x7) <<
6327 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6328 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6329 struct vlan_ethhdr *vhdr;
6330 if (skb_header_cloned(skb) &&
6331 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6332 goto out_drop;
6333 vhdr = (struct vlan_ethhdr *)skb->data;
6334 vhdr->h_vlan_TCI = htons(tx_flags >>
6335 IXGBE_TX_FLAGS_VLAN_SHIFT);
6336 } else {
6337 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6338 }
6339 }
6340
6341 /* record initial flags and protocol */
6342 first->tx_flags = tx_flags;
6343 first->protocol = protocol;
6344
6345 #ifdef IXGBE_FCOE
6346 /* setup tx offload for FCoE */
6347 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6348 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6349 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6350 if (tso < 0)
6351 goto out_drop;
6352
6353 goto xmit_fcoe;
6354 }
6355
6356 #endif /* IXGBE_FCOE */
6357 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6358 if (tso < 0)
6359 goto out_drop;
6360 else if (!tso)
6361 ixgbe_tx_csum(tx_ring, first);
6362
6363 /* add the ATR filter if ATR is on */
6364 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6365 ixgbe_atr(tx_ring, first);
6366
6367 #ifdef IXGBE_FCOE
6368 xmit_fcoe:
6369 #endif /* IXGBE_FCOE */
6370 ixgbe_tx_map(tx_ring, first, hdr_len);
6371
6372 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6373
6374 return NETDEV_TX_OK;
6375
6376 out_drop:
6377 dev_kfree_skb_any(first->skb);
6378 first->skb = NULL;
6379
6380 return NETDEV_TX_OK;
6381 }
6382
6383 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6384 struct net_device *netdev)
6385 {
6386 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6387 struct ixgbe_ring *tx_ring;
6388
6389 /*
6390 * The minimum packet size for olinfo paylen is 17 so pad the skb
6391 * in order to meet this minimum size requirement.
6392 */
6393 if (unlikely(skb->len < 17)) {
6394 if (skb_pad(skb, 17 - skb->len))
6395 return NETDEV_TX_OK;
6396 skb->len = 17;
6397 }
6398
6399 tx_ring = adapter->tx_ring[skb->queue_mapping];
6400 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6401 }
6402
6403 /**
6404 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6405 * @netdev: network interface device structure
6406 * @p: pointer to an address structure
6407 *
6408 * Returns 0 on success, negative on failure
6409 **/
6410 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6411 {
6412 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6413 struct ixgbe_hw *hw = &adapter->hw;
6414 struct sockaddr *addr = p;
6415
6416 if (!is_valid_ether_addr(addr->sa_data))
6417 return -EADDRNOTAVAIL;
6418
6419 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6420 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6421
6422 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6423 IXGBE_RAH_AV);
6424
6425 return 0;
6426 }
6427
6428 static int
6429 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6430 {
6431 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6432 struct ixgbe_hw *hw = &adapter->hw;
6433 u16 value;
6434 int rc;
6435
6436 if (prtad != hw->phy.mdio.prtad)
6437 return -EINVAL;
6438 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6439 if (!rc)
6440 rc = value;
6441 return rc;
6442 }
6443
6444 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6445 u16 addr, u16 value)
6446 {
6447 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6448 struct ixgbe_hw *hw = &adapter->hw;
6449
6450 if (prtad != hw->phy.mdio.prtad)
6451 return -EINVAL;
6452 return hw->phy.ops.write_reg(hw, addr, devad, value);
6453 }
6454
6455 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6456 {
6457 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6458
6459 switch (cmd) {
6460 #ifdef CONFIG_IXGBE_PTP
6461 case SIOCSHWTSTAMP:
6462 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6463 #endif
6464 default:
6465 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6466 }
6467 }
6468
6469 /**
6470 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6471 * netdev->dev_addrs
6472 * @netdev: network interface device structure
6473 *
6474 * Returns non-zero on failure
6475 **/
6476 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6477 {
6478 int err = 0;
6479 struct ixgbe_adapter *adapter = netdev_priv(dev);
6480 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6481
6482 if (is_valid_ether_addr(mac->san_addr)) {
6483 rtnl_lock();
6484 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6485 rtnl_unlock();
6486 }
6487 return err;
6488 }
6489
6490 /**
6491 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6492 * netdev->dev_addrs
6493 * @netdev: network interface device structure
6494 *
6495 * Returns non-zero on failure
6496 **/
6497 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6498 {
6499 int err = 0;
6500 struct ixgbe_adapter *adapter = netdev_priv(dev);
6501 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6502
6503 if (is_valid_ether_addr(mac->san_addr)) {
6504 rtnl_lock();
6505 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6506 rtnl_unlock();
6507 }
6508 return err;
6509 }
6510
6511 #ifdef CONFIG_NET_POLL_CONTROLLER
6512 /*
6513 * Polling 'interrupt' - used by things like netconsole to send skbs
6514 * without having to re-enable interrupts. It's not called while
6515 * the interrupt routine is executing.
6516 */
6517 static void ixgbe_netpoll(struct net_device *netdev)
6518 {
6519 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6520 int i;
6521
6522 /* if interface is down do nothing */
6523 if (test_bit(__IXGBE_DOWN, &adapter->state))
6524 return;
6525
6526 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6527 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6528 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6529 for (i = 0; i < num_q_vectors; i++) {
6530 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6531 ixgbe_msix_clean_rings(0, q_vector);
6532 }
6533 } else {
6534 ixgbe_intr(adapter->pdev->irq, netdev);
6535 }
6536 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6537 }
6538
6539 #endif
6540 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6541 struct rtnl_link_stats64 *stats)
6542 {
6543 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6544 int i;
6545
6546 rcu_read_lock();
6547 for (i = 0; i < adapter->num_rx_queues; i++) {
6548 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6549 u64 bytes, packets;
6550 unsigned int start;
6551
6552 if (ring) {
6553 do {
6554 start = u64_stats_fetch_begin_bh(&ring->syncp);
6555 packets = ring->stats.packets;
6556 bytes = ring->stats.bytes;
6557 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6558 stats->rx_packets += packets;
6559 stats->rx_bytes += bytes;
6560 }
6561 }
6562
6563 for (i = 0; i < adapter->num_tx_queues; i++) {
6564 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6565 u64 bytes, packets;
6566 unsigned int start;
6567
6568 if (ring) {
6569 do {
6570 start = u64_stats_fetch_begin_bh(&ring->syncp);
6571 packets = ring->stats.packets;
6572 bytes = ring->stats.bytes;
6573 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6574 stats->tx_packets += packets;
6575 stats->tx_bytes += bytes;
6576 }
6577 }
6578 rcu_read_unlock();
6579 /* following stats updated by ixgbe_watchdog_task() */
6580 stats->multicast = netdev->stats.multicast;
6581 stats->rx_errors = netdev->stats.rx_errors;
6582 stats->rx_length_errors = netdev->stats.rx_length_errors;
6583 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6584 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6585 return stats;
6586 }
6587
6588 #ifdef CONFIG_IXGBE_DCB
6589 /**
6590 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6591 * @adapter: pointer to ixgbe_adapter
6592 * @tc: number of traffic classes currently enabled
6593 *
6594 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6595 * 802.1Q priority maps to a packet buffer that exists.
6596 */
6597 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6598 {
6599 struct ixgbe_hw *hw = &adapter->hw;
6600 u32 reg, rsave;
6601 int i;
6602
6603 /* 82598 have a static priority to TC mapping that can not
6604 * be changed so no validation is needed.
6605 */
6606 if (hw->mac.type == ixgbe_mac_82598EB)
6607 return;
6608
6609 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6610 rsave = reg;
6611
6612 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6613 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6614
6615 /* If up2tc is out of bounds default to zero */
6616 if (up2tc > tc)
6617 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6618 }
6619
6620 if (reg != rsave)
6621 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6622
6623 return;
6624 }
6625
6626 /**
6627 * ixgbe_setup_tc - configure net_device for multiple traffic classes
6628 *
6629 * @netdev: net device to configure
6630 * @tc: number of traffic classes to enable
6631 */
6632 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6633 {
6634 struct ixgbe_adapter *adapter = netdev_priv(dev);
6635 struct ixgbe_hw *hw = &adapter->hw;
6636
6637 /* Multiple traffic classes requires multiple queues */
6638 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6639 e_err(drv, "Enable failed, needs MSI-X\n");
6640 return -EINVAL;
6641 }
6642
6643 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6644 e_err(drv, "Enable failed, SR-IOV enabled\n");
6645 return -EINVAL;
6646 }
6647
6648 /* Hardware supports up to 8 traffic classes */
6649 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
6650 (hw->mac.type == ixgbe_mac_82598EB &&
6651 tc < MAX_TRAFFIC_CLASS))
6652 return -EINVAL;
6653
6654 /* Hardware has to reinitialize queues and interrupts to
6655 * match packet buffer alignment. Unfortunately, the
6656 * hardware is not flexible enough to do this dynamically.
6657 */
6658 if (netif_running(dev))
6659 ixgbe_close(dev);
6660 ixgbe_clear_interrupt_scheme(adapter);
6661
6662 if (tc) {
6663 netdev_set_num_tc(dev, tc);
6664 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6665 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6666
6667 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6668 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
6669 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6670 }
6671 } else {
6672 netdev_reset_tc(dev);
6673 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6674 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6675
6676 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6677 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6678
6679 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6680 adapter->dcb_cfg.pfc_mode_enable = false;
6681 }
6682
6683 ixgbe_init_interrupt_scheme(adapter);
6684 ixgbe_validate_rtr(adapter, tc);
6685 if (netif_running(dev))
6686 ixgbe_open(dev);
6687
6688 return 0;
6689 }
6690
6691 #endif /* CONFIG_IXGBE_DCB */
6692 void ixgbe_do_reset(struct net_device *netdev)
6693 {
6694 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6695
6696 if (netif_running(netdev))
6697 ixgbe_reinit_locked(adapter);
6698 else
6699 ixgbe_reset(adapter);
6700 }
6701
6702 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
6703 netdev_features_t features)
6704 {
6705 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6706
6707 /* return error if RXHASH is being enabled when RSS is not supported */
6708 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
6709 features &= ~NETIF_F_RXHASH;
6710
6711 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6712 if (!(features & NETIF_F_RXCSUM))
6713 features &= ~NETIF_F_LRO;
6714
6715 /* Turn off LRO if not RSC capable */
6716 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6717 features &= ~NETIF_F_LRO;
6718
6719 return features;
6720 }
6721
6722 static int ixgbe_set_features(struct net_device *netdev,
6723 netdev_features_t features)
6724 {
6725 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6726 netdev_features_t changed = netdev->features ^ features;
6727 bool need_reset = false;
6728
6729 /* Make sure RSC matches LRO, reset if change */
6730 if (!(features & NETIF_F_LRO)) {
6731 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6732 need_reset = true;
6733 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6734 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6735 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6736 if (adapter->rx_itr_setting == 1 ||
6737 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6738 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6739 need_reset = true;
6740 } else if ((changed ^ features) & NETIF_F_LRO) {
6741 e_info(probe, "rx-usecs set too low, "
6742 "disabling RSC\n");
6743 }
6744 }
6745
6746 /*
6747 * Check if Flow Director n-tuple support was enabled or disabled. If
6748 * the state changed, we need to reset.
6749 */
6750 if (!(features & NETIF_F_NTUPLE)) {
6751 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
6752 /* turn off Flow Director, set ATR and reset */
6753 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
6754 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
6755 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6756 need_reset = true;
6757 }
6758 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6759 } else if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
6760 /* turn off ATR, enable perfect filters and reset */
6761 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6762 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6763 need_reset = true;
6764 }
6765
6766 if (features & NETIF_F_HW_VLAN_RX)
6767 ixgbe_vlan_strip_enable(adapter);
6768 else
6769 ixgbe_vlan_strip_disable(adapter);
6770
6771 if (changed & NETIF_F_RXALL)
6772 need_reset = true;
6773
6774 netdev->features = features;
6775 if (need_reset)
6776 ixgbe_do_reset(netdev);
6777
6778 return 0;
6779 }
6780
6781 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm,
6782 struct net_device *dev,
6783 unsigned char *addr,
6784 u16 flags)
6785 {
6786 struct ixgbe_adapter *adapter = netdev_priv(dev);
6787 int err = -EOPNOTSUPP;
6788
6789 if (ndm->ndm_state & NUD_PERMANENT) {
6790 pr_info("%s: FDB only supports static addresses\n",
6791 ixgbe_driver_name);
6792 return -EINVAL;
6793 }
6794
6795 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6796 if (is_unicast_ether_addr(addr))
6797 err = dev_uc_add_excl(dev, addr);
6798 else if (is_multicast_ether_addr(addr))
6799 err = dev_mc_add_excl(dev, addr);
6800 else
6801 err = -EINVAL;
6802 }
6803
6804 /* Only return duplicate errors if NLM_F_EXCL is set */
6805 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6806 err = 0;
6807
6808 return err;
6809 }
6810
6811 static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
6812 struct net_device *dev,
6813 unsigned char *addr)
6814 {
6815 struct ixgbe_adapter *adapter = netdev_priv(dev);
6816 int err = -EOPNOTSUPP;
6817
6818 if (ndm->ndm_state & NUD_PERMANENT) {
6819 pr_info("%s: FDB only supports static addresses\n",
6820 ixgbe_driver_name);
6821 return -EINVAL;
6822 }
6823
6824 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6825 if (is_unicast_ether_addr(addr))
6826 err = dev_uc_del(dev, addr);
6827 else if (is_multicast_ether_addr(addr))
6828 err = dev_mc_del(dev, addr);
6829 else
6830 err = -EINVAL;
6831 }
6832
6833 return err;
6834 }
6835
6836 static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
6837 struct netlink_callback *cb,
6838 struct net_device *dev,
6839 int idx)
6840 {
6841 struct ixgbe_adapter *adapter = netdev_priv(dev);
6842
6843 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6844 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
6845
6846 return idx;
6847 }
6848
6849 static const struct net_device_ops ixgbe_netdev_ops = {
6850 .ndo_open = ixgbe_open,
6851 .ndo_stop = ixgbe_close,
6852 .ndo_start_xmit = ixgbe_xmit_frame,
6853 .ndo_select_queue = ixgbe_select_queue,
6854 .ndo_set_rx_mode = ixgbe_set_rx_mode,
6855 .ndo_validate_addr = eth_validate_addr,
6856 .ndo_set_mac_address = ixgbe_set_mac,
6857 .ndo_change_mtu = ixgbe_change_mtu,
6858 .ndo_tx_timeout = ixgbe_tx_timeout,
6859 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6860 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6861 .ndo_do_ioctl = ixgbe_ioctl,
6862 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6863 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6864 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6865 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
6866 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
6867 .ndo_get_stats64 = ixgbe_get_stats64,
6868 #ifdef CONFIG_IXGBE_DCB
6869 .ndo_setup_tc = ixgbe_setup_tc,
6870 #endif
6871 #ifdef CONFIG_NET_POLL_CONTROLLER
6872 .ndo_poll_controller = ixgbe_netpoll,
6873 #endif
6874 #ifdef IXGBE_FCOE
6875 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6876 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
6877 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6878 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6879 .ndo_fcoe_disable = ixgbe_fcoe_disable,
6880 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6881 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
6882 #endif /* IXGBE_FCOE */
6883 .ndo_set_features = ixgbe_set_features,
6884 .ndo_fix_features = ixgbe_fix_features,
6885 .ndo_fdb_add = ixgbe_ndo_fdb_add,
6886 .ndo_fdb_del = ixgbe_ndo_fdb_del,
6887 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
6888 };
6889
6890 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6891 const struct ixgbe_info *ii)
6892 {
6893 #ifdef CONFIG_PCI_IOV
6894 struct ixgbe_hw *hw = &adapter->hw;
6895
6896 if (hw->mac.type == ixgbe_mac_82598EB)
6897 return;
6898
6899 /* The 82599 supports up to 64 VFs per physical function
6900 * but this implementation limits allocation to 63 so that
6901 * basic networking resources are still available to the
6902 * physical function. If the user requests greater thn
6903 * 63 VFs then it is an error - reset to default of zero.
6904 */
6905 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
6906 ixgbe_enable_sriov(adapter, ii);
6907 #endif /* CONFIG_PCI_IOV */
6908 }
6909
6910 /**
6911 * ixgbe_wol_supported - Check whether device supports WoL
6912 * @hw: hw specific details
6913 * @device_id: the device ID
6914 * @subdev_id: the subsystem device ID
6915 *
6916 * This function is used by probe and ethtool to determine
6917 * which devices have WoL support
6918 *
6919 **/
6920 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
6921 u16 subdevice_id)
6922 {
6923 struct ixgbe_hw *hw = &adapter->hw;
6924 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
6925 int is_wol_supported = 0;
6926
6927 switch (device_id) {
6928 case IXGBE_DEV_ID_82599_SFP:
6929 /* Only these subdevices could supports WOL */
6930 switch (subdevice_id) {
6931 case IXGBE_SUBDEV_ID_82599_560FLR:
6932 /* only support first port */
6933 if (hw->bus.func != 0)
6934 break;
6935 case IXGBE_SUBDEV_ID_82599_SFP:
6936 is_wol_supported = 1;
6937 break;
6938 }
6939 break;
6940 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
6941 /* All except this subdevice support WOL */
6942 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
6943 is_wol_supported = 1;
6944 break;
6945 case IXGBE_DEV_ID_82599_KX4:
6946 is_wol_supported = 1;
6947 break;
6948 case IXGBE_DEV_ID_X540T:
6949 /* check eeprom to see if enabled wol */
6950 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
6951 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
6952 (hw->bus.func == 0))) {
6953 is_wol_supported = 1;
6954 }
6955 break;
6956 }
6957
6958 return is_wol_supported;
6959 }
6960
6961 /**
6962 * ixgbe_probe - Device Initialization Routine
6963 * @pdev: PCI device information struct
6964 * @ent: entry in ixgbe_pci_tbl
6965 *
6966 * Returns 0 on success, negative on failure
6967 *
6968 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6969 * The OS initialization, configuring of the adapter private structure,
6970 * and a hardware reset occur.
6971 **/
6972 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6973 const struct pci_device_id *ent)
6974 {
6975 struct net_device *netdev;
6976 struct ixgbe_adapter *adapter = NULL;
6977 struct ixgbe_hw *hw;
6978 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6979 static int cards_found;
6980 int i, err, pci_using_dac;
6981 u8 part_str[IXGBE_PBANUM_LENGTH];
6982 unsigned int indices = num_possible_cpus();
6983 #ifdef IXGBE_FCOE
6984 u16 device_caps;
6985 #endif
6986 u32 eec;
6987
6988 /* Catch broken hardware that put the wrong VF device ID in
6989 * the PCIe SR-IOV capability.
6990 */
6991 if (pdev->is_virtfn) {
6992 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6993 pci_name(pdev), pdev->vendor, pdev->device);
6994 return -EINVAL;
6995 }
6996
6997 err = pci_enable_device_mem(pdev);
6998 if (err)
6999 return err;
7000
7001 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7002 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7003 pci_using_dac = 1;
7004 } else {
7005 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7006 if (err) {
7007 err = dma_set_coherent_mask(&pdev->dev,
7008 DMA_BIT_MASK(32));
7009 if (err) {
7010 dev_err(&pdev->dev,
7011 "No usable DMA configuration, aborting\n");
7012 goto err_dma;
7013 }
7014 }
7015 pci_using_dac = 0;
7016 }
7017
7018 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7019 IORESOURCE_MEM), ixgbe_driver_name);
7020 if (err) {
7021 dev_err(&pdev->dev,
7022 "pci_request_selected_regions failed 0x%x\n", err);
7023 goto err_pci_reg;
7024 }
7025
7026 pci_enable_pcie_error_reporting(pdev);
7027
7028 pci_set_master(pdev);
7029 pci_save_state(pdev);
7030
7031 #ifdef CONFIG_IXGBE_DCB
7032 indices *= MAX_TRAFFIC_CLASS;
7033 #endif
7034
7035 if (ii->mac == ixgbe_mac_82598EB)
7036 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7037 else
7038 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7039
7040 #ifdef IXGBE_FCOE
7041 indices += min_t(unsigned int, num_possible_cpus(),
7042 IXGBE_MAX_FCOE_INDICES);
7043 #endif
7044 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7045 if (!netdev) {
7046 err = -ENOMEM;
7047 goto err_alloc_etherdev;
7048 }
7049
7050 SET_NETDEV_DEV(netdev, &pdev->dev);
7051
7052 adapter = netdev_priv(netdev);
7053 pci_set_drvdata(pdev, adapter);
7054
7055 adapter->netdev = netdev;
7056 adapter->pdev = pdev;
7057 hw = &adapter->hw;
7058 hw->back = adapter;
7059 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7060
7061 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7062 pci_resource_len(pdev, 0));
7063 if (!hw->hw_addr) {
7064 err = -EIO;
7065 goto err_ioremap;
7066 }
7067
7068 for (i = 1; i <= 5; i++) {
7069 if (pci_resource_len(pdev, i) == 0)
7070 continue;
7071 }
7072
7073 netdev->netdev_ops = &ixgbe_netdev_ops;
7074 ixgbe_set_ethtool_ops(netdev);
7075 netdev->watchdog_timeo = 5 * HZ;
7076 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7077
7078 adapter->bd_number = cards_found;
7079
7080 /* Setup hw api */
7081 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7082 hw->mac.type = ii->mac;
7083
7084 /* EEPROM */
7085 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7086 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7087 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7088 if (!(eec & (1 << 8)))
7089 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7090
7091 /* PHY */
7092 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7093 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7094 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7095 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7096 hw->phy.mdio.mmds = 0;
7097 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7098 hw->phy.mdio.dev = netdev;
7099 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7100 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7101
7102 ii->get_invariants(hw);
7103
7104 /* setup the private structure */
7105 err = ixgbe_sw_init(adapter);
7106 if (err)
7107 goto err_sw_init;
7108
7109 /* Make it possible the adapter to be woken up via WOL */
7110 switch (adapter->hw.mac.type) {
7111 case ixgbe_mac_82599EB:
7112 case ixgbe_mac_X540:
7113 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7114 break;
7115 default:
7116 break;
7117 }
7118
7119 /*
7120 * If there is a fan on this device and it has failed log the
7121 * failure.
7122 */
7123 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7124 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7125 if (esdp & IXGBE_ESDP_SDP1)
7126 e_crit(probe, "Fan has stopped, replace the adapter\n");
7127 }
7128
7129 if (allow_unsupported_sfp)
7130 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7131
7132 /* reset_hw fills in the perm_addr as well */
7133 hw->phy.reset_if_overtemp = true;
7134 err = hw->mac.ops.reset_hw(hw);
7135 hw->phy.reset_if_overtemp = false;
7136 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7137 hw->mac.type == ixgbe_mac_82598EB) {
7138 err = 0;
7139 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7140 e_dev_err("failed to load because an unsupported SFP+ "
7141 "module type was detected.\n");
7142 e_dev_err("Reload the driver after installing a supported "
7143 "module.\n");
7144 goto err_sw_init;
7145 } else if (err) {
7146 e_dev_err("HW Init failed: %d\n", err);
7147 goto err_sw_init;
7148 }
7149
7150 ixgbe_probe_vf(adapter, ii);
7151
7152 netdev->features = NETIF_F_SG |
7153 NETIF_F_IP_CSUM |
7154 NETIF_F_IPV6_CSUM |
7155 NETIF_F_HW_VLAN_TX |
7156 NETIF_F_HW_VLAN_RX |
7157 NETIF_F_HW_VLAN_FILTER |
7158 NETIF_F_TSO |
7159 NETIF_F_TSO6 |
7160 NETIF_F_RXHASH |
7161 NETIF_F_RXCSUM;
7162
7163 netdev->hw_features = netdev->features;
7164
7165 switch (adapter->hw.mac.type) {
7166 case ixgbe_mac_82599EB:
7167 case ixgbe_mac_X540:
7168 netdev->features |= NETIF_F_SCTP_CSUM;
7169 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7170 NETIF_F_NTUPLE;
7171 break;
7172 default:
7173 break;
7174 }
7175
7176 netdev->hw_features |= NETIF_F_RXALL;
7177
7178 netdev->vlan_features |= NETIF_F_TSO;
7179 netdev->vlan_features |= NETIF_F_TSO6;
7180 netdev->vlan_features |= NETIF_F_IP_CSUM;
7181 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7182 netdev->vlan_features |= NETIF_F_SG;
7183
7184 netdev->priv_flags |= IFF_UNICAST_FLT;
7185 netdev->priv_flags |= IFF_SUPP_NOFCS;
7186
7187 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7188 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7189 IXGBE_FLAG_DCB_ENABLED);
7190
7191 #ifdef CONFIG_IXGBE_DCB
7192 netdev->dcbnl_ops = &dcbnl_ops;
7193 #endif
7194
7195 #ifdef IXGBE_FCOE
7196 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7197 if (hw->mac.ops.get_device_caps) {
7198 hw->mac.ops.get_device_caps(hw, &device_caps);
7199 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7200 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7201 }
7202 }
7203 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7204 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7205 netdev->vlan_features |= NETIF_F_FSO;
7206 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7207 }
7208 #endif /* IXGBE_FCOE */
7209 if (pci_using_dac) {
7210 netdev->features |= NETIF_F_HIGHDMA;
7211 netdev->vlan_features |= NETIF_F_HIGHDMA;
7212 }
7213
7214 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7215 netdev->hw_features |= NETIF_F_LRO;
7216 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7217 netdev->features |= NETIF_F_LRO;
7218
7219 /* make sure the EEPROM is good */
7220 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7221 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7222 err = -EIO;
7223 goto err_sw_init;
7224 }
7225
7226 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7227 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7228
7229 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7230 e_dev_err("invalid MAC address\n");
7231 err = -EIO;
7232 goto err_sw_init;
7233 }
7234
7235 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7236 (unsigned long) adapter);
7237
7238 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7239 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7240
7241 err = ixgbe_init_interrupt_scheme(adapter);
7242 if (err)
7243 goto err_sw_init;
7244
7245 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7246 netdev->hw_features &= ~NETIF_F_RXHASH;
7247 netdev->features &= ~NETIF_F_RXHASH;
7248 }
7249
7250 /* WOL not supported for all devices */
7251 adapter->wol = 0;
7252 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7253 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
7254 adapter->wol = IXGBE_WUFC_MAG;
7255
7256 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7257
7258 #ifdef CONFIG_IXGBE_PTP
7259 ixgbe_ptp_init(adapter);
7260 #endif /* CONFIG_IXGBE_PTP*/
7261
7262 /* save off EEPROM version number */
7263 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7264 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7265
7266 /* pick up the PCI bus settings for reporting later */
7267 hw->mac.ops.get_bus_info(hw);
7268
7269 /* print bus type/speed/width info */
7270 e_dev_info("(PCI Express:%s:%s) %pM\n",
7271 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7272 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7273 "Unknown"),
7274 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7275 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7276 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7277 "Unknown"),
7278 netdev->dev_addr);
7279
7280 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7281 if (err)
7282 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7283 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7284 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7285 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7286 part_str);
7287 else
7288 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7289 hw->mac.type, hw->phy.type, part_str);
7290
7291 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7292 e_dev_warn("PCI-Express bandwidth available for this card is "
7293 "not sufficient for optimal performance.\n");
7294 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7295 "is required.\n");
7296 }
7297
7298 /* reset the hardware with the new settings */
7299 err = hw->mac.ops.start_hw(hw);
7300 if (err == IXGBE_ERR_EEPROM_VERSION) {
7301 /* We are running on a pre-production device, log a warning */
7302 e_dev_warn("This device is a pre-production adapter/LOM. "
7303 "Please be aware there may be issues associated "
7304 "with your hardware. If you are experiencing "
7305 "problems please contact your Intel or hardware "
7306 "representative who provided you with this "
7307 "hardware.\n");
7308 }
7309 strcpy(netdev->name, "eth%d");
7310 err = register_netdev(netdev);
7311 if (err)
7312 goto err_register;
7313
7314 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7315 if (hw->mac.ops.disable_tx_laser &&
7316 ((hw->phy.multispeed_fiber) ||
7317 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7318 (hw->mac.type == ixgbe_mac_82599EB))))
7319 hw->mac.ops.disable_tx_laser(hw);
7320
7321 /* carrier off reporting is important to ethtool even BEFORE open */
7322 netif_carrier_off(netdev);
7323
7324 #ifdef CONFIG_IXGBE_DCA
7325 if (dca_add_requester(&pdev->dev) == 0) {
7326 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7327 ixgbe_setup_dca(adapter);
7328 }
7329 #endif
7330 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7331 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7332 for (i = 0; i < adapter->num_vfs; i++)
7333 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7334 }
7335
7336 /* firmware requires driver version to be 0xFFFFFFFF
7337 * since os does not support feature
7338 */
7339 if (hw->mac.ops.set_fw_drv_ver)
7340 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7341 0xFF);
7342
7343 /* add san mac addr to netdev */
7344 ixgbe_add_sanmac_netdev(netdev);
7345
7346 e_dev_info("%s\n", ixgbe_default_device_descr);
7347 cards_found++;
7348
7349 #ifdef CONFIG_IXGBE_HWMON
7350 if (ixgbe_sysfs_init(adapter))
7351 e_err(probe, "failed to allocate sysfs resources\n");
7352 #endif /* CONFIG_IXGBE_HWMON */
7353
7354 return 0;
7355
7356 err_register:
7357 ixgbe_release_hw_control(adapter);
7358 ixgbe_clear_interrupt_scheme(adapter);
7359 err_sw_init:
7360 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7361 ixgbe_disable_sriov(adapter);
7362 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7363 iounmap(hw->hw_addr);
7364 err_ioremap:
7365 free_netdev(netdev);
7366 err_alloc_etherdev:
7367 pci_release_selected_regions(pdev,
7368 pci_select_bars(pdev, IORESOURCE_MEM));
7369 err_pci_reg:
7370 err_dma:
7371 pci_disable_device(pdev);
7372 return err;
7373 }
7374
7375 /**
7376 * ixgbe_remove - Device Removal Routine
7377 * @pdev: PCI device information struct
7378 *
7379 * ixgbe_remove is called by the PCI subsystem to alert the driver
7380 * that it should release a PCI device. The could be caused by a
7381 * Hot-Plug event, or because the driver is going to be removed from
7382 * memory.
7383 **/
7384 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7385 {
7386 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7387 struct net_device *netdev = adapter->netdev;
7388
7389 set_bit(__IXGBE_DOWN, &adapter->state);
7390 cancel_work_sync(&adapter->service_task);
7391
7392 #ifdef CONFIG_IXGBE_PTP
7393 ixgbe_ptp_stop(adapter);
7394 #endif
7395
7396 #ifdef CONFIG_IXGBE_DCA
7397 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7398 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7399 dca_remove_requester(&pdev->dev);
7400 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7401 }
7402
7403 #endif
7404 #ifdef CONFIG_IXGBE_HWMON
7405 ixgbe_sysfs_exit(adapter);
7406 #endif /* CONFIG_IXGBE_HWMON */
7407
7408 #ifdef IXGBE_FCOE
7409 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7410 ixgbe_cleanup_fcoe(adapter);
7411
7412 #endif /* IXGBE_FCOE */
7413
7414 /* remove the added san mac */
7415 ixgbe_del_sanmac_netdev(netdev);
7416
7417 if (netdev->reg_state == NETREG_REGISTERED)
7418 unregister_netdev(netdev);
7419
7420 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7421 if (!(ixgbe_check_vf_assignment(adapter)))
7422 ixgbe_disable_sriov(adapter);
7423 else
7424 e_dev_warn("Unloading driver while VFs are assigned "
7425 "- VFs will not be deallocated\n");
7426 }
7427
7428 ixgbe_clear_interrupt_scheme(adapter);
7429
7430 ixgbe_release_hw_control(adapter);
7431
7432 #ifdef CONFIG_DCB
7433 kfree(adapter->ixgbe_ieee_pfc);
7434 kfree(adapter->ixgbe_ieee_ets);
7435
7436 #endif
7437 iounmap(adapter->hw.hw_addr);
7438 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7439 IORESOURCE_MEM));
7440
7441 e_dev_info("complete\n");
7442
7443 free_netdev(netdev);
7444
7445 pci_disable_pcie_error_reporting(pdev);
7446
7447 pci_disable_device(pdev);
7448 }
7449
7450 /**
7451 * ixgbe_io_error_detected - called when PCI error is detected
7452 * @pdev: Pointer to PCI device
7453 * @state: The current pci connection state
7454 *
7455 * This function is called after a PCI bus error affecting
7456 * this device has been detected.
7457 */
7458 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7459 pci_channel_state_t state)
7460 {
7461 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7462 struct net_device *netdev = adapter->netdev;
7463
7464 #ifdef CONFIG_PCI_IOV
7465 struct pci_dev *bdev, *vfdev;
7466 u32 dw0, dw1, dw2, dw3;
7467 int vf, pos;
7468 u16 req_id, pf_func;
7469
7470 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7471 adapter->num_vfs == 0)
7472 goto skip_bad_vf_detection;
7473
7474 bdev = pdev->bus->self;
7475 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7476 bdev = bdev->bus->self;
7477
7478 if (!bdev)
7479 goto skip_bad_vf_detection;
7480
7481 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7482 if (!pos)
7483 goto skip_bad_vf_detection;
7484
7485 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7486 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7487 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7488 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7489
7490 req_id = dw1 >> 16;
7491 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7492 if (!(req_id & 0x0080))
7493 goto skip_bad_vf_detection;
7494
7495 pf_func = req_id & 0x01;
7496 if ((pf_func & 1) == (pdev->devfn & 1)) {
7497 unsigned int device_id;
7498
7499 vf = (req_id & 0x7F) >> 1;
7500 e_dev_err("VF %d has caused a PCIe error\n", vf);
7501 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7502 "%8.8x\tdw3: %8.8x\n",
7503 dw0, dw1, dw2, dw3);
7504 switch (adapter->hw.mac.type) {
7505 case ixgbe_mac_82599EB:
7506 device_id = IXGBE_82599_VF_DEVICE_ID;
7507 break;
7508 case ixgbe_mac_X540:
7509 device_id = IXGBE_X540_VF_DEVICE_ID;
7510 break;
7511 default:
7512 device_id = 0;
7513 break;
7514 }
7515
7516 /* Find the pci device of the offending VF */
7517 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
7518 while (vfdev) {
7519 if (vfdev->devfn == (req_id & 0xFF))
7520 break;
7521 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
7522 device_id, vfdev);
7523 }
7524 /*
7525 * There's a slim chance the VF could have been hot plugged,
7526 * so if it is no longer present we don't need to issue the
7527 * VFLR. Just clean up the AER in that case.
7528 */
7529 if (vfdev) {
7530 e_dev_err("Issuing VFLR to VF %d\n", vf);
7531 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7532 }
7533
7534 pci_cleanup_aer_uncorrect_error_status(pdev);
7535 }
7536
7537 /*
7538 * Even though the error may have occurred on the other port
7539 * we still need to increment the vf error reference count for
7540 * both ports because the I/O resume function will be called
7541 * for both of them.
7542 */
7543 adapter->vferr_refcount++;
7544
7545 return PCI_ERS_RESULT_RECOVERED;
7546
7547 skip_bad_vf_detection:
7548 #endif /* CONFIG_PCI_IOV */
7549 netif_device_detach(netdev);
7550
7551 if (state == pci_channel_io_perm_failure)
7552 return PCI_ERS_RESULT_DISCONNECT;
7553
7554 if (netif_running(netdev))
7555 ixgbe_down(adapter);
7556 pci_disable_device(pdev);
7557
7558 /* Request a slot reset. */
7559 return PCI_ERS_RESULT_NEED_RESET;
7560 }
7561
7562 /**
7563 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7564 * @pdev: Pointer to PCI device
7565 *
7566 * Restart the card from scratch, as if from a cold-boot.
7567 */
7568 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7569 {
7570 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7571 pci_ers_result_t result;
7572 int err;
7573
7574 if (pci_enable_device_mem(pdev)) {
7575 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7576 result = PCI_ERS_RESULT_DISCONNECT;
7577 } else {
7578 pci_set_master(pdev);
7579 pci_restore_state(pdev);
7580 pci_save_state(pdev);
7581
7582 pci_wake_from_d3(pdev, false);
7583
7584 ixgbe_reset(adapter);
7585 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7586 result = PCI_ERS_RESULT_RECOVERED;
7587 }
7588
7589 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7590 if (err) {
7591 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7592 "failed 0x%0x\n", err);
7593 /* non-fatal, continue */
7594 }
7595
7596 return result;
7597 }
7598
7599 /**
7600 * ixgbe_io_resume - called when traffic can start flowing again.
7601 * @pdev: Pointer to PCI device
7602 *
7603 * This callback is called when the error recovery driver tells us that
7604 * its OK to resume normal operation.
7605 */
7606 static void ixgbe_io_resume(struct pci_dev *pdev)
7607 {
7608 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7609 struct net_device *netdev = adapter->netdev;
7610
7611 #ifdef CONFIG_PCI_IOV
7612 if (adapter->vferr_refcount) {
7613 e_info(drv, "Resuming after VF err\n");
7614 adapter->vferr_refcount--;
7615 return;
7616 }
7617
7618 #endif
7619 if (netif_running(netdev))
7620 ixgbe_up(adapter);
7621
7622 netif_device_attach(netdev);
7623 }
7624
7625 static struct pci_error_handlers ixgbe_err_handler = {
7626 .error_detected = ixgbe_io_error_detected,
7627 .slot_reset = ixgbe_io_slot_reset,
7628 .resume = ixgbe_io_resume,
7629 };
7630
7631 static struct pci_driver ixgbe_driver = {
7632 .name = ixgbe_driver_name,
7633 .id_table = ixgbe_pci_tbl,
7634 .probe = ixgbe_probe,
7635 .remove = __devexit_p(ixgbe_remove),
7636 #ifdef CONFIG_PM
7637 .suspend = ixgbe_suspend,
7638 .resume = ixgbe_resume,
7639 #endif
7640 .shutdown = ixgbe_shutdown,
7641 .err_handler = &ixgbe_err_handler
7642 };
7643
7644 /**
7645 * ixgbe_init_module - Driver Registration Routine
7646 *
7647 * ixgbe_init_module is the first routine called when the driver is
7648 * loaded. All it does is register with the PCI subsystem.
7649 **/
7650 static int __init ixgbe_init_module(void)
7651 {
7652 int ret;
7653 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7654 pr_info("%s\n", ixgbe_copyright);
7655
7656 #ifdef CONFIG_IXGBE_DCA
7657 dca_register_notify(&dca_notifier);
7658 #endif
7659
7660 ret = pci_register_driver(&ixgbe_driver);
7661 return ret;
7662 }
7663
7664 module_init(ixgbe_init_module);
7665
7666 /**
7667 * ixgbe_exit_module - Driver Exit Cleanup Routine
7668 *
7669 * ixgbe_exit_module is called just before the driver is removed
7670 * from memory.
7671 **/
7672 static void __exit ixgbe_exit_module(void)
7673 {
7674 #ifdef CONFIG_IXGBE_DCA
7675 dca_unregister_notify(&dca_notifier);
7676 #endif
7677 pci_unregister_driver(&ixgbe_driver);
7678 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7679 }
7680
7681 #ifdef CONFIG_IXGBE_DCA
7682 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7683 void *p)
7684 {
7685 int ret_val;
7686
7687 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7688 __ixgbe_notify_dca);
7689
7690 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7691 }
7692
7693 #endif /* CONFIG_IXGBE_DCA */
7694
7695 module_exit(ixgbe_exit_module);
7696
7697 /* ixgbe_main.c */
Linux kernel - Deliverables
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