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ixgbe: Do not pad FCoE frames as this can cause issues with FCoE DDP
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/prefetch.h>
48 #include <scsi/fc/fc_fcoe.h>
49
50 #include "ixgbe.h"
51 #include "ixgbe_common.h"
52 #include "ixgbe_dcb_82599.h"
53 #include "ixgbe_sriov.h"
54
55 char ixgbe_driver_name[] = "ixgbe";
56 static const char ixgbe_driver_string[] =
57 "Intel(R) 10 Gigabit PCI Express Network Driver";
58 #ifdef IXGBE_FCOE
59 char ixgbe_default_device_descr[] =
60 "Intel(R) 10 Gigabit Network Connection";
61 #else
62 static char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
64 #endif
65 #define MAJ 3
66 #define MIN 9
67 #define BUILD 15
68 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
69 __stringify(BUILD) "-k"
70 const char ixgbe_driver_version[] = DRV_VERSION;
71 static const char ixgbe_copyright[] =
72 "Copyright (c) 1999-2012 Intel Corporation.";
73
74 static const struct ixgbe_info *ixgbe_info_tbl[] = {
75 [board_82598] = &ixgbe_82598_info,
76 [board_82599] = &ixgbe_82599_info,
77 [board_X540] = &ixgbe_X540_info,
78 };
79
80 /* ixgbe_pci_tbl - PCI Device ID Table
81 *
82 * Wildcard entries (PCI_ANY_ID) should come last
83 * Last entry must be all 0s
84 *
85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
86 * Class, Class Mask, private data (not used) }
87 */
88 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
117 /* required last entry */
118 {0, }
119 };
120 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121
122 #ifdef CONFIG_IXGBE_DCA
123 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
124 void *p);
125 static struct notifier_block dca_notifier = {
126 .notifier_call = ixgbe_notify_dca,
127 .next = NULL,
128 .priority = 0
129 };
130 #endif
131
132 #ifdef CONFIG_PCI_IOV
133 static unsigned int max_vfs;
134 module_param(max_vfs, uint, 0);
135 MODULE_PARM_DESC(max_vfs,
136 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
137 #endif /* CONFIG_PCI_IOV */
138
139 static unsigned int allow_unsupported_sfp;
140 module_param(allow_unsupported_sfp, uint, 0);
141 MODULE_PARM_DESC(allow_unsupported_sfp,
142 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
143
144 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
145 static int debug = -1;
146 module_param(debug, int, 0);
147 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
148
149 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
150 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
151 MODULE_LICENSE("GPL");
152 MODULE_VERSION(DRV_VERSION);
153
154 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
155 {
156 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
157 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
158 schedule_work(&adapter->service_task);
159 }
160
161 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
162 {
163 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
164
165 /* flush memory to make sure state is correct before next watchdog */
166 smp_mb__before_clear_bit();
167 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
168 }
169
170 struct ixgbe_reg_info {
171 u32 ofs;
172 char *name;
173 };
174
175 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
176
177 /* General Registers */
178 {IXGBE_CTRL, "CTRL"},
179 {IXGBE_STATUS, "STATUS"},
180 {IXGBE_CTRL_EXT, "CTRL_EXT"},
181
182 /* Interrupt Registers */
183 {IXGBE_EICR, "EICR"},
184
185 /* RX Registers */
186 {IXGBE_SRRCTL(0), "SRRCTL"},
187 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
188 {IXGBE_RDLEN(0), "RDLEN"},
189 {IXGBE_RDH(0), "RDH"},
190 {IXGBE_RDT(0), "RDT"},
191 {IXGBE_RXDCTL(0), "RXDCTL"},
192 {IXGBE_RDBAL(0), "RDBAL"},
193 {IXGBE_RDBAH(0), "RDBAH"},
194
195 /* TX Registers */
196 {IXGBE_TDBAL(0), "TDBAL"},
197 {IXGBE_TDBAH(0), "TDBAH"},
198 {IXGBE_TDLEN(0), "TDLEN"},
199 {IXGBE_TDH(0), "TDH"},
200 {IXGBE_TDT(0), "TDT"},
201 {IXGBE_TXDCTL(0), "TXDCTL"},
202
203 /* List Terminator */
204 {}
205 };
206
207
208 /*
209 * ixgbe_regdump - register printout routine
210 */
211 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
212 {
213 int i = 0, j = 0;
214 char rname[16];
215 u32 regs[64];
216
217 switch (reginfo->ofs) {
218 case IXGBE_SRRCTL(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
221 break;
222 case IXGBE_DCA_RXCTRL(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
225 break;
226 case IXGBE_RDLEN(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
229 break;
230 case IXGBE_RDH(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
233 break;
234 case IXGBE_RDT(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
237 break;
238 case IXGBE_RXDCTL(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
241 break;
242 case IXGBE_RDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
245 break;
246 case IXGBE_RDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
249 break;
250 case IXGBE_TDBAL(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
253 break;
254 case IXGBE_TDBAH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
257 break;
258 case IXGBE_TDLEN(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
261 break;
262 case IXGBE_TDH(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
265 break;
266 case IXGBE_TDT(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
269 break;
270 case IXGBE_TXDCTL(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
273 break;
274 default:
275 pr_info("%-15s %08x\n", reginfo->name,
276 IXGBE_READ_REG(hw, reginfo->ofs));
277 return;
278 }
279
280 for (i = 0; i < 8; i++) {
281 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
282 pr_err("%-15s", rname);
283 for (j = 0; j < 8; j++)
284 pr_cont(" %08x", regs[i*8+j]);
285 pr_cont("\n");
286 }
287
288 }
289
290 /*
291 * ixgbe_dump - Print registers, tx-rings and rx-rings
292 */
293 static void ixgbe_dump(struct ixgbe_adapter *adapter)
294 {
295 struct net_device *netdev = adapter->netdev;
296 struct ixgbe_hw *hw = &adapter->hw;
297 struct ixgbe_reg_info *reginfo;
298 int n = 0;
299 struct ixgbe_ring *tx_ring;
300 struct ixgbe_tx_buffer *tx_buffer;
301 union ixgbe_adv_tx_desc *tx_desc;
302 struct my_u0 { u64 a; u64 b; } *u0;
303 struct ixgbe_ring *rx_ring;
304 union ixgbe_adv_rx_desc *rx_desc;
305 struct ixgbe_rx_buffer *rx_buffer_info;
306 u32 staterr;
307 int i = 0;
308
309 if (!netif_msg_hw(adapter))
310 return;
311
312 /* Print netdevice Info */
313 if (netdev) {
314 dev_info(&adapter->pdev->dev, "Net device Info\n");
315 pr_info("Device Name state "
316 "trans_start last_rx\n");
317 pr_info("%-15s %016lX %016lX %016lX\n",
318 netdev->name,
319 netdev->state,
320 netdev->trans_start,
321 netdev->last_rx);
322 }
323
324 /* Print Registers */
325 dev_info(&adapter->pdev->dev, "Register Dump\n");
326 pr_info(" Register Name Value\n");
327 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
328 reginfo->name; reginfo++) {
329 ixgbe_regdump(hw, reginfo);
330 }
331
332 /* Print TX Ring Summary */
333 if (!netdev || !netif_running(netdev))
334 goto exit;
335
336 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
337 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
338 for (n = 0; n < adapter->num_tx_queues; n++) {
339 tx_ring = adapter->tx_ring[n];
340 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
341 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
342 n, tx_ring->next_to_use, tx_ring->next_to_clean,
343 (u64)dma_unmap_addr(tx_buffer, dma),
344 dma_unmap_len(tx_buffer, len),
345 tx_buffer->next_to_watch,
346 (u64)tx_buffer->time_stamp);
347 }
348
349 /* Print TX Rings */
350 if (!netif_msg_tx_done(adapter))
351 goto rx_ring_summary;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
354
355 /* Transmit Descriptor Formats
356 *
357 * Advanced Transmit Descriptor
358 * +--------------------------------------------------------------+
359 * 0 | Buffer Address [63:0] |
360 * +--------------------------------------------------------------+
361 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
362 * +--------------------------------------------------------------+
363 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
364 */
365
366 for (n = 0; n < adapter->num_tx_queues; n++) {
367 tx_ring = adapter->tx_ring[n];
368 pr_info("------------------------------------\n");
369 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
370 pr_info("------------------------------------\n");
371 pr_info("T [desc] [address 63:0 ] "
372 "[PlPOIdStDDt Ln] [bi->dma ] "
373 "leng ntw timestamp bi->skb\n");
374
375 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
376 tx_desc = IXGBE_TX_DESC(tx_ring, i);
377 tx_buffer = &tx_ring->tx_buffer_info[i];
378 u0 = (struct my_u0 *)tx_desc;
379 pr_info("T [0x%03X] %016llX %016llX %016llX"
380 " %04X %p %016llX %p", i,
381 le64_to_cpu(u0->a),
382 le64_to_cpu(u0->b),
383 (u64)dma_unmap_addr(tx_buffer, dma),
384 dma_unmap_len(tx_buffer, len),
385 tx_buffer->next_to_watch,
386 (u64)tx_buffer->time_stamp,
387 tx_buffer->skb);
388 if (i == tx_ring->next_to_use &&
389 i == tx_ring->next_to_clean)
390 pr_cont(" NTC/U\n");
391 else if (i == tx_ring->next_to_use)
392 pr_cont(" NTU\n");
393 else if (i == tx_ring->next_to_clean)
394 pr_cont(" NTC\n");
395 else
396 pr_cont("\n");
397
398 if (netif_msg_pktdata(adapter) &&
399 dma_unmap_len(tx_buffer, len) != 0)
400 print_hex_dump(KERN_INFO, "",
401 DUMP_PREFIX_ADDRESS, 16, 1,
402 phys_to_virt(dma_unmap_addr(tx_buffer,
403 dma)),
404 dma_unmap_len(tx_buffer, len),
405 true);
406 }
407 }
408
409 /* Print RX Rings Summary */
410 rx_ring_summary:
411 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
412 pr_info("Queue [NTU] [NTC]\n");
413 for (n = 0; n < adapter->num_rx_queues; n++) {
414 rx_ring = adapter->rx_ring[n];
415 pr_info("%5d %5X %5X\n",
416 n, rx_ring->next_to_use, rx_ring->next_to_clean);
417 }
418
419 /* Print RX Rings */
420 if (!netif_msg_rx_status(adapter))
421 goto exit;
422
423 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
424
425 /* Advanced Receive Descriptor (Read) Format
426 * 63 1 0
427 * +-----------------------------------------------------+
428 * 0 | Packet Buffer Address [63:1] |A0/NSE|
429 * +----------------------------------------------+------+
430 * 8 | Header Buffer Address [63:1] | DD |
431 * +-----------------------------------------------------+
432 *
433 *
434 * Advanced Receive Descriptor (Write-Back) Format
435 *
436 * 63 48 47 32 31 30 21 20 16 15 4 3 0
437 * +------------------------------------------------------+
438 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
439 * | Checksum Ident | | | | Type | Type |
440 * +------------------------------------------------------+
441 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
442 * +------------------------------------------------------+
443 * 63 48 47 32 31 20 19 0
444 */
445 for (n = 0; n < adapter->num_rx_queues; n++) {
446 rx_ring = adapter->rx_ring[n];
447 pr_info("------------------------------------\n");
448 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
449 pr_info("------------------------------------\n");
450 pr_info("R [desc] [ PktBuf A0] "
451 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
452 "<-- Adv Rx Read format\n");
453 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
454 "[vl er S cks ln] ---------------- [bi->skb] "
455 "<-- Adv Rx Write-Back format\n");
456
457 for (i = 0; i < rx_ring->count; i++) {
458 rx_buffer_info = &rx_ring->rx_buffer_info[i];
459 rx_desc = IXGBE_RX_DESC(rx_ring, i);
460 u0 = (struct my_u0 *)rx_desc;
461 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
462 if (staterr & IXGBE_RXD_STAT_DD) {
463 /* Descriptor Done */
464 pr_info("RWB[0x%03X] %016llX "
465 "%016llX ---------------- %p", i,
466 le64_to_cpu(u0->a),
467 le64_to_cpu(u0->b),
468 rx_buffer_info->skb);
469 } else {
470 pr_info("R [0x%03X] %016llX "
471 "%016llX %016llX %p", i,
472 le64_to_cpu(u0->a),
473 le64_to_cpu(u0->b),
474 (u64)rx_buffer_info->dma,
475 rx_buffer_info->skb);
476
477 if (netif_msg_pktdata(adapter)) {
478 print_hex_dump(KERN_INFO, "",
479 DUMP_PREFIX_ADDRESS, 16, 1,
480 phys_to_virt(rx_buffer_info->dma),
481 ixgbe_rx_bufsz(rx_ring), true);
482 }
483 }
484
485 if (i == rx_ring->next_to_use)
486 pr_cont(" NTU\n");
487 else if (i == rx_ring->next_to_clean)
488 pr_cont(" NTC\n");
489 else
490 pr_cont("\n");
491
492 }
493 }
494
495 exit:
496 return;
497 }
498
499 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
500 {
501 u32 ctrl_ext;
502
503 /* Let firmware take over control of h/w */
504 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
505 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
506 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
507 }
508
509 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
510 {
511 u32 ctrl_ext;
512
513 /* Let firmware know the driver has taken over */
514 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
515 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
516 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
517 }
518
519 /*
520 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
521 * @adapter: pointer to adapter struct
522 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
523 * @queue: queue to map the corresponding interrupt to
524 * @msix_vector: the vector to map to the corresponding queue
525 *
526 */
527 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
528 u8 queue, u8 msix_vector)
529 {
530 u32 ivar, index;
531 struct ixgbe_hw *hw = &adapter->hw;
532 switch (hw->mac.type) {
533 case ixgbe_mac_82598EB:
534 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
535 if (direction == -1)
536 direction = 0;
537 index = (((direction * 64) + queue) >> 2) & 0x1F;
538 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
539 ivar &= ~(0xFF << (8 * (queue & 0x3)));
540 ivar |= (msix_vector << (8 * (queue & 0x3)));
541 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
542 break;
543 case ixgbe_mac_82599EB:
544 case ixgbe_mac_X540:
545 if (direction == -1) {
546 /* other causes */
547 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
548 index = ((queue & 1) * 8);
549 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
550 ivar &= ~(0xFF << index);
551 ivar |= (msix_vector << index);
552 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
553 break;
554 } else {
555 /* tx or rx causes */
556 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
557 index = ((16 * (queue & 1)) + (8 * direction));
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
559 ivar &= ~(0xFF << index);
560 ivar |= (msix_vector << index);
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
562 break;
563 }
564 default:
565 break;
566 }
567 }
568
569 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
570 u64 qmask)
571 {
572 u32 mask;
573
574 switch (adapter->hw.mac.type) {
575 case ixgbe_mac_82598EB:
576 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
577 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
578 break;
579 case ixgbe_mac_82599EB:
580 case ixgbe_mac_X540:
581 mask = (qmask & 0xFFFFFFFF);
582 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
583 mask = (qmask >> 32);
584 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
585 break;
586 default:
587 break;
588 }
589 }
590
591 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
592 struct ixgbe_tx_buffer *tx_buffer)
593 {
594 if (tx_buffer->skb) {
595 dev_kfree_skb_any(tx_buffer->skb);
596 if (dma_unmap_len(tx_buffer, len))
597 dma_unmap_single(ring->dev,
598 dma_unmap_addr(tx_buffer, dma),
599 dma_unmap_len(tx_buffer, len),
600 DMA_TO_DEVICE);
601 } else if (dma_unmap_len(tx_buffer, len)) {
602 dma_unmap_page(ring->dev,
603 dma_unmap_addr(tx_buffer, dma),
604 dma_unmap_len(tx_buffer, len),
605 DMA_TO_DEVICE);
606 }
607 tx_buffer->next_to_watch = NULL;
608 tx_buffer->skb = NULL;
609 dma_unmap_len_set(tx_buffer, len, 0);
610 /* tx_buffer must be completely set up in the transmit path */
611 }
612
613 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
614 {
615 struct ixgbe_hw *hw = &adapter->hw;
616 struct ixgbe_hw_stats *hwstats = &adapter->stats;
617 int i;
618 u32 data;
619
620 if ((hw->fc.current_mode != ixgbe_fc_full) &&
621 (hw->fc.current_mode != ixgbe_fc_rx_pause))
622 return;
623
624 switch (hw->mac.type) {
625 case ixgbe_mac_82598EB:
626 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
627 break;
628 default:
629 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
630 }
631 hwstats->lxoffrxc += data;
632
633 /* refill credits (no tx hang) if we received xoff */
634 if (!data)
635 return;
636
637 for (i = 0; i < adapter->num_tx_queues; i++)
638 clear_bit(__IXGBE_HANG_CHECK_ARMED,
639 &adapter->tx_ring[i]->state);
640 }
641
642 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
643 {
644 struct ixgbe_hw *hw = &adapter->hw;
645 struct ixgbe_hw_stats *hwstats = &adapter->stats;
646 u32 xoff[8] = {0};
647 int i;
648 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
649
650 if (adapter->ixgbe_ieee_pfc)
651 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
652
653 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
654 ixgbe_update_xoff_rx_lfc(adapter);
655 return;
656 }
657
658 /* update stats for each tc, only valid with PFC enabled */
659 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
660 switch (hw->mac.type) {
661 case ixgbe_mac_82598EB:
662 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
663 break;
664 default:
665 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
666 }
667 hwstats->pxoffrxc[i] += xoff[i];
668 }
669
670 /* disarm tx queues that have received xoff frames */
671 for (i = 0; i < adapter->num_tx_queues; i++) {
672 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
673 u8 tc = tx_ring->dcb_tc;
674
675 if (xoff[tc])
676 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
677 }
678 }
679
680 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
681 {
682 return ring->stats.packets;
683 }
684
685 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
686 {
687 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
688 struct ixgbe_hw *hw = &adapter->hw;
689
690 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
691 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
692
693 if (head != tail)
694 return (head < tail) ?
695 tail - head : (tail + ring->count - head);
696
697 return 0;
698 }
699
700 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
701 {
702 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
703 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
704 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
705 bool ret = false;
706
707 clear_check_for_tx_hang(tx_ring);
708
709 /*
710 * Check for a hung queue, but be thorough. This verifies
711 * that a transmit has been completed since the previous
712 * check AND there is at least one packet pending. The
713 * ARMED bit is set to indicate a potential hang. The
714 * bit is cleared if a pause frame is received to remove
715 * false hang detection due to PFC or 802.3x frames. By
716 * requiring this to fail twice we avoid races with
717 * pfc clearing the ARMED bit and conditions where we
718 * run the check_tx_hang logic with a transmit completion
719 * pending but without time to complete it yet.
720 */
721 if ((tx_done_old == tx_done) && tx_pending) {
722 /* make sure it is true for two checks in a row */
723 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
724 &tx_ring->state);
725 } else {
726 /* update completed stats and continue */
727 tx_ring->tx_stats.tx_done_old = tx_done;
728 /* reset the countdown */
729 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
730 }
731
732 return ret;
733 }
734
735 /**
736 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
737 * @adapter: driver private struct
738 **/
739 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
740 {
741
742 /* Do the reset outside of interrupt context */
743 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
744 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
745 ixgbe_service_event_schedule(adapter);
746 }
747 }
748
749 /**
750 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
751 * @q_vector: structure containing interrupt and ring information
752 * @tx_ring: tx ring to clean
753 **/
754 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
755 struct ixgbe_ring *tx_ring)
756 {
757 struct ixgbe_adapter *adapter = q_vector->adapter;
758 struct ixgbe_tx_buffer *tx_buffer;
759 union ixgbe_adv_tx_desc *tx_desc;
760 unsigned int total_bytes = 0, total_packets = 0;
761 unsigned int budget = q_vector->tx.work_limit;
762 unsigned int i = tx_ring->next_to_clean;
763
764 if (test_bit(__IXGBE_DOWN, &adapter->state))
765 return true;
766
767 tx_buffer = &tx_ring->tx_buffer_info[i];
768 tx_desc = IXGBE_TX_DESC(tx_ring, i);
769 i -= tx_ring->count;
770
771 do {
772 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
773
774 /* if next_to_watch is not set then there is no work pending */
775 if (!eop_desc)
776 break;
777
778 /* prevent any other reads prior to eop_desc */
779 rmb();
780
781 /* if DD is not set pending work has not been completed */
782 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
783 break;
784
785 /* clear next_to_watch to prevent false hangs */
786 tx_buffer->next_to_watch = NULL;
787
788 /* update the statistics for this packet */
789 total_bytes += tx_buffer->bytecount;
790 total_packets += tx_buffer->gso_segs;
791
792 #ifdef CONFIG_IXGBE_PTP
793 if (unlikely(tx_buffer->tx_flags &
794 IXGBE_TX_FLAGS_TSTAMP))
795 ixgbe_ptp_tx_hwtstamp(q_vector,
796 tx_buffer->skb);
797
798 #endif
799 /* free the skb */
800 dev_kfree_skb_any(tx_buffer->skb);
801
802 /* unmap skb header data */
803 dma_unmap_single(tx_ring->dev,
804 dma_unmap_addr(tx_buffer, dma),
805 dma_unmap_len(tx_buffer, len),
806 DMA_TO_DEVICE);
807
808 /* clear tx_buffer data */
809 tx_buffer->skb = NULL;
810 dma_unmap_len_set(tx_buffer, len, 0);
811
812 /* unmap remaining buffers */
813 while (tx_desc != eop_desc) {
814 tx_buffer++;
815 tx_desc++;
816 i++;
817 if (unlikely(!i)) {
818 i -= tx_ring->count;
819 tx_buffer = tx_ring->tx_buffer_info;
820 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
821 }
822
823 /* unmap any remaining paged data */
824 if (dma_unmap_len(tx_buffer, len)) {
825 dma_unmap_page(tx_ring->dev,
826 dma_unmap_addr(tx_buffer, dma),
827 dma_unmap_len(tx_buffer, len),
828 DMA_TO_DEVICE);
829 dma_unmap_len_set(tx_buffer, len, 0);
830 }
831 }
832
833 /* move us one more past the eop_desc for start of next pkt */
834 tx_buffer++;
835 tx_desc++;
836 i++;
837 if (unlikely(!i)) {
838 i -= tx_ring->count;
839 tx_buffer = tx_ring->tx_buffer_info;
840 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
841 }
842
843 /* issue prefetch for next Tx descriptor */
844 prefetch(tx_desc);
845
846 /* update budget accounting */
847 budget--;
848 } while (likely(budget));
849
850 i += tx_ring->count;
851 tx_ring->next_to_clean = i;
852 u64_stats_update_begin(&tx_ring->syncp);
853 tx_ring->stats.bytes += total_bytes;
854 tx_ring->stats.packets += total_packets;
855 u64_stats_update_end(&tx_ring->syncp);
856 q_vector->tx.total_bytes += total_bytes;
857 q_vector->tx.total_packets += total_packets;
858
859 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
860 /* schedule immediate reset if we believe we hung */
861 struct ixgbe_hw *hw = &adapter->hw;
862 e_err(drv, "Detected Tx Unit Hang\n"
863 " Tx Queue <%d>\n"
864 " TDH, TDT <%x>, <%x>\n"
865 " next_to_use <%x>\n"
866 " next_to_clean <%x>\n"
867 "tx_buffer_info[next_to_clean]\n"
868 " time_stamp <%lx>\n"
869 " jiffies <%lx>\n",
870 tx_ring->queue_index,
871 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
872 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
873 tx_ring->next_to_use, i,
874 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
875
876 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
877
878 e_info(probe,
879 "tx hang %d detected on queue %d, resetting adapter\n",
880 adapter->tx_timeout_count + 1, tx_ring->queue_index);
881
882 /* schedule immediate reset if we believe we hung */
883 ixgbe_tx_timeout_reset(adapter);
884
885 /* the adapter is about to reset, no point in enabling stuff */
886 return true;
887 }
888
889 netdev_tx_completed_queue(txring_txq(tx_ring),
890 total_packets, total_bytes);
891
892 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
893 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
894 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
895 /* Make sure that anybody stopping the queue after this
896 * sees the new next_to_clean.
897 */
898 smp_mb();
899 if (__netif_subqueue_stopped(tx_ring->netdev,
900 tx_ring->queue_index)
901 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
902 netif_wake_subqueue(tx_ring->netdev,
903 tx_ring->queue_index);
904 ++tx_ring->tx_stats.restart_queue;
905 }
906 }
907
908 return !!budget;
909 }
910
911 #ifdef CONFIG_IXGBE_DCA
912 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
913 struct ixgbe_ring *tx_ring,
914 int cpu)
915 {
916 struct ixgbe_hw *hw = &adapter->hw;
917 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
918 u16 reg_offset;
919
920 switch (hw->mac.type) {
921 case ixgbe_mac_82598EB:
922 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
923 break;
924 case ixgbe_mac_82599EB:
925 case ixgbe_mac_X540:
926 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
927 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
928 break;
929 default:
930 /* for unknown hardware do not write register */
931 return;
932 }
933
934 /*
935 * We can enable relaxed ordering for reads, but not writes when
936 * DCA is enabled. This is due to a known issue in some chipsets
937 * which will cause the DCA tag to be cleared.
938 */
939 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
940 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
941 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
942
943 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
944 }
945
946 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
947 struct ixgbe_ring *rx_ring,
948 int cpu)
949 {
950 struct ixgbe_hw *hw = &adapter->hw;
951 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
952 u8 reg_idx = rx_ring->reg_idx;
953
954
955 switch (hw->mac.type) {
956 case ixgbe_mac_82599EB:
957 case ixgbe_mac_X540:
958 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
959 break;
960 default:
961 break;
962 }
963
964 /*
965 * We can enable relaxed ordering for reads, but not writes when
966 * DCA is enabled. This is due to a known issue in some chipsets
967 * which will cause the DCA tag to be cleared.
968 */
969 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
970 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
971 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
972
973 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
974 }
975
976 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
977 {
978 struct ixgbe_adapter *adapter = q_vector->adapter;
979 struct ixgbe_ring *ring;
980 int cpu = get_cpu();
981
982 if (q_vector->cpu == cpu)
983 goto out_no_update;
984
985 ixgbe_for_each_ring(ring, q_vector->tx)
986 ixgbe_update_tx_dca(adapter, ring, cpu);
987
988 ixgbe_for_each_ring(ring, q_vector->rx)
989 ixgbe_update_rx_dca(adapter, ring, cpu);
990
991 q_vector->cpu = cpu;
992 out_no_update:
993 put_cpu();
994 }
995
996 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
997 {
998 int num_q_vectors;
999 int i;
1000
1001 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1002 return;
1003
1004 /* always use CB2 mode, difference is masked in the CB driver */
1005 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1006
1007 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1008 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1009 else
1010 num_q_vectors = 1;
1011
1012 for (i = 0; i < num_q_vectors; i++) {
1013 adapter->q_vector[i]->cpu = -1;
1014 ixgbe_update_dca(adapter->q_vector[i]);
1015 }
1016 }
1017
1018 static int __ixgbe_notify_dca(struct device *dev, void *data)
1019 {
1020 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1021 unsigned long event = *(unsigned long *)data;
1022
1023 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1024 return 0;
1025
1026 switch (event) {
1027 case DCA_PROVIDER_ADD:
1028 /* if we're already enabled, don't do it again */
1029 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1030 break;
1031 if (dca_add_requester(dev) == 0) {
1032 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1033 ixgbe_setup_dca(adapter);
1034 break;
1035 }
1036 /* Fall Through since DCA is disabled. */
1037 case DCA_PROVIDER_REMOVE:
1038 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1039 dca_remove_requester(dev);
1040 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1041 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1042 }
1043 break;
1044 }
1045
1046 return 0;
1047 }
1048
1049 #endif /* CONFIG_IXGBE_DCA */
1050 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1051 union ixgbe_adv_rx_desc *rx_desc,
1052 struct sk_buff *skb)
1053 {
1054 if (ring->netdev->features & NETIF_F_RXHASH)
1055 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1056 }
1057
1058 #ifdef IXGBE_FCOE
1059 /**
1060 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1061 * @ring: structure containing ring specific data
1062 * @rx_desc: advanced rx descriptor
1063 *
1064 * Returns : true if it is FCoE pkt
1065 */
1066 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1067 union ixgbe_adv_rx_desc *rx_desc)
1068 {
1069 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1070
1071 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1072 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1073 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1074 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1075 }
1076
1077 #endif /* IXGBE_FCOE */
1078 /**
1079 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1080 * @ring: structure containing ring specific data
1081 * @rx_desc: current Rx descriptor being processed
1082 * @skb: skb currently being received and modified
1083 **/
1084 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1085 union ixgbe_adv_rx_desc *rx_desc,
1086 struct sk_buff *skb)
1087 {
1088 skb_checksum_none_assert(skb);
1089
1090 /* Rx csum disabled */
1091 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1092 return;
1093
1094 /* if IP and error */
1095 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1096 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1097 ring->rx_stats.csum_err++;
1098 return;
1099 }
1100
1101 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1102 return;
1103
1104 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1105 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1106
1107 /*
1108 * 82599 errata, UDP frames with a 0 checksum can be marked as
1109 * checksum errors.
1110 */
1111 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1112 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1113 return;
1114
1115 ring->rx_stats.csum_err++;
1116 return;
1117 }
1118
1119 /* It must be a TCP or UDP packet with a valid checksum */
1120 skb->ip_summed = CHECKSUM_UNNECESSARY;
1121 }
1122
1123 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1124 {
1125 rx_ring->next_to_use = val;
1126
1127 /* update next to alloc since we have filled the ring */
1128 rx_ring->next_to_alloc = val;
1129 /*
1130 * Force memory writes to complete before letting h/w
1131 * know there are new descriptors to fetch. (Only
1132 * applicable for weak-ordered memory model archs,
1133 * such as IA-64).
1134 */
1135 wmb();
1136 writel(val, rx_ring->tail);
1137 }
1138
1139 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1140 struct ixgbe_rx_buffer *bi)
1141 {
1142 struct page *page = bi->page;
1143 dma_addr_t dma = bi->dma;
1144
1145 /* since we are recycling buffers we should seldom need to alloc */
1146 if (likely(dma))
1147 return true;
1148
1149 /* alloc new page for storage */
1150 if (likely(!page)) {
1151 page = alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1152 ixgbe_rx_pg_order(rx_ring));
1153 if (unlikely(!page)) {
1154 rx_ring->rx_stats.alloc_rx_page_failed++;
1155 return false;
1156 }
1157 bi->page = page;
1158 }
1159
1160 /* map page for use */
1161 dma = dma_map_page(rx_ring->dev, page, 0,
1162 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1163
1164 /*
1165 * if mapping failed free memory back to system since
1166 * there isn't much point in holding memory we can't use
1167 */
1168 if (dma_mapping_error(rx_ring->dev, dma)) {
1169 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1170 bi->page = NULL;
1171
1172 rx_ring->rx_stats.alloc_rx_page_failed++;
1173 return false;
1174 }
1175
1176 bi->dma = dma;
1177 bi->page_offset ^= ixgbe_rx_bufsz(rx_ring);
1178
1179 return true;
1180 }
1181
1182 /**
1183 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1184 * @rx_ring: ring to place buffers on
1185 * @cleaned_count: number of buffers to replace
1186 **/
1187 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1188 {
1189 union ixgbe_adv_rx_desc *rx_desc;
1190 struct ixgbe_rx_buffer *bi;
1191 u16 i = rx_ring->next_to_use;
1192
1193 /* nothing to do */
1194 if (!cleaned_count)
1195 return;
1196
1197 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1198 bi = &rx_ring->rx_buffer_info[i];
1199 i -= rx_ring->count;
1200
1201 do {
1202 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1203 break;
1204
1205 /*
1206 * Refresh the desc even if buffer_addrs didn't change
1207 * because each write-back erases this info.
1208 */
1209 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1210
1211 rx_desc++;
1212 bi++;
1213 i++;
1214 if (unlikely(!i)) {
1215 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1216 bi = rx_ring->rx_buffer_info;
1217 i -= rx_ring->count;
1218 }
1219
1220 /* clear the hdr_addr for the next_to_use descriptor */
1221 rx_desc->read.hdr_addr = 0;
1222
1223 cleaned_count--;
1224 } while (cleaned_count);
1225
1226 i += rx_ring->count;
1227
1228 if (rx_ring->next_to_use != i)
1229 ixgbe_release_rx_desc(rx_ring, i);
1230 }
1231
1232 /**
1233 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1234 * @data: pointer to the start of the headers
1235 * @max_len: total length of section to find headers in
1236 *
1237 * This function is meant to determine the length of headers that will
1238 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1239 * motivation of doing this is to only perform one pull for IPv4 TCP
1240 * packets so that we can do basic things like calculating the gso_size
1241 * based on the average data per packet.
1242 **/
1243 static unsigned int ixgbe_get_headlen(unsigned char *data,
1244 unsigned int max_len)
1245 {
1246 union {
1247 unsigned char *network;
1248 /* l2 headers */
1249 struct ethhdr *eth;
1250 struct vlan_hdr *vlan;
1251 /* l3 headers */
1252 struct iphdr *ipv4;
1253 } hdr;
1254 __be16 protocol;
1255 u8 nexthdr = 0; /* default to not TCP */
1256 u8 hlen;
1257
1258 /* this should never happen, but better safe than sorry */
1259 if (max_len < ETH_HLEN)
1260 return max_len;
1261
1262 /* initialize network frame pointer */
1263 hdr.network = data;
1264
1265 /* set first protocol and move network header forward */
1266 protocol = hdr.eth->h_proto;
1267 hdr.network += ETH_HLEN;
1268
1269 /* handle any vlan tag if present */
1270 if (protocol == __constant_htons(ETH_P_8021Q)) {
1271 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1272 return max_len;
1273
1274 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1275 hdr.network += VLAN_HLEN;
1276 }
1277
1278 /* handle L3 protocols */
1279 if (protocol == __constant_htons(ETH_P_IP)) {
1280 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1281 return max_len;
1282
1283 /* access ihl as a u8 to avoid unaligned access on ia64 */
1284 hlen = (hdr.network[0] & 0x0F) << 2;
1285
1286 /* verify hlen meets minimum size requirements */
1287 if (hlen < sizeof(struct iphdr))
1288 return hdr.network - data;
1289
1290 /* record next protocol */
1291 nexthdr = hdr.ipv4->protocol;
1292 hdr.network += hlen;
1293 #ifdef IXGBE_FCOE
1294 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1295 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1296 return max_len;
1297 hdr.network += FCOE_HEADER_LEN;
1298 #endif
1299 } else {
1300 return hdr.network - data;
1301 }
1302
1303 /* finally sort out TCP */
1304 if (nexthdr == IPPROTO_TCP) {
1305 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1306 return max_len;
1307
1308 /* access doff as a u8 to avoid unaligned access on ia64 */
1309 hlen = (hdr.network[12] & 0xF0) >> 2;
1310
1311 /* verify hlen meets minimum size requirements */
1312 if (hlen < sizeof(struct tcphdr))
1313 return hdr.network - data;
1314
1315 hdr.network += hlen;
1316 }
1317
1318 /*
1319 * If everything has gone correctly hdr.network should be the
1320 * data section of the packet and will be the end of the header.
1321 * If not then it probably represents the end of the last recognized
1322 * header.
1323 */
1324 if ((hdr.network - data) < max_len)
1325 return hdr.network - data;
1326 else
1327 return max_len;
1328 }
1329
1330 static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1331 union ixgbe_adv_rx_desc *rx_desc,
1332 struct sk_buff *skb)
1333 {
1334 __le32 rsc_enabled;
1335 u32 rsc_cnt;
1336
1337 if (!ring_is_rsc_enabled(rx_ring))
1338 return;
1339
1340 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1341 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1342
1343 /* If this is an RSC frame rsc_cnt should be non-zero */
1344 if (!rsc_enabled)
1345 return;
1346
1347 rsc_cnt = le32_to_cpu(rsc_enabled);
1348 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1349
1350 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1351 }
1352
1353 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1354 struct sk_buff *skb)
1355 {
1356 u16 hdr_len = skb_headlen(skb);
1357
1358 /* set gso_size to avoid messing up TCP MSS */
1359 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1360 IXGBE_CB(skb)->append_cnt);
1361 }
1362
1363 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1364 struct sk_buff *skb)
1365 {
1366 /* if append_cnt is 0 then frame is not RSC */
1367 if (!IXGBE_CB(skb)->append_cnt)
1368 return;
1369
1370 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1371 rx_ring->rx_stats.rsc_flush++;
1372
1373 ixgbe_set_rsc_gso_size(rx_ring, skb);
1374
1375 /* gso_size is computed using append_cnt so always clear it last */
1376 IXGBE_CB(skb)->append_cnt = 0;
1377 }
1378
1379 /**
1380 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1381 * @rx_ring: rx descriptor ring packet is being transacted on
1382 * @rx_desc: pointer to the EOP Rx descriptor
1383 * @skb: pointer to current skb being populated
1384 *
1385 * This function checks the ring, descriptor, and packet information in
1386 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1387 * other fields within the skb.
1388 **/
1389 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1390 union ixgbe_adv_rx_desc *rx_desc,
1391 struct sk_buff *skb)
1392 {
1393 struct net_device *dev = rx_ring->netdev;
1394
1395 ixgbe_update_rsc_stats(rx_ring, skb);
1396
1397 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1398
1399 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1400
1401 #ifdef CONFIG_IXGBE_PTP
1402 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))
1403 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, skb);
1404 #endif
1405
1406 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1407 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1408 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1409 __vlan_hwaccel_put_tag(skb, vid);
1410 }
1411
1412 skb_record_rx_queue(skb, rx_ring->queue_index);
1413
1414 skb->protocol = eth_type_trans(skb, dev);
1415 }
1416
1417 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1418 struct sk_buff *skb)
1419 {
1420 struct ixgbe_adapter *adapter = q_vector->adapter;
1421
1422 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1423 napi_gro_receive(&q_vector->napi, skb);
1424 else
1425 netif_rx(skb);
1426 }
1427
1428 /**
1429 * ixgbe_is_non_eop - process handling of non-EOP buffers
1430 * @rx_ring: Rx ring being processed
1431 * @rx_desc: Rx descriptor for current buffer
1432 * @skb: Current socket buffer containing buffer in progress
1433 *
1434 * This function updates next to clean. If the buffer is an EOP buffer
1435 * this function exits returning false, otherwise it will place the
1436 * sk_buff in the next buffer to be chained and return true indicating
1437 * that this is in fact a non-EOP buffer.
1438 **/
1439 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1440 union ixgbe_adv_rx_desc *rx_desc,
1441 struct sk_buff *skb)
1442 {
1443 u32 ntc = rx_ring->next_to_clean + 1;
1444
1445 /* fetch, update, and store next to clean */
1446 ntc = (ntc < rx_ring->count) ? ntc : 0;
1447 rx_ring->next_to_clean = ntc;
1448
1449 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1450
1451 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1452 return false;
1453
1454 /* append_cnt indicates packet is RSC, if so fetch nextp */
1455 if (IXGBE_CB(skb)->append_cnt) {
1456 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1457 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1458 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1459 }
1460
1461 /* place skb in next buffer to be received */
1462 rx_ring->rx_buffer_info[ntc].skb = skb;
1463 rx_ring->rx_stats.non_eop_descs++;
1464
1465 return true;
1466 }
1467
1468 /**
1469 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1470 * @rx_ring: rx descriptor ring packet is being transacted on
1471 * @rx_desc: pointer to the EOP Rx descriptor
1472 * @skb: pointer to current skb being fixed
1473 *
1474 * Check for corrupted packet headers caused by senders on the local L2
1475 * embedded NIC switch not setting up their Tx Descriptors right. These
1476 * should be very rare.
1477 *
1478 * Also address the case where we are pulling data in on pages only
1479 * and as such no data is present in the skb header.
1480 *
1481 * In addition if skb is not at least 60 bytes we need to pad it so that
1482 * it is large enough to qualify as a valid Ethernet frame.
1483 *
1484 * Returns true if an error was encountered and skb was freed.
1485 **/
1486 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1487 union ixgbe_adv_rx_desc *rx_desc,
1488 struct sk_buff *skb)
1489 {
1490 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1491 struct net_device *netdev = rx_ring->netdev;
1492 unsigned char *va;
1493 unsigned int pull_len;
1494
1495 /* if the page was released unmap it, else just sync our portion */
1496 if (unlikely(IXGBE_CB(skb)->page_released)) {
1497 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1498 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1499 IXGBE_CB(skb)->page_released = false;
1500 } else {
1501 dma_sync_single_range_for_cpu(rx_ring->dev,
1502 IXGBE_CB(skb)->dma,
1503 frag->page_offset,
1504 ixgbe_rx_bufsz(rx_ring),
1505 DMA_FROM_DEVICE);
1506 }
1507 IXGBE_CB(skb)->dma = 0;
1508
1509 /* verify that the packet does not have any known errors */
1510 if (unlikely(ixgbe_test_staterr(rx_desc,
1511 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1512 !(netdev->features & NETIF_F_RXALL))) {
1513 dev_kfree_skb_any(skb);
1514 return true;
1515 }
1516
1517 /*
1518 * it is valid to use page_address instead of kmap since we are
1519 * working with pages allocated out of the lomem pool per
1520 * alloc_page(GFP_ATOMIC)
1521 */
1522 va = skb_frag_address(frag);
1523
1524 /*
1525 * we need the header to contain the greater of either ETH_HLEN or
1526 * 60 bytes if the skb->len is less than 60 for skb_pad.
1527 */
1528 pull_len = skb_frag_size(frag);
1529 if (pull_len > 256)
1530 pull_len = ixgbe_get_headlen(va, pull_len);
1531
1532 /* align pull length to size of long to optimize memcpy performance */
1533 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1534
1535 /* update all of the pointers */
1536 skb_frag_size_sub(frag, pull_len);
1537 frag->page_offset += pull_len;
1538 skb->data_len -= pull_len;
1539 skb->tail += pull_len;
1540
1541 /*
1542 * if we sucked the frag empty then we should free it,
1543 * if there are other frags here something is screwed up in hardware
1544 */
1545 if (skb_frag_size(frag) == 0) {
1546 BUG_ON(skb_shinfo(skb)->nr_frags != 1);
1547 skb_shinfo(skb)->nr_frags = 0;
1548 __skb_frag_unref(frag);
1549 skb->truesize -= ixgbe_rx_bufsz(rx_ring);
1550 }
1551
1552 #ifdef IXGBE_FCOE
1553 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1554 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1555 return false;
1556
1557 #endif
1558 /* if skb_pad returns an error the skb was freed */
1559 if (unlikely(skb->len < 60)) {
1560 int pad_len = 60 - skb->len;
1561
1562 if (skb_pad(skb, pad_len))
1563 return true;
1564 __skb_put(skb, pad_len);
1565 }
1566
1567 return false;
1568 }
1569
1570 /**
1571 * ixgbe_can_reuse_page - determine if we can reuse a page
1572 * @rx_buffer: pointer to rx_buffer containing the page we want to reuse
1573 *
1574 * Returns true if page can be reused in another Rx buffer
1575 **/
1576 static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer)
1577 {
1578 struct page *page = rx_buffer->page;
1579
1580 /* if we are only owner of page and it is local we can reuse it */
1581 return likely(page_count(page) == 1) &&
1582 likely(page_to_nid(page) == numa_node_id());
1583 }
1584
1585 /**
1586 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1587 * @rx_ring: rx descriptor ring to store buffers on
1588 * @old_buff: donor buffer to have page reused
1589 *
1590 * Syncronizes page for reuse by the adapter
1591 **/
1592 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1593 struct ixgbe_rx_buffer *old_buff)
1594 {
1595 struct ixgbe_rx_buffer *new_buff;
1596 u16 nta = rx_ring->next_to_alloc;
1597 u16 bufsz = ixgbe_rx_bufsz(rx_ring);
1598
1599 new_buff = &rx_ring->rx_buffer_info[nta];
1600
1601 /* update, and store next to alloc */
1602 nta++;
1603 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1604
1605 /* transfer page from old buffer to new buffer */
1606 new_buff->page = old_buff->page;
1607 new_buff->dma = old_buff->dma;
1608
1609 /* flip page offset to other buffer and store to new_buff */
1610 new_buff->page_offset = old_buff->page_offset ^ bufsz;
1611
1612 /* sync the buffer for use by the device */
1613 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1614 new_buff->page_offset, bufsz,
1615 DMA_FROM_DEVICE);
1616
1617 /* bump ref count on page before it is given to the stack */
1618 get_page(new_buff->page);
1619 }
1620
1621 /**
1622 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1623 * @rx_ring: rx descriptor ring to transact packets on
1624 * @rx_buffer: buffer containing page to add
1625 * @rx_desc: descriptor containing length of buffer written by hardware
1626 * @skb: sk_buff to place the data into
1627 *
1628 * This function is based on skb_add_rx_frag. I would have used that
1629 * function however it doesn't handle the truesize case correctly since we
1630 * are allocating more memory than might be used for a single receive.
1631 **/
1632 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1633 struct ixgbe_rx_buffer *rx_buffer,
1634 struct sk_buff *skb, int size)
1635 {
1636 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1637 rx_buffer->page, rx_buffer->page_offset,
1638 size);
1639 skb->len += size;
1640 skb->data_len += size;
1641 skb->truesize += ixgbe_rx_bufsz(rx_ring);
1642 }
1643
1644 /**
1645 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1646 * @q_vector: structure containing interrupt and ring information
1647 * @rx_ring: rx descriptor ring to transact packets on
1648 * @budget: Total limit on number of packets to process
1649 *
1650 * This function provides a "bounce buffer" approach to Rx interrupt
1651 * processing. The advantage to this is that on systems that have
1652 * expensive overhead for IOMMU access this provides a means of avoiding
1653 * it by maintaining the mapping of the page to the syste.
1654 *
1655 * Returns true if all work is completed without reaching budget
1656 **/
1657 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1658 struct ixgbe_ring *rx_ring,
1659 int budget)
1660 {
1661 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1662 #ifdef IXGBE_FCOE
1663 struct ixgbe_adapter *adapter = q_vector->adapter;
1664 int ddp_bytes = 0;
1665 #endif /* IXGBE_FCOE */
1666 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1667
1668 do {
1669 struct ixgbe_rx_buffer *rx_buffer;
1670 union ixgbe_adv_rx_desc *rx_desc;
1671 struct sk_buff *skb;
1672 struct page *page;
1673 u16 ntc;
1674
1675 /* return some buffers to hardware, one at a time is too slow */
1676 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1677 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1678 cleaned_count = 0;
1679 }
1680
1681 ntc = rx_ring->next_to_clean;
1682 rx_desc = IXGBE_RX_DESC(rx_ring, ntc);
1683 rx_buffer = &rx_ring->rx_buffer_info[ntc];
1684
1685 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1686 break;
1687
1688 /*
1689 * This memory barrier is needed to keep us from reading
1690 * any other fields out of the rx_desc until we know the
1691 * RXD_STAT_DD bit is set
1692 */
1693 rmb();
1694
1695 page = rx_buffer->page;
1696 prefetchw(page);
1697
1698 skb = rx_buffer->skb;
1699
1700 if (likely(!skb)) {
1701 void *page_addr = page_address(page) +
1702 rx_buffer->page_offset;
1703
1704 /* prefetch first cache line of first page */
1705 prefetch(page_addr);
1706 #if L1_CACHE_BYTES < 128
1707 prefetch(page_addr + L1_CACHE_BYTES);
1708 #endif
1709
1710 /* allocate a skb to store the frags */
1711 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1712 IXGBE_RX_HDR_SIZE);
1713 if (unlikely(!skb)) {
1714 rx_ring->rx_stats.alloc_rx_buff_failed++;
1715 break;
1716 }
1717
1718 /*
1719 * we will be copying header into skb->data in
1720 * pskb_may_pull so it is in our interest to prefetch
1721 * it now to avoid a possible cache miss
1722 */
1723 prefetchw(skb->data);
1724
1725 /*
1726 * Delay unmapping of the first packet. It carries the
1727 * header information, HW may still access the header
1728 * after the writeback. Only unmap it when EOP is
1729 * reached
1730 */
1731 IXGBE_CB(skb)->dma = rx_buffer->dma;
1732 } else {
1733 /* we are reusing so sync this buffer for CPU use */
1734 dma_sync_single_range_for_cpu(rx_ring->dev,
1735 rx_buffer->dma,
1736 rx_buffer->page_offset,
1737 ixgbe_rx_bufsz(rx_ring),
1738 DMA_FROM_DEVICE);
1739 }
1740
1741 /* pull page into skb */
1742 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb,
1743 le16_to_cpu(rx_desc->wb.upper.length));
1744
1745 if (ixgbe_can_reuse_page(rx_buffer)) {
1746 /* hand second half of page back to the ring */
1747 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1748 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1749 /* the page has been released from the ring */
1750 IXGBE_CB(skb)->page_released = true;
1751 } else {
1752 /* we are not reusing the buffer so unmap it */
1753 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1754 ixgbe_rx_pg_size(rx_ring),
1755 DMA_FROM_DEVICE);
1756 }
1757
1758 /* clear contents of buffer_info */
1759 rx_buffer->skb = NULL;
1760 rx_buffer->dma = 0;
1761 rx_buffer->page = NULL;
1762
1763 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
1764
1765 cleaned_count++;
1766
1767 /* place incomplete frames back on ring for completion */
1768 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1769 continue;
1770
1771 /* verify the packet layout is correct */
1772 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1773 continue;
1774
1775 /* probably a little skewed due to removing CRC */
1776 total_rx_bytes += skb->len;
1777 total_rx_packets++;
1778
1779 /* populate checksum, timestamp, VLAN, and protocol */
1780 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1781
1782 #ifdef IXGBE_FCOE
1783 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1784 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
1785 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1786 if (!ddp_bytes) {
1787 dev_kfree_skb_any(skb);
1788 continue;
1789 }
1790 }
1791
1792 #endif /* IXGBE_FCOE */
1793 ixgbe_rx_skb(q_vector, skb);
1794
1795 /* update budget accounting */
1796 budget--;
1797 } while (likely(budget));
1798
1799 #ifdef IXGBE_FCOE
1800 /* include DDPed FCoE data */
1801 if (ddp_bytes > 0) {
1802 unsigned int mss;
1803
1804 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1805 sizeof(struct fc_frame_header) -
1806 sizeof(struct fcoe_crc_eof);
1807 if (mss > 512)
1808 mss &= ~511;
1809 total_rx_bytes += ddp_bytes;
1810 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1811 }
1812
1813 #endif /* IXGBE_FCOE */
1814 u64_stats_update_begin(&rx_ring->syncp);
1815 rx_ring->stats.packets += total_rx_packets;
1816 rx_ring->stats.bytes += total_rx_bytes;
1817 u64_stats_update_end(&rx_ring->syncp);
1818 q_vector->rx.total_packets += total_rx_packets;
1819 q_vector->rx.total_bytes += total_rx_bytes;
1820
1821 if (cleaned_count)
1822 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1823
1824 return !!budget;
1825 }
1826
1827 /**
1828 * ixgbe_configure_msix - Configure MSI-X hardware
1829 * @adapter: board private structure
1830 *
1831 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1832 * interrupts.
1833 **/
1834 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1835 {
1836 struct ixgbe_q_vector *q_vector;
1837 int q_vectors, v_idx;
1838 u32 mask;
1839
1840 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1841
1842 /* Populate MSIX to EITR Select */
1843 if (adapter->num_vfs > 32) {
1844 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1845 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1846 }
1847
1848 /*
1849 * Populate the IVAR table and set the ITR values to the
1850 * corresponding register.
1851 */
1852 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1853 struct ixgbe_ring *ring;
1854 q_vector = adapter->q_vector[v_idx];
1855
1856 ixgbe_for_each_ring(ring, q_vector->rx)
1857 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1858
1859 ixgbe_for_each_ring(ring, q_vector->tx)
1860 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1861
1862 if (q_vector->tx.ring && !q_vector->rx.ring) {
1863 /* tx only vector */
1864 if (adapter->tx_itr_setting == 1)
1865 q_vector->itr = IXGBE_10K_ITR;
1866 else
1867 q_vector->itr = adapter->tx_itr_setting;
1868 } else {
1869 /* rx or rx/tx vector */
1870 if (adapter->rx_itr_setting == 1)
1871 q_vector->itr = IXGBE_20K_ITR;
1872 else
1873 q_vector->itr = adapter->rx_itr_setting;
1874 }
1875
1876 ixgbe_write_eitr(q_vector);
1877 }
1878
1879 switch (adapter->hw.mac.type) {
1880 case ixgbe_mac_82598EB:
1881 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1882 v_idx);
1883 break;
1884 case ixgbe_mac_82599EB:
1885 case ixgbe_mac_X540:
1886 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1887 break;
1888 default:
1889 break;
1890 }
1891 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1892
1893 /* set up to autoclear timer, and the vectors */
1894 mask = IXGBE_EIMS_ENABLE_MASK;
1895 mask &= ~(IXGBE_EIMS_OTHER |
1896 IXGBE_EIMS_MAILBOX |
1897 IXGBE_EIMS_LSC);
1898
1899 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1900 }
1901
1902 enum latency_range {
1903 lowest_latency = 0,
1904 low_latency = 1,
1905 bulk_latency = 2,
1906 latency_invalid = 255
1907 };
1908
1909 /**
1910 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1911 * @q_vector: structure containing interrupt and ring information
1912 * @ring_container: structure containing ring performance data
1913 *
1914 * Stores a new ITR value based on packets and byte
1915 * counts during the last interrupt. The advantage of per interrupt
1916 * computation is faster updates and more accurate ITR for the current
1917 * traffic pattern. Constants in this function were computed
1918 * based on theoretical maximum wire speed and thresholds were set based
1919 * on testing data as well as attempting to minimize response time
1920 * while increasing bulk throughput.
1921 * this functionality is controlled by the InterruptThrottleRate module
1922 * parameter (see ixgbe_param.c)
1923 **/
1924 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1925 struct ixgbe_ring_container *ring_container)
1926 {
1927 int bytes = ring_container->total_bytes;
1928 int packets = ring_container->total_packets;
1929 u32 timepassed_us;
1930 u64 bytes_perint;
1931 u8 itr_setting = ring_container->itr;
1932
1933 if (packets == 0)
1934 return;
1935
1936 /* simple throttlerate management
1937 * 0-10MB/s lowest (100000 ints/s)
1938 * 10-20MB/s low (20000 ints/s)
1939 * 20-1249MB/s bulk (8000 ints/s)
1940 */
1941 /* what was last interrupt timeslice? */
1942 timepassed_us = q_vector->itr >> 2;
1943 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1944
1945 switch (itr_setting) {
1946 case lowest_latency:
1947 if (bytes_perint > 10)
1948 itr_setting = low_latency;
1949 break;
1950 case low_latency:
1951 if (bytes_perint > 20)
1952 itr_setting = bulk_latency;
1953 else if (bytes_perint <= 10)
1954 itr_setting = lowest_latency;
1955 break;
1956 case bulk_latency:
1957 if (bytes_perint <= 20)
1958 itr_setting = low_latency;
1959 break;
1960 }
1961
1962 /* clear work counters since we have the values we need */
1963 ring_container->total_bytes = 0;
1964 ring_container->total_packets = 0;
1965
1966 /* write updated itr to ring container */
1967 ring_container->itr = itr_setting;
1968 }
1969
1970 /**
1971 * ixgbe_write_eitr - write EITR register in hardware specific way
1972 * @q_vector: structure containing interrupt and ring information
1973 *
1974 * This function is made to be called by ethtool and by the driver
1975 * when it needs to update EITR registers at runtime. Hardware
1976 * specific quirks/differences are taken care of here.
1977 */
1978 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1979 {
1980 struct ixgbe_adapter *adapter = q_vector->adapter;
1981 struct ixgbe_hw *hw = &adapter->hw;
1982 int v_idx = q_vector->v_idx;
1983 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
1984
1985 switch (adapter->hw.mac.type) {
1986 case ixgbe_mac_82598EB:
1987 /* must write high and low 16 bits to reset counter */
1988 itr_reg |= (itr_reg << 16);
1989 break;
1990 case ixgbe_mac_82599EB:
1991 case ixgbe_mac_X540:
1992 /*
1993 * set the WDIS bit to not clear the timer bits and cause an
1994 * immediate assertion of the interrupt
1995 */
1996 itr_reg |= IXGBE_EITR_CNT_WDIS;
1997 break;
1998 default:
1999 break;
2000 }
2001 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2002 }
2003
2004 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2005 {
2006 u32 new_itr = q_vector->itr;
2007 u8 current_itr;
2008
2009 ixgbe_update_itr(q_vector, &q_vector->tx);
2010 ixgbe_update_itr(q_vector, &q_vector->rx);
2011
2012 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2013
2014 switch (current_itr) {
2015 /* counts and packets in update_itr are dependent on these numbers */
2016 case lowest_latency:
2017 new_itr = IXGBE_100K_ITR;
2018 break;
2019 case low_latency:
2020 new_itr = IXGBE_20K_ITR;
2021 break;
2022 case bulk_latency:
2023 new_itr = IXGBE_8K_ITR;
2024 break;
2025 default:
2026 break;
2027 }
2028
2029 if (new_itr != q_vector->itr) {
2030 /* do an exponential smoothing */
2031 new_itr = (10 * new_itr * q_vector->itr) /
2032 ((9 * new_itr) + q_vector->itr);
2033
2034 /* save the algorithm value here */
2035 q_vector->itr = new_itr;
2036
2037 ixgbe_write_eitr(q_vector);
2038 }
2039 }
2040
2041 /**
2042 * ixgbe_check_overtemp_subtask - check for over temperature
2043 * @adapter: pointer to adapter
2044 **/
2045 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2046 {
2047 struct ixgbe_hw *hw = &adapter->hw;
2048 u32 eicr = adapter->interrupt_event;
2049
2050 if (test_bit(__IXGBE_DOWN, &adapter->state))
2051 return;
2052
2053 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2054 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2055 return;
2056
2057 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2058
2059 switch (hw->device_id) {
2060 case IXGBE_DEV_ID_82599_T3_LOM:
2061 /*
2062 * Since the warning interrupt is for both ports
2063 * we don't have to check if:
2064 * - This interrupt wasn't for our port.
2065 * - We may have missed the interrupt so always have to
2066 * check if we got a LSC
2067 */
2068 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2069 !(eicr & IXGBE_EICR_LSC))
2070 return;
2071
2072 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2073 u32 autoneg;
2074 bool link_up = false;
2075
2076 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2077
2078 if (link_up)
2079 return;
2080 }
2081
2082 /* Check if this is not due to overtemp */
2083 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2084 return;
2085
2086 break;
2087 default:
2088 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2089 return;
2090 break;
2091 }
2092 e_crit(drv,
2093 "Network adapter has been stopped because it has over heated. "
2094 "Restart the computer. If the problem persists, "
2095 "power off the system and replace the adapter\n");
2096
2097 adapter->interrupt_event = 0;
2098 }
2099
2100 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2101 {
2102 struct ixgbe_hw *hw = &adapter->hw;
2103
2104 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2105 (eicr & IXGBE_EICR_GPI_SDP1)) {
2106 e_crit(probe, "Fan has stopped, replace the adapter\n");
2107 /* write to clear the interrupt */
2108 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2109 }
2110 }
2111
2112 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2113 {
2114 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2115 return;
2116
2117 switch (adapter->hw.mac.type) {
2118 case ixgbe_mac_82599EB:
2119 /*
2120 * Need to check link state so complete overtemp check
2121 * on service task
2122 */
2123 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2124 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2125 adapter->interrupt_event = eicr;
2126 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2127 ixgbe_service_event_schedule(adapter);
2128 return;
2129 }
2130 return;
2131 case ixgbe_mac_X540:
2132 if (!(eicr & IXGBE_EICR_TS))
2133 return;
2134 break;
2135 default:
2136 return;
2137 }
2138
2139 e_crit(drv,
2140 "Network adapter has been stopped because it has over heated. "
2141 "Restart the computer. If the problem persists, "
2142 "power off the system and replace the adapter\n");
2143 }
2144
2145 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2146 {
2147 struct ixgbe_hw *hw = &adapter->hw;
2148
2149 if (eicr & IXGBE_EICR_GPI_SDP2) {
2150 /* Clear the interrupt */
2151 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2152 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2153 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2154 ixgbe_service_event_schedule(adapter);
2155 }
2156 }
2157
2158 if (eicr & IXGBE_EICR_GPI_SDP1) {
2159 /* Clear the interrupt */
2160 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2161 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2162 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2163 ixgbe_service_event_schedule(adapter);
2164 }
2165 }
2166 }
2167
2168 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2169 {
2170 struct ixgbe_hw *hw = &adapter->hw;
2171
2172 adapter->lsc_int++;
2173 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2174 adapter->link_check_timeout = jiffies;
2175 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2176 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2177 IXGBE_WRITE_FLUSH(hw);
2178 ixgbe_service_event_schedule(adapter);
2179 }
2180 }
2181
2182 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2183 u64 qmask)
2184 {
2185 u32 mask;
2186 struct ixgbe_hw *hw = &adapter->hw;
2187
2188 switch (hw->mac.type) {
2189 case ixgbe_mac_82598EB:
2190 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2191 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2192 break;
2193 case ixgbe_mac_82599EB:
2194 case ixgbe_mac_X540:
2195 mask = (qmask & 0xFFFFFFFF);
2196 if (mask)
2197 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2198 mask = (qmask >> 32);
2199 if (mask)
2200 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2201 break;
2202 default:
2203 break;
2204 }
2205 /* skip the flush */
2206 }
2207
2208 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2209 u64 qmask)
2210 {
2211 u32 mask;
2212 struct ixgbe_hw *hw = &adapter->hw;
2213
2214 switch (hw->mac.type) {
2215 case ixgbe_mac_82598EB:
2216 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2217 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2218 break;
2219 case ixgbe_mac_82599EB:
2220 case ixgbe_mac_X540:
2221 mask = (qmask & 0xFFFFFFFF);
2222 if (mask)
2223 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2224 mask = (qmask >> 32);
2225 if (mask)
2226 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2227 break;
2228 default:
2229 break;
2230 }
2231 /* skip the flush */
2232 }
2233
2234 /**
2235 * ixgbe_irq_enable - Enable default interrupt generation settings
2236 * @adapter: board private structure
2237 **/
2238 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2239 bool flush)
2240 {
2241 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2242
2243 /* don't reenable LSC while waiting for link */
2244 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2245 mask &= ~IXGBE_EIMS_LSC;
2246
2247 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2248 switch (adapter->hw.mac.type) {
2249 case ixgbe_mac_82599EB:
2250 mask |= IXGBE_EIMS_GPI_SDP0;
2251 break;
2252 case ixgbe_mac_X540:
2253 mask |= IXGBE_EIMS_TS;
2254 break;
2255 default:
2256 break;
2257 }
2258 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2259 mask |= IXGBE_EIMS_GPI_SDP1;
2260 switch (adapter->hw.mac.type) {
2261 case ixgbe_mac_82599EB:
2262 mask |= IXGBE_EIMS_GPI_SDP1;
2263 mask |= IXGBE_EIMS_GPI_SDP2;
2264 case ixgbe_mac_X540:
2265 mask |= IXGBE_EIMS_ECC;
2266 mask |= IXGBE_EIMS_MAILBOX;
2267 break;
2268 default:
2269 break;
2270 }
2271 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2272 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2273 mask |= IXGBE_EIMS_FLOW_DIR;
2274
2275 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2276 if (queues)
2277 ixgbe_irq_enable_queues(adapter, ~0);
2278 if (flush)
2279 IXGBE_WRITE_FLUSH(&adapter->hw);
2280 }
2281
2282 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2283 {
2284 struct ixgbe_adapter *adapter = data;
2285 struct ixgbe_hw *hw = &adapter->hw;
2286 u32 eicr;
2287
2288 /*
2289 * Workaround for Silicon errata. Use clear-by-write instead
2290 * of clear-by-read. Reading with EICS will return the
2291 * interrupt causes without clearing, which later be done
2292 * with the write to EICR.
2293 */
2294 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2295 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2296
2297 if (eicr & IXGBE_EICR_LSC)
2298 ixgbe_check_lsc(adapter);
2299
2300 if (eicr & IXGBE_EICR_MAILBOX)
2301 ixgbe_msg_task(adapter);
2302
2303 switch (hw->mac.type) {
2304 case ixgbe_mac_82599EB:
2305 case ixgbe_mac_X540:
2306 if (eicr & IXGBE_EICR_ECC)
2307 e_info(link, "Received unrecoverable ECC Err, please "
2308 "reboot\n");
2309 /* Handle Flow Director Full threshold interrupt */
2310 if (eicr & IXGBE_EICR_FLOW_DIR) {
2311 int reinit_count = 0;
2312 int i;
2313 for (i = 0; i < adapter->num_tx_queues; i++) {
2314 struct ixgbe_ring *ring = adapter->tx_ring[i];
2315 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2316 &ring->state))
2317 reinit_count++;
2318 }
2319 if (reinit_count) {
2320 /* no more flow director interrupts until after init */
2321 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2322 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2323 ixgbe_service_event_schedule(adapter);
2324 }
2325 }
2326 ixgbe_check_sfp_event(adapter, eicr);
2327 ixgbe_check_overtemp_event(adapter, eicr);
2328 break;
2329 default:
2330 break;
2331 }
2332
2333 ixgbe_check_fan_failure(adapter, eicr);
2334 #ifdef CONFIG_IXGBE_PTP
2335 ixgbe_ptp_check_pps_event(adapter, eicr);
2336 #endif
2337
2338 /* re-enable the original interrupt state, no lsc, no queues */
2339 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2340 ixgbe_irq_enable(adapter, false, false);
2341
2342 return IRQ_HANDLED;
2343 }
2344
2345 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2346 {
2347 struct ixgbe_q_vector *q_vector = data;
2348
2349 /* EIAM disabled interrupts (on this vector) for us */
2350
2351 if (q_vector->rx.ring || q_vector->tx.ring)
2352 napi_schedule(&q_vector->napi);
2353
2354 return IRQ_HANDLED;
2355 }
2356
2357 /**
2358 * ixgbe_poll - NAPI Rx polling callback
2359 * @napi: structure for representing this polling device
2360 * @budget: how many packets driver is allowed to clean
2361 *
2362 * This function is used for legacy and MSI, NAPI mode
2363 **/
2364 int ixgbe_poll(struct napi_struct *napi, int budget)
2365 {
2366 struct ixgbe_q_vector *q_vector =
2367 container_of(napi, struct ixgbe_q_vector, napi);
2368 struct ixgbe_adapter *adapter = q_vector->adapter;
2369 struct ixgbe_ring *ring;
2370 int per_ring_budget;
2371 bool clean_complete = true;
2372
2373 #ifdef CONFIG_IXGBE_DCA
2374 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2375 ixgbe_update_dca(q_vector);
2376 #endif
2377
2378 ixgbe_for_each_ring(ring, q_vector->tx)
2379 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2380
2381 /* attempt to distribute budget to each queue fairly, but don't allow
2382 * the budget to go below 1 because we'll exit polling */
2383 if (q_vector->rx.count > 1)
2384 per_ring_budget = max(budget/q_vector->rx.count, 1);
2385 else
2386 per_ring_budget = budget;
2387
2388 ixgbe_for_each_ring(ring, q_vector->rx)
2389 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2390 per_ring_budget);
2391
2392 /* If all work not completed, return budget and keep polling */
2393 if (!clean_complete)
2394 return budget;
2395
2396 /* all work done, exit the polling mode */
2397 napi_complete(napi);
2398 if (adapter->rx_itr_setting & 1)
2399 ixgbe_set_itr(q_vector);
2400 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2401 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2402
2403 return 0;
2404 }
2405
2406 /**
2407 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2408 * @adapter: board private structure
2409 *
2410 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2411 * interrupts from the kernel.
2412 **/
2413 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2414 {
2415 struct net_device *netdev = adapter->netdev;
2416 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2417 int vector, err;
2418 int ri = 0, ti = 0;
2419
2420 for (vector = 0; vector < q_vectors; vector++) {
2421 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2422 struct msix_entry *entry = &adapter->msix_entries[vector];
2423
2424 if (q_vector->tx.ring && q_vector->rx.ring) {
2425 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2426 "%s-%s-%d", netdev->name, "TxRx", ri++);
2427 ti++;
2428 } else if (q_vector->rx.ring) {
2429 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2430 "%s-%s-%d", netdev->name, "rx", ri++);
2431 } else if (q_vector->tx.ring) {
2432 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2433 "%s-%s-%d", netdev->name, "tx", ti++);
2434 } else {
2435 /* skip this unused q_vector */
2436 continue;
2437 }
2438 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2439 q_vector->name, q_vector);
2440 if (err) {
2441 e_err(probe, "request_irq failed for MSIX interrupt "
2442 "Error: %d\n", err);
2443 goto free_queue_irqs;
2444 }
2445 /* If Flow Director is enabled, set interrupt affinity */
2446 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2447 /* assign the mask for this irq */
2448 irq_set_affinity_hint(entry->vector,
2449 &q_vector->affinity_mask);
2450 }
2451 }
2452
2453 err = request_irq(adapter->msix_entries[vector].vector,
2454 ixgbe_msix_other, 0, netdev->name, adapter);
2455 if (err) {
2456 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2457 goto free_queue_irqs;
2458 }
2459
2460 return 0;
2461
2462 free_queue_irqs:
2463 while (vector) {
2464 vector--;
2465 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2466 NULL);
2467 free_irq(adapter->msix_entries[vector].vector,
2468 adapter->q_vector[vector]);
2469 }
2470 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2471 pci_disable_msix(adapter->pdev);
2472 kfree(adapter->msix_entries);
2473 adapter->msix_entries = NULL;
2474 return err;
2475 }
2476
2477 /**
2478 * ixgbe_intr - legacy mode Interrupt Handler
2479 * @irq: interrupt number
2480 * @data: pointer to a network interface device structure
2481 **/
2482 static irqreturn_t ixgbe_intr(int irq, void *data)
2483 {
2484 struct ixgbe_adapter *adapter = data;
2485 struct ixgbe_hw *hw = &adapter->hw;
2486 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2487 u32 eicr;
2488
2489 /*
2490 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2491 * before the read of EICR.
2492 */
2493 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2494
2495 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2496 * therefore no explicit interrupt disable is necessary */
2497 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2498 if (!eicr) {
2499 /*
2500 * shared interrupt alert!
2501 * make sure interrupts are enabled because the read will
2502 * have disabled interrupts due to EIAM
2503 * finish the workaround of silicon errata on 82598. Unmask
2504 * the interrupt that we masked before the EICR read.
2505 */
2506 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2507 ixgbe_irq_enable(adapter, true, true);
2508 return IRQ_NONE; /* Not our interrupt */
2509 }
2510
2511 if (eicr & IXGBE_EICR_LSC)
2512 ixgbe_check_lsc(adapter);
2513
2514 switch (hw->mac.type) {
2515 case ixgbe_mac_82599EB:
2516 ixgbe_check_sfp_event(adapter, eicr);
2517 /* Fall through */
2518 case ixgbe_mac_X540:
2519 if (eicr & IXGBE_EICR_ECC)
2520 e_info(link, "Received unrecoverable ECC err, please "
2521 "reboot\n");
2522 ixgbe_check_overtemp_event(adapter, eicr);
2523 break;
2524 default:
2525 break;
2526 }
2527
2528 ixgbe_check_fan_failure(adapter, eicr);
2529 #ifdef CONFIG_IXGBE_PTP
2530 ixgbe_ptp_check_pps_event(adapter, eicr);
2531 #endif
2532
2533 /* would disable interrupts here but EIAM disabled it */
2534 napi_schedule(&q_vector->napi);
2535
2536 /*
2537 * re-enable link(maybe) and non-queue interrupts, no flush.
2538 * ixgbe_poll will re-enable the queue interrupts
2539 */
2540 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2541 ixgbe_irq_enable(adapter, false, false);
2542
2543 return IRQ_HANDLED;
2544 }
2545
2546 /**
2547 * ixgbe_request_irq - initialize interrupts
2548 * @adapter: board private structure
2549 *
2550 * Attempts to configure interrupts using the best available
2551 * capabilities of the hardware and kernel.
2552 **/
2553 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2554 {
2555 struct net_device *netdev = adapter->netdev;
2556 int err;
2557
2558 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2559 err = ixgbe_request_msix_irqs(adapter);
2560 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2561 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2562 netdev->name, adapter);
2563 else
2564 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2565 netdev->name, adapter);
2566
2567 if (err)
2568 e_err(probe, "request_irq failed, Error %d\n", err);
2569
2570 return err;
2571 }
2572
2573 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2574 {
2575 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2576 int i, q_vectors;
2577
2578 q_vectors = adapter->num_msix_vectors;
2579 i = q_vectors - 1;
2580 free_irq(adapter->msix_entries[i].vector, adapter);
2581 i--;
2582
2583 for (; i >= 0; i--) {
2584 /* free only the irqs that were actually requested */
2585 if (!adapter->q_vector[i]->rx.ring &&
2586 !adapter->q_vector[i]->tx.ring)
2587 continue;
2588
2589 /* clear the affinity_mask in the IRQ descriptor */
2590 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2591 NULL);
2592
2593 free_irq(adapter->msix_entries[i].vector,
2594 adapter->q_vector[i]);
2595 }
2596 } else {
2597 free_irq(adapter->pdev->irq, adapter);
2598 }
2599 }
2600
2601 /**
2602 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2603 * @adapter: board private structure
2604 **/
2605 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2606 {
2607 switch (adapter->hw.mac.type) {
2608 case ixgbe_mac_82598EB:
2609 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2610 break;
2611 case ixgbe_mac_82599EB:
2612 case ixgbe_mac_X540:
2613 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2614 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2615 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2616 break;
2617 default:
2618 break;
2619 }
2620 IXGBE_WRITE_FLUSH(&adapter->hw);
2621 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2622 int i;
2623 for (i = 0; i < adapter->num_msix_vectors; i++)
2624 synchronize_irq(adapter->msix_entries[i].vector);
2625 } else {
2626 synchronize_irq(adapter->pdev->irq);
2627 }
2628 }
2629
2630 /**
2631 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2632 *
2633 **/
2634 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2635 {
2636 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2637
2638 /* rx/tx vector */
2639 if (adapter->rx_itr_setting == 1)
2640 q_vector->itr = IXGBE_20K_ITR;
2641 else
2642 q_vector->itr = adapter->rx_itr_setting;
2643
2644 ixgbe_write_eitr(q_vector);
2645
2646 ixgbe_set_ivar(adapter, 0, 0, 0);
2647 ixgbe_set_ivar(adapter, 1, 0, 0);
2648
2649 e_info(hw, "Legacy interrupt IVAR setup done\n");
2650 }
2651
2652 /**
2653 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2654 * @adapter: board private structure
2655 * @ring: structure containing ring specific data
2656 *
2657 * Configure the Tx descriptor ring after a reset.
2658 **/
2659 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2660 struct ixgbe_ring *ring)
2661 {
2662 struct ixgbe_hw *hw = &adapter->hw;
2663 u64 tdba = ring->dma;
2664 int wait_loop = 10;
2665 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2666 u8 reg_idx = ring->reg_idx;
2667
2668 /* disable queue to avoid issues while updating state */
2669 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2670 IXGBE_WRITE_FLUSH(hw);
2671
2672 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2673 (tdba & DMA_BIT_MASK(32)));
2674 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2675 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2676 ring->count * sizeof(union ixgbe_adv_tx_desc));
2677 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2678 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2679 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2680
2681 /*
2682 * set WTHRESH to encourage burst writeback, it should not be set
2683 * higher than 1 when ITR is 0 as it could cause false TX hangs
2684 *
2685 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2686 * to or less than the number of on chip descriptors, which is
2687 * currently 40.
2688 */
2689 if (!ring->q_vector || (ring->q_vector->itr < 8))
2690 txdctl |= (1 << 16); /* WTHRESH = 1 */
2691 else
2692 txdctl |= (8 << 16); /* WTHRESH = 8 */
2693
2694 /*
2695 * Setting PTHRESH to 32 both improves performance
2696 * and avoids a TX hang with DFP enabled
2697 */
2698 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2699 32; /* PTHRESH = 32 */
2700
2701 /* reinitialize flowdirector state */
2702 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2703 adapter->atr_sample_rate) {
2704 ring->atr_sample_rate = adapter->atr_sample_rate;
2705 ring->atr_count = 0;
2706 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2707 } else {
2708 ring->atr_sample_rate = 0;
2709 }
2710
2711 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2712
2713 /* enable queue */
2714 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2715
2716 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2717 if (hw->mac.type == ixgbe_mac_82598EB &&
2718 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2719 return;
2720
2721 /* poll to verify queue is enabled */
2722 do {
2723 usleep_range(1000, 2000);
2724 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2725 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2726 if (!wait_loop)
2727 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2728 }
2729
2730 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2731 {
2732 struct ixgbe_hw *hw = &adapter->hw;
2733 u32 rttdcs;
2734 u32 reg;
2735 u8 tcs = netdev_get_num_tc(adapter->netdev);
2736
2737 if (hw->mac.type == ixgbe_mac_82598EB)
2738 return;
2739
2740 /* disable the arbiter while setting MTQC */
2741 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2742 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2743 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2744
2745 /* set transmit pool layout */
2746 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2747 case (IXGBE_FLAG_SRIOV_ENABLED):
2748 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2749 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2750 break;
2751 default:
2752 if (!tcs)
2753 reg = IXGBE_MTQC_64Q_1PB;
2754 else if (tcs <= 4)
2755 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2756 else
2757 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2758
2759 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2760
2761 /* Enable Security TX Buffer IFG for multiple pb */
2762 if (tcs) {
2763 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2764 reg |= IXGBE_SECTX_DCB;
2765 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2766 }
2767 break;
2768 }
2769
2770 /* re-enable the arbiter */
2771 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2772 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2773 }
2774
2775 /**
2776 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2777 * @adapter: board private structure
2778 *
2779 * Configure the Tx unit of the MAC after a reset.
2780 **/
2781 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2782 {
2783 struct ixgbe_hw *hw = &adapter->hw;
2784 u32 dmatxctl;
2785 u32 i;
2786
2787 ixgbe_setup_mtqc(adapter);
2788
2789 if (hw->mac.type != ixgbe_mac_82598EB) {
2790 /* DMATXCTL.EN must be before Tx queues are enabled */
2791 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2792 dmatxctl |= IXGBE_DMATXCTL_TE;
2793 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2794 }
2795
2796 /* Setup the HW Tx Head and Tail descriptor pointers */
2797 for (i = 0; i < adapter->num_tx_queues; i++)
2798 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2799 }
2800
2801 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2802 struct ixgbe_ring *ring)
2803 {
2804 struct ixgbe_hw *hw = &adapter->hw;
2805 u8 reg_idx = ring->reg_idx;
2806 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2807
2808 srrctl |= IXGBE_SRRCTL_DROP_EN;
2809
2810 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2811 }
2812
2813 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2814 struct ixgbe_ring *ring)
2815 {
2816 struct ixgbe_hw *hw = &adapter->hw;
2817 u8 reg_idx = ring->reg_idx;
2818 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2819
2820 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2821
2822 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2823 }
2824
2825 #ifdef CONFIG_IXGBE_DCB
2826 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2827 #else
2828 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2829 #endif
2830 {
2831 int i;
2832 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2833
2834 if (adapter->ixgbe_ieee_pfc)
2835 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2836
2837 /*
2838 * We should set the drop enable bit if:
2839 * SR-IOV is enabled
2840 * or
2841 * Number of Rx queues > 1 and flow control is disabled
2842 *
2843 * This allows us to avoid head of line blocking for security
2844 * and performance reasons.
2845 */
2846 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2847 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2848 for (i = 0; i < adapter->num_rx_queues; i++)
2849 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2850 } else {
2851 for (i = 0; i < adapter->num_rx_queues; i++)
2852 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2853 }
2854 }
2855
2856 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2857
2858 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2859 struct ixgbe_ring *rx_ring)
2860 {
2861 u32 srrctl;
2862 u8 reg_idx = rx_ring->reg_idx;
2863
2864 switch (adapter->hw.mac.type) {
2865 case ixgbe_mac_82598EB: {
2866 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2867 const int mask = feature[RING_F_RSS].mask;
2868 reg_idx = reg_idx & mask;
2869 }
2870 break;
2871 case ixgbe_mac_82599EB:
2872 case ixgbe_mac_X540:
2873 default:
2874 break;
2875 }
2876
2877 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2878
2879 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2880 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2881 if (adapter->num_vfs)
2882 srrctl |= IXGBE_SRRCTL_DROP_EN;
2883
2884 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2885 IXGBE_SRRCTL_BSIZEHDR_MASK;
2886
2887 #if PAGE_SIZE > IXGBE_MAX_RXBUFFER
2888 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2889 #else
2890 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2891 #endif
2892 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2893
2894 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2895 }
2896
2897 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2898 {
2899 struct ixgbe_hw *hw = &adapter->hw;
2900 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2901 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2902 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2903 u32 mrqc = 0, reta = 0;
2904 u32 rxcsum;
2905 int i, j;
2906 u8 tcs = netdev_get_num_tc(adapter->netdev);
2907 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2908
2909 if (tcs)
2910 maxq = min(maxq, adapter->num_tx_queues / tcs);
2911
2912 /* Fill out hash function seeds */
2913 for (i = 0; i < 10; i++)
2914 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2915
2916 /* Fill out redirection table */
2917 for (i = 0, j = 0; i < 128; i++, j++) {
2918 if (j == maxq)
2919 j = 0;
2920 /* reta = 4-byte sliding window of
2921 * 0x00..(indices-1)(indices-1)00..etc. */
2922 reta = (reta << 8) | (j * 0x11);
2923 if ((i & 3) == 3)
2924 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2925 }
2926
2927 /* Disable indicating checksum in descriptor, enables RSS hash */
2928 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2929 rxcsum |= IXGBE_RXCSUM_PCSD;
2930 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2931
2932 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2933 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2934 mrqc = IXGBE_MRQC_RSSEN;
2935 } else {
2936 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2937 | IXGBE_FLAG_SRIOV_ENABLED);
2938
2939 switch (mask) {
2940 case (IXGBE_FLAG_RSS_ENABLED):
2941 if (!tcs)
2942 mrqc = IXGBE_MRQC_RSSEN;
2943 else if (tcs <= 4)
2944 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2945 else
2946 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2947 break;
2948 case (IXGBE_FLAG_SRIOV_ENABLED):
2949 mrqc = IXGBE_MRQC_VMDQEN;
2950 break;
2951 default:
2952 break;
2953 }
2954 }
2955
2956 /* Perform hash on these packet types */
2957 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2958 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2959 | IXGBE_MRQC_RSS_FIELD_IPV6
2960 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2961
2962 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2963 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2964 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2965 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2966
2967 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2968 }
2969
2970 /**
2971 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2972 * @adapter: address of board private structure
2973 * @index: index of ring to set
2974 **/
2975 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2976 struct ixgbe_ring *ring)
2977 {
2978 struct ixgbe_hw *hw = &adapter->hw;
2979 u32 rscctrl;
2980 u8 reg_idx = ring->reg_idx;
2981
2982 if (!ring_is_rsc_enabled(ring))
2983 return;
2984
2985 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2986 rscctrl |= IXGBE_RSCCTL_RSCEN;
2987 /*
2988 * we must limit the number of descriptors so that the
2989 * total size of max desc * buf_len is not greater
2990 * than 65536
2991 */
2992 #if (PAGE_SIZE <= 8192)
2993 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2994 #elif (PAGE_SIZE <= 16384)
2995 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2996 #else
2997 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2998 #endif
2999 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3000 }
3001
3002 #define IXGBE_MAX_RX_DESC_POLL 10
3003 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3004 struct ixgbe_ring *ring)
3005 {
3006 struct ixgbe_hw *hw = &adapter->hw;
3007 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3008 u32 rxdctl;
3009 u8 reg_idx = ring->reg_idx;
3010
3011 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3012 if (hw->mac.type == ixgbe_mac_82598EB &&
3013 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3014 return;
3015
3016 do {
3017 usleep_range(1000, 2000);
3018 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3019 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3020
3021 if (!wait_loop) {
3022 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3023 "the polling period\n", reg_idx);
3024 }
3025 }
3026
3027 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3028 struct ixgbe_ring *ring)
3029 {
3030 struct ixgbe_hw *hw = &adapter->hw;
3031 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3032 u32 rxdctl;
3033 u8 reg_idx = ring->reg_idx;
3034
3035 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3036 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3037
3038 /* write value back with RXDCTL.ENABLE bit cleared */
3039 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3040
3041 if (hw->mac.type == ixgbe_mac_82598EB &&
3042 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3043 return;
3044
3045 /* the hardware may take up to 100us to really disable the rx queue */
3046 do {
3047 udelay(10);
3048 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3049 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3050
3051 if (!wait_loop) {
3052 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3053 "the polling period\n", reg_idx);
3054 }
3055 }
3056
3057 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3058 struct ixgbe_ring *ring)
3059 {
3060 struct ixgbe_hw *hw = &adapter->hw;
3061 u64 rdba = ring->dma;
3062 u32 rxdctl;
3063 u8 reg_idx = ring->reg_idx;
3064
3065 /* disable queue to avoid issues while updating state */
3066 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3067 ixgbe_disable_rx_queue(adapter, ring);
3068
3069 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3070 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3071 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3072 ring->count * sizeof(union ixgbe_adv_rx_desc));
3073 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3074 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3075 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3076
3077 ixgbe_configure_srrctl(adapter, ring);
3078 ixgbe_configure_rscctl(adapter, ring);
3079
3080 /* If operating in IOV mode set RLPML for X540 */
3081 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3082 hw->mac.type == ixgbe_mac_X540) {
3083 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3084 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3085 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3086 }
3087
3088 if (hw->mac.type == ixgbe_mac_82598EB) {
3089 /*
3090 * enable cache line friendly hardware writes:
3091 * PTHRESH=32 descriptors (half the internal cache),
3092 * this also removes ugly rx_no_buffer_count increment
3093 * HTHRESH=4 descriptors (to minimize latency on fetch)
3094 * WTHRESH=8 burst writeback up to two cache lines
3095 */
3096 rxdctl &= ~0x3FFFFF;
3097 rxdctl |= 0x080420;
3098 }
3099
3100 /* enable receive descriptor ring */
3101 rxdctl |= IXGBE_RXDCTL_ENABLE;
3102 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3103
3104 ixgbe_rx_desc_queue_enable(adapter, ring);
3105 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3106 }
3107
3108 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3109 {
3110 struct ixgbe_hw *hw = &adapter->hw;
3111 int p;
3112
3113 /* PSRTYPE must be initialized in non 82598 adapters */
3114 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3115 IXGBE_PSRTYPE_UDPHDR |
3116 IXGBE_PSRTYPE_IPV4HDR |
3117 IXGBE_PSRTYPE_L2HDR |
3118 IXGBE_PSRTYPE_IPV6HDR;
3119
3120 if (hw->mac.type == ixgbe_mac_82598EB)
3121 return;
3122
3123 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3124 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3125
3126 for (p = 0; p < adapter->num_rx_pools; p++)
3127 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3128 psrtype);
3129 }
3130
3131 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3132 {
3133 struct ixgbe_hw *hw = &adapter->hw;
3134 u32 gcr_ext;
3135 u32 vt_reg_bits;
3136 u32 reg_offset, vf_shift;
3137 u32 vmdctl;
3138 int i;
3139
3140 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3141 return;
3142
3143 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3144 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3145 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3146 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3147
3148 vf_shift = adapter->num_vfs % 32;
3149 reg_offset = (adapter->num_vfs >= 32) ? 1 : 0;
3150
3151 /* Enable only the PF's pool for Tx/Rx */
3152 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3153 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3154 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3155 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3156 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3157
3158 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3159 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3160
3161 /*
3162 * Set up VF register offsets for selected VT Mode,
3163 * i.e. 32 or 64 VFs for SR-IOV
3164 */
3165 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3166 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3167 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3168 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3169
3170 /* enable Tx loopback for VF/PF communication */
3171 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3172 /* Enable MAC Anti-Spoofing */
3173 hw->mac.ops.set_mac_anti_spoofing(hw,
3174 (adapter->num_vfs != 0),
3175 adapter->num_vfs);
3176 /* For VFs that have spoof checking turned off */
3177 for (i = 0; i < adapter->num_vfs; i++) {
3178 if (!adapter->vfinfo[i].spoofchk_enabled)
3179 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3180 }
3181 }
3182
3183 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3184 {
3185 struct ixgbe_hw *hw = &adapter->hw;
3186 struct net_device *netdev = adapter->netdev;
3187 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3188 struct ixgbe_ring *rx_ring;
3189 int i;
3190 u32 mhadd, hlreg0;
3191
3192 #ifdef IXGBE_FCOE
3193 /* adjust max frame to be able to do baby jumbo for FCoE */
3194 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3195 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3196 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3197
3198 #endif /* IXGBE_FCOE */
3199 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3200 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3201 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3202 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3203
3204 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3205 }
3206
3207 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3208 max_frame += VLAN_HLEN;
3209
3210 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3211 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3212 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3213 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3214
3215 /*
3216 * Setup the HW Rx Head and Tail Descriptor Pointers and
3217 * the Base and Length of the Rx Descriptor Ring
3218 */
3219 for (i = 0; i < adapter->num_rx_queues; i++) {
3220 rx_ring = adapter->rx_ring[i];
3221 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3222 set_ring_rsc_enabled(rx_ring);
3223 else
3224 clear_ring_rsc_enabled(rx_ring);
3225 }
3226 }
3227
3228 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3229 {
3230 struct ixgbe_hw *hw = &adapter->hw;
3231 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3232
3233 switch (hw->mac.type) {
3234 case ixgbe_mac_82598EB:
3235 /*
3236 * For VMDq support of different descriptor types or
3237 * buffer sizes through the use of multiple SRRCTL
3238 * registers, RDRXCTL.MVMEN must be set to 1
3239 *
3240 * also, the manual doesn't mention it clearly but DCA hints
3241 * will only use queue 0's tags unless this bit is set. Side
3242 * effects of setting this bit are only that SRRCTL must be
3243 * fully programmed [0..15]
3244 */
3245 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3246 break;
3247 case ixgbe_mac_82599EB:
3248 case ixgbe_mac_X540:
3249 /* Disable RSC for ACK packets */
3250 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3251 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3252 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3253 /* hardware requires some bits to be set by default */
3254 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3255 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3256 break;
3257 default:
3258 /* We should do nothing since we don't know this hardware */
3259 return;
3260 }
3261
3262 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3263 }
3264
3265 /**
3266 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3267 * @adapter: board private structure
3268 *
3269 * Configure the Rx unit of the MAC after a reset.
3270 **/
3271 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3272 {
3273 struct ixgbe_hw *hw = &adapter->hw;
3274 int i;
3275 u32 rxctrl;
3276
3277 /* disable receives while setting up the descriptors */
3278 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3279 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3280
3281 ixgbe_setup_psrtype(adapter);
3282 ixgbe_setup_rdrxctl(adapter);
3283
3284 /* Program registers for the distribution of queues */
3285 ixgbe_setup_mrqc(adapter);
3286
3287 /* set_rx_buffer_len must be called before ring initialization */
3288 ixgbe_set_rx_buffer_len(adapter);
3289
3290 /*
3291 * Setup the HW Rx Head and Tail Descriptor Pointers and
3292 * the Base and Length of the Rx Descriptor Ring
3293 */
3294 for (i = 0; i < adapter->num_rx_queues; i++)
3295 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3296
3297 /* disable drop enable for 82598 parts */
3298 if (hw->mac.type == ixgbe_mac_82598EB)
3299 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3300
3301 /* enable all receives */
3302 rxctrl |= IXGBE_RXCTRL_RXEN;
3303 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3304 }
3305
3306 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3307 {
3308 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3309 struct ixgbe_hw *hw = &adapter->hw;
3310 int pool_ndx = adapter->num_vfs;
3311
3312 /* add VID to filter table */
3313 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3314 set_bit(vid, adapter->active_vlans);
3315
3316 return 0;
3317 }
3318
3319 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3320 {
3321 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3322 struct ixgbe_hw *hw = &adapter->hw;
3323 int pool_ndx = adapter->num_vfs;
3324
3325 /* remove VID from filter table */
3326 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3327 clear_bit(vid, adapter->active_vlans);
3328
3329 return 0;
3330 }
3331
3332 /**
3333 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3334 * @adapter: driver data
3335 */
3336 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3337 {
3338 struct ixgbe_hw *hw = &adapter->hw;
3339 u32 vlnctrl;
3340
3341 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3342 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3343 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3344 }
3345
3346 /**
3347 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3348 * @adapter: driver data
3349 */
3350 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3351 {
3352 struct ixgbe_hw *hw = &adapter->hw;
3353 u32 vlnctrl;
3354
3355 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3356 vlnctrl |= IXGBE_VLNCTRL_VFE;
3357 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3358 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3359 }
3360
3361 /**
3362 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3363 * @adapter: driver data
3364 */
3365 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3366 {
3367 struct ixgbe_hw *hw = &adapter->hw;
3368 u32 vlnctrl;
3369 int i, j;
3370
3371 switch (hw->mac.type) {
3372 case ixgbe_mac_82598EB:
3373 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3374 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3375 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3376 break;
3377 case ixgbe_mac_82599EB:
3378 case ixgbe_mac_X540:
3379 for (i = 0; i < adapter->num_rx_queues; i++) {
3380 j = adapter->rx_ring[i]->reg_idx;
3381 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3382 vlnctrl &= ~IXGBE_RXDCTL_VME;
3383 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3384 }
3385 break;
3386 default:
3387 break;
3388 }
3389 }
3390
3391 /**
3392 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3393 * @adapter: driver data
3394 */
3395 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3396 {
3397 struct ixgbe_hw *hw = &adapter->hw;
3398 u32 vlnctrl;
3399 int i, j;
3400
3401 switch (hw->mac.type) {
3402 case ixgbe_mac_82598EB:
3403 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3404 vlnctrl |= IXGBE_VLNCTRL_VME;
3405 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3406 break;
3407 case ixgbe_mac_82599EB:
3408 case ixgbe_mac_X540:
3409 for (i = 0; i < adapter->num_rx_queues; i++) {
3410 j = adapter->rx_ring[i]->reg_idx;
3411 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3412 vlnctrl |= IXGBE_RXDCTL_VME;
3413 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3414 }
3415 break;
3416 default:
3417 break;
3418 }
3419 }
3420
3421 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3422 {
3423 u16 vid;
3424
3425 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3426
3427 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3428 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3429 }
3430
3431 /**
3432 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3433 * @netdev: network interface device structure
3434 *
3435 * Writes unicast address list to the RAR table.
3436 * Returns: -ENOMEM on failure/insufficient address space
3437 * 0 on no addresses written
3438 * X on writing X addresses to the RAR table
3439 **/
3440 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3441 {
3442 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3443 struct ixgbe_hw *hw = &adapter->hw;
3444 unsigned int vfn = adapter->num_vfs;
3445 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3446 int count = 0;
3447
3448 /* return ENOMEM indicating insufficient memory for addresses */
3449 if (netdev_uc_count(netdev) > rar_entries)
3450 return -ENOMEM;
3451
3452 if (!netdev_uc_empty(netdev) && rar_entries) {
3453 struct netdev_hw_addr *ha;
3454 /* return error if we do not support writing to RAR table */
3455 if (!hw->mac.ops.set_rar)
3456 return -ENOMEM;
3457
3458 netdev_for_each_uc_addr(ha, netdev) {
3459 if (!rar_entries)
3460 break;
3461 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3462 vfn, IXGBE_RAH_AV);
3463 count++;
3464 }
3465 }
3466 /* write the addresses in reverse order to avoid write combining */
3467 for (; rar_entries > 0 ; rar_entries--)
3468 hw->mac.ops.clear_rar(hw, rar_entries);
3469
3470 return count;
3471 }
3472
3473 /**
3474 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3475 * @netdev: network interface device structure
3476 *
3477 * The set_rx_method entry point is called whenever the unicast/multicast
3478 * address list or the network interface flags are updated. This routine is
3479 * responsible for configuring the hardware for proper unicast, multicast and
3480 * promiscuous mode.
3481 **/
3482 void ixgbe_set_rx_mode(struct net_device *netdev)
3483 {
3484 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3485 struct ixgbe_hw *hw = &adapter->hw;
3486 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3487 int count;
3488
3489 /* Check for Promiscuous and All Multicast modes */
3490
3491 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3492
3493 /* set all bits that we expect to always be set */
3494 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3495 fctrl |= IXGBE_FCTRL_BAM;
3496 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3497 fctrl |= IXGBE_FCTRL_PMCF;
3498
3499 /* clear the bits we are changing the status of */
3500 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3501
3502 if (netdev->flags & IFF_PROMISC) {
3503 hw->addr_ctrl.user_set_promisc = true;
3504 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3505 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3506 /* don't hardware filter vlans in promisc mode */
3507 ixgbe_vlan_filter_disable(adapter);
3508 } else {
3509 if (netdev->flags & IFF_ALLMULTI) {
3510 fctrl |= IXGBE_FCTRL_MPE;
3511 vmolr |= IXGBE_VMOLR_MPE;
3512 } else {
3513 /*
3514 * Write addresses to the MTA, if the attempt fails
3515 * then we should just turn on promiscuous mode so
3516 * that we can at least receive multicast traffic
3517 */
3518 hw->mac.ops.update_mc_addr_list(hw, netdev);
3519 vmolr |= IXGBE_VMOLR_ROMPE;
3520 }
3521 ixgbe_vlan_filter_enable(adapter);
3522 hw->addr_ctrl.user_set_promisc = false;
3523 }
3524
3525 /*
3526 * Write addresses to available RAR registers, if there is not
3527 * sufficient space to store all the addresses then enable
3528 * unicast promiscuous mode
3529 */
3530 count = ixgbe_write_uc_addr_list(netdev);
3531 if (count < 0) {
3532 fctrl |= IXGBE_FCTRL_UPE;
3533 vmolr |= IXGBE_VMOLR_ROPE;
3534 }
3535
3536 if (adapter->num_vfs) {
3537 ixgbe_restore_vf_multicasts(adapter);
3538 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3539 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3540 IXGBE_VMOLR_ROPE);
3541 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3542 }
3543
3544 /* This is useful for sniffing bad packets. */
3545 if (adapter->netdev->features & NETIF_F_RXALL) {
3546 /* UPE and MPE will be handled by normal PROMISC logic
3547 * in e1000e_set_rx_mode */
3548 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3549 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3550 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3551
3552 fctrl &= ~(IXGBE_FCTRL_DPF);
3553 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3554 }
3555
3556 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3557
3558 if (netdev->features & NETIF_F_HW_VLAN_RX)
3559 ixgbe_vlan_strip_enable(adapter);
3560 else
3561 ixgbe_vlan_strip_disable(adapter);
3562 }
3563
3564 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3565 {
3566 int q_idx;
3567 struct ixgbe_q_vector *q_vector;
3568 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3569
3570 /* legacy and MSI only use one vector */
3571 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3572 q_vectors = 1;
3573
3574 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3575 q_vector = adapter->q_vector[q_idx];
3576 napi_enable(&q_vector->napi);
3577 }
3578 }
3579
3580 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3581 {
3582 int q_idx;
3583 struct ixgbe_q_vector *q_vector;
3584 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3585
3586 /* legacy and MSI only use one vector */
3587 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3588 q_vectors = 1;
3589
3590 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3591 q_vector = adapter->q_vector[q_idx];
3592 napi_disable(&q_vector->napi);
3593 }
3594 }
3595
3596 #ifdef CONFIG_IXGBE_DCB
3597 /*
3598 * ixgbe_configure_dcb - Configure DCB hardware
3599 * @adapter: ixgbe adapter struct
3600 *
3601 * This is called by the driver on open to configure the DCB hardware.
3602 * This is also called by the gennetlink interface when reconfiguring
3603 * the DCB state.
3604 */
3605 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3606 {
3607 struct ixgbe_hw *hw = &adapter->hw;
3608 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3609
3610 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3611 if (hw->mac.type == ixgbe_mac_82598EB)
3612 netif_set_gso_max_size(adapter->netdev, 65536);
3613 return;
3614 }
3615
3616 if (hw->mac.type == ixgbe_mac_82598EB)
3617 netif_set_gso_max_size(adapter->netdev, 32768);
3618
3619 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3620
3621 #ifdef IXGBE_FCOE
3622 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3623 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3624 #endif
3625
3626 /* reconfigure the hardware */
3627 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3628 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3629 DCB_TX_CONFIG);
3630 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3631 DCB_RX_CONFIG);
3632 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3633 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3634 ixgbe_dcb_hw_ets(&adapter->hw,
3635 adapter->ixgbe_ieee_ets,
3636 max_frame);
3637 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3638 adapter->ixgbe_ieee_pfc->pfc_en,
3639 adapter->ixgbe_ieee_ets->prio_tc);
3640 }
3641
3642 /* Enable RSS Hash per TC */
3643 if (hw->mac.type != ixgbe_mac_82598EB) {
3644 int i;
3645 u32 reg = 0;
3646
3647 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3648 u8 msb = 0;
3649 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3650
3651 while (cnt >>= 1)
3652 msb++;
3653
3654 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3655 }
3656 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3657 }
3658 }
3659 #endif
3660
3661 /* Additional bittime to account for IXGBE framing */
3662 #define IXGBE_ETH_FRAMING 20
3663
3664 /*
3665 * ixgbe_hpbthresh - calculate high water mark for flow control
3666 *
3667 * @adapter: board private structure to calculate for
3668 * @pb - packet buffer to calculate
3669 */
3670 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3671 {
3672 struct ixgbe_hw *hw = &adapter->hw;
3673 struct net_device *dev = adapter->netdev;
3674 int link, tc, kb, marker;
3675 u32 dv_id, rx_pba;
3676
3677 /* Calculate max LAN frame size */
3678 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3679
3680 #ifdef IXGBE_FCOE
3681 /* FCoE traffic class uses FCOE jumbo frames */
3682 if (dev->features & NETIF_F_FCOE_MTU) {
3683 int fcoe_pb = 0;
3684
3685 #ifdef CONFIG_IXGBE_DCB
3686 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3687
3688 #endif
3689 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3690 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3691 }
3692 #endif
3693
3694 /* Calculate delay value for device */
3695 switch (hw->mac.type) {
3696 case ixgbe_mac_X540:
3697 dv_id = IXGBE_DV_X540(link, tc);
3698 break;
3699 default:
3700 dv_id = IXGBE_DV(link, tc);
3701 break;
3702 }
3703
3704 /* Loopback switch introduces additional latency */
3705 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3706 dv_id += IXGBE_B2BT(tc);
3707
3708 /* Delay value is calculated in bit times convert to KB */
3709 kb = IXGBE_BT2KB(dv_id);
3710 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3711
3712 marker = rx_pba - kb;
3713
3714 /* It is possible that the packet buffer is not large enough
3715 * to provide required headroom. In this case throw an error
3716 * to user and a do the best we can.
3717 */
3718 if (marker < 0) {
3719 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3720 "headroom to support flow control."
3721 "Decrease MTU or number of traffic classes\n", pb);
3722 marker = tc + 1;
3723 }
3724
3725 return marker;
3726 }
3727
3728 /*
3729 * ixgbe_lpbthresh - calculate low water mark for for flow control
3730 *
3731 * @adapter: board private structure to calculate for
3732 * @pb - packet buffer to calculate
3733 */
3734 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3735 {
3736 struct ixgbe_hw *hw = &adapter->hw;
3737 struct net_device *dev = adapter->netdev;
3738 int tc;
3739 u32 dv_id;
3740
3741 /* Calculate max LAN frame size */
3742 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3743
3744 /* Calculate delay value for device */
3745 switch (hw->mac.type) {
3746 case ixgbe_mac_X540:
3747 dv_id = IXGBE_LOW_DV_X540(tc);
3748 break;
3749 default:
3750 dv_id = IXGBE_LOW_DV(tc);
3751 break;
3752 }
3753
3754 /* Delay value is calculated in bit times convert to KB */
3755 return IXGBE_BT2KB(dv_id);
3756 }
3757
3758 /*
3759 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3760 */
3761 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3762 {
3763 struct ixgbe_hw *hw = &adapter->hw;
3764 int num_tc = netdev_get_num_tc(adapter->netdev);
3765 int i;
3766
3767 if (!num_tc)
3768 num_tc = 1;
3769
3770 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3771
3772 for (i = 0; i < num_tc; i++) {
3773 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3774
3775 /* Low water marks must not be larger than high water marks */
3776 if (hw->fc.low_water > hw->fc.high_water[i])
3777 hw->fc.low_water = 0;
3778 }
3779 }
3780
3781 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3782 {
3783 struct ixgbe_hw *hw = &adapter->hw;
3784 int hdrm;
3785 u8 tc = netdev_get_num_tc(adapter->netdev);
3786
3787 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3788 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3789 hdrm = 32 << adapter->fdir_pballoc;
3790 else
3791 hdrm = 0;
3792
3793 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3794 ixgbe_pbthresh_setup(adapter);
3795 }
3796
3797 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3798 {
3799 struct ixgbe_hw *hw = &adapter->hw;
3800 struct hlist_node *node, *node2;
3801 struct ixgbe_fdir_filter *filter;
3802
3803 spin_lock(&adapter->fdir_perfect_lock);
3804
3805 if (!hlist_empty(&adapter->fdir_filter_list))
3806 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3807
3808 hlist_for_each_entry_safe(filter, node, node2,
3809 &adapter->fdir_filter_list, fdir_node) {
3810 ixgbe_fdir_write_perfect_filter_82599(hw,
3811 &filter->filter,
3812 filter->sw_idx,
3813 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3814 IXGBE_FDIR_DROP_QUEUE :
3815 adapter->rx_ring[filter->action]->reg_idx);
3816 }
3817
3818 spin_unlock(&adapter->fdir_perfect_lock);
3819 }
3820
3821 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3822 {
3823 struct ixgbe_hw *hw = &adapter->hw;
3824
3825 ixgbe_configure_pb(adapter);
3826 #ifdef CONFIG_IXGBE_DCB
3827 ixgbe_configure_dcb(adapter);
3828 #endif
3829
3830 ixgbe_set_rx_mode(adapter->netdev);
3831 ixgbe_restore_vlan(adapter);
3832
3833 #ifdef IXGBE_FCOE
3834 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3835 ixgbe_configure_fcoe(adapter);
3836
3837 #endif /* IXGBE_FCOE */
3838
3839 switch (hw->mac.type) {
3840 case ixgbe_mac_82599EB:
3841 case ixgbe_mac_X540:
3842 hw->mac.ops.disable_rx_buff(hw);
3843 break;
3844 default:
3845 break;
3846 }
3847
3848 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3849 ixgbe_init_fdir_signature_82599(&adapter->hw,
3850 adapter->fdir_pballoc);
3851 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3852 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3853 adapter->fdir_pballoc);
3854 ixgbe_fdir_filter_restore(adapter);
3855 }
3856
3857 switch (hw->mac.type) {
3858 case ixgbe_mac_82599EB:
3859 case ixgbe_mac_X540:
3860 hw->mac.ops.enable_rx_buff(hw);
3861 break;
3862 default:
3863 break;
3864 }
3865
3866 ixgbe_configure_virtualization(adapter);
3867
3868 ixgbe_configure_tx(adapter);
3869 ixgbe_configure_rx(adapter);
3870 }
3871
3872 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3873 {
3874 switch (hw->phy.type) {
3875 case ixgbe_phy_sfp_avago:
3876 case ixgbe_phy_sfp_ftl:
3877 case ixgbe_phy_sfp_intel:
3878 case ixgbe_phy_sfp_unknown:
3879 case ixgbe_phy_sfp_passive_tyco:
3880 case ixgbe_phy_sfp_passive_unknown:
3881 case ixgbe_phy_sfp_active_unknown:
3882 case ixgbe_phy_sfp_ftl_active:
3883 return true;
3884 case ixgbe_phy_nl:
3885 if (hw->mac.type == ixgbe_mac_82598EB)
3886 return true;
3887 default:
3888 return false;
3889 }
3890 }
3891
3892 /**
3893 * ixgbe_sfp_link_config - set up SFP+ link
3894 * @adapter: pointer to private adapter struct
3895 **/
3896 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3897 {
3898 /*
3899 * We are assuming the worst case scenario here, and that
3900 * is that an SFP was inserted/removed after the reset
3901 * but before SFP detection was enabled. As such the best
3902 * solution is to just start searching as soon as we start
3903 */
3904 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3905 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3906
3907 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3908 }
3909
3910 /**
3911 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3912 * @hw: pointer to private hardware struct
3913 *
3914 * Returns 0 on success, negative on failure
3915 **/
3916 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3917 {
3918 u32 autoneg;
3919 bool negotiation, link_up = false;
3920 u32 ret = IXGBE_ERR_LINK_SETUP;
3921
3922 if (hw->mac.ops.check_link)
3923 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3924
3925 if (ret)
3926 goto link_cfg_out;
3927
3928 autoneg = hw->phy.autoneg_advertised;
3929 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3930 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3931 &negotiation);
3932 if (ret)
3933 goto link_cfg_out;
3934
3935 if (hw->mac.ops.setup_link)
3936 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3937 link_cfg_out:
3938 return ret;
3939 }
3940
3941 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3942 {
3943 struct ixgbe_hw *hw = &adapter->hw;
3944 u32 gpie = 0;
3945
3946 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3947 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3948 IXGBE_GPIE_OCD;
3949 gpie |= IXGBE_GPIE_EIAME;
3950 /*
3951 * use EIAM to auto-mask when MSI-X interrupt is asserted
3952 * this saves a register write for every interrupt
3953 */
3954 switch (hw->mac.type) {
3955 case ixgbe_mac_82598EB:
3956 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3957 break;
3958 case ixgbe_mac_82599EB:
3959 case ixgbe_mac_X540:
3960 default:
3961 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3962 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3963 break;
3964 }
3965 } else {
3966 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3967 * specifically only auto mask tx and rx interrupts */
3968 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3969 }
3970
3971 /* XXX: to interrupt immediately for EICS writes, enable this */
3972 /* gpie |= IXGBE_GPIE_EIMEN; */
3973
3974 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3975 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3976 gpie |= IXGBE_GPIE_VTMODE_64;
3977 }
3978
3979 /* Enable Thermal over heat sensor interrupt */
3980 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3981 switch (adapter->hw.mac.type) {
3982 case ixgbe_mac_82599EB:
3983 gpie |= IXGBE_SDP0_GPIEN;
3984 break;
3985 case ixgbe_mac_X540:
3986 gpie |= IXGBE_EIMS_TS;
3987 break;
3988 default:
3989 break;
3990 }
3991 }
3992
3993 /* Enable fan failure interrupt */
3994 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3995 gpie |= IXGBE_SDP1_GPIEN;
3996
3997 if (hw->mac.type == ixgbe_mac_82599EB) {
3998 gpie |= IXGBE_SDP1_GPIEN;
3999 gpie |= IXGBE_SDP2_GPIEN;
4000 }
4001
4002 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4003 }
4004
4005 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4006 {
4007 struct ixgbe_hw *hw = &adapter->hw;
4008 int err;
4009 u32 ctrl_ext;
4010
4011 ixgbe_get_hw_control(adapter);
4012 ixgbe_setup_gpie(adapter);
4013
4014 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4015 ixgbe_configure_msix(adapter);
4016 else
4017 ixgbe_configure_msi_and_legacy(adapter);
4018
4019 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
4020 if (hw->mac.ops.enable_tx_laser &&
4021 ((hw->phy.multispeed_fiber) ||
4022 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4023 (hw->mac.type == ixgbe_mac_82599EB))))
4024 hw->mac.ops.enable_tx_laser(hw);
4025
4026 clear_bit(__IXGBE_DOWN, &adapter->state);
4027 ixgbe_napi_enable_all(adapter);
4028
4029 if (ixgbe_is_sfp(hw)) {
4030 ixgbe_sfp_link_config(adapter);
4031 } else {
4032 err = ixgbe_non_sfp_link_config(hw);
4033 if (err)
4034 e_err(probe, "link_config FAILED %d\n", err);
4035 }
4036
4037 /* clear any pending interrupts, may auto mask */
4038 IXGBE_READ_REG(hw, IXGBE_EICR);
4039 ixgbe_irq_enable(adapter, true, true);
4040
4041 /*
4042 * If this adapter has a fan, check to see if we had a failure
4043 * before we enabled the interrupt.
4044 */
4045 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4046 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4047 if (esdp & IXGBE_ESDP_SDP1)
4048 e_crit(drv, "Fan has stopped, replace the adapter\n");
4049 }
4050
4051 /* enable transmits */
4052 netif_tx_start_all_queues(adapter->netdev);
4053
4054 /* bring the link up in the watchdog, this could race with our first
4055 * link up interrupt but shouldn't be a problem */
4056 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4057 adapter->link_check_timeout = jiffies;
4058 mod_timer(&adapter->service_timer, jiffies);
4059
4060 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4061 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4062 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4063 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4064 }
4065
4066 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4067 {
4068 WARN_ON(in_interrupt());
4069 /* put off any impending NetWatchDogTimeout */
4070 adapter->netdev->trans_start = jiffies;
4071
4072 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4073 usleep_range(1000, 2000);
4074 ixgbe_down(adapter);
4075 /*
4076 * If SR-IOV enabled then wait a bit before bringing the adapter
4077 * back up to give the VFs time to respond to the reset. The
4078 * two second wait is based upon the watchdog timer cycle in
4079 * the VF driver.
4080 */
4081 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4082 msleep(2000);
4083 ixgbe_up(adapter);
4084 clear_bit(__IXGBE_RESETTING, &adapter->state);
4085 }
4086
4087 void ixgbe_up(struct ixgbe_adapter *adapter)
4088 {
4089 /* hardware has been reset, we need to reload some things */
4090 ixgbe_configure(adapter);
4091
4092 ixgbe_up_complete(adapter);
4093 }
4094
4095 void ixgbe_reset(struct ixgbe_adapter *adapter)
4096 {
4097 struct ixgbe_hw *hw = &adapter->hw;
4098 int err;
4099
4100 /* lock SFP init bit to prevent race conditions with the watchdog */
4101 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4102 usleep_range(1000, 2000);
4103
4104 /* clear all SFP and link config related flags while holding SFP_INIT */
4105 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4106 IXGBE_FLAG2_SFP_NEEDS_RESET);
4107 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4108
4109 err = hw->mac.ops.init_hw(hw);
4110 switch (err) {
4111 case 0:
4112 case IXGBE_ERR_SFP_NOT_PRESENT:
4113 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4114 break;
4115 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4116 e_dev_err("master disable timed out\n");
4117 break;
4118 case IXGBE_ERR_EEPROM_VERSION:
4119 /* We are running on a pre-production device, log a warning */
4120 e_dev_warn("This device is a pre-production adapter/LOM. "
4121 "Please be aware there may be issues associated with "
4122 "your hardware. If you are experiencing problems "
4123 "please contact your Intel or hardware "
4124 "representative who provided you with this "
4125 "hardware.\n");
4126 break;
4127 default:
4128 e_dev_err("Hardware Error: %d\n", err);
4129 }
4130
4131 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4132
4133 /* reprogram the RAR[0] in case user changed it. */
4134 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4135 IXGBE_RAH_AV);
4136 }
4137
4138 /**
4139 * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers
4140 * @rx_ring: ring to setup
4141 *
4142 * On many IA platforms the L1 cache has a critical stride of 4K, this
4143 * results in each receive buffer starting in the same cache set. To help
4144 * reduce the pressure on this cache set we can interleave the offsets so
4145 * that only every other buffer will be in the same cache set.
4146 **/
4147 static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring)
4148 {
4149 struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info;
4150 u16 i;
4151
4152 for (i = 0; i < rx_ring->count; i += 2) {
4153 rx_buffer[0].page_offset = 0;
4154 rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring);
4155 rx_buffer = &rx_buffer[2];
4156 }
4157 }
4158
4159 /**
4160 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4161 * @rx_ring: ring to free buffers from
4162 **/
4163 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4164 {
4165 struct device *dev = rx_ring->dev;
4166 unsigned long size;
4167 u16 i;
4168
4169 /* ring already cleared, nothing to do */
4170 if (!rx_ring->rx_buffer_info)
4171 return;
4172
4173 /* Free all the Rx ring sk_buffs */
4174 for (i = 0; i < rx_ring->count; i++) {
4175 struct ixgbe_rx_buffer *rx_buffer;
4176
4177 rx_buffer = &rx_ring->rx_buffer_info[i];
4178 if (rx_buffer->skb) {
4179 struct sk_buff *skb = rx_buffer->skb;
4180 if (IXGBE_CB(skb)->page_released) {
4181 dma_unmap_page(dev,
4182 IXGBE_CB(skb)->dma,
4183 ixgbe_rx_bufsz(rx_ring),
4184 DMA_FROM_DEVICE);
4185 IXGBE_CB(skb)->page_released = false;
4186 }
4187 dev_kfree_skb(skb);
4188 }
4189 rx_buffer->skb = NULL;
4190 if (rx_buffer->dma)
4191 dma_unmap_page(dev, rx_buffer->dma,
4192 ixgbe_rx_pg_size(rx_ring),
4193 DMA_FROM_DEVICE);
4194 rx_buffer->dma = 0;
4195 if (rx_buffer->page)
4196 __free_pages(rx_buffer->page,
4197 ixgbe_rx_pg_order(rx_ring));
4198 rx_buffer->page = NULL;
4199 }
4200
4201 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4202 memset(rx_ring->rx_buffer_info, 0, size);
4203
4204 ixgbe_init_rx_page_offset(rx_ring);
4205
4206 /* Zero out the descriptor ring */
4207 memset(rx_ring->desc, 0, rx_ring->size);
4208
4209 rx_ring->next_to_alloc = 0;
4210 rx_ring->next_to_clean = 0;
4211 rx_ring->next_to_use = 0;
4212 }
4213
4214 /**
4215 * ixgbe_clean_tx_ring - Free Tx Buffers
4216 * @tx_ring: ring to be cleaned
4217 **/
4218 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4219 {
4220 struct ixgbe_tx_buffer *tx_buffer_info;
4221 unsigned long size;
4222 u16 i;
4223
4224 /* ring already cleared, nothing to do */
4225 if (!tx_ring->tx_buffer_info)
4226 return;
4227
4228 /* Free all the Tx ring sk_buffs */
4229 for (i = 0; i < tx_ring->count; i++) {
4230 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4231 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4232 }
4233
4234 netdev_tx_reset_queue(txring_txq(tx_ring));
4235
4236 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4237 memset(tx_ring->tx_buffer_info, 0, size);
4238
4239 /* Zero out the descriptor ring */
4240 memset(tx_ring->desc, 0, tx_ring->size);
4241
4242 tx_ring->next_to_use = 0;
4243 tx_ring->next_to_clean = 0;
4244 }
4245
4246 /**
4247 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4248 * @adapter: board private structure
4249 **/
4250 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4251 {
4252 int i;
4253
4254 for (i = 0; i < adapter->num_rx_queues; i++)
4255 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4256 }
4257
4258 /**
4259 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4260 * @adapter: board private structure
4261 **/
4262 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4263 {
4264 int i;
4265
4266 for (i = 0; i < adapter->num_tx_queues; i++)
4267 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4268 }
4269
4270 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4271 {
4272 struct hlist_node *node, *node2;
4273 struct ixgbe_fdir_filter *filter;
4274
4275 spin_lock(&adapter->fdir_perfect_lock);
4276
4277 hlist_for_each_entry_safe(filter, node, node2,
4278 &adapter->fdir_filter_list, fdir_node) {
4279 hlist_del(&filter->fdir_node);
4280 kfree(filter);
4281 }
4282 adapter->fdir_filter_count = 0;
4283
4284 spin_unlock(&adapter->fdir_perfect_lock);
4285 }
4286
4287 void ixgbe_down(struct ixgbe_adapter *adapter)
4288 {
4289 struct net_device *netdev = adapter->netdev;
4290 struct ixgbe_hw *hw = &adapter->hw;
4291 u32 rxctrl;
4292 int i;
4293
4294 /* signal that we are down to the interrupt handler */
4295 set_bit(__IXGBE_DOWN, &adapter->state);
4296
4297 /* disable receives */
4298 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4299 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4300
4301 /* disable all enabled rx queues */
4302 for (i = 0; i < adapter->num_rx_queues; i++)
4303 /* this call also flushes the previous write */
4304 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4305
4306 usleep_range(10000, 20000);
4307
4308 netif_tx_stop_all_queues(netdev);
4309
4310 /* call carrier off first to avoid false dev_watchdog timeouts */
4311 netif_carrier_off(netdev);
4312 netif_tx_disable(netdev);
4313
4314 ixgbe_irq_disable(adapter);
4315
4316 ixgbe_napi_disable_all(adapter);
4317
4318 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4319 IXGBE_FLAG2_RESET_REQUESTED);
4320 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4321
4322 del_timer_sync(&adapter->service_timer);
4323
4324 if (adapter->num_vfs) {
4325 /* Clear EITR Select mapping */
4326 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4327
4328 /* Mark all the VFs as inactive */
4329 for (i = 0 ; i < adapter->num_vfs; i++)
4330 adapter->vfinfo[i].clear_to_send = false;
4331
4332 /* ping all the active vfs to let them know we are going down */
4333 ixgbe_ping_all_vfs(adapter);
4334
4335 /* Disable all VFTE/VFRE TX/RX */
4336 ixgbe_disable_tx_rx(adapter);
4337 }
4338
4339 /* disable transmits in the hardware now that interrupts are off */
4340 for (i = 0; i < adapter->num_tx_queues; i++) {
4341 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4342 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4343 }
4344
4345 /* Disable the Tx DMA engine on 82599 and X540 */
4346 switch (hw->mac.type) {
4347 case ixgbe_mac_82599EB:
4348 case ixgbe_mac_X540:
4349 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4350 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4351 ~IXGBE_DMATXCTL_TE));
4352 break;
4353 default:
4354 break;
4355 }
4356
4357 if (!pci_channel_offline(adapter->pdev))
4358 ixgbe_reset(adapter);
4359
4360 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4361 if (hw->mac.ops.disable_tx_laser &&
4362 ((hw->phy.multispeed_fiber) ||
4363 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4364 (hw->mac.type == ixgbe_mac_82599EB))))
4365 hw->mac.ops.disable_tx_laser(hw);
4366
4367 ixgbe_clean_all_tx_rings(adapter);
4368 ixgbe_clean_all_rx_rings(adapter);
4369
4370 #ifdef CONFIG_IXGBE_DCA
4371 /* since we reset the hardware DCA settings were cleared */
4372 ixgbe_setup_dca(adapter);
4373 #endif
4374 }
4375
4376 /**
4377 * ixgbe_tx_timeout - Respond to a Tx Hang
4378 * @netdev: network interface device structure
4379 **/
4380 static void ixgbe_tx_timeout(struct net_device *netdev)
4381 {
4382 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4383
4384 /* Do the reset outside of interrupt context */
4385 ixgbe_tx_timeout_reset(adapter);
4386 }
4387
4388 /**
4389 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4390 * @adapter: board private structure to initialize
4391 *
4392 * ixgbe_sw_init initializes the Adapter private data structure.
4393 * Fields are initialized based on PCI device information and
4394 * OS network device settings (MTU size).
4395 **/
4396 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4397 {
4398 struct ixgbe_hw *hw = &adapter->hw;
4399 struct pci_dev *pdev = adapter->pdev;
4400 unsigned int rss;
4401 #ifdef CONFIG_IXGBE_DCB
4402 int j;
4403 struct tc_configuration *tc;
4404 #endif
4405
4406 /* PCI config space info */
4407
4408 hw->vendor_id = pdev->vendor;
4409 hw->device_id = pdev->device;
4410 hw->revision_id = pdev->revision;
4411 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4412 hw->subsystem_device_id = pdev->subsystem_device;
4413
4414 /* Set capability flags */
4415 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4416 adapter->ring_feature[RING_F_RSS].indices = rss;
4417 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4418 switch (hw->mac.type) {
4419 case ixgbe_mac_82598EB:
4420 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4421 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4422 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4423 break;
4424 case ixgbe_mac_X540:
4425 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4426 case ixgbe_mac_82599EB:
4427 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4428 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4429 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4430 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4431 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4432 /* Flow Director hash filters enabled */
4433 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4434 adapter->atr_sample_rate = 20;
4435 adapter->ring_feature[RING_F_FDIR].indices =
4436 IXGBE_MAX_FDIR_INDICES;
4437 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4438 #ifdef IXGBE_FCOE
4439 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4440 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4441 adapter->ring_feature[RING_F_FCOE].indices = 0;
4442 #ifdef CONFIG_IXGBE_DCB
4443 /* Default traffic class to use for FCoE */
4444 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4445 #endif
4446 #endif /* IXGBE_FCOE */
4447 break;
4448 default:
4449 break;
4450 }
4451
4452 /* n-tuple support exists, always init our spinlock */
4453 spin_lock_init(&adapter->fdir_perfect_lock);
4454
4455 #ifdef CONFIG_IXGBE_DCB
4456 switch (hw->mac.type) {
4457 case ixgbe_mac_X540:
4458 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4459 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4460 break;
4461 default:
4462 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4463 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4464 break;
4465 }
4466
4467 /* Configure DCB traffic classes */
4468 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4469 tc = &adapter->dcb_cfg.tc_config[j];
4470 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4471 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4472 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4473 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4474 tc->dcb_pfc = pfc_disabled;
4475 }
4476
4477 /* Initialize default user to priority mapping, UPx->TC0 */
4478 tc = &adapter->dcb_cfg.tc_config[0];
4479 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4480 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4481
4482 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4483 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4484 adapter->dcb_cfg.pfc_mode_enable = false;
4485 adapter->dcb_set_bitmap = 0x00;
4486 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4487 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4488 sizeof(adapter->temp_dcb_cfg));
4489
4490 #endif
4491
4492 /* default flow control settings */
4493 hw->fc.requested_mode = ixgbe_fc_full;
4494 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4495 ixgbe_pbthresh_setup(adapter);
4496 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4497 hw->fc.send_xon = true;
4498 hw->fc.disable_fc_autoneg = false;
4499
4500 /* enable itr by default in dynamic mode */
4501 adapter->rx_itr_setting = 1;
4502 adapter->tx_itr_setting = 1;
4503
4504 /* set default ring sizes */
4505 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4506 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4507
4508 /* set default work limits */
4509 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4510
4511 /* initialize eeprom parameters */
4512 if (ixgbe_init_eeprom_params_generic(hw)) {
4513 e_dev_err("EEPROM initialization failed\n");
4514 return -EIO;
4515 }
4516
4517 set_bit(__IXGBE_DOWN, &adapter->state);
4518
4519 return 0;
4520 }
4521
4522 /**
4523 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4524 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4525 *
4526 * Return 0 on success, negative on failure
4527 **/
4528 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4529 {
4530 struct device *dev = tx_ring->dev;
4531 int orig_node = dev_to_node(dev);
4532 int numa_node = -1;
4533 int size;
4534
4535 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4536
4537 if (tx_ring->q_vector)
4538 numa_node = tx_ring->q_vector->numa_node;
4539
4540 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4541 if (!tx_ring->tx_buffer_info)
4542 tx_ring->tx_buffer_info = vzalloc(size);
4543 if (!tx_ring->tx_buffer_info)
4544 goto err;
4545
4546 /* round up to nearest 4K */
4547 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4548 tx_ring->size = ALIGN(tx_ring->size, 4096);
4549
4550 set_dev_node(dev, numa_node);
4551 tx_ring->desc = dma_alloc_coherent(dev,
4552 tx_ring->size,
4553 &tx_ring->dma,
4554 GFP_KERNEL);
4555 set_dev_node(dev, orig_node);
4556 if (!tx_ring->desc)
4557 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4558 &tx_ring->dma, GFP_KERNEL);
4559 if (!tx_ring->desc)
4560 goto err;
4561
4562 tx_ring->next_to_use = 0;
4563 tx_ring->next_to_clean = 0;
4564 return 0;
4565
4566 err:
4567 vfree(tx_ring->tx_buffer_info);
4568 tx_ring->tx_buffer_info = NULL;
4569 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4570 return -ENOMEM;
4571 }
4572
4573 /**
4574 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4575 * @adapter: board private structure
4576 *
4577 * If this function returns with an error, then it's possible one or
4578 * more of the rings is populated (while the rest are not). It is the
4579 * callers duty to clean those orphaned rings.
4580 *
4581 * Return 0 on success, negative on failure
4582 **/
4583 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4584 {
4585 int i, err = 0;
4586
4587 for (i = 0; i < adapter->num_tx_queues; i++) {
4588 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4589 if (!err)
4590 continue;
4591 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4592 break;
4593 }
4594
4595 return err;
4596 }
4597
4598 /**
4599 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4600 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4601 *
4602 * Returns 0 on success, negative on failure
4603 **/
4604 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4605 {
4606 struct device *dev = rx_ring->dev;
4607 int orig_node = dev_to_node(dev);
4608 int numa_node = -1;
4609 int size;
4610
4611 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4612
4613 if (rx_ring->q_vector)
4614 numa_node = rx_ring->q_vector->numa_node;
4615
4616 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4617 if (!rx_ring->rx_buffer_info)
4618 rx_ring->rx_buffer_info = vzalloc(size);
4619 if (!rx_ring->rx_buffer_info)
4620 goto err;
4621
4622 /* Round up to nearest 4K */
4623 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4624 rx_ring->size = ALIGN(rx_ring->size, 4096);
4625
4626 set_dev_node(dev, numa_node);
4627 rx_ring->desc = dma_alloc_coherent(dev,
4628 rx_ring->size,
4629 &rx_ring->dma,
4630 GFP_KERNEL);
4631 set_dev_node(dev, orig_node);
4632 if (!rx_ring->desc)
4633 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4634 &rx_ring->dma, GFP_KERNEL);
4635 if (!rx_ring->desc)
4636 goto err;
4637
4638 rx_ring->next_to_clean = 0;
4639 rx_ring->next_to_use = 0;
4640
4641 ixgbe_init_rx_page_offset(rx_ring);
4642
4643 return 0;
4644 err:
4645 vfree(rx_ring->rx_buffer_info);
4646 rx_ring->rx_buffer_info = NULL;
4647 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4648 return -ENOMEM;
4649 }
4650
4651 /**
4652 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4653 * @adapter: board private structure
4654 *
4655 * If this function returns with an error, then it's possible one or
4656 * more of the rings is populated (while the rest are not). It is the
4657 * callers duty to clean those orphaned rings.
4658 *
4659 * Return 0 on success, negative on failure
4660 **/
4661 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4662 {
4663 int i, err = 0;
4664
4665 for (i = 0; i < adapter->num_rx_queues; i++) {
4666 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4667 if (!err)
4668 continue;
4669 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4670 break;
4671 }
4672
4673 return err;
4674 }
4675
4676 /**
4677 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4678 * @tx_ring: Tx descriptor ring for a specific queue
4679 *
4680 * Free all transmit software resources
4681 **/
4682 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
4683 {
4684 ixgbe_clean_tx_ring(tx_ring);
4685
4686 vfree(tx_ring->tx_buffer_info);
4687 tx_ring->tx_buffer_info = NULL;
4688
4689 /* if not set, then don't free */
4690 if (!tx_ring->desc)
4691 return;
4692
4693 dma_free_coherent(tx_ring->dev, tx_ring->size,
4694 tx_ring->desc, tx_ring->dma);
4695
4696 tx_ring->desc = NULL;
4697 }
4698
4699 /**
4700 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4701 * @adapter: board private structure
4702 *
4703 * Free all transmit software resources
4704 **/
4705 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4706 {
4707 int i;
4708
4709 for (i = 0; i < adapter->num_tx_queues; i++)
4710 if (adapter->tx_ring[i]->desc)
4711 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4712 }
4713
4714 /**
4715 * ixgbe_free_rx_resources - Free Rx Resources
4716 * @rx_ring: ring to clean the resources from
4717 *
4718 * Free all receive software resources
4719 **/
4720 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
4721 {
4722 ixgbe_clean_rx_ring(rx_ring);
4723
4724 vfree(rx_ring->rx_buffer_info);
4725 rx_ring->rx_buffer_info = NULL;
4726
4727 /* if not set, then don't free */
4728 if (!rx_ring->desc)
4729 return;
4730
4731 dma_free_coherent(rx_ring->dev, rx_ring->size,
4732 rx_ring->desc, rx_ring->dma);
4733
4734 rx_ring->desc = NULL;
4735 }
4736
4737 /**
4738 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4739 * @adapter: board private structure
4740 *
4741 * Free all receive software resources
4742 **/
4743 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4744 {
4745 int i;
4746
4747 for (i = 0; i < adapter->num_rx_queues; i++)
4748 if (adapter->rx_ring[i]->desc)
4749 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4750 }
4751
4752 /**
4753 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4754 * @netdev: network interface device structure
4755 * @new_mtu: new value for maximum frame size
4756 *
4757 * Returns 0 on success, negative on failure
4758 **/
4759 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4760 {
4761 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4762 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4763
4764 /* MTU < 68 is an error and causes problems on some kernels */
4765 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4766 return -EINVAL;
4767
4768 /*
4769 * For 82599EB we cannot allow PF to change MTU greater than 1500
4770 * in SR-IOV mode as it may cause buffer overruns in guest VFs that
4771 * don't allocate and chain buffers correctly.
4772 */
4773 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4774 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4775 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
4776 return -EINVAL;
4777
4778 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
4779
4780 /* must set new MTU before calling down or up */
4781 netdev->mtu = new_mtu;
4782
4783 if (netif_running(netdev))
4784 ixgbe_reinit_locked(adapter);
4785
4786 return 0;
4787 }
4788
4789 /**
4790 * ixgbe_open - Called when a network interface is made active
4791 * @netdev: network interface device structure
4792 *
4793 * Returns 0 on success, negative value on failure
4794 *
4795 * The open entry point is called when a network interface is made
4796 * active by the system (IFF_UP). At this point all resources needed
4797 * for transmit and receive operations are allocated, the interrupt
4798 * handler is registered with the OS, the watchdog timer is started,
4799 * and the stack is notified that the interface is ready.
4800 **/
4801 static int ixgbe_open(struct net_device *netdev)
4802 {
4803 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4804 int err;
4805
4806 /* disallow open during test */
4807 if (test_bit(__IXGBE_TESTING, &adapter->state))
4808 return -EBUSY;
4809
4810 netif_carrier_off(netdev);
4811
4812 /* allocate transmit descriptors */
4813 err = ixgbe_setup_all_tx_resources(adapter);
4814 if (err)
4815 goto err_setup_tx;
4816
4817 /* allocate receive descriptors */
4818 err = ixgbe_setup_all_rx_resources(adapter);
4819 if (err)
4820 goto err_setup_rx;
4821
4822 ixgbe_configure(adapter);
4823
4824 err = ixgbe_request_irq(adapter);
4825 if (err)
4826 goto err_req_irq;
4827
4828 ixgbe_up_complete(adapter);
4829
4830 return 0;
4831
4832 err_req_irq:
4833 err_setup_rx:
4834 ixgbe_free_all_rx_resources(adapter);
4835 err_setup_tx:
4836 ixgbe_free_all_tx_resources(adapter);
4837 ixgbe_reset(adapter);
4838
4839 return err;
4840 }
4841
4842 /**
4843 * ixgbe_close - Disables a network interface
4844 * @netdev: network interface device structure
4845 *
4846 * Returns 0, this is not allowed to fail
4847 *
4848 * The close entry point is called when an interface is de-activated
4849 * by the OS. The hardware is still under the drivers control, but
4850 * needs to be disabled. A global MAC reset is issued to stop the
4851 * hardware, and all transmit and receive resources are freed.
4852 **/
4853 static int ixgbe_close(struct net_device *netdev)
4854 {
4855 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4856
4857 ixgbe_down(adapter);
4858 ixgbe_free_irq(adapter);
4859
4860 ixgbe_fdir_filter_exit(adapter);
4861
4862 ixgbe_free_all_tx_resources(adapter);
4863 ixgbe_free_all_rx_resources(adapter);
4864
4865 ixgbe_release_hw_control(adapter);
4866
4867 return 0;
4868 }
4869
4870 #ifdef CONFIG_PM
4871 static int ixgbe_resume(struct pci_dev *pdev)
4872 {
4873 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4874 struct net_device *netdev = adapter->netdev;
4875 u32 err;
4876
4877 pci_set_power_state(pdev, PCI_D0);
4878 pci_restore_state(pdev);
4879 /*
4880 * pci_restore_state clears dev->state_saved so call
4881 * pci_save_state to restore it.
4882 */
4883 pci_save_state(pdev);
4884
4885 err = pci_enable_device_mem(pdev);
4886 if (err) {
4887 e_dev_err("Cannot enable PCI device from suspend\n");
4888 return err;
4889 }
4890 pci_set_master(pdev);
4891
4892 pci_wake_from_d3(pdev, false);
4893
4894 rtnl_lock();
4895 err = ixgbe_init_interrupt_scheme(adapter);
4896 rtnl_unlock();
4897 if (err) {
4898 e_dev_err("Cannot initialize interrupts for device\n");
4899 return err;
4900 }
4901
4902 ixgbe_reset(adapter);
4903
4904 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4905
4906 if (netif_running(netdev)) {
4907 err = ixgbe_open(netdev);
4908 if (err)
4909 return err;
4910 }
4911
4912 netif_device_attach(netdev);
4913
4914 return 0;
4915 }
4916 #endif /* CONFIG_PM */
4917
4918 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4919 {
4920 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4921 struct net_device *netdev = adapter->netdev;
4922 struct ixgbe_hw *hw = &adapter->hw;
4923 u32 ctrl, fctrl;
4924 u32 wufc = adapter->wol;
4925 #ifdef CONFIG_PM
4926 int retval = 0;
4927 #endif
4928
4929 netif_device_detach(netdev);
4930
4931 if (netif_running(netdev)) {
4932 rtnl_lock();
4933 ixgbe_down(adapter);
4934 ixgbe_free_irq(adapter);
4935 ixgbe_free_all_tx_resources(adapter);
4936 ixgbe_free_all_rx_resources(adapter);
4937 rtnl_unlock();
4938 }
4939
4940 ixgbe_clear_interrupt_scheme(adapter);
4941
4942 #ifdef CONFIG_PM
4943 retval = pci_save_state(pdev);
4944 if (retval)
4945 return retval;
4946
4947 #endif
4948 if (wufc) {
4949 ixgbe_set_rx_mode(netdev);
4950
4951 /*
4952 * enable the optics for both mult-speed fiber and
4953 * 82599 SFP+ fiber as we can WoL.
4954 */
4955 if (hw->mac.ops.enable_tx_laser &&
4956 (hw->phy.multispeed_fiber ||
4957 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber &&
4958 hw->mac.type == ixgbe_mac_82599EB)))
4959 hw->mac.ops.enable_tx_laser(hw);
4960
4961 /* turn on all-multi mode if wake on multicast is enabled */
4962 if (wufc & IXGBE_WUFC_MC) {
4963 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4964 fctrl |= IXGBE_FCTRL_MPE;
4965 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4966 }
4967
4968 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4969 ctrl |= IXGBE_CTRL_GIO_DIS;
4970 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4971
4972 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4973 } else {
4974 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4975 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4976 }
4977
4978 switch (hw->mac.type) {
4979 case ixgbe_mac_82598EB:
4980 pci_wake_from_d3(pdev, false);
4981 break;
4982 case ixgbe_mac_82599EB:
4983 case ixgbe_mac_X540:
4984 pci_wake_from_d3(pdev, !!wufc);
4985 break;
4986 default:
4987 break;
4988 }
4989
4990 *enable_wake = !!wufc;
4991
4992 ixgbe_release_hw_control(adapter);
4993
4994 pci_disable_device(pdev);
4995
4996 return 0;
4997 }
4998
4999 #ifdef CONFIG_PM
5000 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5001 {
5002 int retval;
5003 bool wake;
5004
5005 retval = __ixgbe_shutdown(pdev, &wake);
5006 if (retval)
5007 return retval;
5008
5009 if (wake) {
5010 pci_prepare_to_sleep(pdev);
5011 } else {
5012 pci_wake_from_d3(pdev, false);
5013 pci_set_power_state(pdev, PCI_D3hot);
5014 }
5015
5016 return 0;
5017 }
5018 #endif /* CONFIG_PM */
5019
5020 static void ixgbe_shutdown(struct pci_dev *pdev)
5021 {
5022 bool wake;
5023
5024 __ixgbe_shutdown(pdev, &wake);
5025
5026 if (system_state == SYSTEM_POWER_OFF) {
5027 pci_wake_from_d3(pdev, wake);
5028 pci_set_power_state(pdev, PCI_D3hot);
5029 }
5030 }
5031
5032 /**
5033 * ixgbe_update_stats - Update the board statistics counters.
5034 * @adapter: board private structure
5035 **/
5036 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5037 {
5038 struct net_device *netdev = adapter->netdev;
5039 struct ixgbe_hw *hw = &adapter->hw;
5040 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5041 u64 total_mpc = 0;
5042 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5043 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5044 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5045 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5046 #ifdef IXGBE_FCOE
5047 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5048 unsigned int cpu;
5049 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5050 #endif /* IXGBE_FCOE */
5051
5052 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5053 test_bit(__IXGBE_RESETTING, &adapter->state))
5054 return;
5055
5056 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5057 u64 rsc_count = 0;
5058 u64 rsc_flush = 0;
5059 for (i = 0; i < adapter->num_rx_queues; i++) {
5060 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5061 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5062 }
5063 adapter->rsc_total_count = rsc_count;
5064 adapter->rsc_total_flush = rsc_flush;
5065 }
5066
5067 for (i = 0; i < adapter->num_rx_queues; i++) {
5068 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5069 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5070 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5071 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5072 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5073 bytes += rx_ring->stats.bytes;
5074 packets += rx_ring->stats.packets;
5075 }
5076 adapter->non_eop_descs = non_eop_descs;
5077 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5078 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5079 adapter->hw_csum_rx_error = hw_csum_rx_error;
5080 netdev->stats.rx_bytes = bytes;
5081 netdev->stats.rx_packets = packets;
5082
5083 bytes = 0;
5084 packets = 0;
5085 /* gather some stats to the adapter struct that are per queue */
5086 for (i = 0; i < adapter->num_tx_queues; i++) {
5087 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5088 restart_queue += tx_ring->tx_stats.restart_queue;
5089 tx_busy += tx_ring->tx_stats.tx_busy;
5090 bytes += tx_ring->stats.bytes;
5091 packets += tx_ring->stats.packets;
5092 }
5093 adapter->restart_queue = restart_queue;
5094 adapter->tx_busy = tx_busy;
5095 netdev->stats.tx_bytes = bytes;
5096 netdev->stats.tx_packets = packets;
5097
5098 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5099
5100 /* 8 register reads */
5101 for (i = 0; i < 8; i++) {
5102 /* for packet buffers not used, the register should read 0 */
5103 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5104 missed_rx += mpc;
5105 hwstats->mpc[i] += mpc;
5106 total_mpc += hwstats->mpc[i];
5107 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5108 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5109 switch (hw->mac.type) {
5110 case ixgbe_mac_82598EB:
5111 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5112 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5113 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5114 hwstats->pxonrxc[i] +=
5115 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5116 break;
5117 case ixgbe_mac_82599EB:
5118 case ixgbe_mac_X540:
5119 hwstats->pxonrxc[i] +=
5120 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5121 break;
5122 default:
5123 break;
5124 }
5125 }
5126
5127 /*16 register reads */
5128 for (i = 0; i < 16; i++) {
5129 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5130 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5131 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5132 (hw->mac.type == ixgbe_mac_X540)) {
5133 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5134 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5135 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5136 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5137 }
5138 }
5139
5140 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5141 /* work around hardware counting issue */
5142 hwstats->gprc -= missed_rx;
5143
5144 ixgbe_update_xoff_received(adapter);
5145
5146 /* 82598 hardware only has a 32 bit counter in the high register */
5147 switch (hw->mac.type) {
5148 case ixgbe_mac_82598EB:
5149 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5150 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5151 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5152 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5153 break;
5154 case ixgbe_mac_X540:
5155 /* OS2BMC stats are X540 only*/
5156 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5157 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5158 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5159 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5160 case ixgbe_mac_82599EB:
5161 for (i = 0; i < 16; i++)
5162 adapter->hw_rx_no_dma_resources +=
5163 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5164 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5165 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5166 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5167 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5168 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5169 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5170 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5171 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5172 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5173 #ifdef IXGBE_FCOE
5174 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5175 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5176 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5177 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5178 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5179 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5180 /* Add up per cpu counters for total ddp aloc fail */
5181 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5182 for_each_possible_cpu(cpu) {
5183 fcoe_noddp_counts_sum +=
5184 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5185 fcoe_noddp_ext_buff_counts_sum +=
5186 *per_cpu_ptr(fcoe->
5187 pcpu_noddp_ext_buff, cpu);
5188 }
5189 }
5190 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5191 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
5192 #endif /* IXGBE_FCOE */
5193 break;
5194 default:
5195 break;
5196 }
5197 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5198 hwstats->bprc += bprc;
5199 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5200 if (hw->mac.type == ixgbe_mac_82598EB)
5201 hwstats->mprc -= bprc;
5202 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5203 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5204 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5205 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5206 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5207 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5208 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5209 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5210 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5211 hwstats->lxontxc += lxon;
5212 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5213 hwstats->lxofftxc += lxoff;
5214 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5215 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5216 /*
5217 * 82598 errata - tx of flow control packets is included in tx counters
5218 */
5219 xon_off_tot = lxon + lxoff;
5220 hwstats->gptc -= xon_off_tot;
5221 hwstats->mptc -= xon_off_tot;
5222 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5223 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5224 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5225 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5226 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5227 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5228 hwstats->ptc64 -= xon_off_tot;
5229 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5230 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5231 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5232 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5233 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5234 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5235
5236 /* Fill out the OS statistics structure */
5237 netdev->stats.multicast = hwstats->mprc;
5238
5239 /* Rx Errors */
5240 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5241 netdev->stats.rx_dropped = 0;
5242 netdev->stats.rx_length_errors = hwstats->rlec;
5243 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5244 netdev->stats.rx_missed_errors = total_mpc;
5245 }
5246
5247 /**
5248 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5249 * @adapter - pointer to the device adapter structure
5250 **/
5251 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5252 {
5253 struct ixgbe_hw *hw = &adapter->hw;
5254 int i;
5255
5256 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5257 return;
5258
5259 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5260
5261 /* if interface is down do nothing */
5262 if (test_bit(__IXGBE_DOWN, &adapter->state))
5263 return;
5264
5265 /* do nothing if we are not using signature filters */
5266 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5267 return;
5268
5269 adapter->fdir_overflow++;
5270
5271 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5272 for (i = 0; i < adapter->num_tx_queues; i++)
5273 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5274 &(adapter->tx_ring[i]->state));
5275 /* re-enable flow director interrupts */
5276 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5277 } else {
5278 e_err(probe, "failed to finish FDIR re-initialization, "
5279 "ignored adding FDIR ATR filters\n");
5280 }
5281 }
5282
5283 /**
5284 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5285 * @adapter - pointer to the device adapter structure
5286 *
5287 * This function serves two purposes. First it strobes the interrupt lines
5288 * in order to make certain interrupts are occurring. Secondly it sets the
5289 * bits needed to check for TX hangs. As a result we should immediately
5290 * determine if a hang has occurred.
5291 */
5292 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5293 {
5294 struct ixgbe_hw *hw = &adapter->hw;
5295 u64 eics = 0;
5296 int i;
5297
5298 /* If we're down or resetting, just bail */
5299 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5300 test_bit(__IXGBE_RESETTING, &adapter->state))
5301 return;
5302
5303 /* Force detection of hung controller */
5304 if (netif_carrier_ok(adapter->netdev)) {
5305 for (i = 0; i < adapter->num_tx_queues; i++)
5306 set_check_for_tx_hang(adapter->tx_ring[i]);
5307 }
5308
5309 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5310 /*
5311 * for legacy and MSI interrupts don't set any bits
5312 * that are enabled for EIAM, because this operation
5313 * would set *both* EIMS and EICS for any bit in EIAM
5314 */
5315 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5316 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5317 } else {
5318 /* get one bit for every active tx/rx interrupt vector */
5319 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5320 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5321 if (qv->rx.ring || qv->tx.ring)
5322 eics |= ((u64)1 << i);
5323 }
5324 }
5325
5326 /* Cause software interrupt to ensure rings are cleaned */
5327 ixgbe_irq_rearm_queues(adapter, eics);
5328
5329 }
5330
5331 /**
5332 * ixgbe_watchdog_update_link - update the link status
5333 * @adapter - pointer to the device adapter structure
5334 * @link_speed - pointer to a u32 to store the link_speed
5335 **/
5336 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5337 {
5338 struct ixgbe_hw *hw = &adapter->hw;
5339 u32 link_speed = adapter->link_speed;
5340 bool link_up = adapter->link_up;
5341 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
5342
5343 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5344 return;
5345
5346 if (hw->mac.ops.check_link) {
5347 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5348 } else {
5349 /* always assume link is up, if no check link function */
5350 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5351 link_up = true;
5352 }
5353
5354 if (adapter->ixgbe_ieee_pfc)
5355 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5356
5357 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
5358 hw->mac.ops.fc_enable(hw);
5359 ixgbe_set_rx_drop_en(adapter);
5360 }
5361
5362 if (link_up ||
5363 time_after(jiffies, (adapter->link_check_timeout +
5364 IXGBE_TRY_LINK_TIMEOUT))) {
5365 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5366 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5367 IXGBE_WRITE_FLUSH(hw);
5368 }
5369
5370 adapter->link_up = link_up;
5371 adapter->link_speed = link_speed;
5372 }
5373
5374 /**
5375 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5376 * print link up message
5377 * @adapter - pointer to the device adapter structure
5378 **/
5379 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5380 {
5381 struct net_device *netdev = adapter->netdev;
5382 struct ixgbe_hw *hw = &adapter->hw;
5383 u32 link_speed = adapter->link_speed;
5384 bool flow_rx, flow_tx;
5385
5386 /* only continue if link was previously down */
5387 if (netif_carrier_ok(netdev))
5388 return;
5389
5390 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5391
5392 switch (hw->mac.type) {
5393 case ixgbe_mac_82598EB: {
5394 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5395 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5396 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5397 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5398 }
5399 break;
5400 case ixgbe_mac_X540:
5401 case ixgbe_mac_82599EB: {
5402 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5403 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5404 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5405 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5406 }
5407 break;
5408 default:
5409 flow_tx = false;
5410 flow_rx = false;
5411 break;
5412 }
5413
5414 #ifdef CONFIG_IXGBE_PTP
5415 ixgbe_ptp_start_cyclecounter(adapter);
5416 #endif
5417
5418 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5419 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5420 "10 Gbps" :
5421 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5422 "1 Gbps" :
5423 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5424 "100 Mbps" :
5425 "unknown speed"))),
5426 ((flow_rx && flow_tx) ? "RX/TX" :
5427 (flow_rx ? "RX" :
5428 (flow_tx ? "TX" : "None"))));
5429
5430 netif_carrier_on(netdev);
5431 ixgbe_check_vf_rate_limit(adapter);
5432 }
5433
5434 /**
5435 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5436 * print link down message
5437 * @adapter - pointer to the adapter structure
5438 **/
5439 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5440 {
5441 struct net_device *netdev = adapter->netdev;
5442 struct ixgbe_hw *hw = &adapter->hw;
5443
5444 adapter->link_up = false;
5445 adapter->link_speed = 0;
5446
5447 /* only continue if link was up previously */
5448 if (!netif_carrier_ok(netdev))
5449 return;
5450
5451 /* poll for SFP+ cable when link is down */
5452 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5453 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5454
5455 #ifdef CONFIG_IXGBE_PTP
5456 ixgbe_ptp_start_cyclecounter(adapter);
5457 #endif
5458
5459 e_info(drv, "NIC Link is Down\n");
5460 netif_carrier_off(netdev);
5461 }
5462
5463 /**
5464 * ixgbe_watchdog_flush_tx - flush queues on link down
5465 * @adapter - pointer to the device adapter structure
5466 **/
5467 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5468 {
5469 int i;
5470 int some_tx_pending = 0;
5471
5472 if (!netif_carrier_ok(adapter->netdev)) {
5473 for (i = 0; i < adapter->num_tx_queues; i++) {
5474 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5475 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5476 some_tx_pending = 1;
5477 break;
5478 }
5479 }
5480
5481 if (some_tx_pending) {
5482 /* We've lost link, so the controller stops DMA,
5483 * but we've got queued Tx work that's never going
5484 * to get done, so reset controller to flush Tx.
5485 * (Do the reset outside of interrupt context).
5486 */
5487 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5488 }
5489 }
5490 }
5491
5492 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5493 {
5494 u32 ssvpc;
5495
5496 /* Do not perform spoof check for 82598 */
5497 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5498 return;
5499
5500 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5501
5502 /*
5503 * ssvpc register is cleared on read, if zero then no
5504 * spoofed packets in the last interval.
5505 */
5506 if (!ssvpc)
5507 return;
5508
5509 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5510 }
5511
5512 /**
5513 * ixgbe_watchdog_subtask - check and bring link up
5514 * @adapter - pointer to the device adapter structure
5515 **/
5516 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5517 {
5518 /* if interface is down do nothing */
5519 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5520 test_bit(__IXGBE_RESETTING, &adapter->state))
5521 return;
5522
5523 ixgbe_watchdog_update_link(adapter);
5524
5525 if (adapter->link_up)
5526 ixgbe_watchdog_link_is_up(adapter);
5527 else
5528 ixgbe_watchdog_link_is_down(adapter);
5529
5530 ixgbe_spoof_check(adapter);
5531 ixgbe_update_stats(adapter);
5532
5533 ixgbe_watchdog_flush_tx(adapter);
5534 }
5535
5536 /**
5537 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5538 * @adapter - the ixgbe adapter structure
5539 **/
5540 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5541 {
5542 struct ixgbe_hw *hw = &adapter->hw;
5543 s32 err;
5544
5545 /* not searching for SFP so there is nothing to do here */
5546 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5547 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5548 return;
5549
5550 /* someone else is in init, wait until next service event */
5551 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5552 return;
5553
5554 err = hw->phy.ops.identify_sfp(hw);
5555 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5556 goto sfp_out;
5557
5558 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5559 /* If no cable is present, then we need to reset
5560 * the next time we find a good cable. */
5561 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5562 }
5563
5564 /* exit on error */
5565 if (err)
5566 goto sfp_out;
5567
5568 /* exit if reset not needed */
5569 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5570 goto sfp_out;
5571
5572 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5573
5574 /*
5575 * A module may be identified correctly, but the EEPROM may not have
5576 * support for that module. setup_sfp() will fail in that case, so
5577 * we should not allow that module to load.
5578 */
5579 if (hw->mac.type == ixgbe_mac_82598EB)
5580 err = hw->phy.ops.reset(hw);
5581 else
5582 err = hw->mac.ops.setup_sfp(hw);
5583
5584 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5585 goto sfp_out;
5586
5587 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5588 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5589
5590 sfp_out:
5591 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5592
5593 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5594 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5595 e_dev_err("failed to initialize because an unsupported "
5596 "SFP+ module type was detected.\n");
5597 e_dev_err("Reload the driver after installing a "
5598 "supported module.\n");
5599 unregister_netdev(adapter->netdev);
5600 }
5601 }
5602
5603 /**
5604 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5605 * @adapter - the ixgbe adapter structure
5606 **/
5607 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5608 {
5609 struct ixgbe_hw *hw = &adapter->hw;
5610 u32 autoneg;
5611 bool negotiation;
5612
5613 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5614 return;
5615
5616 /* someone else is in init, wait until next service event */
5617 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5618 return;
5619
5620 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5621
5622 autoneg = hw->phy.autoneg_advertised;
5623 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5624 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5625 if (hw->mac.ops.setup_link)
5626 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5627
5628 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5629 adapter->link_check_timeout = jiffies;
5630 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5631 }
5632
5633 #ifdef CONFIG_PCI_IOV
5634 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5635 {
5636 int vf;
5637 struct ixgbe_hw *hw = &adapter->hw;
5638 struct net_device *netdev = adapter->netdev;
5639 u32 gpc;
5640 u32 ciaa, ciad;
5641
5642 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5643 if (gpc) /* If incrementing then no need for the check below */
5644 return;
5645 /*
5646 * Check to see if a bad DMA write target from an errant or
5647 * malicious VF has caused a PCIe error. If so then we can
5648 * issue a VFLR to the offending VF(s) and then resume without
5649 * requesting a full slot reset.
5650 */
5651
5652 for (vf = 0; vf < adapter->num_vfs; vf++) {
5653 ciaa = (vf << 16) | 0x80000000;
5654 /* 32 bit read so align, we really want status at offset 6 */
5655 ciaa |= PCI_COMMAND;
5656 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5657 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5658 ciaa &= 0x7FFFFFFF;
5659 /* disable debug mode asap after reading data */
5660 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5661 /* Get the upper 16 bits which will be the PCI status reg */
5662 ciad >>= 16;
5663 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5664 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5665 /* Issue VFLR */
5666 ciaa = (vf << 16) | 0x80000000;
5667 ciaa |= 0xA8;
5668 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5669 ciad = 0x00008000; /* VFLR */
5670 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5671 ciaa &= 0x7FFFFFFF;
5672 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5673 }
5674 }
5675 }
5676
5677 #endif
5678 /**
5679 * ixgbe_service_timer - Timer Call-back
5680 * @data: pointer to adapter cast into an unsigned long
5681 **/
5682 static void ixgbe_service_timer(unsigned long data)
5683 {
5684 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5685 unsigned long next_event_offset;
5686 bool ready = true;
5687
5688 /* poll faster when waiting for link */
5689 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5690 next_event_offset = HZ / 10;
5691 else
5692 next_event_offset = HZ * 2;
5693
5694 #ifdef CONFIG_PCI_IOV
5695 /*
5696 * don't bother with SR-IOV VF DMA hang check if there are
5697 * no VFs or the link is down
5698 */
5699 if (!adapter->num_vfs ||
5700 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5701 goto normal_timer_service;
5702
5703 /* If we have VFs allocated then we must check for DMA hangs */
5704 ixgbe_check_for_bad_vf(adapter);
5705 next_event_offset = HZ / 50;
5706 adapter->timer_event_accumulator++;
5707
5708 if (adapter->timer_event_accumulator >= 100)
5709 adapter->timer_event_accumulator = 0;
5710 else
5711 ready = false;
5712
5713 normal_timer_service:
5714 #endif
5715 /* Reset the timer */
5716 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5717
5718 if (ready)
5719 ixgbe_service_event_schedule(adapter);
5720 }
5721
5722 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5723 {
5724 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5725 return;
5726
5727 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5728
5729 /* If we're already down or resetting, just bail */
5730 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5731 test_bit(__IXGBE_RESETTING, &adapter->state))
5732 return;
5733
5734 ixgbe_dump(adapter);
5735 netdev_err(adapter->netdev, "Reset adapter\n");
5736 adapter->tx_timeout_count++;
5737
5738 ixgbe_reinit_locked(adapter);
5739 }
5740
5741 /**
5742 * ixgbe_service_task - manages and runs subtasks
5743 * @work: pointer to work_struct containing our data
5744 **/
5745 static void ixgbe_service_task(struct work_struct *work)
5746 {
5747 struct ixgbe_adapter *adapter = container_of(work,
5748 struct ixgbe_adapter,
5749 service_task);
5750
5751 ixgbe_reset_subtask(adapter);
5752 ixgbe_sfp_detection_subtask(adapter);
5753 ixgbe_sfp_link_config_subtask(adapter);
5754 ixgbe_check_overtemp_subtask(adapter);
5755 ixgbe_watchdog_subtask(adapter);
5756 ixgbe_fdir_reinit_subtask(adapter);
5757 ixgbe_check_hang_subtask(adapter);
5758 #ifdef CONFIG_IXGBE_PTP
5759 ixgbe_ptp_overflow_check(adapter);
5760 #endif
5761
5762 ixgbe_service_event_complete(adapter);
5763 }
5764
5765 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5766 struct ixgbe_tx_buffer *first,
5767 u8 *hdr_len)
5768 {
5769 struct sk_buff *skb = first->skb;
5770 u32 vlan_macip_lens, type_tucmd;
5771 u32 mss_l4len_idx, l4len;
5772
5773 if (!skb_is_gso(skb))
5774 return 0;
5775
5776 if (skb_header_cloned(skb)) {
5777 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5778 if (err)
5779 return err;
5780 }
5781
5782 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5783 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5784
5785 if (first->protocol == __constant_htons(ETH_P_IP)) {
5786 struct iphdr *iph = ip_hdr(skb);
5787 iph->tot_len = 0;
5788 iph->check = 0;
5789 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5790 iph->daddr, 0,
5791 IPPROTO_TCP,
5792 0);
5793 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5794 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5795 IXGBE_TX_FLAGS_CSUM |
5796 IXGBE_TX_FLAGS_IPV4;
5797 } else if (skb_is_gso_v6(skb)) {
5798 ipv6_hdr(skb)->payload_len = 0;
5799 tcp_hdr(skb)->check =
5800 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5801 &ipv6_hdr(skb)->daddr,
5802 0, IPPROTO_TCP, 0);
5803 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5804 IXGBE_TX_FLAGS_CSUM;
5805 }
5806
5807 /* compute header lengths */
5808 l4len = tcp_hdrlen(skb);
5809 *hdr_len = skb_transport_offset(skb) + l4len;
5810
5811 /* update gso size and bytecount with header size */
5812 first->gso_segs = skb_shinfo(skb)->gso_segs;
5813 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5814
5815 /* mss_l4len_id: use 1 as index for TSO */
5816 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5817 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5818 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5819
5820 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5821 vlan_macip_lens = skb_network_header_len(skb);
5822 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5823 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5824
5825 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
5826 mss_l4len_idx);
5827
5828 return 1;
5829 }
5830
5831 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5832 struct ixgbe_tx_buffer *first)
5833 {
5834 struct sk_buff *skb = first->skb;
5835 u32 vlan_macip_lens = 0;
5836 u32 mss_l4len_idx = 0;
5837 u32 type_tucmd = 0;
5838
5839 if (skb->ip_summed != CHECKSUM_PARTIAL) {
5840 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
5841 !(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5842 return;
5843 } else {
5844 u8 l4_hdr = 0;
5845 switch (first->protocol) {
5846 case __constant_htons(ETH_P_IP):
5847 vlan_macip_lens |= skb_network_header_len(skb);
5848 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5849 l4_hdr = ip_hdr(skb)->protocol;
5850 break;
5851 case __constant_htons(ETH_P_IPV6):
5852 vlan_macip_lens |= skb_network_header_len(skb);
5853 l4_hdr = ipv6_hdr(skb)->nexthdr;
5854 break;
5855 default:
5856 if (unlikely(net_ratelimit())) {
5857 dev_warn(tx_ring->dev,
5858 "partial checksum but proto=%x!\n",
5859 first->protocol);
5860 }
5861 break;
5862 }
5863
5864 switch (l4_hdr) {
5865 case IPPROTO_TCP:
5866 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5867 mss_l4len_idx = tcp_hdrlen(skb) <<
5868 IXGBE_ADVTXD_L4LEN_SHIFT;
5869 break;
5870 case IPPROTO_SCTP:
5871 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5872 mss_l4len_idx = sizeof(struct sctphdr) <<
5873 IXGBE_ADVTXD_L4LEN_SHIFT;
5874 break;
5875 case IPPROTO_UDP:
5876 mss_l4len_idx = sizeof(struct udphdr) <<
5877 IXGBE_ADVTXD_L4LEN_SHIFT;
5878 break;
5879 default:
5880 if (unlikely(net_ratelimit())) {
5881 dev_warn(tx_ring->dev,
5882 "partial checksum but l4 proto=%x!\n",
5883 l4_hdr);
5884 }
5885 break;
5886 }
5887
5888 /* update TX checksum flag */
5889 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
5890 }
5891
5892 /* vlan_macip_lens: MACLEN, VLAN tag */
5893 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5894 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5895
5896 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
5897 type_tucmd, mss_l4len_idx);
5898 }
5899
5900 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
5901 {
5902 /* set type for advanced descriptor with frame checksum insertion */
5903 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
5904 IXGBE_ADVTXD_DCMD_IFCS |
5905 IXGBE_ADVTXD_DCMD_DEXT);
5906
5907 /* set HW vlan bit if vlan is present */
5908 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
5909 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
5910
5911 #ifdef CONFIG_IXGBE_PTP
5912 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP)
5913 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP);
5914 #endif
5915
5916 /* set segmentation enable bits for TSO/FSO */
5917 #ifdef IXGBE_FCOE
5918 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
5919 #else
5920 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5921 #endif
5922 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
5923
5924 return cmd_type;
5925 }
5926
5927 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
5928 u32 tx_flags, unsigned int paylen)
5929 {
5930 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
5931
5932 /* enable L4 checksum for TSO and TX checksum offload */
5933 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5934 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
5935
5936 /* enble IPv4 checksum for TSO */
5937 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5938 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
5939
5940 /* use index 1 context for TSO/FSO/FCOE */
5941 #ifdef IXGBE_FCOE
5942 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
5943 #else
5944 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5945 #endif
5946 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
5947
5948 /*
5949 * Check Context must be set if Tx switch is enabled, which it
5950 * always is for case where virtual functions are running
5951 */
5952 #ifdef IXGBE_FCOE
5953 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
5954 #else
5955 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
5956 #endif
5957 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
5958
5959 tx_desc->read.olinfo_status = olinfo_status;
5960 }
5961
5962 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
5963 IXGBE_TXD_CMD_RS)
5964
5965 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
5966 struct ixgbe_tx_buffer *first,
5967 const u8 hdr_len)
5968 {
5969 dma_addr_t dma;
5970 struct sk_buff *skb = first->skb;
5971 struct ixgbe_tx_buffer *tx_buffer;
5972 union ixgbe_adv_tx_desc *tx_desc;
5973 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
5974 unsigned int data_len = skb->data_len;
5975 unsigned int size = skb_headlen(skb);
5976 unsigned int paylen = skb->len - hdr_len;
5977 u32 tx_flags = first->tx_flags;
5978 __le32 cmd_type;
5979 u16 i = tx_ring->next_to_use;
5980
5981 tx_desc = IXGBE_TX_DESC(tx_ring, i);
5982
5983 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
5984 cmd_type = ixgbe_tx_cmd_type(tx_flags);
5985
5986 #ifdef IXGBE_FCOE
5987 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5988 if (data_len < sizeof(struct fcoe_crc_eof)) {
5989 size -= sizeof(struct fcoe_crc_eof) - data_len;
5990 data_len = 0;
5991 } else {
5992 data_len -= sizeof(struct fcoe_crc_eof);
5993 }
5994 }
5995
5996 #endif
5997 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
5998 if (dma_mapping_error(tx_ring->dev, dma))
5999 goto dma_error;
6000
6001 /* record length, and DMA address */
6002 dma_unmap_len_set(first, len, size);
6003 dma_unmap_addr_set(first, dma, dma);
6004
6005 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6006
6007 for (;;) {
6008 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6009 tx_desc->read.cmd_type_len =
6010 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6011
6012 i++;
6013 tx_desc++;
6014 if (i == tx_ring->count) {
6015 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6016 i = 0;
6017 }
6018
6019 dma += IXGBE_MAX_DATA_PER_TXD;
6020 size -= IXGBE_MAX_DATA_PER_TXD;
6021
6022 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6023 tx_desc->read.olinfo_status = 0;
6024 }
6025
6026 if (likely(!data_len))
6027 break;
6028
6029 if (unlikely(skb->no_fcs))
6030 cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS));
6031 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6032
6033 i++;
6034 tx_desc++;
6035 if (i == tx_ring->count) {
6036 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6037 i = 0;
6038 }
6039
6040 #ifdef IXGBE_FCOE
6041 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6042 #else
6043 size = skb_frag_size(frag);
6044 #endif
6045 data_len -= size;
6046
6047 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6048 DMA_TO_DEVICE);
6049 if (dma_mapping_error(tx_ring->dev, dma))
6050 goto dma_error;
6051
6052 tx_buffer = &tx_ring->tx_buffer_info[i];
6053 dma_unmap_len_set(tx_buffer, len, size);
6054 dma_unmap_addr_set(tx_buffer, dma, dma);
6055
6056 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6057 tx_desc->read.olinfo_status = 0;
6058
6059 frag++;
6060 }
6061
6062 /* write last descriptor with RS and EOP bits */
6063 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6064 tx_desc->read.cmd_type_len = cmd_type;
6065
6066 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6067
6068 /* set the timestamp */
6069 first->time_stamp = jiffies;
6070
6071 /*
6072 * Force memory writes to complete before letting h/w know there
6073 * are new descriptors to fetch. (Only applicable for weak-ordered
6074 * memory model archs, such as IA-64).
6075 *
6076 * We also need this memory barrier to make certain all of the
6077 * status bits have been updated before next_to_watch is written.
6078 */
6079 wmb();
6080
6081 /* set next_to_watch value indicating a packet is present */
6082 first->next_to_watch = tx_desc;
6083
6084 i++;
6085 if (i == tx_ring->count)
6086 i = 0;
6087
6088 tx_ring->next_to_use = i;
6089
6090 /* notify HW of packet */
6091 writel(i, tx_ring->tail);
6092
6093 return;
6094 dma_error:
6095 dev_err(tx_ring->dev, "TX DMA map failed\n");
6096
6097 /* clear dma mappings for failed tx_buffer_info map */
6098 for (;;) {
6099 tx_buffer = &tx_ring->tx_buffer_info[i];
6100 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6101 if (tx_buffer == first)
6102 break;
6103 if (i == 0)
6104 i = tx_ring->count;
6105 i--;
6106 }
6107
6108 tx_ring->next_to_use = i;
6109 }
6110
6111 static void ixgbe_atr(struct ixgbe_ring *ring,
6112 struct ixgbe_tx_buffer *first)
6113 {
6114 struct ixgbe_q_vector *q_vector = ring->q_vector;
6115 union ixgbe_atr_hash_dword input = { .dword = 0 };
6116 union ixgbe_atr_hash_dword common = { .dword = 0 };
6117 union {
6118 unsigned char *network;
6119 struct iphdr *ipv4;
6120 struct ipv6hdr *ipv6;
6121 } hdr;
6122 struct tcphdr *th;
6123 __be16 vlan_id;
6124
6125 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6126 if (!q_vector)
6127 return;
6128
6129 /* do nothing if sampling is disabled */
6130 if (!ring->atr_sample_rate)
6131 return;
6132
6133 ring->atr_count++;
6134
6135 /* snag network header to get L4 type and address */
6136 hdr.network = skb_network_header(first->skb);
6137
6138 /* Currently only IPv4/IPv6 with TCP is supported */
6139 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6140 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6141 (first->protocol != __constant_htons(ETH_P_IP) ||
6142 hdr.ipv4->protocol != IPPROTO_TCP))
6143 return;
6144
6145 th = tcp_hdr(first->skb);
6146
6147 /* skip this packet since it is invalid or the socket is closing */
6148 if (!th || th->fin)
6149 return;
6150
6151 /* sample on all syn packets or once every atr sample count */
6152 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6153 return;
6154
6155 /* reset sample count */
6156 ring->atr_count = 0;
6157
6158 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6159
6160 /*
6161 * src and dst are inverted, think how the receiver sees them
6162 *
6163 * The input is broken into two sections, a non-compressed section
6164 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6165 * is XORed together and stored in the compressed dword.
6166 */
6167 input.formatted.vlan_id = vlan_id;
6168
6169 /*
6170 * since src port and flex bytes occupy the same word XOR them together
6171 * and write the value to source port portion of compressed dword
6172 */
6173 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6174 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6175 else
6176 common.port.src ^= th->dest ^ first->protocol;
6177 common.port.dst ^= th->source;
6178
6179 if (first->protocol == __constant_htons(ETH_P_IP)) {
6180 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6181 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6182 } else {
6183 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6184 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6185 hdr.ipv6->saddr.s6_addr32[1] ^
6186 hdr.ipv6->saddr.s6_addr32[2] ^
6187 hdr.ipv6->saddr.s6_addr32[3] ^
6188 hdr.ipv6->daddr.s6_addr32[0] ^
6189 hdr.ipv6->daddr.s6_addr32[1] ^
6190 hdr.ipv6->daddr.s6_addr32[2] ^
6191 hdr.ipv6->daddr.s6_addr32[3];
6192 }
6193
6194 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6195 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6196 input, common, ring->queue_index);
6197 }
6198
6199 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6200 {
6201 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6202 /* Herbert's original patch had:
6203 * smp_mb__after_netif_stop_queue();
6204 * but since that doesn't exist yet, just open code it. */
6205 smp_mb();
6206
6207 /* We need to check again in a case another CPU has just
6208 * made room available. */
6209 if (likely(ixgbe_desc_unused(tx_ring) < size))
6210 return -EBUSY;
6211
6212 /* A reprieve! - use start_queue because it doesn't call schedule */
6213 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6214 ++tx_ring->tx_stats.restart_queue;
6215 return 0;
6216 }
6217
6218 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6219 {
6220 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6221 return 0;
6222 return __ixgbe_maybe_stop_tx(tx_ring, size);
6223 }
6224
6225 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6226 {
6227 struct ixgbe_adapter *adapter = netdev_priv(dev);
6228 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6229 smp_processor_id();
6230 #ifdef IXGBE_FCOE
6231 __be16 protocol = vlan_get_protocol(skb);
6232
6233 if (((protocol == htons(ETH_P_FCOE)) ||
6234 (protocol == htons(ETH_P_FIP))) &&
6235 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6236 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6237 txq += adapter->ring_feature[RING_F_FCOE].mask;
6238 return txq;
6239 }
6240 #endif
6241
6242 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6243 while (unlikely(txq >= dev->real_num_tx_queues))
6244 txq -= dev->real_num_tx_queues;
6245 return txq;
6246 }
6247
6248 return skb_tx_hash(dev, skb);
6249 }
6250
6251 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6252 struct ixgbe_adapter *adapter,
6253 struct ixgbe_ring *tx_ring)
6254 {
6255 struct ixgbe_tx_buffer *first;
6256 int tso;
6257 u32 tx_flags = 0;
6258 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6259 unsigned short f;
6260 #endif
6261 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6262 __be16 protocol = skb->protocol;
6263 u8 hdr_len = 0;
6264
6265 /*
6266 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6267 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6268 * + 2 desc gap to keep tail from touching head,
6269 * + 1 desc for context descriptor,
6270 * otherwise try next time
6271 */
6272 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6273 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6274 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6275 #else
6276 count += skb_shinfo(skb)->nr_frags;
6277 #endif
6278 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6279 tx_ring->tx_stats.tx_busy++;
6280 return NETDEV_TX_BUSY;
6281 }
6282
6283 /* record the location of the first descriptor for this packet */
6284 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6285 first->skb = skb;
6286 first->bytecount = skb->len;
6287 first->gso_segs = 1;
6288
6289 /* if we have a HW VLAN tag being added default to the HW one */
6290 if (vlan_tx_tag_present(skb)) {
6291 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6292 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6293 /* else if it is a SW VLAN check the next protocol and store the tag */
6294 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6295 struct vlan_hdr *vhdr, _vhdr;
6296 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6297 if (!vhdr)
6298 goto out_drop;
6299
6300 protocol = vhdr->h_vlan_encapsulated_proto;
6301 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6302 IXGBE_TX_FLAGS_VLAN_SHIFT;
6303 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6304 }
6305
6306 skb_tx_timestamp(skb);
6307
6308 #ifdef CONFIG_IXGBE_PTP
6309 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6310 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6311 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6312 }
6313 #endif
6314
6315 #ifdef CONFIG_PCI_IOV
6316 /*
6317 * Use the l2switch_enable flag - would be false if the DMA
6318 * Tx switch had been disabled.
6319 */
6320 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6321 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6322
6323 #endif
6324 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6325 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6326 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6327 (skb->priority != TC_PRIO_CONTROL))) {
6328 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6329 tx_flags |= (skb->priority & 0x7) <<
6330 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6331 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6332 struct vlan_ethhdr *vhdr;
6333 if (skb_header_cloned(skb) &&
6334 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6335 goto out_drop;
6336 vhdr = (struct vlan_ethhdr *)skb->data;
6337 vhdr->h_vlan_TCI = htons(tx_flags >>
6338 IXGBE_TX_FLAGS_VLAN_SHIFT);
6339 } else {
6340 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6341 }
6342 }
6343
6344 /* record initial flags and protocol */
6345 first->tx_flags = tx_flags;
6346 first->protocol = protocol;
6347
6348 #ifdef IXGBE_FCOE
6349 /* setup tx offload for FCoE */
6350 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6351 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6352 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6353 if (tso < 0)
6354 goto out_drop;
6355
6356 goto xmit_fcoe;
6357 }
6358
6359 #endif /* IXGBE_FCOE */
6360 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6361 if (tso < 0)
6362 goto out_drop;
6363 else if (!tso)
6364 ixgbe_tx_csum(tx_ring, first);
6365
6366 /* add the ATR filter if ATR is on */
6367 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6368 ixgbe_atr(tx_ring, first);
6369
6370 #ifdef IXGBE_FCOE
6371 xmit_fcoe:
6372 #endif /* IXGBE_FCOE */
6373 ixgbe_tx_map(tx_ring, first, hdr_len);
6374
6375 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6376
6377 return NETDEV_TX_OK;
6378
6379 out_drop:
6380 dev_kfree_skb_any(first->skb);
6381 first->skb = NULL;
6382
6383 return NETDEV_TX_OK;
6384 }
6385
6386 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6387 struct net_device *netdev)
6388 {
6389 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6390 struct ixgbe_ring *tx_ring;
6391
6392 if (skb->len <= 0) {
6393 dev_kfree_skb_any(skb);
6394 return NETDEV_TX_OK;
6395 }
6396
6397 /*
6398 * The minimum packet size for olinfo paylen is 17 so pad the skb
6399 * in order to meet this minimum size requirement.
6400 */
6401 if (skb->len < 17) {
6402 if (skb_padto(skb, 17))
6403 return NETDEV_TX_OK;
6404 skb->len = 17;
6405 }
6406
6407 tx_ring = adapter->tx_ring[skb->queue_mapping];
6408 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6409 }
6410
6411 /**
6412 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6413 * @netdev: network interface device structure
6414 * @p: pointer to an address structure
6415 *
6416 * Returns 0 on success, negative on failure
6417 **/
6418 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6419 {
6420 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6421 struct ixgbe_hw *hw = &adapter->hw;
6422 struct sockaddr *addr = p;
6423
6424 if (!is_valid_ether_addr(addr->sa_data))
6425 return -EADDRNOTAVAIL;
6426
6427 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6428 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6429
6430 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6431 IXGBE_RAH_AV);
6432
6433 return 0;
6434 }
6435
6436 static int
6437 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6438 {
6439 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6440 struct ixgbe_hw *hw = &adapter->hw;
6441 u16 value;
6442 int rc;
6443
6444 if (prtad != hw->phy.mdio.prtad)
6445 return -EINVAL;
6446 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6447 if (!rc)
6448 rc = value;
6449 return rc;
6450 }
6451
6452 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6453 u16 addr, u16 value)
6454 {
6455 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6456 struct ixgbe_hw *hw = &adapter->hw;
6457
6458 if (prtad != hw->phy.mdio.prtad)
6459 return -EINVAL;
6460 return hw->phy.ops.write_reg(hw, addr, devad, value);
6461 }
6462
6463 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6464 {
6465 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6466
6467 switch (cmd) {
6468 #ifdef CONFIG_IXGBE_PTP
6469 case SIOCSHWTSTAMP:
6470 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6471 #endif
6472 default:
6473 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6474 }
6475 }
6476
6477 /**
6478 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6479 * netdev->dev_addrs
6480 * @netdev: network interface device structure
6481 *
6482 * Returns non-zero on failure
6483 **/
6484 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6485 {
6486 int err = 0;
6487 struct ixgbe_adapter *adapter = netdev_priv(dev);
6488 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6489
6490 if (is_valid_ether_addr(mac->san_addr)) {
6491 rtnl_lock();
6492 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6493 rtnl_unlock();
6494 }
6495 return err;
6496 }
6497
6498 /**
6499 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6500 * netdev->dev_addrs
6501 * @netdev: network interface device structure
6502 *
6503 * Returns non-zero on failure
6504 **/
6505 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6506 {
6507 int err = 0;
6508 struct ixgbe_adapter *adapter = netdev_priv(dev);
6509 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6510
6511 if (is_valid_ether_addr(mac->san_addr)) {
6512 rtnl_lock();
6513 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6514 rtnl_unlock();
6515 }
6516 return err;
6517 }
6518
6519 #ifdef CONFIG_NET_POLL_CONTROLLER
6520 /*
6521 * Polling 'interrupt' - used by things like netconsole to send skbs
6522 * without having to re-enable interrupts. It's not called while
6523 * the interrupt routine is executing.
6524 */
6525 static void ixgbe_netpoll(struct net_device *netdev)
6526 {
6527 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6528 int i;
6529
6530 /* if interface is down do nothing */
6531 if (test_bit(__IXGBE_DOWN, &adapter->state))
6532 return;
6533
6534 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6535 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6536 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6537 for (i = 0; i < num_q_vectors; i++) {
6538 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6539 ixgbe_msix_clean_rings(0, q_vector);
6540 }
6541 } else {
6542 ixgbe_intr(adapter->pdev->irq, netdev);
6543 }
6544 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6545 }
6546
6547 #endif
6548 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6549 struct rtnl_link_stats64 *stats)
6550 {
6551 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6552 int i;
6553
6554 rcu_read_lock();
6555 for (i = 0; i < adapter->num_rx_queues; i++) {
6556 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6557 u64 bytes, packets;
6558 unsigned int start;
6559
6560 if (ring) {
6561 do {
6562 start = u64_stats_fetch_begin_bh(&ring->syncp);
6563 packets = ring->stats.packets;
6564 bytes = ring->stats.bytes;
6565 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6566 stats->rx_packets += packets;
6567 stats->rx_bytes += bytes;
6568 }
6569 }
6570
6571 for (i = 0; i < adapter->num_tx_queues; i++) {
6572 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6573 u64 bytes, packets;
6574 unsigned int start;
6575
6576 if (ring) {
6577 do {
6578 start = u64_stats_fetch_begin_bh(&ring->syncp);
6579 packets = ring->stats.packets;
6580 bytes = ring->stats.bytes;
6581 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6582 stats->tx_packets += packets;
6583 stats->tx_bytes += bytes;
6584 }
6585 }
6586 rcu_read_unlock();
6587 /* following stats updated by ixgbe_watchdog_task() */
6588 stats->multicast = netdev->stats.multicast;
6589 stats->rx_errors = netdev->stats.rx_errors;
6590 stats->rx_length_errors = netdev->stats.rx_length_errors;
6591 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6592 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6593 return stats;
6594 }
6595
6596 #ifdef CONFIG_IXGBE_DCB
6597 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6598 * #adapter: pointer to ixgbe_adapter
6599 * @tc: number of traffic classes currently enabled
6600 *
6601 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6602 * 802.1Q priority maps to a packet buffer that exists.
6603 */
6604 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6605 {
6606 struct ixgbe_hw *hw = &adapter->hw;
6607 u32 reg, rsave;
6608 int i;
6609
6610 /* 82598 have a static priority to TC mapping that can not
6611 * be changed so no validation is needed.
6612 */
6613 if (hw->mac.type == ixgbe_mac_82598EB)
6614 return;
6615
6616 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6617 rsave = reg;
6618
6619 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6620 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6621
6622 /* If up2tc is out of bounds default to zero */
6623 if (up2tc > tc)
6624 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6625 }
6626
6627 if (reg != rsave)
6628 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6629
6630 return;
6631 }
6632
6633 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
6634 * classes.
6635 *
6636 * @netdev: net device to configure
6637 * @tc: number of traffic classes to enable
6638 */
6639 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6640 {
6641 struct ixgbe_adapter *adapter = netdev_priv(dev);
6642 struct ixgbe_hw *hw = &adapter->hw;
6643
6644 /* Multiple traffic classes requires multiple queues */
6645 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6646 e_err(drv, "Enable failed, needs MSI-X\n");
6647 return -EINVAL;
6648 }
6649
6650 /* Hardware supports up to 8 traffic classes */
6651 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
6652 (hw->mac.type == ixgbe_mac_82598EB &&
6653 tc < MAX_TRAFFIC_CLASS))
6654 return -EINVAL;
6655
6656 /* Hardware has to reinitialize queues and interrupts to
6657 * match packet buffer alignment. Unfortunately, the
6658 * hardware is not flexible enough to do this dynamically.
6659 */
6660 if (netif_running(dev))
6661 ixgbe_close(dev);
6662 ixgbe_clear_interrupt_scheme(adapter);
6663
6664 if (tc) {
6665 netdev_set_num_tc(dev, tc);
6666 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6667 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6668
6669 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6670 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
6671 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6672 }
6673 } else {
6674 netdev_reset_tc(dev);
6675 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6676 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6677
6678 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6679 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6680
6681 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6682 adapter->dcb_cfg.pfc_mode_enable = false;
6683 }
6684
6685 ixgbe_init_interrupt_scheme(adapter);
6686 ixgbe_validate_rtr(adapter, tc);
6687 if (netif_running(dev))
6688 ixgbe_open(dev);
6689
6690 return 0;
6691 }
6692
6693 #endif /* CONFIG_IXGBE_DCB */
6694 void ixgbe_do_reset(struct net_device *netdev)
6695 {
6696 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6697
6698 if (netif_running(netdev))
6699 ixgbe_reinit_locked(adapter);
6700 else
6701 ixgbe_reset(adapter);
6702 }
6703
6704 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
6705 netdev_features_t features)
6706 {
6707 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6708
6709 /* return error if RXHASH is being enabled when RSS is not supported */
6710 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
6711 features &= ~NETIF_F_RXHASH;
6712
6713 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6714 if (!(features & NETIF_F_RXCSUM))
6715 features &= ~NETIF_F_LRO;
6716
6717 /* Turn off LRO if not RSC capable */
6718 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6719 features &= ~NETIF_F_LRO;
6720
6721 return features;
6722 }
6723
6724 static int ixgbe_set_features(struct net_device *netdev,
6725 netdev_features_t features)
6726 {
6727 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6728 netdev_features_t changed = netdev->features ^ features;
6729 bool need_reset = false;
6730
6731 /* Make sure RSC matches LRO, reset if change */
6732 if (!(features & NETIF_F_LRO)) {
6733 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6734 need_reset = true;
6735 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6736 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6737 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6738 if (adapter->rx_itr_setting == 1 ||
6739 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6740 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6741 need_reset = true;
6742 } else if ((changed ^ features) & NETIF_F_LRO) {
6743 e_info(probe, "rx-usecs set too low, "
6744 "disabling RSC\n");
6745 }
6746 }
6747
6748 /*
6749 * Check if Flow Director n-tuple support was enabled or disabled. If
6750 * the state changed, we need to reset.
6751 */
6752 if (!(features & NETIF_F_NTUPLE)) {
6753 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
6754 /* turn off Flow Director, set ATR and reset */
6755 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
6756 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
6757 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6758 need_reset = true;
6759 }
6760 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6761 } else if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
6762 /* turn off ATR, enable perfect filters and reset */
6763 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6764 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6765 need_reset = true;
6766 }
6767
6768 if (features & NETIF_F_HW_VLAN_RX)
6769 ixgbe_vlan_strip_enable(adapter);
6770 else
6771 ixgbe_vlan_strip_disable(adapter);
6772
6773 if (changed & NETIF_F_RXALL)
6774 need_reset = true;
6775
6776 netdev->features = features;
6777 if (need_reset)
6778 ixgbe_do_reset(netdev);
6779
6780 return 0;
6781 }
6782
6783 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm,
6784 struct net_device *dev,
6785 unsigned char *addr,
6786 u16 flags)
6787 {
6788 struct ixgbe_adapter *adapter = netdev_priv(dev);
6789 int err = -EOPNOTSUPP;
6790
6791 if (ndm->ndm_state & NUD_PERMANENT) {
6792 pr_info("%s: FDB only supports static addresses\n",
6793 ixgbe_driver_name);
6794 return -EINVAL;
6795 }
6796
6797 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6798 if (is_unicast_ether_addr(addr))
6799 err = dev_uc_add_excl(dev, addr);
6800 else if (is_multicast_ether_addr(addr))
6801 err = dev_mc_add_excl(dev, addr);
6802 else
6803 err = -EINVAL;
6804 }
6805
6806 /* Only return duplicate errors if NLM_F_EXCL is set */
6807 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6808 err = 0;
6809
6810 return err;
6811 }
6812
6813 static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
6814 struct net_device *dev,
6815 unsigned char *addr)
6816 {
6817 struct ixgbe_adapter *adapter = netdev_priv(dev);
6818 int err = -EOPNOTSUPP;
6819
6820 if (ndm->ndm_state & NUD_PERMANENT) {
6821 pr_info("%s: FDB only supports static addresses\n",
6822 ixgbe_driver_name);
6823 return -EINVAL;
6824 }
6825
6826 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6827 if (is_unicast_ether_addr(addr))
6828 err = dev_uc_del(dev, addr);
6829 else if (is_multicast_ether_addr(addr))
6830 err = dev_mc_del(dev, addr);
6831 else
6832 err = -EINVAL;
6833 }
6834
6835 return err;
6836 }
6837
6838 static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
6839 struct netlink_callback *cb,
6840 struct net_device *dev,
6841 int idx)
6842 {
6843 struct ixgbe_adapter *adapter = netdev_priv(dev);
6844
6845 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6846 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
6847
6848 return idx;
6849 }
6850
6851 static const struct net_device_ops ixgbe_netdev_ops = {
6852 .ndo_open = ixgbe_open,
6853 .ndo_stop = ixgbe_close,
6854 .ndo_start_xmit = ixgbe_xmit_frame,
6855 .ndo_select_queue = ixgbe_select_queue,
6856 .ndo_set_rx_mode = ixgbe_set_rx_mode,
6857 .ndo_validate_addr = eth_validate_addr,
6858 .ndo_set_mac_address = ixgbe_set_mac,
6859 .ndo_change_mtu = ixgbe_change_mtu,
6860 .ndo_tx_timeout = ixgbe_tx_timeout,
6861 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6862 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6863 .ndo_do_ioctl = ixgbe_ioctl,
6864 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6865 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6866 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6867 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
6868 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
6869 .ndo_get_stats64 = ixgbe_get_stats64,
6870 #ifdef CONFIG_IXGBE_DCB
6871 .ndo_setup_tc = ixgbe_setup_tc,
6872 #endif
6873 #ifdef CONFIG_NET_POLL_CONTROLLER
6874 .ndo_poll_controller = ixgbe_netpoll,
6875 #endif
6876 #ifdef IXGBE_FCOE
6877 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6878 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
6879 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6880 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6881 .ndo_fcoe_disable = ixgbe_fcoe_disable,
6882 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6883 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
6884 #endif /* IXGBE_FCOE */
6885 .ndo_set_features = ixgbe_set_features,
6886 .ndo_fix_features = ixgbe_fix_features,
6887 .ndo_fdb_add = ixgbe_ndo_fdb_add,
6888 .ndo_fdb_del = ixgbe_ndo_fdb_del,
6889 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
6890 };
6891
6892 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6893 const struct ixgbe_info *ii)
6894 {
6895 #ifdef CONFIG_PCI_IOV
6896 struct ixgbe_hw *hw = &adapter->hw;
6897
6898 if (hw->mac.type == ixgbe_mac_82598EB)
6899 return;
6900
6901 /* The 82599 supports up to 64 VFs per physical function
6902 * but this implementation limits allocation to 63 so that
6903 * basic networking resources are still available to the
6904 * physical function. If the user requests greater thn
6905 * 63 VFs then it is an error - reset to default of zero.
6906 */
6907 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
6908 ixgbe_enable_sriov(adapter, ii);
6909 #endif /* CONFIG_PCI_IOV */
6910 }
6911
6912 /**
6913 * ixgbe_wol_supported - Check whether device supports WoL
6914 * @hw: hw specific details
6915 * @device_id: the device ID
6916 * @subdev_id: the subsystem device ID
6917 *
6918 * This function is used by probe and ethtool to determine
6919 * which devices have WoL support
6920 *
6921 **/
6922 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
6923 u16 subdevice_id)
6924 {
6925 struct ixgbe_hw *hw = &adapter->hw;
6926 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
6927 int is_wol_supported = 0;
6928
6929 switch (device_id) {
6930 case IXGBE_DEV_ID_82599_SFP:
6931 /* Only these subdevices could supports WOL */
6932 switch (subdevice_id) {
6933 case IXGBE_SUBDEV_ID_82599_560FLR:
6934 /* only support first port */
6935 if (hw->bus.func != 0)
6936 break;
6937 case IXGBE_SUBDEV_ID_82599_SFP:
6938 is_wol_supported = 1;
6939 break;
6940 }
6941 break;
6942 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
6943 /* All except this subdevice support WOL */
6944 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
6945 is_wol_supported = 1;
6946 break;
6947 case IXGBE_DEV_ID_82599_KX4:
6948 is_wol_supported = 1;
6949 break;
6950 case IXGBE_DEV_ID_X540T:
6951 /* check eeprom to see if enabled wol */
6952 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
6953 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
6954 (hw->bus.func == 0))) {
6955 is_wol_supported = 1;
6956 }
6957 break;
6958 }
6959
6960 return is_wol_supported;
6961 }
6962
6963 /**
6964 * ixgbe_probe - Device Initialization Routine
6965 * @pdev: PCI device information struct
6966 * @ent: entry in ixgbe_pci_tbl
6967 *
6968 * Returns 0 on success, negative on failure
6969 *
6970 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6971 * The OS initialization, configuring of the adapter private structure,
6972 * and a hardware reset occur.
6973 **/
6974 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6975 const struct pci_device_id *ent)
6976 {
6977 struct net_device *netdev;
6978 struct ixgbe_adapter *adapter = NULL;
6979 struct ixgbe_hw *hw;
6980 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6981 static int cards_found;
6982 int i, err, pci_using_dac;
6983 u8 part_str[IXGBE_PBANUM_LENGTH];
6984 unsigned int indices = num_possible_cpus();
6985 #ifdef IXGBE_FCOE
6986 u16 device_caps;
6987 #endif
6988 u32 eec;
6989
6990 /* Catch broken hardware that put the wrong VF device ID in
6991 * the PCIe SR-IOV capability.
6992 */
6993 if (pdev->is_virtfn) {
6994 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6995 pci_name(pdev), pdev->vendor, pdev->device);
6996 return -EINVAL;
6997 }
6998
6999 err = pci_enable_device_mem(pdev);
7000 if (err)
7001 return err;
7002
7003 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7004 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7005 pci_using_dac = 1;
7006 } else {
7007 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7008 if (err) {
7009 err = dma_set_coherent_mask(&pdev->dev,
7010 DMA_BIT_MASK(32));
7011 if (err) {
7012 dev_err(&pdev->dev,
7013 "No usable DMA configuration, aborting\n");
7014 goto err_dma;
7015 }
7016 }
7017 pci_using_dac = 0;
7018 }
7019
7020 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7021 IORESOURCE_MEM), ixgbe_driver_name);
7022 if (err) {
7023 dev_err(&pdev->dev,
7024 "pci_request_selected_regions failed 0x%x\n", err);
7025 goto err_pci_reg;
7026 }
7027
7028 pci_enable_pcie_error_reporting(pdev);
7029
7030 pci_set_master(pdev);
7031 pci_save_state(pdev);
7032
7033 #ifdef CONFIG_IXGBE_DCB
7034 indices *= MAX_TRAFFIC_CLASS;
7035 #endif
7036
7037 if (ii->mac == ixgbe_mac_82598EB)
7038 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7039 else
7040 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7041
7042 #ifdef IXGBE_FCOE
7043 indices += min_t(unsigned int, num_possible_cpus(),
7044 IXGBE_MAX_FCOE_INDICES);
7045 #endif
7046 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7047 if (!netdev) {
7048 err = -ENOMEM;
7049 goto err_alloc_etherdev;
7050 }
7051
7052 SET_NETDEV_DEV(netdev, &pdev->dev);
7053
7054 adapter = netdev_priv(netdev);
7055 pci_set_drvdata(pdev, adapter);
7056
7057 adapter->netdev = netdev;
7058 adapter->pdev = pdev;
7059 hw = &adapter->hw;
7060 hw->back = adapter;
7061 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7062
7063 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7064 pci_resource_len(pdev, 0));
7065 if (!hw->hw_addr) {
7066 err = -EIO;
7067 goto err_ioremap;
7068 }
7069
7070 for (i = 1; i <= 5; i++) {
7071 if (pci_resource_len(pdev, i) == 0)
7072 continue;
7073 }
7074
7075 netdev->netdev_ops = &ixgbe_netdev_ops;
7076 ixgbe_set_ethtool_ops(netdev);
7077 netdev->watchdog_timeo = 5 * HZ;
7078 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7079
7080 adapter->bd_number = cards_found;
7081
7082 /* Setup hw api */
7083 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7084 hw->mac.type = ii->mac;
7085
7086 /* EEPROM */
7087 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7088 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7089 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7090 if (!(eec & (1 << 8)))
7091 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7092
7093 /* PHY */
7094 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7095 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7096 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7097 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7098 hw->phy.mdio.mmds = 0;
7099 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7100 hw->phy.mdio.dev = netdev;
7101 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7102 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7103
7104 ii->get_invariants(hw);
7105
7106 /* setup the private structure */
7107 err = ixgbe_sw_init(adapter);
7108 if (err)
7109 goto err_sw_init;
7110
7111 /* Make it possible the adapter to be woken up via WOL */
7112 switch (adapter->hw.mac.type) {
7113 case ixgbe_mac_82599EB:
7114 case ixgbe_mac_X540:
7115 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7116 break;
7117 default:
7118 break;
7119 }
7120
7121 /*
7122 * If there is a fan on this device and it has failed log the
7123 * failure.
7124 */
7125 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7126 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7127 if (esdp & IXGBE_ESDP_SDP1)
7128 e_crit(probe, "Fan has stopped, replace the adapter\n");
7129 }
7130
7131 if (allow_unsupported_sfp)
7132 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7133
7134 /* reset_hw fills in the perm_addr as well */
7135 hw->phy.reset_if_overtemp = true;
7136 err = hw->mac.ops.reset_hw(hw);
7137 hw->phy.reset_if_overtemp = false;
7138 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7139 hw->mac.type == ixgbe_mac_82598EB) {
7140 err = 0;
7141 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7142 e_dev_err("failed to load because an unsupported SFP+ "
7143 "module type was detected.\n");
7144 e_dev_err("Reload the driver after installing a supported "
7145 "module.\n");
7146 goto err_sw_init;
7147 } else if (err) {
7148 e_dev_err("HW Init failed: %d\n", err);
7149 goto err_sw_init;
7150 }
7151
7152 ixgbe_probe_vf(adapter, ii);
7153
7154 netdev->features = NETIF_F_SG |
7155 NETIF_F_IP_CSUM |
7156 NETIF_F_IPV6_CSUM |
7157 NETIF_F_HW_VLAN_TX |
7158 NETIF_F_HW_VLAN_RX |
7159 NETIF_F_HW_VLAN_FILTER |
7160 NETIF_F_TSO |
7161 NETIF_F_TSO6 |
7162 NETIF_F_RXHASH |
7163 NETIF_F_RXCSUM;
7164
7165 netdev->hw_features = netdev->features;
7166
7167 switch (adapter->hw.mac.type) {
7168 case ixgbe_mac_82599EB:
7169 case ixgbe_mac_X540:
7170 netdev->features |= NETIF_F_SCTP_CSUM;
7171 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7172 NETIF_F_NTUPLE;
7173 break;
7174 default:
7175 break;
7176 }
7177
7178 netdev->hw_features |= NETIF_F_RXALL;
7179
7180 netdev->vlan_features |= NETIF_F_TSO;
7181 netdev->vlan_features |= NETIF_F_TSO6;
7182 netdev->vlan_features |= NETIF_F_IP_CSUM;
7183 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7184 netdev->vlan_features |= NETIF_F_SG;
7185
7186 netdev->priv_flags |= IFF_UNICAST_FLT;
7187 netdev->priv_flags |= IFF_SUPP_NOFCS;
7188
7189 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7190 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7191 IXGBE_FLAG_DCB_ENABLED);
7192
7193 #ifdef CONFIG_IXGBE_DCB
7194 netdev->dcbnl_ops = &dcbnl_ops;
7195 #endif
7196
7197 #ifdef IXGBE_FCOE
7198 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7199 if (hw->mac.ops.get_device_caps) {
7200 hw->mac.ops.get_device_caps(hw, &device_caps);
7201 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7202 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7203 }
7204 }
7205 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7206 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7207 netdev->vlan_features |= NETIF_F_FSO;
7208 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7209 }
7210 #endif /* IXGBE_FCOE */
7211 if (pci_using_dac) {
7212 netdev->features |= NETIF_F_HIGHDMA;
7213 netdev->vlan_features |= NETIF_F_HIGHDMA;
7214 }
7215
7216 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7217 netdev->hw_features |= NETIF_F_LRO;
7218 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7219 netdev->features |= NETIF_F_LRO;
7220
7221 /* make sure the EEPROM is good */
7222 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7223 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7224 err = -EIO;
7225 goto err_sw_init;
7226 }
7227
7228 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7229 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7230
7231 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7232 e_dev_err("invalid MAC address\n");
7233 err = -EIO;
7234 goto err_sw_init;
7235 }
7236
7237 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7238 (unsigned long) adapter);
7239
7240 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7241 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7242
7243 err = ixgbe_init_interrupt_scheme(adapter);
7244 if (err)
7245 goto err_sw_init;
7246
7247 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7248 netdev->hw_features &= ~NETIF_F_RXHASH;
7249 netdev->features &= ~NETIF_F_RXHASH;
7250 }
7251
7252 /* WOL not supported for all devices */
7253 adapter->wol = 0;
7254 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7255 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
7256 adapter->wol = IXGBE_WUFC_MAG;
7257
7258 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7259
7260 #ifdef CONFIG_IXGBE_PTP
7261 ixgbe_ptp_init(adapter);
7262 #endif /* CONFIG_IXGBE_PTP*/
7263
7264 /* save off EEPROM version number */
7265 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7266 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7267
7268 /* pick up the PCI bus settings for reporting later */
7269 hw->mac.ops.get_bus_info(hw);
7270
7271 /* print bus type/speed/width info */
7272 e_dev_info("(PCI Express:%s:%s) %pM\n",
7273 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7274 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7275 "Unknown"),
7276 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7277 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7278 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7279 "Unknown"),
7280 netdev->dev_addr);
7281
7282 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7283 if (err)
7284 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7285 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7286 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7287 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7288 part_str);
7289 else
7290 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7291 hw->mac.type, hw->phy.type, part_str);
7292
7293 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7294 e_dev_warn("PCI-Express bandwidth available for this card is "
7295 "not sufficient for optimal performance.\n");
7296 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7297 "is required.\n");
7298 }
7299
7300 /* reset the hardware with the new settings */
7301 err = hw->mac.ops.start_hw(hw);
7302 if (err == IXGBE_ERR_EEPROM_VERSION) {
7303 /* We are running on a pre-production device, log a warning */
7304 e_dev_warn("This device is a pre-production adapter/LOM. "
7305 "Please be aware there may be issues associated "
7306 "with your hardware. If you are experiencing "
7307 "problems please contact your Intel or hardware "
7308 "representative who provided you with this "
7309 "hardware.\n");
7310 }
7311 strcpy(netdev->name, "eth%d");
7312 err = register_netdev(netdev);
7313 if (err)
7314 goto err_register;
7315
7316 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7317 if (hw->mac.ops.disable_tx_laser &&
7318 ((hw->phy.multispeed_fiber) ||
7319 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7320 (hw->mac.type == ixgbe_mac_82599EB))))
7321 hw->mac.ops.disable_tx_laser(hw);
7322
7323 /* carrier off reporting is important to ethtool even BEFORE open */
7324 netif_carrier_off(netdev);
7325
7326 #ifdef CONFIG_IXGBE_DCA
7327 if (dca_add_requester(&pdev->dev) == 0) {
7328 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7329 ixgbe_setup_dca(adapter);
7330 }
7331 #endif
7332 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7333 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7334 for (i = 0; i < adapter->num_vfs; i++)
7335 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7336 }
7337
7338 /* firmware requires driver version to be 0xFFFFFFFF
7339 * since os does not support feature
7340 */
7341 if (hw->mac.ops.set_fw_drv_ver)
7342 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7343 0xFF);
7344
7345 /* add san mac addr to netdev */
7346 ixgbe_add_sanmac_netdev(netdev);
7347
7348 e_dev_info("%s\n", ixgbe_default_device_descr);
7349 cards_found++;
7350
7351 #ifdef CONFIG_IXGBE_HWMON
7352 if (ixgbe_sysfs_init(adapter))
7353 e_err(probe, "failed to allocate sysfs resources\n");
7354 #endif /* CONFIG_IXGBE_HWMON */
7355
7356 return 0;
7357
7358 err_register:
7359 ixgbe_release_hw_control(adapter);
7360 ixgbe_clear_interrupt_scheme(adapter);
7361 err_sw_init:
7362 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7363 ixgbe_disable_sriov(adapter);
7364 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7365 iounmap(hw->hw_addr);
7366 err_ioremap:
7367 free_netdev(netdev);
7368 err_alloc_etherdev:
7369 pci_release_selected_regions(pdev,
7370 pci_select_bars(pdev, IORESOURCE_MEM));
7371 err_pci_reg:
7372 err_dma:
7373 pci_disable_device(pdev);
7374 return err;
7375 }
7376
7377 /**
7378 * ixgbe_remove - Device Removal Routine
7379 * @pdev: PCI device information struct
7380 *
7381 * ixgbe_remove is called by the PCI subsystem to alert the driver
7382 * that it should release a PCI device. The could be caused by a
7383 * Hot-Plug event, or because the driver is going to be removed from
7384 * memory.
7385 **/
7386 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7387 {
7388 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7389 struct net_device *netdev = adapter->netdev;
7390
7391 set_bit(__IXGBE_DOWN, &adapter->state);
7392 cancel_work_sync(&adapter->service_task);
7393
7394 #ifdef CONFIG_IXGBE_PTP
7395 ixgbe_ptp_stop(adapter);
7396 #endif
7397
7398 #ifdef CONFIG_IXGBE_DCA
7399 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7400 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7401 dca_remove_requester(&pdev->dev);
7402 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7403 }
7404
7405 #endif
7406 #ifdef CONFIG_IXGBE_HWMON
7407 ixgbe_sysfs_exit(adapter);
7408 #endif /* CONFIG_IXGBE_HWMON */
7409
7410 #ifdef IXGBE_FCOE
7411 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7412 ixgbe_cleanup_fcoe(adapter);
7413
7414 #endif /* IXGBE_FCOE */
7415
7416 /* remove the added san mac */
7417 ixgbe_del_sanmac_netdev(netdev);
7418
7419 if (netdev->reg_state == NETREG_REGISTERED)
7420 unregister_netdev(netdev);
7421
7422 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7423 if (!(ixgbe_check_vf_assignment(adapter)))
7424 ixgbe_disable_sriov(adapter);
7425 else
7426 e_dev_warn("Unloading driver while VFs are assigned "
7427 "- VFs will not be deallocated\n");
7428 }
7429
7430 ixgbe_clear_interrupt_scheme(adapter);
7431
7432 ixgbe_release_hw_control(adapter);
7433
7434 #ifdef CONFIG_DCB
7435 kfree(adapter->ixgbe_ieee_pfc);
7436 kfree(adapter->ixgbe_ieee_ets);
7437
7438 #endif
7439 iounmap(adapter->hw.hw_addr);
7440 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7441 IORESOURCE_MEM));
7442
7443 e_dev_info("complete\n");
7444
7445 free_netdev(netdev);
7446
7447 pci_disable_pcie_error_reporting(pdev);
7448
7449 pci_disable_device(pdev);
7450 }
7451
7452 /**
7453 * ixgbe_io_error_detected - called when PCI error is detected
7454 * @pdev: Pointer to PCI device
7455 * @state: The current pci connection state
7456 *
7457 * This function is called after a PCI bus error affecting
7458 * this device has been detected.
7459 */
7460 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7461 pci_channel_state_t state)
7462 {
7463 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7464 struct net_device *netdev = adapter->netdev;
7465
7466 #ifdef CONFIG_PCI_IOV
7467 struct pci_dev *bdev, *vfdev;
7468 u32 dw0, dw1, dw2, dw3;
7469 int vf, pos;
7470 u16 req_id, pf_func;
7471
7472 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7473 adapter->num_vfs == 0)
7474 goto skip_bad_vf_detection;
7475
7476 bdev = pdev->bus->self;
7477 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7478 bdev = bdev->bus->self;
7479
7480 if (!bdev)
7481 goto skip_bad_vf_detection;
7482
7483 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7484 if (!pos)
7485 goto skip_bad_vf_detection;
7486
7487 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7488 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7489 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7490 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7491
7492 req_id = dw1 >> 16;
7493 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7494 if (!(req_id & 0x0080))
7495 goto skip_bad_vf_detection;
7496
7497 pf_func = req_id & 0x01;
7498 if ((pf_func & 1) == (pdev->devfn & 1)) {
7499 unsigned int device_id;
7500
7501 vf = (req_id & 0x7F) >> 1;
7502 e_dev_err("VF %d has caused a PCIe error\n", vf);
7503 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7504 "%8.8x\tdw3: %8.8x\n",
7505 dw0, dw1, dw2, dw3);
7506 switch (adapter->hw.mac.type) {
7507 case ixgbe_mac_82599EB:
7508 device_id = IXGBE_82599_VF_DEVICE_ID;
7509 break;
7510 case ixgbe_mac_X540:
7511 device_id = IXGBE_X540_VF_DEVICE_ID;
7512 break;
7513 default:
7514 device_id = 0;
7515 break;
7516 }
7517
7518 /* Find the pci device of the offending VF */
7519 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
7520 while (vfdev) {
7521 if (vfdev->devfn == (req_id & 0xFF))
7522 break;
7523 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
7524 device_id, vfdev);
7525 }
7526 /*
7527 * There's a slim chance the VF could have been hot plugged,
7528 * so if it is no longer present we don't need to issue the
7529 * VFLR. Just clean up the AER in that case.
7530 */
7531 if (vfdev) {
7532 e_dev_err("Issuing VFLR to VF %d\n", vf);
7533 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7534 }
7535
7536 pci_cleanup_aer_uncorrect_error_status(pdev);
7537 }
7538
7539 /*
7540 * Even though the error may have occurred on the other port
7541 * we still need to increment the vf error reference count for
7542 * both ports because the I/O resume function will be called
7543 * for both of them.
7544 */
7545 adapter->vferr_refcount++;
7546
7547 return PCI_ERS_RESULT_RECOVERED;
7548
7549 skip_bad_vf_detection:
7550 #endif /* CONFIG_PCI_IOV */
7551 netif_device_detach(netdev);
7552
7553 if (state == pci_channel_io_perm_failure)
7554 return PCI_ERS_RESULT_DISCONNECT;
7555
7556 if (netif_running(netdev))
7557 ixgbe_down(adapter);
7558 pci_disable_device(pdev);
7559
7560 /* Request a slot reset. */
7561 return PCI_ERS_RESULT_NEED_RESET;
7562 }
7563
7564 /**
7565 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7566 * @pdev: Pointer to PCI device
7567 *
7568 * Restart the card from scratch, as if from a cold-boot.
7569 */
7570 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7571 {
7572 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7573 pci_ers_result_t result;
7574 int err;
7575
7576 if (pci_enable_device_mem(pdev)) {
7577 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7578 result = PCI_ERS_RESULT_DISCONNECT;
7579 } else {
7580 pci_set_master(pdev);
7581 pci_restore_state(pdev);
7582 pci_save_state(pdev);
7583
7584 pci_wake_from_d3(pdev, false);
7585
7586 ixgbe_reset(adapter);
7587 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7588 result = PCI_ERS_RESULT_RECOVERED;
7589 }
7590
7591 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7592 if (err) {
7593 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7594 "failed 0x%0x\n", err);
7595 /* non-fatal, continue */
7596 }
7597
7598 return result;
7599 }
7600
7601 /**
7602 * ixgbe_io_resume - called when traffic can start flowing again.
7603 * @pdev: Pointer to PCI device
7604 *
7605 * This callback is called when the error recovery driver tells us that
7606 * its OK to resume normal operation.
7607 */
7608 static void ixgbe_io_resume(struct pci_dev *pdev)
7609 {
7610 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7611 struct net_device *netdev = adapter->netdev;
7612
7613 #ifdef CONFIG_PCI_IOV
7614 if (adapter->vferr_refcount) {
7615 e_info(drv, "Resuming after VF err\n");
7616 adapter->vferr_refcount--;
7617 return;
7618 }
7619
7620 #endif
7621 if (netif_running(netdev))
7622 ixgbe_up(adapter);
7623
7624 netif_device_attach(netdev);
7625 }
7626
7627 static struct pci_error_handlers ixgbe_err_handler = {
7628 .error_detected = ixgbe_io_error_detected,
7629 .slot_reset = ixgbe_io_slot_reset,
7630 .resume = ixgbe_io_resume,
7631 };
7632
7633 static struct pci_driver ixgbe_driver = {
7634 .name = ixgbe_driver_name,
7635 .id_table = ixgbe_pci_tbl,
7636 .probe = ixgbe_probe,
7637 .remove = __devexit_p(ixgbe_remove),
7638 #ifdef CONFIG_PM
7639 .suspend = ixgbe_suspend,
7640 .resume = ixgbe_resume,
7641 #endif
7642 .shutdown = ixgbe_shutdown,
7643 .err_handler = &ixgbe_err_handler
7644 };
7645
7646 /**
7647 * ixgbe_init_module - Driver Registration Routine
7648 *
7649 * ixgbe_init_module is the first routine called when the driver is
7650 * loaded. All it does is register with the PCI subsystem.
7651 **/
7652 static int __init ixgbe_init_module(void)
7653 {
7654 int ret;
7655 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7656 pr_info("%s\n", ixgbe_copyright);
7657
7658 #ifdef CONFIG_IXGBE_DCA
7659 dca_register_notify(&dca_notifier);
7660 #endif
7661
7662 ret = pci_register_driver(&ixgbe_driver);
7663 return ret;
7664 }
7665
7666 module_init(ixgbe_init_module);
7667
7668 /**
7669 * ixgbe_exit_module - Driver Exit Cleanup Routine
7670 *
7671 * ixgbe_exit_module is called just before the driver is removed
7672 * from memory.
7673 **/
7674 static void __exit ixgbe_exit_module(void)
7675 {
7676 #ifdef CONFIG_IXGBE_DCA
7677 dca_unregister_notify(&dca_notifier);
7678 #endif
7679 pci_unregister_driver(&ixgbe_driver);
7680 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7681 }
7682
7683 #ifdef CONFIG_IXGBE_DCA
7684 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7685 void *p)
7686 {
7687 int ret_val;
7688
7689 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7690 __ixgbe_notify_dca);
7691
7692 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7693 }
7694
7695 #endif /* CONFIG_IXGBE_DCA */
7696
7697 module_exit(ixgbe_exit_module);
7698
7699 /* ixgbe_main.c */
Linux kernel - Deliverables
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