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ixgbe/ixgbevf: Add support for bulk free in Tx cleanup & cleanup boolean logic
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2016 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/types.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/vmalloc.h>
34 #include <linux/string.h>
35 #include <linux/in.h>
36 #include <linux/interrupt.h>
37 #include <linux/ip.h>
38 #include <linux/tcp.h>
39 #include <linux/sctp.h>
40 #include <linux/pkt_sched.h>
41 #include <linux/ipv6.h>
42 #include <linux/slab.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/etherdevice.h>
46 #include <linux/ethtool.h>
47 #include <linux/if.h>
48 #include <linux/if_vlan.h>
49 #include <linux/if_macvlan.h>
50 #include <linux/if_bridge.h>
51 #include <linux/prefetch.h>
52 #include <scsi/fc/fc_fcoe.h>
53 #include <net/vxlan.h>
54 #include <net/pkt_cls.h>
55 #include <net/tc_act/tc_gact.h>
56
57 #include "ixgbe.h"
58 #include "ixgbe_common.h"
59 #include "ixgbe_dcb_82599.h"
60 #include "ixgbe_sriov.h"
61 #include "ixgbe_model.h"
62
63 char ixgbe_driver_name[] = "ixgbe";
64 static const char ixgbe_driver_string[] =
65 "Intel(R) 10 Gigabit PCI Express Network Driver";
66 #ifdef IXGBE_FCOE
67 char ixgbe_default_device_descr[] =
68 "Intel(R) 10 Gigabit Network Connection";
69 #else
70 static char ixgbe_default_device_descr[] =
71 "Intel(R) 10 Gigabit Network Connection";
72 #endif
73 #define DRV_VERSION "4.2.1-k"
74 const char ixgbe_driver_version[] = DRV_VERSION;
75 static const char ixgbe_copyright[] =
76 "Copyright (c) 1999-2015 Intel Corporation.";
77
78 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
79
80 static const struct ixgbe_info *ixgbe_info_tbl[] = {
81 [board_82598] = &ixgbe_82598_info,
82 [board_82599] = &ixgbe_82599_info,
83 [board_X540] = &ixgbe_X540_info,
84 [board_X550] = &ixgbe_X550_info,
85 [board_X550EM_x] = &ixgbe_X550EM_x_info,
86 };
87
88 /* ixgbe_pci_tbl - PCI Device ID Table
89 *
90 * Wildcard entries (PCI_ANY_ID) should come last
91 * Last entry must be all 0s
92 *
93 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
94 * Class, Class Mask, private data (not used) }
95 */
96 static const struct pci_device_id ixgbe_pci_tbl[] = {
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
132 /* required last entry */
133 {0, }
134 };
135 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
136
137 #ifdef CONFIG_IXGBE_DCA
138 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
139 void *p);
140 static struct notifier_block dca_notifier = {
141 .notifier_call = ixgbe_notify_dca,
142 .next = NULL,
143 .priority = 0
144 };
145 #endif
146
147 #ifdef CONFIG_PCI_IOV
148 static unsigned int max_vfs;
149 module_param(max_vfs, uint, 0);
150 MODULE_PARM_DESC(max_vfs,
151 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
152 #endif /* CONFIG_PCI_IOV */
153
154 static unsigned int allow_unsupported_sfp;
155 module_param(allow_unsupported_sfp, uint, 0);
156 MODULE_PARM_DESC(allow_unsupported_sfp,
157 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
158
159 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
160 static int debug = -1;
161 module_param(debug, int, 0);
162 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
163
164 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
165 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
166 MODULE_LICENSE("GPL");
167 MODULE_VERSION(DRV_VERSION);
168
169 static struct workqueue_struct *ixgbe_wq;
170
171 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
172
173 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
174 u32 reg, u16 *value)
175 {
176 struct pci_dev *parent_dev;
177 struct pci_bus *parent_bus;
178
179 parent_bus = adapter->pdev->bus->parent;
180 if (!parent_bus)
181 return -1;
182
183 parent_dev = parent_bus->self;
184 if (!parent_dev)
185 return -1;
186
187 if (!pci_is_pcie(parent_dev))
188 return -1;
189
190 pcie_capability_read_word(parent_dev, reg, value);
191 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
192 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
193 return -1;
194 return 0;
195 }
196
197 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
198 {
199 struct ixgbe_hw *hw = &adapter->hw;
200 u16 link_status = 0;
201 int err;
202
203 hw->bus.type = ixgbe_bus_type_pci_express;
204
205 /* Get the negotiated link width and speed from PCI config space of the
206 * parent, as this device is behind a switch
207 */
208 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
209
210 /* assume caller will handle error case */
211 if (err)
212 return err;
213
214 hw->bus.width = ixgbe_convert_bus_width(link_status);
215 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
216
217 return 0;
218 }
219
220 /**
221 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
222 * @hw: hw specific details
223 *
224 * This function is used by probe to determine whether a device's PCI-Express
225 * bandwidth details should be gathered from the parent bus instead of from the
226 * device. Used to ensure that various locations all have the correct device ID
227 * checks.
228 */
229 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
230 {
231 switch (hw->device_id) {
232 case IXGBE_DEV_ID_82599_SFP_SF_QP:
233 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
234 return true;
235 default:
236 return false;
237 }
238 }
239
240 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
241 int expected_gts)
242 {
243 struct ixgbe_hw *hw = &adapter->hw;
244 int max_gts = 0;
245 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
246 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
247 struct pci_dev *pdev;
248
249 /* Some devices are not connected over PCIe and thus do not negotiate
250 * speed. These devices do not have valid bus info, and thus any report
251 * we generate may not be correct.
252 */
253 if (hw->bus.type == ixgbe_bus_type_internal)
254 return;
255
256 /* determine whether to use the parent device */
257 if (ixgbe_pcie_from_parent(&adapter->hw))
258 pdev = adapter->pdev->bus->parent->self;
259 else
260 pdev = adapter->pdev;
261
262 if (pcie_get_minimum_link(pdev, &speed, &width) ||
263 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
264 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
265 return;
266 }
267
268 switch (speed) {
269 case PCIE_SPEED_2_5GT:
270 /* 8b/10b encoding reduces max throughput by 20% */
271 max_gts = 2 * width;
272 break;
273 case PCIE_SPEED_5_0GT:
274 /* 8b/10b encoding reduces max throughput by 20% */
275 max_gts = 4 * width;
276 break;
277 case PCIE_SPEED_8_0GT:
278 /* 128b/130b encoding reduces throughput by less than 2% */
279 max_gts = 8 * width;
280 break;
281 default:
282 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
283 return;
284 }
285
286 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
287 max_gts);
288 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
289 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
290 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
291 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
292 "Unknown"),
293 width,
294 (speed == PCIE_SPEED_2_5GT ? "20%" :
295 speed == PCIE_SPEED_5_0GT ? "20%" :
296 speed == PCIE_SPEED_8_0GT ? "<2%" :
297 "Unknown"));
298
299 if (max_gts < expected_gts) {
300 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
301 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
302 expected_gts);
303 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
304 }
305 }
306
307 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
308 {
309 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
310 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
311 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
312 queue_work(ixgbe_wq, &adapter->service_task);
313 }
314
315 static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
316 {
317 struct ixgbe_adapter *adapter = hw->back;
318
319 if (!hw->hw_addr)
320 return;
321 hw->hw_addr = NULL;
322 e_dev_err("Adapter removed\n");
323 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
324 ixgbe_service_event_schedule(adapter);
325 }
326
327 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
328 {
329 u32 value;
330
331 /* The following check not only optimizes a bit by not
332 * performing a read on the status register when the
333 * register just read was a status register read that
334 * returned IXGBE_FAILED_READ_REG. It also blocks any
335 * potential recursion.
336 */
337 if (reg == IXGBE_STATUS) {
338 ixgbe_remove_adapter(hw);
339 return;
340 }
341 value = ixgbe_read_reg(hw, IXGBE_STATUS);
342 if (value == IXGBE_FAILED_READ_REG)
343 ixgbe_remove_adapter(hw);
344 }
345
346 /**
347 * ixgbe_read_reg - Read from device register
348 * @hw: hw specific details
349 * @reg: offset of register to read
350 *
351 * Returns : value read or IXGBE_FAILED_READ_REG if removed
352 *
353 * This function is used to read device registers. It checks for device
354 * removal by confirming any read that returns all ones by checking the
355 * status register value for all ones. This function avoids reading from
356 * the hardware if a removal was previously detected in which case it
357 * returns IXGBE_FAILED_READ_REG (all ones).
358 */
359 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
360 {
361 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
362 u32 value;
363
364 if (ixgbe_removed(reg_addr))
365 return IXGBE_FAILED_READ_REG;
366 value = readl(reg_addr + reg);
367 if (unlikely(value == IXGBE_FAILED_READ_REG))
368 ixgbe_check_remove(hw, reg);
369 return value;
370 }
371
372 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
373 {
374 u16 value;
375
376 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
377 if (value == IXGBE_FAILED_READ_CFG_WORD) {
378 ixgbe_remove_adapter(hw);
379 return true;
380 }
381 return false;
382 }
383
384 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
385 {
386 struct ixgbe_adapter *adapter = hw->back;
387 u16 value;
388
389 if (ixgbe_removed(hw->hw_addr))
390 return IXGBE_FAILED_READ_CFG_WORD;
391 pci_read_config_word(adapter->pdev, reg, &value);
392 if (value == IXGBE_FAILED_READ_CFG_WORD &&
393 ixgbe_check_cfg_remove(hw, adapter->pdev))
394 return IXGBE_FAILED_READ_CFG_WORD;
395 return value;
396 }
397
398 #ifdef CONFIG_PCI_IOV
399 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
400 {
401 struct ixgbe_adapter *adapter = hw->back;
402 u32 value;
403
404 if (ixgbe_removed(hw->hw_addr))
405 return IXGBE_FAILED_READ_CFG_DWORD;
406 pci_read_config_dword(adapter->pdev, reg, &value);
407 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
408 ixgbe_check_cfg_remove(hw, adapter->pdev))
409 return IXGBE_FAILED_READ_CFG_DWORD;
410 return value;
411 }
412 #endif /* CONFIG_PCI_IOV */
413
414 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
415 {
416 struct ixgbe_adapter *adapter = hw->back;
417
418 if (ixgbe_removed(hw->hw_addr))
419 return;
420 pci_write_config_word(adapter->pdev, reg, value);
421 }
422
423 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
424 {
425 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
426
427 /* flush memory to make sure state is correct before next watchdog */
428 smp_mb__before_atomic();
429 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
430 }
431
432 struct ixgbe_reg_info {
433 u32 ofs;
434 char *name;
435 };
436
437 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
438
439 /* General Registers */
440 {IXGBE_CTRL, "CTRL"},
441 {IXGBE_STATUS, "STATUS"},
442 {IXGBE_CTRL_EXT, "CTRL_EXT"},
443
444 /* Interrupt Registers */
445 {IXGBE_EICR, "EICR"},
446
447 /* RX Registers */
448 {IXGBE_SRRCTL(0), "SRRCTL"},
449 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
450 {IXGBE_RDLEN(0), "RDLEN"},
451 {IXGBE_RDH(0), "RDH"},
452 {IXGBE_RDT(0), "RDT"},
453 {IXGBE_RXDCTL(0), "RXDCTL"},
454 {IXGBE_RDBAL(0), "RDBAL"},
455 {IXGBE_RDBAH(0), "RDBAH"},
456
457 /* TX Registers */
458 {IXGBE_TDBAL(0), "TDBAL"},
459 {IXGBE_TDBAH(0), "TDBAH"},
460 {IXGBE_TDLEN(0), "TDLEN"},
461 {IXGBE_TDH(0), "TDH"},
462 {IXGBE_TDT(0), "TDT"},
463 {IXGBE_TXDCTL(0), "TXDCTL"},
464
465 /* List Terminator */
466 { .name = NULL }
467 };
468
469
470 /*
471 * ixgbe_regdump - register printout routine
472 */
473 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
474 {
475 int i = 0, j = 0;
476 char rname[16];
477 u32 regs[64];
478
479 switch (reginfo->ofs) {
480 case IXGBE_SRRCTL(0):
481 for (i = 0; i < 64; i++)
482 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
483 break;
484 case IXGBE_DCA_RXCTRL(0):
485 for (i = 0; i < 64; i++)
486 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
487 break;
488 case IXGBE_RDLEN(0):
489 for (i = 0; i < 64; i++)
490 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
491 break;
492 case IXGBE_RDH(0):
493 for (i = 0; i < 64; i++)
494 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
495 break;
496 case IXGBE_RDT(0):
497 for (i = 0; i < 64; i++)
498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
499 break;
500 case IXGBE_RXDCTL(0):
501 for (i = 0; i < 64; i++)
502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
503 break;
504 case IXGBE_RDBAL(0):
505 for (i = 0; i < 64; i++)
506 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
507 break;
508 case IXGBE_RDBAH(0):
509 for (i = 0; i < 64; i++)
510 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
511 break;
512 case IXGBE_TDBAL(0):
513 for (i = 0; i < 64; i++)
514 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
515 break;
516 case IXGBE_TDBAH(0):
517 for (i = 0; i < 64; i++)
518 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
519 break;
520 case IXGBE_TDLEN(0):
521 for (i = 0; i < 64; i++)
522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
523 break;
524 case IXGBE_TDH(0):
525 for (i = 0; i < 64; i++)
526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
527 break;
528 case IXGBE_TDT(0):
529 for (i = 0; i < 64; i++)
530 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
531 break;
532 case IXGBE_TXDCTL(0):
533 for (i = 0; i < 64; i++)
534 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
535 break;
536 default:
537 pr_info("%-15s %08x\n", reginfo->name,
538 IXGBE_READ_REG(hw, reginfo->ofs));
539 return;
540 }
541
542 for (i = 0; i < 8; i++) {
543 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
544 pr_err("%-15s", rname);
545 for (j = 0; j < 8; j++)
546 pr_cont(" %08x", regs[i*8+j]);
547 pr_cont("\n");
548 }
549
550 }
551
552 /*
553 * ixgbe_dump - Print registers, tx-rings and rx-rings
554 */
555 static void ixgbe_dump(struct ixgbe_adapter *adapter)
556 {
557 struct net_device *netdev = adapter->netdev;
558 struct ixgbe_hw *hw = &adapter->hw;
559 struct ixgbe_reg_info *reginfo;
560 int n = 0;
561 struct ixgbe_ring *tx_ring;
562 struct ixgbe_tx_buffer *tx_buffer;
563 union ixgbe_adv_tx_desc *tx_desc;
564 struct my_u0 { u64 a; u64 b; } *u0;
565 struct ixgbe_ring *rx_ring;
566 union ixgbe_adv_rx_desc *rx_desc;
567 struct ixgbe_rx_buffer *rx_buffer_info;
568 u32 staterr;
569 int i = 0;
570
571 if (!netif_msg_hw(adapter))
572 return;
573
574 /* Print netdevice Info */
575 if (netdev) {
576 dev_info(&adapter->pdev->dev, "Net device Info\n");
577 pr_info("Device Name state "
578 "trans_start last_rx\n");
579 pr_info("%-15s %016lX %016lX %016lX\n",
580 netdev->name,
581 netdev->state,
582 netdev->trans_start,
583 netdev->last_rx);
584 }
585
586 /* Print Registers */
587 dev_info(&adapter->pdev->dev, "Register Dump\n");
588 pr_info(" Register Name Value\n");
589 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
590 reginfo->name; reginfo++) {
591 ixgbe_regdump(hw, reginfo);
592 }
593
594 /* Print TX Ring Summary */
595 if (!netdev || !netif_running(netdev))
596 return;
597
598 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
599 pr_info(" %s %s %s %s\n",
600 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
601 "leng", "ntw", "timestamp");
602 for (n = 0; n < adapter->num_tx_queues; n++) {
603 tx_ring = adapter->tx_ring[n];
604 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
605 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
606 n, tx_ring->next_to_use, tx_ring->next_to_clean,
607 (u64)dma_unmap_addr(tx_buffer, dma),
608 dma_unmap_len(tx_buffer, len),
609 tx_buffer->next_to_watch,
610 (u64)tx_buffer->time_stamp);
611 }
612
613 /* Print TX Rings */
614 if (!netif_msg_tx_done(adapter))
615 goto rx_ring_summary;
616
617 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
618
619 /* Transmit Descriptor Formats
620 *
621 * 82598 Advanced Transmit Descriptor
622 * +--------------------------------------------------------------+
623 * 0 | Buffer Address [63:0] |
624 * +--------------------------------------------------------------+
625 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
626 * +--------------------------------------------------------------+
627 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
628 *
629 * 82598 Advanced Transmit Descriptor (Write-Back Format)
630 * +--------------------------------------------------------------+
631 * 0 | RSV [63:0] |
632 * +--------------------------------------------------------------+
633 * 8 | RSV | STA | NXTSEQ |
634 * +--------------------------------------------------------------+
635 * 63 36 35 32 31 0
636 *
637 * 82599+ Advanced Transmit Descriptor
638 * +--------------------------------------------------------------+
639 * 0 | Buffer Address [63:0] |
640 * +--------------------------------------------------------------+
641 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
642 * +--------------------------------------------------------------+
643 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
644 *
645 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
646 * +--------------------------------------------------------------+
647 * 0 | RSV [63:0] |
648 * +--------------------------------------------------------------+
649 * 8 | RSV | STA | RSV |
650 * +--------------------------------------------------------------+
651 * 63 36 35 32 31 0
652 */
653
654 for (n = 0; n < adapter->num_tx_queues; n++) {
655 tx_ring = adapter->tx_ring[n];
656 pr_info("------------------------------------\n");
657 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
658 pr_info("------------------------------------\n");
659 pr_info("%s%s %s %s %s %s\n",
660 "T [desc] [address 63:0 ] ",
661 "[PlPOIdStDDt Ln] [bi->dma ] ",
662 "leng", "ntw", "timestamp", "bi->skb");
663
664 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
665 tx_desc = IXGBE_TX_DESC(tx_ring, i);
666 tx_buffer = &tx_ring->tx_buffer_info[i];
667 u0 = (struct my_u0 *)tx_desc;
668 if (dma_unmap_len(tx_buffer, len) > 0) {
669 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
670 i,
671 le64_to_cpu(u0->a),
672 le64_to_cpu(u0->b),
673 (u64)dma_unmap_addr(tx_buffer, dma),
674 dma_unmap_len(tx_buffer, len),
675 tx_buffer->next_to_watch,
676 (u64)tx_buffer->time_stamp,
677 tx_buffer->skb);
678 if (i == tx_ring->next_to_use &&
679 i == tx_ring->next_to_clean)
680 pr_cont(" NTC/U\n");
681 else if (i == tx_ring->next_to_use)
682 pr_cont(" NTU\n");
683 else if (i == tx_ring->next_to_clean)
684 pr_cont(" NTC\n");
685 else
686 pr_cont("\n");
687
688 if (netif_msg_pktdata(adapter) &&
689 tx_buffer->skb)
690 print_hex_dump(KERN_INFO, "",
691 DUMP_PREFIX_ADDRESS, 16, 1,
692 tx_buffer->skb->data,
693 dma_unmap_len(tx_buffer, len),
694 true);
695 }
696 }
697 }
698
699 /* Print RX Rings Summary */
700 rx_ring_summary:
701 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
702 pr_info("Queue [NTU] [NTC]\n");
703 for (n = 0; n < adapter->num_rx_queues; n++) {
704 rx_ring = adapter->rx_ring[n];
705 pr_info("%5d %5X %5X\n",
706 n, rx_ring->next_to_use, rx_ring->next_to_clean);
707 }
708
709 /* Print RX Rings */
710 if (!netif_msg_rx_status(adapter))
711 return;
712
713 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
714
715 /* Receive Descriptor Formats
716 *
717 * 82598 Advanced Receive Descriptor (Read) Format
718 * 63 1 0
719 * +-----------------------------------------------------+
720 * 0 | Packet Buffer Address [63:1] |A0/NSE|
721 * +----------------------------------------------+------+
722 * 8 | Header Buffer Address [63:1] | DD |
723 * +-----------------------------------------------------+
724 *
725 *
726 * 82598 Advanced Receive Descriptor (Write-Back) Format
727 *
728 * 63 48 47 32 31 30 21 20 16 15 4 3 0
729 * +------------------------------------------------------+
730 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
731 * | Packet | IP | | | | Type | Type |
732 * | Checksum | Ident | | | | | |
733 * +------------------------------------------------------+
734 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
735 * +------------------------------------------------------+
736 * 63 48 47 32 31 20 19 0
737 *
738 * 82599+ Advanced Receive Descriptor (Read) Format
739 * 63 1 0
740 * +-----------------------------------------------------+
741 * 0 | Packet Buffer Address [63:1] |A0/NSE|
742 * +----------------------------------------------+------+
743 * 8 | Header Buffer Address [63:1] | DD |
744 * +-----------------------------------------------------+
745 *
746 *
747 * 82599+ Advanced Receive Descriptor (Write-Back) Format
748 *
749 * 63 48 47 32 31 30 21 20 17 16 4 3 0
750 * +------------------------------------------------------+
751 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
752 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
753 * |/ Flow Dir Flt ID | | | | | |
754 * +------------------------------------------------------+
755 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
756 * +------------------------------------------------------+
757 * 63 48 47 32 31 20 19 0
758 */
759
760 for (n = 0; n < adapter->num_rx_queues; n++) {
761 rx_ring = adapter->rx_ring[n];
762 pr_info("------------------------------------\n");
763 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
764 pr_info("------------------------------------\n");
765 pr_info("%s%s%s",
766 "R [desc] [ PktBuf A0] ",
767 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
768 "<-- Adv Rx Read format\n");
769 pr_info("%s%s%s",
770 "RWB[desc] [PcsmIpSHl PtRs] ",
771 "[vl er S cks ln] ---------------- [bi->skb ] ",
772 "<-- Adv Rx Write-Back format\n");
773
774 for (i = 0; i < rx_ring->count; i++) {
775 rx_buffer_info = &rx_ring->rx_buffer_info[i];
776 rx_desc = IXGBE_RX_DESC(rx_ring, i);
777 u0 = (struct my_u0 *)rx_desc;
778 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
779 if (staterr & IXGBE_RXD_STAT_DD) {
780 /* Descriptor Done */
781 pr_info("RWB[0x%03X] %016llX "
782 "%016llX ---------------- %p", i,
783 le64_to_cpu(u0->a),
784 le64_to_cpu(u0->b),
785 rx_buffer_info->skb);
786 } else {
787 pr_info("R [0x%03X] %016llX "
788 "%016llX %016llX %p", i,
789 le64_to_cpu(u0->a),
790 le64_to_cpu(u0->b),
791 (u64)rx_buffer_info->dma,
792 rx_buffer_info->skb);
793
794 if (netif_msg_pktdata(adapter) &&
795 rx_buffer_info->dma) {
796 print_hex_dump(KERN_INFO, "",
797 DUMP_PREFIX_ADDRESS, 16, 1,
798 page_address(rx_buffer_info->page) +
799 rx_buffer_info->page_offset,
800 ixgbe_rx_bufsz(rx_ring), true);
801 }
802 }
803
804 if (i == rx_ring->next_to_use)
805 pr_cont(" NTU\n");
806 else if (i == rx_ring->next_to_clean)
807 pr_cont(" NTC\n");
808 else
809 pr_cont("\n");
810
811 }
812 }
813 }
814
815 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
816 {
817 u32 ctrl_ext;
818
819 /* Let firmware take over control of h/w */
820 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
821 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
822 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
823 }
824
825 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
826 {
827 u32 ctrl_ext;
828
829 /* Let firmware know the driver has taken over */
830 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
831 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
832 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
833 }
834
835 /**
836 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
837 * @adapter: pointer to adapter struct
838 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
839 * @queue: queue to map the corresponding interrupt to
840 * @msix_vector: the vector to map to the corresponding queue
841 *
842 */
843 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
844 u8 queue, u8 msix_vector)
845 {
846 u32 ivar, index;
847 struct ixgbe_hw *hw = &adapter->hw;
848 switch (hw->mac.type) {
849 case ixgbe_mac_82598EB:
850 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
851 if (direction == -1)
852 direction = 0;
853 index = (((direction * 64) + queue) >> 2) & 0x1F;
854 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
855 ivar &= ~(0xFF << (8 * (queue & 0x3)));
856 ivar |= (msix_vector << (8 * (queue & 0x3)));
857 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
858 break;
859 case ixgbe_mac_82599EB:
860 case ixgbe_mac_X540:
861 case ixgbe_mac_X550:
862 case ixgbe_mac_X550EM_x:
863 if (direction == -1) {
864 /* other causes */
865 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
866 index = ((queue & 1) * 8);
867 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
868 ivar &= ~(0xFF << index);
869 ivar |= (msix_vector << index);
870 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
871 break;
872 } else {
873 /* tx or rx causes */
874 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
875 index = ((16 * (queue & 1)) + (8 * direction));
876 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
877 ivar &= ~(0xFF << index);
878 ivar |= (msix_vector << index);
879 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
880 break;
881 }
882 default:
883 break;
884 }
885 }
886
887 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
888 u64 qmask)
889 {
890 u32 mask;
891
892 switch (adapter->hw.mac.type) {
893 case ixgbe_mac_82598EB:
894 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
895 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
896 break;
897 case ixgbe_mac_82599EB:
898 case ixgbe_mac_X540:
899 case ixgbe_mac_X550:
900 case ixgbe_mac_X550EM_x:
901 mask = (qmask & 0xFFFFFFFF);
902 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
903 mask = (qmask >> 32);
904 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
905 break;
906 default:
907 break;
908 }
909 }
910
911 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
912 struct ixgbe_tx_buffer *tx_buffer)
913 {
914 if (tx_buffer->skb) {
915 dev_kfree_skb_any(tx_buffer->skb);
916 if (dma_unmap_len(tx_buffer, len))
917 dma_unmap_single(ring->dev,
918 dma_unmap_addr(tx_buffer, dma),
919 dma_unmap_len(tx_buffer, len),
920 DMA_TO_DEVICE);
921 } else if (dma_unmap_len(tx_buffer, len)) {
922 dma_unmap_page(ring->dev,
923 dma_unmap_addr(tx_buffer, dma),
924 dma_unmap_len(tx_buffer, len),
925 DMA_TO_DEVICE);
926 }
927 tx_buffer->next_to_watch = NULL;
928 tx_buffer->skb = NULL;
929 dma_unmap_len_set(tx_buffer, len, 0);
930 /* tx_buffer must be completely set up in the transmit path */
931 }
932
933 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
934 {
935 struct ixgbe_hw *hw = &adapter->hw;
936 struct ixgbe_hw_stats *hwstats = &adapter->stats;
937 int i;
938 u32 data;
939
940 if ((hw->fc.current_mode != ixgbe_fc_full) &&
941 (hw->fc.current_mode != ixgbe_fc_rx_pause))
942 return;
943
944 switch (hw->mac.type) {
945 case ixgbe_mac_82598EB:
946 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
947 break;
948 default:
949 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
950 }
951 hwstats->lxoffrxc += data;
952
953 /* refill credits (no tx hang) if we received xoff */
954 if (!data)
955 return;
956
957 for (i = 0; i < adapter->num_tx_queues; i++)
958 clear_bit(__IXGBE_HANG_CHECK_ARMED,
959 &adapter->tx_ring[i]->state);
960 }
961
962 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
963 {
964 struct ixgbe_hw *hw = &adapter->hw;
965 struct ixgbe_hw_stats *hwstats = &adapter->stats;
966 u32 xoff[8] = {0};
967 u8 tc;
968 int i;
969 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
970
971 if (adapter->ixgbe_ieee_pfc)
972 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
973
974 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
975 ixgbe_update_xoff_rx_lfc(adapter);
976 return;
977 }
978
979 /* update stats for each tc, only valid with PFC enabled */
980 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
981 u32 pxoffrxc;
982
983 switch (hw->mac.type) {
984 case ixgbe_mac_82598EB:
985 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
986 break;
987 default:
988 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
989 }
990 hwstats->pxoffrxc[i] += pxoffrxc;
991 /* Get the TC for given UP */
992 tc = netdev_get_prio_tc_map(adapter->netdev, i);
993 xoff[tc] += pxoffrxc;
994 }
995
996 /* disarm tx queues that have received xoff frames */
997 for (i = 0; i < adapter->num_tx_queues; i++) {
998 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
999
1000 tc = tx_ring->dcb_tc;
1001 if (xoff[tc])
1002 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1003 }
1004 }
1005
1006 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
1007 {
1008 return ring->stats.packets;
1009 }
1010
1011 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1012 {
1013 struct ixgbe_adapter *adapter;
1014 struct ixgbe_hw *hw;
1015 u32 head, tail;
1016
1017 if (ring->l2_accel_priv)
1018 adapter = ring->l2_accel_priv->real_adapter;
1019 else
1020 adapter = netdev_priv(ring->netdev);
1021
1022 hw = &adapter->hw;
1023 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1024 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
1025
1026 if (head != tail)
1027 return (head < tail) ?
1028 tail - head : (tail + ring->count - head);
1029
1030 return 0;
1031 }
1032
1033 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1034 {
1035 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1036 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1037 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1038
1039 clear_check_for_tx_hang(tx_ring);
1040
1041 /*
1042 * Check for a hung queue, but be thorough. This verifies
1043 * that a transmit has been completed since the previous
1044 * check AND there is at least one packet pending. The
1045 * ARMED bit is set to indicate a potential hang. The
1046 * bit is cleared if a pause frame is received to remove
1047 * false hang detection due to PFC or 802.3x frames. By
1048 * requiring this to fail twice we avoid races with
1049 * pfc clearing the ARMED bit and conditions where we
1050 * run the check_tx_hang logic with a transmit completion
1051 * pending but without time to complete it yet.
1052 */
1053 if (tx_done_old == tx_done && tx_pending)
1054 /* make sure it is true for two checks in a row */
1055 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1056 &tx_ring->state);
1057 /* update completed stats and continue */
1058 tx_ring->tx_stats.tx_done_old = tx_done;
1059 /* reset the countdown */
1060 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1061
1062 return false;
1063 }
1064
1065 /**
1066 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1067 * @adapter: driver private struct
1068 **/
1069 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1070 {
1071
1072 /* Do the reset outside of interrupt context */
1073 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1074 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
1075 e_warn(drv, "initiating reset due to tx timeout\n");
1076 ixgbe_service_event_schedule(adapter);
1077 }
1078 }
1079
1080 /**
1081 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate
1082 **/
1083 static int ixgbe_tx_maxrate(struct net_device *netdev,
1084 int queue_index, u32 maxrate)
1085 {
1086 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1087 struct ixgbe_hw *hw = &adapter->hw;
1088 u32 bcnrc_val = ixgbe_link_mbps(adapter);
1089
1090 if (!maxrate)
1091 return 0;
1092
1093 /* Calculate the rate factor values to set */
1094 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT;
1095 bcnrc_val /= maxrate;
1096
1097 /* clear everything but the rate factor */
1098 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK |
1099 IXGBE_RTTBCNRC_RF_DEC_MASK;
1100
1101 /* enable the rate scheduler */
1102 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA;
1103
1104 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index);
1105 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
1106
1107 return 0;
1108 }
1109
1110 /**
1111 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
1112 * @q_vector: structure containing interrupt and ring information
1113 * @tx_ring: tx ring to clean
1114 * @napi_budget: Used to determine if we are in netpoll
1115 **/
1116 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
1117 struct ixgbe_ring *tx_ring, int napi_budget)
1118 {
1119 struct ixgbe_adapter *adapter = q_vector->adapter;
1120 struct ixgbe_tx_buffer *tx_buffer;
1121 union ixgbe_adv_tx_desc *tx_desc;
1122 unsigned int total_bytes = 0, total_packets = 0;
1123 unsigned int budget = q_vector->tx.work_limit;
1124 unsigned int i = tx_ring->next_to_clean;
1125
1126 if (test_bit(__IXGBE_DOWN, &adapter->state))
1127 return true;
1128
1129 tx_buffer = &tx_ring->tx_buffer_info[i];
1130 tx_desc = IXGBE_TX_DESC(tx_ring, i);
1131 i -= tx_ring->count;
1132
1133 do {
1134 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1135
1136 /* if next_to_watch is not set then there is no work pending */
1137 if (!eop_desc)
1138 break;
1139
1140 /* prevent any other reads prior to eop_desc */
1141 read_barrier_depends();
1142
1143 /* if DD is not set pending work has not been completed */
1144 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1145 break;
1146
1147 /* clear next_to_watch to prevent false hangs */
1148 tx_buffer->next_to_watch = NULL;
1149
1150 /* update the statistics for this packet */
1151 total_bytes += tx_buffer->bytecount;
1152 total_packets += tx_buffer->gso_segs;
1153
1154 /* free the skb */
1155 napi_consume_skb(tx_buffer->skb, napi_budget);
1156
1157 /* unmap skb header data */
1158 dma_unmap_single(tx_ring->dev,
1159 dma_unmap_addr(tx_buffer, dma),
1160 dma_unmap_len(tx_buffer, len),
1161 DMA_TO_DEVICE);
1162
1163 /* clear tx_buffer data */
1164 tx_buffer->skb = NULL;
1165 dma_unmap_len_set(tx_buffer, len, 0);
1166
1167 /* unmap remaining buffers */
1168 while (tx_desc != eop_desc) {
1169 tx_buffer++;
1170 tx_desc++;
1171 i++;
1172 if (unlikely(!i)) {
1173 i -= tx_ring->count;
1174 tx_buffer = tx_ring->tx_buffer_info;
1175 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1176 }
1177
1178 /* unmap any remaining paged data */
1179 if (dma_unmap_len(tx_buffer, len)) {
1180 dma_unmap_page(tx_ring->dev,
1181 dma_unmap_addr(tx_buffer, dma),
1182 dma_unmap_len(tx_buffer, len),
1183 DMA_TO_DEVICE);
1184 dma_unmap_len_set(tx_buffer, len, 0);
1185 }
1186 }
1187
1188 /* move us one more past the eop_desc for start of next pkt */
1189 tx_buffer++;
1190 tx_desc++;
1191 i++;
1192 if (unlikely(!i)) {
1193 i -= tx_ring->count;
1194 tx_buffer = tx_ring->tx_buffer_info;
1195 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1196 }
1197
1198 /* issue prefetch for next Tx descriptor */
1199 prefetch(tx_desc);
1200
1201 /* update budget accounting */
1202 budget--;
1203 } while (likely(budget));
1204
1205 i += tx_ring->count;
1206 tx_ring->next_to_clean = i;
1207 u64_stats_update_begin(&tx_ring->syncp);
1208 tx_ring->stats.bytes += total_bytes;
1209 tx_ring->stats.packets += total_packets;
1210 u64_stats_update_end(&tx_ring->syncp);
1211 q_vector->tx.total_bytes += total_bytes;
1212 q_vector->tx.total_packets += total_packets;
1213
1214 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1215 /* schedule immediate reset if we believe we hung */
1216 struct ixgbe_hw *hw = &adapter->hw;
1217 e_err(drv, "Detected Tx Unit Hang\n"
1218 " Tx Queue <%d>\n"
1219 " TDH, TDT <%x>, <%x>\n"
1220 " next_to_use <%x>\n"
1221 " next_to_clean <%x>\n"
1222 "tx_buffer_info[next_to_clean]\n"
1223 " time_stamp <%lx>\n"
1224 " jiffies <%lx>\n",
1225 tx_ring->queue_index,
1226 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1227 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1228 tx_ring->next_to_use, i,
1229 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1230
1231 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1232
1233 e_info(probe,
1234 "tx hang %d detected on queue %d, resetting adapter\n",
1235 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1236
1237 /* schedule immediate reset if we believe we hung */
1238 ixgbe_tx_timeout_reset(adapter);
1239
1240 /* the adapter is about to reset, no point in enabling stuff */
1241 return true;
1242 }
1243
1244 netdev_tx_completed_queue(txring_txq(tx_ring),
1245 total_packets, total_bytes);
1246
1247 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1248 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1249 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1250 /* Make sure that anybody stopping the queue after this
1251 * sees the new next_to_clean.
1252 */
1253 smp_mb();
1254 if (__netif_subqueue_stopped(tx_ring->netdev,
1255 tx_ring->queue_index)
1256 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1257 netif_wake_subqueue(tx_ring->netdev,
1258 tx_ring->queue_index);
1259 ++tx_ring->tx_stats.restart_queue;
1260 }
1261 }
1262
1263 return !!budget;
1264 }
1265
1266 #ifdef CONFIG_IXGBE_DCA
1267 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1268 struct ixgbe_ring *tx_ring,
1269 int cpu)
1270 {
1271 struct ixgbe_hw *hw = &adapter->hw;
1272 u32 txctrl = 0;
1273 u16 reg_offset;
1274
1275 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1276 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1277
1278 switch (hw->mac.type) {
1279 case ixgbe_mac_82598EB:
1280 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1281 break;
1282 case ixgbe_mac_82599EB:
1283 case ixgbe_mac_X540:
1284 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1285 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1286 break;
1287 default:
1288 /* for unknown hardware do not write register */
1289 return;
1290 }
1291
1292 /*
1293 * We can enable relaxed ordering for reads, but not writes when
1294 * DCA is enabled. This is due to a known issue in some chipsets
1295 * which will cause the DCA tag to be cleared.
1296 */
1297 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1298 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1299 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1300
1301 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1302 }
1303
1304 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1305 struct ixgbe_ring *rx_ring,
1306 int cpu)
1307 {
1308 struct ixgbe_hw *hw = &adapter->hw;
1309 u32 rxctrl = 0;
1310 u8 reg_idx = rx_ring->reg_idx;
1311
1312 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1313 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1314
1315 switch (hw->mac.type) {
1316 case ixgbe_mac_82599EB:
1317 case ixgbe_mac_X540:
1318 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1319 break;
1320 default:
1321 break;
1322 }
1323
1324 /*
1325 * We can enable relaxed ordering for reads, but not writes when
1326 * DCA is enabled. This is due to a known issue in some chipsets
1327 * which will cause the DCA tag to be cleared.
1328 */
1329 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1330 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
1331 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1332
1333 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1334 }
1335
1336 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1337 {
1338 struct ixgbe_adapter *adapter = q_vector->adapter;
1339 struct ixgbe_ring *ring;
1340 int cpu = get_cpu();
1341
1342 if (q_vector->cpu == cpu)
1343 goto out_no_update;
1344
1345 ixgbe_for_each_ring(ring, q_vector->tx)
1346 ixgbe_update_tx_dca(adapter, ring, cpu);
1347
1348 ixgbe_for_each_ring(ring, q_vector->rx)
1349 ixgbe_update_rx_dca(adapter, ring, cpu);
1350
1351 q_vector->cpu = cpu;
1352 out_no_update:
1353 put_cpu();
1354 }
1355
1356 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1357 {
1358 int i;
1359
1360 /* always use CB2 mode, difference is masked in the CB driver */
1361 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1362 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1363 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1364 else
1365 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1366 IXGBE_DCA_CTRL_DCA_DISABLE);
1367
1368 for (i = 0; i < adapter->num_q_vectors; i++) {
1369 adapter->q_vector[i]->cpu = -1;
1370 ixgbe_update_dca(adapter->q_vector[i]);
1371 }
1372 }
1373
1374 static int __ixgbe_notify_dca(struct device *dev, void *data)
1375 {
1376 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1377 unsigned long event = *(unsigned long *)data;
1378
1379 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1380 return 0;
1381
1382 switch (event) {
1383 case DCA_PROVIDER_ADD:
1384 /* if we're already enabled, don't do it again */
1385 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1386 break;
1387 if (dca_add_requester(dev) == 0) {
1388 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1389 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1390 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1391 break;
1392 }
1393 /* Fall Through since DCA is disabled. */
1394 case DCA_PROVIDER_REMOVE:
1395 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1396 dca_remove_requester(dev);
1397 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1398 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1399 IXGBE_DCA_CTRL_DCA_DISABLE);
1400 }
1401 break;
1402 }
1403
1404 return 0;
1405 }
1406
1407 #endif /* CONFIG_IXGBE_DCA */
1408
1409 #define IXGBE_RSS_L4_TYPES_MASK \
1410 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1411 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1412 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1413 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1414
1415 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1416 union ixgbe_adv_rx_desc *rx_desc,
1417 struct sk_buff *skb)
1418 {
1419 u16 rss_type;
1420
1421 if (!(ring->netdev->features & NETIF_F_RXHASH))
1422 return;
1423
1424 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1425 IXGBE_RXDADV_RSSTYPE_MASK;
1426
1427 if (!rss_type)
1428 return;
1429
1430 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1431 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1432 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
1433 }
1434
1435 #ifdef IXGBE_FCOE
1436 /**
1437 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1438 * @ring: structure containing ring specific data
1439 * @rx_desc: advanced rx descriptor
1440 *
1441 * Returns : true if it is FCoE pkt
1442 */
1443 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1444 union ixgbe_adv_rx_desc *rx_desc)
1445 {
1446 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1447
1448 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1449 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1450 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1451 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1452 }
1453
1454 #endif /* IXGBE_FCOE */
1455 /**
1456 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1457 * @ring: structure containing ring specific data
1458 * @rx_desc: current Rx descriptor being processed
1459 * @skb: skb currently being received and modified
1460 **/
1461 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1462 union ixgbe_adv_rx_desc *rx_desc,
1463 struct sk_buff *skb)
1464 {
1465 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1466 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1467 bool encap_pkt = false;
1468
1469 skb_checksum_none_assert(skb);
1470
1471 /* Rx csum disabled */
1472 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1473 return;
1474
1475 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1476 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1477 encap_pkt = true;
1478 skb->encapsulation = 1;
1479 }
1480
1481 /* if IP and error */
1482 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1483 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1484 ring->rx_stats.csum_err++;
1485 return;
1486 }
1487
1488 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1489 return;
1490
1491 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1492 /*
1493 * 82599 errata, UDP frames with a 0 checksum can be marked as
1494 * checksum errors.
1495 */
1496 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1497 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1498 return;
1499
1500 ring->rx_stats.csum_err++;
1501 return;
1502 }
1503
1504 /* It must be a TCP or UDP packet with a valid checksum */
1505 skb->ip_summed = CHECKSUM_UNNECESSARY;
1506 if (encap_pkt) {
1507 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1508 return;
1509
1510 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1511 skb->ip_summed = CHECKSUM_NONE;
1512 return;
1513 }
1514 /* If we checked the outer header let the stack know */
1515 skb->csum_level = 1;
1516 }
1517 }
1518
1519 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1520 struct ixgbe_rx_buffer *bi)
1521 {
1522 struct page *page = bi->page;
1523 dma_addr_t dma;
1524
1525 /* since we are recycling buffers we should seldom need to alloc */
1526 if (likely(page))
1527 return true;
1528
1529 /* alloc new page for storage */
1530 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1531 if (unlikely(!page)) {
1532 rx_ring->rx_stats.alloc_rx_page_failed++;
1533 return false;
1534 }
1535
1536 /* map page for use */
1537 dma = dma_map_page(rx_ring->dev, page, 0,
1538 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1539
1540 /*
1541 * if mapping failed free memory back to system since
1542 * there isn't much point in holding memory we can't use
1543 */
1544 if (dma_mapping_error(rx_ring->dev, dma)) {
1545 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1546
1547 rx_ring->rx_stats.alloc_rx_page_failed++;
1548 return false;
1549 }
1550
1551 bi->dma = dma;
1552 bi->page = page;
1553 bi->page_offset = 0;
1554
1555 return true;
1556 }
1557
1558 /**
1559 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1560 * @rx_ring: ring to place buffers on
1561 * @cleaned_count: number of buffers to replace
1562 **/
1563 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1564 {
1565 union ixgbe_adv_rx_desc *rx_desc;
1566 struct ixgbe_rx_buffer *bi;
1567 u16 i = rx_ring->next_to_use;
1568
1569 /* nothing to do */
1570 if (!cleaned_count)
1571 return;
1572
1573 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1574 bi = &rx_ring->rx_buffer_info[i];
1575 i -= rx_ring->count;
1576
1577 do {
1578 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1579 break;
1580
1581 /*
1582 * Refresh the desc even if buffer_addrs didn't change
1583 * because each write-back erases this info.
1584 */
1585 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1586
1587 rx_desc++;
1588 bi++;
1589 i++;
1590 if (unlikely(!i)) {
1591 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1592 bi = rx_ring->rx_buffer_info;
1593 i -= rx_ring->count;
1594 }
1595
1596 /* clear the status bits for the next_to_use descriptor */
1597 rx_desc->wb.upper.status_error = 0;
1598
1599 cleaned_count--;
1600 } while (cleaned_count);
1601
1602 i += rx_ring->count;
1603
1604 if (rx_ring->next_to_use != i) {
1605 rx_ring->next_to_use = i;
1606
1607 /* update next to alloc since we have filled the ring */
1608 rx_ring->next_to_alloc = i;
1609
1610 /* Force memory writes to complete before letting h/w
1611 * know there are new descriptors to fetch. (Only
1612 * applicable for weak-ordered memory model archs,
1613 * such as IA-64).
1614 */
1615 wmb();
1616 writel(i, rx_ring->tail);
1617 }
1618 }
1619
1620 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1621 struct sk_buff *skb)
1622 {
1623 u16 hdr_len = skb_headlen(skb);
1624
1625 /* set gso_size to avoid messing up TCP MSS */
1626 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1627 IXGBE_CB(skb)->append_cnt);
1628 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1629 }
1630
1631 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1632 struct sk_buff *skb)
1633 {
1634 /* if append_cnt is 0 then frame is not RSC */
1635 if (!IXGBE_CB(skb)->append_cnt)
1636 return;
1637
1638 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1639 rx_ring->rx_stats.rsc_flush++;
1640
1641 ixgbe_set_rsc_gso_size(rx_ring, skb);
1642
1643 /* gso_size is computed using append_cnt so always clear it last */
1644 IXGBE_CB(skb)->append_cnt = 0;
1645 }
1646
1647 /**
1648 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1649 * @rx_ring: rx descriptor ring packet is being transacted on
1650 * @rx_desc: pointer to the EOP Rx descriptor
1651 * @skb: pointer to current skb being populated
1652 *
1653 * This function checks the ring, descriptor, and packet information in
1654 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1655 * other fields within the skb.
1656 **/
1657 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1658 union ixgbe_adv_rx_desc *rx_desc,
1659 struct sk_buff *skb)
1660 {
1661 struct net_device *dev = rx_ring->netdev;
1662 u32 flags = rx_ring->q_vector->adapter->flags;
1663
1664 ixgbe_update_rsc_stats(rx_ring, skb);
1665
1666 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1667
1668 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1669
1670 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED))
1671 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1672
1673 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1674 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1675 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1676 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1677 }
1678
1679 skb_record_rx_queue(skb, rx_ring->queue_index);
1680
1681 skb->protocol = eth_type_trans(skb, dev);
1682 }
1683
1684 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1685 struct sk_buff *skb)
1686 {
1687 skb_mark_napi_id(skb, &q_vector->napi);
1688 if (ixgbe_qv_busy_polling(q_vector))
1689 netif_receive_skb(skb);
1690 else
1691 napi_gro_receive(&q_vector->napi, skb);
1692 }
1693
1694 /**
1695 * ixgbe_is_non_eop - process handling of non-EOP buffers
1696 * @rx_ring: Rx ring being processed
1697 * @rx_desc: Rx descriptor for current buffer
1698 * @skb: Current socket buffer containing buffer in progress
1699 *
1700 * This function updates next to clean. If the buffer is an EOP buffer
1701 * this function exits returning false, otherwise it will place the
1702 * sk_buff in the next buffer to be chained and return true indicating
1703 * that this is in fact a non-EOP buffer.
1704 **/
1705 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1706 union ixgbe_adv_rx_desc *rx_desc,
1707 struct sk_buff *skb)
1708 {
1709 u32 ntc = rx_ring->next_to_clean + 1;
1710
1711 /* fetch, update, and store next to clean */
1712 ntc = (ntc < rx_ring->count) ? ntc : 0;
1713 rx_ring->next_to_clean = ntc;
1714
1715 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1716
1717 /* update RSC append count if present */
1718 if (ring_is_rsc_enabled(rx_ring)) {
1719 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1720 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1721
1722 if (unlikely(rsc_enabled)) {
1723 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1724
1725 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1726 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1727
1728 /* update ntc based on RSC value */
1729 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1730 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1731 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1732 }
1733 }
1734
1735 /* if we are the last buffer then there is nothing else to do */
1736 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1737 return false;
1738
1739 /* place skb in next buffer to be received */
1740 rx_ring->rx_buffer_info[ntc].skb = skb;
1741 rx_ring->rx_stats.non_eop_descs++;
1742
1743 return true;
1744 }
1745
1746 /**
1747 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1748 * @rx_ring: rx descriptor ring packet is being transacted on
1749 * @skb: pointer to current skb being adjusted
1750 *
1751 * This function is an ixgbe specific version of __pskb_pull_tail. The
1752 * main difference between this version and the original function is that
1753 * this function can make several assumptions about the state of things
1754 * that allow for significant optimizations versus the standard function.
1755 * As a result we can do things like drop a frag and maintain an accurate
1756 * truesize for the skb.
1757 */
1758 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1759 struct sk_buff *skb)
1760 {
1761 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1762 unsigned char *va;
1763 unsigned int pull_len;
1764
1765 /*
1766 * it is valid to use page_address instead of kmap since we are
1767 * working with pages allocated out of the lomem pool per
1768 * alloc_page(GFP_ATOMIC)
1769 */
1770 va = skb_frag_address(frag);
1771
1772 /*
1773 * we need the header to contain the greater of either ETH_HLEN or
1774 * 60 bytes if the skb->len is less than 60 for skb_pad.
1775 */
1776 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
1777
1778 /* align pull length to size of long to optimize memcpy performance */
1779 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1780
1781 /* update all of the pointers */
1782 skb_frag_size_sub(frag, pull_len);
1783 frag->page_offset += pull_len;
1784 skb->data_len -= pull_len;
1785 skb->tail += pull_len;
1786 }
1787
1788 /**
1789 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1790 * @rx_ring: rx descriptor ring packet is being transacted on
1791 * @skb: pointer to current skb being updated
1792 *
1793 * This function provides a basic DMA sync up for the first fragment of an
1794 * skb. The reason for doing this is that the first fragment cannot be
1795 * unmapped until we have reached the end of packet descriptor for a buffer
1796 * chain.
1797 */
1798 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1799 struct sk_buff *skb)
1800 {
1801 /* if the page was released unmap it, else just sync our portion */
1802 if (unlikely(IXGBE_CB(skb)->page_released)) {
1803 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1804 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1805 IXGBE_CB(skb)->page_released = false;
1806 } else {
1807 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1808
1809 dma_sync_single_range_for_cpu(rx_ring->dev,
1810 IXGBE_CB(skb)->dma,
1811 frag->page_offset,
1812 ixgbe_rx_bufsz(rx_ring),
1813 DMA_FROM_DEVICE);
1814 }
1815 IXGBE_CB(skb)->dma = 0;
1816 }
1817
1818 /**
1819 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1820 * @rx_ring: rx descriptor ring packet is being transacted on
1821 * @rx_desc: pointer to the EOP Rx descriptor
1822 * @skb: pointer to current skb being fixed
1823 *
1824 * Check for corrupted packet headers caused by senders on the local L2
1825 * embedded NIC switch not setting up their Tx Descriptors right. These
1826 * should be very rare.
1827 *
1828 * Also address the case where we are pulling data in on pages only
1829 * and as such no data is present in the skb header.
1830 *
1831 * In addition if skb is not at least 60 bytes we need to pad it so that
1832 * it is large enough to qualify as a valid Ethernet frame.
1833 *
1834 * Returns true if an error was encountered and skb was freed.
1835 **/
1836 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1837 union ixgbe_adv_rx_desc *rx_desc,
1838 struct sk_buff *skb)
1839 {
1840 struct net_device *netdev = rx_ring->netdev;
1841
1842 /* verify that the packet does not have any known errors */
1843 if (unlikely(ixgbe_test_staterr(rx_desc,
1844 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1845 !(netdev->features & NETIF_F_RXALL))) {
1846 dev_kfree_skb_any(skb);
1847 return true;
1848 }
1849
1850 /* place header in linear portion of buffer */
1851 if (skb_is_nonlinear(skb))
1852 ixgbe_pull_tail(rx_ring, skb);
1853
1854 #ifdef IXGBE_FCOE
1855 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1856 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1857 return false;
1858
1859 #endif
1860 /* if eth_skb_pad returns an error the skb was freed */
1861 if (eth_skb_pad(skb))
1862 return true;
1863
1864 return false;
1865 }
1866
1867 /**
1868 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1869 * @rx_ring: rx descriptor ring to store buffers on
1870 * @old_buff: donor buffer to have page reused
1871 *
1872 * Synchronizes page for reuse by the adapter
1873 **/
1874 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1875 struct ixgbe_rx_buffer *old_buff)
1876 {
1877 struct ixgbe_rx_buffer *new_buff;
1878 u16 nta = rx_ring->next_to_alloc;
1879
1880 new_buff = &rx_ring->rx_buffer_info[nta];
1881
1882 /* update, and store next to alloc */
1883 nta++;
1884 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1885
1886 /* transfer page from old buffer to new buffer */
1887 *new_buff = *old_buff;
1888
1889 /* sync the buffer for use by the device */
1890 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1891 new_buff->page_offset,
1892 ixgbe_rx_bufsz(rx_ring),
1893 DMA_FROM_DEVICE);
1894 }
1895
1896 static inline bool ixgbe_page_is_reserved(struct page *page)
1897 {
1898 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
1899 }
1900
1901 /**
1902 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1903 * @rx_ring: rx descriptor ring to transact packets on
1904 * @rx_buffer: buffer containing page to add
1905 * @rx_desc: descriptor containing length of buffer written by hardware
1906 * @skb: sk_buff to place the data into
1907 *
1908 * This function will add the data contained in rx_buffer->page to the skb.
1909 * This is done either through a direct copy if the data in the buffer is
1910 * less than the skb header size, otherwise it will just attach the page as
1911 * a frag to the skb.
1912 *
1913 * The function will then update the page offset if necessary and return
1914 * true if the buffer can be reused by the adapter.
1915 **/
1916 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1917 struct ixgbe_rx_buffer *rx_buffer,
1918 union ixgbe_adv_rx_desc *rx_desc,
1919 struct sk_buff *skb)
1920 {
1921 struct page *page = rx_buffer->page;
1922 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1923 #if (PAGE_SIZE < 8192)
1924 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1925 #else
1926 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1927 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1928 ixgbe_rx_bufsz(rx_ring);
1929 #endif
1930
1931 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1932 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1933
1934 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1935
1936 /* page is not reserved, we can reuse buffer as-is */
1937 if (likely(!ixgbe_page_is_reserved(page)))
1938 return true;
1939
1940 /* this page cannot be reused so discard it */
1941 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1942 return false;
1943 }
1944
1945 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1946 rx_buffer->page_offset, size, truesize);
1947
1948 /* avoid re-using remote pages */
1949 if (unlikely(ixgbe_page_is_reserved(page)))
1950 return false;
1951
1952 #if (PAGE_SIZE < 8192)
1953 /* if we are only owner of page we can reuse it */
1954 if (unlikely(page_count(page) != 1))
1955 return false;
1956
1957 /* flip page offset to other buffer */
1958 rx_buffer->page_offset ^= truesize;
1959 #else
1960 /* move offset up to the next cache line */
1961 rx_buffer->page_offset += truesize;
1962
1963 if (rx_buffer->page_offset > last_offset)
1964 return false;
1965 #endif
1966
1967 /* Even if we own the page, we are not allowed to use atomic_set()
1968 * This would break get_page_unless_zero() users.
1969 */
1970 page_ref_inc(page);
1971
1972 return true;
1973 }
1974
1975 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1976 union ixgbe_adv_rx_desc *rx_desc)
1977 {
1978 struct ixgbe_rx_buffer *rx_buffer;
1979 struct sk_buff *skb;
1980 struct page *page;
1981
1982 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1983 page = rx_buffer->page;
1984 prefetchw(page);
1985
1986 skb = rx_buffer->skb;
1987
1988 if (likely(!skb)) {
1989 void *page_addr = page_address(page) +
1990 rx_buffer->page_offset;
1991
1992 /* prefetch first cache line of first page */
1993 prefetch(page_addr);
1994 #if L1_CACHE_BYTES < 128
1995 prefetch(page_addr + L1_CACHE_BYTES);
1996 #endif
1997
1998 /* allocate a skb to store the frags */
1999 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
2000 IXGBE_RX_HDR_SIZE);
2001 if (unlikely(!skb)) {
2002 rx_ring->rx_stats.alloc_rx_buff_failed++;
2003 return NULL;
2004 }
2005
2006 /*
2007 * we will be copying header into skb->data in
2008 * pskb_may_pull so it is in our interest to prefetch
2009 * it now to avoid a possible cache miss
2010 */
2011 prefetchw(skb->data);
2012
2013 /*
2014 * Delay unmapping of the first packet. It carries the
2015 * header information, HW may still access the header
2016 * after the writeback. Only unmap it when EOP is
2017 * reached
2018 */
2019 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
2020 goto dma_sync;
2021
2022 IXGBE_CB(skb)->dma = rx_buffer->dma;
2023 } else {
2024 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2025 ixgbe_dma_sync_frag(rx_ring, skb);
2026
2027 dma_sync:
2028 /* we are reusing so sync this buffer for CPU use */
2029 dma_sync_single_range_for_cpu(rx_ring->dev,
2030 rx_buffer->dma,
2031 rx_buffer->page_offset,
2032 ixgbe_rx_bufsz(rx_ring),
2033 DMA_FROM_DEVICE);
2034
2035 rx_buffer->skb = NULL;
2036 }
2037
2038 /* pull page into skb */
2039 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2040 /* hand second half of page back to the ring */
2041 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2042 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2043 /* the page has been released from the ring */
2044 IXGBE_CB(skb)->page_released = true;
2045 } else {
2046 /* we are not reusing the buffer so unmap it */
2047 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2048 ixgbe_rx_pg_size(rx_ring),
2049 DMA_FROM_DEVICE);
2050 }
2051
2052 /* clear contents of buffer_info */
2053 rx_buffer->page = NULL;
2054
2055 return skb;
2056 }
2057
2058 /**
2059 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2060 * @q_vector: structure containing interrupt and ring information
2061 * @rx_ring: rx descriptor ring to transact packets on
2062 * @budget: Total limit on number of packets to process
2063 *
2064 * This function provides a "bounce buffer" approach to Rx interrupt
2065 * processing. The advantage to this is that on systems that have
2066 * expensive overhead for IOMMU access this provides a means of avoiding
2067 * it by maintaining the mapping of the page to the syste.
2068 *
2069 * Returns amount of work completed
2070 **/
2071 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
2072 struct ixgbe_ring *rx_ring,
2073 const int budget)
2074 {
2075 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2076 #ifdef IXGBE_FCOE
2077 struct ixgbe_adapter *adapter = q_vector->adapter;
2078 int ddp_bytes;
2079 unsigned int mss = 0;
2080 #endif /* IXGBE_FCOE */
2081 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
2082
2083 while (likely(total_rx_packets < budget)) {
2084 union ixgbe_adv_rx_desc *rx_desc;
2085 struct sk_buff *skb;
2086
2087 /* return some buffers to hardware, one at a time is too slow */
2088 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2089 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2090 cleaned_count = 0;
2091 }
2092
2093 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2094
2095 if (!rx_desc->wb.upper.status_error)
2096 break;
2097
2098 /* This memory barrier is needed to keep us from reading
2099 * any other fields out of the rx_desc until we know the
2100 * descriptor has been written back
2101 */
2102 dma_rmb();
2103
2104 /* retrieve a buffer from the ring */
2105 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
2106
2107 /* exit if we failed to retrieve a buffer */
2108 if (!skb)
2109 break;
2110
2111 cleaned_count++;
2112
2113 /* place incomplete frames back on ring for completion */
2114 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2115 continue;
2116
2117 /* verify the packet layout is correct */
2118 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2119 continue;
2120
2121 /* probably a little skewed due to removing CRC */
2122 total_rx_bytes += skb->len;
2123
2124 /* populate checksum, timestamp, VLAN, and protocol */
2125 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2126
2127 #ifdef IXGBE_FCOE
2128 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2129 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2130 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2131 /* include DDPed FCoE data */
2132 if (ddp_bytes > 0) {
2133 if (!mss) {
2134 mss = rx_ring->netdev->mtu -
2135 sizeof(struct fcoe_hdr) -
2136 sizeof(struct fc_frame_header) -
2137 sizeof(struct fcoe_crc_eof);
2138 if (mss > 512)
2139 mss &= ~511;
2140 }
2141 total_rx_bytes += ddp_bytes;
2142 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2143 mss);
2144 }
2145 if (!ddp_bytes) {
2146 dev_kfree_skb_any(skb);
2147 continue;
2148 }
2149 }
2150
2151 #endif /* IXGBE_FCOE */
2152 ixgbe_rx_skb(q_vector, skb);
2153
2154 /* update budget accounting */
2155 total_rx_packets++;
2156 }
2157
2158 u64_stats_update_begin(&rx_ring->syncp);
2159 rx_ring->stats.packets += total_rx_packets;
2160 rx_ring->stats.bytes += total_rx_bytes;
2161 u64_stats_update_end(&rx_ring->syncp);
2162 q_vector->rx.total_packets += total_rx_packets;
2163 q_vector->rx.total_bytes += total_rx_bytes;
2164
2165 return total_rx_packets;
2166 }
2167
2168 #ifdef CONFIG_NET_RX_BUSY_POLL
2169 /* must be called with local_bh_disable()d */
2170 static int ixgbe_low_latency_recv(struct napi_struct *napi)
2171 {
2172 struct ixgbe_q_vector *q_vector =
2173 container_of(napi, struct ixgbe_q_vector, napi);
2174 struct ixgbe_adapter *adapter = q_vector->adapter;
2175 struct ixgbe_ring *ring;
2176 int found = 0;
2177
2178 if (test_bit(__IXGBE_DOWN, &adapter->state))
2179 return LL_FLUSH_FAILED;
2180
2181 if (!ixgbe_qv_lock_poll(q_vector))
2182 return LL_FLUSH_BUSY;
2183
2184 ixgbe_for_each_ring(ring, q_vector->rx) {
2185 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
2186 #ifdef BP_EXTENDED_STATS
2187 if (found)
2188 ring->stats.cleaned += found;
2189 else
2190 ring->stats.misses++;
2191 #endif
2192 if (found)
2193 break;
2194 }
2195
2196 ixgbe_qv_unlock_poll(q_vector);
2197
2198 return found;
2199 }
2200 #endif /* CONFIG_NET_RX_BUSY_POLL */
2201
2202 /**
2203 * ixgbe_configure_msix - Configure MSI-X hardware
2204 * @adapter: board private structure
2205 *
2206 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2207 * interrupts.
2208 **/
2209 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2210 {
2211 struct ixgbe_q_vector *q_vector;
2212 int v_idx;
2213 u32 mask;
2214
2215 /* Populate MSIX to EITR Select */
2216 if (adapter->num_vfs > 32) {
2217 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2218 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2219 }
2220
2221 /*
2222 * Populate the IVAR table and set the ITR values to the
2223 * corresponding register.
2224 */
2225 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2226 struct ixgbe_ring *ring;
2227 q_vector = adapter->q_vector[v_idx];
2228
2229 ixgbe_for_each_ring(ring, q_vector->rx)
2230 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2231
2232 ixgbe_for_each_ring(ring, q_vector->tx)
2233 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2234
2235 ixgbe_write_eitr(q_vector);
2236 }
2237
2238 switch (adapter->hw.mac.type) {
2239 case ixgbe_mac_82598EB:
2240 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2241 v_idx);
2242 break;
2243 case ixgbe_mac_82599EB:
2244 case ixgbe_mac_X540:
2245 case ixgbe_mac_X550:
2246 case ixgbe_mac_X550EM_x:
2247 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2248 break;
2249 default:
2250 break;
2251 }
2252 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2253
2254 /* set up to autoclear timer, and the vectors */
2255 mask = IXGBE_EIMS_ENABLE_MASK;
2256 mask &= ~(IXGBE_EIMS_OTHER |
2257 IXGBE_EIMS_MAILBOX |
2258 IXGBE_EIMS_LSC);
2259
2260 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2261 }
2262
2263 enum latency_range {
2264 lowest_latency = 0,
2265 low_latency = 1,
2266 bulk_latency = 2,
2267 latency_invalid = 255
2268 };
2269
2270 /**
2271 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2272 * @q_vector: structure containing interrupt and ring information
2273 * @ring_container: structure containing ring performance data
2274 *
2275 * Stores a new ITR value based on packets and byte
2276 * counts during the last interrupt. The advantage of per interrupt
2277 * computation is faster updates and more accurate ITR for the current
2278 * traffic pattern. Constants in this function were computed
2279 * based on theoretical maximum wire speed and thresholds were set based
2280 * on testing data as well as attempting to minimize response time
2281 * while increasing bulk throughput.
2282 * this functionality is controlled by the InterruptThrottleRate module
2283 * parameter (see ixgbe_param.c)
2284 **/
2285 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2286 struct ixgbe_ring_container *ring_container)
2287 {
2288 int bytes = ring_container->total_bytes;
2289 int packets = ring_container->total_packets;
2290 u32 timepassed_us;
2291 u64 bytes_perint;
2292 u8 itr_setting = ring_container->itr;
2293
2294 if (packets == 0)
2295 return;
2296
2297 /* simple throttlerate management
2298 * 0-10MB/s lowest (100000 ints/s)
2299 * 10-20MB/s low (20000 ints/s)
2300 * 20-1249MB/s bulk (12000 ints/s)
2301 */
2302 /* what was last interrupt timeslice? */
2303 timepassed_us = q_vector->itr >> 2;
2304 if (timepassed_us == 0)
2305 return;
2306
2307 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2308
2309 switch (itr_setting) {
2310 case lowest_latency:
2311 if (bytes_perint > 10)
2312 itr_setting = low_latency;
2313 break;
2314 case low_latency:
2315 if (bytes_perint > 20)
2316 itr_setting = bulk_latency;
2317 else if (bytes_perint <= 10)
2318 itr_setting = lowest_latency;
2319 break;
2320 case bulk_latency:
2321 if (bytes_perint <= 20)
2322 itr_setting = low_latency;
2323 break;
2324 }
2325
2326 /* clear work counters since we have the values we need */
2327 ring_container->total_bytes = 0;
2328 ring_container->total_packets = 0;
2329
2330 /* write updated itr to ring container */
2331 ring_container->itr = itr_setting;
2332 }
2333
2334 /**
2335 * ixgbe_write_eitr - write EITR register in hardware specific way
2336 * @q_vector: structure containing interrupt and ring information
2337 *
2338 * This function is made to be called by ethtool and by the driver
2339 * when it needs to update EITR registers at runtime. Hardware
2340 * specific quirks/differences are taken care of here.
2341 */
2342 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2343 {
2344 struct ixgbe_adapter *adapter = q_vector->adapter;
2345 struct ixgbe_hw *hw = &adapter->hw;
2346 int v_idx = q_vector->v_idx;
2347 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2348
2349 switch (adapter->hw.mac.type) {
2350 case ixgbe_mac_82598EB:
2351 /* must write high and low 16 bits to reset counter */
2352 itr_reg |= (itr_reg << 16);
2353 break;
2354 case ixgbe_mac_82599EB:
2355 case ixgbe_mac_X540:
2356 case ixgbe_mac_X550:
2357 case ixgbe_mac_X550EM_x:
2358 /*
2359 * set the WDIS bit to not clear the timer bits and cause an
2360 * immediate assertion of the interrupt
2361 */
2362 itr_reg |= IXGBE_EITR_CNT_WDIS;
2363 break;
2364 default:
2365 break;
2366 }
2367 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2368 }
2369
2370 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2371 {
2372 u32 new_itr = q_vector->itr;
2373 u8 current_itr;
2374
2375 ixgbe_update_itr(q_vector, &q_vector->tx);
2376 ixgbe_update_itr(q_vector, &q_vector->rx);
2377
2378 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2379
2380 switch (current_itr) {
2381 /* counts and packets in update_itr are dependent on these numbers */
2382 case lowest_latency:
2383 new_itr = IXGBE_100K_ITR;
2384 break;
2385 case low_latency:
2386 new_itr = IXGBE_20K_ITR;
2387 break;
2388 case bulk_latency:
2389 new_itr = IXGBE_12K_ITR;
2390 break;
2391 default:
2392 break;
2393 }
2394
2395 if (new_itr != q_vector->itr) {
2396 /* do an exponential smoothing */
2397 new_itr = (10 * new_itr * q_vector->itr) /
2398 ((9 * new_itr) + q_vector->itr);
2399
2400 /* save the algorithm value here */
2401 q_vector->itr = new_itr;
2402
2403 ixgbe_write_eitr(q_vector);
2404 }
2405 }
2406
2407 /**
2408 * ixgbe_check_overtemp_subtask - check for over temperature
2409 * @adapter: pointer to adapter
2410 **/
2411 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2412 {
2413 struct ixgbe_hw *hw = &adapter->hw;
2414 u32 eicr = adapter->interrupt_event;
2415
2416 if (test_bit(__IXGBE_DOWN, &adapter->state))
2417 return;
2418
2419 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2420 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2421 return;
2422
2423 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2424
2425 switch (hw->device_id) {
2426 case IXGBE_DEV_ID_82599_T3_LOM:
2427 /*
2428 * Since the warning interrupt is for both ports
2429 * we don't have to check if:
2430 * - This interrupt wasn't for our port.
2431 * - We may have missed the interrupt so always have to
2432 * check if we got a LSC
2433 */
2434 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
2435 !(eicr & IXGBE_EICR_LSC))
2436 return;
2437
2438 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2439 u32 speed;
2440 bool link_up = false;
2441
2442 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2443
2444 if (link_up)
2445 return;
2446 }
2447
2448 /* Check if this is not due to overtemp */
2449 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2450 return;
2451
2452 break;
2453 default:
2454 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2455 return;
2456 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
2457 return;
2458 break;
2459 }
2460 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2461
2462 adapter->interrupt_event = 0;
2463 }
2464
2465 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2466 {
2467 struct ixgbe_hw *hw = &adapter->hw;
2468
2469 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2470 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2471 e_crit(probe, "Fan has stopped, replace the adapter\n");
2472 /* write to clear the interrupt */
2473 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2474 }
2475 }
2476
2477 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2478 {
2479 struct ixgbe_hw *hw = &adapter->hw;
2480
2481 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2482 return;
2483
2484 switch (adapter->hw.mac.type) {
2485 case ixgbe_mac_82599EB:
2486 /*
2487 * Need to check link state so complete overtemp check
2488 * on service task
2489 */
2490 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2491 (eicr & IXGBE_EICR_LSC)) &&
2492 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2493 adapter->interrupt_event = eicr;
2494 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2495 ixgbe_service_event_schedule(adapter);
2496 return;
2497 }
2498 return;
2499 case ixgbe_mac_X540:
2500 if (!(eicr & IXGBE_EICR_TS))
2501 return;
2502 break;
2503 default:
2504 return;
2505 }
2506
2507 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2508 }
2509
2510 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2511 {
2512 switch (hw->mac.type) {
2513 case ixgbe_mac_82598EB:
2514 if (hw->phy.type == ixgbe_phy_nl)
2515 return true;
2516 return false;
2517 case ixgbe_mac_82599EB:
2518 case ixgbe_mac_X550EM_x:
2519 switch (hw->mac.ops.get_media_type(hw)) {
2520 case ixgbe_media_type_fiber:
2521 case ixgbe_media_type_fiber_qsfp:
2522 return true;
2523 default:
2524 return false;
2525 }
2526 default:
2527 return false;
2528 }
2529 }
2530
2531 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2532 {
2533 struct ixgbe_hw *hw = &adapter->hw;
2534 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
2535
2536 if (!ixgbe_is_sfp(hw))
2537 return;
2538
2539 /* Later MAC's use different SDP */
2540 if (hw->mac.type >= ixgbe_mac_X540)
2541 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2542
2543 if (eicr & eicr_mask) {
2544 /* Clear the interrupt */
2545 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
2546 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2547 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2548 adapter->sfp_poll_time = 0;
2549 ixgbe_service_event_schedule(adapter);
2550 }
2551 }
2552
2553 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2554 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2555 /* Clear the interrupt */
2556 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2557 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2558 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2559 ixgbe_service_event_schedule(adapter);
2560 }
2561 }
2562 }
2563
2564 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2565 {
2566 struct ixgbe_hw *hw = &adapter->hw;
2567
2568 adapter->lsc_int++;
2569 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2570 adapter->link_check_timeout = jiffies;
2571 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2572 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2573 IXGBE_WRITE_FLUSH(hw);
2574 ixgbe_service_event_schedule(adapter);
2575 }
2576 }
2577
2578 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2579 u64 qmask)
2580 {
2581 u32 mask;
2582 struct ixgbe_hw *hw = &adapter->hw;
2583
2584 switch (hw->mac.type) {
2585 case ixgbe_mac_82598EB:
2586 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2587 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2588 break;
2589 case ixgbe_mac_82599EB:
2590 case ixgbe_mac_X540:
2591 case ixgbe_mac_X550:
2592 case ixgbe_mac_X550EM_x:
2593 mask = (qmask & 0xFFFFFFFF);
2594 if (mask)
2595 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2596 mask = (qmask >> 32);
2597 if (mask)
2598 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2599 break;
2600 default:
2601 break;
2602 }
2603 /* skip the flush */
2604 }
2605
2606 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2607 u64 qmask)
2608 {
2609 u32 mask;
2610 struct ixgbe_hw *hw = &adapter->hw;
2611
2612 switch (hw->mac.type) {
2613 case ixgbe_mac_82598EB:
2614 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2615 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2616 break;
2617 case ixgbe_mac_82599EB:
2618 case ixgbe_mac_X540:
2619 case ixgbe_mac_X550:
2620 case ixgbe_mac_X550EM_x:
2621 mask = (qmask & 0xFFFFFFFF);
2622 if (mask)
2623 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2624 mask = (qmask >> 32);
2625 if (mask)
2626 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2627 break;
2628 default:
2629 break;
2630 }
2631 /* skip the flush */
2632 }
2633
2634 /**
2635 * ixgbe_irq_enable - Enable default interrupt generation settings
2636 * @adapter: board private structure
2637 **/
2638 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2639 bool flush)
2640 {
2641 struct ixgbe_hw *hw = &adapter->hw;
2642 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2643
2644 /* don't reenable LSC while waiting for link */
2645 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2646 mask &= ~IXGBE_EIMS_LSC;
2647
2648 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2649 switch (adapter->hw.mac.type) {
2650 case ixgbe_mac_82599EB:
2651 mask |= IXGBE_EIMS_GPI_SDP0(hw);
2652 break;
2653 case ixgbe_mac_X540:
2654 case ixgbe_mac_X550:
2655 case ixgbe_mac_X550EM_x:
2656 mask |= IXGBE_EIMS_TS;
2657 break;
2658 default:
2659 break;
2660 }
2661 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2662 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2663 switch (adapter->hw.mac.type) {
2664 case ixgbe_mac_82599EB:
2665 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2666 mask |= IXGBE_EIMS_GPI_SDP2(hw);
2667 /* fall through */
2668 case ixgbe_mac_X540:
2669 case ixgbe_mac_X550:
2670 case ixgbe_mac_X550EM_x:
2671 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2672 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
2673 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2674 mask |= IXGBE_EICR_GPI_SDP0_X540;
2675 mask |= IXGBE_EIMS_ECC;
2676 mask |= IXGBE_EIMS_MAILBOX;
2677 break;
2678 default:
2679 break;
2680 }
2681
2682 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2683 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2684 mask |= IXGBE_EIMS_FLOW_DIR;
2685
2686 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2687 if (queues)
2688 ixgbe_irq_enable_queues(adapter, ~0);
2689 if (flush)
2690 IXGBE_WRITE_FLUSH(&adapter->hw);
2691 }
2692
2693 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2694 {
2695 struct ixgbe_adapter *adapter = data;
2696 struct ixgbe_hw *hw = &adapter->hw;
2697 u32 eicr;
2698
2699 /*
2700 * Workaround for Silicon errata. Use clear-by-write instead
2701 * of clear-by-read. Reading with EICS will return the
2702 * interrupt causes without clearing, which later be done
2703 * with the write to EICR.
2704 */
2705 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2706
2707 /* The lower 16bits of the EICR register are for the queue interrupts
2708 * which should be masked here in order to not accidentally clear them if
2709 * the bits are high when ixgbe_msix_other is called. There is a race
2710 * condition otherwise which results in possible performance loss
2711 * especially if the ixgbe_msix_other interrupt is triggering
2712 * consistently (as it would when PPS is turned on for the X540 device)
2713 */
2714 eicr &= 0xFFFF0000;
2715
2716 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2717
2718 if (eicr & IXGBE_EICR_LSC)
2719 ixgbe_check_lsc(adapter);
2720
2721 if (eicr & IXGBE_EICR_MAILBOX)
2722 ixgbe_msg_task(adapter);
2723
2724 switch (hw->mac.type) {
2725 case ixgbe_mac_82599EB:
2726 case ixgbe_mac_X540:
2727 case ixgbe_mac_X550:
2728 case ixgbe_mac_X550EM_x:
2729 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2730 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2731 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2732 ixgbe_service_event_schedule(adapter);
2733 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2734 IXGBE_EICR_GPI_SDP0_X540);
2735 }
2736 if (eicr & IXGBE_EICR_ECC) {
2737 e_info(link, "Received ECC Err, initiating reset\n");
2738 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2739 ixgbe_service_event_schedule(adapter);
2740 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2741 }
2742 /* Handle Flow Director Full threshold interrupt */
2743 if (eicr & IXGBE_EICR_FLOW_DIR) {
2744 int reinit_count = 0;
2745 int i;
2746 for (i = 0; i < adapter->num_tx_queues; i++) {
2747 struct ixgbe_ring *ring = adapter->tx_ring[i];
2748 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2749 &ring->state))
2750 reinit_count++;
2751 }
2752 if (reinit_count) {
2753 /* no more flow director interrupts until after init */
2754 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2755 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2756 ixgbe_service_event_schedule(adapter);
2757 }
2758 }
2759 ixgbe_check_sfp_event(adapter, eicr);
2760 ixgbe_check_overtemp_event(adapter, eicr);
2761 break;
2762 default:
2763 break;
2764 }
2765
2766 ixgbe_check_fan_failure(adapter, eicr);
2767
2768 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2769 ixgbe_ptp_check_pps_event(adapter);
2770
2771 /* re-enable the original interrupt state, no lsc, no queues */
2772 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2773 ixgbe_irq_enable(adapter, false, false);
2774
2775 return IRQ_HANDLED;
2776 }
2777
2778 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2779 {
2780 struct ixgbe_q_vector *q_vector = data;
2781
2782 /* EIAM disabled interrupts (on this vector) for us */
2783
2784 if (q_vector->rx.ring || q_vector->tx.ring)
2785 napi_schedule_irqoff(&q_vector->napi);
2786
2787 return IRQ_HANDLED;
2788 }
2789
2790 /**
2791 * ixgbe_poll - NAPI Rx polling callback
2792 * @napi: structure for representing this polling device
2793 * @budget: how many packets driver is allowed to clean
2794 *
2795 * This function is used for legacy and MSI, NAPI mode
2796 **/
2797 int ixgbe_poll(struct napi_struct *napi, int budget)
2798 {
2799 struct ixgbe_q_vector *q_vector =
2800 container_of(napi, struct ixgbe_q_vector, napi);
2801 struct ixgbe_adapter *adapter = q_vector->adapter;
2802 struct ixgbe_ring *ring;
2803 int per_ring_budget, work_done = 0;
2804 bool clean_complete = true;
2805
2806 #ifdef CONFIG_IXGBE_DCA
2807 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2808 ixgbe_update_dca(q_vector);
2809 #endif
2810
2811 ixgbe_for_each_ring(ring, q_vector->tx) {
2812 if (!ixgbe_clean_tx_irq(q_vector, ring, budget))
2813 clean_complete = false;
2814 }
2815
2816 /* Exit if we are called by netpoll or busy polling is active */
2817 if ((budget <= 0) || !ixgbe_qv_lock_napi(q_vector))
2818 return budget;
2819
2820 /* attempt to distribute budget to each queue fairly, but don't allow
2821 * the budget to go below 1 because we'll exit polling */
2822 if (q_vector->rx.count > 1)
2823 per_ring_budget = max(budget/q_vector->rx.count, 1);
2824 else
2825 per_ring_budget = budget;
2826
2827 ixgbe_for_each_ring(ring, q_vector->rx) {
2828 int cleaned = ixgbe_clean_rx_irq(q_vector, ring,
2829 per_ring_budget);
2830
2831 work_done += cleaned;
2832 if (cleaned >= per_ring_budget)
2833 clean_complete = false;
2834 }
2835
2836 ixgbe_qv_unlock_napi(q_vector);
2837 /* If all work not completed, return budget and keep polling */
2838 if (!clean_complete)
2839 return budget;
2840
2841 /* all work done, exit the polling mode */
2842 napi_complete_done(napi, work_done);
2843 if (adapter->rx_itr_setting & 1)
2844 ixgbe_set_itr(q_vector);
2845 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2846 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2847
2848 return 0;
2849 }
2850
2851 /**
2852 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2853 * @adapter: board private structure
2854 *
2855 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2856 * interrupts from the kernel.
2857 **/
2858 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2859 {
2860 struct net_device *netdev = adapter->netdev;
2861 int vector, err;
2862 int ri = 0, ti = 0;
2863
2864 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2865 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2866 struct msix_entry *entry = &adapter->msix_entries[vector];
2867
2868 if (q_vector->tx.ring && q_vector->rx.ring) {
2869 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2870 "%s-%s-%d", netdev->name, "TxRx", ri++);
2871 ti++;
2872 } else if (q_vector->rx.ring) {
2873 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2874 "%s-%s-%d", netdev->name, "rx", ri++);
2875 } else if (q_vector->tx.ring) {
2876 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2877 "%s-%s-%d", netdev->name, "tx", ti++);
2878 } else {
2879 /* skip this unused q_vector */
2880 continue;
2881 }
2882 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2883 q_vector->name, q_vector);
2884 if (err) {
2885 e_err(probe, "request_irq failed for MSIX interrupt "
2886 "Error: %d\n", err);
2887 goto free_queue_irqs;
2888 }
2889 /* If Flow Director is enabled, set interrupt affinity */
2890 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2891 /* assign the mask for this irq */
2892 irq_set_affinity_hint(entry->vector,
2893 &q_vector->affinity_mask);
2894 }
2895 }
2896
2897 err = request_irq(adapter->msix_entries[vector].vector,
2898 ixgbe_msix_other, 0, netdev->name, adapter);
2899 if (err) {
2900 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2901 goto free_queue_irqs;
2902 }
2903
2904 return 0;
2905
2906 free_queue_irqs:
2907 while (vector) {
2908 vector--;
2909 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2910 NULL);
2911 free_irq(adapter->msix_entries[vector].vector,
2912 adapter->q_vector[vector]);
2913 }
2914 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2915 pci_disable_msix(adapter->pdev);
2916 kfree(adapter->msix_entries);
2917 adapter->msix_entries = NULL;
2918 return err;
2919 }
2920
2921 /**
2922 * ixgbe_intr - legacy mode Interrupt Handler
2923 * @irq: interrupt number
2924 * @data: pointer to a network interface device structure
2925 **/
2926 static irqreturn_t ixgbe_intr(int irq, void *data)
2927 {
2928 struct ixgbe_adapter *adapter = data;
2929 struct ixgbe_hw *hw = &adapter->hw;
2930 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2931 u32 eicr;
2932
2933 /*
2934 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2935 * before the read of EICR.
2936 */
2937 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2938
2939 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2940 * therefore no explicit interrupt disable is necessary */
2941 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2942 if (!eicr) {
2943 /*
2944 * shared interrupt alert!
2945 * make sure interrupts are enabled because the read will
2946 * have disabled interrupts due to EIAM
2947 * finish the workaround of silicon errata on 82598. Unmask
2948 * the interrupt that we masked before the EICR read.
2949 */
2950 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2951 ixgbe_irq_enable(adapter, true, true);
2952 return IRQ_NONE; /* Not our interrupt */
2953 }
2954
2955 if (eicr & IXGBE_EICR_LSC)
2956 ixgbe_check_lsc(adapter);
2957
2958 switch (hw->mac.type) {
2959 case ixgbe_mac_82599EB:
2960 ixgbe_check_sfp_event(adapter, eicr);
2961 /* Fall through */
2962 case ixgbe_mac_X540:
2963 case ixgbe_mac_X550:
2964 case ixgbe_mac_X550EM_x:
2965 if (eicr & IXGBE_EICR_ECC) {
2966 e_info(link, "Received ECC Err, initiating reset\n");
2967 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2968 ixgbe_service_event_schedule(adapter);
2969 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2970 }
2971 ixgbe_check_overtemp_event(adapter, eicr);
2972 break;
2973 default:
2974 break;
2975 }
2976
2977 ixgbe_check_fan_failure(adapter, eicr);
2978 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2979 ixgbe_ptp_check_pps_event(adapter);
2980
2981 /* would disable interrupts here but EIAM disabled it */
2982 napi_schedule_irqoff(&q_vector->napi);
2983
2984 /*
2985 * re-enable link(maybe) and non-queue interrupts, no flush.
2986 * ixgbe_poll will re-enable the queue interrupts
2987 */
2988 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2989 ixgbe_irq_enable(adapter, false, false);
2990
2991 return IRQ_HANDLED;
2992 }
2993
2994 /**
2995 * ixgbe_request_irq - initialize interrupts
2996 * @adapter: board private structure
2997 *
2998 * Attempts to configure interrupts using the best available
2999 * capabilities of the hardware and kernel.
3000 **/
3001 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
3002 {
3003 struct net_device *netdev = adapter->netdev;
3004 int err;
3005
3006 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3007 err = ixgbe_request_msix_irqs(adapter);
3008 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
3009 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
3010 netdev->name, adapter);
3011 else
3012 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
3013 netdev->name, adapter);
3014
3015 if (err)
3016 e_err(probe, "request_irq failed, Error %d\n", err);
3017
3018 return err;
3019 }
3020
3021 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
3022 {
3023 int vector;
3024
3025 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3026 free_irq(adapter->pdev->irq, adapter);
3027 return;
3028 }
3029
3030 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3031 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3032 struct msix_entry *entry = &adapter->msix_entries[vector];
3033
3034 /* free only the irqs that were actually requested */
3035 if (!q_vector->rx.ring && !q_vector->tx.ring)
3036 continue;
3037
3038 /* clear the affinity_mask in the IRQ descriptor */
3039 irq_set_affinity_hint(entry->vector, NULL);
3040
3041 free_irq(entry->vector, q_vector);
3042 }
3043
3044 free_irq(adapter->msix_entries[vector++].vector, adapter);
3045 }
3046
3047 /**
3048 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3049 * @adapter: board private structure
3050 **/
3051 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3052 {
3053 switch (adapter->hw.mac.type) {
3054 case ixgbe_mac_82598EB:
3055 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
3056 break;
3057 case ixgbe_mac_82599EB:
3058 case ixgbe_mac_X540:
3059 case ixgbe_mac_X550:
3060 case ixgbe_mac_X550EM_x:
3061 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3062 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
3063 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
3064 break;
3065 default:
3066 break;
3067 }
3068 IXGBE_WRITE_FLUSH(&adapter->hw);
3069 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3070 int vector;
3071
3072 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3073 synchronize_irq(adapter->msix_entries[vector].vector);
3074
3075 synchronize_irq(adapter->msix_entries[vector++].vector);
3076 } else {
3077 synchronize_irq(adapter->pdev->irq);
3078 }
3079 }
3080
3081 /**
3082 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3083 *
3084 **/
3085 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3086 {
3087 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3088
3089 ixgbe_write_eitr(q_vector);
3090
3091 ixgbe_set_ivar(adapter, 0, 0, 0);
3092 ixgbe_set_ivar(adapter, 1, 0, 0);
3093
3094 e_info(hw, "Legacy interrupt IVAR setup done\n");
3095 }
3096
3097 /**
3098 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3099 * @adapter: board private structure
3100 * @ring: structure containing ring specific data
3101 *
3102 * Configure the Tx descriptor ring after a reset.
3103 **/
3104 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3105 struct ixgbe_ring *ring)
3106 {
3107 struct ixgbe_hw *hw = &adapter->hw;
3108 u64 tdba = ring->dma;
3109 int wait_loop = 10;
3110 u32 txdctl = IXGBE_TXDCTL_ENABLE;
3111 u8 reg_idx = ring->reg_idx;
3112
3113 /* disable queue to avoid issues while updating state */
3114 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
3115 IXGBE_WRITE_FLUSH(hw);
3116
3117 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
3118 (tdba & DMA_BIT_MASK(32)));
3119 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3120 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3121 ring->count * sizeof(union ixgbe_adv_tx_desc));
3122 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3123 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
3124 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
3125
3126 /*
3127 * set WTHRESH to encourage burst writeback, it should not be set
3128 * higher than 1 when:
3129 * - ITR is 0 as it could cause false TX hangs
3130 * - ITR is set to > 100k int/sec and BQL is enabled
3131 *
3132 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3133 * to or less than the number of on chip descriptors, which is
3134 * currently 40.
3135 */
3136 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3137 txdctl |= (1 << 16); /* WTHRESH = 1 */
3138 else
3139 txdctl |= (8 << 16); /* WTHRESH = 8 */
3140
3141 /*
3142 * Setting PTHRESH to 32 both improves performance
3143 * and avoids a TX hang with DFP enabled
3144 */
3145 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3146 32; /* PTHRESH = 32 */
3147
3148 /* reinitialize flowdirector state */
3149 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3150 ring->atr_sample_rate = adapter->atr_sample_rate;
3151 ring->atr_count = 0;
3152 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3153 } else {
3154 ring->atr_sample_rate = 0;
3155 }
3156
3157 /* initialize XPS */
3158 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3159 struct ixgbe_q_vector *q_vector = ring->q_vector;
3160
3161 if (q_vector)
3162 netif_set_xps_queue(ring->netdev,
3163 &q_vector->affinity_mask,
3164 ring->queue_index);
3165 }
3166
3167 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3168
3169 /* enable queue */
3170 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3171
3172 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3173 if (hw->mac.type == ixgbe_mac_82598EB &&
3174 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3175 return;
3176
3177 /* poll to verify queue is enabled */
3178 do {
3179 usleep_range(1000, 2000);
3180 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3181 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3182 if (!wait_loop)
3183 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
3184 }
3185
3186 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3187 {
3188 struct ixgbe_hw *hw = &adapter->hw;
3189 u32 rttdcs, mtqc;
3190 u8 tcs = netdev_get_num_tc(adapter->netdev);
3191
3192 if (hw->mac.type == ixgbe_mac_82598EB)
3193 return;
3194
3195 /* disable the arbiter while setting MTQC */
3196 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3197 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3198 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3199
3200 /* set transmit pool layout */
3201 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3202 mtqc = IXGBE_MTQC_VT_ENA;
3203 if (tcs > 4)
3204 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3205 else if (tcs > 1)
3206 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3207 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3208 mtqc |= IXGBE_MTQC_32VF;
3209 else
3210 mtqc |= IXGBE_MTQC_64VF;
3211 } else {
3212 if (tcs > 4)
3213 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3214 else if (tcs > 1)
3215 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3216 else
3217 mtqc = IXGBE_MTQC_64Q_1PB;
3218 }
3219
3220 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3221
3222 /* Enable Security TX Buffer IFG for multiple pb */
3223 if (tcs) {
3224 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3225 sectx |= IXGBE_SECTX_DCB;
3226 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3227 }
3228
3229 /* re-enable the arbiter */
3230 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3231 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3232 }
3233
3234 /**
3235 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3236 * @adapter: board private structure
3237 *
3238 * Configure the Tx unit of the MAC after a reset.
3239 **/
3240 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3241 {
3242 struct ixgbe_hw *hw = &adapter->hw;
3243 u32 dmatxctl;
3244 u32 i;
3245
3246 ixgbe_setup_mtqc(adapter);
3247
3248 if (hw->mac.type != ixgbe_mac_82598EB) {
3249 /* DMATXCTL.EN must be before Tx queues are enabled */
3250 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3251 dmatxctl |= IXGBE_DMATXCTL_TE;
3252 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3253 }
3254
3255 /* Setup the HW Tx Head and Tail descriptor pointers */
3256 for (i = 0; i < adapter->num_tx_queues; i++)
3257 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3258 }
3259
3260 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3261 struct ixgbe_ring *ring)
3262 {
3263 struct ixgbe_hw *hw = &adapter->hw;
3264 u8 reg_idx = ring->reg_idx;
3265 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3266
3267 srrctl |= IXGBE_SRRCTL_DROP_EN;
3268
3269 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3270 }
3271
3272 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3273 struct ixgbe_ring *ring)
3274 {
3275 struct ixgbe_hw *hw = &adapter->hw;
3276 u8 reg_idx = ring->reg_idx;
3277 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3278
3279 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3280
3281 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3282 }
3283
3284 #ifdef CONFIG_IXGBE_DCB
3285 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3286 #else
3287 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3288 #endif
3289 {
3290 int i;
3291 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3292
3293 if (adapter->ixgbe_ieee_pfc)
3294 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3295
3296 /*
3297 * We should set the drop enable bit if:
3298 * SR-IOV is enabled
3299 * or
3300 * Number of Rx queues > 1 and flow control is disabled
3301 *
3302 * This allows us to avoid head of line blocking for security
3303 * and performance reasons.
3304 */
3305 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3306 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3307 for (i = 0; i < adapter->num_rx_queues; i++)
3308 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3309 } else {
3310 for (i = 0; i < adapter->num_rx_queues; i++)
3311 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3312 }
3313 }
3314
3315 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3316
3317 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3318 struct ixgbe_ring *rx_ring)
3319 {
3320 struct ixgbe_hw *hw = &adapter->hw;
3321 u32 srrctl;
3322 u8 reg_idx = rx_ring->reg_idx;
3323
3324 if (hw->mac.type == ixgbe_mac_82598EB) {
3325 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3326
3327 /*
3328 * if VMDq is not active we must program one srrctl register
3329 * per RSS queue since we have enabled RDRXCTL.MVMEN
3330 */
3331 reg_idx &= mask;
3332 }
3333
3334 /* configure header buffer length, needed for RSC */
3335 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3336
3337 /* configure the packet buffer length */
3338 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3339
3340 /* configure descriptor type */
3341 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3342
3343 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3344 }
3345
3346 /**
3347 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
3348 * @adapter: device handle
3349 *
3350 * - 82598/82599/X540: 128
3351 * - X550(non-SRIOV mode): 512
3352 * - X550(SRIOV mode): 64
3353 */
3354 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
3355 {
3356 if (adapter->hw.mac.type < ixgbe_mac_X550)
3357 return 128;
3358 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3359 return 64;
3360 else
3361 return 512;
3362 }
3363
3364 /**
3365 * ixgbe_store_reta - Write the RETA table to HW
3366 * @adapter: device handle
3367 *
3368 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3369 */
3370 void ixgbe_store_reta(struct ixgbe_adapter *adapter)
3371 {
3372 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3373 struct ixgbe_hw *hw = &adapter->hw;
3374 u32 reta = 0;
3375 u32 indices_multi;
3376 u8 *indir_tbl = adapter->rss_indir_tbl;
3377
3378 /* Fill out the redirection table as follows:
3379 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3380 * indices.
3381 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3382 * - X550: 8 bit wide entries containing 6 bit RSS index
3383 */
3384 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3385 indices_multi = 0x11;
3386 else
3387 indices_multi = 0x1;
3388
3389 /* Write redirection table to HW */
3390 for (i = 0; i < reta_entries; i++) {
3391 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
3392 if ((i & 3) == 3) {
3393 if (i < 128)
3394 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3395 else
3396 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3397 reta);
3398 reta = 0;
3399 }
3400 }
3401 }
3402
3403 /**
3404 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
3405 * @adapter: device handle
3406 *
3407 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3408 */
3409 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
3410 {
3411 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3412 struct ixgbe_hw *hw = &adapter->hw;
3413 u32 vfreta = 0;
3414 unsigned int pf_pool = adapter->num_vfs;
3415
3416 /* Write redirection table to HW */
3417 for (i = 0; i < reta_entries; i++) {
3418 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3419 if ((i & 3) == 3) {
3420 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3421 vfreta);
3422 vfreta = 0;
3423 }
3424 }
3425 }
3426
3427 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3428 {
3429 struct ixgbe_hw *hw = &adapter->hw;
3430 u32 i, j;
3431 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3432 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3433
3434 /* Program table for at least 2 queues w/ SR-IOV so that VFs can
3435 * make full use of any rings they may have. We will use the
3436 * PSRTYPE register to control how many rings we use within the PF.
3437 */
3438 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3439 rss_i = 2;
3440
3441 /* Fill out hash function seeds */
3442 for (i = 0; i < 10; i++)
3443 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3444
3445 /* Fill out redirection table */
3446 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3447
3448 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3449 if (j == rss_i)
3450 j = 0;
3451
3452 adapter->rss_indir_tbl[i] = j;
3453 }
3454
3455 ixgbe_store_reta(adapter);
3456 }
3457
3458 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3459 {
3460 struct ixgbe_hw *hw = &adapter->hw;
3461 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3462 unsigned int pf_pool = adapter->num_vfs;
3463 int i, j;
3464
3465 /* Fill out hash function seeds */
3466 for (i = 0; i < 10; i++)
3467 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3468 adapter->rss_key[i]);
3469
3470 /* Fill out the redirection table */
3471 for (i = 0, j = 0; i < 64; i++, j++) {
3472 if (j == rss_i)
3473 j = 0;
3474
3475 adapter->rss_indir_tbl[i] = j;
3476 }
3477
3478 ixgbe_store_vfreta(adapter);
3479 }
3480
3481 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3482 {
3483 struct ixgbe_hw *hw = &adapter->hw;
3484 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
3485 u32 rxcsum;
3486
3487 /* Disable indicating checksum in descriptor, enables RSS hash */
3488 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3489 rxcsum |= IXGBE_RXCSUM_PCSD;
3490 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3491
3492 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3493 if (adapter->ring_feature[RING_F_RSS].mask)
3494 mrqc = IXGBE_MRQC_RSSEN;
3495 } else {
3496 u8 tcs = netdev_get_num_tc(adapter->netdev);
3497
3498 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3499 if (tcs > 4)
3500 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3501 else if (tcs > 1)
3502 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3503 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3504 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3505 else
3506 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3507 } else {
3508 if (tcs > 4)
3509 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3510 else if (tcs > 1)
3511 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3512 else
3513 mrqc = IXGBE_MRQC_RSSEN;
3514 }
3515 }
3516
3517 /* Perform hash on these packet types */
3518 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3519 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3520 IXGBE_MRQC_RSS_FIELD_IPV6 |
3521 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3522
3523 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3524 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3525 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3526 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3527
3528 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
3529 if ((hw->mac.type >= ixgbe_mac_X550) &&
3530 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3531 unsigned int pf_pool = adapter->num_vfs;
3532
3533 /* Enable VF RSS mode */
3534 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3535 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3536
3537 /* Setup RSS through the VF registers */
3538 ixgbe_setup_vfreta(adapter);
3539 vfmrqc = IXGBE_MRQC_RSSEN;
3540 vfmrqc |= rss_field;
3541 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3542 } else {
3543 ixgbe_setup_reta(adapter);
3544 mrqc |= rss_field;
3545 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3546 }
3547 }
3548
3549 /**
3550 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3551 * @adapter: address of board private structure
3552 * @index: index of ring to set
3553 **/
3554 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3555 struct ixgbe_ring *ring)
3556 {
3557 struct ixgbe_hw *hw = &adapter->hw;
3558 u32 rscctrl;
3559 u8 reg_idx = ring->reg_idx;
3560
3561 if (!ring_is_rsc_enabled(ring))
3562 return;
3563
3564 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3565 rscctrl |= IXGBE_RSCCTL_RSCEN;
3566 /*
3567 * we must limit the number of descriptors so that the
3568 * total size of max desc * buf_len is not greater
3569 * than 65536
3570 */
3571 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3572 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3573 }
3574
3575 #define IXGBE_MAX_RX_DESC_POLL 10
3576 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3577 struct ixgbe_ring *ring)
3578 {
3579 struct ixgbe_hw *hw = &adapter->hw;
3580 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3581 u32 rxdctl;
3582 u8 reg_idx = ring->reg_idx;
3583
3584 if (ixgbe_removed(hw->hw_addr))
3585 return;
3586 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3587 if (hw->mac.type == ixgbe_mac_82598EB &&
3588 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3589 return;
3590
3591 do {
3592 usleep_range(1000, 2000);
3593 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3594 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3595
3596 if (!wait_loop) {
3597 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3598 "the polling period\n", reg_idx);
3599 }
3600 }
3601
3602 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3603 struct ixgbe_ring *ring)
3604 {
3605 struct ixgbe_hw *hw = &adapter->hw;
3606 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3607 u32 rxdctl;
3608 u8 reg_idx = ring->reg_idx;
3609
3610 if (ixgbe_removed(hw->hw_addr))
3611 return;
3612 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3613 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3614
3615 /* write value back with RXDCTL.ENABLE bit cleared */
3616 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3617
3618 if (hw->mac.type == ixgbe_mac_82598EB &&
3619 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3620 return;
3621
3622 /* the hardware may take up to 100us to really disable the rx queue */
3623 do {
3624 udelay(10);
3625 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3626 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3627
3628 if (!wait_loop) {
3629 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3630 "the polling period\n", reg_idx);
3631 }
3632 }
3633
3634 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3635 struct ixgbe_ring *ring)
3636 {
3637 struct ixgbe_hw *hw = &adapter->hw;
3638 u64 rdba = ring->dma;
3639 u32 rxdctl;
3640 u8 reg_idx = ring->reg_idx;
3641
3642 /* disable queue to avoid issues while updating state */
3643 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3644 ixgbe_disable_rx_queue(adapter, ring);
3645
3646 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3647 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3648 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3649 ring->count * sizeof(union ixgbe_adv_rx_desc));
3650 /* Force flushing of IXGBE_RDLEN to prevent MDD */
3651 IXGBE_WRITE_FLUSH(hw);
3652
3653 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3654 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3655 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
3656
3657 ixgbe_configure_srrctl(adapter, ring);
3658 ixgbe_configure_rscctl(adapter, ring);
3659
3660 if (hw->mac.type == ixgbe_mac_82598EB) {
3661 /*
3662 * enable cache line friendly hardware writes:
3663 * PTHRESH=32 descriptors (half the internal cache),
3664 * this also removes ugly rx_no_buffer_count increment
3665 * HTHRESH=4 descriptors (to minimize latency on fetch)
3666 * WTHRESH=8 burst writeback up to two cache lines
3667 */
3668 rxdctl &= ~0x3FFFFF;
3669 rxdctl |= 0x080420;
3670 }
3671
3672 /* enable receive descriptor ring */
3673 rxdctl |= IXGBE_RXDCTL_ENABLE;
3674 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3675
3676 ixgbe_rx_desc_queue_enable(adapter, ring);
3677 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3678 }
3679
3680 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3681 {
3682 struct ixgbe_hw *hw = &adapter->hw;
3683 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3684 u16 pool;
3685
3686 /* PSRTYPE must be initialized in non 82598 adapters */
3687 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3688 IXGBE_PSRTYPE_UDPHDR |
3689 IXGBE_PSRTYPE_IPV4HDR |
3690 IXGBE_PSRTYPE_L2HDR |
3691 IXGBE_PSRTYPE_IPV6HDR;
3692
3693 if (hw->mac.type == ixgbe_mac_82598EB)
3694 return;
3695
3696 if (rss_i > 3)
3697 psrtype |= 2 << 29;
3698 else if (rss_i > 1)
3699 psrtype |= 1 << 29;
3700
3701 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3702 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
3703 }
3704
3705 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3706 {
3707 struct ixgbe_hw *hw = &adapter->hw;
3708 u32 reg_offset, vf_shift;
3709 u32 gcr_ext, vmdctl;
3710 int i;
3711
3712 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3713 return;
3714
3715 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3716 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3717 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3718 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3719 vmdctl |= IXGBE_VT_CTL_REPLEN;
3720 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3721
3722 vf_shift = VMDQ_P(0) % 32;
3723 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3724
3725 /* Enable only the PF's pool for Tx/Rx */
3726 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3727 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3728 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3729 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3730 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
3731 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3732
3733 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3734 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3735
3736 /* clear VLAN promisc flag so VFTA will be updated if necessary */
3737 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
3738
3739 /*
3740 * Set up VF register offsets for selected VT Mode,
3741 * i.e. 32 or 64 VFs for SR-IOV
3742 */
3743 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3744 case IXGBE_82599_VMDQ_8Q_MASK:
3745 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3746 break;
3747 case IXGBE_82599_VMDQ_4Q_MASK:
3748 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3749 break;
3750 default:
3751 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3752 break;
3753 }
3754
3755 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3756
3757
3758 /* Enable MAC Anti-Spoofing */
3759 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3760 adapter->num_vfs);
3761
3762 /* Ensure LLDP and FC is set for Ethertype Antispoofing if we will be
3763 * calling set_ethertype_anti_spoofing for each VF in loop below
3764 */
3765 if (hw->mac.ops.set_ethertype_anti_spoofing) {
3766 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
3767 (IXGBE_ETQF_FILTER_EN |
3768 IXGBE_ETQF_TX_ANTISPOOF |
3769 IXGBE_ETH_P_LLDP));
3770
3771 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FC),
3772 (IXGBE_ETQF_FILTER_EN |
3773 IXGBE_ETQF_TX_ANTISPOOF |
3774 ETH_P_PAUSE));
3775 }
3776
3777 /* For VFs that have spoof checking turned off */
3778 for (i = 0; i < adapter->num_vfs; i++) {
3779 if (!adapter->vfinfo[i].spoofchk_enabled)
3780 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3781
3782 /* enable ethertype anti spoofing if hw supports it */
3783 if (hw->mac.ops.set_ethertype_anti_spoofing)
3784 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
3785
3786 /* Enable/Disable RSS query feature */
3787 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
3788 adapter->vfinfo[i].rss_query_enabled);
3789 }
3790 }
3791
3792 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3793 {
3794 struct ixgbe_hw *hw = &adapter->hw;
3795 struct net_device *netdev = adapter->netdev;
3796 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3797 struct ixgbe_ring *rx_ring;
3798 int i;
3799 u32 mhadd, hlreg0;
3800
3801 #ifdef IXGBE_FCOE
3802 /* adjust max frame to be able to do baby jumbo for FCoE */
3803 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3804 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3805 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3806
3807 #endif /* IXGBE_FCOE */
3808
3809 /* adjust max frame to be at least the size of a standard frame */
3810 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3811 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3812
3813 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3814 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3815 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3816 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3817
3818 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3819 }
3820
3821 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3822 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3823 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3824 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3825
3826 /*
3827 * Setup the HW Rx Head and Tail Descriptor Pointers and
3828 * the Base and Length of the Rx Descriptor Ring
3829 */
3830 for (i = 0; i < adapter->num_rx_queues; i++) {
3831 rx_ring = adapter->rx_ring[i];
3832 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3833 set_ring_rsc_enabled(rx_ring);
3834 else
3835 clear_ring_rsc_enabled(rx_ring);
3836 }
3837 }
3838
3839 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3840 {
3841 struct ixgbe_hw *hw = &adapter->hw;
3842 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3843
3844 switch (hw->mac.type) {
3845 case ixgbe_mac_82598EB:
3846 /*
3847 * For VMDq support of different descriptor types or
3848 * buffer sizes through the use of multiple SRRCTL
3849 * registers, RDRXCTL.MVMEN must be set to 1
3850 *
3851 * also, the manual doesn't mention it clearly but DCA hints
3852 * will only use queue 0's tags unless this bit is set. Side
3853 * effects of setting this bit are only that SRRCTL must be
3854 * fully programmed [0..15]
3855 */
3856 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3857 break;
3858 case ixgbe_mac_X550:
3859 case ixgbe_mac_X550EM_x:
3860 if (adapter->num_vfs)
3861 rdrxctl |= IXGBE_RDRXCTL_PSP;
3862 /* fall through for older HW */
3863 case ixgbe_mac_82599EB:
3864 case ixgbe_mac_X540:
3865 /* Disable RSC for ACK packets */
3866 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3867 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3868 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3869 /* hardware requires some bits to be set by default */
3870 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3871 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3872 break;
3873 default:
3874 /* We should do nothing since we don't know this hardware */
3875 return;
3876 }
3877
3878 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3879 }
3880
3881 /**
3882 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3883 * @adapter: board private structure
3884 *
3885 * Configure the Rx unit of the MAC after a reset.
3886 **/
3887 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3888 {
3889 struct ixgbe_hw *hw = &adapter->hw;
3890 int i;
3891 u32 rxctrl, rfctl;
3892
3893 /* disable receives while setting up the descriptors */
3894 hw->mac.ops.disable_rx(hw);
3895
3896 ixgbe_setup_psrtype(adapter);
3897 ixgbe_setup_rdrxctl(adapter);
3898
3899 /* RSC Setup */
3900 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3901 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3902 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3903 rfctl |= IXGBE_RFCTL_RSC_DIS;
3904 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3905
3906 /* Program registers for the distribution of queues */
3907 ixgbe_setup_mrqc(adapter);
3908
3909 /* set_rx_buffer_len must be called before ring initialization */
3910 ixgbe_set_rx_buffer_len(adapter);
3911
3912 /*
3913 * Setup the HW Rx Head and Tail Descriptor Pointers and
3914 * the Base and Length of the Rx Descriptor Ring
3915 */
3916 for (i = 0; i < adapter->num_rx_queues; i++)
3917 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3918
3919 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3920 /* disable drop enable for 82598 parts */
3921 if (hw->mac.type == ixgbe_mac_82598EB)
3922 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3923
3924 /* enable all receives */
3925 rxctrl |= IXGBE_RXCTRL_RXEN;
3926 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3927 }
3928
3929 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3930 __be16 proto, u16 vid)
3931 {
3932 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3933 struct ixgbe_hw *hw = &adapter->hw;
3934
3935 /* add VID to filter table */
3936 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
3937 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid);
3938
3939 set_bit(vid, adapter->active_vlans);
3940
3941 return 0;
3942 }
3943
3944 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan)
3945 {
3946 u32 vlvf;
3947 int idx;
3948
3949 /* short cut the special case */
3950 if (vlan == 0)
3951 return 0;
3952
3953 /* Search for the vlan id in the VLVF entries */
3954 for (idx = IXGBE_VLVF_ENTRIES; --idx;) {
3955 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx));
3956 if ((vlvf & VLAN_VID_MASK) == vlan)
3957 break;
3958 }
3959
3960 return idx;
3961 }
3962
3963 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid)
3964 {
3965 struct ixgbe_hw *hw = &adapter->hw;
3966 u32 bits, word;
3967 int idx;
3968
3969 idx = ixgbe_find_vlvf_entry(hw, vid);
3970 if (!idx)
3971 return;
3972
3973 /* See if any other pools are set for this VLAN filter
3974 * entry other than the PF.
3975 */
3976 word = idx * 2 + (VMDQ_P(0) / 32);
3977 bits = ~(1 << (VMDQ_P(0)) % 32);
3978 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
3979
3980 /* Disable the filter so this falls into the default pool. */
3981 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) {
3982 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
3983 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0);
3984 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0);
3985 }
3986 }
3987
3988 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3989 __be16 proto, u16 vid)
3990 {
3991 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3992 struct ixgbe_hw *hw = &adapter->hw;
3993
3994 /* remove VID from filter table */
3995 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
3996 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true);
3997
3998 clear_bit(vid, adapter->active_vlans);
3999
4000 return 0;
4001 }
4002
4003 /**
4004 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
4005 * @adapter: driver data
4006 */
4007 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
4008 {
4009 struct ixgbe_hw *hw = &adapter->hw;
4010 u32 vlnctrl;
4011 int i, j;
4012
4013 switch (hw->mac.type) {
4014 case ixgbe_mac_82598EB:
4015 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4016 vlnctrl &= ~IXGBE_VLNCTRL_VME;
4017 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4018 break;
4019 case ixgbe_mac_82599EB:
4020 case ixgbe_mac_X540:
4021 case ixgbe_mac_X550:
4022 case ixgbe_mac_X550EM_x:
4023 for (i = 0; i < adapter->num_rx_queues; i++) {
4024 struct ixgbe_ring *ring = adapter->rx_ring[i];
4025
4026 if (ring->l2_accel_priv)
4027 continue;
4028 j = ring->reg_idx;
4029 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4030 vlnctrl &= ~IXGBE_RXDCTL_VME;
4031 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4032 }
4033 break;
4034 default:
4035 break;
4036 }
4037 }
4038
4039 /**
4040 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
4041 * @adapter: driver data
4042 */
4043 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
4044 {
4045 struct ixgbe_hw *hw = &adapter->hw;
4046 u32 vlnctrl;
4047 int i, j;
4048
4049 switch (hw->mac.type) {
4050 case ixgbe_mac_82598EB:
4051 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4052 vlnctrl |= IXGBE_VLNCTRL_VME;
4053 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4054 break;
4055 case ixgbe_mac_82599EB:
4056 case ixgbe_mac_X540:
4057 case ixgbe_mac_X550:
4058 case ixgbe_mac_X550EM_x:
4059 for (i = 0; i < adapter->num_rx_queues; i++) {
4060 struct ixgbe_ring *ring = adapter->rx_ring[i];
4061
4062 if (ring->l2_accel_priv)
4063 continue;
4064 j = ring->reg_idx;
4065 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4066 vlnctrl |= IXGBE_RXDCTL_VME;
4067 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4068 }
4069 break;
4070 default:
4071 break;
4072 }
4073 }
4074
4075 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter)
4076 {
4077 struct ixgbe_hw *hw = &adapter->hw;
4078 u32 vlnctrl, i;
4079
4080 switch (hw->mac.type) {
4081 case ixgbe_mac_82599EB:
4082 case ixgbe_mac_X540:
4083 case ixgbe_mac_X550:
4084 case ixgbe_mac_X550EM_x:
4085 default:
4086 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)
4087 break;
4088 /* fall through */
4089 case ixgbe_mac_82598EB:
4090 /* legacy case, we can just disable VLAN filtering */
4091 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4092 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4093 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4094 return;
4095 }
4096
4097 /* We are already in VLAN promisc, nothing to do */
4098 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
4099 return;
4100
4101 /* Set flag so we don't redo unnecessary work */
4102 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC;
4103
4104 /* Add PF to all active pools */
4105 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4106 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);
4107 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);
4108
4109 vlvfb |= 1 << (VMDQ_P(0) % 32);
4110 IXGBE_WRITE_REG(hw, reg_offset, vlvfb);
4111 }
4112
4113 /* Set all bits in the VLAN filter table array */
4114 for (i = hw->mac.vft_size; i--;)
4115 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U);
4116 }
4117
4118 #define VFTA_BLOCK_SIZE 8
4119 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4120 {
4121 struct ixgbe_hw *hw = &adapter->hw;
4122 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4123 u32 vid_start = vfta_offset * 32;
4124 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4125 u32 i, vid, word, bits;
4126
4127 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4128 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
4129
4130 /* pull VLAN ID from VLVF */
4131 vid = vlvf & VLAN_VID_MASK;
4132
4133 /* only concern outselves with a certain range */
4134 if (vid < vid_start || vid >= vid_end)
4135 continue;
4136
4137 if (vlvf) {
4138 /* record VLAN ID in VFTA */
4139 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32);
4140
4141 /* if PF is part of this then continue */
4142 if (test_bit(vid, adapter->active_vlans))
4143 continue;
4144 }
4145
4146 /* remove PF from the pool */
4147 word = i * 2 + VMDQ_P(0) / 32;
4148 bits = ~(1 << (VMDQ_P(0) % 32));
4149 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4150 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits);
4151 }
4152
4153 /* extract values from active_vlans and write back to VFTA */
4154 for (i = VFTA_BLOCK_SIZE; i--;) {
4155 vid = (vfta_offset + i) * 32;
4156 word = vid / BITS_PER_LONG;
4157 bits = vid % BITS_PER_LONG;
4158
4159 vfta[i] |= adapter->active_vlans[word] >> bits;
4160
4161 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]);
4162 }
4163 }
4164
4165 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter)
4166 {
4167 struct ixgbe_hw *hw = &adapter->hw;
4168 u32 vlnctrl, i;
4169
4170 switch (hw->mac.type) {
4171 case ixgbe_mac_82599EB:
4172 case ixgbe_mac_X540:
4173 case ixgbe_mac_X550:
4174 case ixgbe_mac_X550EM_x:
4175 default:
4176 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)
4177 break;
4178 /* fall through */
4179 case ixgbe_mac_82598EB:
4180 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4181 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
4182 vlnctrl |= IXGBE_VLNCTRL_VFE;
4183 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4184 return;
4185 }
4186
4187 /* We are not in VLAN promisc, nothing to do */
4188 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4189 return;
4190
4191 /* Set flag so we don't redo unnecessary work */
4192 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4193
4194 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE)
4195 ixgbe_scrub_vfta(adapter, i);
4196 }
4197
4198 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
4199 {
4200 u16 vid = 1;
4201
4202 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
4203
4204 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
4205 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
4206 }
4207
4208 /**
4209 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4210 * @netdev: network interface device structure
4211 *
4212 * Writes multicast address list to the MTA hash table.
4213 * Returns: -ENOMEM on failure
4214 * 0 on no addresses written
4215 * X on writing X addresses to MTA
4216 **/
4217 static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4218 {
4219 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4220 struct ixgbe_hw *hw = &adapter->hw;
4221
4222 if (!netif_running(netdev))
4223 return 0;
4224
4225 if (hw->mac.ops.update_mc_addr_list)
4226 hw->mac.ops.update_mc_addr_list(hw, netdev);
4227 else
4228 return -ENOMEM;
4229
4230 #ifdef CONFIG_PCI_IOV
4231 ixgbe_restore_vf_multicasts(adapter);
4232 #endif
4233
4234 return netdev_mc_count(netdev);
4235 }
4236
4237 #ifdef CONFIG_PCI_IOV
4238 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4239 {
4240 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4241 struct ixgbe_hw *hw = &adapter->hw;
4242 int i;
4243
4244 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4245 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4246
4247 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4248 hw->mac.ops.set_rar(hw, i,
4249 mac_table->addr,
4250 mac_table->pool,
4251 IXGBE_RAH_AV);
4252 else
4253 hw->mac.ops.clear_rar(hw, i);
4254 }
4255 }
4256
4257 #endif
4258 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4259 {
4260 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4261 struct ixgbe_hw *hw = &adapter->hw;
4262 int i;
4263
4264 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4265 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4266 continue;
4267
4268 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4269
4270 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4271 hw->mac.ops.set_rar(hw, i,
4272 mac_table->addr,
4273 mac_table->pool,
4274 IXGBE_RAH_AV);
4275 else
4276 hw->mac.ops.clear_rar(hw, i);
4277 }
4278 }
4279
4280 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4281 {
4282 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4283 struct ixgbe_hw *hw = &adapter->hw;
4284 int i;
4285
4286 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4287 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4288 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4289 }
4290
4291 ixgbe_sync_mac_table(adapter);
4292 }
4293
4294 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
4295 {
4296 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4297 struct ixgbe_hw *hw = &adapter->hw;
4298 int i, count = 0;
4299
4300 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4301 /* do not count default RAR as available */
4302 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4303 continue;
4304
4305 /* only count unused and addresses that belong to us */
4306 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4307 if (mac_table->pool != pool)
4308 continue;
4309 }
4310
4311 count++;
4312 }
4313
4314 return count;
4315 }
4316
4317 /* this function destroys the first RAR entry */
4318 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
4319 {
4320 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4321 struct ixgbe_hw *hw = &adapter->hw;
4322
4323 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4324 mac_table->pool = VMDQ_P(0);
4325
4326 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4327
4328 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
4329 IXGBE_RAH_AV);
4330 }
4331
4332 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4333 const u8 *addr, u16 pool)
4334 {
4335 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4336 struct ixgbe_hw *hw = &adapter->hw;
4337 int i;
4338
4339 if (is_zero_ether_addr(addr))
4340 return -EINVAL;
4341
4342 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4343 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4344 continue;
4345
4346 ether_addr_copy(mac_table->addr, addr);
4347 mac_table->pool = pool;
4348
4349 mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4350 IXGBE_MAC_STATE_IN_USE;
4351
4352 ixgbe_sync_mac_table(adapter);
4353
4354 return i;
4355 }
4356
4357 return -ENOMEM;
4358 }
4359
4360 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4361 const u8 *addr, u16 pool)
4362 {
4363 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4364 struct ixgbe_hw *hw = &adapter->hw;
4365 int i;
4366
4367 if (is_zero_ether_addr(addr))
4368 return -EINVAL;
4369
4370 /* search table for addr, if found clear IN_USE flag and sync */
4371 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4372 /* we can only delete an entry if it is in use */
4373 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4374 continue;
4375 /* we only care about entries that belong to the given pool */
4376 if (mac_table->pool != pool)
4377 continue;
4378 /* we only care about a specific MAC address */
4379 if (!ether_addr_equal(addr, mac_table->addr))
4380 continue;
4381
4382 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4383 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4384
4385 ixgbe_sync_mac_table(adapter);
4386
4387 return 0;
4388 }
4389
4390 return -ENOMEM;
4391 }
4392 /**
4393 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4394 * @netdev: network interface device structure
4395 *
4396 * Writes unicast address list to the RAR table.
4397 * Returns: -ENOMEM on failure/insufficient address space
4398 * 0 on no addresses written
4399 * X on writing X addresses to the RAR table
4400 **/
4401 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
4402 {
4403 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4404 int count = 0;
4405
4406 /* return ENOMEM indicating insufficient memory for addresses */
4407 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn))
4408 return -ENOMEM;
4409
4410 if (!netdev_uc_empty(netdev)) {
4411 struct netdev_hw_addr *ha;
4412 netdev_for_each_uc_addr(ha, netdev) {
4413 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4414 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
4415 count++;
4416 }
4417 }
4418 return count;
4419 }
4420
4421 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4422 {
4423 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4424 int ret;
4425
4426 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4427
4428 return min_t(int, ret, 0);
4429 }
4430
4431 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4432 {
4433 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4434
4435 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4436
4437 return 0;
4438 }
4439
4440 /**
4441 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
4442 * @netdev: network interface device structure
4443 *
4444 * The set_rx_method entry point is called whenever the unicast/multicast
4445 * address list or the network interface flags are updated. This routine is
4446 * responsible for configuring the hardware for proper unicast, multicast and
4447 * promiscuous mode.
4448 **/
4449 void ixgbe_set_rx_mode(struct net_device *netdev)
4450 {
4451 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4452 struct ixgbe_hw *hw = &adapter->hw;
4453 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
4454 netdev_features_t features = netdev->features;
4455 int count;
4456
4457 /* Check for Promiscuous and All Multicast modes */
4458 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4459
4460 /* set all bits that we expect to always be set */
4461 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
4462 fctrl |= IXGBE_FCTRL_BAM;
4463 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4464 fctrl |= IXGBE_FCTRL_PMCF;
4465
4466 /* clear the bits we are changing the status of */
4467 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4468 if (netdev->flags & IFF_PROMISC) {
4469 hw->addr_ctrl.user_set_promisc = true;
4470 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4471 vmolr |= IXGBE_VMOLR_MPE;
4472 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4473 } else {
4474 if (netdev->flags & IFF_ALLMULTI) {
4475 fctrl |= IXGBE_FCTRL_MPE;
4476 vmolr |= IXGBE_VMOLR_MPE;
4477 }
4478 hw->addr_ctrl.user_set_promisc = false;
4479 }
4480
4481 /*
4482 * Write addresses to available RAR registers, if there is not
4483 * sufficient space to store all the addresses then enable
4484 * unicast promiscuous mode
4485 */
4486 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
4487 fctrl |= IXGBE_FCTRL_UPE;
4488 vmolr |= IXGBE_VMOLR_ROPE;
4489 }
4490
4491 /* Write addresses to the MTA, if the attempt fails
4492 * then we should just turn on promiscuous mode so
4493 * that we can at least receive multicast traffic
4494 */
4495 count = ixgbe_write_mc_addr_list(netdev);
4496 if (count < 0) {
4497 fctrl |= IXGBE_FCTRL_MPE;
4498 vmolr |= IXGBE_VMOLR_MPE;
4499 } else if (count) {
4500 vmolr |= IXGBE_VMOLR_ROMPE;
4501 }
4502
4503 if (hw->mac.type != ixgbe_mac_82598EB) {
4504 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
4505 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4506 IXGBE_VMOLR_ROPE);
4507 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
4508 }
4509
4510 /* This is useful for sniffing bad packets. */
4511 if (features & NETIF_F_RXALL) {
4512 /* UPE and MPE will be handled by normal PROMISC logic
4513 * in e1000e_set_rx_mode */
4514 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4515 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4516 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4517
4518 fctrl &= ~(IXGBE_FCTRL_DPF);
4519 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4520 }
4521
4522 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4523
4524 if (features & NETIF_F_HW_VLAN_CTAG_RX)
4525 ixgbe_vlan_strip_enable(adapter);
4526 else
4527 ixgbe_vlan_strip_disable(adapter);
4528
4529 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
4530 ixgbe_vlan_promisc_disable(adapter);
4531 else
4532 ixgbe_vlan_promisc_enable(adapter);
4533 }
4534
4535 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4536 {
4537 int q_idx;
4538
4539 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4540 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
4541 napi_enable(&adapter->q_vector[q_idx]->napi);
4542 }
4543 }
4544
4545 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4546 {
4547 int q_idx;
4548
4549 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4550 napi_disable(&adapter->q_vector[q_idx]->napi);
4551 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
4552 pr_info("QV %d locked\n", q_idx);
4553 usleep_range(1000, 20000);
4554 }
4555 }
4556 }
4557
4558 static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter)
4559 {
4560 switch (adapter->hw.mac.type) {
4561 case ixgbe_mac_X550:
4562 case ixgbe_mac_X550EM_x:
4563 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0);
4564 adapter->vxlan_port = 0;
4565 break;
4566 default:
4567 break;
4568 }
4569 }
4570
4571 #ifdef CONFIG_IXGBE_DCB
4572 /**
4573 * ixgbe_configure_dcb - Configure DCB hardware
4574 * @adapter: ixgbe adapter struct
4575 *
4576 * This is called by the driver on open to configure the DCB hardware.
4577 * This is also called by the gennetlink interface when reconfiguring
4578 * the DCB state.
4579 */
4580 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4581 {
4582 struct ixgbe_hw *hw = &adapter->hw;
4583 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4584
4585 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4586 if (hw->mac.type == ixgbe_mac_82598EB)
4587 netif_set_gso_max_size(adapter->netdev, 65536);
4588 return;
4589 }
4590
4591 if (hw->mac.type == ixgbe_mac_82598EB)
4592 netif_set_gso_max_size(adapter->netdev, 32768);
4593
4594 #ifdef IXGBE_FCOE
4595 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4596 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
4597 #endif
4598
4599 /* reconfigure the hardware */
4600 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
4601 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4602 DCB_TX_CONFIG);
4603 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4604 DCB_RX_CONFIG);
4605 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
4606 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4607 ixgbe_dcb_hw_ets(&adapter->hw,
4608 adapter->ixgbe_ieee_ets,
4609 max_frame);
4610 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4611 adapter->ixgbe_ieee_pfc->pfc_en,
4612 adapter->ixgbe_ieee_ets->prio_tc);
4613 }
4614
4615 /* Enable RSS Hash per TC */
4616 if (hw->mac.type != ixgbe_mac_82598EB) {
4617 u32 msb = 0;
4618 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
4619
4620 while (rss_i) {
4621 msb++;
4622 rss_i >>= 1;
4623 }
4624
4625 /* write msb to all 8 TCs in one write */
4626 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
4627 }
4628 }
4629 #endif
4630
4631 /* Additional bittime to account for IXGBE framing */
4632 #define IXGBE_ETH_FRAMING 20
4633
4634 /**
4635 * ixgbe_hpbthresh - calculate high water mark for flow control
4636 *
4637 * @adapter: board private structure to calculate for
4638 * @pb: packet buffer to calculate
4639 */
4640 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4641 {
4642 struct ixgbe_hw *hw = &adapter->hw;
4643 struct net_device *dev = adapter->netdev;
4644 int link, tc, kb, marker;
4645 u32 dv_id, rx_pba;
4646
4647 /* Calculate max LAN frame size */
4648 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4649
4650 #ifdef IXGBE_FCOE
4651 /* FCoE traffic class uses FCOE jumbo frames */
4652 if ((dev->features & NETIF_F_FCOE_MTU) &&
4653 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4654 (pb == ixgbe_fcoe_get_tc(adapter)))
4655 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4656 #endif
4657
4658 /* Calculate delay value for device */
4659 switch (hw->mac.type) {
4660 case ixgbe_mac_X540:
4661 case ixgbe_mac_X550:
4662 case ixgbe_mac_X550EM_x:
4663 dv_id = IXGBE_DV_X540(link, tc);
4664 break;
4665 default:
4666 dv_id = IXGBE_DV(link, tc);
4667 break;
4668 }
4669
4670 /* Loopback switch introduces additional latency */
4671 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4672 dv_id += IXGBE_B2BT(tc);
4673
4674 /* Delay value is calculated in bit times convert to KB */
4675 kb = IXGBE_BT2KB(dv_id);
4676 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4677
4678 marker = rx_pba - kb;
4679
4680 /* It is possible that the packet buffer is not large enough
4681 * to provide required headroom. In this case throw an error
4682 * to user and a do the best we can.
4683 */
4684 if (marker < 0) {
4685 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4686 "headroom to support flow control."
4687 "Decrease MTU or number of traffic classes\n", pb);
4688 marker = tc + 1;
4689 }
4690
4691 return marker;
4692 }
4693
4694 /**
4695 * ixgbe_lpbthresh - calculate low water mark for for flow control
4696 *
4697 * @adapter: board private structure to calculate for
4698 * @pb: packet buffer to calculate
4699 */
4700 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
4701 {
4702 struct ixgbe_hw *hw = &adapter->hw;
4703 struct net_device *dev = adapter->netdev;
4704 int tc;
4705 u32 dv_id;
4706
4707 /* Calculate max LAN frame size */
4708 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4709
4710 #ifdef IXGBE_FCOE
4711 /* FCoE traffic class uses FCOE jumbo frames */
4712 if ((dev->features & NETIF_F_FCOE_MTU) &&
4713 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4714 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4715 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4716 #endif
4717
4718 /* Calculate delay value for device */
4719 switch (hw->mac.type) {
4720 case ixgbe_mac_X540:
4721 case ixgbe_mac_X550:
4722 case ixgbe_mac_X550EM_x:
4723 dv_id = IXGBE_LOW_DV_X540(tc);
4724 break;
4725 default:
4726 dv_id = IXGBE_LOW_DV(tc);
4727 break;
4728 }
4729
4730 /* Delay value is calculated in bit times convert to KB */
4731 return IXGBE_BT2KB(dv_id);
4732 }
4733
4734 /*
4735 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4736 */
4737 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4738 {
4739 struct ixgbe_hw *hw = &adapter->hw;
4740 int num_tc = netdev_get_num_tc(adapter->netdev);
4741 int i;
4742
4743 if (!num_tc)
4744 num_tc = 1;
4745
4746 for (i = 0; i < num_tc; i++) {
4747 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4748 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
4749
4750 /* Low water marks must not be larger than high water marks */
4751 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4752 hw->fc.low_water[i] = 0;
4753 }
4754
4755 for (; i < MAX_TRAFFIC_CLASS; i++)
4756 hw->fc.high_water[i] = 0;
4757 }
4758
4759 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4760 {
4761 struct ixgbe_hw *hw = &adapter->hw;
4762 int hdrm;
4763 u8 tc = netdev_get_num_tc(adapter->netdev);
4764
4765 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4766 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4767 hdrm = 32 << adapter->fdir_pballoc;
4768 else
4769 hdrm = 0;
4770
4771 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
4772 ixgbe_pbthresh_setup(adapter);
4773 }
4774
4775 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4776 {
4777 struct ixgbe_hw *hw = &adapter->hw;
4778 struct hlist_node *node2;
4779 struct ixgbe_fdir_filter *filter;
4780
4781 spin_lock(&adapter->fdir_perfect_lock);
4782
4783 if (!hlist_empty(&adapter->fdir_filter_list))
4784 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4785
4786 hlist_for_each_entry_safe(filter, node2,
4787 &adapter->fdir_filter_list, fdir_node) {
4788 ixgbe_fdir_write_perfect_filter_82599(hw,
4789 &filter->filter,
4790 filter->sw_idx,
4791 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4792 IXGBE_FDIR_DROP_QUEUE :
4793 adapter->rx_ring[filter->action]->reg_idx);
4794 }
4795
4796 spin_unlock(&adapter->fdir_perfect_lock);
4797 }
4798
4799 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4800 struct ixgbe_adapter *adapter)
4801 {
4802 struct ixgbe_hw *hw = &adapter->hw;
4803 u32 vmolr;
4804
4805 /* No unicast promiscuous support for VMDQ devices. */
4806 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4807 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4808
4809 /* clear the affected bit */
4810 vmolr &= ~IXGBE_VMOLR_MPE;
4811
4812 if (dev->flags & IFF_ALLMULTI) {
4813 vmolr |= IXGBE_VMOLR_MPE;
4814 } else {
4815 vmolr |= IXGBE_VMOLR_ROMPE;
4816 hw->mac.ops.update_mc_addr_list(hw, dev);
4817 }
4818 ixgbe_write_uc_addr_list(adapter->netdev, pool);
4819 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4820 }
4821
4822 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4823 {
4824 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4825 int rss_i = adapter->num_rx_queues_per_pool;
4826 struct ixgbe_hw *hw = &adapter->hw;
4827 u16 pool = vadapter->pool;
4828 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4829 IXGBE_PSRTYPE_UDPHDR |
4830 IXGBE_PSRTYPE_IPV4HDR |
4831 IXGBE_PSRTYPE_L2HDR |
4832 IXGBE_PSRTYPE_IPV6HDR;
4833
4834 if (hw->mac.type == ixgbe_mac_82598EB)
4835 return;
4836
4837 if (rss_i > 3)
4838 psrtype |= 2 << 29;
4839 else if (rss_i > 1)
4840 psrtype |= 1 << 29;
4841
4842 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4843 }
4844
4845 /**
4846 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4847 * @rx_ring: ring to free buffers from
4848 **/
4849 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4850 {
4851 struct device *dev = rx_ring->dev;
4852 unsigned long size;
4853 u16 i;
4854
4855 /* ring already cleared, nothing to do */
4856 if (!rx_ring->rx_buffer_info)
4857 return;
4858
4859 /* Free all the Rx ring sk_buffs */
4860 for (i = 0; i < rx_ring->count; i++) {
4861 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
4862
4863 if (rx_buffer->skb) {
4864 struct sk_buff *skb = rx_buffer->skb;
4865 if (IXGBE_CB(skb)->page_released)
4866 dma_unmap_page(dev,
4867 IXGBE_CB(skb)->dma,
4868 ixgbe_rx_bufsz(rx_ring),
4869 DMA_FROM_DEVICE);
4870 dev_kfree_skb(skb);
4871 rx_buffer->skb = NULL;
4872 }
4873
4874 if (!rx_buffer->page)
4875 continue;
4876
4877 dma_unmap_page(dev, rx_buffer->dma,
4878 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4879 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4880
4881 rx_buffer->page = NULL;
4882 }
4883
4884 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4885 memset(rx_ring->rx_buffer_info, 0, size);
4886
4887 /* Zero out the descriptor ring */
4888 memset(rx_ring->desc, 0, rx_ring->size);
4889
4890 rx_ring->next_to_alloc = 0;
4891 rx_ring->next_to_clean = 0;
4892 rx_ring->next_to_use = 0;
4893 }
4894
4895 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4896 struct ixgbe_ring *rx_ring)
4897 {
4898 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4899 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4900
4901 /* shutdown specific queue receive and wait for dma to settle */
4902 ixgbe_disable_rx_queue(adapter, rx_ring);
4903 usleep_range(10000, 20000);
4904 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4905 ixgbe_clean_rx_ring(rx_ring);
4906 rx_ring->l2_accel_priv = NULL;
4907 }
4908
4909 static int ixgbe_fwd_ring_down(struct net_device *vdev,
4910 struct ixgbe_fwd_adapter *accel)
4911 {
4912 struct ixgbe_adapter *adapter = accel->real_adapter;
4913 unsigned int rxbase = accel->rx_base_queue;
4914 unsigned int txbase = accel->tx_base_queue;
4915 int i;
4916
4917 netif_tx_stop_all_queues(vdev);
4918
4919 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4920 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4921 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4922 }
4923
4924 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4925 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4926 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4927 }
4928
4929
4930 return 0;
4931 }
4932
4933 static int ixgbe_fwd_ring_up(struct net_device *vdev,
4934 struct ixgbe_fwd_adapter *accel)
4935 {
4936 struct ixgbe_adapter *adapter = accel->real_adapter;
4937 unsigned int rxbase, txbase, queues;
4938 int i, baseq, err = 0;
4939
4940 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4941 return 0;
4942
4943 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4944 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4945 accel->pool, adapter->num_rx_pools,
4946 baseq, baseq + adapter->num_rx_queues_per_pool,
4947 adapter->fwd_bitmask);
4948
4949 accel->netdev = vdev;
4950 accel->rx_base_queue = rxbase = baseq;
4951 accel->tx_base_queue = txbase = baseq;
4952
4953 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4954 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4955
4956 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4957 adapter->rx_ring[rxbase + i]->netdev = vdev;
4958 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4959 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4960 }
4961
4962 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4963 adapter->tx_ring[txbase + i]->netdev = vdev;
4964 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4965 }
4966
4967 queues = min_t(unsigned int,
4968 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4969 err = netif_set_real_num_tx_queues(vdev, queues);
4970 if (err)
4971 goto fwd_queue_err;
4972
4973 err = netif_set_real_num_rx_queues(vdev, queues);
4974 if (err)
4975 goto fwd_queue_err;
4976
4977 if (is_valid_ether_addr(vdev->dev_addr))
4978 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4979
4980 ixgbe_fwd_psrtype(accel);
4981 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4982 return err;
4983 fwd_queue_err:
4984 ixgbe_fwd_ring_down(vdev, accel);
4985 return err;
4986 }
4987
4988 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4989 {
4990 struct net_device *upper;
4991 struct list_head *iter;
4992 int err;
4993
4994 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4995 if (netif_is_macvlan(upper)) {
4996 struct macvlan_dev *dfwd = netdev_priv(upper);
4997 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4998
4999 if (dfwd->fwd_priv) {
5000 err = ixgbe_fwd_ring_up(upper, vadapter);
5001 if (err)
5002 continue;
5003 }
5004 }
5005 }
5006 }
5007
5008 static void ixgbe_configure(struct ixgbe_adapter *adapter)
5009 {
5010 struct ixgbe_hw *hw = &adapter->hw;
5011
5012 ixgbe_configure_pb(adapter);
5013 #ifdef CONFIG_IXGBE_DCB
5014 ixgbe_configure_dcb(adapter);
5015 #endif
5016 /*
5017 * We must restore virtualization before VLANs or else
5018 * the VLVF registers will not be populated
5019 */
5020 ixgbe_configure_virtualization(adapter);
5021
5022 ixgbe_set_rx_mode(adapter->netdev);
5023 ixgbe_restore_vlan(adapter);
5024
5025 switch (hw->mac.type) {
5026 case ixgbe_mac_82599EB:
5027 case ixgbe_mac_X540:
5028 hw->mac.ops.disable_rx_buff(hw);
5029 break;
5030 default:
5031 break;
5032 }
5033
5034 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5035 ixgbe_init_fdir_signature_82599(&adapter->hw,
5036 adapter->fdir_pballoc);
5037 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
5038 ixgbe_init_fdir_perfect_82599(&adapter->hw,
5039 adapter->fdir_pballoc);
5040 ixgbe_fdir_filter_restore(adapter);
5041 }
5042
5043 switch (hw->mac.type) {
5044 case ixgbe_mac_82599EB:
5045 case ixgbe_mac_X540:
5046 hw->mac.ops.enable_rx_buff(hw);
5047 break;
5048 default:
5049 break;
5050 }
5051
5052 #ifdef CONFIG_IXGBE_DCA
5053 /* configure DCA */
5054 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
5055 ixgbe_setup_dca(adapter);
5056 #endif /* CONFIG_IXGBE_DCA */
5057
5058 #ifdef IXGBE_FCOE
5059 /* configure FCoE L2 filters, redirection table, and Rx control */
5060 ixgbe_configure_fcoe(adapter);
5061
5062 #endif /* IXGBE_FCOE */
5063 ixgbe_configure_tx(adapter);
5064 ixgbe_configure_rx(adapter);
5065 ixgbe_configure_dfwd(adapter);
5066 }
5067
5068 /**
5069 * ixgbe_sfp_link_config - set up SFP+ link
5070 * @adapter: pointer to private adapter struct
5071 **/
5072 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
5073 {
5074 /*
5075 * We are assuming the worst case scenario here, and that
5076 * is that an SFP was inserted/removed after the reset
5077 * but before SFP detection was enabled. As such the best
5078 * solution is to just start searching as soon as we start
5079 */
5080 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5081 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5082
5083 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5084 adapter->sfp_poll_time = 0;
5085 }
5086
5087 /**
5088 * ixgbe_non_sfp_link_config - set up non-SFP+ link
5089 * @hw: pointer to private hardware struct
5090 *
5091 * Returns 0 on success, negative on failure
5092 **/
5093 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
5094 {
5095 u32 speed;
5096 bool autoneg, link_up = false;
5097 int ret = IXGBE_ERR_LINK_SETUP;
5098
5099 if (hw->mac.ops.check_link)
5100 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
5101
5102 if (ret)
5103 return ret;
5104
5105 speed = hw->phy.autoneg_advertised;
5106 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5107 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
5108 &autoneg);
5109 if (ret)
5110 return ret;
5111
5112 if (hw->mac.ops.setup_link)
5113 ret = hw->mac.ops.setup_link(hw, speed, link_up);
5114
5115 return ret;
5116 }
5117
5118 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
5119 {
5120 struct ixgbe_hw *hw = &adapter->hw;
5121 u32 gpie = 0;
5122
5123 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5124 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5125 IXGBE_GPIE_OCD;
5126 gpie |= IXGBE_GPIE_EIAME;
5127 /*
5128 * use EIAM to auto-mask when MSI-X interrupt is asserted
5129 * this saves a register write for every interrupt
5130 */
5131 switch (hw->mac.type) {
5132 case ixgbe_mac_82598EB:
5133 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5134 break;
5135 case ixgbe_mac_82599EB:
5136 case ixgbe_mac_X540:
5137 case ixgbe_mac_X550:
5138 case ixgbe_mac_X550EM_x:
5139 default:
5140 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5141 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5142 break;
5143 }
5144 } else {
5145 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
5146 * specifically only auto mask tx and rx interrupts */
5147 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5148 }
5149
5150 /* XXX: to interrupt immediately for EICS writes, enable this */
5151 /* gpie |= IXGBE_GPIE_EIMEN; */
5152
5153 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
5154 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
5155
5156 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
5157 case IXGBE_82599_VMDQ_8Q_MASK:
5158 gpie |= IXGBE_GPIE_VTMODE_16;
5159 break;
5160 case IXGBE_82599_VMDQ_4Q_MASK:
5161 gpie |= IXGBE_GPIE_VTMODE_32;
5162 break;
5163 default:
5164 gpie |= IXGBE_GPIE_VTMODE_64;
5165 break;
5166 }
5167 }
5168
5169 /* Enable Thermal over heat sensor interrupt */
5170 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
5171 switch (adapter->hw.mac.type) {
5172 case ixgbe_mac_82599EB:
5173 gpie |= IXGBE_SDP0_GPIEN_8259X;
5174 break;
5175 default:
5176 break;
5177 }
5178 }
5179
5180 /* Enable fan failure interrupt */
5181 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
5182 gpie |= IXGBE_SDP1_GPIEN(hw);
5183
5184 switch (hw->mac.type) {
5185 case ixgbe_mac_82599EB:
5186 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
5187 break;
5188 case ixgbe_mac_X550EM_x:
5189 gpie |= IXGBE_SDP0_GPIEN_X540;
5190 break;
5191 default:
5192 break;
5193 }
5194
5195 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5196 }
5197
5198 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
5199 {
5200 struct ixgbe_hw *hw = &adapter->hw;
5201 int err;
5202 u32 ctrl_ext;
5203
5204 ixgbe_get_hw_control(adapter);
5205 ixgbe_setup_gpie(adapter);
5206
5207 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5208 ixgbe_configure_msix(adapter);
5209 else
5210 ixgbe_configure_msi_and_legacy(adapter);
5211
5212 /* enable the optics for 82599 SFP+ fiber */
5213 if (hw->mac.ops.enable_tx_laser)
5214 hw->mac.ops.enable_tx_laser(hw);
5215
5216 if (hw->phy.ops.set_phy_power)
5217 hw->phy.ops.set_phy_power(hw, true);
5218
5219 smp_mb__before_atomic();
5220 clear_bit(__IXGBE_DOWN, &adapter->state);
5221 ixgbe_napi_enable_all(adapter);
5222
5223 if (ixgbe_is_sfp(hw)) {
5224 ixgbe_sfp_link_config(adapter);
5225 } else {
5226 err = ixgbe_non_sfp_link_config(hw);
5227 if (err)
5228 e_err(probe, "link_config FAILED %d\n", err);
5229 }
5230
5231 /* clear any pending interrupts, may auto mask */
5232 IXGBE_READ_REG(hw, IXGBE_EICR);
5233 ixgbe_irq_enable(adapter, true, true);
5234
5235 /*
5236 * If this adapter has a fan, check to see if we had a failure
5237 * before we enabled the interrupt.
5238 */
5239 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5240 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5241 if (esdp & IXGBE_ESDP_SDP1)
5242 e_crit(drv, "Fan has stopped, replace the adapter\n");
5243 }
5244
5245 /* bring the link up in the watchdog, this could race with our first
5246 * link up interrupt but shouldn't be a problem */
5247 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5248 adapter->link_check_timeout = jiffies;
5249 mod_timer(&adapter->service_timer, jiffies);
5250
5251 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5252 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5253 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5254 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
5255 }
5256
5257 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5258 {
5259 WARN_ON(in_interrupt());
5260 /* put off any impending NetWatchDogTimeout */
5261 adapter->netdev->trans_start = jiffies;
5262
5263 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
5264 usleep_range(1000, 2000);
5265 ixgbe_down(adapter);
5266 /*
5267 * If SR-IOV enabled then wait a bit before bringing the adapter
5268 * back up to give the VFs time to respond to the reset. The
5269 * two second wait is based upon the watchdog timer cycle in
5270 * the VF driver.
5271 */
5272 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5273 msleep(2000);
5274 ixgbe_up(adapter);
5275 clear_bit(__IXGBE_RESETTING, &adapter->state);
5276 }
5277
5278 void ixgbe_up(struct ixgbe_adapter *adapter)
5279 {
5280 /* hardware has been reset, we need to reload some things */
5281 ixgbe_configure(adapter);
5282
5283 ixgbe_up_complete(adapter);
5284 }
5285
5286 void ixgbe_reset(struct ixgbe_adapter *adapter)
5287 {
5288 struct ixgbe_hw *hw = &adapter->hw;
5289 struct net_device *netdev = adapter->netdev;
5290 int err;
5291
5292 if (ixgbe_removed(hw->hw_addr))
5293 return;
5294 /* lock SFP init bit to prevent race conditions with the watchdog */
5295 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5296 usleep_range(1000, 2000);
5297
5298 /* clear all SFP and link config related flags while holding SFP_INIT */
5299 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5300 IXGBE_FLAG2_SFP_NEEDS_RESET);
5301 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5302
5303 err = hw->mac.ops.init_hw(hw);
5304 switch (err) {
5305 case 0:
5306 case IXGBE_ERR_SFP_NOT_PRESENT:
5307 case IXGBE_ERR_SFP_NOT_SUPPORTED:
5308 break;
5309 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
5310 e_dev_err("master disable timed out\n");
5311 break;
5312 case IXGBE_ERR_EEPROM_VERSION:
5313 /* We are running on a pre-production device, log a warning */
5314 e_dev_warn("This device is a pre-production adapter/LOM. "
5315 "Please be aware there may be issues associated with "
5316 "your hardware. If you are experiencing problems "
5317 "please contact your Intel or hardware "
5318 "representative who provided you with this "
5319 "hardware.\n");
5320 break;
5321 default:
5322 e_dev_err("Hardware Error: %d\n", err);
5323 }
5324
5325 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5326
5327 /* flush entries out of MAC table */
5328 ixgbe_flush_sw_mac_table(adapter);
5329 __dev_uc_unsync(netdev, NULL);
5330
5331 /* do not flush user set addresses */
5332 ixgbe_mac_set_default_filter(adapter);
5333
5334 /* update SAN MAC vmdq pool selection */
5335 if (hw->mac.san_mac_rar_index)
5336 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
5337
5338 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
5339 ixgbe_ptp_reset(adapter);
5340
5341 if (hw->phy.ops.set_phy_power) {
5342 if (!netif_running(adapter->netdev) && !adapter->wol)
5343 hw->phy.ops.set_phy_power(hw, false);
5344 else
5345 hw->phy.ops.set_phy_power(hw, true);
5346 }
5347 }
5348
5349 /**
5350 * ixgbe_clean_tx_ring - Free Tx Buffers
5351 * @tx_ring: ring to be cleaned
5352 **/
5353 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
5354 {
5355 struct ixgbe_tx_buffer *tx_buffer_info;
5356 unsigned long size;
5357 u16 i;
5358
5359 /* ring already cleared, nothing to do */
5360 if (!tx_ring->tx_buffer_info)
5361 return;
5362
5363 /* Free all the Tx ring sk_buffs */
5364 for (i = 0; i < tx_ring->count; i++) {
5365 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5366 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
5367 }
5368
5369 netdev_tx_reset_queue(txring_txq(tx_ring));
5370
5371 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5372 memset(tx_ring->tx_buffer_info, 0, size);
5373
5374 /* Zero out the descriptor ring */
5375 memset(tx_ring->desc, 0, tx_ring->size);
5376
5377 tx_ring->next_to_use = 0;
5378 tx_ring->next_to_clean = 0;
5379 }
5380
5381 /**
5382 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
5383 * @adapter: board private structure
5384 **/
5385 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
5386 {
5387 int i;
5388
5389 for (i = 0; i < adapter->num_rx_queues; i++)
5390 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
5391 }
5392
5393 /**
5394 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
5395 * @adapter: board private structure
5396 **/
5397 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
5398 {
5399 int i;
5400
5401 for (i = 0; i < adapter->num_tx_queues; i++)
5402 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
5403 }
5404
5405 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5406 {
5407 struct hlist_node *node2;
5408 struct ixgbe_fdir_filter *filter;
5409
5410 spin_lock(&adapter->fdir_perfect_lock);
5411
5412 hlist_for_each_entry_safe(filter, node2,
5413 &adapter->fdir_filter_list, fdir_node) {
5414 hlist_del(&filter->fdir_node);
5415 kfree(filter);
5416 }
5417 adapter->fdir_filter_count = 0;
5418
5419 spin_unlock(&adapter->fdir_perfect_lock);
5420 }
5421
5422 void ixgbe_down(struct ixgbe_adapter *adapter)
5423 {
5424 struct net_device *netdev = adapter->netdev;
5425 struct ixgbe_hw *hw = &adapter->hw;
5426 struct net_device *upper;
5427 struct list_head *iter;
5428 int i;
5429
5430 /* signal that we are down to the interrupt handler */
5431 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5432 return; /* do nothing if already down */
5433
5434 /* disable receives */
5435 hw->mac.ops.disable_rx(hw);
5436
5437 /* disable all enabled rx queues */
5438 for (i = 0; i < adapter->num_rx_queues; i++)
5439 /* this call also flushes the previous write */
5440 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5441
5442 usleep_range(10000, 20000);
5443
5444 netif_tx_stop_all_queues(netdev);
5445
5446 /* call carrier off first to avoid false dev_watchdog timeouts */
5447 netif_carrier_off(netdev);
5448 netif_tx_disable(netdev);
5449
5450 /* disable any upper devices */
5451 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5452 if (netif_is_macvlan(upper)) {
5453 struct macvlan_dev *vlan = netdev_priv(upper);
5454
5455 if (vlan->fwd_priv) {
5456 netif_tx_stop_all_queues(upper);
5457 netif_carrier_off(upper);
5458 netif_tx_disable(upper);
5459 }
5460 }
5461 }
5462
5463 ixgbe_irq_disable(adapter);
5464
5465 ixgbe_napi_disable_all(adapter);
5466
5467 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5468 IXGBE_FLAG2_RESET_REQUESTED);
5469 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5470
5471 del_timer_sync(&adapter->service_timer);
5472
5473 if (adapter->num_vfs) {
5474 /* Clear EITR Select mapping */
5475 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
5476
5477 /* Mark all the VFs as inactive */
5478 for (i = 0 ; i < adapter->num_vfs; i++)
5479 adapter->vfinfo[i].clear_to_send = false;
5480
5481 /* ping all the active vfs to let them know we are going down */
5482 ixgbe_ping_all_vfs(adapter);
5483
5484 /* Disable all VFTE/VFRE TX/RX */
5485 ixgbe_disable_tx_rx(adapter);
5486 }
5487
5488 /* disable transmits in the hardware now that interrupts are off */
5489 for (i = 0; i < adapter->num_tx_queues; i++) {
5490 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
5491 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5492 }
5493
5494 /* Disable the Tx DMA engine on 82599 and later MAC */
5495 switch (hw->mac.type) {
5496 case ixgbe_mac_82599EB:
5497 case ixgbe_mac_X540:
5498 case ixgbe_mac_X550:
5499 case ixgbe_mac_X550EM_x:
5500 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
5501 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5502 ~IXGBE_DMATXCTL_TE));
5503 break;
5504 default:
5505 break;
5506 }
5507
5508 if (!pci_channel_offline(adapter->pdev))
5509 ixgbe_reset(adapter);
5510
5511 /* power down the optics for 82599 SFP+ fiber */
5512 if (hw->mac.ops.disable_tx_laser)
5513 hw->mac.ops.disable_tx_laser(hw);
5514
5515 ixgbe_clean_all_tx_rings(adapter);
5516 ixgbe_clean_all_rx_rings(adapter);
5517 }
5518
5519 /**
5520 * ixgbe_tx_timeout - Respond to a Tx Hang
5521 * @netdev: network interface device structure
5522 **/
5523 static void ixgbe_tx_timeout(struct net_device *netdev)
5524 {
5525 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5526
5527 /* Do the reset outside of interrupt context */
5528 ixgbe_tx_timeout_reset(adapter);
5529 }
5530
5531 /**
5532 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5533 * @adapter: board private structure to initialize
5534 *
5535 * ixgbe_sw_init initializes the Adapter private data structure.
5536 * Fields are initialized based on PCI device information and
5537 * OS network device settings (MTU size).
5538 **/
5539 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
5540 {
5541 struct ixgbe_hw *hw = &adapter->hw;
5542 struct pci_dev *pdev = adapter->pdev;
5543 unsigned int rss, fdir;
5544 u32 fwsm;
5545 #ifdef CONFIG_IXGBE_DCB
5546 int j;
5547 struct tc_configuration *tc;
5548 #endif
5549
5550 /* PCI config space info */
5551
5552 hw->vendor_id = pdev->vendor;
5553 hw->device_id = pdev->device;
5554 hw->revision_id = pdev->revision;
5555 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5556 hw->subsystem_device_id = pdev->subsystem_device;
5557
5558 /* Set common capability flags and settings */
5559 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
5560 adapter->ring_feature[RING_F_RSS].limit = rss;
5561 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5562 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5563 adapter->atr_sample_rate = 20;
5564 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5565 adapter->ring_feature[RING_F_FDIR].limit = fdir;
5566 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5567 #ifdef CONFIG_IXGBE_DCA
5568 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5569 #endif
5570 #ifdef IXGBE_FCOE
5571 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5572 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5573 #ifdef CONFIG_IXGBE_DCB
5574 /* Default traffic class to use for FCoE */
5575 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5576 #endif /* CONFIG_IXGBE_DCB */
5577 #endif /* IXGBE_FCOE */
5578
5579 /* initialize static ixgbe jump table entries */
5580 adapter->jump_tables[0] = ixgbe_ipv4_fields;
5581
5582 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5583 hw->mac.num_rar_entries,
5584 GFP_ATOMIC);
5585 if (!adapter->mac_table)
5586 return -ENOMEM;
5587
5588 /* Set MAC specific capability flags and exceptions */
5589 switch (hw->mac.type) {
5590 case ixgbe_mac_82598EB:
5591 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5592
5593 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5594 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5595
5596 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
5597 adapter->ring_feature[RING_F_FDIR].limit = 0;
5598 adapter->atr_sample_rate = 0;
5599 adapter->fdir_pballoc = 0;
5600 #ifdef IXGBE_FCOE
5601 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5602 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5603 #ifdef CONFIG_IXGBE_DCB
5604 adapter->fcoe.up = 0;
5605 #endif /* IXGBE_DCB */
5606 #endif /* IXGBE_FCOE */
5607 break;
5608 case ixgbe_mac_82599EB:
5609 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5610 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5611 break;
5612 case ixgbe_mac_X540:
5613 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
5614 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5615 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5616 break;
5617 case ixgbe_mac_X550EM_x:
5618 case ixgbe_mac_X550:
5619 #ifdef CONFIG_IXGBE_DCA
5620 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
5621 #endif
5622 #ifdef CONFIG_IXGBE_VXLAN
5623 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
5624 #endif
5625 break;
5626 default:
5627 break;
5628 }
5629
5630 #ifdef IXGBE_FCOE
5631 /* FCoE support exists, always init the FCoE lock */
5632 spin_lock_init(&adapter->fcoe.lock);
5633
5634 #endif
5635 /* n-tuple support exists, always init our spinlock */
5636 spin_lock_init(&adapter->fdir_perfect_lock);
5637
5638 #ifdef CONFIG_IXGBE_DCB
5639 switch (hw->mac.type) {
5640 case ixgbe_mac_X540:
5641 case ixgbe_mac_X550:
5642 case ixgbe_mac_X550EM_x:
5643 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5644 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5645 break;
5646 default:
5647 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5648 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5649 break;
5650 }
5651
5652 /* Configure DCB traffic classes */
5653 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5654 tc = &adapter->dcb_cfg.tc_config[j];
5655 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5656 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5657 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5658 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5659 tc->dcb_pfc = pfc_disabled;
5660 }
5661
5662 /* Initialize default user to priority mapping, UPx->TC0 */
5663 tc = &adapter->dcb_cfg.tc_config[0];
5664 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5665 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5666
5667 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5668 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5669 adapter->dcb_cfg.pfc_mode_enable = false;
5670 adapter->dcb_set_bitmap = 0x00;
5671 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5672 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5673 sizeof(adapter->temp_dcb_cfg));
5674
5675 #endif
5676
5677 /* default flow control settings */
5678 hw->fc.requested_mode = ixgbe_fc_full;
5679 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5680 ixgbe_pbthresh_setup(adapter);
5681 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5682 hw->fc.send_xon = true;
5683 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
5684
5685 #ifdef CONFIG_PCI_IOV
5686 if (max_vfs > 0)
5687 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5688
5689 /* assign number of SR-IOV VFs */
5690 if (hw->mac.type != ixgbe_mac_82598EB) {
5691 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
5692 adapter->num_vfs = 0;
5693 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5694 } else {
5695 adapter->num_vfs = max_vfs;
5696 }
5697 }
5698 #endif /* CONFIG_PCI_IOV */
5699
5700 /* enable itr by default in dynamic mode */
5701 adapter->rx_itr_setting = 1;
5702 adapter->tx_itr_setting = 1;
5703
5704 /* set default ring sizes */
5705 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5706 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5707
5708 /* set default work limits */
5709 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5710
5711 /* initialize eeprom parameters */
5712 if (ixgbe_init_eeprom_params_generic(hw)) {
5713 e_dev_err("EEPROM initialization failed\n");
5714 return -EIO;
5715 }
5716
5717 /* PF holds first pool slot */
5718 set_bit(0, &adapter->fwd_bitmask);
5719 set_bit(__IXGBE_DOWN, &adapter->state);
5720
5721 return 0;
5722 }
5723
5724 /**
5725 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5726 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5727 *
5728 * Return 0 on success, negative on failure
5729 **/
5730 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5731 {
5732 struct device *dev = tx_ring->dev;
5733 int orig_node = dev_to_node(dev);
5734 int ring_node = -1;
5735 int size;
5736
5737 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5738
5739 if (tx_ring->q_vector)
5740 ring_node = tx_ring->q_vector->numa_node;
5741
5742 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
5743 if (!tx_ring->tx_buffer_info)
5744 tx_ring->tx_buffer_info = vzalloc(size);
5745 if (!tx_ring->tx_buffer_info)
5746 goto err;
5747
5748 u64_stats_init(&tx_ring->syncp);
5749
5750 /* round up to nearest 4K */
5751 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5752 tx_ring->size = ALIGN(tx_ring->size, 4096);
5753
5754 set_dev_node(dev, ring_node);
5755 tx_ring->desc = dma_alloc_coherent(dev,
5756 tx_ring->size,
5757 &tx_ring->dma,
5758 GFP_KERNEL);
5759 set_dev_node(dev, orig_node);
5760 if (!tx_ring->desc)
5761 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5762 &tx_ring->dma, GFP_KERNEL);
5763 if (!tx_ring->desc)
5764 goto err;
5765
5766 tx_ring->next_to_use = 0;
5767 tx_ring->next_to_clean = 0;
5768 return 0;
5769
5770 err:
5771 vfree(tx_ring->tx_buffer_info);
5772 tx_ring->tx_buffer_info = NULL;
5773 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5774 return -ENOMEM;
5775 }
5776
5777 /**
5778 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5779 * @adapter: board private structure
5780 *
5781 * If this function returns with an error, then it's possible one or
5782 * more of the rings is populated (while the rest are not). It is the
5783 * callers duty to clean those orphaned rings.
5784 *
5785 * Return 0 on success, negative on failure
5786 **/
5787 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5788 {
5789 int i, err = 0;
5790
5791 for (i = 0; i < adapter->num_tx_queues; i++) {
5792 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5793 if (!err)
5794 continue;
5795
5796 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5797 goto err_setup_tx;
5798 }
5799
5800 return 0;
5801 err_setup_tx:
5802 /* rewind the index freeing the rings as we go */
5803 while (i--)
5804 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5805 return err;
5806 }
5807
5808 /**
5809 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5810 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5811 *
5812 * Returns 0 on success, negative on failure
5813 **/
5814 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5815 {
5816 struct device *dev = rx_ring->dev;
5817 int orig_node = dev_to_node(dev);
5818 int ring_node = -1;
5819 int size;
5820
5821 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5822
5823 if (rx_ring->q_vector)
5824 ring_node = rx_ring->q_vector->numa_node;
5825
5826 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
5827 if (!rx_ring->rx_buffer_info)
5828 rx_ring->rx_buffer_info = vzalloc(size);
5829 if (!rx_ring->rx_buffer_info)
5830 goto err;
5831
5832 u64_stats_init(&rx_ring->syncp);
5833
5834 /* Round up to nearest 4K */
5835 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5836 rx_ring->size = ALIGN(rx_ring->size, 4096);
5837
5838 set_dev_node(dev, ring_node);
5839 rx_ring->desc = dma_alloc_coherent(dev,
5840 rx_ring->size,
5841 &rx_ring->dma,
5842 GFP_KERNEL);
5843 set_dev_node(dev, orig_node);
5844 if (!rx_ring->desc)
5845 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5846 &rx_ring->dma, GFP_KERNEL);
5847 if (!rx_ring->desc)
5848 goto err;
5849
5850 rx_ring->next_to_clean = 0;
5851 rx_ring->next_to_use = 0;
5852
5853 return 0;
5854 err:
5855 vfree(rx_ring->rx_buffer_info);
5856 rx_ring->rx_buffer_info = NULL;
5857 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5858 return -ENOMEM;
5859 }
5860
5861 /**
5862 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5863 * @adapter: board private structure
5864 *
5865 * If this function returns with an error, then it's possible one or
5866 * more of the rings is populated (while the rest are not). It is the
5867 * callers duty to clean those orphaned rings.
5868 *
5869 * Return 0 on success, negative on failure
5870 **/
5871 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5872 {
5873 int i, err = 0;
5874
5875 for (i = 0; i < adapter->num_rx_queues; i++) {
5876 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5877 if (!err)
5878 continue;
5879
5880 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5881 goto err_setup_rx;
5882 }
5883
5884 #ifdef IXGBE_FCOE
5885 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5886 if (!err)
5887 #endif
5888 return 0;
5889 err_setup_rx:
5890 /* rewind the index freeing the rings as we go */
5891 while (i--)
5892 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5893 return err;
5894 }
5895
5896 /**
5897 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5898 * @tx_ring: Tx descriptor ring for a specific queue
5899 *
5900 * Free all transmit software resources
5901 **/
5902 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5903 {
5904 ixgbe_clean_tx_ring(tx_ring);
5905
5906 vfree(tx_ring->tx_buffer_info);
5907 tx_ring->tx_buffer_info = NULL;
5908
5909 /* if not set, then don't free */
5910 if (!tx_ring->desc)
5911 return;
5912
5913 dma_free_coherent(tx_ring->dev, tx_ring->size,
5914 tx_ring->desc, tx_ring->dma);
5915
5916 tx_ring->desc = NULL;
5917 }
5918
5919 /**
5920 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5921 * @adapter: board private structure
5922 *
5923 * Free all transmit software resources
5924 **/
5925 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5926 {
5927 int i;
5928
5929 for (i = 0; i < adapter->num_tx_queues; i++)
5930 if (adapter->tx_ring[i]->desc)
5931 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5932 }
5933
5934 /**
5935 * ixgbe_free_rx_resources - Free Rx Resources
5936 * @rx_ring: ring to clean the resources from
5937 *
5938 * Free all receive software resources
5939 **/
5940 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5941 {
5942 ixgbe_clean_rx_ring(rx_ring);
5943
5944 vfree(rx_ring->rx_buffer_info);
5945 rx_ring->rx_buffer_info = NULL;
5946
5947 /* if not set, then don't free */
5948 if (!rx_ring->desc)
5949 return;
5950
5951 dma_free_coherent(rx_ring->dev, rx_ring->size,
5952 rx_ring->desc, rx_ring->dma);
5953
5954 rx_ring->desc = NULL;
5955 }
5956
5957 /**
5958 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5959 * @adapter: board private structure
5960 *
5961 * Free all receive software resources
5962 **/
5963 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5964 {
5965 int i;
5966
5967 #ifdef IXGBE_FCOE
5968 ixgbe_free_fcoe_ddp_resources(adapter);
5969
5970 #endif
5971 for (i = 0; i < adapter->num_rx_queues; i++)
5972 if (adapter->rx_ring[i]->desc)
5973 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5974 }
5975
5976 /**
5977 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5978 * @netdev: network interface device structure
5979 * @new_mtu: new value for maximum frame size
5980 *
5981 * Returns 0 on success, negative on failure
5982 **/
5983 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5984 {
5985 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5986 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5987
5988 /* MTU < 68 is an error and causes problems on some kernels */
5989 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5990 return -EINVAL;
5991
5992 /*
5993 * For 82599EB we cannot allow legacy VFs to enable their receive
5994 * paths when MTU greater than 1500 is configured. So display a
5995 * warning that legacy VFs will be disabled.
5996 */
5997 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5998 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
5999 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
6000 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
6001
6002 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
6003
6004 /* must set new MTU before calling down or up */
6005 netdev->mtu = new_mtu;
6006
6007 if (netif_running(netdev))
6008 ixgbe_reinit_locked(adapter);
6009
6010 return 0;
6011 }
6012
6013 /**
6014 * ixgbe_open - Called when a network interface is made active
6015 * @netdev: network interface device structure
6016 *
6017 * Returns 0 on success, negative value on failure
6018 *
6019 * The open entry point is called when a network interface is made
6020 * active by the system (IFF_UP). At this point all resources needed
6021 * for transmit and receive operations are allocated, the interrupt
6022 * handler is registered with the OS, the watchdog timer is started,
6023 * and the stack is notified that the interface is ready.
6024 **/
6025 int ixgbe_open(struct net_device *netdev)
6026 {
6027 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6028 struct ixgbe_hw *hw = &adapter->hw;
6029 int err, queues;
6030
6031 /* disallow open during test */
6032 if (test_bit(__IXGBE_TESTING, &adapter->state))
6033 return -EBUSY;
6034
6035 netif_carrier_off(netdev);
6036
6037 /* allocate transmit descriptors */
6038 err = ixgbe_setup_all_tx_resources(adapter);
6039 if (err)
6040 goto err_setup_tx;
6041
6042 /* allocate receive descriptors */
6043 err = ixgbe_setup_all_rx_resources(adapter);
6044 if (err)
6045 goto err_setup_rx;
6046
6047 ixgbe_configure(adapter);
6048
6049 err = ixgbe_request_irq(adapter);
6050 if (err)
6051 goto err_req_irq;
6052
6053 /* Notify the stack of the actual queue counts. */
6054 if (adapter->num_rx_pools > 1)
6055 queues = adapter->num_rx_queues_per_pool;
6056 else
6057 queues = adapter->num_tx_queues;
6058
6059 err = netif_set_real_num_tx_queues(netdev, queues);
6060 if (err)
6061 goto err_set_queues;
6062
6063 if (adapter->num_rx_pools > 1 &&
6064 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
6065 queues = IXGBE_MAX_L2A_QUEUES;
6066 else
6067 queues = adapter->num_rx_queues;
6068 err = netif_set_real_num_rx_queues(netdev, queues);
6069 if (err)
6070 goto err_set_queues;
6071
6072 ixgbe_ptp_init(adapter);
6073
6074 ixgbe_up_complete(adapter);
6075
6076 ixgbe_clear_vxlan_port(adapter);
6077 #ifdef CONFIG_IXGBE_VXLAN
6078 vxlan_get_rx_port(netdev);
6079 #endif
6080
6081 return 0;
6082
6083 err_set_queues:
6084 ixgbe_free_irq(adapter);
6085 err_req_irq:
6086 ixgbe_free_all_rx_resources(adapter);
6087 if (hw->phy.ops.set_phy_power && !adapter->wol)
6088 hw->phy.ops.set_phy_power(&adapter->hw, false);
6089 err_setup_rx:
6090 ixgbe_free_all_tx_resources(adapter);
6091 err_setup_tx:
6092 ixgbe_reset(adapter);
6093
6094 return err;
6095 }
6096
6097 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
6098 {
6099 ixgbe_ptp_suspend(adapter);
6100
6101 if (adapter->hw.phy.ops.enter_lplu) {
6102 adapter->hw.phy.reset_disable = true;
6103 ixgbe_down(adapter);
6104 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
6105 adapter->hw.phy.reset_disable = false;
6106 } else {
6107 ixgbe_down(adapter);
6108 }
6109
6110 ixgbe_free_irq(adapter);
6111
6112 ixgbe_free_all_tx_resources(adapter);
6113 ixgbe_free_all_rx_resources(adapter);
6114 }
6115
6116 /**
6117 * ixgbe_close - Disables a network interface
6118 * @netdev: network interface device structure
6119 *
6120 * Returns 0, this is not allowed to fail
6121 *
6122 * The close entry point is called when an interface is de-activated
6123 * by the OS. The hardware is still under the drivers control, but
6124 * needs to be disabled. A global MAC reset is issued to stop the
6125 * hardware, and all transmit and receive resources are freed.
6126 **/
6127 int ixgbe_close(struct net_device *netdev)
6128 {
6129 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6130
6131 ixgbe_ptp_stop(adapter);
6132
6133 ixgbe_close_suspend(adapter);
6134
6135 ixgbe_fdir_filter_exit(adapter);
6136
6137 ixgbe_release_hw_control(adapter);
6138
6139 return 0;
6140 }
6141
6142 #ifdef CONFIG_PM
6143 static int ixgbe_resume(struct pci_dev *pdev)
6144 {
6145 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6146 struct net_device *netdev = adapter->netdev;
6147 u32 err;
6148
6149 adapter->hw.hw_addr = adapter->io_addr;
6150 pci_set_power_state(pdev, PCI_D0);
6151 pci_restore_state(pdev);
6152 /*
6153 * pci_restore_state clears dev->state_saved so call
6154 * pci_save_state to restore it.
6155 */
6156 pci_save_state(pdev);
6157
6158 err = pci_enable_device_mem(pdev);
6159 if (err) {
6160 e_dev_err("Cannot enable PCI device from suspend\n");
6161 return err;
6162 }
6163 smp_mb__before_atomic();
6164 clear_bit(__IXGBE_DISABLED, &adapter->state);
6165 pci_set_master(pdev);
6166
6167 pci_wake_from_d3(pdev, false);
6168
6169 ixgbe_reset(adapter);
6170
6171 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6172
6173 rtnl_lock();
6174 err = ixgbe_init_interrupt_scheme(adapter);
6175 if (!err && netif_running(netdev))
6176 err = ixgbe_open(netdev);
6177
6178 rtnl_unlock();
6179
6180 if (err)
6181 return err;
6182
6183 netif_device_attach(netdev);
6184
6185 return 0;
6186 }
6187 #endif /* CONFIG_PM */
6188
6189 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
6190 {
6191 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6192 struct net_device *netdev = adapter->netdev;
6193 struct ixgbe_hw *hw = &adapter->hw;
6194 u32 ctrl, fctrl;
6195 u32 wufc = adapter->wol;
6196 #ifdef CONFIG_PM
6197 int retval = 0;
6198 #endif
6199
6200 netif_device_detach(netdev);
6201
6202 rtnl_lock();
6203 if (netif_running(netdev))
6204 ixgbe_close_suspend(adapter);
6205 rtnl_unlock();
6206
6207 ixgbe_clear_interrupt_scheme(adapter);
6208
6209 #ifdef CONFIG_PM
6210 retval = pci_save_state(pdev);
6211 if (retval)
6212 return retval;
6213
6214 #endif
6215 if (hw->mac.ops.stop_link_on_d3)
6216 hw->mac.ops.stop_link_on_d3(hw);
6217
6218 if (wufc) {
6219 ixgbe_set_rx_mode(netdev);
6220
6221 /* enable the optics for 82599 SFP+ fiber as we can WoL */
6222 if (hw->mac.ops.enable_tx_laser)
6223 hw->mac.ops.enable_tx_laser(hw);
6224
6225 /* turn on all-multi mode if wake on multicast is enabled */
6226 if (wufc & IXGBE_WUFC_MC) {
6227 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6228 fctrl |= IXGBE_FCTRL_MPE;
6229 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
6230 }
6231
6232 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
6233 ctrl |= IXGBE_CTRL_GIO_DIS;
6234 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
6235
6236 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
6237 } else {
6238 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
6239 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
6240 }
6241
6242 switch (hw->mac.type) {
6243 case ixgbe_mac_82598EB:
6244 pci_wake_from_d3(pdev, false);
6245 break;
6246 case ixgbe_mac_82599EB:
6247 case ixgbe_mac_X540:
6248 case ixgbe_mac_X550:
6249 case ixgbe_mac_X550EM_x:
6250 pci_wake_from_d3(pdev, !!wufc);
6251 break;
6252 default:
6253 break;
6254 }
6255
6256 *enable_wake = !!wufc;
6257 if (hw->phy.ops.set_phy_power && !*enable_wake)
6258 hw->phy.ops.set_phy_power(hw, false);
6259
6260 ixgbe_release_hw_control(adapter);
6261
6262 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6263 pci_disable_device(pdev);
6264
6265 return 0;
6266 }
6267
6268 #ifdef CONFIG_PM
6269 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
6270 {
6271 int retval;
6272 bool wake;
6273
6274 retval = __ixgbe_shutdown(pdev, &wake);
6275 if (retval)
6276 return retval;
6277
6278 if (wake) {
6279 pci_prepare_to_sleep(pdev);
6280 } else {
6281 pci_wake_from_d3(pdev, false);
6282 pci_set_power_state(pdev, PCI_D3hot);
6283 }
6284
6285 return 0;
6286 }
6287 #endif /* CONFIG_PM */
6288
6289 static void ixgbe_shutdown(struct pci_dev *pdev)
6290 {
6291 bool wake;
6292
6293 __ixgbe_shutdown(pdev, &wake);
6294
6295 if (system_state == SYSTEM_POWER_OFF) {
6296 pci_wake_from_d3(pdev, wake);
6297 pci_set_power_state(pdev, PCI_D3hot);
6298 }
6299 }
6300
6301 /**
6302 * ixgbe_update_stats - Update the board statistics counters.
6303 * @adapter: board private structure
6304 **/
6305 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6306 {
6307 struct net_device *netdev = adapter->netdev;
6308 struct ixgbe_hw *hw = &adapter->hw;
6309 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6310 u64 total_mpc = 0;
6311 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
6312 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6313 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
6314 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
6315
6316 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6317 test_bit(__IXGBE_RESETTING, &adapter->state))
6318 return;
6319
6320 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
6321 u64 rsc_count = 0;
6322 u64 rsc_flush = 0;
6323 for (i = 0; i < adapter->num_rx_queues; i++) {
6324 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6325 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
6326 }
6327 adapter->rsc_total_count = rsc_count;
6328 adapter->rsc_total_flush = rsc_flush;
6329 }
6330
6331 for (i = 0; i < adapter->num_rx_queues; i++) {
6332 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6333 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6334 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6335 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
6336 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
6337 bytes += rx_ring->stats.bytes;
6338 packets += rx_ring->stats.packets;
6339 }
6340 adapter->non_eop_descs = non_eop_descs;
6341 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6342 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
6343 adapter->hw_csum_rx_error = hw_csum_rx_error;
6344 netdev->stats.rx_bytes = bytes;
6345 netdev->stats.rx_packets = packets;
6346
6347 bytes = 0;
6348 packets = 0;
6349 /* gather some stats to the adapter struct that are per queue */
6350 for (i = 0; i < adapter->num_tx_queues; i++) {
6351 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6352 restart_queue += tx_ring->tx_stats.restart_queue;
6353 tx_busy += tx_ring->tx_stats.tx_busy;
6354 bytes += tx_ring->stats.bytes;
6355 packets += tx_ring->stats.packets;
6356 }
6357 adapter->restart_queue = restart_queue;
6358 adapter->tx_busy = tx_busy;
6359 netdev->stats.tx_bytes = bytes;
6360 netdev->stats.tx_packets = packets;
6361
6362 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6363
6364 /* 8 register reads */
6365 for (i = 0; i < 8; i++) {
6366 /* for packet buffers not used, the register should read 0 */
6367 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6368 missed_rx += mpc;
6369 hwstats->mpc[i] += mpc;
6370 total_mpc += hwstats->mpc[i];
6371 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6372 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6373 switch (hw->mac.type) {
6374 case ixgbe_mac_82598EB:
6375 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6376 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6377 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
6378 hwstats->pxonrxc[i] +=
6379 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
6380 break;
6381 case ixgbe_mac_82599EB:
6382 case ixgbe_mac_X540:
6383 case ixgbe_mac_X550:
6384 case ixgbe_mac_X550EM_x:
6385 hwstats->pxonrxc[i] +=
6386 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
6387 break;
6388 default:
6389 break;
6390 }
6391 }
6392
6393 /*16 register reads */
6394 for (i = 0; i < 16; i++) {
6395 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6396 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6397 if ((hw->mac.type == ixgbe_mac_82599EB) ||
6398 (hw->mac.type == ixgbe_mac_X540) ||
6399 (hw->mac.type == ixgbe_mac_X550) ||
6400 (hw->mac.type == ixgbe_mac_X550EM_x)) {
6401 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6402 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6403 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6404 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6405 }
6406 }
6407
6408 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6409 /* work around hardware counting issue */
6410 hwstats->gprc -= missed_rx;
6411
6412 ixgbe_update_xoff_received(adapter);
6413
6414 /* 82598 hardware only has a 32 bit counter in the high register */
6415 switch (hw->mac.type) {
6416 case ixgbe_mac_82598EB:
6417 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
6418 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6419 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6420 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6421 break;
6422 case ixgbe_mac_X540:
6423 case ixgbe_mac_X550:
6424 case ixgbe_mac_X550EM_x:
6425 /* OS2BMC stats are X540 and later */
6426 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6427 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6428 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6429 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6430 case ixgbe_mac_82599EB:
6431 for (i = 0; i < 16; i++)
6432 adapter->hw_rx_no_dma_resources +=
6433 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
6434 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
6435 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
6436 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
6437 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
6438 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
6439 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
6440 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
6441 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6442 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6443 #ifdef IXGBE_FCOE
6444 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6445 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6446 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6447 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6448 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6449 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6450 /* Add up per cpu counters for total ddp aloc fail */
6451 if (adapter->fcoe.ddp_pool) {
6452 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6453 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6454 unsigned int cpu;
6455 u64 noddp = 0, noddp_ext_buff = 0;
6456 for_each_possible_cpu(cpu) {
6457 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6458 noddp += ddp_pool->noddp;
6459 noddp_ext_buff += ddp_pool->noddp_ext_buff;
6460 }
6461 hwstats->fcoe_noddp = noddp;
6462 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
6463 }
6464 #endif /* IXGBE_FCOE */
6465 break;
6466 default:
6467 break;
6468 }
6469 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
6470 hwstats->bprc += bprc;
6471 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
6472 if (hw->mac.type == ixgbe_mac_82598EB)
6473 hwstats->mprc -= bprc;
6474 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6475 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6476 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6477 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6478 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6479 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6480 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6481 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6482 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
6483 hwstats->lxontxc += lxon;
6484 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
6485 hwstats->lxofftxc += lxoff;
6486 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6487 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6488 /*
6489 * 82598 errata - tx of flow control packets is included in tx counters
6490 */
6491 xon_off_tot = lxon + lxoff;
6492 hwstats->gptc -= xon_off_tot;
6493 hwstats->mptc -= xon_off_tot;
6494 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6495 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6496 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6497 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6498 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6499 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6500 hwstats->ptc64 -= xon_off_tot;
6501 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6502 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6503 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6504 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6505 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6506 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
6507
6508 /* Fill out the OS statistics structure */
6509 netdev->stats.multicast = hwstats->mprc;
6510
6511 /* Rx Errors */
6512 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
6513 netdev->stats.rx_dropped = 0;
6514 netdev->stats.rx_length_errors = hwstats->rlec;
6515 netdev->stats.rx_crc_errors = hwstats->crcerrs;
6516 netdev->stats.rx_missed_errors = total_mpc;
6517 }
6518
6519 /**
6520 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
6521 * @adapter: pointer to the device adapter structure
6522 **/
6523 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
6524 {
6525 struct ixgbe_hw *hw = &adapter->hw;
6526 int i;
6527
6528 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6529 return;
6530
6531 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
6532
6533 /* if interface is down do nothing */
6534 if (test_bit(__IXGBE_DOWN, &adapter->state))
6535 return;
6536
6537 /* do nothing if we are not using signature filters */
6538 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6539 return;
6540
6541 adapter->fdir_overflow++;
6542
6543 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6544 for (i = 0; i < adapter->num_tx_queues; i++)
6545 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
6546 &(adapter->tx_ring[i]->state));
6547 /* re-enable flow director interrupts */
6548 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
6549 } else {
6550 e_err(probe, "failed to finish FDIR re-initialization, "
6551 "ignored adding FDIR ATR filters\n");
6552 }
6553 }
6554
6555 /**
6556 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
6557 * @adapter: pointer to the device adapter structure
6558 *
6559 * This function serves two purposes. First it strobes the interrupt lines
6560 * in order to make certain interrupts are occurring. Secondly it sets the
6561 * bits needed to check for TX hangs. As a result we should immediately
6562 * determine if a hang has occurred.
6563 */
6564 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
6565 {
6566 struct ixgbe_hw *hw = &adapter->hw;
6567 u64 eics = 0;
6568 int i;
6569
6570 /* If we're down, removing or resetting, just bail */
6571 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6572 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6573 test_bit(__IXGBE_RESETTING, &adapter->state))
6574 return;
6575
6576 /* Force detection of hung controller */
6577 if (netif_carrier_ok(adapter->netdev)) {
6578 for (i = 0; i < adapter->num_tx_queues; i++)
6579 set_check_for_tx_hang(adapter->tx_ring[i]);
6580 }
6581
6582 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6583 /*
6584 * for legacy and MSI interrupts don't set any bits
6585 * that are enabled for EIAM, because this operation
6586 * would set *both* EIMS and EICS for any bit in EIAM
6587 */
6588 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6589 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
6590 } else {
6591 /* get one bit for every active tx/rx interrupt vector */
6592 for (i = 0; i < adapter->num_q_vectors; i++) {
6593 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6594 if (qv->rx.ring || qv->tx.ring)
6595 eics |= ((u64)1 << i);
6596 }
6597 }
6598
6599 /* Cause software interrupt to ensure rings are cleaned */
6600 ixgbe_irq_rearm_queues(adapter, eics);
6601 }
6602
6603 /**
6604 * ixgbe_watchdog_update_link - update the link status
6605 * @adapter: pointer to the device adapter structure
6606 * @link_speed: pointer to a u32 to store the link_speed
6607 **/
6608 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
6609 {
6610 struct ixgbe_hw *hw = &adapter->hw;
6611 u32 link_speed = adapter->link_speed;
6612 bool link_up = adapter->link_up;
6613 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
6614
6615 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6616 return;
6617
6618 if (hw->mac.ops.check_link) {
6619 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6620 } else {
6621 /* always assume link is up, if no check link function */
6622 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6623 link_up = true;
6624 }
6625
6626 if (adapter->ixgbe_ieee_pfc)
6627 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6628
6629 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
6630 hw->mac.ops.fc_enable(hw);
6631 ixgbe_set_rx_drop_en(adapter);
6632 }
6633
6634 if (link_up ||
6635 time_after(jiffies, (adapter->link_check_timeout +
6636 IXGBE_TRY_LINK_TIMEOUT))) {
6637 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6638 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6639 IXGBE_WRITE_FLUSH(hw);
6640 }
6641
6642 adapter->link_up = link_up;
6643 adapter->link_speed = link_speed;
6644 }
6645
6646 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6647 {
6648 #ifdef CONFIG_IXGBE_DCB
6649 struct net_device *netdev = adapter->netdev;
6650 struct dcb_app app = {
6651 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6652 .protocol = 0,
6653 };
6654 u8 up = 0;
6655
6656 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6657 up = dcb_ieee_getapp_mask(netdev, &app);
6658
6659 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6660 #endif
6661 }
6662
6663 /**
6664 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6665 * print link up message
6666 * @adapter: pointer to the device adapter structure
6667 **/
6668 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
6669 {
6670 struct net_device *netdev = adapter->netdev;
6671 struct ixgbe_hw *hw = &adapter->hw;
6672 struct net_device *upper;
6673 struct list_head *iter;
6674 u32 link_speed = adapter->link_speed;
6675 const char *speed_str;
6676 bool flow_rx, flow_tx;
6677
6678 /* only continue if link was previously down */
6679 if (netif_carrier_ok(netdev))
6680 return;
6681
6682 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
6683
6684 switch (hw->mac.type) {
6685 case ixgbe_mac_82598EB: {
6686 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6687 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6688 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6689 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6690 }
6691 break;
6692 case ixgbe_mac_X540:
6693 case ixgbe_mac_X550:
6694 case ixgbe_mac_X550EM_x:
6695 case ixgbe_mac_82599EB: {
6696 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6697 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6698 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6699 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6700 }
6701 break;
6702 default:
6703 flow_tx = false;
6704 flow_rx = false;
6705 break;
6706 }
6707
6708 adapter->last_rx_ptp_check = jiffies;
6709
6710 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6711 ixgbe_ptp_start_cyclecounter(adapter);
6712
6713 switch (link_speed) {
6714 case IXGBE_LINK_SPEED_10GB_FULL:
6715 speed_str = "10 Gbps";
6716 break;
6717 case IXGBE_LINK_SPEED_2_5GB_FULL:
6718 speed_str = "2.5 Gbps";
6719 break;
6720 case IXGBE_LINK_SPEED_1GB_FULL:
6721 speed_str = "1 Gbps";
6722 break;
6723 case IXGBE_LINK_SPEED_100_FULL:
6724 speed_str = "100 Mbps";
6725 break;
6726 default:
6727 speed_str = "unknown speed";
6728 break;
6729 }
6730 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
6731 ((flow_rx && flow_tx) ? "RX/TX" :
6732 (flow_rx ? "RX" :
6733 (flow_tx ? "TX" : "None"))));
6734
6735 netif_carrier_on(netdev);
6736 ixgbe_check_vf_rate_limit(adapter);
6737
6738 /* enable transmits */
6739 netif_tx_wake_all_queues(adapter->netdev);
6740
6741 /* enable any upper devices */
6742 rtnl_lock();
6743 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6744 if (netif_is_macvlan(upper)) {
6745 struct macvlan_dev *vlan = netdev_priv(upper);
6746
6747 if (vlan->fwd_priv)
6748 netif_tx_wake_all_queues(upper);
6749 }
6750 }
6751 rtnl_unlock();
6752
6753 /* update the default user priority for VFs */
6754 ixgbe_update_default_up(adapter);
6755
6756 /* ping all the active vfs to let them know link has changed */
6757 ixgbe_ping_all_vfs(adapter);
6758 }
6759
6760 /**
6761 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6762 * print link down message
6763 * @adapter: pointer to the adapter structure
6764 **/
6765 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
6766 {
6767 struct net_device *netdev = adapter->netdev;
6768 struct ixgbe_hw *hw = &adapter->hw;
6769
6770 adapter->link_up = false;
6771 adapter->link_speed = 0;
6772
6773 /* only continue if link was up previously */
6774 if (!netif_carrier_ok(netdev))
6775 return;
6776
6777 /* poll for SFP+ cable when link is down */
6778 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6779 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6780
6781 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6782 ixgbe_ptp_start_cyclecounter(adapter);
6783
6784 e_info(drv, "NIC Link is Down\n");
6785 netif_carrier_off(netdev);
6786
6787 /* ping all the active vfs to let them know link has changed */
6788 ixgbe_ping_all_vfs(adapter);
6789 }
6790
6791 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6792 {
6793 int i;
6794
6795 for (i = 0; i < adapter->num_tx_queues; i++) {
6796 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6797
6798 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6799 return true;
6800 }
6801
6802 return false;
6803 }
6804
6805 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6806 {
6807 struct ixgbe_hw *hw = &adapter->hw;
6808 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6809 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6810
6811 int i, j;
6812
6813 if (!adapter->num_vfs)
6814 return false;
6815
6816 /* resetting the PF is only needed for MAC before X550 */
6817 if (hw->mac.type >= ixgbe_mac_X550)
6818 return false;
6819
6820 for (i = 0; i < adapter->num_vfs; i++) {
6821 for (j = 0; j < q_per_pool; j++) {
6822 u32 h, t;
6823
6824 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6825 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6826
6827 if (h != t)
6828 return true;
6829 }
6830 }
6831
6832 return false;
6833 }
6834
6835 /**
6836 * ixgbe_watchdog_flush_tx - flush queues on link down
6837 * @adapter: pointer to the device adapter structure
6838 **/
6839 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6840 {
6841 if (!netif_carrier_ok(adapter->netdev)) {
6842 if (ixgbe_ring_tx_pending(adapter) ||
6843 ixgbe_vf_tx_pending(adapter)) {
6844 /* We've lost link, so the controller stops DMA,
6845 * but we've got queued Tx work that's never going
6846 * to get done, so reset controller to flush Tx.
6847 * (Do the reset outside of interrupt context).
6848 */
6849 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
6850 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6851 }
6852 }
6853 }
6854
6855 #ifdef CONFIG_PCI_IOV
6856 static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6857 struct pci_dev *vfdev)
6858 {
6859 if (!pci_wait_for_pending_transaction(vfdev))
6860 e_dev_warn("Issuing VFLR with pending transactions\n");
6861
6862 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6863 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6864
6865 msleep(100);
6866 }
6867
6868 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6869 {
6870 struct ixgbe_hw *hw = &adapter->hw;
6871 struct pci_dev *pdev = adapter->pdev;
6872 unsigned int vf;
6873 u32 gpc;
6874
6875 if (!(netif_carrier_ok(adapter->netdev)))
6876 return;
6877
6878 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6879 if (gpc) /* If incrementing then no need for the check below */
6880 return;
6881 /* Check to see if a bad DMA write target from an errant or
6882 * malicious VF has caused a PCIe error. If so then we can
6883 * issue a VFLR to the offending VF(s) and then resume without
6884 * requesting a full slot reset.
6885 */
6886
6887 if (!pdev)
6888 return;
6889
6890 /* check status reg for all VFs owned by this PF */
6891 for (vf = 0; vf < adapter->num_vfs; ++vf) {
6892 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev;
6893 u16 status_reg;
6894
6895 if (!vfdev)
6896 continue;
6897 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6898 if (status_reg != IXGBE_FAILED_READ_CFG_WORD &&
6899 status_reg & PCI_STATUS_REC_MASTER_ABORT)
6900 ixgbe_issue_vf_flr(adapter, vfdev);
6901 }
6902 }
6903
6904 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6905 {
6906 u32 ssvpc;
6907
6908 /* Do not perform spoof check for 82598 or if not in IOV mode */
6909 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6910 adapter->num_vfs == 0)
6911 return;
6912
6913 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6914
6915 /*
6916 * ssvpc register is cleared on read, if zero then no
6917 * spoofed packets in the last interval.
6918 */
6919 if (!ssvpc)
6920 return;
6921
6922 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
6923 }
6924 #else
6925 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
6926 {
6927 }
6928
6929 static void
6930 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
6931 {
6932 }
6933 #endif /* CONFIG_PCI_IOV */
6934
6935
6936 /**
6937 * ixgbe_watchdog_subtask - check and bring link up
6938 * @adapter: pointer to the device adapter structure
6939 **/
6940 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6941 {
6942 /* if interface is down, removing or resetting, do nothing */
6943 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6944 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6945 test_bit(__IXGBE_RESETTING, &adapter->state))
6946 return;
6947
6948 ixgbe_watchdog_update_link(adapter);
6949
6950 if (adapter->link_up)
6951 ixgbe_watchdog_link_is_up(adapter);
6952 else
6953 ixgbe_watchdog_link_is_down(adapter);
6954
6955 ixgbe_check_for_bad_vf(adapter);
6956 ixgbe_spoof_check(adapter);
6957 ixgbe_update_stats(adapter);
6958
6959 ixgbe_watchdog_flush_tx(adapter);
6960 }
6961
6962 /**
6963 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6964 * @adapter: the ixgbe adapter structure
6965 **/
6966 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6967 {
6968 struct ixgbe_hw *hw = &adapter->hw;
6969 s32 err;
6970
6971 /* not searching for SFP so there is nothing to do here */
6972 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6973 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6974 return;
6975
6976 if (adapter->sfp_poll_time &&
6977 time_after(adapter->sfp_poll_time, jiffies))
6978 return; /* If not yet time to poll for SFP */
6979
6980 /* someone else is in init, wait until next service event */
6981 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6982 return;
6983
6984 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
6985
6986 err = hw->phy.ops.identify_sfp(hw);
6987 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6988 goto sfp_out;
6989
6990 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6991 /* If no cable is present, then we need to reset
6992 * the next time we find a good cable. */
6993 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6994 }
6995
6996 /* exit on error */
6997 if (err)
6998 goto sfp_out;
6999
7000 /* exit if reset not needed */
7001 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7002 goto sfp_out;
7003
7004 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
7005
7006 /*
7007 * A module may be identified correctly, but the EEPROM may not have
7008 * support for that module. setup_sfp() will fail in that case, so
7009 * we should not allow that module to load.
7010 */
7011 if (hw->mac.type == ixgbe_mac_82598EB)
7012 err = hw->phy.ops.reset(hw);
7013 else
7014 err = hw->mac.ops.setup_sfp(hw);
7015
7016 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7017 goto sfp_out;
7018
7019 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
7020 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
7021
7022 sfp_out:
7023 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7024
7025 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
7026 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
7027 e_dev_err("failed to initialize because an unsupported "
7028 "SFP+ module type was detected.\n");
7029 e_dev_err("Reload the driver after installing a "
7030 "supported module.\n");
7031 unregister_netdev(adapter->netdev);
7032 }
7033 }
7034
7035 /**
7036 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
7037 * @adapter: the ixgbe adapter structure
7038 **/
7039 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
7040 {
7041 struct ixgbe_hw *hw = &adapter->hw;
7042 u32 speed;
7043 bool autoneg = false;
7044
7045 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
7046 return;
7047
7048 /* someone else is in init, wait until next service event */
7049 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7050 return;
7051
7052 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
7053
7054 speed = hw->phy.autoneg_advertised;
7055 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
7056 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
7057
7058 /* setup the highest link when no autoneg */
7059 if (!autoneg) {
7060 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
7061 speed = IXGBE_LINK_SPEED_10GB_FULL;
7062 }
7063 }
7064
7065 if (hw->mac.ops.setup_link)
7066 hw->mac.ops.setup_link(hw, speed, true);
7067
7068 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
7069 adapter->link_check_timeout = jiffies;
7070 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7071 }
7072
7073 /**
7074 * ixgbe_service_timer - Timer Call-back
7075 * @data: pointer to adapter cast into an unsigned long
7076 **/
7077 static void ixgbe_service_timer(unsigned long data)
7078 {
7079 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
7080 unsigned long next_event_offset;
7081
7082 /* poll faster when waiting for link */
7083 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
7084 next_event_offset = HZ / 10;
7085 else
7086 next_event_offset = HZ * 2;
7087
7088 /* Reset the timer */
7089 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
7090
7091 ixgbe_service_event_schedule(adapter);
7092 }
7093
7094 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
7095 {
7096 struct ixgbe_hw *hw = &adapter->hw;
7097 u32 status;
7098
7099 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
7100 return;
7101
7102 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
7103
7104 if (!hw->phy.ops.handle_lasi)
7105 return;
7106
7107 status = hw->phy.ops.handle_lasi(&adapter->hw);
7108 if (status != IXGBE_ERR_OVERTEMP)
7109 return;
7110
7111 e_crit(drv, "%s\n", ixgbe_overheat_msg);
7112 }
7113
7114 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
7115 {
7116 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
7117 return;
7118
7119 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
7120
7121 /* If we're already down, removing or resetting, just bail */
7122 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7123 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7124 test_bit(__IXGBE_RESETTING, &adapter->state))
7125 return;
7126
7127 ixgbe_dump(adapter);
7128 netdev_err(adapter->netdev, "Reset adapter\n");
7129 adapter->tx_timeout_count++;
7130
7131 rtnl_lock();
7132 ixgbe_reinit_locked(adapter);
7133 rtnl_unlock();
7134 }
7135
7136 /**
7137 * ixgbe_service_task - manages and runs subtasks
7138 * @work: pointer to work_struct containing our data
7139 **/
7140 static void ixgbe_service_task(struct work_struct *work)
7141 {
7142 struct ixgbe_adapter *adapter = container_of(work,
7143 struct ixgbe_adapter,
7144 service_task);
7145 if (ixgbe_removed(adapter->hw.hw_addr)) {
7146 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
7147 rtnl_lock();
7148 ixgbe_down(adapter);
7149 rtnl_unlock();
7150 }
7151 ixgbe_service_event_complete(adapter);
7152 return;
7153 }
7154 #ifdef CONFIG_IXGBE_VXLAN
7155 if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) {
7156 adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED;
7157 vxlan_get_rx_port(adapter->netdev);
7158 }
7159 #endif /* CONFIG_IXGBE_VXLAN */
7160 ixgbe_reset_subtask(adapter);
7161 ixgbe_phy_interrupt_subtask(adapter);
7162 ixgbe_sfp_detection_subtask(adapter);
7163 ixgbe_sfp_link_config_subtask(adapter);
7164 ixgbe_check_overtemp_subtask(adapter);
7165 ixgbe_watchdog_subtask(adapter);
7166 ixgbe_fdir_reinit_subtask(adapter);
7167 ixgbe_check_hang_subtask(adapter);
7168
7169 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
7170 ixgbe_ptp_overflow_check(adapter);
7171 ixgbe_ptp_rx_hang(adapter);
7172 }
7173
7174 ixgbe_service_event_complete(adapter);
7175 }
7176
7177 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
7178 struct ixgbe_tx_buffer *first,
7179 u8 *hdr_len)
7180 {
7181 struct sk_buff *skb = first->skb;
7182 u32 vlan_macip_lens, type_tucmd;
7183 u32 mss_l4len_idx, l4len;
7184 int err;
7185
7186 if (skb->ip_summed != CHECKSUM_PARTIAL)
7187 return 0;
7188
7189 if (!skb_is_gso(skb))
7190 return 0;
7191
7192 err = skb_cow_head(skb, 0);
7193 if (err < 0)
7194 return err;
7195
7196 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
7197 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7198
7199 if (first->protocol == htons(ETH_P_IP)) {
7200 struct iphdr *iph = ip_hdr(skb);
7201 iph->tot_len = 0;
7202 iph->check = 0;
7203 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7204 iph->daddr, 0,
7205 IPPROTO_TCP,
7206 0);
7207 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
7208 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7209 IXGBE_TX_FLAGS_CSUM |
7210 IXGBE_TX_FLAGS_IPV4;
7211 } else if (skb_is_gso_v6(skb)) {
7212 ipv6_hdr(skb)->payload_len = 0;
7213 tcp_hdr(skb)->check =
7214 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
7215 &ipv6_hdr(skb)->daddr,
7216 0, IPPROTO_TCP, 0);
7217 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7218 IXGBE_TX_FLAGS_CSUM;
7219 }
7220
7221 /* compute header lengths */
7222 l4len = tcp_hdrlen(skb);
7223 *hdr_len = skb_transport_offset(skb) + l4len;
7224
7225 /* update gso size and bytecount with header size */
7226 first->gso_segs = skb_shinfo(skb)->gso_segs;
7227 first->bytecount += (first->gso_segs - 1) * *hdr_len;
7228
7229 /* mss_l4len_id: use 0 as index for TSO */
7230 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
7231 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
7232
7233 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
7234 vlan_macip_lens = skb_network_header_len(skb);
7235 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
7236 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
7237
7238 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
7239 mss_l4len_idx);
7240
7241 return 1;
7242 }
7243
7244 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb)
7245 {
7246 unsigned int offset = 0;
7247
7248 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
7249
7250 return offset == skb_checksum_start_offset(skb);
7251 }
7252
7253 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
7254 struct ixgbe_tx_buffer *first)
7255 {
7256 struct sk_buff *skb = first->skb;
7257 u32 vlan_macip_lens = 0;
7258 u32 type_tucmd = 0;
7259
7260 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7261 csum_failed:
7262 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN |
7263 IXGBE_TX_FLAGS_CC)))
7264 return;
7265 goto no_csum;
7266 }
7267
7268 switch (skb->csum_offset) {
7269 case offsetof(struct tcphdr, check):
7270 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7271 /* fall through */
7272 case offsetof(struct udphdr, check):
7273 break;
7274 case offsetof(struct sctphdr, checksum):
7275 /* validate that this is actually an SCTP request */
7276 if (((first->protocol == htons(ETH_P_IP)) &&
7277 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
7278 ((first->protocol == htons(ETH_P_IPV6)) &&
7279 ixgbe_ipv6_csum_is_sctp(skb))) {
7280 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP;
7281 break;
7282 }
7283 /* fall through */
7284 default:
7285 skb_checksum_help(skb);
7286 goto csum_failed;
7287 }
7288
7289 /* update TX checksum flag */
7290 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7291 vlan_macip_lens = skb_checksum_start_offset(skb) -
7292 skb_network_offset(skb);
7293 no_csum:
7294 /* vlan_macip_lens: MACLEN, VLAN tag */
7295 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
7296 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
7297
7298 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 0);
7299 }
7300
7301 #define IXGBE_SET_FLAG(_input, _flag, _result) \
7302 ((_flag <= _result) ? \
7303 ((u32)(_input & _flag) * (_result / _flag)) : \
7304 ((u32)(_input & _flag) / (_flag / _result)))
7305
7306 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
7307 {
7308 /* set type for advanced descriptor with frame checksum insertion */
7309 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7310 IXGBE_ADVTXD_DCMD_DEXT |
7311 IXGBE_ADVTXD_DCMD_IFCS;
7312
7313 /* set HW vlan bit if vlan is present */
7314 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7315 IXGBE_ADVTXD_DCMD_VLE);
7316
7317 /* set segmentation enable bits for TSO/FSO */
7318 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7319 IXGBE_ADVTXD_DCMD_TSE);
7320
7321 /* set timestamp bit if present */
7322 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7323 IXGBE_ADVTXD_MAC_TSTAMP);
7324
7325 /* insert frame checksum */
7326 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
7327
7328 return cmd_type;
7329 }
7330
7331 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7332 u32 tx_flags, unsigned int paylen)
7333 {
7334 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
7335
7336 /* enable L4 checksum for TSO and TX checksum offload */
7337 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7338 IXGBE_TX_FLAGS_CSUM,
7339 IXGBE_ADVTXD_POPTS_TXSM);
7340
7341 /* enble IPv4 checksum for TSO */
7342 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7343 IXGBE_TX_FLAGS_IPV4,
7344 IXGBE_ADVTXD_POPTS_IXSM);
7345
7346 /*
7347 * Check Context must be set if Tx switch is enabled, which it
7348 * always is for case where virtual functions are running
7349 */
7350 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7351 IXGBE_TX_FLAGS_CC,
7352 IXGBE_ADVTXD_CC);
7353
7354 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
7355 }
7356
7357 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7358 {
7359 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7360
7361 /* Herbert's original patch had:
7362 * smp_mb__after_netif_stop_queue();
7363 * but since that doesn't exist yet, just open code it.
7364 */
7365 smp_mb();
7366
7367 /* We need to check again in a case another CPU has just
7368 * made room available.
7369 */
7370 if (likely(ixgbe_desc_unused(tx_ring) < size))
7371 return -EBUSY;
7372
7373 /* A reprieve! - use start_queue because it doesn't call schedule */
7374 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7375 ++tx_ring->tx_stats.restart_queue;
7376 return 0;
7377 }
7378
7379 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7380 {
7381 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7382 return 0;
7383
7384 return __ixgbe_maybe_stop_tx(tx_ring, size);
7385 }
7386
7387 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7388 IXGBE_TXD_CMD_RS)
7389
7390 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
7391 struct ixgbe_tx_buffer *first,
7392 const u8 hdr_len)
7393 {
7394 struct sk_buff *skb = first->skb;
7395 struct ixgbe_tx_buffer *tx_buffer;
7396 union ixgbe_adv_tx_desc *tx_desc;
7397 struct skb_frag_struct *frag;
7398 dma_addr_t dma;
7399 unsigned int data_len, size;
7400 u32 tx_flags = first->tx_flags;
7401 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
7402 u16 i = tx_ring->next_to_use;
7403
7404 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7405
7406 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7407
7408 size = skb_headlen(skb);
7409 data_len = skb->data_len;
7410
7411 #ifdef IXGBE_FCOE
7412 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
7413 if (data_len < sizeof(struct fcoe_crc_eof)) {
7414 size -= sizeof(struct fcoe_crc_eof) - data_len;
7415 data_len = 0;
7416 } else {
7417 data_len -= sizeof(struct fcoe_crc_eof);
7418 }
7419 }
7420
7421 #endif
7422 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
7423
7424 tx_buffer = first;
7425
7426 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7427 if (dma_mapping_error(tx_ring->dev, dma))
7428 goto dma_error;
7429
7430 /* record length, and DMA address */
7431 dma_unmap_len_set(tx_buffer, len, size);
7432 dma_unmap_addr_set(tx_buffer, dma, dma);
7433
7434 tx_desc->read.buffer_addr = cpu_to_le64(dma);
7435
7436 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
7437 tx_desc->read.cmd_type_len =
7438 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
7439
7440 i++;
7441 tx_desc++;
7442 if (i == tx_ring->count) {
7443 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7444 i = 0;
7445 }
7446 tx_desc->read.olinfo_status = 0;
7447
7448 dma += IXGBE_MAX_DATA_PER_TXD;
7449 size -= IXGBE_MAX_DATA_PER_TXD;
7450
7451 tx_desc->read.buffer_addr = cpu_to_le64(dma);
7452 }
7453
7454 if (likely(!data_len))
7455 break;
7456
7457 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
7458
7459 i++;
7460 tx_desc++;
7461 if (i == tx_ring->count) {
7462 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7463 i = 0;
7464 }
7465 tx_desc->read.olinfo_status = 0;
7466
7467 #ifdef IXGBE_FCOE
7468 size = min_t(unsigned int, data_len, skb_frag_size(frag));
7469 #else
7470 size = skb_frag_size(frag);
7471 #endif
7472 data_len -= size;
7473
7474 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7475 DMA_TO_DEVICE);
7476
7477 tx_buffer = &tx_ring->tx_buffer_info[i];
7478 }
7479
7480 /* write last descriptor with RS and EOP bits */
7481 cmd_type |= size | IXGBE_TXD_CMD;
7482 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
7483
7484 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
7485
7486 /* set the timestamp */
7487 first->time_stamp = jiffies;
7488
7489 /*
7490 * Force memory writes to complete before letting h/w know there
7491 * are new descriptors to fetch. (Only applicable for weak-ordered
7492 * memory model archs, such as IA-64).
7493 *
7494 * We also need this memory barrier to make certain all of the
7495 * status bits have been updated before next_to_watch is written.
7496 */
7497 wmb();
7498
7499 /* set next_to_watch value indicating a packet is present */
7500 first->next_to_watch = tx_desc;
7501
7502 i++;
7503 if (i == tx_ring->count)
7504 i = 0;
7505
7506 tx_ring->next_to_use = i;
7507
7508 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7509
7510 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
7511 writel(i, tx_ring->tail);
7512
7513 /* we need this if more than one processor can write to our tail
7514 * at a time, it synchronizes IO on IA64/Altix systems
7515 */
7516 mmiowb();
7517 }
7518
7519 return;
7520 dma_error:
7521 dev_err(tx_ring->dev, "TX DMA map failed\n");
7522
7523 /* clear dma mappings for failed tx_buffer_info map */
7524 for (;;) {
7525 tx_buffer = &tx_ring->tx_buffer_info[i];
7526 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7527 if (tx_buffer == first)
7528 break;
7529 if (i == 0)
7530 i = tx_ring->count;
7531 i--;
7532 }
7533
7534 tx_ring->next_to_use = i;
7535 }
7536
7537 static void ixgbe_atr(struct ixgbe_ring *ring,
7538 struct ixgbe_tx_buffer *first)
7539 {
7540 struct ixgbe_q_vector *q_vector = ring->q_vector;
7541 union ixgbe_atr_hash_dword input = { .dword = 0 };
7542 union ixgbe_atr_hash_dword common = { .dword = 0 };
7543 union {
7544 unsigned char *network;
7545 struct iphdr *ipv4;
7546 struct ipv6hdr *ipv6;
7547 } hdr;
7548 struct tcphdr *th;
7549 unsigned int hlen;
7550 struct sk_buff *skb;
7551 __be16 vlan_id;
7552 int l4_proto;
7553
7554 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7555 if (!q_vector)
7556 return;
7557
7558 /* do nothing if sampling is disabled */
7559 if (!ring->atr_sample_rate)
7560 return;
7561
7562 ring->atr_count++;
7563
7564 /* currently only IPv4/IPv6 with TCP is supported */
7565 if ((first->protocol != htons(ETH_P_IP)) &&
7566 (first->protocol != htons(ETH_P_IPV6)))
7567 return;
7568
7569 /* snag network header to get L4 type and address */
7570 skb = first->skb;
7571 hdr.network = skb_network_header(skb);
7572 #ifdef CONFIG_IXGBE_VXLAN
7573 if (skb->encapsulation &&
7574 first->protocol == htons(ETH_P_IP) &&
7575 hdr.ipv4->protocol != IPPROTO_UDP) {
7576 struct ixgbe_adapter *adapter = q_vector->adapter;
7577
7578 /* verify the port is recognized as VXLAN */
7579 if (adapter->vxlan_port &&
7580 udp_hdr(skb)->dest == adapter->vxlan_port)
7581 hdr.network = skb_inner_network_header(skb);
7582 }
7583 #endif /* CONFIG_IXGBE_VXLAN */
7584
7585 /* Currently only IPv4/IPv6 with TCP is supported */
7586 switch (hdr.ipv4->version) {
7587 case IPVERSION:
7588 /* access ihl as u8 to avoid unaligned access on ia64 */
7589 hlen = (hdr.network[0] & 0x0F) << 2;
7590 l4_proto = hdr.ipv4->protocol;
7591 break;
7592 case 6:
7593 hlen = hdr.network - skb->data;
7594 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL);
7595 hlen -= hdr.network - skb->data;
7596 break;
7597 default:
7598 return;
7599 }
7600
7601 if (l4_proto != IPPROTO_TCP)
7602 return;
7603
7604 th = (struct tcphdr *)(hdr.network + hlen);
7605
7606 /* skip this packet since the socket is closing */
7607 if (th->fin)
7608 return;
7609
7610 /* sample on all syn packets or once every atr sample count */
7611 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7612 return;
7613
7614 /* reset sample count */
7615 ring->atr_count = 0;
7616
7617 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
7618
7619 /*
7620 * src and dst are inverted, think how the receiver sees them
7621 *
7622 * The input is broken into two sections, a non-compressed section
7623 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7624 * is XORed together and stored in the compressed dword.
7625 */
7626 input.formatted.vlan_id = vlan_id;
7627
7628 /*
7629 * since src port and flex bytes occupy the same word XOR them together
7630 * and write the value to source port portion of compressed dword
7631 */
7632 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
7633 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
7634 else
7635 common.port.src ^= th->dest ^ first->protocol;
7636 common.port.dst ^= th->source;
7637
7638 switch (hdr.ipv4->version) {
7639 case IPVERSION:
7640 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7641 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7642 break;
7643 case 6:
7644 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7645 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7646 hdr.ipv6->saddr.s6_addr32[1] ^
7647 hdr.ipv6->saddr.s6_addr32[2] ^
7648 hdr.ipv6->saddr.s6_addr32[3] ^
7649 hdr.ipv6->daddr.s6_addr32[0] ^
7650 hdr.ipv6->daddr.s6_addr32[1] ^
7651 hdr.ipv6->daddr.s6_addr32[2] ^
7652 hdr.ipv6->daddr.s6_addr32[3];
7653 break;
7654 default:
7655 break;
7656 }
7657
7658 if (hdr.network != skb_network_header(skb))
7659 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
7660
7661 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
7662 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7663 input, common, ring->queue_index);
7664 }
7665
7666 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
7667 void *accel_priv, select_queue_fallback_t fallback)
7668 {
7669 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7670 #ifdef IXGBE_FCOE
7671 struct ixgbe_adapter *adapter;
7672 struct ixgbe_ring_feature *f;
7673 int txq;
7674 #endif
7675
7676 if (fwd_adapter)
7677 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7678
7679 #ifdef IXGBE_FCOE
7680
7681 /*
7682 * only execute the code below if protocol is FCoE
7683 * or FIP and we have FCoE enabled on the adapter
7684 */
7685 switch (vlan_get_protocol(skb)) {
7686 case htons(ETH_P_FCOE):
7687 case htons(ETH_P_FIP):
7688 adapter = netdev_priv(dev);
7689
7690 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7691 break;
7692 default:
7693 return fallback(dev, skb);
7694 }
7695
7696 f = &adapter->ring_feature[RING_F_FCOE];
7697
7698 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7699 smp_processor_id();
7700
7701 while (txq >= f->indices)
7702 txq -= f->indices;
7703
7704 return txq + f->offset;
7705 #else
7706 return fallback(dev, skb);
7707 #endif
7708 }
7709
7710 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
7711 struct ixgbe_adapter *adapter,
7712 struct ixgbe_ring *tx_ring)
7713 {
7714 struct ixgbe_tx_buffer *first;
7715 int tso;
7716 u32 tx_flags = 0;
7717 unsigned short f;
7718 u16 count = TXD_USE_COUNT(skb_headlen(skb));
7719 __be16 protocol = skb->protocol;
7720 u8 hdr_len = 0;
7721
7722 /*
7723 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
7724 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
7725 * + 2 desc gap to keep tail from touching head,
7726 * + 1 desc for context descriptor,
7727 * otherwise try next time
7728 */
7729 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7730 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7731
7732 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7733 tx_ring->tx_stats.tx_busy++;
7734 return NETDEV_TX_BUSY;
7735 }
7736
7737 /* record the location of the first descriptor for this packet */
7738 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7739 first->skb = skb;
7740 first->bytecount = skb->len;
7741 first->gso_segs = 1;
7742
7743 /* if we have a HW VLAN tag being added default to the HW one */
7744 if (skb_vlan_tag_present(skb)) {
7745 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7746 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7747 /* else if it is a SW VLAN check the next protocol and store the tag */
7748 } else if (protocol == htons(ETH_P_8021Q)) {
7749 struct vlan_hdr *vhdr, _vhdr;
7750 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7751 if (!vhdr)
7752 goto out_drop;
7753
7754 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7755 IXGBE_TX_FLAGS_VLAN_SHIFT;
7756 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7757 }
7758 protocol = vlan_get_protocol(skb);
7759
7760 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7761 adapter->ptp_clock &&
7762 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7763 &adapter->state)) {
7764 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7765 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
7766
7767 /* schedule check for Tx timestamp */
7768 adapter->ptp_tx_skb = skb_get(skb);
7769 adapter->ptp_tx_start = jiffies;
7770 schedule_work(&adapter->ptp_tx_work);
7771 }
7772
7773 skb_tx_timestamp(skb);
7774
7775 #ifdef CONFIG_PCI_IOV
7776 /*
7777 * Use the l2switch_enable flag - would be false if the DMA
7778 * Tx switch had been disabled.
7779 */
7780 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7781 tx_flags |= IXGBE_TX_FLAGS_CC;
7782
7783 #endif
7784 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
7785 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7786 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7787 (skb->priority != TC_PRIO_CONTROL))) {
7788 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
7789 tx_flags |= (skb->priority & 0x7) <<
7790 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
7791 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7792 struct vlan_ethhdr *vhdr;
7793
7794 if (skb_cow_head(skb, 0))
7795 goto out_drop;
7796 vhdr = (struct vlan_ethhdr *)skb->data;
7797 vhdr->h_vlan_TCI = htons(tx_flags >>
7798 IXGBE_TX_FLAGS_VLAN_SHIFT);
7799 } else {
7800 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7801 }
7802 }
7803
7804 /* record initial flags and protocol */
7805 first->tx_flags = tx_flags;
7806 first->protocol = protocol;
7807
7808 #ifdef IXGBE_FCOE
7809 /* setup tx offload for FCoE */
7810 if ((protocol == htons(ETH_P_FCOE)) &&
7811 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
7812 tso = ixgbe_fso(tx_ring, first, &hdr_len);
7813 if (tso < 0)
7814 goto out_drop;
7815
7816 goto xmit_fcoe;
7817 }
7818
7819 #endif /* IXGBE_FCOE */
7820 tso = ixgbe_tso(tx_ring, first, &hdr_len);
7821 if (tso < 0)
7822 goto out_drop;
7823 else if (!tso)
7824 ixgbe_tx_csum(tx_ring, first);
7825
7826 /* add the ATR filter if ATR is on */
7827 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7828 ixgbe_atr(tx_ring, first);
7829
7830 #ifdef IXGBE_FCOE
7831 xmit_fcoe:
7832 #endif /* IXGBE_FCOE */
7833 ixgbe_tx_map(tx_ring, first, hdr_len);
7834
7835 return NETDEV_TX_OK;
7836
7837 out_drop:
7838 dev_kfree_skb_any(first->skb);
7839 first->skb = NULL;
7840
7841 return NETDEV_TX_OK;
7842 }
7843
7844 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7845 struct net_device *netdev,
7846 struct ixgbe_ring *ring)
7847 {
7848 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7849 struct ixgbe_ring *tx_ring;
7850
7851 /*
7852 * The minimum packet size for olinfo paylen is 17 so pad the skb
7853 * in order to meet this minimum size requirement.
7854 */
7855 if (skb_put_padto(skb, 17))
7856 return NETDEV_TX_OK;
7857
7858 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7859
7860 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
7861 }
7862
7863 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7864 struct net_device *netdev)
7865 {
7866 return __ixgbe_xmit_frame(skb, netdev, NULL);
7867 }
7868
7869 /**
7870 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7871 * @netdev: network interface device structure
7872 * @p: pointer to an address structure
7873 *
7874 * Returns 0 on success, negative on failure
7875 **/
7876 static int ixgbe_set_mac(struct net_device *netdev, void *p)
7877 {
7878 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7879 struct ixgbe_hw *hw = &adapter->hw;
7880 struct sockaddr *addr = p;
7881
7882 if (!is_valid_ether_addr(addr->sa_data))
7883 return -EADDRNOTAVAIL;
7884
7885 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
7886 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
7887
7888 ixgbe_mac_set_default_filter(adapter);
7889
7890 return 0;
7891 }
7892
7893 static int
7894 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7895 {
7896 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7897 struct ixgbe_hw *hw = &adapter->hw;
7898 u16 value;
7899 int rc;
7900
7901 if (prtad != hw->phy.mdio.prtad)
7902 return -EINVAL;
7903 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7904 if (!rc)
7905 rc = value;
7906 return rc;
7907 }
7908
7909 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7910 u16 addr, u16 value)
7911 {
7912 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7913 struct ixgbe_hw *hw = &adapter->hw;
7914
7915 if (prtad != hw->phy.mdio.prtad)
7916 return -EINVAL;
7917 return hw->phy.ops.write_reg(hw, addr, devad, value);
7918 }
7919
7920 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7921 {
7922 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7923
7924 switch (cmd) {
7925 case SIOCSHWTSTAMP:
7926 return ixgbe_ptp_set_ts_config(adapter, req);
7927 case SIOCGHWTSTAMP:
7928 return ixgbe_ptp_get_ts_config(adapter, req);
7929 default:
7930 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7931 }
7932 }
7933
7934 /**
7935 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
7936 * netdev->dev_addrs
7937 * @netdev: network interface device structure
7938 *
7939 * Returns non-zero on failure
7940 **/
7941 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7942 {
7943 int err = 0;
7944 struct ixgbe_adapter *adapter = netdev_priv(dev);
7945 struct ixgbe_hw *hw = &adapter->hw;
7946
7947 if (is_valid_ether_addr(hw->mac.san_addr)) {
7948 rtnl_lock();
7949 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
7950 rtnl_unlock();
7951
7952 /* update SAN MAC vmdq pool selection */
7953 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
7954 }
7955 return err;
7956 }
7957
7958 /**
7959 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7960 * netdev->dev_addrs
7961 * @netdev: network interface device structure
7962 *
7963 * Returns non-zero on failure
7964 **/
7965 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7966 {
7967 int err = 0;
7968 struct ixgbe_adapter *adapter = netdev_priv(dev);
7969 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7970
7971 if (is_valid_ether_addr(mac->san_addr)) {
7972 rtnl_lock();
7973 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7974 rtnl_unlock();
7975 }
7976 return err;
7977 }
7978
7979 #ifdef CONFIG_NET_POLL_CONTROLLER
7980 /*
7981 * Polling 'interrupt' - used by things like netconsole to send skbs
7982 * without having to re-enable interrupts. It's not called while
7983 * the interrupt routine is executing.
7984 */
7985 static void ixgbe_netpoll(struct net_device *netdev)
7986 {
7987 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7988 int i;
7989
7990 /* if interface is down do nothing */
7991 if (test_bit(__IXGBE_DOWN, &adapter->state))
7992 return;
7993
7994 /* loop through and schedule all active queues */
7995 for (i = 0; i < adapter->num_q_vectors; i++)
7996 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
7997 }
7998
7999 #endif
8000 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
8001 struct rtnl_link_stats64 *stats)
8002 {
8003 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8004 int i;
8005
8006 rcu_read_lock();
8007 for (i = 0; i < adapter->num_rx_queues; i++) {
8008 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
8009 u64 bytes, packets;
8010 unsigned int start;
8011
8012 if (ring) {
8013 do {
8014 start = u64_stats_fetch_begin_irq(&ring->syncp);
8015 packets = ring->stats.packets;
8016 bytes = ring->stats.bytes;
8017 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
8018 stats->rx_packets += packets;
8019 stats->rx_bytes += bytes;
8020 }
8021 }
8022
8023 for (i = 0; i < adapter->num_tx_queues; i++) {
8024 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
8025 u64 bytes, packets;
8026 unsigned int start;
8027
8028 if (ring) {
8029 do {
8030 start = u64_stats_fetch_begin_irq(&ring->syncp);
8031 packets = ring->stats.packets;
8032 bytes = ring->stats.bytes;
8033 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
8034 stats->tx_packets += packets;
8035 stats->tx_bytes += bytes;
8036 }
8037 }
8038 rcu_read_unlock();
8039 /* following stats updated by ixgbe_watchdog_task() */
8040 stats->multicast = netdev->stats.multicast;
8041 stats->rx_errors = netdev->stats.rx_errors;
8042 stats->rx_length_errors = netdev->stats.rx_length_errors;
8043 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
8044 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
8045 return stats;
8046 }
8047
8048 #ifdef CONFIG_IXGBE_DCB
8049 /**
8050 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
8051 * @adapter: pointer to ixgbe_adapter
8052 * @tc: number of traffic classes currently enabled
8053 *
8054 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
8055 * 802.1Q priority maps to a packet buffer that exists.
8056 */
8057 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
8058 {
8059 struct ixgbe_hw *hw = &adapter->hw;
8060 u32 reg, rsave;
8061 int i;
8062
8063 /* 82598 have a static priority to TC mapping that can not
8064 * be changed so no validation is needed.
8065 */
8066 if (hw->mac.type == ixgbe_mac_82598EB)
8067 return;
8068
8069 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
8070 rsave = reg;
8071
8072 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
8073 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
8074
8075 /* If up2tc is out of bounds default to zero */
8076 if (up2tc > tc)
8077 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
8078 }
8079
8080 if (reg != rsave)
8081 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
8082
8083 return;
8084 }
8085
8086 /**
8087 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
8088 * @adapter: Pointer to adapter struct
8089 *
8090 * Populate the netdev user priority to tc map
8091 */
8092 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
8093 {
8094 struct net_device *dev = adapter->netdev;
8095 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
8096 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
8097 u8 prio;
8098
8099 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
8100 u8 tc = 0;
8101
8102 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
8103 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
8104 else if (ets)
8105 tc = ets->prio_tc[prio];
8106
8107 netdev_set_prio_tc_map(dev, prio, tc);
8108 }
8109 }
8110
8111 #endif /* CONFIG_IXGBE_DCB */
8112 /**
8113 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8114 *
8115 * @netdev: net device to configure
8116 * @tc: number of traffic classes to enable
8117 */
8118 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
8119 {
8120 struct ixgbe_adapter *adapter = netdev_priv(dev);
8121 struct ixgbe_hw *hw = &adapter->hw;
8122 bool pools;
8123
8124 /* Hardware supports up to 8 traffic classes */
8125 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
8126 return -EINVAL;
8127
8128 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
8129 return -EINVAL;
8130
8131 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
8132 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
8133 return -EBUSY;
8134
8135 /* Hardware has to reinitialize queues and interrupts to
8136 * match packet buffer alignment. Unfortunately, the
8137 * hardware is not flexible enough to do this dynamically.
8138 */
8139 if (netif_running(dev))
8140 ixgbe_close(dev);
8141 else
8142 ixgbe_reset(adapter);
8143
8144 ixgbe_clear_interrupt_scheme(adapter);
8145
8146 #ifdef CONFIG_IXGBE_DCB
8147 if (tc) {
8148 netdev_set_num_tc(dev, tc);
8149 ixgbe_set_prio_tc_map(adapter);
8150
8151 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
8152
8153 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
8154 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
8155 adapter->hw.fc.requested_mode = ixgbe_fc_none;
8156 }
8157 } else {
8158 netdev_reset_tc(dev);
8159
8160 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8161 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
8162
8163 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
8164
8165 adapter->temp_dcb_cfg.pfc_mode_enable = false;
8166 adapter->dcb_cfg.pfc_mode_enable = false;
8167 }
8168
8169 ixgbe_validate_rtr(adapter, tc);
8170
8171 #endif /* CONFIG_IXGBE_DCB */
8172 ixgbe_init_interrupt_scheme(adapter);
8173
8174 if (netif_running(dev))
8175 return ixgbe_open(dev);
8176
8177 return 0;
8178 }
8179
8180 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter,
8181 struct tc_cls_u32_offload *cls)
8182 {
8183 u32 uhtid = TC_U32_USERHTID(cls->knode.handle);
8184 u32 loc;
8185 int err;
8186
8187 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE))
8188 return -EINVAL;
8189
8190 loc = cls->knode.handle & 0xfffff;
8191
8192 spin_lock(&adapter->fdir_perfect_lock);
8193 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc);
8194 spin_unlock(&adapter->fdir_perfect_lock);
8195 return err;
8196 }
8197
8198 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter,
8199 __be16 protocol,
8200 struct tc_cls_u32_offload *cls)
8201 {
8202 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
8203
8204 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8205 return -EINVAL;
8206
8207 /* This ixgbe devices do not support hash tables at the moment
8208 * so abort when given hash tables.
8209 */
8210 if (cls->hnode.divisor > 0)
8211 return -EINVAL;
8212
8213 set_bit(uhtid - 1, &adapter->tables);
8214 return 0;
8215 }
8216
8217 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter,
8218 struct tc_cls_u32_offload *cls)
8219 {
8220 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
8221
8222 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8223 return -EINVAL;
8224
8225 clear_bit(uhtid - 1, &adapter->tables);
8226 return 0;
8227 }
8228
8229 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter,
8230 __be16 protocol,
8231 struct tc_cls_u32_offload *cls)
8232 {
8233 u32 loc = cls->knode.handle & 0xfffff;
8234 struct ixgbe_hw *hw = &adapter->hw;
8235 struct ixgbe_mat_field *field_ptr;
8236 struct ixgbe_fdir_filter *input;
8237 union ixgbe_atr_input mask;
8238 #ifdef CONFIG_NET_CLS_ACT
8239 const struct tc_action *a;
8240 #endif
8241 int i, err = 0;
8242 u8 queue;
8243 u32 uhtid, link_uhtid;
8244
8245 memset(&mask, 0, sizeof(union ixgbe_atr_input));
8246 uhtid = TC_U32_USERHTID(cls->knode.handle);
8247 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle);
8248
8249 /* At the moment cls_u32 jumps to network layer and skips past
8250 * L2 headers. The canonical method to match L2 frames is to use
8251 * negative values. However this is error prone at best but really
8252 * just broken because there is no way to "know" what sort of hdr
8253 * is in front of the network layer. Fix cls_u32 to support L2
8254 * headers when needed.
8255 */
8256 if (protocol != htons(ETH_P_IP))
8257 return -EINVAL;
8258
8259 if (link_uhtid) {
8260 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps;
8261
8262 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE)
8263 return -EINVAL;
8264
8265 if (!test_bit(link_uhtid - 1, &adapter->tables))
8266 return -EINVAL;
8267
8268 for (i = 0; nexthdr[i].jump; i++) {
8269 if (nexthdr[i].o != cls->knode.sel->offoff ||
8270 nexthdr[i].s != cls->knode.sel->offshift ||
8271 nexthdr[i].m != cls->knode.sel->offmask ||
8272 /* do not support multiple key jumps its just mad */
8273 cls->knode.sel->nkeys > 1)
8274 return -EINVAL;
8275
8276 if (nexthdr[i].off == cls->knode.sel->keys[0].off &&
8277 nexthdr[i].val == cls->knode.sel->keys[0].val &&
8278 nexthdr[i].mask == cls->knode.sel->keys[0].mask) {
8279 adapter->jump_tables[link_uhtid] =
8280 nexthdr[i].jump;
8281 break;
8282 }
8283 }
8284 return 0;
8285 }
8286
8287 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) {
8288 e_err(drv, "Location out of range\n");
8289 return -EINVAL;
8290 }
8291
8292 /* cls u32 is a graph starting at root node 0x800. The driver tracks
8293 * links and also the fields used to advance the parser across each
8294 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map
8295 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h
8296 * To add support for new nodes update ixgbe_model.h parse structures
8297 * this function _should_ be generic try not to hardcode values here.
8298 */
8299 if (uhtid == 0x800) {
8300 field_ptr = adapter->jump_tables[0];
8301 } else {
8302 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8303 return -EINVAL;
8304
8305 field_ptr = adapter->jump_tables[uhtid];
8306 }
8307
8308 if (!field_ptr)
8309 return -EINVAL;
8310
8311 input = kzalloc(sizeof(*input), GFP_KERNEL);
8312 if (!input)
8313 return -ENOMEM;
8314
8315 for (i = 0; i < cls->knode.sel->nkeys; i++) {
8316 int off = cls->knode.sel->keys[i].off;
8317 __be32 val = cls->knode.sel->keys[i].val;
8318 __be32 m = cls->knode.sel->keys[i].mask;
8319 bool found_entry = false;
8320 int j;
8321
8322 for (j = 0; field_ptr[j].val; j++) {
8323 if (field_ptr[j].off == off) {
8324 field_ptr[j].val(input, &mask, val, m);
8325 input->filter.formatted.flow_type |=
8326 field_ptr[j].type;
8327 found_entry = true;
8328 break;
8329 }
8330 }
8331
8332 if (!found_entry)
8333 goto err_out;
8334 }
8335
8336 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
8337 IXGBE_ATR_L4TYPE_MASK;
8338
8339 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
8340 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
8341
8342 #ifdef CONFIG_NET_CLS_ACT
8343 if (list_empty(&cls->knode.exts->actions))
8344 goto err_out;
8345
8346 list_for_each_entry(a, &cls->knode.exts->actions, list) {
8347 if (!is_tcf_gact_shot(a))
8348 goto err_out;
8349 }
8350 #endif
8351
8352 input->action = IXGBE_FDIR_DROP_QUEUE;
8353 queue = IXGBE_FDIR_DROP_QUEUE;
8354 input->sw_idx = loc;
8355
8356 spin_lock(&adapter->fdir_perfect_lock);
8357
8358 if (hlist_empty(&adapter->fdir_filter_list)) {
8359 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
8360 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
8361 if (err)
8362 goto err_out_w_lock;
8363 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
8364 err = -EINVAL;
8365 goto err_out_w_lock;
8366 }
8367
8368 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
8369 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter,
8370 input->sw_idx, queue);
8371 if (!err)
8372 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
8373 spin_unlock(&adapter->fdir_perfect_lock);
8374
8375 return err;
8376 err_out_w_lock:
8377 spin_unlock(&adapter->fdir_perfect_lock);
8378 err_out:
8379 kfree(input);
8380 return -EINVAL;
8381 }
8382
8383 static int __ixgbe_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
8384 struct tc_to_netdev *tc)
8385 {
8386 struct ixgbe_adapter *adapter = netdev_priv(dev);
8387
8388 if (TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS) &&
8389 tc->type == TC_SETUP_CLSU32) {
8390 switch (tc->cls_u32->command) {
8391 case TC_CLSU32_NEW_KNODE:
8392 case TC_CLSU32_REPLACE_KNODE:
8393 return ixgbe_configure_clsu32(adapter,
8394 proto, tc->cls_u32);
8395 case TC_CLSU32_DELETE_KNODE:
8396 return ixgbe_delete_clsu32(adapter, tc->cls_u32);
8397 case TC_CLSU32_NEW_HNODE:
8398 case TC_CLSU32_REPLACE_HNODE:
8399 return ixgbe_configure_clsu32_add_hnode(adapter, proto,
8400 tc->cls_u32);
8401 case TC_CLSU32_DELETE_HNODE:
8402 return ixgbe_configure_clsu32_del_hnode(adapter,
8403 tc->cls_u32);
8404 default:
8405 return -EINVAL;
8406 }
8407 }
8408
8409 if (tc->type != TC_SETUP_MQPRIO)
8410 return -EINVAL;
8411
8412 return ixgbe_setup_tc(dev, tc->tc);
8413 }
8414
8415 #ifdef CONFIG_PCI_IOV
8416 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
8417 {
8418 struct net_device *netdev = adapter->netdev;
8419
8420 rtnl_lock();
8421 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
8422 rtnl_unlock();
8423 }
8424
8425 #endif
8426 void ixgbe_do_reset(struct net_device *netdev)
8427 {
8428 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8429
8430 if (netif_running(netdev))
8431 ixgbe_reinit_locked(adapter);
8432 else
8433 ixgbe_reset(adapter);
8434 }
8435
8436 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
8437 netdev_features_t features)
8438 {
8439 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8440
8441 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
8442 if (!(features & NETIF_F_RXCSUM))
8443 features &= ~NETIF_F_LRO;
8444
8445 /* Turn off LRO if not RSC capable */
8446 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
8447 features &= ~NETIF_F_LRO;
8448
8449 return features;
8450 }
8451
8452 static int ixgbe_set_features(struct net_device *netdev,
8453 netdev_features_t features)
8454 {
8455 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8456 netdev_features_t changed = netdev->features ^ features;
8457 bool need_reset = false;
8458
8459 /* Make sure RSC matches LRO, reset if change */
8460 if (!(features & NETIF_F_LRO)) {
8461 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
8462 need_reset = true;
8463 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
8464 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
8465 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
8466 if (adapter->rx_itr_setting == 1 ||
8467 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
8468 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8469 need_reset = true;
8470 } else if ((changed ^ features) & NETIF_F_LRO) {
8471 e_info(probe, "rx-usecs set too low, "
8472 "disabling RSC\n");
8473 }
8474 }
8475
8476 /*
8477 * Check if Flow Director n-tuple support or hw_tc support was
8478 * enabled or disabled. If the state changed, we need to reset.
8479 */
8480 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) {
8481 /* turn off ATR, enable perfect filters and reset */
8482 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
8483 need_reset = true;
8484
8485 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
8486 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8487 } else {
8488 /* turn off perfect filters, enable ATR and reset */
8489 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
8490 need_reset = true;
8491
8492 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8493
8494 /* We cannot enable ATR if SR-IOV is enabled */
8495 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED ||
8496 /* We cannot enable ATR if we have 2 or more tcs */
8497 (netdev_get_num_tc(netdev) > 1) ||
8498 /* We cannot enable ATR if RSS is disabled */
8499 (adapter->ring_feature[RING_F_RSS].limit <= 1) ||
8500 /* A sample rate of 0 indicates ATR disabled */
8501 (!adapter->atr_sample_rate))
8502 ; /* do nothing not supported */
8503 else /* otherwise supported and set the flag */
8504 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
8505 }
8506
8507 if (changed & NETIF_F_RXALL)
8508 need_reset = true;
8509
8510 netdev->features = features;
8511
8512 #ifdef CONFIG_IXGBE_VXLAN
8513 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
8514 if (features & NETIF_F_RXCSUM)
8515 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8516 else
8517 ixgbe_clear_vxlan_port(adapter);
8518 }
8519 #endif /* CONFIG_IXGBE_VXLAN */
8520
8521 if (need_reset)
8522 ixgbe_do_reset(netdev);
8523 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX |
8524 NETIF_F_HW_VLAN_CTAG_FILTER))
8525 ixgbe_set_rx_mode(netdev);
8526
8527 return 0;
8528 }
8529
8530 #ifdef CONFIG_IXGBE_VXLAN
8531 /**
8532 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up
8533 * @dev: The port's netdev
8534 * @sa_family: Socket Family that VXLAN is notifiying us about
8535 * @port: New UDP port number that VXLAN started listening to
8536 **/
8537 static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8538 __be16 port)
8539 {
8540 struct ixgbe_adapter *adapter = netdev_priv(dev);
8541 struct ixgbe_hw *hw = &adapter->hw;
8542
8543 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8544 return;
8545
8546 if (sa_family == AF_INET6)
8547 return;
8548
8549 if (adapter->vxlan_port == port)
8550 return;
8551
8552 if (adapter->vxlan_port) {
8553 netdev_info(dev,
8554 "Hit Max num of VXLAN ports, not adding port %d\n",
8555 ntohs(port));
8556 return;
8557 }
8558
8559 adapter->vxlan_port = port;
8560 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, ntohs(port));
8561 }
8562
8563 /**
8564 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away
8565 * @dev: The port's netdev
8566 * @sa_family: Socket Family that VXLAN is notifying us about
8567 * @port: UDP port number that VXLAN stopped listening to
8568 **/
8569 static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8570 __be16 port)
8571 {
8572 struct ixgbe_adapter *adapter = netdev_priv(dev);
8573
8574 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8575 return;
8576
8577 if (sa_family == AF_INET6)
8578 return;
8579
8580 if (adapter->vxlan_port != port) {
8581 netdev_info(dev, "Port %d was not found, not deleting\n",
8582 ntohs(port));
8583 return;
8584 }
8585
8586 ixgbe_clear_vxlan_port(adapter);
8587 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8588 }
8589 #endif /* CONFIG_IXGBE_VXLAN */
8590
8591 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8592 struct net_device *dev,
8593 const unsigned char *addr, u16 vid,
8594 u16 flags)
8595 {
8596 /* guarantee we can provide a unique filter for the unicast address */
8597 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
8598 struct ixgbe_adapter *adapter = netdev_priv(dev);
8599 u16 pool = VMDQ_P(0);
8600
8601 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool))
8602 return -ENOMEM;
8603 }
8604
8605 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
8606 }
8607
8608 /**
8609 * ixgbe_configure_bridge_mode - set various bridge modes
8610 * @adapter - the private structure
8611 * @mode - requested bridge mode
8612 *
8613 * Configure some settings require for various bridge modes.
8614 **/
8615 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
8616 __u16 mode)
8617 {
8618 struct ixgbe_hw *hw = &adapter->hw;
8619 unsigned int p, num_pools;
8620 u32 vmdctl;
8621
8622 switch (mode) {
8623 case BRIDGE_MODE_VEPA:
8624 /* disable Tx loopback, rely on switch hairpin mode */
8625 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
8626
8627 /* must enable Rx switching replication to allow multicast
8628 * packet reception on all VFs, and to enable source address
8629 * pruning.
8630 */
8631 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8632 vmdctl |= IXGBE_VT_CTL_REPLEN;
8633 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8634
8635 /* enable Rx source address pruning. Note, this requires
8636 * replication to be enabled or else it does nothing.
8637 */
8638 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8639 for (p = 0; p < num_pools; p++) {
8640 if (hw->mac.ops.set_source_address_pruning)
8641 hw->mac.ops.set_source_address_pruning(hw,
8642 true,
8643 p);
8644 }
8645 break;
8646 case BRIDGE_MODE_VEB:
8647 /* enable Tx loopback for internal VF/PF communication */
8648 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
8649 IXGBE_PFDTXGSWC_VT_LBEN);
8650
8651 /* disable Rx switching replication unless we have SR-IOV
8652 * virtual functions
8653 */
8654 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8655 if (!adapter->num_vfs)
8656 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
8657 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8658
8659 /* disable Rx source address pruning, since we don't expect to
8660 * be receiving external loopback of our transmitted frames.
8661 */
8662 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8663 for (p = 0; p < num_pools; p++) {
8664 if (hw->mac.ops.set_source_address_pruning)
8665 hw->mac.ops.set_source_address_pruning(hw,
8666 false,
8667 p);
8668 }
8669 break;
8670 default:
8671 return -EINVAL;
8672 }
8673
8674 adapter->bridge_mode = mode;
8675
8676 e_info(drv, "enabling bridge mode: %s\n",
8677 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
8678
8679 return 0;
8680 }
8681
8682 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
8683 struct nlmsghdr *nlh, u16 flags)
8684 {
8685 struct ixgbe_adapter *adapter = netdev_priv(dev);
8686 struct nlattr *attr, *br_spec;
8687 int rem;
8688
8689 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8690 return -EOPNOTSUPP;
8691
8692 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8693 if (!br_spec)
8694 return -EINVAL;
8695
8696 nla_for_each_nested(attr, br_spec, rem) {
8697 int status;
8698 __u16 mode;
8699
8700 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8701 continue;
8702
8703 if (nla_len(attr) < sizeof(mode))
8704 return -EINVAL;
8705
8706 mode = nla_get_u16(attr);
8707 status = ixgbe_configure_bridge_mode(adapter, mode);
8708 if (status)
8709 return status;
8710
8711 break;
8712 }
8713
8714 return 0;
8715 }
8716
8717 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8718 struct net_device *dev,
8719 u32 filter_mask, int nlflags)
8720 {
8721 struct ixgbe_adapter *adapter = netdev_priv(dev);
8722
8723 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8724 return 0;
8725
8726 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
8727 adapter->bridge_mode, 0, 0, nlflags,
8728 filter_mask, NULL);
8729 }
8730
8731 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
8732 {
8733 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
8734 struct ixgbe_adapter *adapter = netdev_priv(pdev);
8735 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
8736 unsigned int limit;
8737 int pool, err;
8738
8739 /* Hardware has a limited number of available pools. Each VF, and the
8740 * PF require a pool. Check to ensure we don't attempt to use more
8741 * then the available number of pools.
8742 */
8743 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
8744 return ERR_PTR(-EINVAL);
8745
8746 #ifdef CONFIG_RPS
8747 if (vdev->num_rx_queues != vdev->num_tx_queues) {
8748 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
8749 vdev->name);
8750 return ERR_PTR(-EINVAL);
8751 }
8752 #endif
8753 /* Check for hardware restriction on number of rx/tx queues */
8754 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
8755 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
8756 netdev_info(pdev,
8757 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
8758 pdev->name);
8759 return ERR_PTR(-EINVAL);
8760 }
8761
8762 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8763 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
8764 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
8765 return ERR_PTR(-EBUSY);
8766
8767 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL);
8768 if (!fwd_adapter)
8769 return ERR_PTR(-ENOMEM);
8770
8771 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
8772 adapter->num_rx_pools++;
8773 set_bit(pool, &adapter->fwd_bitmask);
8774 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8775
8776 /* Enable VMDq flag so device will be set in VM mode */
8777 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
8778 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
8779 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
8780
8781 /* Force reinit of ring allocation with VMDQ enabled */
8782 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8783 if (err)
8784 goto fwd_add_err;
8785 fwd_adapter->pool = pool;
8786 fwd_adapter->real_adapter = adapter;
8787 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
8788 if (err)
8789 goto fwd_add_err;
8790 netif_tx_start_all_queues(vdev);
8791 return fwd_adapter;
8792 fwd_add_err:
8793 /* unwind counter and free adapter struct */
8794 netdev_info(pdev,
8795 "%s: dfwd hardware acceleration failed\n", vdev->name);
8796 clear_bit(pool, &adapter->fwd_bitmask);
8797 adapter->num_rx_pools--;
8798 kfree(fwd_adapter);
8799 return ERR_PTR(err);
8800 }
8801
8802 static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8803 {
8804 struct ixgbe_fwd_adapter *fwd_adapter = priv;
8805 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
8806 unsigned int limit;
8807
8808 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
8809 adapter->num_rx_pools--;
8810
8811 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8812 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
8813 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
8814 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8815 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
8816 fwd_adapter->pool, adapter->num_rx_pools,
8817 fwd_adapter->rx_base_queue,
8818 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
8819 adapter->fwd_bitmask);
8820 kfree(fwd_adapter);
8821 }
8822
8823 #define IXGBE_MAX_TUNNEL_HDR_LEN 80
8824 static netdev_features_t
8825 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
8826 netdev_features_t features)
8827 {
8828 if (!skb->encapsulation)
8829 return features;
8830
8831 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) >
8832 IXGBE_MAX_TUNNEL_HDR_LEN))
8833 return features & ~NETIF_F_CSUM_MASK;
8834
8835 return features;
8836 }
8837
8838 static const struct net_device_ops ixgbe_netdev_ops = {
8839 .ndo_open = ixgbe_open,
8840 .ndo_stop = ixgbe_close,
8841 .ndo_start_xmit = ixgbe_xmit_frame,
8842 .ndo_select_queue = ixgbe_select_queue,
8843 .ndo_set_rx_mode = ixgbe_set_rx_mode,
8844 .ndo_validate_addr = eth_validate_addr,
8845 .ndo_set_mac_address = ixgbe_set_mac,
8846 .ndo_change_mtu = ixgbe_change_mtu,
8847 .ndo_tx_timeout = ixgbe_tx_timeout,
8848 .ndo_set_tx_maxrate = ixgbe_tx_maxrate,
8849 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
8850 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
8851 .ndo_do_ioctl = ixgbe_ioctl,
8852 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
8853 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
8854 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
8855 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
8856 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
8857 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
8858 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
8859 .ndo_get_stats64 = ixgbe_get_stats64,
8860 .ndo_setup_tc = __ixgbe_setup_tc,
8861 #ifdef CONFIG_NET_POLL_CONTROLLER
8862 .ndo_poll_controller = ixgbe_netpoll,
8863 #endif
8864 #ifdef CONFIG_NET_RX_BUSY_POLL
8865 .ndo_busy_poll = ixgbe_low_latency_recv,
8866 #endif
8867 #ifdef IXGBE_FCOE
8868 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
8869 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
8870 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8871 .ndo_fcoe_enable = ixgbe_fcoe_enable,
8872 .ndo_fcoe_disable = ixgbe_fcoe_disable,
8873 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
8874 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
8875 #endif /* IXGBE_FCOE */
8876 .ndo_set_features = ixgbe_set_features,
8877 .ndo_fix_features = ixgbe_fix_features,
8878 .ndo_fdb_add = ixgbe_ndo_fdb_add,
8879 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
8880 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
8881 .ndo_dfwd_add_station = ixgbe_fwd_add,
8882 .ndo_dfwd_del_station = ixgbe_fwd_del,
8883 #ifdef CONFIG_IXGBE_VXLAN
8884 .ndo_add_vxlan_port = ixgbe_add_vxlan_port,
8885 .ndo_del_vxlan_port = ixgbe_del_vxlan_port,
8886 #endif /* CONFIG_IXGBE_VXLAN */
8887 .ndo_features_check = ixgbe_features_check,
8888 };
8889
8890 /**
8891 * ixgbe_enumerate_functions - Get the number of ports this device has
8892 * @adapter: adapter structure
8893 *
8894 * This function enumerates the phsyical functions co-located on a single slot,
8895 * in order to determine how many ports a device has. This is most useful in
8896 * determining the required GT/s of PCIe bandwidth necessary for optimal
8897 * performance.
8898 **/
8899 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
8900 {
8901 struct pci_dev *entry, *pdev = adapter->pdev;
8902 int physfns = 0;
8903
8904 /* Some cards can not use the generic count PCIe functions method,
8905 * because they are behind a parent switch, so we hardcode these with
8906 * the correct number of functions.
8907 */
8908 if (ixgbe_pcie_from_parent(&adapter->hw))
8909 physfns = 4;
8910
8911 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
8912 /* don't count virtual functions */
8913 if (entry->is_virtfn)
8914 continue;
8915
8916 /* When the devices on the bus don't all match our device ID,
8917 * we can't reliably determine the correct number of
8918 * functions. This can occur if a function has been direct
8919 * attached to a virtual machine using VT-d, for example. In
8920 * this case, simply return -1 to indicate this.
8921 */
8922 if ((entry->vendor != pdev->vendor) ||
8923 (entry->device != pdev->device))
8924 return -1;
8925
8926 physfns++;
8927 }
8928
8929 return physfns;
8930 }
8931
8932 /**
8933 * ixgbe_wol_supported - Check whether device supports WoL
8934 * @hw: hw specific details
8935 * @device_id: the device ID
8936 * @subdev_id: the subsystem device ID
8937 *
8938 * This function is used by probe and ethtool to determine
8939 * which devices have WoL support
8940 *
8941 **/
8942 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8943 u16 subdevice_id)
8944 {
8945 struct ixgbe_hw *hw = &adapter->hw;
8946 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8947 int is_wol_supported = 0;
8948
8949 switch (device_id) {
8950 case IXGBE_DEV_ID_82599_SFP:
8951 /* Only these subdevices could supports WOL */
8952 switch (subdevice_id) {
8953 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8954 case IXGBE_SUBDEV_ID_82599_560FLR:
8955 /* only support first port */
8956 if (hw->bus.func != 0)
8957 break;
8958 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8959 case IXGBE_SUBDEV_ID_82599_SFP:
8960 case IXGBE_SUBDEV_ID_82599_RNDC:
8961 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
8962 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8963 is_wol_supported = 1;
8964 break;
8965 }
8966 break;
8967 case IXGBE_DEV_ID_82599EN_SFP:
8968 /* Only this subdevice supports WOL */
8969 switch (subdevice_id) {
8970 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8971 is_wol_supported = 1;
8972 break;
8973 }
8974 break;
8975 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8976 /* All except this subdevice support WOL */
8977 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8978 is_wol_supported = 1;
8979 break;
8980 case IXGBE_DEV_ID_82599_KX4:
8981 is_wol_supported = 1;
8982 break;
8983 case IXGBE_DEV_ID_X540T:
8984 case IXGBE_DEV_ID_X540T1:
8985 case IXGBE_DEV_ID_X550T:
8986 case IXGBE_DEV_ID_X550EM_X_KX4:
8987 case IXGBE_DEV_ID_X550EM_X_KR:
8988 case IXGBE_DEV_ID_X550EM_X_10G_T:
8989 /* check eeprom to see if enabled wol */
8990 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8991 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8992 (hw->bus.func == 0))) {
8993 is_wol_supported = 1;
8994 }
8995 break;
8996 }
8997
8998 return is_wol_supported;
8999 }
9000
9001 /**
9002 * ixgbe_probe - Device Initialization Routine
9003 * @pdev: PCI device information struct
9004 * @ent: entry in ixgbe_pci_tbl
9005 *
9006 * Returns 0 on success, negative on failure
9007 *
9008 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
9009 * The OS initialization, configuring of the adapter private structure,
9010 * and a hardware reset occur.
9011 **/
9012 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9013 {
9014 struct net_device *netdev;
9015 struct ixgbe_adapter *adapter = NULL;
9016 struct ixgbe_hw *hw;
9017 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9018 int i, err, pci_using_dac, expected_gts;
9019 unsigned int indices = MAX_TX_QUEUES;
9020 u8 part_str[IXGBE_PBANUM_LENGTH];
9021 bool disable_dev = false;
9022 #ifdef IXGBE_FCOE
9023 u16 device_caps;
9024 #endif
9025 u32 eec;
9026
9027 /* Catch broken hardware that put the wrong VF device ID in
9028 * the PCIe SR-IOV capability.
9029 */
9030 if (pdev->is_virtfn) {
9031 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
9032 pci_name(pdev), pdev->vendor, pdev->device);
9033 return -EINVAL;
9034 }
9035
9036 err = pci_enable_device_mem(pdev);
9037 if (err)
9038 return err;
9039
9040 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9041 pci_using_dac = 1;
9042 } else {
9043 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9044 if (err) {
9045 dev_err(&pdev->dev,
9046 "No usable DMA configuration, aborting\n");
9047 goto err_dma;
9048 }
9049 pci_using_dac = 0;
9050 }
9051
9052 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
9053 IORESOURCE_MEM), ixgbe_driver_name);
9054 if (err) {
9055 dev_err(&pdev->dev,
9056 "pci_request_selected_regions failed 0x%x\n", err);
9057 goto err_pci_reg;
9058 }
9059
9060 pci_enable_pcie_error_reporting(pdev);
9061
9062 pci_set_master(pdev);
9063 pci_save_state(pdev);
9064
9065 if (ii->mac == ixgbe_mac_82598EB) {
9066 #ifdef CONFIG_IXGBE_DCB
9067 /* 8 TC w/ 4 queues per TC */
9068 indices = 4 * MAX_TRAFFIC_CLASS;
9069 #else
9070 indices = IXGBE_MAX_RSS_INDICES;
9071 #endif
9072 }
9073
9074 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9075 if (!netdev) {
9076 err = -ENOMEM;
9077 goto err_alloc_etherdev;
9078 }
9079
9080 SET_NETDEV_DEV(netdev, &pdev->dev);
9081
9082 adapter = netdev_priv(netdev);
9083
9084 adapter->netdev = netdev;
9085 adapter->pdev = pdev;
9086 hw = &adapter->hw;
9087 hw->back = adapter;
9088 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9089
9090 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
9091 pci_resource_len(pdev, 0));
9092 adapter->io_addr = hw->hw_addr;
9093 if (!hw->hw_addr) {
9094 err = -EIO;
9095 goto err_ioremap;
9096 }
9097
9098 netdev->netdev_ops = &ixgbe_netdev_ops;
9099 ixgbe_set_ethtool_ops(netdev);
9100 netdev->watchdog_timeo = 5 * HZ;
9101 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9102
9103 /* Setup hw api */
9104 hw->mac.ops = *ii->mac_ops;
9105 hw->mac.type = ii->mac;
9106 hw->mvals = ii->mvals;
9107
9108 /* EEPROM */
9109 hw->eeprom.ops = *ii->eeprom_ops;
9110 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
9111 if (ixgbe_removed(hw->hw_addr)) {
9112 err = -EIO;
9113 goto err_ioremap;
9114 }
9115 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
9116 if (!(eec & (1 << 8)))
9117 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
9118
9119 /* PHY */
9120 hw->phy.ops = *ii->phy_ops;
9121 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
9122 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
9123 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
9124 hw->phy.mdio.mmds = 0;
9125 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9126 hw->phy.mdio.dev = netdev;
9127 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
9128 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
9129
9130 ii->get_invariants(hw);
9131
9132 /* setup the private structure */
9133 err = ixgbe_sw_init(adapter);
9134 if (err)
9135 goto err_sw_init;
9136
9137 /* Make sure the SWFW semaphore is in a valid state */
9138 if (hw->mac.ops.init_swfw_sync)
9139 hw->mac.ops.init_swfw_sync(hw);
9140
9141 /* Make it possible the adapter to be woken up via WOL */
9142 switch (adapter->hw.mac.type) {
9143 case ixgbe_mac_82599EB:
9144 case ixgbe_mac_X540:
9145 case ixgbe_mac_X550:
9146 case ixgbe_mac_X550EM_x:
9147 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
9148 break;
9149 default:
9150 break;
9151 }
9152
9153 /*
9154 * If there is a fan on this device and it has failed log the
9155 * failure.
9156 */
9157 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
9158 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
9159 if (esdp & IXGBE_ESDP_SDP1)
9160 e_crit(probe, "Fan has stopped, replace the adapter\n");
9161 }
9162
9163 if (allow_unsupported_sfp)
9164 hw->allow_unsupported_sfp = allow_unsupported_sfp;
9165
9166 /* reset_hw fills in the perm_addr as well */
9167 hw->phy.reset_if_overtemp = true;
9168 err = hw->mac.ops.reset_hw(hw);
9169 hw->phy.reset_if_overtemp = false;
9170 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
9171 err = 0;
9172 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
9173 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
9174 e_dev_err("Reload the driver after installing a supported module.\n");
9175 goto err_sw_init;
9176 } else if (err) {
9177 e_dev_err("HW Init failed: %d\n", err);
9178 goto err_sw_init;
9179 }
9180
9181 #ifdef CONFIG_PCI_IOV
9182 /* SR-IOV not supported on the 82598 */
9183 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
9184 goto skip_sriov;
9185 /* Mailbox */
9186 ixgbe_init_mbx_params_pf(hw);
9187 hw->mbx.ops = ii->mbx_ops;
9188 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
9189 ixgbe_enable_sriov(adapter);
9190 skip_sriov:
9191
9192 #endif
9193 netdev->features = NETIF_F_SG |
9194 NETIF_F_TSO |
9195 NETIF_F_TSO6 |
9196 NETIF_F_RXHASH |
9197 NETIF_F_RXCSUM |
9198 NETIF_F_HW_CSUM |
9199 NETIF_F_HW_VLAN_CTAG_TX |
9200 NETIF_F_HW_VLAN_CTAG_RX |
9201 NETIF_F_HW_VLAN_CTAG_FILTER;
9202
9203 if (hw->mac.type >= ixgbe_mac_82599EB)
9204 netdev->features |= NETIF_F_SCTP_CRC;
9205
9206 /* copy netdev features into list of user selectable features */
9207 netdev->hw_features |= netdev->features;
9208 netdev->hw_features |= NETIF_F_RXALL |
9209 NETIF_F_HW_L2FW_DOFFLOAD;
9210
9211 if (hw->mac.type >= ixgbe_mac_82599EB)
9212 netdev->hw_features |= NETIF_F_NTUPLE |
9213 NETIF_F_HW_TC;
9214
9215 netdev->vlan_features |= NETIF_F_SG |
9216 NETIF_F_TSO |
9217 NETIF_F_TSO6 |
9218 NETIF_F_HW_CSUM |
9219 NETIF_F_SCTP_CRC;
9220
9221 netdev->mpls_features |= NETIF_F_HW_CSUM;
9222 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
9223
9224 netdev->priv_flags |= IFF_UNICAST_FLT;
9225 netdev->priv_flags |= IFF_SUPP_NOFCS;
9226
9227 #ifdef CONFIG_IXGBE_DCB
9228 netdev->dcbnl_ops = &dcbnl_ops;
9229 #endif
9230
9231 #ifdef IXGBE_FCOE
9232 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
9233 unsigned int fcoe_l;
9234
9235 if (hw->mac.ops.get_device_caps) {
9236 hw->mac.ops.get_device_caps(hw, &device_caps);
9237 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
9238 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
9239 }
9240
9241
9242 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
9243 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
9244
9245 netdev->features |= NETIF_F_FSO |
9246 NETIF_F_FCOE_CRC;
9247
9248 netdev->vlan_features |= NETIF_F_FSO |
9249 NETIF_F_FCOE_CRC |
9250 NETIF_F_FCOE_MTU;
9251 }
9252 #endif /* IXGBE_FCOE */
9253 if (pci_using_dac) {
9254 netdev->features |= NETIF_F_HIGHDMA;
9255 netdev->vlan_features |= NETIF_F_HIGHDMA;
9256 }
9257
9258 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
9259 netdev->hw_features |= NETIF_F_LRO;
9260 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
9261 netdev->features |= NETIF_F_LRO;
9262
9263 /* make sure the EEPROM is good */
9264 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9265 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9266 err = -EIO;
9267 goto err_sw_init;
9268 }
9269
9270 eth_platform_get_mac_address(&adapter->pdev->dev,
9271 adapter->hw.mac.perm_addr);
9272
9273 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9274
9275 if (!is_valid_ether_addr(netdev->dev_addr)) {
9276 e_dev_err("invalid MAC address\n");
9277 err = -EIO;
9278 goto err_sw_init;
9279 }
9280
9281 /* Set hw->mac.addr to permanent MAC address */
9282 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr);
9283 ixgbe_mac_set_default_filter(adapter);
9284
9285 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
9286 (unsigned long) adapter);
9287
9288 if (ixgbe_removed(hw->hw_addr)) {
9289 err = -EIO;
9290 goto err_sw_init;
9291 }
9292 INIT_WORK(&adapter->service_task, ixgbe_service_task);
9293 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
9294 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9295
9296 err = ixgbe_init_interrupt_scheme(adapter);
9297 if (err)
9298 goto err_sw_init;
9299
9300 /* WOL not supported for all devices */
9301 adapter->wol = 0;
9302 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
9303 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
9304 pdev->subsystem_device);
9305 if (hw->wol_enabled)
9306 adapter->wol = IXGBE_WUFC_MAG;
9307
9308 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9309
9310 /* save off EEPROM version number */
9311 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
9312 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
9313
9314 /* pick up the PCI bus settings for reporting later */
9315 if (ixgbe_pcie_from_parent(hw))
9316 ixgbe_get_parent_bus_info(adapter);
9317 else
9318 hw->mac.ops.get_bus_info(hw);
9319
9320 /* calculate the expected PCIe bandwidth required for optimal
9321 * performance. Note that some older parts will never have enough
9322 * bandwidth due to being older generation PCIe parts. We clamp these
9323 * parts to ensure no warning is displayed if it can't be fixed.
9324 */
9325 switch (hw->mac.type) {
9326 case ixgbe_mac_82598EB:
9327 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
9328 break;
9329 default:
9330 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
9331 break;
9332 }
9333
9334 /* don't check link if we failed to enumerate functions */
9335 if (expected_gts > 0)
9336 ixgbe_check_minimum_link(adapter, expected_gts);
9337
9338 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
9339 if (err)
9340 strlcpy(part_str, "Unknown", sizeof(part_str));
9341 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
9342 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
9343 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
9344 part_str);
9345 else
9346 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
9347 hw->mac.type, hw->phy.type, part_str);
9348
9349 e_dev_info("%pM\n", netdev->dev_addr);
9350
9351 /* reset the hardware with the new settings */
9352 err = hw->mac.ops.start_hw(hw);
9353 if (err == IXGBE_ERR_EEPROM_VERSION) {
9354 /* We are running on a pre-production device, log a warning */
9355 e_dev_warn("This device is a pre-production adapter/LOM. "
9356 "Please be aware there may be issues associated "
9357 "with your hardware. If you are experiencing "
9358 "problems please contact your Intel or hardware "
9359 "representative who provided you with this "
9360 "hardware.\n");
9361 }
9362 strcpy(netdev->name, "eth%d");
9363 err = register_netdev(netdev);
9364 if (err)
9365 goto err_register;
9366
9367 pci_set_drvdata(pdev, adapter);
9368
9369 /* power down the optics for 82599 SFP+ fiber */
9370 if (hw->mac.ops.disable_tx_laser)
9371 hw->mac.ops.disable_tx_laser(hw);
9372
9373 /* carrier off reporting is important to ethtool even BEFORE open */
9374 netif_carrier_off(netdev);
9375
9376 #ifdef CONFIG_IXGBE_DCA
9377 if (dca_add_requester(&pdev->dev) == 0) {
9378 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
9379 ixgbe_setup_dca(adapter);
9380 }
9381 #endif
9382 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
9383 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
9384 for (i = 0; i < adapter->num_vfs; i++)
9385 ixgbe_vf_configuration(pdev, (i | 0x10000000));
9386 }
9387
9388 /* firmware requires driver version to be 0xFFFFFFFF
9389 * since os does not support feature
9390 */
9391 if (hw->mac.ops.set_fw_drv_ver)
9392 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
9393 0xFF);
9394
9395 /* add san mac addr to netdev */
9396 ixgbe_add_sanmac_netdev(netdev);
9397
9398 e_dev_info("%s\n", ixgbe_default_device_descr);
9399
9400 #ifdef CONFIG_IXGBE_HWMON
9401 if (ixgbe_sysfs_init(adapter))
9402 e_err(probe, "failed to allocate sysfs resources\n");
9403 #endif /* CONFIG_IXGBE_HWMON */
9404
9405 ixgbe_dbg_adapter_init(adapter);
9406
9407 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
9408 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
9409 hw->mac.ops.setup_link(hw,
9410 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
9411 true);
9412
9413 return 0;
9414
9415 err_register:
9416 ixgbe_release_hw_control(adapter);
9417 ixgbe_clear_interrupt_scheme(adapter);
9418 err_sw_init:
9419 ixgbe_disable_sriov(adapter);
9420 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9421 iounmap(adapter->io_addr);
9422 kfree(adapter->mac_table);
9423 err_ioremap:
9424 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9425 free_netdev(netdev);
9426 err_alloc_etherdev:
9427 pci_release_selected_regions(pdev,
9428 pci_select_bars(pdev, IORESOURCE_MEM));
9429 err_pci_reg:
9430 err_dma:
9431 if (!adapter || disable_dev)
9432 pci_disable_device(pdev);
9433 return err;
9434 }
9435
9436 /**
9437 * ixgbe_remove - Device Removal Routine
9438 * @pdev: PCI device information struct
9439 *
9440 * ixgbe_remove is called by the PCI subsystem to alert the driver
9441 * that it should release a PCI device. The could be caused by a
9442 * Hot-Plug event, or because the driver is going to be removed from
9443 * memory.
9444 **/
9445 static void ixgbe_remove(struct pci_dev *pdev)
9446 {
9447 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9448 struct net_device *netdev;
9449 bool disable_dev;
9450
9451 /* if !adapter then we already cleaned up in probe */
9452 if (!adapter)
9453 return;
9454
9455 netdev = adapter->netdev;
9456 ixgbe_dbg_adapter_exit(adapter);
9457
9458 set_bit(__IXGBE_REMOVING, &adapter->state);
9459 cancel_work_sync(&adapter->service_task);
9460
9461
9462 #ifdef CONFIG_IXGBE_DCA
9463 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
9464 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9465 dca_remove_requester(&pdev->dev);
9466 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
9467 IXGBE_DCA_CTRL_DCA_DISABLE);
9468 }
9469
9470 #endif
9471 #ifdef CONFIG_IXGBE_HWMON
9472 ixgbe_sysfs_exit(adapter);
9473 #endif /* CONFIG_IXGBE_HWMON */
9474
9475 /* remove the added san mac */
9476 ixgbe_del_sanmac_netdev(netdev);
9477
9478 #ifdef CONFIG_PCI_IOV
9479 ixgbe_disable_sriov(adapter);
9480 #endif
9481 if (netdev->reg_state == NETREG_REGISTERED)
9482 unregister_netdev(netdev);
9483
9484 ixgbe_clear_interrupt_scheme(adapter);
9485
9486 ixgbe_release_hw_control(adapter);
9487
9488 #ifdef CONFIG_DCB
9489 kfree(adapter->ixgbe_ieee_pfc);
9490 kfree(adapter->ixgbe_ieee_ets);
9491
9492 #endif
9493 iounmap(adapter->io_addr);
9494 pci_release_selected_regions(pdev, pci_select_bars(pdev,
9495 IORESOURCE_MEM));
9496
9497 e_dev_info("complete\n");
9498
9499 kfree(adapter->mac_table);
9500 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9501 free_netdev(netdev);
9502
9503 pci_disable_pcie_error_reporting(pdev);
9504
9505 if (disable_dev)
9506 pci_disable_device(pdev);
9507 }
9508
9509 /**
9510 * ixgbe_io_error_detected - called when PCI error is detected
9511 * @pdev: Pointer to PCI device
9512 * @state: The current pci connection state
9513 *
9514 * This function is called after a PCI bus error affecting
9515 * this device has been detected.
9516 */
9517 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
9518 pci_channel_state_t state)
9519 {
9520 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9521 struct net_device *netdev = adapter->netdev;
9522
9523 #ifdef CONFIG_PCI_IOV
9524 struct ixgbe_hw *hw = &adapter->hw;
9525 struct pci_dev *bdev, *vfdev;
9526 u32 dw0, dw1, dw2, dw3;
9527 int vf, pos;
9528 u16 req_id, pf_func;
9529
9530 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
9531 adapter->num_vfs == 0)
9532 goto skip_bad_vf_detection;
9533
9534 bdev = pdev->bus->self;
9535 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
9536 bdev = bdev->bus->self;
9537
9538 if (!bdev)
9539 goto skip_bad_vf_detection;
9540
9541 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
9542 if (!pos)
9543 goto skip_bad_vf_detection;
9544
9545 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
9546 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
9547 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
9548 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
9549 if (ixgbe_removed(hw->hw_addr))
9550 goto skip_bad_vf_detection;
9551
9552 req_id = dw1 >> 16;
9553 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
9554 if (!(req_id & 0x0080))
9555 goto skip_bad_vf_detection;
9556
9557 pf_func = req_id & 0x01;
9558 if ((pf_func & 1) == (pdev->devfn & 1)) {
9559 unsigned int device_id;
9560
9561 vf = (req_id & 0x7F) >> 1;
9562 e_dev_err("VF %d has caused a PCIe error\n", vf);
9563 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
9564 "%8.8x\tdw3: %8.8x\n",
9565 dw0, dw1, dw2, dw3);
9566 switch (adapter->hw.mac.type) {
9567 case ixgbe_mac_82599EB:
9568 device_id = IXGBE_82599_VF_DEVICE_ID;
9569 break;
9570 case ixgbe_mac_X540:
9571 device_id = IXGBE_X540_VF_DEVICE_ID;
9572 break;
9573 case ixgbe_mac_X550:
9574 device_id = IXGBE_DEV_ID_X550_VF;
9575 break;
9576 case ixgbe_mac_X550EM_x:
9577 device_id = IXGBE_DEV_ID_X550EM_X_VF;
9578 break;
9579 default:
9580 device_id = 0;
9581 break;
9582 }
9583
9584 /* Find the pci device of the offending VF */
9585 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
9586 while (vfdev) {
9587 if (vfdev->devfn == (req_id & 0xFF))
9588 break;
9589 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
9590 device_id, vfdev);
9591 }
9592 /*
9593 * There's a slim chance the VF could have been hot plugged,
9594 * so if it is no longer present we don't need to issue the
9595 * VFLR. Just clean up the AER in that case.
9596 */
9597 if (vfdev) {
9598 ixgbe_issue_vf_flr(adapter, vfdev);
9599 /* Free device reference count */
9600 pci_dev_put(vfdev);
9601 }
9602
9603 pci_cleanup_aer_uncorrect_error_status(pdev);
9604 }
9605
9606 /*
9607 * Even though the error may have occurred on the other port
9608 * we still need to increment the vf error reference count for
9609 * both ports because the I/O resume function will be called
9610 * for both of them.
9611 */
9612 adapter->vferr_refcount++;
9613
9614 return PCI_ERS_RESULT_RECOVERED;
9615
9616 skip_bad_vf_detection:
9617 #endif /* CONFIG_PCI_IOV */
9618 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
9619 return PCI_ERS_RESULT_DISCONNECT;
9620
9621 rtnl_lock();
9622 netif_device_detach(netdev);
9623
9624 if (state == pci_channel_io_perm_failure) {
9625 rtnl_unlock();
9626 return PCI_ERS_RESULT_DISCONNECT;
9627 }
9628
9629 if (netif_running(netdev))
9630 ixgbe_down(adapter);
9631
9632 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
9633 pci_disable_device(pdev);
9634 rtnl_unlock();
9635
9636 /* Request a slot reset. */
9637 return PCI_ERS_RESULT_NEED_RESET;
9638 }
9639
9640 /**
9641 * ixgbe_io_slot_reset - called after the pci bus has been reset.
9642 * @pdev: Pointer to PCI device
9643 *
9644 * Restart the card from scratch, as if from a cold-boot.
9645 */
9646 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
9647 {
9648 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9649 pci_ers_result_t result;
9650 int err;
9651
9652 if (pci_enable_device_mem(pdev)) {
9653 e_err(probe, "Cannot re-enable PCI device after reset.\n");
9654 result = PCI_ERS_RESULT_DISCONNECT;
9655 } else {
9656 smp_mb__before_atomic();
9657 clear_bit(__IXGBE_DISABLED, &adapter->state);
9658 adapter->hw.hw_addr = adapter->io_addr;
9659 pci_set_master(pdev);
9660 pci_restore_state(pdev);
9661 pci_save_state(pdev);
9662
9663 pci_wake_from_d3(pdev, false);
9664
9665 ixgbe_reset(adapter);
9666 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
9667 result = PCI_ERS_RESULT_RECOVERED;
9668 }
9669
9670 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9671 if (err) {
9672 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
9673 "failed 0x%0x\n", err);
9674 /* non-fatal, continue */
9675 }
9676
9677 return result;
9678 }
9679
9680 /**
9681 * ixgbe_io_resume - called when traffic can start flowing again.
9682 * @pdev: Pointer to PCI device
9683 *
9684 * This callback is called when the error recovery driver tells us that
9685 * its OK to resume normal operation.
9686 */
9687 static void ixgbe_io_resume(struct pci_dev *pdev)
9688 {
9689 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9690 struct net_device *netdev = adapter->netdev;
9691
9692 #ifdef CONFIG_PCI_IOV
9693 if (adapter->vferr_refcount) {
9694 e_info(drv, "Resuming after VF err\n");
9695 adapter->vferr_refcount--;
9696 return;
9697 }
9698
9699 #endif
9700 if (netif_running(netdev))
9701 ixgbe_up(adapter);
9702
9703 netif_device_attach(netdev);
9704 }
9705
9706 static const struct pci_error_handlers ixgbe_err_handler = {
9707 .error_detected = ixgbe_io_error_detected,
9708 .slot_reset = ixgbe_io_slot_reset,
9709 .resume = ixgbe_io_resume,
9710 };
9711
9712 static struct pci_driver ixgbe_driver = {
9713 .name = ixgbe_driver_name,
9714 .id_table = ixgbe_pci_tbl,
9715 .probe = ixgbe_probe,
9716 .remove = ixgbe_remove,
9717 #ifdef CONFIG_PM
9718 .suspend = ixgbe_suspend,
9719 .resume = ixgbe_resume,
9720 #endif
9721 .shutdown = ixgbe_shutdown,
9722 .sriov_configure = ixgbe_pci_sriov_configure,
9723 .err_handler = &ixgbe_err_handler
9724 };
9725
9726 /**
9727 * ixgbe_init_module - Driver Registration Routine
9728 *
9729 * ixgbe_init_module is the first routine called when the driver is
9730 * loaded. All it does is register with the PCI subsystem.
9731 **/
9732 static int __init ixgbe_init_module(void)
9733 {
9734 int ret;
9735 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
9736 pr_info("%s\n", ixgbe_copyright);
9737
9738 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
9739 if (!ixgbe_wq) {
9740 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
9741 return -ENOMEM;
9742 }
9743
9744 ixgbe_dbg_init();
9745
9746 ret = pci_register_driver(&ixgbe_driver);
9747 if (ret) {
9748 ixgbe_dbg_exit();
9749 return ret;
9750 }
9751
9752 #ifdef CONFIG_IXGBE_DCA
9753 dca_register_notify(&dca_notifier);
9754 #endif
9755
9756 return 0;
9757 }
9758
9759 module_init(ixgbe_init_module);
9760
9761 /**
9762 * ixgbe_exit_module - Driver Exit Cleanup Routine
9763 *
9764 * ixgbe_exit_module is called just before the driver is removed
9765 * from memory.
9766 **/
9767 static void __exit ixgbe_exit_module(void)
9768 {
9769 #ifdef CONFIG_IXGBE_DCA
9770 dca_unregister_notify(&dca_notifier);
9771 #endif
9772 pci_unregister_driver(&ixgbe_driver);
9773
9774 ixgbe_dbg_exit();
9775 if (ixgbe_wq) {
9776 destroy_workqueue(ixgbe_wq);
9777 ixgbe_wq = NULL;
9778 }
9779 }
9780
9781 #ifdef CONFIG_IXGBE_DCA
9782 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
9783 void *p)
9784 {
9785 int ret_val;
9786
9787 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
9788 __ixgbe_notify_dca);
9789
9790 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
9791 }
9792
9793 #endif /* CONFIG_IXGBE_DCA */
9794
9795 module_exit(ixgbe_exit_module);
9796
9797 /* ixgbe_main.c */
Linux kernel - Deliverables
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