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Merge tag 'nfs-for-3.19-1' of git://git.linux-nfs.org/projects/trondmy/linux-nfs
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2014 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/types.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/vmalloc.h>
34 #include <linux/string.h>
35 #include <linux/in.h>
36 #include <linux/interrupt.h>
37 #include <linux/ip.h>
38 #include <linux/tcp.h>
39 #include <linux/sctp.h>
40 #include <linux/pkt_sched.h>
41 #include <linux/ipv6.h>
42 #include <linux/slab.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/ethtool.h>
46 #include <linux/if.h>
47 #include <linux/if_vlan.h>
48 #include <linux/if_macvlan.h>
49 #include <linux/if_bridge.h>
50 #include <linux/prefetch.h>
51 #include <scsi/fc/fc_fcoe.h>
52
53 #include "ixgbe.h"
54 #include "ixgbe_common.h"
55 #include "ixgbe_dcb_82599.h"
56 #include "ixgbe_sriov.h"
57
58 char ixgbe_driver_name[] = "ixgbe";
59 static const char ixgbe_driver_string[] =
60 "Intel(R) 10 Gigabit PCI Express Network Driver";
61 #ifdef IXGBE_FCOE
62 char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
64 #else
65 static char ixgbe_default_device_descr[] =
66 "Intel(R) 10 Gigabit Network Connection";
67 #endif
68 #define DRV_VERSION "3.19.1-k"
69 const char ixgbe_driver_version[] = DRV_VERSION;
70 static const char ixgbe_copyright[] =
71 "Copyright (c) 1999-2014 Intel Corporation.";
72
73 static const struct ixgbe_info *ixgbe_info_tbl[] = {
74 [board_82598] = &ixgbe_82598_info,
75 [board_82599] = &ixgbe_82599_info,
76 [board_X540] = &ixgbe_X540_info,
77 };
78
79 /* ixgbe_pci_tbl - PCI Device ID Table
80 *
81 * Wildcard entries (PCI_ANY_ID) should come last
82 * Last entry must be all 0s
83 *
84 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
85 * Class, Class Mask, private data (not used) }
86 */
87 static const struct pci_device_id ixgbe_pci_tbl[] = {
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
118 /* required last entry */
119 {0, }
120 };
121 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
122
123 #ifdef CONFIG_IXGBE_DCA
124 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
125 void *p);
126 static struct notifier_block dca_notifier = {
127 .notifier_call = ixgbe_notify_dca,
128 .next = NULL,
129 .priority = 0
130 };
131 #endif
132
133 #ifdef CONFIG_PCI_IOV
134 static unsigned int max_vfs;
135 module_param(max_vfs, uint, 0);
136 MODULE_PARM_DESC(max_vfs,
137 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
138 #endif /* CONFIG_PCI_IOV */
139
140 static unsigned int allow_unsupported_sfp;
141 module_param(allow_unsupported_sfp, uint, 0);
142 MODULE_PARM_DESC(allow_unsupported_sfp,
143 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
144
145 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
146 static int debug = -1;
147 module_param(debug, int, 0);
148 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
149
150 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
151 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
152 MODULE_LICENSE("GPL");
153 MODULE_VERSION(DRV_VERSION);
154
155 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
156
157 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
158 u32 reg, u16 *value)
159 {
160 struct pci_dev *parent_dev;
161 struct pci_bus *parent_bus;
162
163 parent_bus = adapter->pdev->bus->parent;
164 if (!parent_bus)
165 return -1;
166
167 parent_dev = parent_bus->self;
168 if (!parent_dev)
169 return -1;
170
171 if (!pci_is_pcie(parent_dev))
172 return -1;
173
174 pcie_capability_read_word(parent_dev, reg, value);
175 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
176 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
177 return -1;
178 return 0;
179 }
180
181 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
182 {
183 struct ixgbe_hw *hw = &adapter->hw;
184 u16 link_status = 0;
185 int err;
186
187 hw->bus.type = ixgbe_bus_type_pci_express;
188
189 /* Get the negotiated link width and speed from PCI config space of the
190 * parent, as this device is behind a switch
191 */
192 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
193
194 /* assume caller will handle error case */
195 if (err)
196 return err;
197
198 hw->bus.width = ixgbe_convert_bus_width(link_status);
199 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
200
201 return 0;
202 }
203
204 /**
205 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
206 * @hw: hw specific details
207 *
208 * This function is used by probe to determine whether a device's PCI-Express
209 * bandwidth details should be gathered from the parent bus instead of from the
210 * device. Used to ensure that various locations all have the correct device ID
211 * checks.
212 */
213 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
214 {
215 switch (hw->device_id) {
216 case IXGBE_DEV_ID_82599_SFP_SF_QP:
217 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
218 return true;
219 default:
220 return false;
221 }
222 }
223
224 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
225 int expected_gts)
226 {
227 int max_gts = 0;
228 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
229 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
230 struct pci_dev *pdev;
231
232 /* determine whether to use the the parent device
233 */
234 if (ixgbe_pcie_from_parent(&adapter->hw))
235 pdev = adapter->pdev->bus->parent->self;
236 else
237 pdev = adapter->pdev;
238
239 if (pcie_get_minimum_link(pdev, &speed, &width) ||
240 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
241 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
242 return;
243 }
244
245 switch (speed) {
246 case PCIE_SPEED_2_5GT:
247 /* 8b/10b encoding reduces max throughput by 20% */
248 max_gts = 2 * width;
249 break;
250 case PCIE_SPEED_5_0GT:
251 /* 8b/10b encoding reduces max throughput by 20% */
252 max_gts = 4 * width;
253 break;
254 case PCIE_SPEED_8_0GT:
255 /* 128b/130b encoding reduces throughput by less than 2% */
256 max_gts = 8 * width;
257 break;
258 default:
259 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
260 return;
261 }
262
263 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
264 max_gts);
265 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
266 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
267 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
268 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
269 "Unknown"),
270 width,
271 (speed == PCIE_SPEED_2_5GT ? "20%" :
272 speed == PCIE_SPEED_5_0GT ? "20%" :
273 speed == PCIE_SPEED_8_0GT ? "<2%" :
274 "Unknown"));
275
276 if (max_gts < expected_gts) {
277 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
278 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
279 expected_gts);
280 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
281 }
282 }
283
284 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
285 {
286 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
287 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
288 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
289 schedule_work(&adapter->service_task);
290 }
291
292 static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
293 {
294 struct ixgbe_adapter *adapter = hw->back;
295
296 if (!hw->hw_addr)
297 return;
298 hw->hw_addr = NULL;
299 e_dev_err("Adapter removed\n");
300 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
301 ixgbe_service_event_schedule(adapter);
302 }
303
304 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
305 {
306 u32 value;
307
308 /* The following check not only optimizes a bit by not
309 * performing a read on the status register when the
310 * register just read was a status register read that
311 * returned IXGBE_FAILED_READ_REG. It also blocks any
312 * potential recursion.
313 */
314 if (reg == IXGBE_STATUS) {
315 ixgbe_remove_adapter(hw);
316 return;
317 }
318 value = ixgbe_read_reg(hw, IXGBE_STATUS);
319 if (value == IXGBE_FAILED_READ_REG)
320 ixgbe_remove_adapter(hw);
321 }
322
323 /**
324 * ixgbe_read_reg - Read from device register
325 * @hw: hw specific details
326 * @reg: offset of register to read
327 *
328 * Returns : value read or IXGBE_FAILED_READ_REG if removed
329 *
330 * This function is used to read device registers. It checks for device
331 * removal by confirming any read that returns all ones by checking the
332 * status register value for all ones. This function avoids reading from
333 * the hardware if a removal was previously detected in which case it
334 * returns IXGBE_FAILED_READ_REG (all ones).
335 */
336 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
337 {
338 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
339 u32 value;
340
341 if (ixgbe_removed(reg_addr))
342 return IXGBE_FAILED_READ_REG;
343 value = readl(reg_addr + reg);
344 if (unlikely(value == IXGBE_FAILED_READ_REG))
345 ixgbe_check_remove(hw, reg);
346 return value;
347 }
348
349 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
350 {
351 u16 value;
352
353 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
354 if (value == IXGBE_FAILED_READ_CFG_WORD) {
355 ixgbe_remove_adapter(hw);
356 return true;
357 }
358 return false;
359 }
360
361 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
362 {
363 struct ixgbe_adapter *adapter = hw->back;
364 u16 value;
365
366 if (ixgbe_removed(hw->hw_addr))
367 return IXGBE_FAILED_READ_CFG_WORD;
368 pci_read_config_word(adapter->pdev, reg, &value);
369 if (value == IXGBE_FAILED_READ_CFG_WORD &&
370 ixgbe_check_cfg_remove(hw, adapter->pdev))
371 return IXGBE_FAILED_READ_CFG_WORD;
372 return value;
373 }
374
375 #ifdef CONFIG_PCI_IOV
376 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
377 {
378 struct ixgbe_adapter *adapter = hw->back;
379 u32 value;
380
381 if (ixgbe_removed(hw->hw_addr))
382 return IXGBE_FAILED_READ_CFG_DWORD;
383 pci_read_config_dword(adapter->pdev, reg, &value);
384 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
385 ixgbe_check_cfg_remove(hw, adapter->pdev))
386 return IXGBE_FAILED_READ_CFG_DWORD;
387 return value;
388 }
389 #endif /* CONFIG_PCI_IOV */
390
391 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
392 {
393 struct ixgbe_adapter *adapter = hw->back;
394
395 if (ixgbe_removed(hw->hw_addr))
396 return;
397 pci_write_config_word(adapter->pdev, reg, value);
398 }
399
400 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
401 {
402 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
403
404 /* flush memory to make sure state is correct before next watchdog */
405 smp_mb__before_atomic();
406 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
407 }
408
409 struct ixgbe_reg_info {
410 u32 ofs;
411 char *name;
412 };
413
414 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
415
416 /* General Registers */
417 {IXGBE_CTRL, "CTRL"},
418 {IXGBE_STATUS, "STATUS"},
419 {IXGBE_CTRL_EXT, "CTRL_EXT"},
420
421 /* Interrupt Registers */
422 {IXGBE_EICR, "EICR"},
423
424 /* RX Registers */
425 {IXGBE_SRRCTL(0), "SRRCTL"},
426 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
427 {IXGBE_RDLEN(0), "RDLEN"},
428 {IXGBE_RDH(0), "RDH"},
429 {IXGBE_RDT(0), "RDT"},
430 {IXGBE_RXDCTL(0), "RXDCTL"},
431 {IXGBE_RDBAL(0), "RDBAL"},
432 {IXGBE_RDBAH(0), "RDBAH"},
433
434 /* TX Registers */
435 {IXGBE_TDBAL(0), "TDBAL"},
436 {IXGBE_TDBAH(0), "TDBAH"},
437 {IXGBE_TDLEN(0), "TDLEN"},
438 {IXGBE_TDH(0), "TDH"},
439 {IXGBE_TDT(0), "TDT"},
440 {IXGBE_TXDCTL(0), "TXDCTL"},
441
442 /* List Terminator */
443 { .name = NULL }
444 };
445
446
447 /*
448 * ixgbe_regdump - register printout routine
449 */
450 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
451 {
452 int i = 0, j = 0;
453 char rname[16];
454 u32 regs[64];
455
456 switch (reginfo->ofs) {
457 case IXGBE_SRRCTL(0):
458 for (i = 0; i < 64; i++)
459 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
460 break;
461 case IXGBE_DCA_RXCTRL(0):
462 for (i = 0; i < 64; i++)
463 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
464 break;
465 case IXGBE_RDLEN(0):
466 for (i = 0; i < 64; i++)
467 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
468 break;
469 case IXGBE_RDH(0):
470 for (i = 0; i < 64; i++)
471 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
472 break;
473 case IXGBE_RDT(0):
474 for (i = 0; i < 64; i++)
475 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
476 break;
477 case IXGBE_RXDCTL(0):
478 for (i = 0; i < 64; i++)
479 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
480 break;
481 case IXGBE_RDBAL(0):
482 for (i = 0; i < 64; i++)
483 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
484 break;
485 case IXGBE_RDBAH(0):
486 for (i = 0; i < 64; i++)
487 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
488 break;
489 case IXGBE_TDBAL(0):
490 for (i = 0; i < 64; i++)
491 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
492 break;
493 case IXGBE_TDBAH(0):
494 for (i = 0; i < 64; i++)
495 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
496 break;
497 case IXGBE_TDLEN(0):
498 for (i = 0; i < 64; i++)
499 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
500 break;
501 case IXGBE_TDH(0):
502 for (i = 0; i < 64; i++)
503 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
504 break;
505 case IXGBE_TDT(0):
506 for (i = 0; i < 64; i++)
507 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
508 break;
509 case IXGBE_TXDCTL(0):
510 for (i = 0; i < 64; i++)
511 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
512 break;
513 default:
514 pr_info("%-15s %08x\n", reginfo->name,
515 IXGBE_READ_REG(hw, reginfo->ofs));
516 return;
517 }
518
519 for (i = 0; i < 8; i++) {
520 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
521 pr_err("%-15s", rname);
522 for (j = 0; j < 8; j++)
523 pr_cont(" %08x", regs[i*8+j]);
524 pr_cont("\n");
525 }
526
527 }
528
529 /*
530 * ixgbe_dump - Print registers, tx-rings and rx-rings
531 */
532 static void ixgbe_dump(struct ixgbe_adapter *adapter)
533 {
534 struct net_device *netdev = adapter->netdev;
535 struct ixgbe_hw *hw = &adapter->hw;
536 struct ixgbe_reg_info *reginfo;
537 int n = 0;
538 struct ixgbe_ring *tx_ring;
539 struct ixgbe_tx_buffer *tx_buffer;
540 union ixgbe_adv_tx_desc *tx_desc;
541 struct my_u0 { u64 a; u64 b; } *u0;
542 struct ixgbe_ring *rx_ring;
543 union ixgbe_adv_rx_desc *rx_desc;
544 struct ixgbe_rx_buffer *rx_buffer_info;
545 u32 staterr;
546 int i = 0;
547
548 if (!netif_msg_hw(adapter))
549 return;
550
551 /* Print netdevice Info */
552 if (netdev) {
553 dev_info(&adapter->pdev->dev, "Net device Info\n");
554 pr_info("Device Name state "
555 "trans_start last_rx\n");
556 pr_info("%-15s %016lX %016lX %016lX\n",
557 netdev->name,
558 netdev->state,
559 netdev->trans_start,
560 netdev->last_rx);
561 }
562
563 /* Print Registers */
564 dev_info(&adapter->pdev->dev, "Register Dump\n");
565 pr_info(" Register Name Value\n");
566 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
567 reginfo->name; reginfo++) {
568 ixgbe_regdump(hw, reginfo);
569 }
570
571 /* Print TX Ring Summary */
572 if (!netdev || !netif_running(netdev))
573 return;
574
575 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
576 pr_info(" %s %s %s %s\n",
577 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
578 "leng", "ntw", "timestamp");
579 for (n = 0; n < adapter->num_tx_queues; n++) {
580 tx_ring = adapter->tx_ring[n];
581 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
582 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
583 n, tx_ring->next_to_use, tx_ring->next_to_clean,
584 (u64)dma_unmap_addr(tx_buffer, dma),
585 dma_unmap_len(tx_buffer, len),
586 tx_buffer->next_to_watch,
587 (u64)tx_buffer->time_stamp);
588 }
589
590 /* Print TX Rings */
591 if (!netif_msg_tx_done(adapter))
592 goto rx_ring_summary;
593
594 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
595
596 /* Transmit Descriptor Formats
597 *
598 * 82598 Advanced Transmit Descriptor
599 * +--------------------------------------------------------------+
600 * 0 | Buffer Address [63:0] |
601 * +--------------------------------------------------------------+
602 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
603 * +--------------------------------------------------------------+
604 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
605 *
606 * 82598 Advanced Transmit Descriptor (Write-Back Format)
607 * +--------------------------------------------------------------+
608 * 0 | RSV [63:0] |
609 * +--------------------------------------------------------------+
610 * 8 | RSV | STA | NXTSEQ |
611 * +--------------------------------------------------------------+
612 * 63 36 35 32 31 0
613 *
614 * 82599+ Advanced Transmit Descriptor
615 * +--------------------------------------------------------------+
616 * 0 | Buffer Address [63:0] |
617 * +--------------------------------------------------------------+
618 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
619 * +--------------------------------------------------------------+
620 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
621 *
622 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
623 * +--------------------------------------------------------------+
624 * 0 | RSV [63:0] |
625 * +--------------------------------------------------------------+
626 * 8 | RSV | STA | RSV |
627 * +--------------------------------------------------------------+
628 * 63 36 35 32 31 0
629 */
630
631 for (n = 0; n < adapter->num_tx_queues; n++) {
632 tx_ring = adapter->tx_ring[n];
633 pr_info("------------------------------------\n");
634 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
635 pr_info("------------------------------------\n");
636 pr_info("%s%s %s %s %s %s\n",
637 "T [desc] [address 63:0 ] ",
638 "[PlPOIdStDDt Ln] [bi->dma ] ",
639 "leng", "ntw", "timestamp", "bi->skb");
640
641 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
642 tx_desc = IXGBE_TX_DESC(tx_ring, i);
643 tx_buffer = &tx_ring->tx_buffer_info[i];
644 u0 = (struct my_u0 *)tx_desc;
645 if (dma_unmap_len(tx_buffer, len) > 0) {
646 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
647 i,
648 le64_to_cpu(u0->a),
649 le64_to_cpu(u0->b),
650 (u64)dma_unmap_addr(tx_buffer, dma),
651 dma_unmap_len(tx_buffer, len),
652 tx_buffer->next_to_watch,
653 (u64)tx_buffer->time_stamp,
654 tx_buffer->skb);
655 if (i == tx_ring->next_to_use &&
656 i == tx_ring->next_to_clean)
657 pr_cont(" NTC/U\n");
658 else if (i == tx_ring->next_to_use)
659 pr_cont(" NTU\n");
660 else if (i == tx_ring->next_to_clean)
661 pr_cont(" NTC\n");
662 else
663 pr_cont("\n");
664
665 if (netif_msg_pktdata(adapter) &&
666 tx_buffer->skb)
667 print_hex_dump(KERN_INFO, "",
668 DUMP_PREFIX_ADDRESS, 16, 1,
669 tx_buffer->skb->data,
670 dma_unmap_len(tx_buffer, len),
671 true);
672 }
673 }
674 }
675
676 /* Print RX Rings Summary */
677 rx_ring_summary:
678 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
679 pr_info("Queue [NTU] [NTC]\n");
680 for (n = 0; n < adapter->num_rx_queues; n++) {
681 rx_ring = adapter->rx_ring[n];
682 pr_info("%5d %5X %5X\n",
683 n, rx_ring->next_to_use, rx_ring->next_to_clean);
684 }
685
686 /* Print RX Rings */
687 if (!netif_msg_rx_status(adapter))
688 return;
689
690 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
691
692 /* Receive Descriptor Formats
693 *
694 * 82598 Advanced Receive Descriptor (Read) Format
695 * 63 1 0
696 * +-----------------------------------------------------+
697 * 0 | Packet Buffer Address [63:1] |A0/NSE|
698 * +----------------------------------------------+------+
699 * 8 | Header Buffer Address [63:1] | DD |
700 * +-----------------------------------------------------+
701 *
702 *
703 * 82598 Advanced Receive Descriptor (Write-Back) Format
704 *
705 * 63 48 47 32 31 30 21 20 16 15 4 3 0
706 * +------------------------------------------------------+
707 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
708 * | Packet | IP | | | | Type | Type |
709 * | Checksum | Ident | | | | | |
710 * +------------------------------------------------------+
711 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
712 * +------------------------------------------------------+
713 * 63 48 47 32 31 20 19 0
714 *
715 * 82599+ Advanced Receive Descriptor (Read) Format
716 * 63 1 0
717 * +-----------------------------------------------------+
718 * 0 | Packet Buffer Address [63:1] |A0/NSE|
719 * +----------------------------------------------+------+
720 * 8 | Header Buffer Address [63:1] | DD |
721 * +-----------------------------------------------------+
722 *
723 *
724 * 82599+ Advanced Receive Descriptor (Write-Back) Format
725 *
726 * 63 48 47 32 31 30 21 20 17 16 4 3 0
727 * +------------------------------------------------------+
728 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
729 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
730 * |/ Flow Dir Flt ID | | | | | |
731 * +------------------------------------------------------+
732 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
733 * +------------------------------------------------------+
734 * 63 48 47 32 31 20 19 0
735 */
736
737 for (n = 0; n < adapter->num_rx_queues; n++) {
738 rx_ring = adapter->rx_ring[n];
739 pr_info("------------------------------------\n");
740 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
741 pr_info("------------------------------------\n");
742 pr_info("%s%s%s",
743 "R [desc] [ PktBuf A0] ",
744 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
745 "<-- Adv Rx Read format\n");
746 pr_info("%s%s%s",
747 "RWB[desc] [PcsmIpSHl PtRs] ",
748 "[vl er S cks ln] ---------------- [bi->skb ] ",
749 "<-- Adv Rx Write-Back format\n");
750
751 for (i = 0; i < rx_ring->count; i++) {
752 rx_buffer_info = &rx_ring->rx_buffer_info[i];
753 rx_desc = IXGBE_RX_DESC(rx_ring, i);
754 u0 = (struct my_u0 *)rx_desc;
755 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
756 if (staterr & IXGBE_RXD_STAT_DD) {
757 /* Descriptor Done */
758 pr_info("RWB[0x%03X] %016llX "
759 "%016llX ---------------- %p", i,
760 le64_to_cpu(u0->a),
761 le64_to_cpu(u0->b),
762 rx_buffer_info->skb);
763 } else {
764 pr_info("R [0x%03X] %016llX "
765 "%016llX %016llX %p", i,
766 le64_to_cpu(u0->a),
767 le64_to_cpu(u0->b),
768 (u64)rx_buffer_info->dma,
769 rx_buffer_info->skb);
770
771 if (netif_msg_pktdata(adapter) &&
772 rx_buffer_info->dma) {
773 print_hex_dump(KERN_INFO, "",
774 DUMP_PREFIX_ADDRESS, 16, 1,
775 page_address(rx_buffer_info->page) +
776 rx_buffer_info->page_offset,
777 ixgbe_rx_bufsz(rx_ring), true);
778 }
779 }
780
781 if (i == rx_ring->next_to_use)
782 pr_cont(" NTU\n");
783 else if (i == rx_ring->next_to_clean)
784 pr_cont(" NTC\n");
785 else
786 pr_cont("\n");
787
788 }
789 }
790 }
791
792 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
793 {
794 u32 ctrl_ext;
795
796 /* Let firmware take over control of h/w */
797 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
798 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
799 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
800 }
801
802 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
803 {
804 u32 ctrl_ext;
805
806 /* Let firmware know the driver has taken over */
807 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
808 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
809 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
810 }
811
812 /**
813 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
814 * @adapter: pointer to adapter struct
815 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
816 * @queue: queue to map the corresponding interrupt to
817 * @msix_vector: the vector to map to the corresponding queue
818 *
819 */
820 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
821 u8 queue, u8 msix_vector)
822 {
823 u32 ivar, index;
824 struct ixgbe_hw *hw = &adapter->hw;
825 switch (hw->mac.type) {
826 case ixgbe_mac_82598EB:
827 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
828 if (direction == -1)
829 direction = 0;
830 index = (((direction * 64) + queue) >> 2) & 0x1F;
831 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
832 ivar &= ~(0xFF << (8 * (queue & 0x3)));
833 ivar |= (msix_vector << (8 * (queue & 0x3)));
834 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
835 break;
836 case ixgbe_mac_82599EB:
837 case ixgbe_mac_X540:
838 if (direction == -1) {
839 /* other causes */
840 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
841 index = ((queue & 1) * 8);
842 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
843 ivar &= ~(0xFF << index);
844 ivar |= (msix_vector << index);
845 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
846 break;
847 } else {
848 /* tx or rx causes */
849 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
850 index = ((16 * (queue & 1)) + (8 * direction));
851 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
852 ivar &= ~(0xFF << index);
853 ivar |= (msix_vector << index);
854 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
855 break;
856 }
857 default:
858 break;
859 }
860 }
861
862 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
863 u64 qmask)
864 {
865 u32 mask;
866
867 switch (adapter->hw.mac.type) {
868 case ixgbe_mac_82598EB:
869 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
870 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
871 break;
872 case ixgbe_mac_82599EB:
873 case ixgbe_mac_X540:
874 mask = (qmask & 0xFFFFFFFF);
875 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
876 mask = (qmask >> 32);
877 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
878 break;
879 default:
880 break;
881 }
882 }
883
884 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
885 struct ixgbe_tx_buffer *tx_buffer)
886 {
887 if (tx_buffer->skb) {
888 dev_kfree_skb_any(tx_buffer->skb);
889 if (dma_unmap_len(tx_buffer, len))
890 dma_unmap_single(ring->dev,
891 dma_unmap_addr(tx_buffer, dma),
892 dma_unmap_len(tx_buffer, len),
893 DMA_TO_DEVICE);
894 } else if (dma_unmap_len(tx_buffer, len)) {
895 dma_unmap_page(ring->dev,
896 dma_unmap_addr(tx_buffer, dma),
897 dma_unmap_len(tx_buffer, len),
898 DMA_TO_DEVICE);
899 }
900 tx_buffer->next_to_watch = NULL;
901 tx_buffer->skb = NULL;
902 dma_unmap_len_set(tx_buffer, len, 0);
903 /* tx_buffer must be completely set up in the transmit path */
904 }
905
906 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
907 {
908 struct ixgbe_hw *hw = &adapter->hw;
909 struct ixgbe_hw_stats *hwstats = &adapter->stats;
910 int i;
911 u32 data;
912
913 if ((hw->fc.current_mode != ixgbe_fc_full) &&
914 (hw->fc.current_mode != ixgbe_fc_rx_pause))
915 return;
916
917 switch (hw->mac.type) {
918 case ixgbe_mac_82598EB:
919 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
920 break;
921 default:
922 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
923 }
924 hwstats->lxoffrxc += data;
925
926 /* refill credits (no tx hang) if we received xoff */
927 if (!data)
928 return;
929
930 for (i = 0; i < adapter->num_tx_queues; i++)
931 clear_bit(__IXGBE_HANG_CHECK_ARMED,
932 &adapter->tx_ring[i]->state);
933 }
934
935 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
936 {
937 struct ixgbe_hw *hw = &adapter->hw;
938 struct ixgbe_hw_stats *hwstats = &adapter->stats;
939 u32 xoff[8] = {0};
940 u8 tc;
941 int i;
942 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
943
944 if (adapter->ixgbe_ieee_pfc)
945 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
946
947 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
948 ixgbe_update_xoff_rx_lfc(adapter);
949 return;
950 }
951
952 /* update stats for each tc, only valid with PFC enabled */
953 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
954 u32 pxoffrxc;
955
956 switch (hw->mac.type) {
957 case ixgbe_mac_82598EB:
958 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
959 break;
960 default:
961 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
962 }
963 hwstats->pxoffrxc[i] += pxoffrxc;
964 /* Get the TC for given UP */
965 tc = netdev_get_prio_tc_map(adapter->netdev, i);
966 xoff[tc] += pxoffrxc;
967 }
968
969 /* disarm tx queues that have received xoff frames */
970 for (i = 0; i < adapter->num_tx_queues; i++) {
971 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
972
973 tc = tx_ring->dcb_tc;
974 if (xoff[tc])
975 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
976 }
977 }
978
979 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
980 {
981 return ring->stats.packets;
982 }
983
984 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
985 {
986 struct ixgbe_adapter *adapter;
987 struct ixgbe_hw *hw;
988 u32 head, tail;
989
990 if (ring->l2_accel_priv)
991 adapter = ring->l2_accel_priv->real_adapter;
992 else
993 adapter = netdev_priv(ring->netdev);
994
995 hw = &adapter->hw;
996 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
997 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
998
999 if (head != tail)
1000 return (head < tail) ?
1001 tail - head : (tail + ring->count - head);
1002
1003 return 0;
1004 }
1005
1006 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1007 {
1008 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1009 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1010 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1011
1012 clear_check_for_tx_hang(tx_ring);
1013
1014 /*
1015 * Check for a hung queue, but be thorough. This verifies
1016 * that a transmit has been completed since the previous
1017 * check AND there is at least one packet pending. The
1018 * ARMED bit is set to indicate a potential hang. The
1019 * bit is cleared if a pause frame is received to remove
1020 * false hang detection due to PFC or 802.3x frames. By
1021 * requiring this to fail twice we avoid races with
1022 * pfc clearing the ARMED bit and conditions where we
1023 * run the check_tx_hang logic with a transmit completion
1024 * pending but without time to complete it yet.
1025 */
1026 if (tx_done_old == tx_done && tx_pending)
1027 /* make sure it is true for two checks in a row */
1028 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1029 &tx_ring->state);
1030 /* update completed stats and continue */
1031 tx_ring->tx_stats.tx_done_old = tx_done;
1032 /* reset the countdown */
1033 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1034
1035 return false;
1036 }
1037
1038 /**
1039 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1040 * @adapter: driver private struct
1041 **/
1042 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1043 {
1044
1045 /* Do the reset outside of interrupt context */
1046 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1047 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
1048 e_warn(drv, "initiating reset due to tx timeout\n");
1049 ixgbe_service_event_schedule(adapter);
1050 }
1051 }
1052
1053 /**
1054 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
1055 * @q_vector: structure containing interrupt and ring information
1056 * @tx_ring: tx ring to clean
1057 **/
1058 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
1059 struct ixgbe_ring *tx_ring)
1060 {
1061 struct ixgbe_adapter *adapter = q_vector->adapter;
1062 struct ixgbe_tx_buffer *tx_buffer;
1063 union ixgbe_adv_tx_desc *tx_desc;
1064 unsigned int total_bytes = 0, total_packets = 0;
1065 unsigned int budget = q_vector->tx.work_limit;
1066 unsigned int i = tx_ring->next_to_clean;
1067
1068 if (test_bit(__IXGBE_DOWN, &adapter->state))
1069 return true;
1070
1071 tx_buffer = &tx_ring->tx_buffer_info[i];
1072 tx_desc = IXGBE_TX_DESC(tx_ring, i);
1073 i -= tx_ring->count;
1074
1075 do {
1076 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1077
1078 /* if next_to_watch is not set then there is no work pending */
1079 if (!eop_desc)
1080 break;
1081
1082 /* prevent any other reads prior to eop_desc */
1083 read_barrier_depends();
1084
1085 /* if DD is not set pending work has not been completed */
1086 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1087 break;
1088
1089 /* clear next_to_watch to prevent false hangs */
1090 tx_buffer->next_to_watch = NULL;
1091
1092 /* update the statistics for this packet */
1093 total_bytes += tx_buffer->bytecount;
1094 total_packets += tx_buffer->gso_segs;
1095
1096 /* free the skb */
1097 dev_consume_skb_any(tx_buffer->skb);
1098
1099 /* unmap skb header data */
1100 dma_unmap_single(tx_ring->dev,
1101 dma_unmap_addr(tx_buffer, dma),
1102 dma_unmap_len(tx_buffer, len),
1103 DMA_TO_DEVICE);
1104
1105 /* clear tx_buffer data */
1106 tx_buffer->skb = NULL;
1107 dma_unmap_len_set(tx_buffer, len, 0);
1108
1109 /* unmap remaining buffers */
1110 while (tx_desc != eop_desc) {
1111 tx_buffer++;
1112 tx_desc++;
1113 i++;
1114 if (unlikely(!i)) {
1115 i -= tx_ring->count;
1116 tx_buffer = tx_ring->tx_buffer_info;
1117 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1118 }
1119
1120 /* unmap any remaining paged data */
1121 if (dma_unmap_len(tx_buffer, len)) {
1122 dma_unmap_page(tx_ring->dev,
1123 dma_unmap_addr(tx_buffer, dma),
1124 dma_unmap_len(tx_buffer, len),
1125 DMA_TO_DEVICE);
1126 dma_unmap_len_set(tx_buffer, len, 0);
1127 }
1128 }
1129
1130 /* move us one more past the eop_desc for start of next pkt */
1131 tx_buffer++;
1132 tx_desc++;
1133 i++;
1134 if (unlikely(!i)) {
1135 i -= tx_ring->count;
1136 tx_buffer = tx_ring->tx_buffer_info;
1137 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1138 }
1139
1140 /* issue prefetch for next Tx descriptor */
1141 prefetch(tx_desc);
1142
1143 /* update budget accounting */
1144 budget--;
1145 } while (likely(budget));
1146
1147 i += tx_ring->count;
1148 tx_ring->next_to_clean = i;
1149 u64_stats_update_begin(&tx_ring->syncp);
1150 tx_ring->stats.bytes += total_bytes;
1151 tx_ring->stats.packets += total_packets;
1152 u64_stats_update_end(&tx_ring->syncp);
1153 q_vector->tx.total_bytes += total_bytes;
1154 q_vector->tx.total_packets += total_packets;
1155
1156 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1157 /* schedule immediate reset if we believe we hung */
1158 struct ixgbe_hw *hw = &adapter->hw;
1159 e_err(drv, "Detected Tx Unit Hang\n"
1160 " Tx Queue <%d>\n"
1161 " TDH, TDT <%x>, <%x>\n"
1162 " next_to_use <%x>\n"
1163 " next_to_clean <%x>\n"
1164 "tx_buffer_info[next_to_clean]\n"
1165 " time_stamp <%lx>\n"
1166 " jiffies <%lx>\n",
1167 tx_ring->queue_index,
1168 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1169 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1170 tx_ring->next_to_use, i,
1171 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1172
1173 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1174
1175 e_info(probe,
1176 "tx hang %d detected on queue %d, resetting adapter\n",
1177 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1178
1179 /* schedule immediate reset if we believe we hung */
1180 ixgbe_tx_timeout_reset(adapter);
1181
1182 /* the adapter is about to reset, no point in enabling stuff */
1183 return true;
1184 }
1185
1186 netdev_tx_completed_queue(txring_txq(tx_ring),
1187 total_packets, total_bytes);
1188
1189 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1190 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1191 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1192 /* Make sure that anybody stopping the queue after this
1193 * sees the new next_to_clean.
1194 */
1195 smp_mb();
1196 if (__netif_subqueue_stopped(tx_ring->netdev,
1197 tx_ring->queue_index)
1198 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1199 netif_wake_subqueue(tx_ring->netdev,
1200 tx_ring->queue_index);
1201 ++tx_ring->tx_stats.restart_queue;
1202 }
1203 }
1204
1205 return !!budget;
1206 }
1207
1208 #ifdef CONFIG_IXGBE_DCA
1209 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1210 struct ixgbe_ring *tx_ring,
1211 int cpu)
1212 {
1213 struct ixgbe_hw *hw = &adapter->hw;
1214 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1215 u16 reg_offset;
1216
1217 switch (hw->mac.type) {
1218 case ixgbe_mac_82598EB:
1219 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1220 break;
1221 case ixgbe_mac_82599EB:
1222 case ixgbe_mac_X540:
1223 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1224 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1225 break;
1226 default:
1227 /* for unknown hardware do not write register */
1228 return;
1229 }
1230
1231 /*
1232 * We can enable relaxed ordering for reads, but not writes when
1233 * DCA is enabled. This is due to a known issue in some chipsets
1234 * which will cause the DCA tag to be cleared.
1235 */
1236 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1237 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1238 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1239
1240 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1241 }
1242
1243 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1244 struct ixgbe_ring *rx_ring,
1245 int cpu)
1246 {
1247 struct ixgbe_hw *hw = &adapter->hw;
1248 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1249 u8 reg_idx = rx_ring->reg_idx;
1250
1251
1252 switch (hw->mac.type) {
1253 case ixgbe_mac_82599EB:
1254 case ixgbe_mac_X540:
1255 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1256 break;
1257 default:
1258 break;
1259 }
1260
1261 /*
1262 * We can enable relaxed ordering for reads, but not writes when
1263 * DCA is enabled. This is due to a known issue in some chipsets
1264 * which will cause the DCA tag to be cleared.
1265 */
1266 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1267 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1268
1269 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1270 }
1271
1272 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1273 {
1274 struct ixgbe_adapter *adapter = q_vector->adapter;
1275 struct ixgbe_ring *ring;
1276 int cpu = get_cpu();
1277
1278 if (q_vector->cpu == cpu)
1279 goto out_no_update;
1280
1281 ixgbe_for_each_ring(ring, q_vector->tx)
1282 ixgbe_update_tx_dca(adapter, ring, cpu);
1283
1284 ixgbe_for_each_ring(ring, q_vector->rx)
1285 ixgbe_update_rx_dca(adapter, ring, cpu);
1286
1287 q_vector->cpu = cpu;
1288 out_no_update:
1289 put_cpu();
1290 }
1291
1292 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1293 {
1294 int i;
1295
1296 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1297 return;
1298
1299 /* always use CB2 mode, difference is masked in the CB driver */
1300 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1301
1302 for (i = 0; i < adapter->num_q_vectors; i++) {
1303 adapter->q_vector[i]->cpu = -1;
1304 ixgbe_update_dca(adapter->q_vector[i]);
1305 }
1306 }
1307
1308 static int __ixgbe_notify_dca(struct device *dev, void *data)
1309 {
1310 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1311 unsigned long event = *(unsigned long *)data;
1312
1313 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1314 return 0;
1315
1316 switch (event) {
1317 case DCA_PROVIDER_ADD:
1318 /* if we're already enabled, don't do it again */
1319 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1320 break;
1321 if (dca_add_requester(dev) == 0) {
1322 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1323 ixgbe_setup_dca(adapter);
1324 break;
1325 }
1326 /* Fall Through since DCA is disabled. */
1327 case DCA_PROVIDER_REMOVE:
1328 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1329 dca_remove_requester(dev);
1330 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1331 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1332 }
1333 break;
1334 }
1335
1336 return 0;
1337 }
1338
1339 #endif /* CONFIG_IXGBE_DCA */
1340 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1341 union ixgbe_adv_rx_desc *rx_desc,
1342 struct sk_buff *skb)
1343 {
1344 if (ring->netdev->features & NETIF_F_RXHASH)
1345 skb_set_hash(skb,
1346 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1347 PKT_HASH_TYPE_L3);
1348 }
1349
1350 #ifdef IXGBE_FCOE
1351 /**
1352 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1353 * @ring: structure containing ring specific data
1354 * @rx_desc: advanced rx descriptor
1355 *
1356 * Returns : true if it is FCoE pkt
1357 */
1358 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1359 union ixgbe_adv_rx_desc *rx_desc)
1360 {
1361 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1362
1363 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1364 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1365 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1366 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1367 }
1368
1369 #endif /* IXGBE_FCOE */
1370 /**
1371 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1372 * @ring: structure containing ring specific data
1373 * @rx_desc: current Rx descriptor being processed
1374 * @skb: skb currently being received and modified
1375 **/
1376 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1377 union ixgbe_adv_rx_desc *rx_desc,
1378 struct sk_buff *skb)
1379 {
1380 skb_checksum_none_assert(skb);
1381
1382 /* Rx csum disabled */
1383 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1384 return;
1385
1386 /* if IP and error */
1387 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1388 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1389 ring->rx_stats.csum_err++;
1390 return;
1391 }
1392
1393 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1394 return;
1395
1396 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1397 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1398
1399 /*
1400 * 82599 errata, UDP frames with a 0 checksum can be marked as
1401 * checksum errors.
1402 */
1403 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1404 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1405 return;
1406
1407 ring->rx_stats.csum_err++;
1408 return;
1409 }
1410
1411 /* It must be a TCP or UDP packet with a valid checksum */
1412 skb->ip_summed = CHECKSUM_UNNECESSARY;
1413 }
1414
1415 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1416 {
1417 rx_ring->next_to_use = val;
1418
1419 /* update next to alloc since we have filled the ring */
1420 rx_ring->next_to_alloc = val;
1421 /*
1422 * Force memory writes to complete before letting h/w
1423 * know there are new descriptors to fetch. (Only
1424 * applicable for weak-ordered memory model archs,
1425 * such as IA-64).
1426 */
1427 wmb();
1428 ixgbe_write_tail(rx_ring, val);
1429 }
1430
1431 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1432 struct ixgbe_rx_buffer *bi)
1433 {
1434 struct page *page = bi->page;
1435 dma_addr_t dma = bi->dma;
1436
1437 /* since we are recycling buffers we should seldom need to alloc */
1438 if (likely(dma))
1439 return true;
1440
1441 /* alloc new page for storage */
1442 if (likely(!page)) {
1443 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1444 bi->skb, ixgbe_rx_pg_order(rx_ring));
1445 if (unlikely(!page)) {
1446 rx_ring->rx_stats.alloc_rx_page_failed++;
1447 return false;
1448 }
1449 bi->page = page;
1450 }
1451
1452 /* map page for use */
1453 dma = dma_map_page(rx_ring->dev, page, 0,
1454 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1455
1456 /*
1457 * if mapping failed free memory back to system since
1458 * there isn't much point in holding memory we can't use
1459 */
1460 if (dma_mapping_error(rx_ring->dev, dma)) {
1461 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1462 bi->page = NULL;
1463
1464 rx_ring->rx_stats.alloc_rx_page_failed++;
1465 return false;
1466 }
1467
1468 bi->dma = dma;
1469 bi->page_offset = 0;
1470
1471 return true;
1472 }
1473
1474 /**
1475 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1476 * @rx_ring: ring to place buffers on
1477 * @cleaned_count: number of buffers to replace
1478 **/
1479 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1480 {
1481 union ixgbe_adv_rx_desc *rx_desc;
1482 struct ixgbe_rx_buffer *bi;
1483 u16 i = rx_ring->next_to_use;
1484
1485 /* nothing to do */
1486 if (!cleaned_count)
1487 return;
1488
1489 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1490 bi = &rx_ring->rx_buffer_info[i];
1491 i -= rx_ring->count;
1492
1493 do {
1494 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1495 break;
1496
1497 /*
1498 * Refresh the desc even if buffer_addrs didn't change
1499 * because each write-back erases this info.
1500 */
1501 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1502
1503 rx_desc++;
1504 bi++;
1505 i++;
1506 if (unlikely(!i)) {
1507 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1508 bi = rx_ring->rx_buffer_info;
1509 i -= rx_ring->count;
1510 }
1511
1512 /* clear the hdr_addr for the next_to_use descriptor */
1513 rx_desc->read.hdr_addr = 0;
1514
1515 cleaned_count--;
1516 } while (cleaned_count);
1517
1518 i += rx_ring->count;
1519
1520 if (rx_ring->next_to_use != i)
1521 ixgbe_release_rx_desc(rx_ring, i);
1522 }
1523
1524 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1525 struct sk_buff *skb)
1526 {
1527 u16 hdr_len = skb_headlen(skb);
1528
1529 /* set gso_size to avoid messing up TCP MSS */
1530 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1531 IXGBE_CB(skb)->append_cnt);
1532 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1533 }
1534
1535 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1536 struct sk_buff *skb)
1537 {
1538 /* if append_cnt is 0 then frame is not RSC */
1539 if (!IXGBE_CB(skb)->append_cnt)
1540 return;
1541
1542 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1543 rx_ring->rx_stats.rsc_flush++;
1544
1545 ixgbe_set_rsc_gso_size(rx_ring, skb);
1546
1547 /* gso_size is computed using append_cnt so always clear it last */
1548 IXGBE_CB(skb)->append_cnt = 0;
1549 }
1550
1551 /**
1552 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1553 * @rx_ring: rx descriptor ring packet is being transacted on
1554 * @rx_desc: pointer to the EOP Rx descriptor
1555 * @skb: pointer to current skb being populated
1556 *
1557 * This function checks the ring, descriptor, and packet information in
1558 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1559 * other fields within the skb.
1560 **/
1561 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1562 union ixgbe_adv_rx_desc *rx_desc,
1563 struct sk_buff *skb)
1564 {
1565 struct net_device *dev = rx_ring->netdev;
1566
1567 ixgbe_update_rsc_stats(rx_ring, skb);
1568
1569 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1570
1571 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1572
1573 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1574 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
1575
1576 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1577 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1578 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1579 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1580 }
1581
1582 skb_record_rx_queue(skb, rx_ring->queue_index);
1583
1584 skb->protocol = eth_type_trans(skb, dev);
1585 }
1586
1587 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1588 struct sk_buff *skb)
1589 {
1590 struct ixgbe_adapter *adapter = q_vector->adapter;
1591
1592 if (ixgbe_qv_busy_polling(q_vector))
1593 netif_receive_skb(skb);
1594 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1595 napi_gro_receive(&q_vector->napi, skb);
1596 else
1597 netif_rx(skb);
1598 }
1599
1600 /**
1601 * ixgbe_is_non_eop - process handling of non-EOP buffers
1602 * @rx_ring: Rx ring being processed
1603 * @rx_desc: Rx descriptor for current buffer
1604 * @skb: Current socket buffer containing buffer in progress
1605 *
1606 * This function updates next to clean. If the buffer is an EOP buffer
1607 * this function exits returning false, otherwise it will place the
1608 * sk_buff in the next buffer to be chained and return true indicating
1609 * that this is in fact a non-EOP buffer.
1610 **/
1611 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1612 union ixgbe_adv_rx_desc *rx_desc,
1613 struct sk_buff *skb)
1614 {
1615 u32 ntc = rx_ring->next_to_clean + 1;
1616
1617 /* fetch, update, and store next to clean */
1618 ntc = (ntc < rx_ring->count) ? ntc : 0;
1619 rx_ring->next_to_clean = ntc;
1620
1621 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1622
1623 /* update RSC append count if present */
1624 if (ring_is_rsc_enabled(rx_ring)) {
1625 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1626 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1627
1628 if (unlikely(rsc_enabled)) {
1629 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1630
1631 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1632 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1633
1634 /* update ntc based on RSC value */
1635 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1636 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1637 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1638 }
1639 }
1640
1641 /* if we are the last buffer then there is nothing else to do */
1642 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1643 return false;
1644
1645 /* place skb in next buffer to be received */
1646 rx_ring->rx_buffer_info[ntc].skb = skb;
1647 rx_ring->rx_stats.non_eop_descs++;
1648
1649 return true;
1650 }
1651
1652 /**
1653 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1654 * @rx_ring: rx descriptor ring packet is being transacted on
1655 * @skb: pointer to current skb being adjusted
1656 *
1657 * This function is an ixgbe specific version of __pskb_pull_tail. The
1658 * main difference between this version and the original function is that
1659 * this function can make several assumptions about the state of things
1660 * that allow for significant optimizations versus the standard function.
1661 * As a result we can do things like drop a frag and maintain an accurate
1662 * truesize for the skb.
1663 */
1664 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1665 struct sk_buff *skb)
1666 {
1667 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1668 unsigned char *va;
1669 unsigned int pull_len;
1670
1671 /*
1672 * it is valid to use page_address instead of kmap since we are
1673 * working with pages allocated out of the lomem pool per
1674 * alloc_page(GFP_ATOMIC)
1675 */
1676 va = skb_frag_address(frag);
1677
1678 /*
1679 * we need the header to contain the greater of either ETH_HLEN or
1680 * 60 bytes if the skb->len is less than 60 for skb_pad.
1681 */
1682 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
1683
1684 /* align pull length to size of long to optimize memcpy performance */
1685 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1686
1687 /* update all of the pointers */
1688 skb_frag_size_sub(frag, pull_len);
1689 frag->page_offset += pull_len;
1690 skb->data_len -= pull_len;
1691 skb->tail += pull_len;
1692 }
1693
1694 /**
1695 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1696 * @rx_ring: rx descriptor ring packet is being transacted on
1697 * @skb: pointer to current skb being updated
1698 *
1699 * This function provides a basic DMA sync up for the first fragment of an
1700 * skb. The reason for doing this is that the first fragment cannot be
1701 * unmapped until we have reached the end of packet descriptor for a buffer
1702 * chain.
1703 */
1704 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1705 struct sk_buff *skb)
1706 {
1707 /* if the page was released unmap it, else just sync our portion */
1708 if (unlikely(IXGBE_CB(skb)->page_released)) {
1709 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1710 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1711 IXGBE_CB(skb)->page_released = false;
1712 } else {
1713 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1714
1715 dma_sync_single_range_for_cpu(rx_ring->dev,
1716 IXGBE_CB(skb)->dma,
1717 frag->page_offset,
1718 ixgbe_rx_bufsz(rx_ring),
1719 DMA_FROM_DEVICE);
1720 }
1721 IXGBE_CB(skb)->dma = 0;
1722 }
1723
1724 /**
1725 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1726 * @rx_ring: rx descriptor ring packet is being transacted on
1727 * @rx_desc: pointer to the EOP Rx descriptor
1728 * @skb: pointer to current skb being fixed
1729 *
1730 * Check for corrupted packet headers caused by senders on the local L2
1731 * embedded NIC switch not setting up their Tx Descriptors right. These
1732 * should be very rare.
1733 *
1734 * Also address the case where we are pulling data in on pages only
1735 * and as such no data is present in the skb header.
1736 *
1737 * In addition if skb is not at least 60 bytes we need to pad it so that
1738 * it is large enough to qualify as a valid Ethernet frame.
1739 *
1740 * Returns true if an error was encountered and skb was freed.
1741 **/
1742 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1743 union ixgbe_adv_rx_desc *rx_desc,
1744 struct sk_buff *skb)
1745 {
1746 struct net_device *netdev = rx_ring->netdev;
1747
1748 /* verify that the packet does not have any known errors */
1749 if (unlikely(ixgbe_test_staterr(rx_desc,
1750 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1751 !(netdev->features & NETIF_F_RXALL))) {
1752 dev_kfree_skb_any(skb);
1753 return true;
1754 }
1755
1756 /* place header in linear portion of buffer */
1757 if (skb_is_nonlinear(skb))
1758 ixgbe_pull_tail(rx_ring, skb);
1759
1760 #ifdef IXGBE_FCOE
1761 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1762 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1763 return false;
1764
1765 #endif
1766 /* if skb_pad returns an error the skb was freed */
1767 if (unlikely(skb->len < 60)) {
1768 int pad_len = 60 - skb->len;
1769
1770 if (skb_pad(skb, pad_len))
1771 return true;
1772 __skb_put(skb, pad_len);
1773 }
1774
1775 return false;
1776 }
1777
1778 /**
1779 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1780 * @rx_ring: rx descriptor ring to store buffers on
1781 * @old_buff: donor buffer to have page reused
1782 *
1783 * Synchronizes page for reuse by the adapter
1784 **/
1785 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1786 struct ixgbe_rx_buffer *old_buff)
1787 {
1788 struct ixgbe_rx_buffer *new_buff;
1789 u16 nta = rx_ring->next_to_alloc;
1790
1791 new_buff = &rx_ring->rx_buffer_info[nta];
1792
1793 /* update, and store next to alloc */
1794 nta++;
1795 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1796
1797 /* transfer page from old buffer to new buffer */
1798 new_buff->page = old_buff->page;
1799 new_buff->dma = old_buff->dma;
1800 new_buff->page_offset = old_buff->page_offset;
1801
1802 /* sync the buffer for use by the device */
1803 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1804 new_buff->page_offset,
1805 ixgbe_rx_bufsz(rx_ring),
1806 DMA_FROM_DEVICE);
1807 }
1808
1809 /**
1810 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1811 * @rx_ring: rx descriptor ring to transact packets on
1812 * @rx_buffer: buffer containing page to add
1813 * @rx_desc: descriptor containing length of buffer written by hardware
1814 * @skb: sk_buff to place the data into
1815 *
1816 * This function will add the data contained in rx_buffer->page to the skb.
1817 * This is done either through a direct copy if the data in the buffer is
1818 * less than the skb header size, otherwise it will just attach the page as
1819 * a frag to the skb.
1820 *
1821 * The function will then update the page offset if necessary and return
1822 * true if the buffer can be reused by the adapter.
1823 **/
1824 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1825 struct ixgbe_rx_buffer *rx_buffer,
1826 union ixgbe_adv_rx_desc *rx_desc,
1827 struct sk_buff *skb)
1828 {
1829 struct page *page = rx_buffer->page;
1830 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1831 #if (PAGE_SIZE < 8192)
1832 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1833 #else
1834 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1835 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1836 ixgbe_rx_bufsz(rx_ring);
1837 #endif
1838
1839 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1840 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1841
1842 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1843
1844 /* we can reuse buffer as-is, just make sure it is local */
1845 if (likely(page_to_nid(page) == numa_node_id()))
1846 return true;
1847
1848 /* this page cannot be reused so discard it */
1849 put_page(page);
1850 return false;
1851 }
1852
1853 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1854 rx_buffer->page_offset, size, truesize);
1855
1856 /* avoid re-using remote pages */
1857 if (unlikely(page_to_nid(page) != numa_node_id()))
1858 return false;
1859
1860 #if (PAGE_SIZE < 8192)
1861 /* if we are only owner of page we can reuse it */
1862 if (unlikely(page_count(page) != 1))
1863 return false;
1864
1865 /* flip page offset to other buffer */
1866 rx_buffer->page_offset ^= truesize;
1867
1868 /* Even if we own the page, we are not allowed to use atomic_set()
1869 * This would break get_page_unless_zero() users.
1870 */
1871 atomic_inc(&page->_count);
1872 #else
1873 /* move offset up to the next cache line */
1874 rx_buffer->page_offset += truesize;
1875
1876 if (rx_buffer->page_offset > last_offset)
1877 return false;
1878
1879 /* bump ref count on page before it is given to the stack */
1880 get_page(page);
1881 #endif
1882
1883 return true;
1884 }
1885
1886 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1887 union ixgbe_adv_rx_desc *rx_desc)
1888 {
1889 struct ixgbe_rx_buffer *rx_buffer;
1890 struct sk_buff *skb;
1891 struct page *page;
1892
1893 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1894 page = rx_buffer->page;
1895 prefetchw(page);
1896
1897 skb = rx_buffer->skb;
1898
1899 if (likely(!skb)) {
1900 void *page_addr = page_address(page) +
1901 rx_buffer->page_offset;
1902
1903 /* prefetch first cache line of first page */
1904 prefetch(page_addr);
1905 #if L1_CACHE_BYTES < 128
1906 prefetch(page_addr + L1_CACHE_BYTES);
1907 #endif
1908
1909 /* allocate a skb to store the frags */
1910 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1911 IXGBE_RX_HDR_SIZE);
1912 if (unlikely(!skb)) {
1913 rx_ring->rx_stats.alloc_rx_buff_failed++;
1914 return NULL;
1915 }
1916
1917 /*
1918 * we will be copying header into skb->data in
1919 * pskb_may_pull so it is in our interest to prefetch
1920 * it now to avoid a possible cache miss
1921 */
1922 prefetchw(skb->data);
1923
1924 /*
1925 * Delay unmapping of the first packet. It carries the
1926 * header information, HW may still access the header
1927 * after the writeback. Only unmap it when EOP is
1928 * reached
1929 */
1930 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1931 goto dma_sync;
1932
1933 IXGBE_CB(skb)->dma = rx_buffer->dma;
1934 } else {
1935 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1936 ixgbe_dma_sync_frag(rx_ring, skb);
1937
1938 dma_sync:
1939 /* we are reusing so sync this buffer for CPU use */
1940 dma_sync_single_range_for_cpu(rx_ring->dev,
1941 rx_buffer->dma,
1942 rx_buffer->page_offset,
1943 ixgbe_rx_bufsz(rx_ring),
1944 DMA_FROM_DEVICE);
1945 }
1946
1947 /* pull page into skb */
1948 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1949 /* hand second half of page back to the ring */
1950 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1951 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1952 /* the page has been released from the ring */
1953 IXGBE_CB(skb)->page_released = true;
1954 } else {
1955 /* we are not reusing the buffer so unmap it */
1956 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1957 ixgbe_rx_pg_size(rx_ring),
1958 DMA_FROM_DEVICE);
1959 }
1960
1961 /* clear contents of buffer_info */
1962 rx_buffer->skb = NULL;
1963 rx_buffer->dma = 0;
1964 rx_buffer->page = NULL;
1965
1966 return skb;
1967 }
1968
1969 /**
1970 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1971 * @q_vector: structure containing interrupt and ring information
1972 * @rx_ring: rx descriptor ring to transact packets on
1973 * @budget: Total limit on number of packets to process
1974 *
1975 * This function provides a "bounce buffer" approach to Rx interrupt
1976 * processing. The advantage to this is that on systems that have
1977 * expensive overhead for IOMMU access this provides a means of avoiding
1978 * it by maintaining the mapping of the page to the syste.
1979 *
1980 * Returns amount of work completed
1981 **/
1982 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1983 struct ixgbe_ring *rx_ring,
1984 const int budget)
1985 {
1986 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1987 #ifdef IXGBE_FCOE
1988 struct ixgbe_adapter *adapter = q_vector->adapter;
1989 int ddp_bytes;
1990 unsigned int mss = 0;
1991 #endif /* IXGBE_FCOE */
1992 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1993
1994 while (likely(total_rx_packets < budget)) {
1995 union ixgbe_adv_rx_desc *rx_desc;
1996 struct sk_buff *skb;
1997
1998 /* return some buffers to hardware, one at a time is too slow */
1999 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2000 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2001 cleaned_count = 0;
2002 }
2003
2004 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2005
2006 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2007 break;
2008
2009 /*
2010 * This memory barrier is needed to keep us from reading
2011 * any other fields out of the rx_desc until we know the
2012 * RXD_STAT_DD bit is set
2013 */
2014 rmb();
2015
2016 /* retrieve a buffer from the ring */
2017 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
2018
2019 /* exit if we failed to retrieve a buffer */
2020 if (!skb)
2021 break;
2022
2023 cleaned_count++;
2024
2025 /* place incomplete frames back on ring for completion */
2026 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2027 continue;
2028
2029 /* verify the packet layout is correct */
2030 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2031 continue;
2032
2033 /* probably a little skewed due to removing CRC */
2034 total_rx_bytes += skb->len;
2035
2036 /* populate checksum, timestamp, VLAN, and protocol */
2037 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2038
2039 #ifdef IXGBE_FCOE
2040 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2041 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2042 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2043 /* include DDPed FCoE data */
2044 if (ddp_bytes > 0) {
2045 if (!mss) {
2046 mss = rx_ring->netdev->mtu -
2047 sizeof(struct fcoe_hdr) -
2048 sizeof(struct fc_frame_header) -
2049 sizeof(struct fcoe_crc_eof);
2050 if (mss > 512)
2051 mss &= ~511;
2052 }
2053 total_rx_bytes += ddp_bytes;
2054 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2055 mss);
2056 }
2057 if (!ddp_bytes) {
2058 dev_kfree_skb_any(skb);
2059 continue;
2060 }
2061 }
2062
2063 #endif /* IXGBE_FCOE */
2064 skb_mark_napi_id(skb, &q_vector->napi);
2065 ixgbe_rx_skb(q_vector, skb);
2066
2067 /* update budget accounting */
2068 total_rx_packets++;
2069 }
2070
2071 u64_stats_update_begin(&rx_ring->syncp);
2072 rx_ring->stats.packets += total_rx_packets;
2073 rx_ring->stats.bytes += total_rx_bytes;
2074 u64_stats_update_end(&rx_ring->syncp);
2075 q_vector->rx.total_packets += total_rx_packets;
2076 q_vector->rx.total_bytes += total_rx_bytes;
2077
2078 return total_rx_packets;
2079 }
2080
2081 #ifdef CONFIG_NET_RX_BUSY_POLL
2082 /* must be called with local_bh_disable()d */
2083 static int ixgbe_low_latency_recv(struct napi_struct *napi)
2084 {
2085 struct ixgbe_q_vector *q_vector =
2086 container_of(napi, struct ixgbe_q_vector, napi);
2087 struct ixgbe_adapter *adapter = q_vector->adapter;
2088 struct ixgbe_ring *ring;
2089 int found = 0;
2090
2091 if (test_bit(__IXGBE_DOWN, &adapter->state))
2092 return LL_FLUSH_FAILED;
2093
2094 if (!ixgbe_qv_lock_poll(q_vector))
2095 return LL_FLUSH_BUSY;
2096
2097 ixgbe_for_each_ring(ring, q_vector->rx) {
2098 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
2099 #ifdef BP_EXTENDED_STATS
2100 if (found)
2101 ring->stats.cleaned += found;
2102 else
2103 ring->stats.misses++;
2104 #endif
2105 if (found)
2106 break;
2107 }
2108
2109 ixgbe_qv_unlock_poll(q_vector);
2110
2111 return found;
2112 }
2113 #endif /* CONFIG_NET_RX_BUSY_POLL */
2114
2115 /**
2116 * ixgbe_configure_msix - Configure MSI-X hardware
2117 * @adapter: board private structure
2118 *
2119 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2120 * interrupts.
2121 **/
2122 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2123 {
2124 struct ixgbe_q_vector *q_vector;
2125 int v_idx;
2126 u32 mask;
2127
2128 /* Populate MSIX to EITR Select */
2129 if (adapter->num_vfs > 32) {
2130 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2131 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2132 }
2133
2134 /*
2135 * Populate the IVAR table and set the ITR values to the
2136 * corresponding register.
2137 */
2138 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2139 struct ixgbe_ring *ring;
2140 q_vector = adapter->q_vector[v_idx];
2141
2142 ixgbe_for_each_ring(ring, q_vector->rx)
2143 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2144
2145 ixgbe_for_each_ring(ring, q_vector->tx)
2146 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2147
2148 ixgbe_write_eitr(q_vector);
2149 }
2150
2151 switch (adapter->hw.mac.type) {
2152 case ixgbe_mac_82598EB:
2153 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2154 v_idx);
2155 break;
2156 case ixgbe_mac_82599EB:
2157 case ixgbe_mac_X540:
2158 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2159 break;
2160 default:
2161 break;
2162 }
2163 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2164
2165 /* set up to autoclear timer, and the vectors */
2166 mask = IXGBE_EIMS_ENABLE_MASK;
2167 mask &= ~(IXGBE_EIMS_OTHER |
2168 IXGBE_EIMS_MAILBOX |
2169 IXGBE_EIMS_LSC);
2170
2171 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2172 }
2173
2174 enum latency_range {
2175 lowest_latency = 0,
2176 low_latency = 1,
2177 bulk_latency = 2,
2178 latency_invalid = 255
2179 };
2180
2181 /**
2182 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2183 * @q_vector: structure containing interrupt and ring information
2184 * @ring_container: structure containing ring performance data
2185 *
2186 * Stores a new ITR value based on packets and byte
2187 * counts during the last interrupt. The advantage of per interrupt
2188 * computation is faster updates and more accurate ITR for the current
2189 * traffic pattern. Constants in this function were computed
2190 * based on theoretical maximum wire speed and thresholds were set based
2191 * on testing data as well as attempting to minimize response time
2192 * while increasing bulk throughput.
2193 * this functionality is controlled by the InterruptThrottleRate module
2194 * parameter (see ixgbe_param.c)
2195 **/
2196 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2197 struct ixgbe_ring_container *ring_container)
2198 {
2199 int bytes = ring_container->total_bytes;
2200 int packets = ring_container->total_packets;
2201 u32 timepassed_us;
2202 u64 bytes_perint;
2203 u8 itr_setting = ring_container->itr;
2204
2205 if (packets == 0)
2206 return;
2207
2208 /* simple throttlerate management
2209 * 0-10MB/s lowest (100000 ints/s)
2210 * 10-20MB/s low (20000 ints/s)
2211 * 20-1249MB/s bulk (8000 ints/s)
2212 */
2213 /* what was last interrupt timeslice? */
2214 timepassed_us = q_vector->itr >> 2;
2215 if (timepassed_us == 0)
2216 return;
2217
2218 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2219
2220 switch (itr_setting) {
2221 case lowest_latency:
2222 if (bytes_perint > 10)
2223 itr_setting = low_latency;
2224 break;
2225 case low_latency:
2226 if (bytes_perint > 20)
2227 itr_setting = bulk_latency;
2228 else if (bytes_perint <= 10)
2229 itr_setting = lowest_latency;
2230 break;
2231 case bulk_latency:
2232 if (bytes_perint <= 20)
2233 itr_setting = low_latency;
2234 break;
2235 }
2236
2237 /* clear work counters since we have the values we need */
2238 ring_container->total_bytes = 0;
2239 ring_container->total_packets = 0;
2240
2241 /* write updated itr to ring container */
2242 ring_container->itr = itr_setting;
2243 }
2244
2245 /**
2246 * ixgbe_write_eitr - write EITR register in hardware specific way
2247 * @q_vector: structure containing interrupt and ring information
2248 *
2249 * This function is made to be called by ethtool and by the driver
2250 * when it needs to update EITR registers at runtime. Hardware
2251 * specific quirks/differences are taken care of here.
2252 */
2253 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2254 {
2255 struct ixgbe_adapter *adapter = q_vector->adapter;
2256 struct ixgbe_hw *hw = &adapter->hw;
2257 int v_idx = q_vector->v_idx;
2258 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2259
2260 switch (adapter->hw.mac.type) {
2261 case ixgbe_mac_82598EB:
2262 /* must write high and low 16 bits to reset counter */
2263 itr_reg |= (itr_reg << 16);
2264 break;
2265 case ixgbe_mac_82599EB:
2266 case ixgbe_mac_X540:
2267 /*
2268 * set the WDIS bit to not clear the timer bits and cause an
2269 * immediate assertion of the interrupt
2270 */
2271 itr_reg |= IXGBE_EITR_CNT_WDIS;
2272 break;
2273 default:
2274 break;
2275 }
2276 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2277 }
2278
2279 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2280 {
2281 u32 new_itr = q_vector->itr;
2282 u8 current_itr;
2283
2284 ixgbe_update_itr(q_vector, &q_vector->tx);
2285 ixgbe_update_itr(q_vector, &q_vector->rx);
2286
2287 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2288
2289 switch (current_itr) {
2290 /* counts and packets in update_itr are dependent on these numbers */
2291 case lowest_latency:
2292 new_itr = IXGBE_100K_ITR;
2293 break;
2294 case low_latency:
2295 new_itr = IXGBE_20K_ITR;
2296 break;
2297 case bulk_latency:
2298 new_itr = IXGBE_8K_ITR;
2299 break;
2300 default:
2301 break;
2302 }
2303
2304 if (new_itr != q_vector->itr) {
2305 /* do an exponential smoothing */
2306 new_itr = (10 * new_itr * q_vector->itr) /
2307 ((9 * new_itr) + q_vector->itr);
2308
2309 /* save the algorithm value here */
2310 q_vector->itr = new_itr;
2311
2312 ixgbe_write_eitr(q_vector);
2313 }
2314 }
2315
2316 /**
2317 * ixgbe_check_overtemp_subtask - check for over temperature
2318 * @adapter: pointer to adapter
2319 **/
2320 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2321 {
2322 struct ixgbe_hw *hw = &adapter->hw;
2323 u32 eicr = adapter->interrupt_event;
2324
2325 if (test_bit(__IXGBE_DOWN, &adapter->state))
2326 return;
2327
2328 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2329 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2330 return;
2331
2332 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2333
2334 switch (hw->device_id) {
2335 case IXGBE_DEV_ID_82599_T3_LOM:
2336 /*
2337 * Since the warning interrupt is for both ports
2338 * we don't have to check if:
2339 * - This interrupt wasn't for our port.
2340 * - We may have missed the interrupt so always have to
2341 * check if we got a LSC
2342 */
2343 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2344 !(eicr & IXGBE_EICR_LSC))
2345 return;
2346
2347 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2348 u32 speed;
2349 bool link_up = false;
2350
2351 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2352
2353 if (link_up)
2354 return;
2355 }
2356
2357 /* Check if this is not due to overtemp */
2358 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2359 return;
2360
2361 break;
2362 default:
2363 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2364 return;
2365 break;
2366 }
2367 e_crit(drv,
2368 "Network adapter has been stopped because it has over heated. "
2369 "Restart the computer. If the problem persists, "
2370 "power off the system and replace the adapter\n");
2371
2372 adapter->interrupt_event = 0;
2373 }
2374
2375 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2376 {
2377 struct ixgbe_hw *hw = &adapter->hw;
2378
2379 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2380 (eicr & IXGBE_EICR_GPI_SDP1)) {
2381 e_crit(probe, "Fan has stopped, replace the adapter\n");
2382 /* write to clear the interrupt */
2383 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2384 }
2385 }
2386
2387 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2388 {
2389 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2390 return;
2391
2392 switch (adapter->hw.mac.type) {
2393 case ixgbe_mac_82599EB:
2394 /*
2395 * Need to check link state so complete overtemp check
2396 * on service task
2397 */
2398 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2399 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2400 adapter->interrupt_event = eicr;
2401 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2402 ixgbe_service_event_schedule(adapter);
2403 return;
2404 }
2405 return;
2406 case ixgbe_mac_X540:
2407 if (!(eicr & IXGBE_EICR_TS))
2408 return;
2409 break;
2410 default:
2411 return;
2412 }
2413
2414 e_crit(drv,
2415 "Network adapter has been stopped because it has over heated. "
2416 "Restart the computer. If the problem persists, "
2417 "power off the system and replace the adapter\n");
2418 }
2419
2420 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2421 {
2422 struct ixgbe_hw *hw = &adapter->hw;
2423
2424 if (eicr & IXGBE_EICR_GPI_SDP2) {
2425 /* Clear the interrupt */
2426 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2427 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2428 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2429 ixgbe_service_event_schedule(adapter);
2430 }
2431 }
2432
2433 if (eicr & IXGBE_EICR_GPI_SDP1) {
2434 /* Clear the interrupt */
2435 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2436 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2437 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2438 ixgbe_service_event_schedule(adapter);
2439 }
2440 }
2441 }
2442
2443 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2444 {
2445 struct ixgbe_hw *hw = &adapter->hw;
2446
2447 adapter->lsc_int++;
2448 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2449 adapter->link_check_timeout = jiffies;
2450 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2451 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2452 IXGBE_WRITE_FLUSH(hw);
2453 ixgbe_service_event_schedule(adapter);
2454 }
2455 }
2456
2457 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2458 u64 qmask)
2459 {
2460 u32 mask;
2461 struct ixgbe_hw *hw = &adapter->hw;
2462
2463 switch (hw->mac.type) {
2464 case ixgbe_mac_82598EB:
2465 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2466 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2467 break;
2468 case ixgbe_mac_82599EB:
2469 case ixgbe_mac_X540:
2470 mask = (qmask & 0xFFFFFFFF);
2471 if (mask)
2472 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2473 mask = (qmask >> 32);
2474 if (mask)
2475 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2476 break;
2477 default:
2478 break;
2479 }
2480 /* skip the flush */
2481 }
2482
2483 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2484 u64 qmask)
2485 {
2486 u32 mask;
2487 struct ixgbe_hw *hw = &adapter->hw;
2488
2489 switch (hw->mac.type) {
2490 case ixgbe_mac_82598EB:
2491 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2492 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2493 break;
2494 case ixgbe_mac_82599EB:
2495 case ixgbe_mac_X540:
2496 mask = (qmask & 0xFFFFFFFF);
2497 if (mask)
2498 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2499 mask = (qmask >> 32);
2500 if (mask)
2501 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2502 break;
2503 default:
2504 break;
2505 }
2506 /* skip the flush */
2507 }
2508
2509 /**
2510 * ixgbe_irq_enable - Enable default interrupt generation settings
2511 * @adapter: board private structure
2512 **/
2513 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2514 bool flush)
2515 {
2516 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2517
2518 /* don't reenable LSC while waiting for link */
2519 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2520 mask &= ~IXGBE_EIMS_LSC;
2521
2522 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2523 switch (adapter->hw.mac.type) {
2524 case ixgbe_mac_82599EB:
2525 mask |= IXGBE_EIMS_GPI_SDP0;
2526 break;
2527 case ixgbe_mac_X540:
2528 mask |= IXGBE_EIMS_TS;
2529 break;
2530 default:
2531 break;
2532 }
2533 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2534 mask |= IXGBE_EIMS_GPI_SDP1;
2535 switch (adapter->hw.mac.type) {
2536 case ixgbe_mac_82599EB:
2537 mask |= IXGBE_EIMS_GPI_SDP1;
2538 mask |= IXGBE_EIMS_GPI_SDP2;
2539 case ixgbe_mac_X540:
2540 mask |= IXGBE_EIMS_ECC;
2541 mask |= IXGBE_EIMS_MAILBOX;
2542 break;
2543 default:
2544 break;
2545 }
2546
2547 if (adapter->hw.mac.type == ixgbe_mac_X540)
2548 mask |= IXGBE_EIMS_TIMESYNC;
2549
2550 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2551 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2552 mask |= IXGBE_EIMS_FLOW_DIR;
2553
2554 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2555 if (queues)
2556 ixgbe_irq_enable_queues(adapter, ~0);
2557 if (flush)
2558 IXGBE_WRITE_FLUSH(&adapter->hw);
2559 }
2560
2561 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2562 {
2563 struct ixgbe_adapter *adapter = data;
2564 struct ixgbe_hw *hw = &adapter->hw;
2565 u32 eicr;
2566
2567 /*
2568 * Workaround for Silicon errata. Use clear-by-write instead
2569 * of clear-by-read. Reading with EICS will return the
2570 * interrupt causes without clearing, which later be done
2571 * with the write to EICR.
2572 */
2573 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2574
2575 /* The lower 16bits of the EICR register are for the queue interrupts
2576 * which should be masked here in order to not accidently clear them if
2577 * the bits are high when ixgbe_msix_other is called. There is a race
2578 * condition otherwise which results in possible performance loss
2579 * especially if the ixgbe_msix_other interrupt is triggering
2580 * consistently (as it would when PPS is turned on for the X540 device)
2581 */
2582 eicr &= 0xFFFF0000;
2583
2584 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2585
2586 if (eicr & IXGBE_EICR_LSC)
2587 ixgbe_check_lsc(adapter);
2588
2589 if (eicr & IXGBE_EICR_MAILBOX)
2590 ixgbe_msg_task(adapter);
2591
2592 switch (hw->mac.type) {
2593 case ixgbe_mac_82599EB:
2594 case ixgbe_mac_X540:
2595 if (eicr & IXGBE_EICR_ECC) {
2596 e_info(link, "Received ECC Err, initiating reset\n");
2597 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2598 ixgbe_service_event_schedule(adapter);
2599 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2600 }
2601 /* Handle Flow Director Full threshold interrupt */
2602 if (eicr & IXGBE_EICR_FLOW_DIR) {
2603 int reinit_count = 0;
2604 int i;
2605 for (i = 0; i < adapter->num_tx_queues; i++) {
2606 struct ixgbe_ring *ring = adapter->tx_ring[i];
2607 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2608 &ring->state))
2609 reinit_count++;
2610 }
2611 if (reinit_count) {
2612 /* no more flow director interrupts until after init */
2613 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2614 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2615 ixgbe_service_event_schedule(adapter);
2616 }
2617 }
2618 ixgbe_check_sfp_event(adapter, eicr);
2619 ixgbe_check_overtemp_event(adapter, eicr);
2620 break;
2621 default:
2622 break;
2623 }
2624
2625 ixgbe_check_fan_failure(adapter, eicr);
2626
2627 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2628 ixgbe_ptp_check_pps_event(adapter, eicr);
2629
2630 /* re-enable the original interrupt state, no lsc, no queues */
2631 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2632 ixgbe_irq_enable(adapter, false, false);
2633
2634 return IRQ_HANDLED;
2635 }
2636
2637 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2638 {
2639 struct ixgbe_q_vector *q_vector = data;
2640
2641 /* EIAM disabled interrupts (on this vector) for us */
2642
2643 if (q_vector->rx.ring || q_vector->tx.ring)
2644 napi_schedule(&q_vector->napi);
2645
2646 return IRQ_HANDLED;
2647 }
2648
2649 /**
2650 * ixgbe_poll - NAPI Rx polling callback
2651 * @napi: structure for representing this polling device
2652 * @budget: how many packets driver is allowed to clean
2653 *
2654 * This function is used for legacy and MSI, NAPI mode
2655 **/
2656 int ixgbe_poll(struct napi_struct *napi, int budget)
2657 {
2658 struct ixgbe_q_vector *q_vector =
2659 container_of(napi, struct ixgbe_q_vector, napi);
2660 struct ixgbe_adapter *adapter = q_vector->adapter;
2661 struct ixgbe_ring *ring;
2662 int per_ring_budget;
2663 bool clean_complete = true;
2664
2665 #ifdef CONFIG_IXGBE_DCA
2666 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2667 ixgbe_update_dca(q_vector);
2668 #endif
2669
2670 ixgbe_for_each_ring(ring, q_vector->tx)
2671 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2672
2673 if (!ixgbe_qv_lock_napi(q_vector))
2674 return budget;
2675
2676 /* attempt to distribute budget to each queue fairly, but don't allow
2677 * the budget to go below 1 because we'll exit polling */
2678 if (q_vector->rx.count > 1)
2679 per_ring_budget = max(budget/q_vector->rx.count, 1);
2680 else
2681 per_ring_budget = budget;
2682
2683 ixgbe_for_each_ring(ring, q_vector->rx)
2684 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2685 per_ring_budget) < per_ring_budget);
2686
2687 ixgbe_qv_unlock_napi(q_vector);
2688 /* If all work not completed, return budget and keep polling */
2689 if (!clean_complete)
2690 return budget;
2691
2692 /* all work done, exit the polling mode */
2693 napi_complete(napi);
2694 if (adapter->rx_itr_setting & 1)
2695 ixgbe_set_itr(q_vector);
2696 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2697 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2698
2699 return 0;
2700 }
2701
2702 /**
2703 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2704 * @adapter: board private structure
2705 *
2706 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2707 * interrupts from the kernel.
2708 **/
2709 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2710 {
2711 struct net_device *netdev = adapter->netdev;
2712 int vector, err;
2713 int ri = 0, ti = 0;
2714
2715 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2716 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2717 struct msix_entry *entry = &adapter->msix_entries[vector];
2718
2719 if (q_vector->tx.ring && q_vector->rx.ring) {
2720 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2721 "%s-%s-%d", netdev->name, "TxRx", ri++);
2722 ti++;
2723 } else if (q_vector->rx.ring) {
2724 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2725 "%s-%s-%d", netdev->name, "rx", ri++);
2726 } else if (q_vector->tx.ring) {
2727 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2728 "%s-%s-%d", netdev->name, "tx", ti++);
2729 } else {
2730 /* skip this unused q_vector */
2731 continue;
2732 }
2733 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2734 q_vector->name, q_vector);
2735 if (err) {
2736 e_err(probe, "request_irq failed for MSIX interrupt "
2737 "Error: %d\n", err);
2738 goto free_queue_irqs;
2739 }
2740 /* If Flow Director is enabled, set interrupt affinity */
2741 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2742 /* assign the mask for this irq */
2743 irq_set_affinity_hint(entry->vector,
2744 &q_vector->affinity_mask);
2745 }
2746 }
2747
2748 err = request_irq(adapter->msix_entries[vector].vector,
2749 ixgbe_msix_other, 0, netdev->name, adapter);
2750 if (err) {
2751 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2752 goto free_queue_irqs;
2753 }
2754
2755 return 0;
2756
2757 free_queue_irqs:
2758 while (vector) {
2759 vector--;
2760 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2761 NULL);
2762 free_irq(adapter->msix_entries[vector].vector,
2763 adapter->q_vector[vector]);
2764 }
2765 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2766 pci_disable_msix(adapter->pdev);
2767 kfree(adapter->msix_entries);
2768 adapter->msix_entries = NULL;
2769 return err;
2770 }
2771
2772 /**
2773 * ixgbe_intr - legacy mode Interrupt Handler
2774 * @irq: interrupt number
2775 * @data: pointer to a network interface device structure
2776 **/
2777 static irqreturn_t ixgbe_intr(int irq, void *data)
2778 {
2779 struct ixgbe_adapter *adapter = data;
2780 struct ixgbe_hw *hw = &adapter->hw;
2781 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2782 u32 eicr;
2783
2784 /*
2785 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2786 * before the read of EICR.
2787 */
2788 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2789
2790 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2791 * therefore no explicit interrupt disable is necessary */
2792 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2793 if (!eicr) {
2794 /*
2795 * shared interrupt alert!
2796 * make sure interrupts are enabled because the read will
2797 * have disabled interrupts due to EIAM
2798 * finish the workaround of silicon errata on 82598. Unmask
2799 * the interrupt that we masked before the EICR read.
2800 */
2801 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2802 ixgbe_irq_enable(adapter, true, true);
2803 return IRQ_NONE; /* Not our interrupt */
2804 }
2805
2806 if (eicr & IXGBE_EICR_LSC)
2807 ixgbe_check_lsc(adapter);
2808
2809 switch (hw->mac.type) {
2810 case ixgbe_mac_82599EB:
2811 ixgbe_check_sfp_event(adapter, eicr);
2812 /* Fall through */
2813 case ixgbe_mac_X540:
2814 if (eicr & IXGBE_EICR_ECC) {
2815 e_info(link, "Received ECC Err, initiating reset\n");
2816 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2817 ixgbe_service_event_schedule(adapter);
2818 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2819 }
2820 ixgbe_check_overtemp_event(adapter, eicr);
2821 break;
2822 default:
2823 break;
2824 }
2825
2826 ixgbe_check_fan_failure(adapter, eicr);
2827 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2828 ixgbe_ptp_check_pps_event(adapter, eicr);
2829
2830 /* would disable interrupts here but EIAM disabled it */
2831 napi_schedule(&q_vector->napi);
2832
2833 /*
2834 * re-enable link(maybe) and non-queue interrupts, no flush.
2835 * ixgbe_poll will re-enable the queue interrupts
2836 */
2837 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2838 ixgbe_irq_enable(adapter, false, false);
2839
2840 return IRQ_HANDLED;
2841 }
2842
2843 /**
2844 * ixgbe_request_irq - initialize interrupts
2845 * @adapter: board private structure
2846 *
2847 * Attempts to configure interrupts using the best available
2848 * capabilities of the hardware and kernel.
2849 **/
2850 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2851 {
2852 struct net_device *netdev = adapter->netdev;
2853 int err;
2854
2855 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2856 err = ixgbe_request_msix_irqs(adapter);
2857 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2858 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2859 netdev->name, adapter);
2860 else
2861 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2862 netdev->name, adapter);
2863
2864 if (err)
2865 e_err(probe, "request_irq failed, Error %d\n", err);
2866
2867 return err;
2868 }
2869
2870 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2871 {
2872 int vector;
2873
2874 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2875 free_irq(adapter->pdev->irq, adapter);
2876 return;
2877 }
2878
2879 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2880 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2881 struct msix_entry *entry = &adapter->msix_entries[vector];
2882
2883 /* free only the irqs that were actually requested */
2884 if (!q_vector->rx.ring && !q_vector->tx.ring)
2885 continue;
2886
2887 /* clear the affinity_mask in the IRQ descriptor */
2888 irq_set_affinity_hint(entry->vector, NULL);
2889
2890 free_irq(entry->vector, q_vector);
2891 }
2892
2893 free_irq(adapter->msix_entries[vector++].vector, adapter);
2894 }
2895
2896 /**
2897 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2898 * @adapter: board private structure
2899 **/
2900 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2901 {
2902 switch (adapter->hw.mac.type) {
2903 case ixgbe_mac_82598EB:
2904 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2905 break;
2906 case ixgbe_mac_82599EB:
2907 case ixgbe_mac_X540:
2908 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2909 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2910 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2911 break;
2912 default:
2913 break;
2914 }
2915 IXGBE_WRITE_FLUSH(&adapter->hw);
2916 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2917 int vector;
2918
2919 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2920 synchronize_irq(adapter->msix_entries[vector].vector);
2921
2922 synchronize_irq(adapter->msix_entries[vector++].vector);
2923 } else {
2924 synchronize_irq(adapter->pdev->irq);
2925 }
2926 }
2927
2928 /**
2929 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2930 *
2931 **/
2932 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2933 {
2934 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2935
2936 ixgbe_write_eitr(q_vector);
2937
2938 ixgbe_set_ivar(adapter, 0, 0, 0);
2939 ixgbe_set_ivar(adapter, 1, 0, 0);
2940
2941 e_info(hw, "Legacy interrupt IVAR setup done\n");
2942 }
2943
2944 /**
2945 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2946 * @adapter: board private structure
2947 * @ring: structure containing ring specific data
2948 *
2949 * Configure the Tx descriptor ring after a reset.
2950 **/
2951 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2952 struct ixgbe_ring *ring)
2953 {
2954 struct ixgbe_hw *hw = &adapter->hw;
2955 u64 tdba = ring->dma;
2956 int wait_loop = 10;
2957 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2958 u8 reg_idx = ring->reg_idx;
2959
2960 /* disable queue to avoid issues while updating state */
2961 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2962 IXGBE_WRITE_FLUSH(hw);
2963
2964 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2965 (tdba & DMA_BIT_MASK(32)));
2966 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2967 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2968 ring->count * sizeof(union ixgbe_adv_tx_desc));
2969 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2970 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2971 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
2972
2973 /*
2974 * set WTHRESH to encourage burst writeback, it should not be set
2975 * higher than 1 when:
2976 * - ITR is 0 as it could cause false TX hangs
2977 * - ITR is set to > 100k int/sec and BQL is enabled
2978 *
2979 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2980 * to or less than the number of on chip descriptors, which is
2981 * currently 40.
2982 */
2983 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
2984 txdctl |= (1 << 16); /* WTHRESH = 1 */
2985 else
2986 txdctl |= (8 << 16); /* WTHRESH = 8 */
2987
2988 /*
2989 * Setting PTHRESH to 32 both improves performance
2990 * and avoids a TX hang with DFP enabled
2991 */
2992 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2993 32; /* PTHRESH = 32 */
2994
2995 /* reinitialize flowdirector state */
2996 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2997 ring->atr_sample_rate = adapter->atr_sample_rate;
2998 ring->atr_count = 0;
2999 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3000 } else {
3001 ring->atr_sample_rate = 0;
3002 }
3003
3004 /* initialize XPS */
3005 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3006 struct ixgbe_q_vector *q_vector = ring->q_vector;
3007
3008 if (q_vector)
3009 netif_set_xps_queue(ring->netdev,
3010 &q_vector->affinity_mask,
3011 ring->queue_index);
3012 }
3013
3014 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3015
3016 /* enable queue */
3017 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3018
3019 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3020 if (hw->mac.type == ixgbe_mac_82598EB &&
3021 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3022 return;
3023
3024 /* poll to verify queue is enabled */
3025 do {
3026 usleep_range(1000, 2000);
3027 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3028 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3029 if (!wait_loop)
3030 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
3031 }
3032
3033 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3034 {
3035 struct ixgbe_hw *hw = &adapter->hw;
3036 u32 rttdcs, mtqc;
3037 u8 tcs = netdev_get_num_tc(adapter->netdev);
3038
3039 if (hw->mac.type == ixgbe_mac_82598EB)
3040 return;
3041
3042 /* disable the arbiter while setting MTQC */
3043 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3044 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3045 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3046
3047 /* set transmit pool layout */
3048 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3049 mtqc = IXGBE_MTQC_VT_ENA;
3050 if (tcs > 4)
3051 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3052 else if (tcs > 1)
3053 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3054 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3055 mtqc |= IXGBE_MTQC_32VF;
3056 else
3057 mtqc |= IXGBE_MTQC_64VF;
3058 } else {
3059 if (tcs > 4)
3060 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3061 else if (tcs > 1)
3062 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3063 else
3064 mtqc = IXGBE_MTQC_64Q_1PB;
3065 }
3066
3067 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3068
3069 /* Enable Security TX Buffer IFG for multiple pb */
3070 if (tcs) {
3071 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3072 sectx |= IXGBE_SECTX_DCB;
3073 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3074 }
3075
3076 /* re-enable the arbiter */
3077 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3078 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3079 }
3080
3081 /**
3082 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3083 * @adapter: board private structure
3084 *
3085 * Configure the Tx unit of the MAC after a reset.
3086 **/
3087 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3088 {
3089 struct ixgbe_hw *hw = &adapter->hw;
3090 u32 dmatxctl;
3091 u32 i;
3092
3093 ixgbe_setup_mtqc(adapter);
3094
3095 if (hw->mac.type != ixgbe_mac_82598EB) {
3096 /* DMATXCTL.EN must be before Tx queues are enabled */
3097 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3098 dmatxctl |= IXGBE_DMATXCTL_TE;
3099 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3100 }
3101
3102 /* Setup the HW Tx Head and Tail descriptor pointers */
3103 for (i = 0; i < adapter->num_tx_queues; i++)
3104 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3105 }
3106
3107 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3108 struct ixgbe_ring *ring)
3109 {
3110 struct ixgbe_hw *hw = &adapter->hw;
3111 u8 reg_idx = ring->reg_idx;
3112 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3113
3114 srrctl |= IXGBE_SRRCTL_DROP_EN;
3115
3116 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3117 }
3118
3119 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3120 struct ixgbe_ring *ring)
3121 {
3122 struct ixgbe_hw *hw = &adapter->hw;
3123 u8 reg_idx = ring->reg_idx;
3124 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3125
3126 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3127
3128 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3129 }
3130
3131 #ifdef CONFIG_IXGBE_DCB
3132 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3133 #else
3134 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3135 #endif
3136 {
3137 int i;
3138 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3139
3140 if (adapter->ixgbe_ieee_pfc)
3141 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3142
3143 /*
3144 * We should set the drop enable bit if:
3145 * SR-IOV is enabled
3146 * or
3147 * Number of Rx queues > 1 and flow control is disabled
3148 *
3149 * This allows us to avoid head of line blocking for security
3150 * and performance reasons.
3151 */
3152 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3153 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3154 for (i = 0; i < adapter->num_rx_queues; i++)
3155 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3156 } else {
3157 for (i = 0; i < adapter->num_rx_queues; i++)
3158 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3159 }
3160 }
3161
3162 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3163
3164 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3165 struct ixgbe_ring *rx_ring)
3166 {
3167 struct ixgbe_hw *hw = &adapter->hw;
3168 u32 srrctl;
3169 u8 reg_idx = rx_ring->reg_idx;
3170
3171 if (hw->mac.type == ixgbe_mac_82598EB) {
3172 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3173
3174 /*
3175 * if VMDq is not active we must program one srrctl register
3176 * per RSS queue since we have enabled RDRXCTL.MVMEN
3177 */
3178 reg_idx &= mask;
3179 }
3180
3181 /* configure header buffer length, needed for RSC */
3182 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3183
3184 /* configure the packet buffer length */
3185 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3186
3187 /* configure descriptor type */
3188 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3189
3190 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3191 }
3192
3193 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3194 {
3195 struct ixgbe_hw *hw = &adapter->hw;
3196 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
3197 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3198 0x6A3E67EA, 0x14364D17, 0x3BED200D};
3199 u32 mrqc = 0, reta = 0;
3200 u32 rxcsum;
3201 int i, j;
3202 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3203
3204 /*
3205 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3206 * make full use of any rings they may have. We will use the
3207 * PSRTYPE register to control how many rings we use within the PF.
3208 */
3209 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3210 rss_i = 2;
3211
3212 /* Fill out hash function seeds */
3213 for (i = 0; i < 10; i++)
3214 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3215
3216 /* Fill out redirection table */
3217 for (i = 0, j = 0; i < 128; i++, j++) {
3218 if (j == rss_i)
3219 j = 0;
3220 /* reta = 4-byte sliding window of
3221 * 0x00..(indices-1)(indices-1)00..etc. */
3222 reta = (reta << 8) | (j * 0x11);
3223 if ((i & 3) == 3)
3224 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3225 }
3226
3227 /* Disable indicating checksum in descriptor, enables RSS hash */
3228 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3229 rxcsum |= IXGBE_RXCSUM_PCSD;
3230 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3231
3232 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3233 if (adapter->ring_feature[RING_F_RSS].mask)
3234 mrqc = IXGBE_MRQC_RSSEN;
3235 } else {
3236 u8 tcs = netdev_get_num_tc(adapter->netdev);
3237
3238 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3239 if (tcs > 4)
3240 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3241 else if (tcs > 1)
3242 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3243 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3244 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3245 else
3246 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3247 } else {
3248 if (tcs > 4)
3249 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3250 else if (tcs > 1)
3251 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3252 else
3253 mrqc = IXGBE_MRQC_RSSEN;
3254 }
3255 }
3256
3257 /* Perform hash on these packet types */
3258 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3259 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3260 IXGBE_MRQC_RSS_FIELD_IPV6 |
3261 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3262
3263 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3264 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3265 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3266 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3267
3268 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3269 }
3270
3271 /**
3272 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3273 * @adapter: address of board private structure
3274 * @index: index of ring to set
3275 **/
3276 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3277 struct ixgbe_ring *ring)
3278 {
3279 struct ixgbe_hw *hw = &adapter->hw;
3280 u32 rscctrl;
3281 u8 reg_idx = ring->reg_idx;
3282
3283 if (!ring_is_rsc_enabled(ring))
3284 return;
3285
3286 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3287 rscctrl |= IXGBE_RSCCTL_RSCEN;
3288 /*
3289 * we must limit the number of descriptors so that the
3290 * total size of max desc * buf_len is not greater
3291 * than 65536
3292 */
3293 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3294 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3295 }
3296
3297 #define IXGBE_MAX_RX_DESC_POLL 10
3298 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3299 struct ixgbe_ring *ring)
3300 {
3301 struct ixgbe_hw *hw = &adapter->hw;
3302 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3303 u32 rxdctl;
3304 u8 reg_idx = ring->reg_idx;
3305
3306 if (ixgbe_removed(hw->hw_addr))
3307 return;
3308 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3309 if (hw->mac.type == ixgbe_mac_82598EB &&
3310 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3311 return;
3312
3313 do {
3314 usleep_range(1000, 2000);
3315 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3316 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3317
3318 if (!wait_loop) {
3319 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3320 "the polling period\n", reg_idx);
3321 }
3322 }
3323
3324 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3325 struct ixgbe_ring *ring)
3326 {
3327 struct ixgbe_hw *hw = &adapter->hw;
3328 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3329 u32 rxdctl;
3330 u8 reg_idx = ring->reg_idx;
3331
3332 if (ixgbe_removed(hw->hw_addr))
3333 return;
3334 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3335 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3336
3337 /* write value back with RXDCTL.ENABLE bit cleared */
3338 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3339
3340 if (hw->mac.type == ixgbe_mac_82598EB &&
3341 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3342 return;
3343
3344 /* the hardware may take up to 100us to really disable the rx queue */
3345 do {
3346 udelay(10);
3347 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3348 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3349
3350 if (!wait_loop) {
3351 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3352 "the polling period\n", reg_idx);
3353 }
3354 }
3355
3356 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3357 struct ixgbe_ring *ring)
3358 {
3359 struct ixgbe_hw *hw = &adapter->hw;
3360 u64 rdba = ring->dma;
3361 u32 rxdctl;
3362 u8 reg_idx = ring->reg_idx;
3363
3364 /* disable queue to avoid issues while updating state */
3365 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3366 ixgbe_disable_rx_queue(adapter, ring);
3367
3368 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3369 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3370 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3371 ring->count * sizeof(union ixgbe_adv_rx_desc));
3372 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3373 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3374 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
3375
3376 ixgbe_configure_srrctl(adapter, ring);
3377 ixgbe_configure_rscctl(adapter, ring);
3378
3379 if (hw->mac.type == ixgbe_mac_82598EB) {
3380 /*
3381 * enable cache line friendly hardware writes:
3382 * PTHRESH=32 descriptors (half the internal cache),
3383 * this also removes ugly rx_no_buffer_count increment
3384 * HTHRESH=4 descriptors (to minimize latency on fetch)
3385 * WTHRESH=8 burst writeback up to two cache lines
3386 */
3387 rxdctl &= ~0x3FFFFF;
3388 rxdctl |= 0x080420;
3389 }
3390
3391 /* enable receive descriptor ring */
3392 rxdctl |= IXGBE_RXDCTL_ENABLE;
3393 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3394
3395 ixgbe_rx_desc_queue_enable(adapter, ring);
3396 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3397 }
3398
3399 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3400 {
3401 struct ixgbe_hw *hw = &adapter->hw;
3402 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3403 u16 pool;
3404
3405 /* PSRTYPE must be initialized in non 82598 adapters */
3406 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3407 IXGBE_PSRTYPE_UDPHDR |
3408 IXGBE_PSRTYPE_IPV4HDR |
3409 IXGBE_PSRTYPE_L2HDR |
3410 IXGBE_PSRTYPE_IPV6HDR;
3411
3412 if (hw->mac.type == ixgbe_mac_82598EB)
3413 return;
3414
3415 if (rss_i > 3)
3416 psrtype |= 2 << 29;
3417 else if (rss_i > 1)
3418 psrtype |= 1 << 29;
3419
3420 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3421 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
3422 }
3423
3424 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3425 {
3426 struct ixgbe_hw *hw = &adapter->hw;
3427 u32 reg_offset, vf_shift;
3428 u32 gcr_ext, vmdctl;
3429 int i;
3430
3431 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3432 return;
3433
3434 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3435 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3436 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3437 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3438 vmdctl |= IXGBE_VT_CTL_REPLEN;
3439 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3440
3441 vf_shift = VMDQ_P(0) % 32;
3442 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3443
3444 /* Enable only the PF's pool for Tx/Rx */
3445 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3446 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3447 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3448 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3449 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3450 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3451
3452 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3453 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3454
3455 /*
3456 * Set up VF register offsets for selected VT Mode,
3457 * i.e. 32 or 64 VFs for SR-IOV
3458 */
3459 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3460 case IXGBE_82599_VMDQ_8Q_MASK:
3461 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3462 break;
3463 case IXGBE_82599_VMDQ_4Q_MASK:
3464 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3465 break;
3466 default:
3467 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3468 break;
3469 }
3470
3471 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3472
3473
3474 /* Enable MAC Anti-Spoofing */
3475 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3476 adapter->num_vfs);
3477 /* For VFs that have spoof checking turned off */
3478 for (i = 0; i < adapter->num_vfs; i++) {
3479 if (!adapter->vfinfo[i].spoofchk_enabled)
3480 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3481 }
3482 }
3483
3484 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3485 {
3486 struct ixgbe_hw *hw = &adapter->hw;
3487 struct net_device *netdev = adapter->netdev;
3488 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3489 struct ixgbe_ring *rx_ring;
3490 int i;
3491 u32 mhadd, hlreg0;
3492
3493 #ifdef IXGBE_FCOE
3494 /* adjust max frame to be able to do baby jumbo for FCoE */
3495 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3496 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3497 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3498
3499 #endif /* IXGBE_FCOE */
3500
3501 /* adjust max frame to be at least the size of a standard frame */
3502 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3503 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3504
3505 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3506 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3507 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3508 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3509
3510 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3511 }
3512
3513 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3514 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3515 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3516 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3517
3518 /*
3519 * Setup the HW Rx Head and Tail Descriptor Pointers and
3520 * the Base and Length of the Rx Descriptor Ring
3521 */
3522 for (i = 0; i < adapter->num_rx_queues; i++) {
3523 rx_ring = adapter->rx_ring[i];
3524 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3525 set_ring_rsc_enabled(rx_ring);
3526 else
3527 clear_ring_rsc_enabled(rx_ring);
3528 }
3529 }
3530
3531 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3532 {
3533 struct ixgbe_hw *hw = &adapter->hw;
3534 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3535
3536 switch (hw->mac.type) {
3537 case ixgbe_mac_82598EB:
3538 /*
3539 * For VMDq support of different descriptor types or
3540 * buffer sizes through the use of multiple SRRCTL
3541 * registers, RDRXCTL.MVMEN must be set to 1
3542 *
3543 * also, the manual doesn't mention it clearly but DCA hints
3544 * will only use queue 0's tags unless this bit is set. Side
3545 * effects of setting this bit are only that SRRCTL must be
3546 * fully programmed [0..15]
3547 */
3548 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3549 break;
3550 case ixgbe_mac_82599EB:
3551 case ixgbe_mac_X540:
3552 /* Disable RSC for ACK packets */
3553 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3554 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3555 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3556 /* hardware requires some bits to be set by default */
3557 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3558 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3559 break;
3560 default:
3561 /* We should do nothing since we don't know this hardware */
3562 return;
3563 }
3564
3565 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3566 }
3567
3568 /**
3569 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3570 * @adapter: board private structure
3571 *
3572 * Configure the Rx unit of the MAC after a reset.
3573 **/
3574 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3575 {
3576 struct ixgbe_hw *hw = &adapter->hw;
3577 int i;
3578 u32 rxctrl, rfctl;
3579
3580 /* disable receives while setting up the descriptors */
3581 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3582 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3583
3584 ixgbe_setup_psrtype(adapter);
3585 ixgbe_setup_rdrxctl(adapter);
3586
3587 /* RSC Setup */
3588 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3589 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3590 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3591 rfctl |= IXGBE_RFCTL_RSC_DIS;
3592 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3593
3594 /* Program registers for the distribution of queues */
3595 ixgbe_setup_mrqc(adapter);
3596
3597 /* set_rx_buffer_len must be called before ring initialization */
3598 ixgbe_set_rx_buffer_len(adapter);
3599
3600 /*
3601 * Setup the HW Rx Head and Tail Descriptor Pointers and
3602 * the Base and Length of the Rx Descriptor Ring
3603 */
3604 for (i = 0; i < adapter->num_rx_queues; i++)
3605 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3606
3607 /* disable drop enable for 82598 parts */
3608 if (hw->mac.type == ixgbe_mac_82598EB)
3609 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3610
3611 /* enable all receives */
3612 rxctrl |= IXGBE_RXCTRL_RXEN;
3613 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3614 }
3615
3616 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3617 __be16 proto, u16 vid)
3618 {
3619 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3620 struct ixgbe_hw *hw = &adapter->hw;
3621
3622 /* add VID to filter table */
3623 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3624 set_bit(vid, adapter->active_vlans);
3625
3626 return 0;
3627 }
3628
3629 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3630 __be16 proto, u16 vid)
3631 {
3632 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3633 struct ixgbe_hw *hw = &adapter->hw;
3634
3635 /* remove VID from filter table */
3636 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3637 clear_bit(vid, adapter->active_vlans);
3638
3639 return 0;
3640 }
3641
3642 /**
3643 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3644 * @adapter: driver data
3645 */
3646 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3647 {
3648 struct ixgbe_hw *hw = &adapter->hw;
3649 u32 vlnctrl;
3650 int i, j;
3651
3652 switch (hw->mac.type) {
3653 case ixgbe_mac_82598EB:
3654 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3655 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3656 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3657 break;
3658 case ixgbe_mac_82599EB:
3659 case ixgbe_mac_X540:
3660 for (i = 0; i < adapter->num_rx_queues; i++) {
3661 struct ixgbe_ring *ring = adapter->rx_ring[i];
3662
3663 if (ring->l2_accel_priv)
3664 continue;
3665 j = ring->reg_idx;
3666 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3667 vlnctrl &= ~IXGBE_RXDCTL_VME;
3668 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3669 }
3670 break;
3671 default:
3672 break;
3673 }
3674 }
3675
3676 /**
3677 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3678 * @adapter: driver data
3679 */
3680 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3681 {
3682 struct ixgbe_hw *hw = &adapter->hw;
3683 u32 vlnctrl;
3684 int i, j;
3685
3686 switch (hw->mac.type) {
3687 case ixgbe_mac_82598EB:
3688 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3689 vlnctrl |= IXGBE_VLNCTRL_VME;
3690 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3691 break;
3692 case ixgbe_mac_82599EB:
3693 case ixgbe_mac_X540:
3694 for (i = 0; i < adapter->num_rx_queues; i++) {
3695 struct ixgbe_ring *ring = adapter->rx_ring[i];
3696
3697 if (ring->l2_accel_priv)
3698 continue;
3699 j = ring->reg_idx;
3700 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3701 vlnctrl |= IXGBE_RXDCTL_VME;
3702 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3703 }
3704 break;
3705 default:
3706 break;
3707 }
3708 }
3709
3710 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3711 {
3712 u16 vid;
3713
3714 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
3715
3716 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3717 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
3718 }
3719
3720 /**
3721 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
3722 * @netdev: network interface device structure
3723 *
3724 * Writes multicast address list to the MTA hash table.
3725 * Returns: -ENOMEM on failure
3726 * 0 on no addresses written
3727 * X on writing X addresses to MTA
3728 **/
3729 static int ixgbe_write_mc_addr_list(struct net_device *netdev)
3730 {
3731 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3732 struct ixgbe_hw *hw = &adapter->hw;
3733
3734 if (!netif_running(netdev))
3735 return 0;
3736
3737 if (hw->mac.ops.update_mc_addr_list)
3738 hw->mac.ops.update_mc_addr_list(hw, netdev);
3739 else
3740 return -ENOMEM;
3741
3742 #ifdef CONFIG_PCI_IOV
3743 ixgbe_restore_vf_multicasts(adapter);
3744 #endif
3745
3746 return netdev_mc_count(netdev);
3747 }
3748
3749 #ifdef CONFIG_PCI_IOV
3750 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
3751 {
3752 struct ixgbe_hw *hw = &adapter->hw;
3753 int i;
3754 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3755 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3756 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
3757 adapter->mac_table[i].queue,
3758 IXGBE_RAH_AV);
3759 else
3760 hw->mac.ops.clear_rar(hw, i);
3761
3762 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED);
3763 }
3764 }
3765 #endif
3766
3767 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
3768 {
3769 struct ixgbe_hw *hw = &adapter->hw;
3770 int i;
3771 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3772 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
3773 if (adapter->mac_table[i].state &
3774 IXGBE_MAC_STATE_IN_USE)
3775 hw->mac.ops.set_rar(hw, i,
3776 adapter->mac_table[i].addr,
3777 adapter->mac_table[i].queue,
3778 IXGBE_RAH_AV);
3779 else
3780 hw->mac.ops.clear_rar(hw, i);
3781
3782 adapter->mac_table[i].state &=
3783 ~(IXGBE_MAC_STATE_MODIFIED);
3784 }
3785 }
3786 }
3787
3788 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
3789 {
3790 int i;
3791 struct ixgbe_hw *hw = &adapter->hw;
3792
3793 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3794 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3795 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
3796 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
3797 adapter->mac_table[i].queue = 0;
3798 }
3799 ixgbe_sync_mac_table(adapter);
3800 }
3801
3802 static int ixgbe_available_rars(struct ixgbe_adapter *adapter)
3803 {
3804 struct ixgbe_hw *hw = &adapter->hw;
3805 int i, count = 0;
3806
3807 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3808 if (adapter->mac_table[i].state == 0)
3809 count++;
3810 }
3811 return count;
3812 }
3813
3814 /* this function destroys the first RAR entry */
3815 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter,
3816 u8 *addr)
3817 {
3818 struct ixgbe_hw *hw = &adapter->hw;
3819
3820 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN);
3821 adapter->mac_table[0].queue = VMDQ_P(0);
3822 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
3823 IXGBE_MAC_STATE_IN_USE);
3824 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
3825 adapter->mac_table[0].queue,
3826 IXGBE_RAH_AV);
3827 }
3828
3829 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3830 {
3831 struct ixgbe_hw *hw = &adapter->hw;
3832 int i;
3833
3834 if (is_zero_ether_addr(addr))
3835 return -EINVAL;
3836
3837 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3838 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3839 continue;
3840 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
3841 IXGBE_MAC_STATE_IN_USE);
3842 ether_addr_copy(adapter->mac_table[i].addr, addr);
3843 adapter->mac_table[i].queue = queue;
3844 ixgbe_sync_mac_table(adapter);
3845 return i;
3846 }
3847 return -ENOMEM;
3848 }
3849
3850 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3851 {
3852 /* search table for addr, if found, set to 0 and sync */
3853 int i;
3854 struct ixgbe_hw *hw = &adapter->hw;
3855
3856 if (is_zero_ether_addr(addr))
3857 return -EINVAL;
3858
3859 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3860 if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
3861 adapter->mac_table[i].queue == queue) {
3862 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3863 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
3864 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
3865 adapter->mac_table[i].queue = 0;
3866 ixgbe_sync_mac_table(adapter);
3867 return 0;
3868 }
3869 }
3870 return -ENOMEM;
3871 }
3872 /**
3873 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3874 * @netdev: network interface device structure
3875 *
3876 * Writes unicast address list to the RAR table.
3877 * Returns: -ENOMEM on failure/insufficient address space
3878 * 0 on no addresses written
3879 * X on writing X addresses to the RAR table
3880 **/
3881 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
3882 {
3883 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3884 int count = 0;
3885
3886 /* return ENOMEM indicating insufficient memory for addresses */
3887 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
3888 return -ENOMEM;
3889
3890 if (!netdev_uc_empty(netdev)) {
3891 struct netdev_hw_addr *ha;
3892 netdev_for_each_uc_addr(ha, netdev) {
3893 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
3894 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
3895 count++;
3896 }
3897 }
3898 return count;
3899 }
3900
3901 /**
3902 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3903 * @netdev: network interface device structure
3904 *
3905 * The set_rx_method entry point is called whenever the unicast/multicast
3906 * address list or the network interface flags are updated. This routine is
3907 * responsible for configuring the hardware for proper unicast, multicast and
3908 * promiscuous mode.
3909 **/
3910 void ixgbe_set_rx_mode(struct net_device *netdev)
3911 {
3912 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3913 struct ixgbe_hw *hw = &adapter->hw;
3914 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3915 u32 vlnctrl;
3916 int count;
3917
3918 /* Check for Promiscuous and All Multicast modes */
3919 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3920 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3921
3922 /* set all bits that we expect to always be set */
3923 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3924 fctrl |= IXGBE_FCTRL_BAM;
3925 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3926 fctrl |= IXGBE_FCTRL_PMCF;
3927
3928 /* clear the bits we are changing the status of */
3929 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3930 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3931 if (netdev->flags & IFF_PROMISC) {
3932 hw->addr_ctrl.user_set_promisc = true;
3933 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3934 vmolr |= IXGBE_VMOLR_MPE;
3935 /* Only disable hardware filter vlans in promiscuous mode
3936 * if SR-IOV and VMDQ are disabled - otherwise ensure
3937 * that hardware VLAN filters remain enabled.
3938 */
3939 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
3940 IXGBE_FLAG_SRIOV_ENABLED))
3941 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3942 } else {
3943 if (netdev->flags & IFF_ALLMULTI) {
3944 fctrl |= IXGBE_FCTRL_MPE;
3945 vmolr |= IXGBE_VMOLR_MPE;
3946 }
3947 vlnctrl |= IXGBE_VLNCTRL_VFE;
3948 hw->addr_ctrl.user_set_promisc = false;
3949 }
3950
3951 /*
3952 * Write addresses to available RAR registers, if there is not
3953 * sufficient space to store all the addresses then enable
3954 * unicast promiscuous mode
3955 */
3956 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0));
3957 if (count < 0) {
3958 fctrl |= IXGBE_FCTRL_UPE;
3959 vmolr |= IXGBE_VMOLR_ROPE;
3960 }
3961
3962 /* Write addresses to the MTA, if the attempt fails
3963 * then we should just turn on promiscuous mode so
3964 * that we can at least receive multicast traffic
3965 */
3966 count = ixgbe_write_mc_addr_list(netdev);
3967 if (count < 0) {
3968 fctrl |= IXGBE_FCTRL_MPE;
3969 vmolr |= IXGBE_VMOLR_MPE;
3970 } else if (count) {
3971 vmolr |= IXGBE_VMOLR_ROMPE;
3972 }
3973
3974 if (hw->mac.type != ixgbe_mac_82598EB) {
3975 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
3976 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3977 IXGBE_VMOLR_ROPE);
3978 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
3979 }
3980
3981 /* This is useful for sniffing bad packets. */
3982 if (adapter->netdev->features & NETIF_F_RXALL) {
3983 /* UPE and MPE will be handled by normal PROMISC logic
3984 * in e1000e_set_rx_mode */
3985 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3986 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3987 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3988
3989 fctrl &= ~(IXGBE_FCTRL_DPF);
3990 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3991 }
3992
3993 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3994 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3995
3996 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3997 ixgbe_vlan_strip_enable(adapter);
3998 else
3999 ixgbe_vlan_strip_disable(adapter);
4000 }
4001
4002 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4003 {
4004 int q_idx;
4005
4006 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4007 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
4008 napi_enable(&adapter->q_vector[q_idx]->napi);
4009 }
4010 }
4011
4012 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4013 {
4014 int q_idx;
4015
4016 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4017 napi_disable(&adapter->q_vector[q_idx]->napi);
4018 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
4019 pr_info("QV %d locked\n", q_idx);
4020 usleep_range(1000, 20000);
4021 }
4022 }
4023 }
4024
4025 #ifdef CONFIG_IXGBE_DCB
4026 /**
4027 * ixgbe_configure_dcb - Configure DCB hardware
4028 * @adapter: ixgbe adapter struct
4029 *
4030 * This is called by the driver on open to configure the DCB hardware.
4031 * This is also called by the gennetlink interface when reconfiguring
4032 * the DCB state.
4033 */
4034 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4035 {
4036 struct ixgbe_hw *hw = &adapter->hw;
4037 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4038
4039 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4040 if (hw->mac.type == ixgbe_mac_82598EB)
4041 netif_set_gso_max_size(adapter->netdev, 65536);
4042 return;
4043 }
4044
4045 if (hw->mac.type == ixgbe_mac_82598EB)
4046 netif_set_gso_max_size(adapter->netdev, 32768);
4047
4048 #ifdef IXGBE_FCOE
4049 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4050 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
4051 #endif
4052
4053 /* reconfigure the hardware */
4054 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
4055 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4056 DCB_TX_CONFIG);
4057 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4058 DCB_RX_CONFIG);
4059 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
4060 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4061 ixgbe_dcb_hw_ets(&adapter->hw,
4062 adapter->ixgbe_ieee_ets,
4063 max_frame);
4064 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4065 adapter->ixgbe_ieee_pfc->pfc_en,
4066 adapter->ixgbe_ieee_ets->prio_tc);
4067 }
4068
4069 /* Enable RSS Hash per TC */
4070 if (hw->mac.type != ixgbe_mac_82598EB) {
4071 u32 msb = 0;
4072 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
4073
4074 while (rss_i) {
4075 msb++;
4076 rss_i >>= 1;
4077 }
4078
4079 /* write msb to all 8 TCs in one write */
4080 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
4081 }
4082 }
4083 #endif
4084
4085 /* Additional bittime to account for IXGBE framing */
4086 #define IXGBE_ETH_FRAMING 20
4087
4088 /**
4089 * ixgbe_hpbthresh - calculate high water mark for flow control
4090 *
4091 * @adapter: board private structure to calculate for
4092 * @pb: packet buffer to calculate
4093 */
4094 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4095 {
4096 struct ixgbe_hw *hw = &adapter->hw;
4097 struct net_device *dev = adapter->netdev;
4098 int link, tc, kb, marker;
4099 u32 dv_id, rx_pba;
4100
4101 /* Calculate max LAN frame size */
4102 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4103
4104 #ifdef IXGBE_FCOE
4105 /* FCoE traffic class uses FCOE jumbo frames */
4106 if ((dev->features & NETIF_F_FCOE_MTU) &&
4107 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4108 (pb == ixgbe_fcoe_get_tc(adapter)))
4109 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4110 #endif
4111
4112 /* Calculate delay value for device */
4113 switch (hw->mac.type) {
4114 case ixgbe_mac_X540:
4115 dv_id = IXGBE_DV_X540(link, tc);
4116 break;
4117 default:
4118 dv_id = IXGBE_DV(link, tc);
4119 break;
4120 }
4121
4122 /* Loopback switch introduces additional latency */
4123 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4124 dv_id += IXGBE_B2BT(tc);
4125
4126 /* Delay value is calculated in bit times convert to KB */
4127 kb = IXGBE_BT2KB(dv_id);
4128 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4129
4130 marker = rx_pba - kb;
4131
4132 /* It is possible that the packet buffer is not large enough
4133 * to provide required headroom. In this case throw an error
4134 * to user and a do the best we can.
4135 */
4136 if (marker < 0) {
4137 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4138 "headroom to support flow control."
4139 "Decrease MTU or number of traffic classes\n", pb);
4140 marker = tc + 1;
4141 }
4142
4143 return marker;
4144 }
4145
4146 /**
4147 * ixgbe_lpbthresh - calculate low water mark for for flow control
4148 *
4149 * @adapter: board private structure to calculate for
4150 * @pb: packet buffer to calculate
4151 */
4152 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
4153 {
4154 struct ixgbe_hw *hw = &adapter->hw;
4155 struct net_device *dev = adapter->netdev;
4156 int tc;
4157 u32 dv_id;
4158
4159 /* Calculate max LAN frame size */
4160 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4161
4162 #ifdef IXGBE_FCOE
4163 /* FCoE traffic class uses FCOE jumbo frames */
4164 if ((dev->features & NETIF_F_FCOE_MTU) &&
4165 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4166 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4167 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4168 #endif
4169
4170 /* Calculate delay value for device */
4171 switch (hw->mac.type) {
4172 case ixgbe_mac_X540:
4173 dv_id = IXGBE_LOW_DV_X540(tc);
4174 break;
4175 default:
4176 dv_id = IXGBE_LOW_DV(tc);
4177 break;
4178 }
4179
4180 /* Delay value is calculated in bit times convert to KB */
4181 return IXGBE_BT2KB(dv_id);
4182 }
4183
4184 /*
4185 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4186 */
4187 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4188 {
4189 struct ixgbe_hw *hw = &adapter->hw;
4190 int num_tc = netdev_get_num_tc(adapter->netdev);
4191 int i;
4192
4193 if (!num_tc)
4194 num_tc = 1;
4195
4196 for (i = 0; i < num_tc; i++) {
4197 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4198 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
4199
4200 /* Low water marks must not be larger than high water marks */
4201 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4202 hw->fc.low_water[i] = 0;
4203 }
4204
4205 for (; i < MAX_TRAFFIC_CLASS; i++)
4206 hw->fc.high_water[i] = 0;
4207 }
4208
4209 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4210 {
4211 struct ixgbe_hw *hw = &adapter->hw;
4212 int hdrm;
4213 u8 tc = netdev_get_num_tc(adapter->netdev);
4214
4215 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4216 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4217 hdrm = 32 << adapter->fdir_pballoc;
4218 else
4219 hdrm = 0;
4220
4221 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
4222 ixgbe_pbthresh_setup(adapter);
4223 }
4224
4225 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4226 {
4227 struct ixgbe_hw *hw = &adapter->hw;
4228 struct hlist_node *node2;
4229 struct ixgbe_fdir_filter *filter;
4230
4231 spin_lock(&adapter->fdir_perfect_lock);
4232
4233 if (!hlist_empty(&adapter->fdir_filter_list))
4234 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4235
4236 hlist_for_each_entry_safe(filter, node2,
4237 &adapter->fdir_filter_list, fdir_node) {
4238 ixgbe_fdir_write_perfect_filter_82599(hw,
4239 &filter->filter,
4240 filter->sw_idx,
4241 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4242 IXGBE_FDIR_DROP_QUEUE :
4243 adapter->rx_ring[filter->action]->reg_idx);
4244 }
4245
4246 spin_unlock(&adapter->fdir_perfect_lock);
4247 }
4248
4249 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4250 struct ixgbe_adapter *adapter)
4251 {
4252 struct ixgbe_hw *hw = &adapter->hw;
4253 u32 vmolr;
4254
4255 /* No unicast promiscuous support for VMDQ devices. */
4256 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4257 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4258
4259 /* clear the affected bit */
4260 vmolr &= ~IXGBE_VMOLR_MPE;
4261
4262 if (dev->flags & IFF_ALLMULTI) {
4263 vmolr |= IXGBE_VMOLR_MPE;
4264 } else {
4265 vmolr |= IXGBE_VMOLR_ROMPE;
4266 hw->mac.ops.update_mc_addr_list(hw, dev);
4267 }
4268 ixgbe_write_uc_addr_list(adapter->netdev, pool);
4269 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4270 }
4271
4272 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4273 {
4274 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4275 int rss_i = adapter->num_rx_queues_per_pool;
4276 struct ixgbe_hw *hw = &adapter->hw;
4277 u16 pool = vadapter->pool;
4278 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4279 IXGBE_PSRTYPE_UDPHDR |
4280 IXGBE_PSRTYPE_IPV4HDR |
4281 IXGBE_PSRTYPE_L2HDR |
4282 IXGBE_PSRTYPE_IPV6HDR;
4283
4284 if (hw->mac.type == ixgbe_mac_82598EB)
4285 return;
4286
4287 if (rss_i > 3)
4288 psrtype |= 2 << 29;
4289 else if (rss_i > 1)
4290 psrtype |= 1 << 29;
4291
4292 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4293 }
4294
4295 /**
4296 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4297 * @rx_ring: ring to free buffers from
4298 **/
4299 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4300 {
4301 struct device *dev = rx_ring->dev;
4302 unsigned long size;
4303 u16 i;
4304
4305 /* ring already cleared, nothing to do */
4306 if (!rx_ring->rx_buffer_info)
4307 return;
4308
4309 /* Free all the Rx ring sk_buffs */
4310 for (i = 0; i < rx_ring->count; i++) {
4311 struct ixgbe_rx_buffer *rx_buffer;
4312
4313 rx_buffer = &rx_ring->rx_buffer_info[i];
4314 if (rx_buffer->skb) {
4315 struct sk_buff *skb = rx_buffer->skb;
4316 if (IXGBE_CB(skb)->page_released) {
4317 dma_unmap_page(dev,
4318 IXGBE_CB(skb)->dma,
4319 ixgbe_rx_bufsz(rx_ring),
4320 DMA_FROM_DEVICE);
4321 IXGBE_CB(skb)->page_released = false;
4322 }
4323 dev_kfree_skb(skb);
4324 rx_buffer->skb = NULL;
4325 }
4326 if (rx_buffer->dma)
4327 dma_unmap_page(dev, rx_buffer->dma,
4328 ixgbe_rx_pg_size(rx_ring),
4329 DMA_FROM_DEVICE);
4330 rx_buffer->dma = 0;
4331 if (rx_buffer->page)
4332 __free_pages(rx_buffer->page,
4333 ixgbe_rx_pg_order(rx_ring));
4334 rx_buffer->page = NULL;
4335 }
4336
4337 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4338 memset(rx_ring->rx_buffer_info, 0, size);
4339
4340 /* Zero out the descriptor ring */
4341 memset(rx_ring->desc, 0, rx_ring->size);
4342
4343 rx_ring->next_to_alloc = 0;
4344 rx_ring->next_to_clean = 0;
4345 rx_ring->next_to_use = 0;
4346 }
4347
4348 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4349 struct ixgbe_ring *rx_ring)
4350 {
4351 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4352 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4353
4354 /* shutdown specific queue receive and wait for dma to settle */
4355 ixgbe_disable_rx_queue(adapter, rx_ring);
4356 usleep_range(10000, 20000);
4357 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4358 ixgbe_clean_rx_ring(rx_ring);
4359 rx_ring->l2_accel_priv = NULL;
4360 }
4361
4362 static int ixgbe_fwd_ring_down(struct net_device *vdev,
4363 struct ixgbe_fwd_adapter *accel)
4364 {
4365 struct ixgbe_adapter *adapter = accel->real_adapter;
4366 unsigned int rxbase = accel->rx_base_queue;
4367 unsigned int txbase = accel->tx_base_queue;
4368 int i;
4369
4370 netif_tx_stop_all_queues(vdev);
4371
4372 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4373 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4374 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4375 }
4376
4377 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4378 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4379 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4380 }
4381
4382
4383 return 0;
4384 }
4385
4386 static int ixgbe_fwd_ring_up(struct net_device *vdev,
4387 struct ixgbe_fwd_adapter *accel)
4388 {
4389 struct ixgbe_adapter *adapter = accel->real_adapter;
4390 unsigned int rxbase, txbase, queues;
4391 int i, baseq, err = 0;
4392
4393 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4394 return 0;
4395
4396 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4397 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4398 accel->pool, adapter->num_rx_pools,
4399 baseq, baseq + adapter->num_rx_queues_per_pool,
4400 adapter->fwd_bitmask);
4401
4402 accel->netdev = vdev;
4403 accel->rx_base_queue = rxbase = baseq;
4404 accel->tx_base_queue = txbase = baseq;
4405
4406 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4407 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4408
4409 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4410 adapter->rx_ring[rxbase + i]->netdev = vdev;
4411 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4412 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4413 }
4414
4415 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4416 adapter->tx_ring[txbase + i]->netdev = vdev;
4417 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4418 }
4419
4420 queues = min_t(unsigned int,
4421 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4422 err = netif_set_real_num_tx_queues(vdev, queues);
4423 if (err)
4424 goto fwd_queue_err;
4425
4426 err = netif_set_real_num_rx_queues(vdev, queues);
4427 if (err)
4428 goto fwd_queue_err;
4429
4430 if (is_valid_ether_addr(vdev->dev_addr))
4431 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4432
4433 ixgbe_fwd_psrtype(accel);
4434 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4435 return err;
4436 fwd_queue_err:
4437 ixgbe_fwd_ring_down(vdev, accel);
4438 return err;
4439 }
4440
4441 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4442 {
4443 struct net_device *upper;
4444 struct list_head *iter;
4445 int err;
4446
4447 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4448 if (netif_is_macvlan(upper)) {
4449 struct macvlan_dev *dfwd = netdev_priv(upper);
4450 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4451
4452 if (dfwd->fwd_priv) {
4453 err = ixgbe_fwd_ring_up(upper, vadapter);
4454 if (err)
4455 continue;
4456 }
4457 }
4458 }
4459 }
4460
4461 static void ixgbe_configure(struct ixgbe_adapter *adapter)
4462 {
4463 struct ixgbe_hw *hw = &adapter->hw;
4464
4465 ixgbe_configure_pb(adapter);
4466 #ifdef CONFIG_IXGBE_DCB
4467 ixgbe_configure_dcb(adapter);
4468 #endif
4469 /*
4470 * We must restore virtualization before VLANs or else
4471 * the VLVF registers will not be populated
4472 */
4473 ixgbe_configure_virtualization(adapter);
4474
4475 ixgbe_set_rx_mode(adapter->netdev);
4476 ixgbe_restore_vlan(adapter);
4477
4478 switch (hw->mac.type) {
4479 case ixgbe_mac_82599EB:
4480 case ixgbe_mac_X540:
4481 hw->mac.ops.disable_rx_buff(hw);
4482 break;
4483 default:
4484 break;
4485 }
4486
4487 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4488 ixgbe_init_fdir_signature_82599(&adapter->hw,
4489 adapter->fdir_pballoc);
4490 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4491 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4492 adapter->fdir_pballoc);
4493 ixgbe_fdir_filter_restore(adapter);
4494 }
4495
4496 switch (hw->mac.type) {
4497 case ixgbe_mac_82599EB:
4498 case ixgbe_mac_X540:
4499 hw->mac.ops.enable_rx_buff(hw);
4500 break;
4501 default:
4502 break;
4503 }
4504
4505 #ifdef IXGBE_FCOE
4506 /* configure FCoE L2 filters, redirection table, and Rx control */
4507 ixgbe_configure_fcoe(adapter);
4508
4509 #endif /* IXGBE_FCOE */
4510 ixgbe_configure_tx(adapter);
4511 ixgbe_configure_rx(adapter);
4512 ixgbe_configure_dfwd(adapter);
4513 }
4514
4515 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4516 {
4517 switch (hw->phy.type) {
4518 case ixgbe_phy_sfp_avago:
4519 case ixgbe_phy_sfp_ftl:
4520 case ixgbe_phy_sfp_intel:
4521 case ixgbe_phy_sfp_unknown:
4522 case ixgbe_phy_sfp_passive_tyco:
4523 case ixgbe_phy_sfp_passive_unknown:
4524 case ixgbe_phy_sfp_active_unknown:
4525 case ixgbe_phy_sfp_ftl_active:
4526 case ixgbe_phy_qsfp_passive_unknown:
4527 case ixgbe_phy_qsfp_active_unknown:
4528 case ixgbe_phy_qsfp_intel:
4529 case ixgbe_phy_qsfp_unknown:
4530 /* ixgbe_phy_none is set when no SFP module is present */
4531 case ixgbe_phy_none:
4532 return true;
4533 case ixgbe_phy_nl:
4534 if (hw->mac.type == ixgbe_mac_82598EB)
4535 return true;
4536 default:
4537 return false;
4538 }
4539 }
4540
4541 /**
4542 * ixgbe_sfp_link_config - set up SFP+ link
4543 * @adapter: pointer to private adapter struct
4544 **/
4545 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4546 {
4547 /*
4548 * We are assuming the worst case scenario here, and that
4549 * is that an SFP was inserted/removed after the reset
4550 * but before SFP detection was enabled. As such the best
4551 * solution is to just start searching as soon as we start
4552 */
4553 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4554 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4555
4556 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4557 }
4558
4559 /**
4560 * ixgbe_non_sfp_link_config - set up non-SFP+ link
4561 * @hw: pointer to private hardware struct
4562 *
4563 * Returns 0 on success, negative on failure
4564 **/
4565 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4566 {
4567 u32 speed;
4568 bool autoneg, link_up = false;
4569 u32 ret = IXGBE_ERR_LINK_SETUP;
4570
4571 if (hw->mac.ops.check_link)
4572 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
4573
4574 if (ret)
4575 return ret;
4576
4577 speed = hw->phy.autoneg_advertised;
4578 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4579 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4580 &autoneg);
4581 if (ret)
4582 return ret;
4583
4584 if (hw->mac.ops.setup_link)
4585 ret = hw->mac.ops.setup_link(hw, speed, link_up);
4586
4587 return ret;
4588 }
4589
4590 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4591 {
4592 struct ixgbe_hw *hw = &adapter->hw;
4593 u32 gpie = 0;
4594
4595 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4596 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4597 IXGBE_GPIE_OCD;
4598 gpie |= IXGBE_GPIE_EIAME;
4599 /*
4600 * use EIAM to auto-mask when MSI-X interrupt is asserted
4601 * this saves a register write for every interrupt
4602 */
4603 switch (hw->mac.type) {
4604 case ixgbe_mac_82598EB:
4605 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4606 break;
4607 case ixgbe_mac_82599EB:
4608 case ixgbe_mac_X540:
4609 default:
4610 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4611 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4612 break;
4613 }
4614 } else {
4615 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4616 * specifically only auto mask tx and rx interrupts */
4617 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4618 }
4619
4620 /* XXX: to interrupt immediately for EICS writes, enable this */
4621 /* gpie |= IXGBE_GPIE_EIMEN; */
4622
4623 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4624 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4625
4626 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4627 case IXGBE_82599_VMDQ_8Q_MASK:
4628 gpie |= IXGBE_GPIE_VTMODE_16;
4629 break;
4630 case IXGBE_82599_VMDQ_4Q_MASK:
4631 gpie |= IXGBE_GPIE_VTMODE_32;
4632 break;
4633 default:
4634 gpie |= IXGBE_GPIE_VTMODE_64;
4635 break;
4636 }
4637 }
4638
4639 /* Enable Thermal over heat sensor interrupt */
4640 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4641 switch (adapter->hw.mac.type) {
4642 case ixgbe_mac_82599EB:
4643 gpie |= IXGBE_SDP0_GPIEN;
4644 break;
4645 case ixgbe_mac_X540:
4646 gpie |= IXGBE_EIMS_TS;
4647 break;
4648 default:
4649 break;
4650 }
4651 }
4652
4653 /* Enable fan failure interrupt */
4654 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4655 gpie |= IXGBE_SDP1_GPIEN;
4656
4657 if (hw->mac.type == ixgbe_mac_82599EB) {
4658 gpie |= IXGBE_SDP1_GPIEN;
4659 gpie |= IXGBE_SDP2_GPIEN;
4660 }
4661
4662 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4663 }
4664
4665 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4666 {
4667 struct ixgbe_hw *hw = &adapter->hw;
4668 int err;
4669 u32 ctrl_ext;
4670
4671 ixgbe_get_hw_control(adapter);
4672 ixgbe_setup_gpie(adapter);
4673
4674 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4675 ixgbe_configure_msix(adapter);
4676 else
4677 ixgbe_configure_msi_and_legacy(adapter);
4678
4679 /* enable the optics for 82599 SFP+ fiber */
4680 if (hw->mac.ops.enable_tx_laser)
4681 hw->mac.ops.enable_tx_laser(hw);
4682
4683 smp_mb__before_atomic();
4684 clear_bit(__IXGBE_DOWN, &adapter->state);
4685 ixgbe_napi_enable_all(adapter);
4686
4687 if (ixgbe_is_sfp(hw)) {
4688 ixgbe_sfp_link_config(adapter);
4689 } else {
4690 err = ixgbe_non_sfp_link_config(hw);
4691 if (err)
4692 e_err(probe, "link_config FAILED %d\n", err);
4693 }
4694
4695 /* clear any pending interrupts, may auto mask */
4696 IXGBE_READ_REG(hw, IXGBE_EICR);
4697 ixgbe_irq_enable(adapter, true, true);
4698
4699 /*
4700 * If this adapter has a fan, check to see if we had a failure
4701 * before we enabled the interrupt.
4702 */
4703 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4704 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4705 if (esdp & IXGBE_ESDP_SDP1)
4706 e_crit(drv, "Fan has stopped, replace the adapter\n");
4707 }
4708
4709 /* bring the link up in the watchdog, this could race with our first
4710 * link up interrupt but shouldn't be a problem */
4711 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4712 adapter->link_check_timeout = jiffies;
4713 mod_timer(&adapter->service_timer, jiffies);
4714
4715 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4716 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4717 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4718 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4719 }
4720
4721 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4722 {
4723 WARN_ON(in_interrupt());
4724 /* put off any impending NetWatchDogTimeout */
4725 adapter->netdev->trans_start = jiffies;
4726
4727 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4728 usleep_range(1000, 2000);
4729 ixgbe_down(adapter);
4730 /*
4731 * If SR-IOV enabled then wait a bit before bringing the adapter
4732 * back up to give the VFs time to respond to the reset. The
4733 * two second wait is based upon the watchdog timer cycle in
4734 * the VF driver.
4735 */
4736 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4737 msleep(2000);
4738 ixgbe_up(adapter);
4739 clear_bit(__IXGBE_RESETTING, &adapter->state);
4740 }
4741
4742 void ixgbe_up(struct ixgbe_adapter *adapter)
4743 {
4744 /* hardware has been reset, we need to reload some things */
4745 ixgbe_configure(adapter);
4746
4747 ixgbe_up_complete(adapter);
4748 }
4749
4750 void ixgbe_reset(struct ixgbe_adapter *adapter)
4751 {
4752 struct ixgbe_hw *hw = &adapter->hw;
4753 struct net_device *netdev = adapter->netdev;
4754 int err;
4755 u8 old_addr[ETH_ALEN];
4756
4757 if (ixgbe_removed(hw->hw_addr))
4758 return;
4759 /* lock SFP init bit to prevent race conditions with the watchdog */
4760 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4761 usleep_range(1000, 2000);
4762
4763 /* clear all SFP and link config related flags while holding SFP_INIT */
4764 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4765 IXGBE_FLAG2_SFP_NEEDS_RESET);
4766 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4767
4768 err = hw->mac.ops.init_hw(hw);
4769 switch (err) {
4770 case 0:
4771 case IXGBE_ERR_SFP_NOT_PRESENT:
4772 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4773 break;
4774 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4775 e_dev_err("master disable timed out\n");
4776 break;
4777 case IXGBE_ERR_EEPROM_VERSION:
4778 /* We are running on a pre-production device, log a warning */
4779 e_dev_warn("This device is a pre-production adapter/LOM. "
4780 "Please be aware there may be issues associated with "
4781 "your hardware. If you are experiencing problems "
4782 "please contact your Intel or hardware "
4783 "representative who provided you with this "
4784 "hardware.\n");
4785 break;
4786 default:
4787 e_dev_err("Hardware Error: %d\n", err);
4788 }
4789
4790 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4791 /* do not flush user set addresses */
4792 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len);
4793 ixgbe_flush_sw_mac_table(adapter);
4794 ixgbe_mac_set_default_filter(adapter, old_addr);
4795
4796 /* update SAN MAC vmdq pool selection */
4797 if (hw->mac.san_mac_rar_index)
4798 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4799
4800 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
4801 ixgbe_ptp_reset(adapter);
4802 }
4803
4804 /**
4805 * ixgbe_clean_tx_ring - Free Tx Buffers
4806 * @tx_ring: ring to be cleaned
4807 **/
4808 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4809 {
4810 struct ixgbe_tx_buffer *tx_buffer_info;
4811 unsigned long size;
4812 u16 i;
4813
4814 /* ring already cleared, nothing to do */
4815 if (!tx_ring->tx_buffer_info)
4816 return;
4817
4818 /* Free all the Tx ring sk_buffs */
4819 for (i = 0; i < tx_ring->count; i++) {
4820 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4821 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4822 }
4823
4824 netdev_tx_reset_queue(txring_txq(tx_ring));
4825
4826 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4827 memset(tx_ring->tx_buffer_info, 0, size);
4828
4829 /* Zero out the descriptor ring */
4830 memset(tx_ring->desc, 0, tx_ring->size);
4831
4832 tx_ring->next_to_use = 0;
4833 tx_ring->next_to_clean = 0;
4834 }
4835
4836 /**
4837 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4838 * @adapter: board private structure
4839 **/
4840 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4841 {
4842 int i;
4843
4844 for (i = 0; i < adapter->num_rx_queues; i++)
4845 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4846 }
4847
4848 /**
4849 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4850 * @adapter: board private structure
4851 **/
4852 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4853 {
4854 int i;
4855
4856 for (i = 0; i < adapter->num_tx_queues; i++)
4857 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4858 }
4859
4860 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4861 {
4862 struct hlist_node *node2;
4863 struct ixgbe_fdir_filter *filter;
4864
4865 spin_lock(&adapter->fdir_perfect_lock);
4866
4867 hlist_for_each_entry_safe(filter, node2,
4868 &adapter->fdir_filter_list, fdir_node) {
4869 hlist_del(&filter->fdir_node);
4870 kfree(filter);
4871 }
4872 adapter->fdir_filter_count = 0;
4873
4874 spin_unlock(&adapter->fdir_perfect_lock);
4875 }
4876
4877 void ixgbe_down(struct ixgbe_adapter *adapter)
4878 {
4879 struct net_device *netdev = adapter->netdev;
4880 struct ixgbe_hw *hw = &adapter->hw;
4881 struct net_device *upper;
4882 struct list_head *iter;
4883 u32 rxctrl;
4884 int i;
4885
4886 /* signal that we are down to the interrupt handler */
4887 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
4888 return; /* do nothing if already down */
4889
4890 /* disable receives */
4891 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4892 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4893
4894 /* disable all enabled rx queues */
4895 for (i = 0; i < adapter->num_rx_queues; i++)
4896 /* this call also flushes the previous write */
4897 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4898
4899 usleep_range(10000, 20000);
4900
4901 netif_tx_stop_all_queues(netdev);
4902
4903 /* call carrier off first to avoid false dev_watchdog timeouts */
4904 netif_carrier_off(netdev);
4905 netif_tx_disable(netdev);
4906
4907 /* disable any upper devices */
4908 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4909 if (netif_is_macvlan(upper)) {
4910 struct macvlan_dev *vlan = netdev_priv(upper);
4911
4912 if (vlan->fwd_priv) {
4913 netif_tx_stop_all_queues(upper);
4914 netif_carrier_off(upper);
4915 netif_tx_disable(upper);
4916 }
4917 }
4918 }
4919
4920 ixgbe_irq_disable(adapter);
4921
4922 ixgbe_napi_disable_all(adapter);
4923
4924 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4925 IXGBE_FLAG2_RESET_REQUESTED);
4926 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4927
4928 del_timer_sync(&adapter->service_timer);
4929
4930 if (adapter->num_vfs) {
4931 /* Clear EITR Select mapping */
4932 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4933
4934 /* Mark all the VFs as inactive */
4935 for (i = 0 ; i < adapter->num_vfs; i++)
4936 adapter->vfinfo[i].clear_to_send = false;
4937
4938 /* ping all the active vfs to let them know we are going down */
4939 ixgbe_ping_all_vfs(adapter);
4940
4941 /* Disable all VFTE/VFRE TX/RX */
4942 ixgbe_disable_tx_rx(adapter);
4943 }
4944
4945 /* disable transmits in the hardware now that interrupts are off */
4946 for (i = 0; i < adapter->num_tx_queues; i++) {
4947 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4948 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4949 }
4950
4951 /* Disable the Tx DMA engine on 82599 and X540 */
4952 switch (hw->mac.type) {
4953 case ixgbe_mac_82599EB:
4954 case ixgbe_mac_X540:
4955 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4956 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4957 ~IXGBE_DMATXCTL_TE));
4958 break;
4959 default:
4960 break;
4961 }
4962
4963 if (!pci_channel_offline(adapter->pdev))
4964 ixgbe_reset(adapter);
4965
4966 /* power down the optics for 82599 SFP+ fiber */
4967 if (hw->mac.ops.disable_tx_laser)
4968 hw->mac.ops.disable_tx_laser(hw);
4969
4970 ixgbe_clean_all_tx_rings(adapter);
4971 ixgbe_clean_all_rx_rings(adapter);
4972
4973 #ifdef CONFIG_IXGBE_DCA
4974 /* since we reset the hardware DCA settings were cleared */
4975 ixgbe_setup_dca(adapter);
4976 #endif
4977 }
4978
4979 /**
4980 * ixgbe_tx_timeout - Respond to a Tx Hang
4981 * @netdev: network interface device structure
4982 **/
4983 static void ixgbe_tx_timeout(struct net_device *netdev)
4984 {
4985 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4986
4987 /* Do the reset outside of interrupt context */
4988 ixgbe_tx_timeout_reset(adapter);
4989 }
4990
4991 /**
4992 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4993 * @adapter: board private structure to initialize
4994 *
4995 * ixgbe_sw_init initializes the Adapter private data structure.
4996 * Fields are initialized based on PCI device information and
4997 * OS network device settings (MTU size).
4998 **/
4999 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
5000 {
5001 struct ixgbe_hw *hw = &adapter->hw;
5002 struct pci_dev *pdev = adapter->pdev;
5003 unsigned int rss, fdir;
5004 u32 fwsm;
5005 #ifdef CONFIG_IXGBE_DCB
5006 int j;
5007 struct tc_configuration *tc;
5008 #endif
5009
5010 /* PCI config space info */
5011
5012 hw->vendor_id = pdev->vendor;
5013 hw->device_id = pdev->device;
5014 hw->revision_id = pdev->revision;
5015 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5016 hw->subsystem_device_id = pdev->subsystem_device;
5017
5018 /* Set common capability flags and settings */
5019 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
5020 adapter->ring_feature[RING_F_RSS].limit = rss;
5021 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5022 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5023 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5024 adapter->atr_sample_rate = 20;
5025 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5026 adapter->ring_feature[RING_F_FDIR].limit = fdir;
5027 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5028 #ifdef CONFIG_IXGBE_DCA
5029 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5030 #endif
5031 #ifdef IXGBE_FCOE
5032 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5033 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5034 #ifdef CONFIG_IXGBE_DCB
5035 /* Default traffic class to use for FCoE */
5036 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5037 #endif /* CONFIG_IXGBE_DCB */
5038 #endif /* IXGBE_FCOE */
5039
5040 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5041 hw->mac.num_rar_entries,
5042 GFP_ATOMIC);
5043
5044 /* Set MAC specific capability flags and exceptions */
5045 switch (hw->mac.type) {
5046 case ixgbe_mac_82598EB:
5047 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5048 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5049
5050 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5051 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5052
5053 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
5054 adapter->ring_feature[RING_F_FDIR].limit = 0;
5055 adapter->atr_sample_rate = 0;
5056 adapter->fdir_pballoc = 0;
5057 #ifdef IXGBE_FCOE
5058 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5059 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5060 #ifdef CONFIG_IXGBE_DCB
5061 adapter->fcoe.up = 0;
5062 #endif /* IXGBE_DCB */
5063 #endif /* IXGBE_FCOE */
5064 break;
5065 case ixgbe_mac_82599EB:
5066 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5067 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5068 break;
5069 case ixgbe_mac_X540:
5070 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
5071 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5072 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5073 break;
5074 default:
5075 break;
5076 }
5077
5078 #ifdef IXGBE_FCOE
5079 /* FCoE support exists, always init the FCoE lock */
5080 spin_lock_init(&adapter->fcoe.lock);
5081
5082 #endif
5083 /* n-tuple support exists, always init our spinlock */
5084 spin_lock_init(&adapter->fdir_perfect_lock);
5085
5086 #ifdef CONFIG_IXGBE_DCB
5087 switch (hw->mac.type) {
5088 case ixgbe_mac_X540:
5089 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5090 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5091 break;
5092 default:
5093 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5094 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5095 break;
5096 }
5097
5098 /* Configure DCB traffic classes */
5099 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5100 tc = &adapter->dcb_cfg.tc_config[j];
5101 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5102 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5103 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5104 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5105 tc->dcb_pfc = pfc_disabled;
5106 }
5107
5108 /* Initialize default user to priority mapping, UPx->TC0 */
5109 tc = &adapter->dcb_cfg.tc_config[0];
5110 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5111 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5112
5113 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5114 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5115 adapter->dcb_cfg.pfc_mode_enable = false;
5116 adapter->dcb_set_bitmap = 0x00;
5117 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5118 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5119 sizeof(adapter->temp_dcb_cfg));
5120
5121 #endif
5122
5123 /* default flow control settings */
5124 hw->fc.requested_mode = ixgbe_fc_full;
5125 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5126 ixgbe_pbthresh_setup(adapter);
5127 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5128 hw->fc.send_xon = true;
5129 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
5130
5131 #ifdef CONFIG_PCI_IOV
5132 if (max_vfs > 0)
5133 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5134
5135 /* assign number of SR-IOV VFs */
5136 if (hw->mac.type != ixgbe_mac_82598EB) {
5137 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
5138 adapter->num_vfs = 0;
5139 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5140 } else {
5141 adapter->num_vfs = max_vfs;
5142 }
5143 }
5144 #endif /* CONFIG_PCI_IOV */
5145
5146 /* enable itr by default in dynamic mode */
5147 adapter->rx_itr_setting = 1;
5148 adapter->tx_itr_setting = 1;
5149
5150 /* set default ring sizes */
5151 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5152 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5153
5154 /* set default work limits */
5155 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5156
5157 /* initialize eeprom parameters */
5158 if (ixgbe_init_eeprom_params_generic(hw)) {
5159 e_dev_err("EEPROM initialization failed\n");
5160 return -EIO;
5161 }
5162
5163 /* PF holds first pool slot */
5164 set_bit(0, &adapter->fwd_bitmask);
5165 set_bit(__IXGBE_DOWN, &adapter->state);
5166
5167 return 0;
5168 }
5169
5170 /**
5171 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5172 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5173 *
5174 * Return 0 on success, negative on failure
5175 **/
5176 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5177 {
5178 struct device *dev = tx_ring->dev;
5179 int orig_node = dev_to_node(dev);
5180 int ring_node = -1;
5181 int size;
5182
5183 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5184
5185 if (tx_ring->q_vector)
5186 ring_node = tx_ring->q_vector->numa_node;
5187
5188 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
5189 if (!tx_ring->tx_buffer_info)
5190 tx_ring->tx_buffer_info = vzalloc(size);
5191 if (!tx_ring->tx_buffer_info)
5192 goto err;
5193
5194 u64_stats_init(&tx_ring->syncp);
5195
5196 /* round up to nearest 4K */
5197 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5198 tx_ring->size = ALIGN(tx_ring->size, 4096);
5199
5200 set_dev_node(dev, ring_node);
5201 tx_ring->desc = dma_alloc_coherent(dev,
5202 tx_ring->size,
5203 &tx_ring->dma,
5204 GFP_KERNEL);
5205 set_dev_node(dev, orig_node);
5206 if (!tx_ring->desc)
5207 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5208 &tx_ring->dma, GFP_KERNEL);
5209 if (!tx_ring->desc)
5210 goto err;
5211
5212 tx_ring->next_to_use = 0;
5213 tx_ring->next_to_clean = 0;
5214 return 0;
5215
5216 err:
5217 vfree(tx_ring->tx_buffer_info);
5218 tx_ring->tx_buffer_info = NULL;
5219 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5220 return -ENOMEM;
5221 }
5222
5223 /**
5224 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5225 * @adapter: board private structure
5226 *
5227 * If this function returns with an error, then it's possible one or
5228 * more of the rings is populated (while the rest are not). It is the
5229 * callers duty to clean those orphaned rings.
5230 *
5231 * Return 0 on success, negative on failure
5232 **/
5233 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5234 {
5235 int i, err = 0;
5236
5237 for (i = 0; i < adapter->num_tx_queues; i++) {
5238 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5239 if (!err)
5240 continue;
5241
5242 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5243 goto err_setup_tx;
5244 }
5245
5246 return 0;
5247 err_setup_tx:
5248 /* rewind the index freeing the rings as we go */
5249 while (i--)
5250 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5251 return err;
5252 }
5253
5254 /**
5255 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5256 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5257 *
5258 * Returns 0 on success, negative on failure
5259 **/
5260 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5261 {
5262 struct device *dev = rx_ring->dev;
5263 int orig_node = dev_to_node(dev);
5264 int ring_node = -1;
5265 int size;
5266
5267 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5268
5269 if (rx_ring->q_vector)
5270 ring_node = rx_ring->q_vector->numa_node;
5271
5272 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
5273 if (!rx_ring->rx_buffer_info)
5274 rx_ring->rx_buffer_info = vzalloc(size);
5275 if (!rx_ring->rx_buffer_info)
5276 goto err;
5277
5278 u64_stats_init(&rx_ring->syncp);
5279
5280 /* Round up to nearest 4K */
5281 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5282 rx_ring->size = ALIGN(rx_ring->size, 4096);
5283
5284 set_dev_node(dev, ring_node);
5285 rx_ring->desc = dma_alloc_coherent(dev,
5286 rx_ring->size,
5287 &rx_ring->dma,
5288 GFP_KERNEL);
5289 set_dev_node(dev, orig_node);
5290 if (!rx_ring->desc)
5291 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5292 &rx_ring->dma, GFP_KERNEL);
5293 if (!rx_ring->desc)
5294 goto err;
5295
5296 rx_ring->next_to_clean = 0;
5297 rx_ring->next_to_use = 0;
5298
5299 return 0;
5300 err:
5301 vfree(rx_ring->rx_buffer_info);
5302 rx_ring->rx_buffer_info = NULL;
5303 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5304 return -ENOMEM;
5305 }
5306
5307 /**
5308 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5309 * @adapter: board private structure
5310 *
5311 * If this function returns with an error, then it's possible one or
5312 * more of the rings is populated (while the rest are not). It is the
5313 * callers duty to clean those orphaned rings.
5314 *
5315 * Return 0 on success, negative on failure
5316 **/
5317 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5318 {
5319 int i, err = 0;
5320
5321 for (i = 0; i < adapter->num_rx_queues; i++) {
5322 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5323 if (!err)
5324 continue;
5325
5326 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5327 goto err_setup_rx;
5328 }
5329
5330 #ifdef IXGBE_FCOE
5331 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5332 if (!err)
5333 #endif
5334 return 0;
5335 err_setup_rx:
5336 /* rewind the index freeing the rings as we go */
5337 while (i--)
5338 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5339 return err;
5340 }
5341
5342 /**
5343 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5344 * @tx_ring: Tx descriptor ring for a specific queue
5345 *
5346 * Free all transmit software resources
5347 **/
5348 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5349 {
5350 ixgbe_clean_tx_ring(tx_ring);
5351
5352 vfree(tx_ring->tx_buffer_info);
5353 tx_ring->tx_buffer_info = NULL;
5354
5355 /* if not set, then don't free */
5356 if (!tx_ring->desc)
5357 return;
5358
5359 dma_free_coherent(tx_ring->dev, tx_ring->size,
5360 tx_ring->desc, tx_ring->dma);
5361
5362 tx_ring->desc = NULL;
5363 }
5364
5365 /**
5366 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5367 * @adapter: board private structure
5368 *
5369 * Free all transmit software resources
5370 **/
5371 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5372 {
5373 int i;
5374
5375 for (i = 0; i < adapter->num_tx_queues; i++)
5376 if (adapter->tx_ring[i]->desc)
5377 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5378 }
5379
5380 /**
5381 * ixgbe_free_rx_resources - Free Rx Resources
5382 * @rx_ring: ring to clean the resources from
5383 *
5384 * Free all receive software resources
5385 **/
5386 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5387 {
5388 ixgbe_clean_rx_ring(rx_ring);
5389
5390 vfree(rx_ring->rx_buffer_info);
5391 rx_ring->rx_buffer_info = NULL;
5392
5393 /* if not set, then don't free */
5394 if (!rx_ring->desc)
5395 return;
5396
5397 dma_free_coherent(rx_ring->dev, rx_ring->size,
5398 rx_ring->desc, rx_ring->dma);
5399
5400 rx_ring->desc = NULL;
5401 }
5402
5403 /**
5404 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5405 * @adapter: board private structure
5406 *
5407 * Free all receive software resources
5408 **/
5409 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5410 {
5411 int i;
5412
5413 #ifdef IXGBE_FCOE
5414 ixgbe_free_fcoe_ddp_resources(adapter);
5415
5416 #endif
5417 for (i = 0; i < adapter->num_rx_queues; i++)
5418 if (adapter->rx_ring[i]->desc)
5419 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5420 }
5421
5422 /**
5423 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5424 * @netdev: network interface device structure
5425 * @new_mtu: new value for maximum frame size
5426 *
5427 * Returns 0 on success, negative on failure
5428 **/
5429 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5430 {
5431 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5432 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5433
5434 /* MTU < 68 is an error and causes problems on some kernels */
5435 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5436 return -EINVAL;
5437
5438 /*
5439 * For 82599EB we cannot allow legacy VFs to enable their receive
5440 * paths when MTU greater than 1500 is configured. So display a
5441 * warning that legacy VFs will be disabled.
5442 */
5443 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5444 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
5445 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
5446 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
5447
5448 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5449
5450 /* must set new MTU before calling down or up */
5451 netdev->mtu = new_mtu;
5452
5453 if (netif_running(netdev))
5454 ixgbe_reinit_locked(adapter);
5455
5456 return 0;
5457 }
5458
5459 /**
5460 * ixgbe_open - Called when a network interface is made active
5461 * @netdev: network interface device structure
5462 *
5463 * Returns 0 on success, negative value on failure
5464 *
5465 * The open entry point is called when a network interface is made
5466 * active by the system (IFF_UP). At this point all resources needed
5467 * for transmit and receive operations are allocated, the interrupt
5468 * handler is registered with the OS, the watchdog timer is started,
5469 * and the stack is notified that the interface is ready.
5470 **/
5471 static int ixgbe_open(struct net_device *netdev)
5472 {
5473 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5474 int err, queues;
5475
5476 /* disallow open during test */
5477 if (test_bit(__IXGBE_TESTING, &adapter->state))
5478 return -EBUSY;
5479
5480 netif_carrier_off(netdev);
5481
5482 /* allocate transmit descriptors */
5483 err = ixgbe_setup_all_tx_resources(adapter);
5484 if (err)
5485 goto err_setup_tx;
5486
5487 /* allocate receive descriptors */
5488 err = ixgbe_setup_all_rx_resources(adapter);
5489 if (err)
5490 goto err_setup_rx;
5491
5492 ixgbe_configure(adapter);
5493
5494 err = ixgbe_request_irq(adapter);
5495 if (err)
5496 goto err_req_irq;
5497
5498 /* Notify the stack of the actual queue counts. */
5499 if (adapter->num_rx_pools > 1)
5500 queues = adapter->num_rx_queues_per_pool;
5501 else
5502 queues = adapter->num_tx_queues;
5503
5504 err = netif_set_real_num_tx_queues(netdev, queues);
5505 if (err)
5506 goto err_set_queues;
5507
5508 if (adapter->num_rx_pools > 1 &&
5509 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5510 queues = IXGBE_MAX_L2A_QUEUES;
5511 else
5512 queues = adapter->num_rx_queues;
5513 err = netif_set_real_num_rx_queues(netdev, queues);
5514 if (err)
5515 goto err_set_queues;
5516
5517 ixgbe_ptp_init(adapter);
5518
5519 ixgbe_up_complete(adapter);
5520
5521 return 0;
5522
5523 err_set_queues:
5524 ixgbe_free_irq(adapter);
5525 err_req_irq:
5526 ixgbe_free_all_rx_resources(adapter);
5527 err_setup_rx:
5528 ixgbe_free_all_tx_resources(adapter);
5529 err_setup_tx:
5530 ixgbe_reset(adapter);
5531
5532 return err;
5533 }
5534
5535 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5536 {
5537 ixgbe_ptp_suspend(adapter);
5538
5539 ixgbe_down(adapter);
5540 ixgbe_free_irq(adapter);
5541
5542 ixgbe_free_all_tx_resources(adapter);
5543 ixgbe_free_all_rx_resources(adapter);
5544 }
5545
5546 /**
5547 * ixgbe_close - Disables a network interface
5548 * @netdev: network interface device structure
5549 *
5550 * Returns 0, this is not allowed to fail
5551 *
5552 * The close entry point is called when an interface is de-activated
5553 * by the OS. The hardware is still under the drivers control, but
5554 * needs to be disabled. A global MAC reset is issued to stop the
5555 * hardware, and all transmit and receive resources are freed.
5556 **/
5557 static int ixgbe_close(struct net_device *netdev)
5558 {
5559 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5560
5561 ixgbe_ptp_stop(adapter);
5562
5563 ixgbe_close_suspend(adapter);
5564
5565 ixgbe_fdir_filter_exit(adapter);
5566
5567 ixgbe_release_hw_control(adapter);
5568
5569 return 0;
5570 }
5571
5572 #ifdef CONFIG_PM
5573 static int ixgbe_resume(struct pci_dev *pdev)
5574 {
5575 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5576 struct net_device *netdev = adapter->netdev;
5577 u32 err;
5578
5579 adapter->hw.hw_addr = adapter->io_addr;
5580 pci_set_power_state(pdev, PCI_D0);
5581 pci_restore_state(pdev);
5582 /*
5583 * pci_restore_state clears dev->state_saved so call
5584 * pci_save_state to restore it.
5585 */
5586 pci_save_state(pdev);
5587
5588 err = pci_enable_device_mem(pdev);
5589 if (err) {
5590 e_dev_err("Cannot enable PCI device from suspend\n");
5591 return err;
5592 }
5593 smp_mb__before_atomic();
5594 clear_bit(__IXGBE_DISABLED, &adapter->state);
5595 pci_set_master(pdev);
5596
5597 pci_wake_from_d3(pdev, false);
5598
5599 ixgbe_reset(adapter);
5600
5601 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5602
5603 rtnl_lock();
5604 err = ixgbe_init_interrupt_scheme(adapter);
5605 if (!err && netif_running(netdev))
5606 err = ixgbe_open(netdev);
5607
5608 rtnl_unlock();
5609
5610 if (err)
5611 return err;
5612
5613 netif_device_attach(netdev);
5614
5615 return 0;
5616 }
5617 #endif /* CONFIG_PM */
5618
5619 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5620 {
5621 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5622 struct net_device *netdev = adapter->netdev;
5623 struct ixgbe_hw *hw = &adapter->hw;
5624 u32 ctrl, fctrl;
5625 u32 wufc = adapter->wol;
5626 #ifdef CONFIG_PM
5627 int retval = 0;
5628 #endif
5629
5630 netif_device_detach(netdev);
5631
5632 rtnl_lock();
5633 if (netif_running(netdev))
5634 ixgbe_close_suspend(adapter);
5635 rtnl_unlock();
5636
5637 ixgbe_clear_interrupt_scheme(adapter);
5638
5639 #ifdef CONFIG_PM
5640 retval = pci_save_state(pdev);
5641 if (retval)
5642 return retval;
5643
5644 #endif
5645 if (hw->mac.ops.stop_link_on_d3)
5646 hw->mac.ops.stop_link_on_d3(hw);
5647
5648 if (wufc) {
5649 ixgbe_set_rx_mode(netdev);
5650
5651 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5652 if (hw->mac.ops.enable_tx_laser)
5653 hw->mac.ops.enable_tx_laser(hw);
5654
5655 /* turn on all-multi mode if wake on multicast is enabled */
5656 if (wufc & IXGBE_WUFC_MC) {
5657 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5658 fctrl |= IXGBE_FCTRL_MPE;
5659 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5660 }
5661
5662 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5663 ctrl |= IXGBE_CTRL_GIO_DIS;
5664 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5665
5666 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5667 } else {
5668 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5669 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5670 }
5671
5672 switch (hw->mac.type) {
5673 case ixgbe_mac_82598EB:
5674 pci_wake_from_d3(pdev, false);
5675 break;
5676 case ixgbe_mac_82599EB:
5677 case ixgbe_mac_X540:
5678 pci_wake_from_d3(pdev, !!wufc);
5679 break;
5680 default:
5681 break;
5682 }
5683
5684 *enable_wake = !!wufc;
5685
5686 ixgbe_release_hw_control(adapter);
5687
5688 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
5689 pci_disable_device(pdev);
5690
5691 return 0;
5692 }
5693
5694 #ifdef CONFIG_PM
5695 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5696 {
5697 int retval;
5698 bool wake;
5699
5700 retval = __ixgbe_shutdown(pdev, &wake);
5701 if (retval)
5702 return retval;
5703
5704 if (wake) {
5705 pci_prepare_to_sleep(pdev);
5706 } else {
5707 pci_wake_from_d3(pdev, false);
5708 pci_set_power_state(pdev, PCI_D3hot);
5709 }
5710
5711 return 0;
5712 }
5713 #endif /* CONFIG_PM */
5714
5715 static void ixgbe_shutdown(struct pci_dev *pdev)
5716 {
5717 bool wake;
5718
5719 __ixgbe_shutdown(pdev, &wake);
5720
5721 if (system_state == SYSTEM_POWER_OFF) {
5722 pci_wake_from_d3(pdev, wake);
5723 pci_set_power_state(pdev, PCI_D3hot);
5724 }
5725 }
5726
5727 /**
5728 * ixgbe_update_stats - Update the board statistics counters.
5729 * @adapter: board private structure
5730 **/
5731 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5732 {
5733 struct net_device *netdev = adapter->netdev;
5734 struct ixgbe_hw *hw = &adapter->hw;
5735 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5736 u64 total_mpc = 0;
5737 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5738 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5739 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5740 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5741
5742 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5743 test_bit(__IXGBE_RESETTING, &adapter->state))
5744 return;
5745
5746 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5747 u64 rsc_count = 0;
5748 u64 rsc_flush = 0;
5749 for (i = 0; i < adapter->num_rx_queues; i++) {
5750 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5751 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5752 }
5753 adapter->rsc_total_count = rsc_count;
5754 adapter->rsc_total_flush = rsc_flush;
5755 }
5756
5757 for (i = 0; i < adapter->num_rx_queues; i++) {
5758 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5759 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5760 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5761 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5762 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5763 bytes += rx_ring->stats.bytes;
5764 packets += rx_ring->stats.packets;
5765 }
5766 adapter->non_eop_descs = non_eop_descs;
5767 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5768 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5769 adapter->hw_csum_rx_error = hw_csum_rx_error;
5770 netdev->stats.rx_bytes = bytes;
5771 netdev->stats.rx_packets = packets;
5772
5773 bytes = 0;
5774 packets = 0;
5775 /* gather some stats to the adapter struct that are per queue */
5776 for (i = 0; i < adapter->num_tx_queues; i++) {
5777 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5778 restart_queue += tx_ring->tx_stats.restart_queue;
5779 tx_busy += tx_ring->tx_stats.tx_busy;
5780 bytes += tx_ring->stats.bytes;
5781 packets += tx_ring->stats.packets;
5782 }
5783 adapter->restart_queue = restart_queue;
5784 adapter->tx_busy = tx_busy;
5785 netdev->stats.tx_bytes = bytes;
5786 netdev->stats.tx_packets = packets;
5787
5788 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5789
5790 /* 8 register reads */
5791 for (i = 0; i < 8; i++) {
5792 /* for packet buffers not used, the register should read 0 */
5793 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5794 missed_rx += mpc;
5795 hwstats->mpc[i] += mpc;
5796 total_mpc += hwstats->mpc[i];
5797 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5798 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5799 switch (hw->mac.type) {
5800 case ixgbe_mac_82598EB:
5801 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5802 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5803 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5804 hwstats->pxonrxc[i] +=
5805 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5806 break;
5807 case ixgbe_mac_82599EB:
5808 case ixgbe_mac_X540:
5809 hwstats->pxonrxc[i] +=
5810 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5811 break;
5812 default:
5813 break;
5814 }
5815 }
5816
5817 /*16 register reads */
5818 for (i = 0; i < 16; i++) {
5819 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5820 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5821 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5822 (hw->mac.type == ixgbe_mac_X540)) {
5823 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5824 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5825 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5826 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5827 }
5828 }
5829
5830 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5831 /* work around hardware counting issue */
5832 hwstats->gprc -= missed_rx;
5833
5834 ixgbe_update_xoff_received(adapter);
5835
5836 /* 82598 hardware only has a 32 bit counter in the high register */
5837 switch (hw->mac.type) {
5838 case ixgbe_mac_82598EB:
5839 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5840 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5841 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5842 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5843 break;
5844 case ixgbe_mac_X540:
5845 /* OS2BMC stats are X540 only*/
5846 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5847 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5848 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5849 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5850 case ixgbe_mac_82599EB:
5851 for (i = 0; i < 16; i++)
5852 adapter->hw_rx_no_dma_resources +=
5853 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5854 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5855 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5856 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5857 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5858 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5859 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5860 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5861 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5862 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5863 #ifdef IXGBE_FCOE
5864 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5865 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5866 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5867 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5868 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5869 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5870 /* Add up per cpu counters for total ddp aloc fail */
5871 if (adapter->fcoe.ddp_pool) {
5872 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5873 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5874 unsigned int cpu;
5875 u64 noddp = 0, noddp_ext_buff = 0;
5876 for_each_possible_cpu(cpu) {
5877 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5878 noddp += ddp_pool->noddp;
5879 noddp_ext_buff += ddp_pool->noddp_ext_buff;
5880 }
5881 hwstats->fcoe_noddp = noddp;
5882 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
5883 }
5884 #endif /* IXGBE_FCOE */
5885 break;
5886 default:
5887 break;
5888 }
5889 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5890 hwstats->bprc += bprc;
5891 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5892 if (hw->mac.type == ixgbe_mac_82598EB)
5893 hwstats->mprc -= bprc;
5894 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5895 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5896 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5897 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5898 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5899 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5900 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5901 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5902 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5903 hwstats->lxontxc += lxon;
5904 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5905 hwstats->lxofftxc += lxoff;
5906 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5907 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5908 /*
5909 * 82598 errata - tx of flow control packets is included in tx counters
5910 */
5911 xon_off_tot = lxon + lxoff;
5912 hwstats->gptc -= xon_off_tot;
5913 hwstats->mptc -= xon_off_tot;
5914 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5915 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5916 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5917 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5918 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5919 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5920 hwstats->ptc64 -= xon_off_tot;
5921 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5922 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5923 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5924 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5925 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5926 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5927
5928 /* Fill out the OS statistics structure */
5929 netdev->stats.multicast = hwstats->mprc;
5930
5931 /* Rx Errors */
5932 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5933 netdev->stats.rx_dropped = 0;
5934 netdev->stats.rx_length_errors = hwstats->rlec;
5935 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5936 netdev->stats.rx_missed_errors = total_mpc;
5937 }
5938
5939 /**
5940 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5941 * @adapter: pointer to the device adapter structure
5942 **/
5943 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5944 {
5945 struct ixgbe_hw *hw = &adapter->hw;
5946 int i;
5947
5948 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5949 return;
5950
5951 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5952
5953 /* if interface is down do nothing */
5954 if (test_bit(__IXGBE_DOWN, &adapter->state))
5955 return;
5956
5957 /* do nothing if we are not using signature filters */
5958 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5959 return;
5960
5961 adapter->fdir_overflow++;
5962
5963 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5964 for (i = 0; i < adapter->num_tx_queues; i++)
5965 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5966 &(adapter->tx_ring[i]->state));
5967 /* re-enable flow director interrupts */
5968 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5969 } else {
5970 e_err(probe, "failed to finish FDIR re-initialization, "
5971 "ignored adding FDIR ATR filters\n");
5972 }
5973 }
5974
5975 /**
5976 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5977 * @adapter: pointer to the device adapter structure
5978 *
5979 * This function serves two purposes. First it strobes the interrupt lines
5980 * in order to make certain interrupts are occurring. Secondly it sets the
5981 * bits needed to check for TX hangs. As a result we should immediately
5982 * determine if a hang has occurred.
5983 */
5984 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5985 {
5986 struct ixgbe_hw *hw = &adapter->hw;
5987 u64 eics = 0;
5988 int i;
5989
5990 /* If we're down, removing or resetting, just bail */
5991 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5992 test_bit(__IXGBE_REMOVING, &adapter->state) ||
5993 test_bit(__IXGBE_RESETTING, &adapter->state))
5994 return;
5995
5996 /* Force detection of hung controller */
5997 if (netif_carrier_ok(adapter->netdev)) {
5998 for (i = 0; i < adapter->num_tx_queues; i++)
5999 set_check_for_tx_hang(adapter->tx_ring[i]);
6000 }
6001
6002 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6003 /*
6004 * for legacy and MSI interrupts don't set any bits
6005 * that are enabled for EIAM, because this operation
6006 * would set *both* EIMS and EICS for any bit in EIAM
6007 */
6008 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6009 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
6010 } else {
6011 /* get one bit for every active tx/rx interrupt vector */
6012 for (i = 0; i < adapter->num_q_vectors; i++) {
6013 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6014 if (qv->rx.ring || qv->tx.ring)
6015 eics |= ((u64)1 << i);
6016 }
6017 }
6018
6019 /* Cause software interrupt to ensure rings are cleaned */
6020 ixgbe_irq_rearm_queues(adapter, eics);
6021
6022 }
6023
6024 /**
6025 * ixgbe_watchdog_update_link - update the link status
6026 * @adapter: pointer to the device adapter structure
6027 * @link_speed: pointer to a u32 to store the link_speed
6028 **/
6029 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
6030 {
6031 struct ixgbe_hw *hw = &adapter->hw;
6032 u32 link_speed = adapter->link_speed;
6033 bool link_up = adapter->link_up;
6034 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
6035
6036 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6037 return;
6038
6039 if (hw->mac.ops.check_link) {
6040 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6041 } else {
6042 /* always assume link is up, if no check link function */
6043 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6044 link_up = true;
6045 }
6046
6047 if (adapter->ixgbe_ieee_pfc)
6048 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6049
6050 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
6051 hw->mac.ops.fc_enable(hw);
6052 ixgbe_set_rx_drop_en(adapter);
6053 }
6054
6055 if (link_up ||
6056 time_after(jiffies, (adapter->link_check_timeout +
6057 IXGBE_TRY_LINK_TIMEOUT))) {
6058 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6059 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6060 IXGBE_WRITE_FLUSH(hw);
6061 }
6062
6063 adapter->link_up = link_up;
6064 adapter->link_speed = link_speed;
6065 }
6066
6067 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6068 {
6069 #ifdef CONFIG_IXGBE_DCB
6070 struct net_device *netdev = adapter->netdev;
6071 struct dcb_app app = {
6072 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6073 .protocol = 0,
6074 };
6075 u8 up = 0;
6076
6077 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6078 up = dcb_ieee_getapp_mask(netdev, &app);
6079
6080 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6081 #endif
6082 }
6083
6084 /**
6085 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6086 * print link up message
6087 * @adapter: pointer to the device adapter structure
6088 **/
6089 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
6090 {
6091 struct net_device *netdev = adapter->netdev;
6092 struct ixgbe_hw *hw = &adapter->hw;
6093 struct net_device *upper;
6094 struct list_head *iter;
6095 u32 link_speed = adapter->link_speed;
6096 bool flow_rx, flow_tx;
6097
6098 /* only continue if link was previously down */
6099 if (netif_carrier_ok(netdev))
6100 return;
6101
6102 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
6103
6104 switch (hw->mac.type) {
6105 case ixgbe_mac_82598EB: {
6106 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6107 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6108 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6109 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6110 }
6111 break;
6112 case ixgbe_mac_X540:
6113 case ixgbe_mac_82599EB: {
6114 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6115 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6116 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6117 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6118 }
6119 break;
6120 default:
6121 flow_tx = false;
6122 flow_rx = false;
6123 break;
6124 }
6125
6126 adapter->last_rx_ptp_check = jiffies;
6127
6128 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6129 ixgbe_ptp_start_cyclecounter(adapter);
6130
6131 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6132 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6133 "10 Gbps" :
6134 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6135 "1 Gbps" :
6136 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6137 "100 Mbps" :
6138 "unknown speed"))),
6139 ((flow_rx && flow_tx) ? "RX/TX" :
6140 (flow_rx ? "RX" :
6141 (flow_tx ? "TX" : "None"))));
6142
6143 netif_carrier_on(netdev);
6144 ixgbe_check_vf_rate_limit(adapter);
6145
6146 /* enable transmits */
6147 netif_tx_wake_all_queues(adapter->netdev);
6148
6149 /* enable any upper devices */
6150 rtnl_lock();
6151 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6152 if (netif_is_macvlan(upper)) {
6153 struct macvlan_dev *vlan = netdev_priv(upper);
6154
6155 if (vlan->fwd_priv)
6156 netif_tx_wake_all_queues(upper);
6157 }
6158 }
6159 rtnl_unlock();
6160
6161 /* update the default user priority for VFs */
6162 ixgbe_update_default_up(adapter);
6163
6164 /* ping all the active vfs to let them know link has changed */
6165 ixgbe_ping_all_vfs(adapter);
6166 }
6167
6168 /**
6169 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6170 * print link down message
6171 * @adapter: pointer to the adapter structure
6172 **/
6173 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
6174 {
6175 struct net_device *netdev = adapter->netdev;
6176 struct ixgbe_hw *hw = &adapter->hw;
6177
6178 adapter->link_up = false;
6179 adapter->link_speed = 0;
6180
6181 /* only continue if link was up previously */
6182 if (!netif_carrier_ok(netdev))
6183 return;
6184
6185 /* poll for SFP+ cable when link is down */
6186 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6187 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6188
6189 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6190 ixgbe_ptp_start_cyclecounter(adapter);
6191
6192 e_info(drv, "NIC Link is Down\n");
6193 netif_carrier_off(netdev);
6194
6195 /* ping all the active vfs to let them know link has changed */
6196 ixgbe_ping_all_vfs(adapter);
6197 }
6198
6199 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6200 {
6201 int i;
6202
6203 for (i = 0; i < adapter->num_tx_queues; i++) {
6204 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6205
6206 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6207 return true;
6208 }
6209
6210 return false;
6211 }
6212
6213 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6214 {
6215 struct ixgbe_hw *hw = &adapter->hw;
6216 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6217 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6218
6219 int i, j;
6220
6221 if (!adapter->num_vfs)
6222 return false;
6223
6224 for (i = 0; i < adapter->num_vfs; i++) {
6225 for (j = 0; j < q_per_pool; j++) {
6226 u32 h, t;
6227
6228 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6229 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6230
6231 if (h != t)
6232 return true;
6233 }
6234 }
6235
6236 return false;
6237 }
6238
6239 /**
6240 * ixgbe_watchdog_flush_tx - flush queues on link down
6241 * @adapter: pointer to the device adapter structure
6242 **/
6243 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6244 {
6245 if (!netif_carrier_ok(adapter->netdev)) {
6246 if (ixgbe_ring_tx_pending(adapter) ||
6247 ixgbe_vf_tx_pending(adapter)) {
6248 /* We've lost link, so the controller stops DMA,
6249 * but we've got queued Tx work that's never going
6250 * to get done, so reset controller to flush Tx.
6251 * (Do the reset outside of interrupt context).
6252 */
6253 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
6254 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6255 }
6256 }
6257 }
6258
6259 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6260 {
6261 u32 ssvpc;
6262
6263 /* Do not perform spoof check for 82598 or if not in IOV mode */
6264 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6265 adapter->num_vfs == 0)
6266 return;
6267
6268 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6269
6270 /*
6271 * ssvpc register is cleared on read, if zero then no
6272 * spoofed packets in the last interval.
6273 */
6274 if (!ssvpc)
6275 return;
6276
6277 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
6278 }
6279
6280 /**
6281 * ixgbe_watchdog_subtask - check and bring link up
6282 * @adapter: pointer to the device adapter structure
6283 **/
6284 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6285 {
6286 /* if interface is down, removing or resetting, do nothing */
6287 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6288 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6289 test_bit(__IXGBE_RESETTING, &adapter->state))
6290 return;
6291
6292 ixgbe_watchdog_update_link(adapter);
6293
6294 if (adapter->link_up)
6295 ixgbe_watchdog_link_is_up(adapter);
6296 else
6297 ixgbe_watchdog_link_is_down(adapter);
6298
6299 ixgbe_spoof_check(adapter);
6300 ixgbe_update_stats(adapter);
6301
6302 ixgbe_watchdog_flush_tx(adapter);
6303 }
6304
6305 /**
6306 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6307 * @adapter: the ixgbe adapter structure
6308 **/
6309 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6310 {
6311 struct ixgbe_hw *hw = &adapter->hw;
6312 s32 err;
6313
6314 /* not searching for SFP so there is nothing to do here */
6315 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6316 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6317 return;
6318
6319 /* someone else is in init, wait until next service event */
6320 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6321 return;
6322
6323 err = hw->phy.ops.identify_sfp(hw);
6324 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6325 goto sfp_out;
6326
6327 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6328 /* If no cable is present, then we need to reset
6329 * the next time we find a good cable. */
6330 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6331 }
6332
6333 /* exit on error */
6334 if (err)
6335 goto sfp_out;
6336
6337 /* exit if reset not needed */
6338 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6339 goto sfp_out;
6340
6341 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6342
6343 /*
6344 * A module may be identified correctly, but the EEPROM may not have
6345 * support for that module. setup_sfp() will fail in that case, so
6346 * we should not allow that module to load.
6347 */
6348 if (hw->mac.type == ixgbe_mac_82598EB)
6349 err = hw->phy.ops.reset(hw);
6350 else
6351 err = hw->mac.ops.setup_sfp(hw);
6352
6353 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6354 goto sfp_out;
6355
6356 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6357 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6358
6359 sfp_out:
6360 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6361
6362 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6363 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6364 e_dev_err("failed to initialize because an unsupported "
6365 "SFP+ module type was detected.\n");
6366 e_dev_err("Reload the driver after installing a "
6367 "supported module.\n");
6368 unregister_netdev(adapter->netdev);
6369 }
6370 }
6371
6372 /**
6373 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6374 * @adapter: the ixgbe adapter structure
6375 **/
6376 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6377 {
6378 struct ixgbe_hw *hw = &adapter->hw;
6379 u32 speed;
6380 bool autoneg = false;
6381
6382 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6383 return;
6384
6385 /* someone else is in init, wait until next service event */
6386 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6387 return;
6388
6389 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6390
6391 speed = hw->phy.autoneg_advertised;
6392 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
6393 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
6394
6395 /* setup the highest link when no autoneg */
6396 if (!autoneg) {
6397 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6398 speed = IXGBE_LINK_SPEED_10GB_FULL;
6399 }
6400 }
6401
6402 if (hw->mac.ops.setup_link)
6403 hw->mac.ops.setup_link(hw, speed, true);
6404
6405 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6406 adapter->link_check_timeout = jiffies;
6407 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6408 }
6409
6410 #ifdef CONFIG_PCI_IOV
6411 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6412 {
6413 int vf;
6414 struct ixgbe_hw *hw = &adapter->hw;
6415 struct net_device *netdev = adapter->netdev;
6416 u32 gpc;
6417 u32 ciaa, ciad;
6418
6419 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6420 if (gpc) /* If incrementing then no need for the check below */
6421 return;
6422 /*
6423 * Check to see if a bad DMA write target from an errant or
6424 * malicious VF has caused a PCIe error. If so then we can
6425 * issue a VFLR to the offending VF(s) and then resume without
6426 * requesting a full slot reset.
6427 */
6428
6429 for (vf = 0; vf < adapter->num_vfs; vf++) {
6430 ciaa = (vf << 16) | 0x80000000;
6431 /* 32 bit read so align, we really want status at offset 6 */
6432 ciaa |= PCI_COMMAND;
6433 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6434 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6435 ciaa &= 0x7FFFFFFF;
6436 /* disable debug mode asap after reading data */
6437 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6438 /* Get the upper 16 bits which will be the PCI status reg */
6439 ciad >>= 16;
6440 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6441 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6442 /* Issue VFLR */
6443 ciaa = (vf << 16) | 0x80000000;
6444 ciaa |= 0xA8;
6445 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6446 ciad = 0x00008000; /* VFLR */
6447 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6448 ciaa &= 0x7FFFFFFF;
6449 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6450 }
6451 }
6452 }
6453
6454 #endif
6455 /**
6456 * ixgbe_service_timer - Timer Call-back
6457 * @data: pointer to adapter cast into an unsigned long
6458 **/
6459 static void ixgbe_service_timer(unsigned long data)
6460 {
6461 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6462 unsigned long next_event_offset;
6463 bool ready = true;
6464
6465 /* poll faster when waiting for link */
6466 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6467 next_event_offset = HZ / 10;
6468 else
6469 next_event_offset = HZ * 2;
6470
6471 #ifdef CONFIG_PCI_IOV
6472 /*
6473 * don't bother with SR-IOV VF DMA hang check if there are
6474 * no VFs or the link is down
6475 */
6476 if (!adapter->num_vfs ||
6477 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6478 goto normal_timer_service;
6479
6480 /* If we have VFs allocated then we must check for DMA hangs */
6481 ixgbe_check_for_bad_vf(adapter);
6482 next_event_offset = HZ / 50;
6483 adapter->timer_event_accumulator++;
6484
6485 if (adapter->timer_event_accumulator >= 100)
6486 adapter->timer_event_accumulator = 0;
6487 else
6488 ready = false;
6489
6490 normal_timer_service:
6491 #endif
6492 /* Reset the timer */
6493 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6494
6495 if (ready)
6496 ixgbe_service_event_schedule(adapter);
6497 }
6498
6499 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6500 {
6501 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6502 return;
6503
6504 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6505
6506 /* If we're already down, removing or resetting, just bail */
6507 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6508 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6509 test_bit(__IXGBE_RESETTING, &adapter->state))
6510 return;
6511
6512 ixgbe_dump(adapter);
6513 netdev_err(adapter->netdev, "Reset adapter\n");
6514 adapter->tx_timeout_count++;
6515
6516 rtnl_lock();
6517 ixgbe_reinit_locked(adapter);
6518 rtnl_unlock();
6519 }
6520
6521 /**
6522 * ixgbe_service_task - manages and runs subtasks
6523 * @work: pointer to work_struct containing our data
6524 **/
6525 static void ixgbe_service_task(struct work_struct *work)
6526 {
6527 struct ixgbe_adapter *adapter = container_of(work,
6528 struct ixgbe_adapter,
6529 service_task);
6530 if (ixgbe_removed(adapter->hw.hw_addr)) {
6531 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6532 rtnl_lock();
6533 ixgbe_down(adapter);
6534 rtnl_unlock();
6535 }
6536 ixgbe_service_event_complete(adapter);
6537 return;
6538 }
6539 ixgbe_reset_subtask(adapter);
6540 ixgbe_sfp_detection_subtask(adapter);
6541 ixgbe_sfp_link_config_subtask(adapter);
6542 ixgbe_check_overtemp_subtask(adapter);
6543 ixgbe_watchdog_subtask(adapter);
6544 ixgbe_fdir_reinit_subtask(adapter);
6545 ixgbe_check_hang_subtask(adapter);
6546
6547 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
6548 ixgbe_ptp_overflow_check(adapter);
6549 ixgbe_ptp_rx_hang(adapter);
6550 }
6551
6552 ixgbe_service_event_complete(adapter);
6553 }
6554
6555 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6556 struct ixgbe_tx_buffer *first,
6557 u8 *hdr_len)
6558 {
6559 struct sk_buff *skb = first->skb;
6560 u32 vlan_macip_lens, type_tucmd;
6561 u32 mss_l4len_idx, l4len;
6562 int err;
6563
6564 if (skb->ip_summed != CHECKSUM_PARTIAL)
6565 return 0;
6566
6567 if (!skb_is_gso(skb))
6568 return 0;
6569
6570 err = skb_cow_head(skb, 0);
6571 if (err < 0)
6572 return err;
6573
6574 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6575 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6576
6577 if (first->protocol == htons(ETH_P_IP)) {
6578 struct iphdr *iph = ip_hdr(skb);
6579 iph->tot_len = 0;
6580 iph->check = 0;
6581 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6582 iph->daddr, 0,
6583 IPPROTO_TCP,
6584 0);
6585 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6586 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6587 IXGBE_TX_FLAGS_CSUM |
6588 IXGBE_TX_FLAGS_IPV4;
6589 } else if (skb_is_gso_v6(skb)) {
6590 ipv6_hdr(skb)->payload_len = 0;
6591 tcp_hdr(skb)->check =
6592 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6593 &ipv6_hdr(skb)->daddr,
6594 0, IPPROTO_TCP, 0);
6595 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6596 IXGBE_TX_FLAGS_CSUM;
6597 }
6598
6599 /* compute header lengths */
6600 l4len = tcp_hdrlen(skb);
6601 *hdr_len = skb_transport_offset(skb) + l4len;
6602
6603 /* update gso size and bytecount with header size */
6604 first->gso_segs = skb_shinfo(skb)->gso_segs;
6605 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6606
6607 /* mss_l4len_id: use 0 as index for TSO */
6608 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6609 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6610
6611 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6612 vlan_macip_lens = skb_network_header_len(skb);
6613 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6614 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6615
6616 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6617 mss_l4len_idx);
6618
6619 return 1;
6620 }
6621
6622 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6623 struct ixgbe_tx_buffer *first)
6624 {
6625 struct sk_buff *skb = first->skb;
6626 u32 vlan_macip_lens = 0;
6627 u32 mss_l4len_idx = 0;
6628 u32 type_tucmd = 0;
6629
6630 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6631 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6632 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6633 return;
6634 } else {
6635 u8 l4_hdr = 0;
6636 switch (first->protocol) {
6637 case htons(ETH_P_IP):
6638 vlan_macip_lens |= skb_network_header_len(skb);
6639 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6640 l4_hdr = ip_hdr(skb)->protocol;
6641 break;
6642 case htons(ETH_P_IPV6):
6643 vlan_macip_lens |= skb_network_header_len(skb);
6644 l4_hdr = ipv6_hdr(skb)->nexthdr;
6645 break;
6646 default:
6647 if (unlikely(net_ratelimit())) {
6648 dev_warn(tx_ring->dev,
6649 "partial checksum but proto=%x!\n",
6650 first->protocol);
6651 }
6652 break;
6653 }
6654
6655 switch (l4_hdr) {
6656 case IPPROTO_TCP:
6657 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6658 mss_l4len_idx = tcp_hdrlen(skb) <<
6659 IXGBE_ADVTXD_L4LEN_SHIFT;
6660 break;
6661 case IPPROTO_SCTP:
6662 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6663 mss_l4len_idx = sizeof(struct sctphdr) <<
6664 IXGBE_ADVTXD_L4LEN_SHIFT;
6665 break;
6666 case IPPROTO_UDP:
6667 mss_l4len_idx = sizeof(struct udphdr) <<
6668 IXGBE_ADVTXD_L4LEN_SHIFT;
6669 break;
6670 default:
6671 if (unlikely(net_ratelimit())) {
6672 dev_warn(tx_ring->dev,
6673 "partial checksum but l4 proto=%x!\n",
6674 l4_hdr);
6675 }
6676 break;
6677 }
6678
6679 /* update TX checksum flag */
6680 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
6681 }
6682
6683 /* vlan_macip_lens: MACLEN, VLAN tag */
6684 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6685 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6686
6687 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6688 type_tucmd, mss_l4len_idx);
6689 }
6690
6691 #define IXGBE_SET_FLAG(_input, _flag, _result) \
6692 ((_flag <= _result) ? \
6693 ((u32)(_input & _flag) * (_result / _flag)) : \
6694 ((u32)(_input & _flag) / (_flag / _result)))
6695
6696 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6697 {
6698 /* set type for advanced descriptor with frame checksum insertion */
6699 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6700 IXGBE_ADVTXD_DCMD_DEXT |
6701 IXGBE_ADVTXD_DCMD_IFCS;
6702
6703 /* set HW vlan bit if vlan is present */
6704 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6705 IXGBE_ADVTXD_DCMD_VLE);
6706
6707 /* set segmentation enable bits for TSO/FSO */
6708 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6709 IXGBE_ADVTXD_DCMD_TSE);
6710
6711 /* set timestamp bit if present */
6712 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6713 IXGBE_ADVTXD_MAC_TSTAMP);
6714
6715 /* insert frame checksum */
6716 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
6717
6718 return cmd_type;
6719 }
6720
6721 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6722 u32 tx_flags, unsigned int paylen)
6723 {
6724 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
6725
6726 /* enable L4 checksum for TSO and TX checksum offload */
6727 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6728 IXGBE_TX_FLAGS_CSUM,
6729 IXGBE_ADVTXD_POPTS_TXSM);
6730
6731 /* enble IPv4 checksum for TSO */
6732 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6733 IXGBE_TX_FLAGS_IPV4,
6734 IXGBE_ADVTXD_POPTS_IXSM);
6735
6736 /*
6737 * Check Context must be set if Tx switch is enabled, which it
6738 * always is for case where virtual functions are running
6739 */
6740 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6741 IXGBE_TX_FLAGS_CC,
6742 IXGBE_ADVTXD_CC);
6743
6744 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6745 }
6746
6747 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6748 {
6749 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6750
6751 /* Herbert's original patch had:
6752 * smp_mb__after_netif_stop_queue();
6753 * but since that doesn't exist yet, just open code it.
6754 */
6755 smp_mb();
6756
6757 /* We need to check again in a case another CPU has just
6758 * made room available.
6759 */
6760 if (likely(ixgbe_desc_unused(tx_ring) < size))
6761 return -EBUSY;
6762
6763 /* A reprieve! - use start_queue because it doesn't call schedule */
6764 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6765 ++tx_ring->tx_stats.restart_queue;
6766 return 0;
6767 }
6768
6769 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6770 {
6771 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6772 return 0;
6773
6774 return __ixgbe_maybe_stop_tx(tx_ring, size);
6775 }
6776
6777 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6778 IXGBE_TXD_CMD_RS)
6779
6780 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6781 struct ixgbe_tx_buffer *first,
6782 const u8 hdr_len)
6783 {
6784 struct sk_buff *skb = first->skb;
6785 struct ixgbe_tx_buffer *tx_buffer;
6786 union ixgbe_adv_tx_desc *tx_desc;
6787 struct skb_frag_struct *frag;
6788 dma_addr_t dma;
6789 unsigned int data_len, size;
6790 u32 tx_flags = first->tx_flags;
6791 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
6792 u16 i = tx_ring->next_to_use;
6793
6794 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6795
6796 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6797
6798 size = skb_headlen(skb);
6799 data_len = skb->data_len;
6800
6801 #ifdef IXGBE_FCOE
6802 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6803 if (data_len < sizeof(struct fcoe_crc_eof)) {
6804 size -= sizeof(struct fcoe_crc_eof) - data_len;
6805 data_len = 0;
6806 } else {
6807 data_len -= sizeof(struct fcoe_crc_eof);
6808 }
6809 }
6810
6811 #endif
6812 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6813
6814 tx_buffer = first;
6815
6816 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6817 if (dma_mapping_error(tx_ring->dev, dma))
6818 goto dma_error;
6819
6820 /* record length, and DMA address */
6821 dma_unmap_len_set(tx_buffer, len, size);
6822 dma_unmap_addr_set(tx_buffer, dma, dma);
6823
6824 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6825
6826 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6827 tx_desc->read.cmd_type_len =
6828 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
6829
6830 i++;
6831 tx_desc++;
6832 if (i == tx_ring->count) {
6833 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6834 i = 0;
6835 }
6836 tx_desc->read.olinfo_status = 0;
6837
6838 dma += IXGBE_MAX_DATA_PER_TXD;
6839 size -= IXGBE_MAX_DATA_PER_TXD;
6840
6841 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6842 }
6843
6844 if (likely(!data_len))
6845 break;
6846
6847 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6848
6849 i++;
6850 tx_desc++;
6851 if (i == tx_ring->count) {
6852 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6853 i = 0;
6854 }
6855 tx_desc->read.olinfo_status = 0;
6856
6857 #ifdef IXGBE_FCOE
6858 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6859 #else
6860 size = skb_frag_size(frag);
6861 #endif
6862 data_len -= size;
6863
6864 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6865 DMA_TO_DEVICE);
6866
6867 tx_buffer = &tx_ring->tx_buffer_info[i];
6868 }
6869
6870 /* write last descriptor with RS and EOP bits */
6871 cmd_type |= size | IXGBE_TXD_CMD;
6872 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6873
6874 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6875
6876 /* set the timestamp */
6877 first->time_stamp = jiffies;
6878
6879 /*
6880 * Force memory writes to complete before letting h/w know there
6881 * are new descriptors to fetch. (Only applicable for weak-ordered
6882 * memory model archs, such as IA-64).
6883 *
6884 * We also need this memory barrier to make certain all of the
6885 * status bits have been updated before next_to_watch is written.
6886 */
6887 wmb();
6888
6889 /* set next_to_watch value indicating a packet is present */
6890 first->next_to_watch = tx_desc;
6891
6892 i++;
6893 if (i == tx_ring->count)
6894 i = 0;
6895
6896 tx_ring->next_to_use = i;
6897
6898 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6899
6900 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
6901 /* notify HW of packet */
6902 ixgbe_write_tail(tx_ring, i);
6903 }
6904
6905 return;
6906 dma_error:
6907 dev_err(tx_ring->dev, "TX DMA map failed\n");
6908
6909 /* clear dma mappings for failed tx_buffer_info map */
6910 for (;;) {
6911 tx_buffer = &tx_ring->tx_buffer_info[i];
6912 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6913 if (tx_buffer == first)
6914 break;
6915 if (i == 0)
6916 i = tx_ring->count;
6917 i--;
6918 }
6919
6920 tx_ring->next_to_use = i;
6921 }
6922
6923 static void ixgbe_atr(struct ixgbe_ring *ring,
6924 struct ixgbe_tx_buffer *first)
6925 {
6926 struct ixgbe_q_vector *q_vector = ring->q_vector;
6927 union ixgbe_atr_hash_dword input = { .dword = 0 };
6928 union ixgbe_atr_hash_dword common = { .dword = 0 };
6929 union {
6930 unsigned char *network;
6931 struct iphdr *ipv4;
6932 struct ipv6hdr *ipv6;
6933 } hdr;
6934 struct tcphdr *th;
6935 __be16 vlan_id;
6936
6937 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6938 if (!q_vector)
6939 return;
6940
6941 /* do nothing if sampling is disabled */
6942 if (!ring->atr_sample_rate)
6943 return;
6944
6945 ring->atr_count++;
6946
6947 /* snag network header to get L4 type and address */
6948 hdr.network = skb_network_header(first->skb);
6949
6950 /* Currently only IPv4/IPv6 with TCP is supported */
6951 if ((first->protocol != htons(ETH_P_IPV6) ||
6952 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6953 (first->protocol != htons(ETH_P_IP) ||
6954 hdr.ipv4->protocol != IPPROTO_TCP))
6955 return;
6956
6957 th = tcp_hdr(first->skb);
6958
6959 /* skip this packet since it is invalid or the socket is closing */
6960 if (!th || th->fin)
6961 return;
6962
6963 /* sample on all syn packets or once every atr sample count */
6964 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6965 return;
6966
6967 /* reset sample count */
6968 ring->atr_count = 0;
6969
6970 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6971
6972 /*
6973 * src and dst are inverted, think how the receiver sees them
6974 *
6975 * The input is broken into two sections, a non-compressed section
6976 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6977 * is XORed together and stored in the compressed dword.
6978 */
6979 input.formatted.vlan_id = vlan_id;
6980
6981 /*
6982 * since src port and flex bytes occupy the same word XOR them together
6983 * and write the value to source port portion of compressed dword
6984 */
6985 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6986 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
6987 else
6988 common.port.src ^= th->dest ^ first->protocol;
6989 common.port.dst ^= th->source;
6990
6991 if (first->protocol == htons(ETH_P_IP)) {
6992 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6993 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6994 } else {
6995 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6996 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6997 hdr.ipv6->saddr.s6_addr32[1] ^
6998 hdr.ipv6->saddr.s6_addr32[2] ^
6999 hdr.ipv6->saddr.s6_addr32[3] ^
7000 hdr.ipv6->daddr.s6_addr32[0] ^
7001 hdr.ipv6->daddr.s6_addr32[1] ^
7002 hdr.ipv6->daddr.s6_addr32[2] ^
7003 hdr.ipv6->daddr.s6_addr32[3];
7004 }
7005
7006 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
7007 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7008 input, common, ring->queue_index);
7009 }
7010
7011 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
7012 void *accel_priv, select_queue_fallback_t fallback)
7013 {
7014 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7015 #ifdef IXGBE_FCOE
7016 struct ixgbe_adapter *adapter;
7017 struct ixgbe_ring_feature *f;
7018 int txq;
7019 #endif
7020
7021 if (fwd_adapter)
7022 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7023
7024 #ifdef IXGBE_FCOE
7025
7026 /*
7027 * only execute the code below if protocol is FCoE
7028 * or FIP and we have FCoE enabled on the adapter
7029 */
7030 switch (vlan_get_protocol(skb)) {
7031 case htons(ETH_P_FCOE):
7032 case htons(ETH_P_FIP):
7033 adapter = netdev_priv(dev);
7034
7035 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7036 break;
7037 default:
7038 return fallback(dev, skb);
7039 }
7040
7041 f = &adapter->ring_feature[RING_F_FCOE];
7042
7043 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7044 smp_processor_id();
7045
7046 while (txq >= f->indices)
7047 txq -= f->indices;
7048
7049 return txq + f->offset;
7050 #else
7051 return fallback(dev, skb);
7052 #endif
7053 }
7054
7055 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
7056 struct ixgbe_adapter *adapter,
7057 struct ixgbe_ring *tx_ring)
7058 {
7059 struct ixgbe_tx_buffer *first;
7060 int tso;
7061 u32 tx_flags = 0;
7062 unsigned short f;
7063 u16 count = TXD_USE_COUNT(skb_headlen(skb));
7064 __be16 protocol = skb->protocol;
7065 u8 hdr_len = 0;
7066
7067 /*
7068 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
7069 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
7070 * + 2 desc gap to keep tail from touching head,
7071 * + 1 desc for context descriptor,
7072 * otherwise try next time
7073 */
7074 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7075 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7076
7077 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7078 tx_ring->tx_stats.tx_busy++;
7079 return NETDEV_TX_BUSY;
7080 }
7081
7082 /* record the location of the first descriptor for this packet */
7083 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7084 first->skb = skb;
7085 first->bytecount = skb->len;
7086 first->gso_segs = 1;
7087
7088 /* if we have a HW VLAN tag being added default to the HW one */
7089 if (vlan_tx_tag_present(skb)) {
7090 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7091 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7092 /* else if it is a SW VLAN check the next protocol and store the tag */
7093 } else if (protocol == htons(ETH_P_8021Q)) {
7094 struct vlan_hdr *vhdr, _vhdr;
7095 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7096 if (!vhdr)
7097 goto out_drop;
7098
7099 protocol = vhdr->h_vlan_encapsulated_proto;
7100 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7101 IXGBE_TX_FLAGS_VLAN_SHIFT;
7102 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7103 }
7104
7105 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7106 adapter->ptp_clock &&
7107 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7108 &adapter->state)) {
7109 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7110 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
7111
7112 /* schedule check for Tx timestamp */
7113 adapter->ptp_tx_skb = skb_get(skb);
7114 adapter->ptp_tx_start = jiffies;
7115 schedule_work(&adapter->ptp_tx_work);
7116 }
7117
7118 skb_tx_timestamp(skb);
7119
7120 #ifdef CONFIG_PCI_IOV
7121 /*
7122 * Use the l2switch_enable flag - would be false if the DMA
7123 * Tx switch had been disabled.
7124 */
7125 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7126 tx_flags |= IXGBE_TX_FLAGS_CC;
7127
7128 #endif
7129 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
7130 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7131 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7132 (skb->priority != TC_PRIO_CONTROL))) {
7133 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
7134 tx_flags |= (skb->priority & 0x7) <<
7135 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
7136 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7137 struct vlan_ethhdr *vhdr;
7138
7139 if (skb_cow_head(skb, 0))
7140 goto out_drop;
7141 vhdr = (struct vlan_ethhdr *)skb->data;
7142 vhdr->h_vlan_TCI = htons(tx_flags >>
7143 IXGBE_TX_FLAGS_VLAN_SHIFT);
7144 } else {
7145 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7146 }
7147 }
7148
7149 /* record initial flags and protocol */
7150 first->tx_flags = tx_flags;
7151 first->protocol = protocol;
7152
7153 #ifdef IXGBE_FCOE
7154 /* setup tx offload for FCoE */
7155 if ((protocol == htons(ETH_P_FCOE)) &&
7156 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
7157 tso = ixgbe_fso(tx_ring, first, &hdr_len);
7158 if (tso < 0)
7159 goto out_drop;
7160
7161 goto xmit_fcoe;
7162 }
7163
7164 #endif /* IXGBE_FCOE */
7165 tso = ixgbe_tso(tx_ring, first, &hdr_len);
7166 if (tso < 0)
7167 goto out_drop;
7168 else if (!tso)
7169 ixgbe_tx_csum(tx_ring, first);
7170
7171 /* add the ATR filter if ATR is on */
7172 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7173 ixgbe_atr(tx_ring, first);
7174
7175 #ifdef IXGBE_FCOE
7176 xmit_fcoe:
7177 #endif /* IXGBE_FCOE */
7178 ixgbe_tx_map(tx_ring, first, hdr_len);
7179
7180 return NETDEV_TX_OK;
7181
7182 out_drop:
7183 dev_kfree_skb_any(first->skb);
7184 first->skb = NULL;
7185
7186 return NETDEV_TX_OK;
7187 }
7188
7189 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7190 struct net_device *netdev,
7191 struct ixgbe_ring *ring)
7192 {
7193 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7194 struct ixgbe_ring *tx_ring;
7195
7196 /*
7197 * The minimum packet size for olinfo paylen is 17 so pad the skb
7198 * in order to meet this minimum size requirement.
7199 */
7200 if (unlikely(skb->len < 17)) {
7201 if (skb_pad(skb, 17 - skb->len))
7202 return NETDEV_TX_OK;
7203 skb->len = 17;
7204 skb_set_tail_pointer(skb, 17);
7205 }
7206
7207 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7208
7209 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
7210 }
7211
7212 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7213 struct net_device *netdev)
7214 {
7215 return __ixgbe_xmit_frame(skb, netdev, NULL);
7216 }
7217
7218 /**
7219 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7220 * @netdev: network interface device structure
7221 * @p: pointer to an address structure
7222 *
7223 * Returns 0 on success, negative on failure
7224 **/
7225 static int ixgbe_set_mac(struct net_device *netdev, void *p)
7226 {
7227 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7228 struct ixgbe_hw *hw = &adapter->hw;
7229 struct sockaddr *addr = p;
7230 int ret;
7231
7232 if (!is_valid_ether_addr(addr->sa_data))
7233 return -EADDRNOTAVAIL;
7234
7235 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7236 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
7237 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
7238
7239 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7240 return ret > 0 ? 0 : ret;
7241 }
7242
7243 static int
7244 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7245 {
7246 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7247 struct ixgbe_hw *hw = &adapter->hw;
7248 u16 value;
7249 int rc;
7250
7251 if (prtad != hw->phy.mdio.prtad)
7252 return -EINVAL;
7253 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7254 if (!rc)
7255 rc = value;
7256 return rc;
7257 }
7258
7259 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7260 u16 addr, u16 value)
7261 {
7262 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7263 struct ixgbe_hw *hw = &adapter->hw;
7264
7265 if (prtad != hw->phy.mdio.prtad)
7266 return -EINVAL;
7267 return hw->phy.ops.write_reg(hw, addr, devad, value);
7268 }
7269
7270 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7271 {
7272 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7273
7274 switch (cmd) {
7275 case SIOCSHWTSTAMP:
7276 return ixgbe_ptp_set_ts_config(adapter, req);
7277 case SIOCGHWTSTAMP:
7278 return ixgbe_ptp_get_ts_config(adapter, req);
7279 default:
7280 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7281 }
7282 }
7283
7284 /**
7285 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
7286 * netdev->dev_addrs
7287 * @netdev: network interface device structure
7288 *
7289 * Returns non-zero on failure
7290 **/
7291 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7292 {
7293 int err = 0;
7294 struct ixgbe_adapter *adapter = netdev_priv(dev);
7295 struct ixgbe_hw *hw = &adapter->hw;
7296
7297 if (is_valid_ether_addr(hw->mac.san_addr)) {
7298 rtnl_lock();
7299 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
7300 rtnl_unlock();
7301
7302 /* update SAN MAC vmdq pool selection */
7303 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
7304 }
7305 return err;
7306 }
7307
7308 /**
7309 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7310 * netdev->dev_addrs
7311 * @netdev: network interface device structure
7312 *
7313 * Returns non-zero on failure
7314 **/
7315 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7316 {
7317 int err = 0;
7318 struct ixgbe_adapter *adapter = netdev_priv(dev);
7319 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7320
7321 if (is_valid_ether_addr(mac->san_addr)) {
7322 rtnl_lock();
7323 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7324 rtnl_unlock();
7325 }
7326 return err;
7327 }
7328
7329 #ifdef CONFIG_NET_POLL_CONTROLLER
7330 /*
7331 * Polling 'interrupt' - used by things like netconsole to send skbs
7332 * without having to re-enable interrupts. It's not called while
7333 * the interrupt routine is executing.
7334 */
7335 static void ixgbe_netpoll(struct net_device *netdev)
7336 {
7337 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7338 int i;
7339
7340 /* if interface is down do nothing */
7341 if (test_bit(__IXGBE_DOWN, &adapter->state))
7342 return;
7343
7344 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
7345 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7346 for (i = 0; i < adapter->num_q_vectors; i++)
7347 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
7348 } else {
7349 ixgbe_intr(adapter->pdev->irq, netdev);
7350 }
7351 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7352 }
7353
7354 #endif
7355 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7356 struct rtnl_link_stats64 *stats)
7357 {
7358 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7359 int i;
7360
7361 rcu_read_lock();
7362 for (i = 0; i < adapter->num_rx_queues; i++) {
7363 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7364 u64 bytes, packets;
7365 unsigned int start;
7366
7367 if (ring) {
7368 do {
7369 start = u64_stats_fetch_begin_irq(&ring->syncp);
7370 packets = ring->stats.packets;
7371 bytes = ring->stats.bytes;
7372 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
7373 stats->rx_packets += packets;
7374 stats->rx_bytes += bytes;
7375 }
7376 }
7377
7378 for (i = 0; i < adapter->num_tx_queues; i++) {
7379 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7380 u64 bytes, packets;
7381 unsigned int start;
7382
7383 if (ring) {
7384 do {
7385 start = u64_stats_fetch_begin_irq(&ring->syncp);
7386 packets = ring->stats.packets;
7387 bytes = ring->stats.bytes;
7388 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
7389 stats->tx_packets += packets;
7390 stats->tx_bytes += bytes;
7391 }
7392 }
7393 rcu_read_unlock();
7394 /* following stats updated by ixgbe_watchdog_task() */
7395 stats->multicast = netdev->stats.multicast;
7396 stats->rx_errors = netdev->stats.rx_errors;
7397 stats->rx_length_errors = netdev->stats.rx_length_errors;
7398 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7399 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7400 return stats;
7401 }
7402
7403 #ifdef CONFIG_IXGBE_DCB
7404 /**
7405 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7406 * @adapter: pointer to ixgbe_adapter
7407 * @tc: number of traffic classes currently enabled
7408 *
7409 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7410 * 802.1Q priority maps to a packet buffer that exists.
7411 */
7412 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7413 {
7414 struct ixgbe_hw *hw = &adapter->hw;
7415 u32 reg, rsave;
7416 int i;
7417
7418 /* 82598 have a static priority to TC mapping that can not
7419 * be changed so no validation is needed.
7420 */
7421 if (hw->mac.type == ixgbe_mac_82598EB)
7422 return;
7423
7424 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7425 rsave = reg;
7426
7427 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7428 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7429
7430 /* If up2tc is out of bounds default to zero */
7431 if (up2tc > tc)
7432 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7433 }
7434
7435 if (reg != rsave)
7436 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7437
7438 return;
7439 }
7440
7441 /**
7442 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7443 * @adapter: Pointer to adapter struct
7444 *
7445 * Populate the netdev user priority to tc map
7446 */
7447 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7448 {
7449 struct net_device *dev = adapter->netdev;
7450 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7451 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7452 u8 prio;
7453
7454 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7455 u8 tc = 0;
7456
7457 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7458 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7459 else if (ets)
7460 tc = ets->prio_tc[prio];
7461
7462 netdev_set_prio_tc_map(dev, prio, tc);
7463 }
7464 }
7465
7466 #endif /* CONFIG_IXGBE_DCB */
7467 /**
7468 * ixgbe_setup_tc - configure net_device for multiple traffic classes
7469 *
7470 * @netdev: net device to configure
7471 * @tc: number of traffic classes to enable
7472 */
7473 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7474 {
7475 struct ixgbe_adapter *adapter = netdev_priv(dev);
7476 struct ixgbe_hw *hw = &adapter->hw;
7477 bool pools;
7478
7479 /* Hardware supports up to 8 traffic classes */
7480 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
7481 (hw->mac.type == ixgbe_mac_82598EB &&
7482 tc < MAX_TRAFFIC_CLASS))
7483 return -EINVAL;
7484
7485 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7486 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7487 return -EBUSY;
7488
7489 /* Hardware has to reinitialize queues and interrupts to
7490 * match packet buffer alignment. Unfortunately, the
7491 * hardware is not flexible enough to do this dynamically.
7492 */
7493 if (netif_running(dev))
7494 ixgbe_close(dev);
7495 ixgbe_clear_interrupt_scheme(adapter);
7496
7497 #ifdef CONFIG_IXGBE_DCB
7498 if (tc) {
7499 netdev_set_num_tc(dev, tc);
7500 ixgbe_set_prio_tc_map(adapter);
7501
7502 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7503
7504 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7505 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
7506 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7507 }
7508 } else {
7509 netdev_reset_tc(dev);
7510
7511 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7512 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7513
7514 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7515
7516 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7517 adapter->dcb_cfg.pfc_mode_enable = false;
7518 }
7519
7520 ixgbe_validate_rtr(adapter, tc);
7521
7522 #endif /* CONFIG_IXGBE_DCB */
7523 ixgbe_init_interrupt_scheme(adapter);
7524
7525 if (netif_running(dev))
7526 return ixgbe_open(dev);
7527
7528 return 0;
7529 }
7530
7531 #ifdef CONFIG_PCI_IOV
7532 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7533 {
7534 struct net_device *netdev = adapter->netdev;
7535
7536 rtnl_lock();
7537 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
7538 rtnl_unlock();
7539 }
7540
7541 #endif
7542 void ixgbe_do_reset(struct net_device *netdev)
7543 {
7544 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7545
7546 if (netif_running(netdev))
7547 ixgbe_reinit_locked(adapter);
7548 else
7549 ixgbe_reset(adapter);
7550 }
7551
7552 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7553 netdev_features_t features)
7554 {
7555 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7556
7557 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7558 if (!(features & NETIF_F_RXCSUM))
7559 features &= ~NETIF_F_LRO;
7560
7561 /* Turn off LRO if not RSC capable */
7562 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7563 features &= ~NETIF_F_LRO;
7564
7565 return features;
7566 }
7567
7568 static int ixgbe_set_features(struct net_device *netdev,
7569 netdev_features_t features)
7570 {
7571 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7572 netdev_features_t changed = netdev->features ^ features;
7573 bool need_reset = false;
7574
7575 /* Make sure RSC matches LRO, reset if change */
7576 if (!(features & NETIF_F_LRO)) {
7577 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7578 need_reset = true;
7579 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7580 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7581 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7582 if (adapter->rx_itr_setting == 1 ||
7583 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7584 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7585 need_reset = true;
7586 } else if ((changed ^ features) & NETIF_F_LRO) {
7587 e_info(probe, "rx-usecs set too low, "
7588 "disabling RSC\n");
7589 }
7590 }
7591
7592 /*
7593 * Check if Flow Director n-tuple support was enabled or disabled. If
7594 * the state changed, we need to reset.
7595 */
7596 switch (features & NETIF_F_NTUPLE) {
7597 case NETIF_F_NTUPLE:
7598 /* turn off ATR, enable perfect filters and reset */
7599 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7600 need_reset = true;
7601
7602 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7603 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7604 break;
7605 default:
7606 /* turn off perfect filters, enable ATR and reset */
7607 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7608 need_reset = true;
7609
7610 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7611
7612 /* We cannot enable ATR if SR-IOV is enabled */
7613 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7614 break;
7615
7616 /* We cannot enable ATR if we have 2 or more traffic classes */
7617 if (netdev_get_num_tc(netdev) > 1)
7618 break;
7619
7620 /* We cannot enable ATR if RSS is disabled */
7621 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7622 break;
7623
7624 /* A sample rate of 0 indicates ATR disabled */
7625 if (!adapter->atr_sample_rate)
7626 break;
7627
7628 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7629 break;
7630 }
7631
7632 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7633 ixgbe_vlan_strip_enable(adapter);
7634 else
7635 ixgbe_vlan_strip_disable(adapter);
7636
7637 if (changed & NETIF_F_RXALL)
7638 need_reset = true;
7639
7640 netdev->features = features;
7641 if (need_reset)
7642 ixgbe_do_reset(netdev);
7643
7644 return 0;
7645 }
7646
7647 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7648 struct net_device *dev,
7649 const unsigned char *addr,
7650 u16 flags)
7651 {
7652 /* guarantee we can provide a unique filter for the unicast address */
7653 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
7654 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev))
7655 return -ENOMEM;
7656 }
7657
7658 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
7659 }
7660
7661 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7662 struct nlmsghdr *nlh)
7663 {
7664 struct ixgbe_adapter *adapter = netdev_priv(dev);
7665 struct nlattr *attr, *br_spec;
7666 int rem;
7667
7668 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7669 return -EOPNOTSUPP;
7670
7671 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7672 if (!br_spec)
7673 return -EINVAL;
7674
7675 nla_for_each_nested(attr, br_spec, rem) {
7676 __u16 mode;
7677 u32 reg = 0;
7678
7679 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7680 continue;
7681
7682 if (nla_len(attr) < sizeof(mode))
7683 return -EINVAL;
7684
7685 mode = nla_get_u16(attr);
7686 if (mode == BRIDGE_MODE_VEPA) {
7687 reg = 0;
7688 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7689 } else if (mode == BRIDGE_MODE_VEB) {
7690 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7691 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7692 } else
7693 return -EINVAL;
7694
7695 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7696
7697 e_info(drv, "enabling bridge mode: %s\n",
7698 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7699 }
7700
7701 return 0;
7702 }
7703
7704 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7705 struct net_device *dev,
7706 u32 filter_mask)
7707 {
7708 struct ixgbe_adapter *adapter = netdev_priv(dev);
7709 u16 mode;
7710
7711 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7712 return 0;
7713
7714 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
7715 mode = BRIDGE_MODE_VEB;
7716 else
7717 mode = BRIDGE_MODE_VEPA;
7718
7719 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7720 }
7721
7722 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
7723 {
7724 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
7725 struct ixgbe_adapter *adapter = netdev_priv(pdev);
7726 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
7727 unsigned int limit;
7728 int pool, err;
7729
7730 /* Hardware has a limited number of available pools. Each VF, and the
7731 * PF require a pool. Check to ensure we don't attempt to use more
7732 * then the available number of pools.
7733 */
7734 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
7735 return ERR_PTR(-EINVAL);
7736
7737 #ifdef CONFIG_RPS
7738 if (vdev->num_rx_queues != vdev->num_tx_queues) {
7739 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
7740 vdev->name);
7741 return ERR_PTR(-EINVAL);
7742 }
7743 #endif
7744 /* Check for hardware restriction on number of rx/tx queues */
7745 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
7746 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
7747 netdev_info(pdev,
7748 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
7749 pdev->name);
7750 return ERR_PTR(-EINVAL);
7751 }
7752
7753 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7754 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
7755 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
7756 return ERR_PTR(-EBUSY);
7757
7758 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL);
7759 if (!fwd_adapter)
7760 return ERR_PTR(-ENOMEM);
7761
7762 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
7763 adapter->num_rx_pools++;
7764 set_bit(pool, &adapter->fwd_bitmask);
7765 limit = find_last_bit(&adapter->fwd_bitmask, 32);
7766
7767 /* Enable VMDq flag so device will be set in VM mode */
7768 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
7769 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
7770 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
7771
7772 /* Force reinit of ring allocation with VMDQ enabled */
7773 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7774 if (err)
7775 goto fwd_add_err;
7776 fwd_adapter->pool = pool;
7777 fwd_adapter->real_adapter = adapter;
7778 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
7779 if (err)
7780 goto fwd_add_err;
7781 netif_tx_start_all_queues(vdev);
7782 return fwd_adapter;
7783 fwd_add_err:
7784 /* unwind counter and free adapter struct */
7785 netdev_info(pdev,
7786 "%s: dfwd hardware acceleration failed\n", vdev->name);
7787 clear_bit(pool, &adapter->fwd_bitmask);
7788 adapter->num_rx_pools--;
7789 kfree(fwd_adapter);
7790 return ERR_PTR(err);
7791 }
7792
7793 static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
7794 {
7795 struct ixgbe_fwd_adapter *fwd_adapter = priv;
7796 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
7797 unsigned int limit;
7798
7799 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
7800 adapter->num_rx_pools--;
7801
7802 limit = find_last_bit(&adapter->fwd_bitmask, 32);
7803 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
7804 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
7805 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7806 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
7807 fwd_adapter->pool, adapter->num_rx_pools,
7808 fwd_adapter->rx_base_queue,
7809 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
7810 adapter->fwd_bitmask);
7811 kfree(fwd_adapter);
7812 }
7813
7814 static const struct net_device_ops ixgbe_netdev_ops = {
7815 .ndo_open = ixgbe_open,
7816 .ndo_stop = ixgbe_close,
7817 .ndo_start_xmit = ixgbe_xmit_frame,
7818 .ndo_select_queue = ixgbe_select_queue,
7819 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7820 .ndo_validate_addr = eth_validate_addr,
7821 .ndo_set_mac_address = ixgbe_set_mac,
7822 .ndo_change_mtu = ixgbe_change_mtu,
7823 .ndo_tx_timeout = ixgbe_tx_timeout,
7824 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7825 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7826 .ndo_do_ioctl = ixgbe_ioctl,
7827 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7828 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7829 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
7830 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7831 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7832 .ndo_get_stats64 = ixgbe_get_stats64,
7833 #ifdef CONFIG_IXGBE_DCB
7834 .ndo_setup_tc = ixgbe_setup_tc,
7835 #endif
7836 #ifdef CONFIG_NET_POLL_CONTROLLER
7837 .ndo_poll_controller = ixgbe_netpoll,
7838 #endif
7839 #ifdef CONFIG_NET_RX_BUSY_POLL
7840 .ndo_busy_poll = ixgbe_low_latency_recv,
7841 #endif
7842 #ifdef IXGBE_FCOE
7843 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7844 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7845 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7846 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7847 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7848 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7849 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7850 #endif /* IXGBE_FCOE */
7851 .ndo_set_features = ixgbe_set_features,
7852 .ndo_fix_features = ixgbe_fix_features,
7853 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7854 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7855 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
7856 .ndo_dfwd_add_station = ixgbe_fwd_add,
7857 .ndo_dfwd_del_station = ixgbe_fwd_del,
7858 };
7859
7860 /**
7861 * ixgbe_enumerate_functions - Get the number of ports this device has
7862 * @adapter: adapter structure
7863 *
7864 * This function enumerates the phsyical functions co-located on a single slot,
7865 * in order to determine how many ports a device has. This is most useful in
7866 * determining the required GT/s of PCIe bandwidth necessary for optimal
7867 * performance.
7868 **/
7869 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7870 {
7871 struct pci_dev *entry, *pdev = adapter->pdev;
7872 int physfns = 0;
7873
7874 /* Some cards can not use the generic count PCIe functions method,
7875 * because they are behind a parent switch, so we hardcode these with
7876 * the correct number of functions.
7877 */
7878 if (ixgbe_pcie_from_parent(&adapter->hw))
7879 physfns = 4;
7880
7881 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
7882 /* don't count virtual functions */
7883 if (entry->is_virtfn)
7884 continue;
7885
7886 /* When the devices on the bus don't all match our device ID,
7887 * we can't reliably determine the correct number of
7888 * functions. This can occur if a function has been direct
7889 * attached to a virtual machine using VT-d, for example. In
7890 * this case, simply return -1 to indicate this.
7891 */
7892 if ((entry->vendor != pdev->vendor) ||
7893 (entry->device != pdev->device))
7894 return -1;
7895
7896 physfns++;
7897 }
7898
7899 return physfns;
7900 }
7901
7902 /**
7903 * ixgbe_wol_supported - Check whether device supports WoL
7904 * @hw: hw specific details
7905 * @device_id: the device ID
7906 * @subdev_id: the subsystem device ID
7907 *
7908 * This function is used by probe and ethtool to determine
7909 * which devices have WoL support
7910 *
7911 **/
7912 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7913 u16 subdevice_id)
7914 {
7915 struct ixgbe_hw *hw = &adapter->hw;
7916 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7917 int is_wol_supported = 0;
7918
7919 switch (device_id) {
7920 case IXGBE_DEV_ID_82599_SFP:
7921 /* Only these subdevices could supports WOL */
7922 switch (subdevice_id) {
7923 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
7924 case IXGBE_SUBDEV_ID_82599_560FLR:
7925 /* only support first port */
7926 if (hw->bus.func != 0)
7927 break;
7928 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
7929 case IXGBE_SUBDEV_ID_82599_SFP:
7930 case IXGBE_SUBDEV_ID_82599_RNDC:
7931 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
7932 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
7933 is_wol_supported = 1;
7934 break;
7935 }
7936 break;
7937 case IXGBE_DEV_ID_82599EN_SFP:
7938 /* Only this subdevice supports WOL */
7939 switch (subdevice_id) {
7940 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
7941 is_wol_supported = 1;
7942 break;
7943 }
7944 break;
7945 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7946 /* All except this subdevice support WOL */
7947 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7948 is_wol_supported = 1;
7949 break;
7950 case IXGBE_DEV_ID_82599_KX4:
7951 is_wol_supported = 1;
7952 break;
7953 case IXGBE_DEV_ID_X540T:
7954 case IXGBE_DEV_ID_X540T1:
7955 /* check eeprom to see if enabled wol */
7956 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7957 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7958 (hw->bus.func == 0))) {
7959 is_wol_supported = 1;
7960 }
7961 break;
7962 }
7963
7964 return is_wol_supported;
7965 }
7966
7967 /**
7968 * ixgbe_probe - Device Initialization Routine
7969 * @pdev: PCI device information struct
7970 * @ent: entry in ixgbe_pci_tbl
7971 *
7972 * Returns 0 on success, negative on failure
7973 *
7974 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7975 * The OS initialization, configuring of the adapter private structure,
7976 * and a hardware reset occur.
7977 **/
7978 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7979 {
7980 struct net_device *netdev;
7981 struct ixgbe_adapter *adapter = NULL;
7982 struct ixgbe_hw *hw;
7983 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7984 int i, err, pci_using_dac, expected_gts;
7985 unsigned int indices = MAX_TX_QUEUES;
7986 u8 part_str[IXGBE_PBANUM_LENGTH];
7987 bool disable_dev = false;
7988 #ifdef IXGBE_FCOE
7989 u16 device_caps;
7990 #endif
7991 u32 eec;
7992
7993 /* Catch broken hardware that put the wrong VF device ID in
7994 * the PCIe SR-IOV capability.
7995 */
7996 if (pdev->is_virtfn) {
7997 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7998 pci_name(pdev), pdev->vendor, pdev->device);
7999 return -EINVAL;
8000 }
8001
8002 err = pci_enable_device_mem(pdev);
8003 if (err)
8004 return err;
8005
8006 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
8007 pci_using_dac = 1;
8008 } else {
8009 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8010 if (err) {
8011 dev_err(&pdev->dev,
8012 "No usable DMA configuration, aborting\n");
8013 goto err_dma;
8014 }
8015 pci_using_dac = 0;
8016 }
8017
8018 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8019 IORESOURCE_MEM), ixgbe_driver_name);
8020 if (err) {
8021 dev_err(&pdev->dev,
8022 "pci_request_selected_regions failed 0x%x\n", err);
8023 goto err_pci_reg;
8024 }
8025
8026 pci_enable_pcie_error_reporting(pdev);
8027
8028 pci_set_master(pdev);
8029 pci_save_state(pdev);
8030
8031 if (ii->mac == ixgbe_mac_82598EB) {
8032 #ifdef CONFIG_IXGBE_DCB
8033 /* 8 TC w/ 4 queues per TC */
8034 indices = 4 * MAX_TRAFFIC_CLASS;
8035 #else
8036 indices = IXGBE_MAX_RSS_INDICES;
8037 #endif
8038 }
8039
8040 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
8041 if (!netdev) {
8042 err = -ENOMEM;
8043 goto err_alloc_etherdev;
8044 }
8045
8046 SET_NETDEV_DEV(netdev, &pdev->dev);
8047
8048 adapter = netdev_priv(netdev);
8049 pci_set_drvdata(pdev, adapter);
8050
8051 adapter->netdev = netdev;
8052 adapter->pdev = pdev;
8053 hw = &adapter->hw;
8054 hw->back = adapter;
8055 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
8056
8057 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8058 pci_resource_len(pdev, 0));
8059 adapter->io_addr = hw->hw_addr;
8060 if (!hw->hw_addr) {
8061 err = -EIO;
8062 goto err_ioremap;
8063 }
8064
8065 netdev->netdev_ops = &ixgbe_netdev_ops;
8066 ixgbe_set_ethtool_ops(netdev);
8067 netdev->watchdog_timeo = 5 * HZ;
8068 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
8069
8070 /* Setup hw api */
8071 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
8072 hw->mac.type = ii->mac;
8073
8074 /* EEPROM */
8075 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
8076 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
8077 if (ixgbe_removed(hw->hw_addr)) {
8078 err = -EIO;
8079 goto err_ioremap;
8080 }
8081 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8082 if (!(eec & (1 << 8)))
8083 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8084
8085 /* PHY */
8086 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
8087 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
8088 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8089 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8090 hw->phy.mdio.mmds = 0;
8091 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8092 hw->phy.mdio.dev = netdev;
8093 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8094 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
8095
8096 ii->get_invariants(hw);
8097
8098 /* setup the private structure */
8099 err = ixgbe_sw_init(adapter);
8100 if (err)
8101 goto err_sw_init;
8102
8103 /* Make it possible the adapter to be woken up via WOL */
8104 switch (adapter->hw.mac.type) {
8105 case ixgbe_mac_82599EB:
8106 case ixgbe_mac_X540:
8107 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
8108 break;
8109 default:
8110 break;
8111 }
8112
8113 /*
8114 * If there is a fan on this device and it has failed log the
8115 * failure.
8116 */
8117 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8118 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8119 if (esdp & IXGBE_ESDP_SDP1)
8120 e_crit(probe, "Fan has stopped, replace the adapter\n");
8121 }
8122
8123 if (allow_unsupported_sfp)
8124 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8125
8126 /* reset_hw fills in the perm_addr as well */
8127 hw->phy.reset_if_overtemp = true;
8128 err = hw->mac.ops.reset_hw(hw);
8129 hw->phy.reset_if_overtemp = false;
8130 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
8131 hw->mac.type == ixgbe_mac_82598EB) {
8132 err = 0;
8133 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
8134 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8135 e_dev_err("Reload the driver after installing a supported module.\n");
8136 goto err_sw_init;
8137 } else if (err) {
8138 e_dev_err("HW Init failed: %d\n", err);
8139 goto err_sw_init;
8140 }
8141
8142 #ifdef CONFIG_PCI_IOV
8143 /* SR-IOV not supported on the 82598 */
8144 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8145 goto skip_sriov;
8146 /* Mailbox */
8147 ixgbe_init_mbx_params_pf(hw);
8148 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
8149 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
8150 ixgbe_enable_sriov(adapter);
8151 skip_sriov:
8152
8153 #endif
8154 netdev->features = NETIF_F_SG |
8155 NETIF_F_IP_CSUM |
8156 NETIF_F_IPV6_CSUM |
8157 NETIF_F_HW_VLAN_CTAG_TX |
8158 NETIF_F_HW_VLAN_CTAG_RX |
8159 NETIF_F_HW_VLAN_CTAG_FILTER |
8160 NETIF_F_TSO |
8161 NETIF_F_TSO6 |
8162 NETIF_F_RXHASH |
8163 NETIF_F_RXCSUM;
8164
8165 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
8166
8167 switch (adapter->hw.mac.type) {
8168 case ixgbe_mac_82599EB:
8169 case ixgbe_mac_X540:
8170 netdev->features |= NETIF_F_SCTP_CSUM;
8171 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8172 NETIF_F_NTUPLE;
8173 break;
8174 default:
8175 break;
8176 }
8177
8178 netdev->hw_features |= NETIF_F_RXALL;
8179
8180 netdev->vlan_features |= NETIF_F_TSO;
8181 netdev->vlan_features |= NETIF_F_TSO6;
8182 netdev->vlan_features |= NETIF_F_IP_CSUM;
8183 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
8184 netdev->vlan_features |= NETIF_F_SG;
8185
8186 netdev->priv_flags |= IFF_UNICAST_FLT;
8187 netdev->priv_flags |= IFF_SUPP_NOFCS;
8188
8189 #ifdef CONFIG_IXGBE_DCB
8190 netdev->dcbnl_ops = &dcbnl_ops;
8191 #endif
8192
8193 #ifdef IXGBE_FCOE
8194 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
8195 unsigned int fcoe_l;
8196
8197 if (hw->mac.ops.get_device_caps) {
8198 hw->mac.ops.get_device_caps(hw, &device_caps);
8199 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8200 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
8201 }
8202
8203
8204 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8205 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
8206
8207 netdev->features |= NETIF_F_FSO |
8208 NETIF_F_FCOE_CRC;
8209
8210 netdev->vlan_features |= NETIF_F_FSO |
8211 NETIF_F_FCOE_CRC |
8212 NETIF_F_FCOE_MTU;
8213 }
8214 #endif /* IXGBE_FCOE */
8215 if (pci_using_dac) {
8216 netdev->features |= NETIF_F_HIGHDMA;
8217 netdev->vlan_features |= NETIF_F_HIGHDMA;
8218 }
8219
8220 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8221 netdev->hw_features |= NETIF_F_LRO;
8222 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
8223 netdev->features |= NETIF_F_LRO;
8224
8225 /* make sure the EEPROM is good */
8226 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
8227 e_dev_err("The EEPROM Checksum Is Not Valid\n");
8228 err = -EIO;
8229 goto err_sw_init;
8230 }
8231
8232 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
8233
8234 if (!is_valid_ether_addr(netdev->dev_addr)) {
8235 e_dev_err("invalid MAC address\n");
8236 err = -EIO;
8237 goto err_sw_init;
8238 }
8239
8240 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr);
8241
8242 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
8243 (unsigned long) adapter);
8244
8245 if (ixgbe_removed(hw->hw_addr)) {
8246 err = -EIO;
8247 goto err_sw_init;
8248 }
8249 INIT_WORK(&adapter->service_task, ixgbe_service_task);
8250 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
8251 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
8252
8253 err = ixgbe_init_interrupt_scheme(adapter);
8254 if (err)
8255 goto err_sw_init;
8256
8257 /* WOL not supported for all devices */
8258 adapter->wol = 0;
8259 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
8260 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
8261 pdev->subsystem_device);
8262 if (hw->wol_enabled)
8263 adapter->wol = IXGBE_WUFC_MAG;
8264
8265 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8266
8267 /* save off EEPROM version number */
8268 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8269 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8270
8271 /* pick up the PCI bus settings for reporting later */
8272 hw->mac.ops.get_bus_info(hw);
8273 if (ixgbe_pcie_from_parent(hw))
8274 ixgbe_get_parent_bus_info(adapter);
8275
8276 /* calculate the expected PCIe bandwidth required for optimal
8277 * performance. Note that some older parts will never have enough
8278 * bandwidth due to being older generation PCIe parts. We clamp these
8279 * parts to ensure no warning is displayed if it can't be fixed.
8280 */
8281 switch (hw->mac.type) {
8282 case ixgbe_mac_82598EB:
8283 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8284 break;
8285 default:
8286 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8287 break;
8288 }
8289
8290 /* don't check link if we failed to enumerate functions */
8291 if (expected_gts > 0)
8292 ixgbe_check_minimum_link(adapter, expected_gts);
8293
8294 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
8295 if (err)
8296 strlcpy(part_str, "Unknown", sizeof(part_str));
8297 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8298 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8299 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
8300 part_str);
8301 else
8302 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8303 hw->mac.type, hw->phy.type, part_str);
8304
8305 e_dev_info("%pM\n", netdev->dev_addr);
8306
8307 /* reset the hardware with the new settings */
8308 err = hw->mac.ops.start_hw(hw);
8309 if (err == IXGBE_ERR_EEPROM_VERSION) {
8310 /* We are running on a pre-production device, log a warning */
8311 e_dev_warn("This device is a pre-production adapter/LOM. "
8312 "Please be aware there may be issues associated "
8313 "with your hardware. If you are experiencing "
8314 "problems please contact your Intel or hardware "
8315 "representative who provided you with this "
8316 "hardware.\n");
8317 }
8318 strcpy(netdev->name, "eth%d");
8319 err = register_netdev(netdev);
8320 if (err)
8321 goto err_register;
8322
8323 /* power down the optics for 82599 SFP+ fiber */
8324 if (hw->mac.ops.disable_tx_laser)
8325 hw->mac.ops.disable_tx_laser(hw);
8326
8327 /* carrier off reporting is important to ethtool even BEFORE open */
8328 netif_carrier_off(netdev);
8329
8330 #ifdef CONFIG_IXGBE_DCA
8331 if (dca_add_requester(&pdev->dev) == 0) {
8332 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
8333 ixgbe_setup_dca(adapter);
8334 }
8335 #endif
8336 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
8337 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
8338 for (i = 0; i < adapter->num_vfs; i++)
8339 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8340 }
8341
8342 /* firmware requires driver version to be 0xFFFFFFFF
8343 * since os does not support feature
8344 */
8345 if (hw->mac.ops.set_fw_drv_ver)
8346 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8347 0xFF);
8348
8349 /* add san mac addr to netdev */
8350 ixgbe_add_sanmac_netdev(netdev);
8351
8352 e_dev_info("%s\n", ixgbe_default_device_descr);
8353
8354 #ifdef CONFIG_IXGBE_HWMON
8355 if (ixgbe_sysfs_init(adapter))
8356 e_err(probe, "failed to allocate sysfs resources\n");
8357 #endif /* CONFIG_IXGBE_HWMON */
8358
8359 ixgbe_dbg_adapter_init(adapter);
8360
8361 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
8362 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
8363 hw->mac.ops.setup_link(hw,
8364 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8365 true);
8366
8367 return 0;
8368
8369 err_register:
8370 ixgbe_release_hw_control(adapter);
8371 ixgbe_clear_interrupt_scheme(adapter);
8372 err_sw_init:
8373 ixgbe_disable_sriov(adapter);
8374 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
8375 iounmap(adapter->io_addr);
8376 kfree(adapter->mac_table);
8377 err_ioremap:
8378 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
8379 free_netdev(netdev);
8380 err_alloc_etherdev:
8381 pci_release_selected_regions(pdev,
8382 pci_select_bars(pdev, IORESOURCE_MEM));
8383 err_pci_reg:
8384 err_dma:
8385 if (!adapter || disable_dev)
8386 pci_disable_device(pdev);
8387 return err;
8388 }
8389
8390 /**
8391 * ixgbe_remove - Device Removal Routine
8392 * @pdev: PCI device information struct
8393 *
8394 * ixgbe_remove is called by the PCI subsystem to alert the driver
8395 * that it should release a PCI device. The could be caused by a
8396 * Hot-Plug event, or because the driver is going to be removed from
8397 * memory.
8398 **/
8399 static void ixgbe_remove(struct pci_dev *pdev)
8400 {
8401 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8402 struct net_device *netdev = adapter->netdev;
8403 bool disable_dev;
8404
8405 ixgbe_dbg_adapter_exit(adapter);
8406
8407 set_bit(__IXGBE_REMOVING, &adapter->state);
8408 cancel_work_sync(&adapter->service_task);
8409
8410
8411 #ifdef CONFIG_IXGBE_DCA
8412 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8413 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8414 dca_remove_requester(&pdev->dev);
8415 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8416 }
8417
8418 #endif
8419 #ifdef CONFIG_IXGBE_HWMON
8420 ixgbe_sysfs_exit(adapter);
8421 #endif /* CONFIG_IXGBE_HWMON */
8422
8423 /* remove the added san mac */
8424 ixgbe_del_sanmac_netdev(netdev);
8425
8426 if (netdev->reg_state == NETREG_REGISTERED)
8427 unregister_netdev(netdev);
8428
8429 #ifdef CONFIG_PCI_IOV
8430 /*
8431 * Only disable SR-IOV on unload if the user specified the now
8432 * deprecated max_vfs module parameter.
8433 */
8434 if (max_vfs)
8435 ixgbe_disable_sriov(adapter);
8436 #endif
8437 ixgbe_clear_interrupt_scheme(adapter);
8438
8439 ixgbe_release_hw_control(adapter);
8440
8441 #ifdef CONFIG_DCB
8442 kfree(adapter->ixgbe_ieee_pfc);
8443 kfree(adapter->ixgbe_ieee_ets);
8444
8445 #endif
8446 iounmap(adapter->io_addr);
8447 pci_release_selected_regions(pdev, pci_select_bars(pdev,
8448 IORESOURCE_MEM));
8449
8450 e_dev_info("complete\n");
8451
8452 kfree(adapter->mac_table);
8453 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
8454 free_netdev(netdev);
8455
8456 pci_disable_pcie_error_reporting(pdev);
8457
8458 if (disable_dev)
8459 pci_disable_device(pdev);
8460 }
8461
8462 /**
8463 * ixgbe_io_error_detected - called when PCI error is detected
8464 * @pdev: Pointer to PCI device
8465 * @state: The current pci connection state
8466 *
8467 * This function is called after a PCI bus error affecting
8468 * this device has been detected.
8469 */
8470 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
8471 pci_channel_state_t state)
8472 {
8473 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8474 struct net_device *netdev = adapter->netdev;
8475
8476 #ifdef CONFIG_PCI_IOV
8477 struct ixgbe_hw *hw = &adapter->hw;
8478 struct pci_dev *bdev, *vfdev;
8479 u32 dw0, dw1, dw2, dw3;
8480 int vf, pos;
8481 u16 req_id, pf_func;
8482
8483 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8484 adapter->num_vfs == 0)
8485 goto skip_bad_vf_detection;
8486
8487 bdev = pdev->bus->self;
8488 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
8489 bdev = bdev->bus->self;
8490
8491 if (!bdev)
8492 goto skip_bad_vf_detection;
8493
8494 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8495 if (!pos)
8496 goto skip_bad_vf_detection;
8497
8498 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
8499 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
8500 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
8501 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
8502 if (ixgbe_removed(hw->hw_addr))
8503 goto skip_bad_vf_detection;
8504
8505 req_id = dw1 >> 16;
8506 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8507 if (!(req_id & 0x0080))
8508 goto skip_bad_vf_detection;
8509
8510 pf_func = req_id & 0x01;
8511 if ((pf_func & 1) == (pdev->devfn & 1)) {
8512 unsigned int device_id;
8513
8514 vf = (req_id & 0x7F) >> 1;
8515 e_dev_err("VF %d has caused a PCIe error\n", vf);
8516 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8517 "%8.8x\tdw3: %8.8x\n",
8518 dw0, dw1, dw2, dw3);
8519 switch (adapter->hw.mac.type) {
8520 case ixgbe_mac_82599EB:
8521 device_id = IXGBE_82599_VF_DEVICE_ID;
8522 break;
8523 case ixgbe_mac_X540:
8524 device_id = IXGBE_X540_VF_DEVICE_ID;
8525 break;
8526 default:
8527 device_id = 0;
8528 break;
8529 }
8530
8531 /* Find the pci device of the offending VF */
8532 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
8533 while (vfdev) {
8534 if (vfdev->devfn == (req_id & 0xFF))
8535 break;
8536 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
8537 device_id, vfdev);
8538 }
8539 /*
8540 * There's a slim chance the VF could have been hot plugged,
8541 * so if it is no longer present we don't need to issue the
8542 * VFLR. Just clean up the AER in that case.
8543 */
8544 if (vfdev) {
8545 e_dev_err("Issuing VFLR to VF %d\n", vf);
8546 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
8547 /* Free device reference count */
8548 pci_dev_put(vfdev);
8549 }
8550
8551 pci_cleanup_aer_uncorrect_error_status(pdev);
8552 }
8553
8554 /*
8555 * Even though the error may have occurred on the other port
8556 * we still need to increment the vf error reference count for
8557 * both ports because the I/O resume function will be called
8558 * for both of them.
8559 */
8560 adapter->vferr_refcount++;
8561
8562 return PCI_ERS_RESULT_RECOVERED;
8563
8564 skip_bad_vf_detection:
8565 #endif /* CONFIG_PCI_IOV */
8566 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
8567 return PCI_ERS_RESULT_DISCONNECT;
8568
8569 rtnl_lock();
8570 netif_device_detach(netdev);
8571
8572 if (state == pci_channel_io_perm_failure) {
8573 rtnl_unlock();
8574 return PCI_ERS_RESULT_DISCONNECT;
8575 }
8576
8577 if (netif_running(netdev))
8578 ixgbe_down(adapter);
8579
8580 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8581 pci_disable_device(pdev);
8582 rtnl_unlock();
8583
8584 /* Request a slot reset. */
8585 return PCI_ERS_RESULT_NEED_RESET;
8586 }
8587
8588 /**
8589 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8590 * @pdev: Pointer to PCI device
8591 *
8592 * Restart the card from scratch, as if from a cold-boot.
8593 */
8594 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8595 {
8596 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8597 pci_ers_result_t result;
8598 int err;
8599
8600 if (pci_enable_device_mem(pdev)) {
8601 e_err(probe, "Cannot re-enable PCI device after reset.\n");
8602 result = PCI_ERS_RESULT_DISCONNECT;
8603 } else {
8604 smp_mb__before_atomic();
8605 clear_bit(__IXGBE_DISABLED, &adapter->state);
8606 adapter->hw.hw_addr = adapter->io_addr;
8607 pci_set_master(pdev);
8608 pci_restore_state(pdev);
8609 pci_save_state(pdev);
8610
8611 pci_wake_from_d3(pdev, false);
8612
8613 ixgbe_reset(adapter);
8614 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
8615 result = PCI_ERS_RESULT_RECOVERED;
8616 }
8617
8618 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8619 if (err) {
8620 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8621 "failed 0x%0x\n", err);
8622 /* non-fatal, continue */
8623 }
8624
8625 return result;
8626 }
8627
8628 /**
8629 * ixgbe_io_resume - called when traffic can start flowing again.
8630 * @pdev: Pointer to PCI device
8631 *
8632 * This callback is called when the error recovery driver tells us that
8633 * its OK to resume normal operation.
8634 */
8635 static void ixgbe_io_resume(struct pci_dev *pdev)
8636 {
8637 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8638 struct net_device *netdev = adapter->netdev;
8639
8640 #ifdef CONFIG_PCI_IOV
8641 if (adapter->vferr_refcount) {
8642 e_info(drv, "Resuming after VF err\n");
8643 adapter->vferr_refcount--;
8644 return;
8645 }
8646
8647 #endif
8648 if (netif_running(netdev))
8649 ixgbe_up(adapter);
8650
8651 netif_device_attach(netdev);
8652 }
8653
8654 static const struct pci_error_handlers ixgbe_err_handler = {
8655 .error_detected = ixgbe_io_error_detected,
8656 .slot_reset = ixgbe_io_slot_reset,
8657 .resume = ixgbe_io_resume,
8658 };
8659
8660 static struct pci_driver ixgbe_driver = {
8661 .name = ixgbe_driver_name,
8662 .id_table = ixgbe_pci_tbl,
8663 .probe = ixgbe_probe,
8664 .remove = ixgbe_remove,
8665 #ifdef CONFIG_PM
8666 .suspend = ixgbe_suspend,
8667 .resume = ixgbe_resume,
8668 #endif
8669 .shutdown = ixgbe_shutdown,
8670 .sriov_configure = ixgbe_pci_sriov_configure,
8671 .err_handler = &ixgbe_err_handler
8672 };
8673
8674 /**
8675 * ixgbe_init_module - Driver Registration Routine
8676 *
8677 * ixgbe_init_module is the first routine called when the driver is
8678 * loaded. All it does is register with the PCI subsystem.
8679 **/
8680 static int __init ixgbe_init_module(void)
8681 {
8682 int ret;
8683 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
8684 pr_info("%s\n", ixgbe_copyright);
8685
8686 ixgbe_dbg_init();
8687
8688 ret = pci_register_driver(&ixgbe_driver);
8689 if (ret) {
8690 ixgbe_dbg_exit();
8691 return ret;
8692 }
8693
8694 #ifdef CONFIG_IXGBE_DCA
8695 dca_register_notify(&dca_notifier);
8696 #endif
8697
8698 return 0;
8699 }
8700
8701 module_init(ixgbe_init_module);
8702
8703 /**
8704 * ixgbe_exit_module - Driver Exit Cleanup Routine
8705 *
8706 * ixgbe_exit_module is called just before the driver is removed
8707 * from memory.
8708 **/
8709 static void __exit ixgbe_exit_module(void)
8710 {
8711 #ifdef CONFIG_IXGBE_DCA
8712 dca_unregister_notify(&dca_notifier);
8713 #endif
8714 pci_unregister_driver(&ixgbe_driver);
8715
8716 ixgbe_dbg_exit();
8717
8718 rcu_barrier(); /* Wait for completion of call_rcu()'s */
8719 }
8720
8721 #ifdef CONFIG_IXGBE_DCA
8722 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
8723 void *p)
8724 {
8725 int ret_val;
8726
8727 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
8728 __ixgbe_notify_dca);
8729
8730 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8731 }
8732
8733 #endif /* CONFIG_IXGBE_DCA */
8734
8735 module_exit(ixgbe_exit_module);
8736
8737 /* ixgbe_main.c */
Linux kernel - Deliverables
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