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rtlwifi: Change order in device startup
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_phy.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2014 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/pci.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
32
33 #include "ixgbe.h"
34 #include "ixgbe_phy.h"
35
36 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
37 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
38 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
39 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
40 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
41 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
42 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
43 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
45 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
46 static bool ixgbe_get_i2c_data(u32 *i2cctl);
47 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
48 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
49 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
50 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
51
52 /**
53 * ixgbe_identify_phy_generic - Get physical layer module
54 * @hw: pointer to hardware structure
55 *
56 * Determines the physical layer module found on the current adapter.
57 **/
58 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
59 {
60 u32 phy_addr;
61 u16 ext_ability = 0;
62
63 if (hw->phy.type == ixgbe_phy_unknown) {
64 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
65 hw->phy.mdio.prtad = phy_addr;
66 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
67 ixgbe_get_phy_id(hw);
68 hw->phy.type =
69 ixgbe_get_phy_type_from_id(hw->phy.id);
70
71 if (hw->phy.type == ixgbe_phy_unknown) {
72 hw->phy.ops.read_reg(hw,
73 MDIO_PMA_EXTABLE,
74 MDIO_MMD_PMAPMD,
75 &ext_ability);
76 if (ext_ability &
77 (MDIO_PMA_EXTABLE_10GBT |
78 MDIO_PMA_EXTABLE_1000BT))
79 hw->phy.type =
80 ixgbe_phy_cu_unknown;
81 else
82 hw->phy.type =
83 ixgbe_phy_generic;
84 }
85
86 return 0;
87 }
88 }
89 /* clear value if nothing found */
90 hw->phy.mdio.prtad = 0;
91 return IXGBE_ERR_PHY_ADDR_INVALID;
92 }
93 return 0;
94 }
95
96 /**
97 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
98 * @hw: pointer to the hardware structure
99 *
100 * This function checks the MMNGC.MNG_VETO bit to see if there are
101 * any constraints on link from manageability. For MAC's that don't
102 * have this bit just return false since the link can not be blocked
103 * via this method.
104 **/
105 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
106 {
107 u32 mmngc;
108
109 /* If we don't have this bit, it can't be blocking */
110 if (hw->mac.type == ixgbe_mac_82598EB)
111 return false;
112
113 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
114 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
115 hw_dbg(hw, "MNG_VETO bit detected.\n");
116 return true;
117 }
118
119 return false;
120 }
121
122 /**
123 * ixgbe_get_phy_id - Get the phy type
124 * @hw: pointer to hardware structure
125 *
126 **/
127 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
128 {
129 u32 status;
130 u16 phy_id_high = 0;
131 u16 phy_id_low = 0;
132
133 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
134 &phy_id_high);
135
136 if (status == 0) {
137 hw->phy.id = (u32)(phy_id_high << 16);
138 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
139 &phy_id_low);
140 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
141 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
142 }
143 return status;
144 }
145
146 /**
147 * ixgbe_get_phy_type_from_id - Get the phy type
148 * @hw: pointer to hardware structure
149 *
150 **/
151 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
152 {
153 enum ixgbe_phy_type phy_type;
154
155 switch (phy_id) {
156 case TN1010_PHY_ID:
157 phy_type = ixgbe_phy_tn;
158 break;
159 case X540_PHY_ID:
160 phy_type = ixgbe_phy_aq;
161 break;
162 case QT2022_PHY_ID:
163 phy_type = ixgbe_phy_qt;
164 break;
165 case ATH_PHY_ID:
166 phy_type = ixgbe_phy_nl;
167 break;
168 default:
169 phy_type = ixgbe_phy_unknown;
170 break;
171 }
172
173 return phy_type;
174 }
175
176 /**
177 * ixgbe_reset_phy_generic - Performs a PHY reset
178 * @hw: pointer to hardware structure
179 **/
180 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
181 {
182 u32 i;
183 u16 ctrl = 0;
184 s32 status = 0;
185
186 if (hw->phy.type == ixgbe_phy_unknown)
187 status = ixgbe_identify_phy_generic(hw);
188
189 if (status != 0 || hw->phy.type == ixgbe_phy_none)
190 return status;
191
192 /* Don't reset PHY if it's shut down due to overtemp. */
193 if (!hw->phy.reset_if_overtemp &&
194 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
195 return 0;
196
197 /* Blocked by MNG FW so bail */
198 if (ixgbe_check_reset_blocked(hw))
199 return 0;
200
201 /*
202 * Perform soft PHY reset to the PHY_XS.
203 * This will cause a soft reset to the PHY
204 */
205 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
206 MDIO_MMD_PHYXS,
207 MDIO_CTRL1_RESET);
208
209 /*
210 * Poll for reset bit to self-clear indicating reset is complete.
211 * Some PHYs could take up to 3 seconds to complete and need about
212 * 1.7 usec delay after the reset is complete.
213 */
214 for (i = 0; i < 30; i++) {
215 msleep(100);
216 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
217 MDIO_MMD_PHYXS, &ctrl);
218 if (!(ctrl & MDIO_CTRL1_RESET)) {
219 udelay(2);
220 break;
221 }
222 }
223
224 if (ctrl & MDIO_CTRL1_RESET) {
225 hw_dbg(hw, "PHY reset polling failed to complete.\n");
226 return IXGBE_ERR_RESET_FAILED;
227 }
228
229 return 0;
230 }
231
232 /**
233 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
234 * the SWFW lock
235 * @hw: pointer to hardware structure
236 * @reg_addr: 32 bit address of PHY register to read
237 * @phy_data: Pointer to read data from PHY register
238 **/
239 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
240 u16 *phy_data)
241 {
242 u32 i, data, command;
243
244 /* Setup and write the address cycle command */
245 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
246 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
247 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
248 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
249
250 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
251
252 /* Check every 10 usec to see if the address cycle completed.
253 * The MDI Command bit will clear when the operation is
254 * complete
255 */
256 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
257 udelay(10);
258
259 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
260 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
261 break;
262 }
263
264
265 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
266 hw_dbg(hw, "PHY address command did not complete.\n");
267 return IXGBE_ERR_PHY;
268 }
269
270 /* Address cycle complete, setup and write the read
271 * command
272 */
273 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
274 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
275 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
276 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
277
278 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
279
280 /* Check every 10 usec to see if the address cycle
281 * completed. The MDI Command bit will clear when the
282 * operation is complete
283 */
284 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
285 udelay(10);
286
287 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
288 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
289 break;
290 }
291
292 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
293 hw_dbg(hw, "PHY read command didn't complete\n");
294 return IXGBE_ERR_PHY;
295 }
296
297 /* Read operation is complete. Get the data
298 * from MSRWD
299 */
300 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
301 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
302 *phy_data = (u16)(data);
303
304 return 0;
305 }
306
307 /**
308 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
309 * using the SWFW lock - this function is needed in most cases
310 * @hw: pointer to hardware structure
311 * @reg_addr: 32 bit address of PHY register to read
312 * @phy_data: Pointer to read data from PHY register
313 **/
314 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
315 u32 device_type, u16 *phy_data)
316 {
317 s32 status;
318 u16 gssr;
319
320 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
321 gssr = IXGBE_GSSR_PHY1_SM;
322 else
323 gssr = IXGBE_GSSR_PHY0_SM;
324
325 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
326 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
327 phy_data);
328 hw->mac.ops.release_swfw_sync(hw, gssr);
329 } else {
330 return IXGBE_ERR_SWFW_SYNC;
331 }
332
333 return status;
334 }
335
336 /**
337 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
338 * without SWFW lock
339 * @hw: pointer to hardware structure
340 * @reg_addr: 32 bit PHY register to write
341 * @device_type: 5 bit device type
342 * @phy_data: Data to write to the PHY register
343 **/
344 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
345 u32 device_type, u16 phy_data)
346 {
347 u32 i, command;
348
349 /* Put the data in the MDI single read and write data register*/
350 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
351
352 /* Setup and write the address cycle command */
353 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
354 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
355 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
356 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
357
358 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
359
360 /*
361 * Check every 10 usec to see if the address cycle completed.
362 * The MDI Command bit will clear when the operation is
363 * complete
364 */
365 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
366 udelay(10);
367
368 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
369 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
370 break;
371 }
372
373 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
374 hw_dbg(hw, "PHY address cmd didn't complete\n");
375 return IXGBE_ERR_PHY;
376 }
377
378 /*
379 * Address cycle complete, setup and write the write
380 * command
381 */
382 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
383 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
384 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
385 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
386
387 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
388
389 /* Check every 10 usec to see if the address cycle
390 * completed. The MDI Command bit will clear when the
391 * operation is complete
392 */
393 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
394 udelay(10);
395
396 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
397 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
398 break;
399 }
400
401 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
402 hw_dbg(hw, "PHY write cmd didn't complete\n");
403 return IXGBE_ERR_PHY;
404 }
405
406 return 0;
407 }
408
409 /**
410 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
411 * using SWFW lock- this function is needed in most cases
412 * @hw: pointer to hardware structure
413 * @reg_addr: 32 bit PHY register to write
414 * @device_type: 5 bit device type
415 * @phy_data: Data to write to the PHY register
416 **/
417 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
418 u32 device_type, u16 phy_data)
419 {
420 s32 status;
421 u16 gssr;
422
423 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
424 gssr = IXGBE_GSSR_PHY1_SM;
425 else
426 gssr = IXGBE_GSSR_PHY0_SM;
427
428 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
429 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
430 phy_data);
431 hw->mac.ops.release_swfw_sync(hw, gssr);
432 } else {
433 return IXGBE_ERR_SWFW_SYNC;
434 }
435
436 return status;
437 }
438
439 /**
440 * ixgbe_setup_phy_link_generic - Set and restart autoneg
441 * @hw: pointer to hardware structure
442 *
443 * Restart autonegotiation and PHY and waits for completion.
444 **/
445 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
446 {
447 s32 status = 0;
448 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
449 bool autoneg = false;
450 ixgbe_link_speed speed;
451
452 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
453
454 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
455 /* Set or unset auto-negotiation 10G advertisement */
456 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
457 MDIO_MMD_AN,
458 &autoneg_reg);
459
460 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
461 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
462 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
463
464 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
465 MDIO_MMD_AN,
466 autoneg_reg);
467 }
468
469 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
470 /* Set or unset auto-negotiation 1G advertisement */
471 hw->phy.ops.read_reg(hw,
472 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
473 MDIO_MMD_AN,
474 &autoneg_reg);
475
476 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
477 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
478 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
479
480 hw->phy.ops.write_reg(hw,
481 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
482 MDIO_MMD_AN,
483 autoneg_reg);
484 }
485
486 if (speed & IXGBE_LINK_SPEED_100_FULL) {
487 /* Set or unset auto-negotiation 100M advertisement */
488 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
489 MDIO_MMD_AN,
490 &autoneg_reg);
491
492 autoneg_reg &= ~(ADVERTISE_100FULL |
493 ADVERTISE_100HALF);
494 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
495 autoneg_reg |= ADVERTISE_100FULL;
496
497 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
498 MDIO_MMD_AN,
499 autoneg_reg);
500 }
501
502 /* Blocked by MNG FW so don't reset PHY */
503 if (ixgbe_check_reset_blocked(hw))
504 return 0;
505
506 /* Restart PHY autonegotiation and wait for completion */
507 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
508 MDIO_MMD_AN, &autoneg_reg);
509
510 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
511
512 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
513 MDIO_MMD_AN, autoneg_reg);
514
515 return status;
516 }
517
518 /**
519 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
520 * @hw: pointer to hardware structure
521 * @speed: new link speed
522 **/
523 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
524 ixgbe_link_speed speed,
525 bool autoneg_wait_to_complete)
526 {
527
528 /*
529 * Clear autoneg_advertised and set new values based on input link
530 * speed.
531 */
532 hw->phy.autoneg_advertised = 0;
533
534 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
535 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
536
537 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
538 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
539
540 if (speed & IXGBE_LINK_SPEED_100_FULL)
541 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
542
543 /* Setup link based on the new speed settings */
544 hw->phy.ops.setup_link(hw);
545
546 return 0;
547 }
548
549 /**
550 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
551 * @hw: pointer to hardware structure
552 * @speed: pointer to link speed
553 * @autoneg: boolean auto-negotiation value
554 *
555 * Determines the link capabilities by reading the AUTOC register.
556 */
557 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
558 ixgbe_link_speed *speed,
559 bool *autoneg)
560 {
561 s32 status;
562 u16 speed_ability;
563
564 *speed = 0;
565 *autoneg = true;
566
567 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
568 &speed_ability);
569
570 if (status == 0) {
571 if (speed_ability & MDIO_SPEED_10G)
572 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
573 if (speed_ability & MDIO_PMA_SPEED_1000)
574 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
575 if (speed_ability & MDIO_PMA_SPEED_100)
576 *speed |= IXGBE_LINK_SPEED_100_FULL;
577 }
578
579 return status;
580 }
581
582 /**
583 * ixgbe_check_phy_link_tnx - Determine link and speed status
584 * @hw: pointer to hardware structure
585 *
586 * Reads the VS1 register to determine if link is up and the current speed for
587 * the PHY.
588 **/
589 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
590 bool *link_up)
591 {
592 s32 status;
593 u32 time_out;
594 u32 max_time_out = 10;
595 u16 phy_link = 0;
596 u16 phy_speed = 0;
597 u16 phy_data = 0;
598
599 /* Initialize speed and link to default case */
600 *link_up = false;
601 *speed = IXGBE_LINK_SPEED_10GB_FULL;
602
603 /*
604 * Check current speed and link status of the PHY register.
605 * This is a vendor specific register and may have to
606 * be changed for other copper PHYs.
607 */
608 for (time_out = 0; time_out < max_time_out; time_out++) {
609 udelay(10);
610 status = hw->phy.ops.read_reg(hw,
611 MDIO_STAT1,
612 MDIO_MMD_VEND1,
613 &phy_data);
614 phy_link = phy_data &
615 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
616 phy_speed = phy_data &
617 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
618 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
619 *link_up = true;
620 if (phy_speed ==
621 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
622 *speed = IXGBE_LINK_SPEED_1GB_FULL;
623 break;
624 }
625 }
626
627 return status;
628 }
629
630 /**
631 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
632 * @hw: pointer to hardware structure
633 *
634 * Restart autonegotiation and PHY and waits for completion.
635 **/
636 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
637 {
638 s32 status;
639 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
640 bool autoneg = false;
641 ixgbe_link_speed speed;
642
643 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
644
645 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
646 /* Set or unset auto-negotiation 10G advertisement */
647 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
648 MDIO_MMD_AN,
649 &autoneg_reg);
650
651 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
652 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
653 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
654
655 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
656 MDIO_MMD_AN,
657 autoneg_reg);
658 }
659
660 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
661 /* Set or unset auto-negotiation 1G advertisement */
662 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
663 MDIO_MMD_AN,
664 &autoneg_reg);
665
666 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
667 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
668 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
669
670 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
671 MDIO_MMD_AN,
672 autoneg_reg);
673 }
674
675 if (speed & IXGBE_LINK_SPEED_100_FULL) {
676 /* Set or unset auto-negotiation 100M advertisement */
677 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
678 MDIO_MMD_AN,
679 &autoneg_reg);
680
681 autoneg_reg &= ~(ADVERTISE_100FULL |
682 ADVERTISE_100HALF);
683 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
684 autoneg_reg |= ADVERTISE_100FULL;
685
686 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
687 MDIO_MMD_AN,
688 autoneg_reg);
689 }
690
691 /* Blocked by MNG FW so don't reset PHY */
692 if (ixgbe_check_reset_blocked(hw))
693 return 0;
694
695 /* Restart PHY autonegotiation and wait for completion */
696 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
697 MDIO_MMD_AN, &autoneg_reg);
698
699 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
700
701 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
702 MDIO_MMD_AN, autoneg_reg);
703
704 return status;
705 }
706
707 /**
708 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
709 * @hw: pointer to hardware structure
710 * @firmware_version: pointer to the PHY Firmware Version
711 **/
712 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
713 u16 *firmware_version)
714 {
715 s32 status;
716
717 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
718 MDIO_MMD_VEND1,
719 firmware_version);
720
721 return status;
722 }
723
724 /**
725 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
726 * @hw: pointer to hardware structure
727 * @firmware_version: pointer to the PHY Firmware Version
728 **/
729 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
730 u16 *firmware_version)
731 {
732 s32 status;
733
734 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
735 MDIO_MMD_VEND1,
736 firmware_version);
737
738 return status;
739 }
740
741 /**
742 * ixgbe_reset_phy_nl - Performs a PHY reset
743 * @hw: pointer to hardware structure
744 **/
745 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
746 {
747 u16 phy_offset, control, eword, edata, block_crc;
748 bool end_data = false;
749 u16 list_offset, data_offset;
750 u16 phy_data = 0;
751 s32 ret_val;
752 u32 i;
753
754 /* Blocked by MNG FW so bail */
755 if (ixgbe_check_reset_blocked(hw))
756 return 0;
757
758 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
759
760 /* reset the PHY and poll for completion */
761 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
762 (phy_data | MDIO_CTRL1_RESET));
763
764 for (i = 0; i < 100; i++) {
765 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
766 &phy_data);
767 if ((phy_data & MDIO_CTRL1_RESET) == 0)
768 break;
769 usleep_range(10000, 20000);
770 }
771
772 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
773 hw_dbg(hw, "PHY reset did not complete.\n");
774 return IXGBE_ERR_PHY;
775 }
776
777 /* Get init offsets */
778 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
779 &data_offset);
780 if (ret_val)
781 return ret_val;
782
783 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
784 data_offset++;
785 while (!end_data) {
786 /*
787 * Read control word from PHY init contents offset
788 */
789 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
790 if (ret_val)
791 goto err_eeprom;
792 control = (eword & IXGBE_CONTROL_MASK_NL) >>
793 IXGBE_CONTROL_SHIFT_NL;
794 edata = eword & IXGBE_DATA_MASK_NL;
795 switch (control) {
796 case IXGBE_DELAY_NL:
797 data_offset++;
798 hw_dbg(hw, "DELAY: %d MS\n", edata);
799 usleep_range(edata * 1000, edata * 2000);
800 break;
801 case IXGBE_DATA_NL:
802 hw_dbg(hw, "DATA:\n");
803 data_offset++;
804 ret_val = hw->eeprom.ops.read(hw, data_offset++,
805 &phy_offset);
806 if (ret_val)
807 goto err_eeprom;
808 for (i = 0; i < edata; i++) {
809 ret_val = hw->eeprom.ops.read(hw, data_offset,
810 &eword);
811 if (ret_val)
812 goto err_eeprom;
813 hw->phy.ops.write_reg(hw, phy_offset,
814 MDIO_MMD_PMAPMD, eword);
815 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
816 phy_offset);
817 data_offset++;
818 phy_offset++;
819 }
820 break;
821 case IXGBE_CONTROL_NL:
822 data_offset++;
823 hw_dbg(hw, "CONTROL:\n");
824 if (edata == IXGBE_CONTROL_EOL_NL) {
825 hw_dbg(hw, "EOL\n");
826 end_data = true;
827 } else if (edata == IXGBE_CONTROL_SOL_NL) {
828 hw_dbg(hw, "SOL\n");
829 } else {
830 hw_dbg(hw, "Bad control value\n");
831 return IXGBE_ERR_PHY;
832 }
833 break;
834 default:
835 hw_dbg(hw, "Bad control type\n");
836 return IXGBE_ERR_PHY;
837 }
838 }
839
840 return ret_val;
841
842 err_eeprom:
843 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
844 return IXGBE_ERR_PHY;
845 }
846
847 /**
848 * ixgbe_identify_module_generic - Identifies module type
849 * @hw: pointer to hardware structure
850 *
851 * Determines HW type and calls appropriate function.
852 **/
853 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
854 {
855 switch (hw->mac.ops.get_media_type(hw)) {
856 case ixgbe_media_type_fiber:
857 return ixgbe_identify_sfp_module_generic(hw);
858 case ixgbe_media_type_fiber_qsfp:
859 return ixgbe_identify_qsfp_module_generic(hw);
860 default:
861 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
862 return IXGBE_ERR_SFP_NOT_PRESENT;
863 }
864
865 return IXGBE_ERR_SFP_NOT_PRESENT;
866 }
867
868 /**
869 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
870 * @hw: pointer to hardware structure
871 *
872 * Searches for and identifies the SFP module and assigns appropriate PHY type.
873 **/
874 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
875 {
876 struct ixgbe_adapter *adapter = hw->back;
877 s32 status;
878 u32 vendor_oui = 0;
879 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
880 u8 identifier = 0;
881 u8 comp_codes_1g = 0;
882 u8 comp_codes_10g = 0;
883 u8 oui_bytes[3] = {0, 0, 0};
884 u8 cable_tech = 0;
885 u8 cable_spec = 0;
886 u16 enforce_sfp = 0;
887
888 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
889 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
890 return IXGBE_ERR_SFP_NOT_PRESENT;
891 }
892
893 status = hw->phy.ops.read_i2c_eeprom(hw,
894 IXGBE_SFF_IDENTIFIER,
895 &identifier);
896
897 if (status)
898 goto err_read_i2c_eeprom;
899
900 /* LAN ID is needed for sfp_type determination */
901 hw->mac.ops.set_lan_id(hw);
902
903 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
904 hw->phy.type = ixgbe_phy_sfp_unsupported;
905 return IXGBE_ERR_SFP_NOT_SUPPORTED;
906 }
907 status = hw->phy.ops.read_i2c_eeprom(hw,
908 IXGBE_SFF_1GBE_COMP_CODES,
909 &comp_codes_1g);
910
911 if (status)
912 goto err_read_i2c_eeprom;
913
914 status = hw->phy.ops.read_i2c_eeprom(hw,
915 IXGBE_SFF_10GBE_COMP_CODES,
916 &comp_codes_10g);
917
918 if (status)
919 goto err_read_i2c_eeprom;
920 status = hw->phy.ops.read_i2c_eeprom(hw,
921 IXGBE_SFF_CABLE_TECHNOLOGY,
922 &cable_tech);
923
924 if (status)
925 goto err_read_i2c_eeprom;
926
927 /* ID Module
928 * =========
929 * 0 SFP_DA_CU
930 * 1 SFP_SR
931 * 2 SFP_LR
932 * 3 SFP_DA_CORE0 - 82599-specific
933 * 4 SFP_DA_CORE1 - 82599-specific
934 * 5 SFP_SR/LR_CORE0 - 82599-specific
935 * 6 SFP_SR/LR_CORE1 - 82599-specific
936 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
937 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
938 * 9 SFP_1g_cu_CORE0 - 82599-specific
939 * 10 SFP_1g_cu_CORE1 - 82599-specific
940 * 11 SFP_1g_sx_CORE0 - 82599-specific
941 * 12 SFP_1g_sx_CORE1 - 82599-specific
942 */
943 if (hw->mac.type == ixgbe_mac_82598EB) {
944 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
945 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
946 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
947 hw->phy.sfp_type = ixgbe_sfp_type_sr;
948 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
949 hw->phy.sfp_type = ixgbe_sfp_type_lr;
950 else
951 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
952 } else if (hw->mac.type == ixgbe_mac_82599EB) {
953 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
954 if (hw->bus.lan_id == 0)
955 hw->phy.sfp_type =
956 ixgbe_sfp_type_da_cu_core0;
957 else
958 hw->phy.sfp_type =
959 ixgbe_sfp_type_da_cu_core1;
960 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
961 hw->phy.ops.read_i2c_eeprom(
962 hw, IXGBE_SFF_CABLE_SPEC_COMP,
963 &cable_spec);
964 if (cable_spec &
965 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
966 if (hw->bus.lan_id == 0)
967 hw->phy.sfp_type =
968 ixgbe_sfp_type_da_act_lmt_core0;
969 else
970 hw->phy.sfp_type =
971 ixgbe_sfp_type_da_act_lmt_core1;
972 } else {
973 hw->phy.sfp_type =
974 ixgbe_sfp_type_unknown;
975 }
976 } else if (comp_codes_10g &
977 (IXGBE_SFF_10GBASESR_CAPABLE |
978 IXGBE_SFF_10GBASELR_CAPABLE)) {
979 if (hw->bus.lan_id == 0)
980 hw->phy.sfp_type =
981 ixgbe_sfp_type_srlr_core0;
982 else
983 hw->phy.sfp_type =
984 ixgbe_sfp_type_srlr_core1;
985 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
986 if (hw->bus.lan_id == 0)
987 hw->phy.sfp_type =
988 ixgbe_sfp_type_1g_cu_core0;
989 else
990 hw->phy.sfp_type =
991 ixgbe_sfp_type_1g_cu_core1;
992 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
993 if (hw->bus.lan_id == 0)
994 hw->phy.sfp_type =
995 ixgbe_sfp_type_1g_sx_core0;
996 else
997 hw->phy.sfp_type =
998 ixgbe_sfp_type_1g_sx_core1;
999 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1000 if (hw->bus.lan_id == 0)
1001 hw->phy.sfp_type =
1002 ixgbe_sfp_type_1g_lx_core0;
1003 else
1004 hw->phy.sfp_type =
1005 ixgbe_sfp_type_1g_lx_core1;
1006 } else {
1007 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1008 }
1009 }
1010
1011 if (hw->phy.sfp_type != stored_sfp_type)
1012 hw->phy.sfp_setup_needed = true;
1013
1014 /* Determine if the SFP+ PHY is dual speed or not. */
1015 hw->phy.multispeed_fiber = false;
1016 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1017 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1018 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1019 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1020 hw->phy.multispeed_fiber = true;
1021
1022 /* Determine PHY vendor */
1023 if (hw->phy.type != ixgbe_phy_nl) {
1024 hw->phy.id = identifier;
1025 status = hw->phy.ops.read_i2c_eeprom(hw,
1026 IXGBE_SFF_VENDOR_OUI_BYTE0,
1027 &oui_bytes[0]);
1028
1029 if (status != 0)
1030 goto err_read_i2c_eeprom;
1031
1032 status = hw->phy.ops.read_i2c_eeprom(hw,
1033 IXGBE_SFF_VENDOR_OUI_BYTE1,
1034 &oui_bytes[1]);
1035
1036 if (status != 0)
1037 goto err_read_i2c_eeprom;
1038
1039 status = hw->phy.ops.read_i2c_eeprom(hw,
1040 IXGBE_SFF_VENDOR_OUI_BYTE2,
1041 &oui_bytes[2]);
1042
1043 if (status != 0)
1044 goto err_read_i2c_eeprom;
1045
1046 vendor_oui =
1047 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1048 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1049 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1050
1051 switch (vendor_oui) {
1052 case IXGBE_SFF_VENDOR_OUI_TYCO:
1053 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1054 hw->phy.type =
1055 ixgbe_phy_sfp_passive_tyco;
1056 break;
1057 case IXGBE_SFF_VENDOR_OUI_FTL:
1058 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1059 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1060 else
1061 hw->phy.type = ixgbe_phy_sfp_ftl;
1062 break;
1063 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1064 hw->phy.type = ixgbe_phy_sfp_avago;
1065 break;
1066 case IXGBE_SFF_VENDOR_OUI_INTEL:
1067 hw->phy.type = ixgbe_phy_sfp_intel;
1068 break;
1069 default:
1070 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1071 hw->phy.type =
1072 ixgbe_phy_sfp_passive_unknown;
1073 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1074 hw->phy.type =
1075 ixgbe_phy_sfp_active_unknown;
1076 else
1077 hw->phy.type = ixgbe_phy_sfp_unknown;
1078 break;
1079 }
1080 }
1081
1082 /* Allow any DA cable vendor */
1083 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1084 IXGBE_SFF_DA_ACTIVE_CABLE))
1085 return 0;
1086
1087 /* Verify supported 1G SFP modules */
1088 if (comp_codes_10g == 0 &&
1089 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1090 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1091 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1092 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1093 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1094 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1095 hw->phy.type = ixgbe_phy_sfp_unsupported;
1096 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1097 }
1098
1099 /* Anything else 82598-based is supported */
1100 if (hw->mac.type == ixgbe_mac_82598EB)
1101 return 0;
1102
1103 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1104 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1105 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1106 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1107 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1108 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1109 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1110 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1111 /* Make sure we're a supported PHY type */
1112 if (hw->phy.type == ixgbe_phy_sfp_intel)
1113 return 0;
1114 if (hw->allow_unsupported_sfp) {
1115 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1116 return 0;
1117 }
1118 hw_dbg(hw, "SFP+ module not supported\n");
1119 hw->phy.type = ixgbe_phy_sfp_unsupported;
1120 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1121 }
1122 return 0;
1123
1124 err_read_i2c_eeprom:
1125 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1126 if (hw->phy.type != ixgbe_phy_nl) {
1127 hw->phy.id = 0;
1128 hw->phy.type = ixgbe_phy_unknown;
1129 }
1130 return IXGBE_ERR_SFP_NOT_PRESENT;
1131 }
1132
1133 /**
1134 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1135 * @hw: pointer to hardware structure
1136 *
1137 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1138 **/
1139 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1140 {
1141 struct ixgbe_adapter *adapter = hw->back;
1142 s32 status;
1143 u32 vendor_oui = 0;
1144 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1145 u8 identifier = 0;
1146 u8 comp_codes_1g = 0;
1147 u8 comp_codes_10g = 0;
1148 u8 oui_bytes[3] = {0, 0, 0};
1149 u16 enforce_sfp = 0;
1150 u8 connector = 0;
1151 u8 cable_length = 0;
1152 u8 device_tech = 0;
1153 bool active_cable = false;
1154
1155 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1156 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1157 return IXGBE_ERR_SFP_NOT_PRESENT;
1158 }
1159
1160 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1161 &identifier);
1162
1163 if (status != 0)
1164 goto err_read_i2c_eeprom;
1165
1166 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1167 hw->phy.type = ixgbe_phy_sfp_unsupported;
1168 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1169 }
1170
1171 hw->phy.id = identifier;
1172
1173 /* LAN ID is needed for sfp_type determination */
1174 hw->mac.ops.set_lan_id(hw);
1175
1176 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1177 &comp_codes_10g);
1178
1179 if (status != 0)
1180 goto err_read_i2c_eeprom;
1181
1182 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1183 &comp_codes_1g);
1184
1185 if (status != 0)
1186 goto err_read_i2c_eeprom;
1187
1188 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1189 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1190 if (hw->bus.lan_id == 0)
1191 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1192 else
1193 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1194 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1195 IXGBE_SFF_10GBASELR_CAPABLE)) {
1196 if (hw->bus.lan_id == 0)
1197 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1198 else
1199 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1200 } else {
1201 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1202 active_cable = true;
1203
1204 if (!active_cable) {
1205 /* check for active DA cables that pre-date
1206 * SFF-8436 v3.6
1207 */
1208 hw->phy.ops.read_i2c_eeprom(hw,
1209 IXGBE_SFF_QSFP_CONNECTOR,
1210 &connector);
1211
1212 hw->phy.ops.read_i2c_eeprom(hw,
1213 IXGBE_SFF_QSFP_CABLE_LENGTH,
1214 &cable_length);
1215
1216 hw->phy.ops.read_i2c_eeprom(hw,
1217 IXGBE_SFF_QSFP_DEVICE_TECH,
1218 &device_tech);
1219
1220 if ((connector ==
1221 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1222 (cable_length > 0) &&
1223 ((device_tech >> 4) ==
1224 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1225 active_cable = true;
1226 }
1227
1228 if (active_cable) {
1229 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1230 if (hw->bus.lan_id == 0)
1231 hw->phy.sfp_type =
1232 ixgbe_sfp_type_da_act_lmt_core0;
1233 else
1234 hw->phy.sfp_type =
1235 ixgbe_sfp_type_da_act_lmt_core1;
1236 } else {
1237 /* unsupported module type */
1238 hw->phy.type = ixgbe_phy_sfp_unsupported;
1239 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1240 }
1241 }
1242
1243 if (hw->phy.sfp_type != stored_sfp_type)
1244 hw->phy.sfp_setup_needed = true;
1245
1246 /* Determine if the QSFP+ PHY is dual speed or not. */
1247 hw->phy.multispeed_fiber = false;
1248 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1249 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1250 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1251 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1252 hw->phy.multispeed_fiber = true;
1253
1254 /* Determine PHY vendor for optical modules */
1255 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1256 IXGBE_SFF_10GBASELR_CAPABLE)) {
1257 status = hw->phy.ops.read_i2c_eeprom(hw,
1258 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1259 &oui_bytes[0]);
1260
1261 if (status != 0)
1262 goto err_read_i2c_eeprom;
1263
1264 status = hw->phy.ops.read_i2c_eeprom(hw,
1265 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1266 &oui_bytes[1]);
1267
1268 if (status != 0)
1269 goto err_read_i2c_eeprom;
1270
1271 status = hw->phy.ops.read_i2c_eeprom(hw,
1272 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1273 &oui_bytes[2]);
1274
1275 if (status != 0)
1276 goto err_read_i2c_eeprom;
1277
1278 vendor_oui =
1279 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1280 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1281 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1282
1283 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1284 hw->phy.type = ixgbe_phy_qsfp_intel;
1285 else
1286 hw->phy.type = ixgbe_phy_qsfp_unknown;
1287
1288 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1289 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1290 /* Make sure we're a supported PHY type */
1291 if (hw->phy.type == ixgbe_phy_qsfp_intel)
1292 return 0;
1293 if (hw->allow_unsupported_sfp) {
1294 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1295 return 0;
1296 }
1297 hw_dbg(hw, "QSFP module not supported\n");
1298 hw->phy.type = ixgbe_phy_sfp_unsupported;
1299 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1300 }
1301 return 0;
1302 }
1303 return 0;
1304
1305 err_read_i2c_eeprom:
1306 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1307 hw->phy.id = 0;
1308 hw->phy.type = ixgbe_phy_unknown;
1309
1310 return IXGBE_ERR_SFP_NOT_PRESENT;
1311 }
1312
1313 /**
1314 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1315 * @hw: pointer to hardware structure
1316 * @list_offset: offset to the SFP ID list
1317 * @data_offset: offset to the SFP data block
1318 *
1319 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1320 * so it returns the offsets to the phy init sequence block.
1321 **/
1322 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1323 u16 *list_offset,
1324 u16 *data_offset)
1325 {
1326 u16 sfp_id;
1327 u16 sfp_type = hw->phy.sfp_type;
1328
1329 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1330 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1331
1332 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1333 return IXGBE_ERR_SFP_NOT_PRESENT;
1334
1335 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1336 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1337 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1338
1339 /*
1340 * Limiting active cables and 1G Phys must be initialized as
1341 * SR modules
1342 */
1343 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1344 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1345 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1346 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1347 sfp_type = ixgbe_sfp_type_srlr_core0;
1348 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1349 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1350 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1351 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1352 sfp_type = ixgbe_sfp_type_srlr_core1;
1353
1354 /* Read offset to PHY init contents */
1355 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1356 hw_err(hw, "eeprom read at %d failed\n",
1357 IXGBE_PHY_INIT_OFFSET_NL);
1358 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1359 }
1360
1361 if ((!*list_offset) || (*list_offset == 0xFFFF))
1362 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1363
1364 /* Shift offset to first ID word */
1365 (*list_offset)++;
1366
1367 /*
1368 * Find the matching SFP ID in the EEPROM
1369 * and program the init sequence
1370 */
1371 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1372 goto err_phy;
1373
1374 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1375 if (sfp_id == sfp_type) {
1376 (*list_offset)++;
1377 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1378 goto err_phy;
1379 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1380 hw_dbg(hw, "SFP+ module not supported\n");
1381 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1382 } else {
1383 break;
1384 }
1385 } else {
1386 (*list_offset) += 2;
1387 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1388 goto err_phy;
1389 }
1390 }
1391
1392 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1393 hw_dbg(hw, "No matching SFP+ module found\n");
1394 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1395 }
1396
1397 return 0;
1398
1399 err_phy:
1400 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
1401 return IXGBE_ERR_PHY;
1402 }
1403
1404 /**
1405 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1406 * @hw: pointer to hardware structure
1407 * @byte_offset: EEPROM byte offset to read
1408 * @eeprom_data: value read
1409 *
1410 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1411 **/
1412 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1413 u8 *eeprom_data)
1414 {
1415 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1416 IXGBE_I2C_EEPROM_DEV_ADDR,
1417 eeprom_data);
1418 }
1419
1420 /**
1421 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1422 * @hw: pointer to hardware structure
1423 * @byte_offset: byte offset at address 0xA2
1424 * @eeprom_data: value read
1425 *
1426 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1427 **/
1428 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1429 u8 *sff8472_data)
1430 {
1431 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1432 IXGBE_I2C_EEPROM_DEV_ADDR2,
1433 sff8472_data);
1434 }
1435
1436 /**
1437 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1438 * @hw: pointer to hardware structure
1439 * @byte_offset: EEPROM byte offset to write
1440 * @eeprom_data: value to write
1441 *
1442 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1443 **/
1444 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1445 u8 eeprom_data)
1446 {
1447 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1448 IXGBE_I2C_EEPROM_DEV_ADDR,
1449 eeprom_data);
1450 }
1451
1452 /**
1453 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1454 * @hw: pointer to hardware structure
1455 * @byte_offset: byte offset to read
1456 * @data: value read
1457 *
1458 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1459 * a specified device address.
1460 **/
1461 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1462 u8 dev_addr, u8 *data)
1463 {
1464 s32 status;
1465 u32 max_retry = 10;
1466 u32 retry = 0;
1467 u16 swfw_mask = 0;
1468 bool nack = true;
1469 *data = 0;
1470
1471 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1472 swfw_mask = IXGBE_GSSR_PHY1_SM;
1473 else
1474 swfw_mask = IXGBE_GSSR_PHY0_SM;
1475
1476 do {
1477 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1478 return IXGBE_ERR_SWFW_SYNC;
1479
1480 ixgbe_i2c_start(hw);
1481
1482 /* Device Address and write indication */
1483 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1484 if (status != 0)
1485 goto fail;
1486
1487 status = ixgbe_get_i2c_ack(hw);
1488 if (status != 0)
1489 goto fail;
1490
1491 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1492 if (status != 0)
1493 goto fail;
1494
1495 status = ixgbe_get_i2c_ack(hw);
1496 if (status != 0)
1497 goto fail;
1498
1499 ixgbe_i2c_start(hw);
1500
1501 /* Device Address and read indication */
1502 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1503 if (status != 0)
1504 goto fail;
1505
1506 status = ixgbe_get_i2c_ack(hw);
1507 if (status != 0)
1508 goto fail;
1509
1510 status = ixgbe_clock_in_i2c_byte(hw, data);
1511 if (status != 0)
1512 goto fail;
1513
1514 status = ixgbe_clock_out_i2c_bit(hw, nack);
1515 if (status != 0)
1516 goto fail;
1517
1518 ixgbe_i2c_stop(hw);
1519 break;
1520
1521 fail:
1522 ixgbe_i2c_bus_clear(hw);
1523 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1524 msleep(100);
1525 retry++;
1526 if (retry < max_retry)
1527 hw_dbg(hw, "I2C byte read error - Retrying.\n");
1528 else
1529 hw_dbg(hw, "I2C byte read error.\n");
1530
1531 } while (retry < max_retry);
1532
1533 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1534
1535 return status;
1536 }
1537
1538 /**
1539 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1540 * @hw: pointer to hardware structure
1541 * @byte_offset: byte offset to write
1542 * @data: value to write
1543 *
1544 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1545 * a specified device address.
1546 **/
1547 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1548 u8 dev_addr, u8 data)
1549 {
1550 s32 status;
1551 u32 max_retry = 1;
1552 u32 retry = 0;
1553 u16 swfw_mask = 0;
1554
1555 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1556 swfw_mask = IXGBE_GSSR_PHY1_SM;
1557 else
1558 swfw_mask = IXGBE_GSSR_PHY0_SM;
1559
1560 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1561 return IXGBE_ERR_SWFW_SYNC;
1562
1563 do {
1564 ixgbe_i2c_start(hw);
1565
1566 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1567 if (status != 0)
1568 goto fail;
1569
1570 status = ixgbe_get_i2c_ack(hw);
1571 if (status != 0)
1572 goto fail;
1573
1574 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1575 if (status != 0)
1576 goto fail;
1577
1578 status = ixgbe_get_i2c_ack(hw);
1579 if (status != 0)
1580 goto fail;
1581
1582 status = ixgbe_clock_out_i2c_byte(hw, data);
1583 if (status != 0)
1584 goto fail;
1585
1586 status = ixgbe_get_i2c_ack(hw);
1587 if (status != 0)
1588 goto fail;
1589
1590 ixgbe_i2c_stop(hw);
1591 break;
1592
1593 fail:
1594 ixgbe_i2c_bus_clear(hw);
1595 retry++;
1596 if (retry < max_retry)
1597 hw_dbg(hw, "I2C byte write error - Retrying.\n");
1598 else
1599 hw_dbg(hw, "I2C byte write error.\n");
1600 } while (retry < max_retry);
1601
1602 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1603
1604 return status;
1605 }
1606
1607 /**
1608 * ixgbe_i2c_start - Sets I2C start condition
1609 * @hw: pointer to hardware structure
1610 *
1611 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1612 **/
1613 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1614 {
1615 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1616
1617 /* Start condition must begin with data and clock high */
1618 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1619 ixgbe_raise_i2c_clk(hw, &i2cctl);
1620
1621 /* Setup time for start condition (4.7us) */
1622 udelay(IXGBE_I2C_T_SU_STA);
1623
1624 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1625
1626 /* Hold time for start condition (4us) */
1627 udelay(IXGBE_I2C_T_HD_STA);
1628
1629 ixgbe_lower_i2c_clk(hw, &i2cctl);
1630
1631 /* Minimum low period of clock is 4.7 us */
1632 udelay(IXGBE_I2C_T_LOW);
1633
1634 }
1635
1636 /**
1637 * ixgbe_i2c_stop - Sets I2C stop condition
1638 * @hw: pointer to hardware structure
1639 *
1640 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1641 **/
1642 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1643 {
1644 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1645
1646 /* Stop condition must begin with data low and clock high */
1647 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1648 ixgbe_raise_i2c_clk(hw, &i2cctl);
1649
1650 /* Setup time for stop condition (4us) */
1651 udelay(IXGBE_I2C_T_SU_STO);
1652
1653 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1654
1655 /* bus free time between stop and start (4.7us)*/
1656 udelay(IXGBE_I2C_T_BUF);
1657 }
1658
1659 /**
1660 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1661 * @hw: pointer to hardware structure
1662 * @data: data byte to clock in
1663 *
1664 * Clocks in one byte data via I2C data/clock
1665 **/
1666 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1667 {
1668 s32 i;
1669 bool bit = false;
1670
1671 for (i = 7; i >= 0; i--) {
1672 ixgbe_clock_in_i2c_bit(hw, &bit);
1673 *data |= bit << i;
1674 }
1675
1676 return 0;
1677 }
1678
1679 /**
1680 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1681 * @hw: pointer to hardware structure
1682 * @data: data byte clocked out
1683 *
1684 * Clocks out one byte data via I2C data/clock
1685 **/
1686 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1687 {
1688 s32 status;
1689 s32 i;
1690 u32 i2cctl;
1691 bool bit = false;
1692
1693 for (i = 7; i >= 0; i--) {
1694 bit = (data >> i) & 0x1;
1695 status = ixgbe_clock_out_i2c_bit(hw, bit);
1696
1697 if (status != 0)
1698 break;
1699 }
1700
1701 /* Release SDA line (set high) */
1702 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1703 i2cctl |= IXGBE_I2C_DATA_OUT;
1704 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1705 IXGBE_WRITE_FLUSH(hw);
1706
1707 return status;
1708 }
1709
1710 /**
1711 * ixgbe_get_i2c_ack - Polls for I2C ACK
1712 * @hw: pointer to hardware structure
1713 *
1714 * Clocks in/out one bit via I2C data/clock
1715 **/
1716 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1717 {
1718 s32 status = 0;
1719 u32 i = 0;
1720 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1721 u32 timeout = 10;
1722 bool ack = true;
1723
1724 ixgbe_raise_i2c_clk(hw, &i2cctl);
1725
1726
1727 /* Minimum high period of clock is 4us */
1728 udelay(IXGBE_I2C_T_HIGH);
1729
1730 /* Poll for ACK. Note that ACK in I2C spec is
1731 * transition from 1 to 0 */
1732 for (i = 0; i < timeout; i++) {
1733 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1734 ack = ixgbe_get_i2c_data(&i2cctl);
1735
1736 udelay(1);
1737 if (ack == 0)
1738 break;
1739 }
1740
1741 if (ack == 1) {
1742 hw_dbg(hw, "I2C ack was not received.\n");
1743 status = IXGBE_ERR_I2C;
1744 }
1745
1746 ixgbe_lower_i2c_clk(hw, &i2cctl);
1747
1748 /* Minimum low period of clock is 4.7 us */
1749 udelay(IXGBE_I2C_T_LOW);
1750
1751 return status;
1752 }
1753
1754 /**
1755 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1756 * @hw: pointer to hardware structure
1757 * @data: read data value
1758 *
1759 * Clocks in one bit via I2C data/clock
1760 **/
1761 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1762 {
1763 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1764
1765 ixgbe_raise_i2c_clk(hw, &i2cctl);
1766
1767 /* Minimum high period of clock is 4us */
1768 udelay(IXGBE_I2C_T_HIGH);
1769
1770 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1771 *data = ixgbe_get_i2c_data(&i2cctl);
1772
1773 ixgbe_lower_i2c_clk(hw, &i2cctl);
1774
1775 /* Minimum low period of clock is 4.7 us */
1776 udelay(IXGBE_I2C_T_LOW);
1777
1778 return 0;
1779 }
1780
1781 /**
1782 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1783 * @hw: pointer to hardware structure
1784 * @data: data value to write
1785 *
1786 * Clocks out one bit via I2C data/clock
1787 **/
1788 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1789 {
1790 s32 status;
1791 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1792
1793 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1794 if (status == 0) {
1795 ixgbe_raise_i2c_clk(hw, &i2cctl);
1796
1797 /* Minimum high period of clock is 4us */
1798 udelay(IXGBE_I2C_T_HIGH);
1799
1800 ixgbe_lower_i2c_clk(hw, &i2cctl);
1801
1802 /* Minimum low period of clock is 4.7 us.
1803 * This also takes care of the data hold time.
1804 */
1805 udelay(IXGBE_I2C_T_LOW);
1806 } else {
1807 hw_dbg(hw, "I2C data was not set to %X\n", data);
1808 return IXGBE_ERR_I2C;
1809 }
1810
1811 return 0;
1812 }
1813 /**
1814 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1815 * @hw: pointer to hardware structure
1816 * @i2cctl: Current value of I2CCTL register
1817 *
1818 * Raises the I2C clock line '0'->'1'
1819 **/
1820 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1821 {
1822 u32 i = 0;
1823 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1824 u32 i2cctl_r = 0;
1825
1826 for (i = 0; i < timeout; i++) {
1827 *i2cctl |= IXGBE_I2C_CLK_OUT;
1828 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1829 IXGBE_WRITE_FLUSH(hw);
1830 /* SCL rise time (1000ns) */
1831 udelay(IXGBE_I2C_T_RISE);
1832
1833 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1834 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1835 break;
1836 }
1837 }
1838
1839 /**
1840 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1841 * @hw: pointer to hardware structure
1842 * @i2cctl: Current value of I2CCTL register
1843 *
1844 * Lowers the I2C clock line '1'->'0'
1845 **/
1846 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1847 {
1848
1849 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1850
1851 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1852 IXGBE_WRITE_FLUSH(hw);
1853
1854 /* SCL fall time (300ns) */
1855 udelay(IXGBE_I2C_T_FALL);
1856 }
1857
1858 /**
1859 * ixgbe_set_i2c_data - Sets the I2C data bit
1860 * @hw: pointer to hardware structure
1861 * @i2cctl: Current value of I2CCTL register
1862 * @data: I2C data value (0 or 1) to set
1863 *
1864 * Sets the I2C data bit
1865 **/
1866 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1867 {
1868 if (data)
1869 *i2cctl |= IXGBE_I2C_DATA_OUT;
1870 else
1871 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1872
1873 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1874 IXGBE_WRITE_FLUSH(hw);
1875
1876 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1877 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1878
1879 /* Verify data was set correctly */
1880 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1881 if (data != ixgbe_get_i2c_data(i2cctl)) {
1882 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1883 return IXGBE_ERR_I2C;
1884 }
1885
1886 return 0;
1887 }
1888
1889 /**
1890 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1891 * @hw: pointer to hardware structure
1892 * @i2cctl: Current value of I2CCTL register
1893 *
1894 * Returns the I2C data bit value
1895 **/
1896 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1897 {
1898 if (*i2cctl & IXGBE_I2C_DATA_IN)
1899 return true;
1900 return false;
1901 }
1902
1903 /**
1904 * ixgbe_i2c_bus_clear - Clears the I2C bus
1905 * @hw: pointer to hardware structure
1906 *
1907 * Clears the I2C bus by sending nine clock pulses.
1908 * Used when data line is stuck low.
1909 **/
1910 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1911 {
1912 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1913 u32 i;
1914
1915 ixgbe_i2c_start(hw);
1916
1917 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1918
1919 for (i = 0; i < 9; i++) {
1920 ixgbe_raise_i2c_clk(hw, &i2cctl);
1921
1922 /* Min high period of clock is 4us */
1923 udelay(IXGBE_I2C_T_HIGH);
1924
1925 ixgbe_lower_i2c_clk(hw, &i2cctl);
1926
1927 /* Min low period of clock is 4.7us*/
1928 udelay(IXGBE_I2C_T_LOW);
1929 }
1930
1931 ixgbe_i2c_start(hw);
1932
1933 /* Put the i2c bus back to default state */
1934 ixgbe_i2c_stop(hw);
1935 }
1936
1937 /**
1938 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1939 * @hw: pointer to hardware structure
1940 *
1941 * Checks if the LASI temp alarm status was triggered due to overtemp
1942 **/
1943 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1944 {
1945 u16 phy_data = 0;
1946
1947 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1948 return 0;
1949
1950 /* Check that the LASI temp alarm status was triggered */
1951 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1952 MDIO_MMD_PMAPMD, &phy_data);
1953
1954 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1955 return 0;
1956
1957 return IXGBE_ERR_OVERTEMP;
1958 }
Linux kernel - Deliverables
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