drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27 #include "ixgbe.h"
  28 #include <linux/export.h>
  29 #include <linux/ptp_classify.h>
  30
  31 /*
  32  * The 82599 and the X540 do not have true 64bit nanosecond scale
  33  * counter registers. Instead, SYSTIME is defined by a fixed point
  34  * system which allows the user to define the scale counter increment
  35  * value at every level change of the oscillator driving the SYSTIME
  36  * value. For both devices the TIMINCA:IV field defines this
  37  * increment. On the X540 device, 31 bits are provided. However on the
  38  * 82599 only provides 24 bits. The time unit is determined by the
  39  * clock frequency of the oscillator in combination with the TIMINCA
  40  * register. When these devices link at 10Gb the oscillator has a
  41  * period of 6.4ns. In order to convert the scale counter into
  42  * nanoseconds the cyclecounter and timecounter structures are
  43  * used. The SYSTIME registers need to be converted to ns values by use
  44  * of only a right shift (division by power of 2). The following math
  45  * determines the largest incvalue that will fit into the available
  46  * bits in the TIMINCA register.
  47  *
  48  * PeriodWidth: Number of bits to store the clock period
  49  * MaxWidth: The maximum width value of the TIMINCA register
  50  * Period: The clock period for the oscillator
  51  * round(): discard the fractional portion of the calculation
  52  *
  53  * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
  54  *
  55  * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns
  56  * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns
  57  *
  58  * The period also changes based on the link speed:
  59  * At 10Gb link or no link, the period remains the same.
  60  * At 1Gb link, the period is multiplied by 10. (64ns)
  61  * At 100Mb link, the period is multiplied by 100. (640ns)
  62  *
  63  * The calculated value allows us to right shift the SYSTIME register
  64  * value in order to quickly convert it into a nanosecond clock,
  65  * while allowing for the maximum possible adjustment value.
  66  *
  67  * These diagrams are only for the 10Gb link period
  68  *
  69  *           SYSTIMEH            SYSTIMEL
  70  *       +--------------+  +--------------+
  71  * X540  |      32      |  | 1 | 3 |  28  |
  72  *       *--------------+  +--------------+
  73  *        \________ 36 bits ______/  fract
  74  *
  75  *       +--------------+  +--------------+
  76  * 82599 |      32      |  | 8 | 3 |  21  |
  77  *       *--------------+  +--------------+
  78  *        \________ 43 bits ______/  fract
  79  *
  80  * The 36 bit X540 SYSTIME overflows every
  81  *   2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
  82  *
  83  * The 43 bit 82599 SYSTIME overflows every
  84  *   2^43 * 10^-9 / 3600 = 2.4 hours
  85  */
  86 #define IXGBE_INCVAL_10GB 0x66666666
  87 #define IXGBE_INCVAL_1GB  0x40000000
  88 #define IXGBE_INCVAL_100  0x50000000
  89
  90 #define IXGBE_INCVAL_SHIFT_10GB  28
  91 #define IXGBE_INCVAL_SHIFT_1GB   24
  92 #define IXGBE_INCVAL_SHIFT_100   21
  93
  94 #define IXGBE_INCVAL_SHIFT_82599 7
  95 #define IXGBE_INCPER_SHIFT_82599 24
  96 #define IXGBE_MAX_TIMEADJ_VALUE  0x7FFFFFFFFFFFFFFFULL
  97
  98 #define IXGBE_OVERFLOW_PERIOD    (HZ * 30)
  99
 100 #ifndef NSECS_PER_SEC
 101 #define NSECS_PER_SEC 1000000000ULL
 102 #endif
 103
 104 static struct sock_filter ptp_filter[] = {
 105         PTP_FILTER
 106 };
 107
 108 /**
 109  * ixgbe_ptp_setup_sdp
 110  * @hw: the hardware private structure
 111  *
 112  * this function enables or disables the clock out feature on SDP0 for
 113  * the X540 device. It will create a 1second periodic output that can
 114  * be used as the PPS (via an interrupt).
 115  *
 116  * It calculates when the systime will be on an exact second, and then
 117  * aligns the start of the PPS signal to that value. The shift is
 118  * necessary because it can change based on the link speed.
 119  */
 120 static void ixgbe_ptp_setup_sdp(struct ixgbe_adapter *adapter)
 121 {
 122         struct ixgbe_hw *hw = &adapter->hw;
 123         int shift = adapter->cc.shift;
 124         u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
 125         u64 ns = 0, clock_edge = 0;
 126
 127         if ((adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED) &&
 128             (hw->mac.type == ixgbe_mac_X540)) {
 129
 130                 /* disable the pin first */
 131                 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
 132                 IXGBE_WRITE_FLUSH(hw);
 133
 134                 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 135
 136                 /*
 137                  * enable the SDP0 pin as output, and connected to the
 138                  * native function for Timesync (ClockOut)
 139                  */
 140                 esdp |= (IXGBE_ESDP_SDP0_DIR |
 141                          IXGBE_ESDP_SDP0_NATIVE);
 142
 143                 /*
 144                  * enable the Clock Out feature on SDP0, and allow
 145                  * interrupts to occur when the pin changes
 146                  */
 147                 tsauxc = (IXGBE_TSAUXC_EN_CLK |
 148                           IXGBE_TSAUXC_SYNCLK |
 149                           IXGBE_TSAUXC_SDP0_INT);
 150
 151                 /* clock period (or pulse length) */
 152                 clktiml = (u32)(NSECS_PER_SEC << shift);
 153                 clktimh = (u32)((NSECS_PER_SEC << shift) >> 32);
 154
 155                 /*
 156                  * Account for the cyclecounter wrap-around value by
 157                  * using the converted ns value of the current time to
 158                  * check for when the next aligned second would occur.
 159                  */
 160                 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
 161                 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
 162                 ns = timecounter_cyc2time(&adapter->tc, clock_edge);
 163
 164                 div_u64_rem(ns, NSECS_PER_SEC, &rem);
 165                 clock_edge += ((NSECS_PER_SEC - (u64)rem) << shift);
 166
 167                 /* specify the initial clock start time */
 168                 trgttiml = (u32)clock_edge;
 169                 trgttimh = (u32)(clock_edge >> 32);
 170
 171                 IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
 172                 IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
 173                 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
 174                 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
 175
 176                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 177                 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
 178         } else {
 179                 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
 180         }
 181
 182         IXGBE_WRITE_FLUSH(hw);
 183 }
 184
 185 /**
 186  * ixgbe_ptp_read - read raw cycle counter (to be used by time counter)
 187  * @cc: the cyclecounter structure
 188  *
 189  * this function reads the cyclecounter registers and is called by the
 190  * cyclecounter structure used to construct a ns counter from the
 191  * arbitrary fixed point registers
 192  */
 193 static cycle_t ixgbe_ptp_read(const struct cyclecounter *cc)
 194 {
 195         struct ixgbe_adapter *adapter =
 196                 container_of(cc, struct ixgbe_adapter, cc);
 197         struct ixgbe_hw *hw = &adapter->hw;
 198         u64 stamp = 0;
 199
 200         stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
 201         stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
 202
 203         return stamp;
 204 }
 205
 206 /**
 207  * ixgbe_ptp_adjfreq
 208  * @ptp: the ptp clock structure
 209  * @ppb: parts per billion adjustment from base
 210  *
 211  * adjust the frequency of the ptp cycle counter by the
 212  * indicated ppb from the base frequency.
 213  */
 214 static int ixgbe_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
 215 {
 216         struct ixgbe_adapter *adapter =
 217                 container_of(ptp, struct ixgbe_adapter, ptp_caps);
 218         struct ixgbe_hw *hw = &adapter->hw;
 219         u64 freq;
 220         u32 diff, incval;
 221         int neg_adj = 0;
 222
 223         if (ppb < 0) {
 224                 neg_adj = 1;
 225                 ppb = -ppb;
 226         }
 227
 228         smp_mb();
 229         incval = ACCESS_ONCE(adapter->base_incval);
 230
 231         freq = incval;
 232         freq *= ppb;
 233         diff = div_u64(freq, 1000000000ULL);
 234
 235         incval = neg_adj ? (incval - diff) : (incval + diff);
 236
 237         switch (hw->mac.type) {
 238         case ixgbe_mac_X540:
 239                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
 240                 break;
 241         case ixgbe_mac_82599EB:
 242                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
 243                                 (1 << IXGBE_INCPER_SHIFT_82599) |
 244                                 incval);
 245                 break;
 246         default:
 247                 break;
 248         }
 249
 250         return 0;
 251 }
 252
 253 /**
 254  * ixgbe_ptp_adjtime
 255  * @ptp: the ptp clock structure
 256  * @delta: offset to adjust the cycle counter by
 257  *
 258  * adjust the timer by resetting the timecounter structure.
 259  */
 260 static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
 261 {
 262         struct ixgbe_adapter *adapter =
 263                 container_of(ptp, struct ixgbe_adapter, ptp_caps);
 264         unsigned long flags;
 265         u64 now;
 266
 267         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 268
 269         now = timecounter_read(&adapter->tc);
 270         now += delta;
 271
 272         /* reset the timecounter */
 273         timecounter_init(&adapter->tc,
 274                          &adapter->cc,
 275                          now);
 276
 277         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 278
 279         ixgbe_ptp_setup_sdp(adapter);
 280
 281         return 0;
 282 }
 283
 284 /**
 285  * ixgbe_ptp_gettime
 286  * @ptp: the ptp clock structure
 287  * @ts: timespec structure to hold the current time value
 288  *
 289  * read the timecounter and return the correct value on ns,
 290  * after converting it into a struct timespec.
 291  */
 292 static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
 293 {
 294         struct ixgbe_adapter *adapter =
 295                 container_of(ptp, struct ixgbe_adapter, ptp_caps);
 296         u64 ns;
 297         u32 remainder;
 298         unsigned long flags;
 299
 300         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 301         ns = timecounter_read(&adapter->tc);
 302         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 303
 304         ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
 305         ts->tv_nsec = remainder;
 306
 307         return 0;
 308 }
 309
 310 /**
 311  * ixgbe_ptp_settime
 312  * @ptp: the ptp clock structure
 313  * @ts: the timespec containing the new time for the cycle counter
 314  *
 315  * reset the timecounter to use a new base value instead of the kernel
 316  * wall timer value.
 317  */
 318 static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
 319                              const struct timespec *ts)
 320 {
 321         struct ixgbe_adapter *adapter =
 322                 container_of(ptp, struct ixgbe_adapter, ptp_caps);
 323         u64 ns;
 324         unsigned long flags;
 325
 326         ns = ts->tv_sec * 1000000000ULL;
 327         ns += ts->tv_nsec;
 328
 329         /* reset the timecounter */
 330         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 331         timecounter_init(&adapter->tc, &adapter->cc, ns);
 332         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 333
 334         ixgbe_ptp_setup_sdp(adapter);
 335         return 0;
 336 }
 337
 338 /**
 339  * ixgbe_ptp_enable
 340  * @ptp: the ptp clock structure
 341  * @rq: the requested feature to change
 342  * @on: whether to enable or disable the feature
 343  *
 344  * enable (or disable) ancillary features of the phc subsystem.
 345  * our driver only supports the PPS feature on the X540
 346  */
 347 static int ixgbe_ptp_enable(struct ptp_clock_info *ptp,
 348                             struct ptp_clock_request *rq, int on)
 349 {
 350         struct ixgbe_adapter *adapter =
 351                 container_of(ptp, struct ixgbe_adapter, ptp_caps);
 352
 353         /**
 354          * When PPS is enabled, unmask the interrupt for the ClockOut
 355          * feature, so that the interrupt handler can send the PPS
 356          * event when the clock SDP triggers. Clear mask when PPS is
 357          * disabled
 358          */
 359         if (rq->type == PTP_CLK_REQ_PPS) {
 360                 switch (adapter->hw.mac.type) {
 361                 case ixgbe_mac_X540:
 362                         if (on)
 363                                 adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
 364                         else
 365                                 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
 366
 367                         ixgbe_ptp_setup_sdp(adapter);
 368                         return 0;
 369                 default:
 370                         break;
 371                 }
 372         }
 373
 374         return -ENOTSUPP;
 375 }
 376
 377 /**
 378  * ixgbe_ptp_check_pps_event
 379  * @adapter: the private adapter structure
 380  * @eicr: the interrupt cause register value
 381  *
 382  * This function is called by the interrupt routine when checking for
 383  * interrupts. It will check and handle a pps event.
 384  */
 385 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr)
 386 {
 387         struct ixgbe_hw *hw = &adapter->hw;
 388         struct ptp_clock_event event;
 389
 390         event.type = PTP_CLOCK_PPS;
 391
 392         /* this check is necessary in case the interrupt was enabled via some
 393          * alternative means (ex. debug_fs). Better to check here than
 394          * everywhere that calls this function.
 395          */
 396         if (!adapter->ptp_clock)
 397                 return;
 398
 399         switch (hw->mac.type) {
 400         case ixgbe_mac_X540:
 401                 ptp_clock_event(adapter->ptp_clock, &event);
 402                 break;
 403         default:
 404                 break;
 405         }
 406 }
 407
 408
 409 /**
 410  * ixgbe_ptp_overflow_check - delayed work to detect SYSTIME overflow
 411  * @work: structure containing information about this work task
 412  *
 413  * this work function is scheduled to continue reading the timecounter
 414  * in order to prevent missing when the system time registers wrap
 415  * around. This needs to be run approximately twice a minute when no
 416  * PTP activity is occurring.
 417  */
 418 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter)
 419 {
 420         unsigned long elapsed_jiffies = adapter->last_overflow_check - jiffies;
 421         struct timespec ts;
 422
 423         if ((adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED) &&
 424             (elapsed_jiffies >= IXGBE_OVERFLOW_PERIOD)) {
 425                 ixgbe_ptp_gettime(&adapter->ptp_caps, &ts);
 426                 adapter->last_overflow_check = jiffies;
 427         }
 428 }
 429
 430 /**
 431  * ixgbe_ptp_match - determine if this skb matches a ptp packet
 432  * @skb: pointer to the skb
 433  * @hwtstamp: pointer to the hwtstamp_config to check
 434  *
 435  * Determine whether the skb should have been timestamped, assuming the
 436  * hwtstamp was set via the hwtstamp ioctl. Returns non-zero when the packet
 437  * should have a timestamp waiting in the registers, and 0 otherwise.
 438  *
 439  * V1 packets have to check the version type to determine whether they are
 440  * correct. However, we can't directly access the data because it might be
 441  * fragmented in the SKB, in paged memory. In order to work around this, we
 442  * use skb_copy_bits which will properly copy the data whether it is in the
 443  * paged memory fragments or not. We have to copy the IP header as well as the
 444  * message type.
 445  */
 446 static int ixgbe_ptp_match(struct sk_buff *skb, int rx_filter)
 447 {
 448         struct iphdr iph;
 449         u8 msgtype;
 450         unsigned int type, offset;
 451
 452         if (rx_filter == HWTSTAMP_FILTER_NONE)
 453                 return 0;
 454
 455         type = sk_run_filter(skb, ptp_filter);
 456
 457         if (likely(rx_filter == HWTSTAMP_FILTER_PTP_V2_EVENT))
 458                 return type & PTP_CLASS_V2;
 459
 460         /* For the remaining cases actually check message type */
 461         switch (type) {
 462         case PTP_CLASS_V1_IPV4:
 463                 skb_copy_bits(skb, OFF_IHL, &iph, sizeof(iph));
 464                 offset = ETH_HLEN + (iph.ihl << 2) + UDP_HLEN + OFF_PTP_CONTROL;
 465                 break;
 466         case PTP_CLASS_V1_IPV6:
 467                 offset = OFF_PTP6 + OFF_PTP_CONTROL;
 468                 break;
 469         default:
 470                 /* other cases invalid or handled above */
 471                 return 0;
 472         }
 473
 474         /* Make sure our buffer is long enough */
 475         if (skb->len < offset)
 476                 return 0;
 477
 478         skb_copy_bits(skb, offset, &msgtype, sizeof(msgtype));
 479
 480         switch (rx_filter) {
 481         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 482                 return (msgtype == IXGBE_RXMTRL_V1_SYNC_MSG);
 483                 break;
 484         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 485                 return (msgtype == IXGBE_RXMTRL_V1_DELAY_REQ_MSG);
 486                 break;
 487         default:
 488                 return 0;
 489         }
 490 }
 491
 492 /**
 493  * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp
 494  * @q_vector: structure containing interrupt and ring information
 495  * @skb: particular skb to send timestamp with
 496  *
 497  * if the timestamp is valid, we convert it into the timecounter ns
 498  * value, then store that result into the shhwtstamps structure which
 499  * is passed up the network stack
 500  */
 501 void ixgbe_ptp_tx_hwtstamp(struct ixgbe_q_vector *q_vector,
 502                            struct sk_buff *skb)
 503 {
 504         struct ixgbe_adapter *adapter;
 505         struct ixgbe_hw *hw;
 506         struct skb_shared_hwtstamps shhwtstamps;
 507         u64 regval = 0, ns;
 508         u32 tsynctxctl;
 509         unsigned long flags;
 510
 511         /* we cannot process timestamps on a ring without a q_vector */
 512         if (!q_vector || !q_vector->adapter)
 513                 return;
 514
 515         adapter = q_vector->adapter;
 516         hw = &adapter->hw;
 517
 518         tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
 519         regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
 520         regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
 521
 522         /*
 523          * if TX timestamp is not valid, exit after clearing the
 524          * timestamp registers
 525          */
 526         if (!(tsynctxctl & IXGBE_TSYNCTXCTL_VALID))
 527                 return;
 528
 529         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 530         ns = timecounter_cyc2time(&adapter->tc, regval);
 531         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 532
 533         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 534         shhwtstamps.hwtstamp = ns_to_ktime(ns);
 535         skb_tstamp_tx(skb, &shhwtstamps);
 536 }
 537
 538 /**
 539  * ixgbe_ptp_rx_hwtstamp - utility function which checks for RX time stamp
 540  * @q_vector: structure containing interrupt and ring information
 541  * @rx_desc: the rx descriptor
 542  * @skb: particular skb to send timestamp with
 543  *
 544  * if the timestamp is valid, we convert it into the timecounter ns
 545  * value, then store that result into the shhwtstamps structure which
 546  * is passed up the network stack
 547  */
 548 void ixgbe_ptp_rx_hwtstamp(struct ixgbe_q_vector *q_vector,
 549                            union ixgbe_adv_rx_desc *rx_desc,
 550                            struct sk_buff *skb)
 551 {
 552         struct ixgbe_adapter *adapter;
 553         struct ixgbe_hw *hw;
 554         struct skb_shared_hwtstamps *shhwtstamps;
 555         u64 regval = 0, ns;
 556         u32 tsyncrxctl;
 557         unsigned long flags;
 558
 559         /* we cannot process timestamps on a ring without a q_vector */
 560         if (!q_vector || !q_vector->adapter)
 561                 return;
 562
 563         adapter = q_vector->adapter;
 564         hw = &adapter->hw;
 565
 566         if (likely(!ixgbe_ptp_match(skb, adapter->rx_hwtstamp_filter)))
 567                 return;
 568
 569         tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
 570
 571         /* Check if we have a valid timestamp and make sure the skb should
 572          * have been timestamped */
 573         if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID))
 574                 return;
 575
 576         /*
 577          * Always read the registers, in order to clear a possible fault
 578          * because of stagnant RX timestamp values for a packet that never
 579          * reached the queue.
 580          */
 581         regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
 582         regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
 583
 584         /*
 585          * If the timestamp bit is set in the packet's descriptor, we know the
 586          * timestamp belongs to this packet. No other packet can be
 587          * timestamped until the registers for timestamping have been read.
 588          * Therefor only one packet with this bit can be in the queue at a
 589          * time, and the rx timestamp values that were in the registers belong
 590          * to this packet.
 591          *
 592          * If nothing went wrong, then it should have a skb_shared_tx that we
 593          * can turn into a skb_shared_hwtstamps.
 594          */
 595         if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
 596                 return;
 597
 598         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 599         ns = timecounter_cyc2time(&adapter->tc, regval);
 600         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 601
 602         shhwtstamps = skb_hwtstamps(skb);
 603         shhwtstamps->hwtstamp = ns_to_ktime(ns);
 604 }
 605
 606 /**
 607  * ixgbe_ptp_hwtstamp_ioctl - control hardware time stamping
 608  * @adapter: pointer to adapter struct
 609  * @ifreq: ioctl data
 610  * @cmd: particular ioctl requested
 611  *
 612  * Outgoing time stamping can be enabled and disabled. Play nice and
 613  * disable it when requested, although it shouldn't case any overhead
 614  * when no packet needs it. At most one packet in the queue may be
 615  * marked for time stamping, otherwise it would be impossible to tell
 616  * for sure to which packet the hardware time stamp belongs.
 617  *
 618  * Incoming time stamping has to be configured via the hardware
 619  * filters. Not all combinations are supported, in particular event
 620  * type has to be specified. Matching the kind of event packet is
 621  * not supported, with the exception of "all V2 events regardless of
 622  * level 2 or 4".
 623  *
 624  * Since hardware always timestamps Path delay packets when timestamping V2
 625  * packets, regardless of the type specified in the register, only use V2
 626  * Event mode. This more accurately tells the user what the hardware is going
 627  * to do anyways.
 628  */
 629 int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter,
 630                              struct ifreq *ifr, int cmd)
 631 {
 632         struct ixgbe_hw *hw = &adapter->hw;
 633         struct hwtstamp_config config;
 634         u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
 635         u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
 636         u32 tsync_rx_mtrl = 0;
 637         bool is_l4 = false;
 638         bool is_l2 = false;
 639         u32 regval;
 640
 641         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 642                 return -EFAULT;
 643
 644         /* reserved for future extensions */
 645         if (config.flags)
 646                 return -EINVAL;
 647
 648         switch (config.tx_type) {
 649         case HWTSTAMP_TX_OFF:
 650                 tsync_tx_ctl = 0;
 651         case HWTSTAMP_TX_ON:
 652                 break;
 653         default:
 654                 return -ERANGE;
 655         }
 656
 657         switch (config.rx_filter) {
 658         case HWTSTAMP_FILTER_NONE:
 659                 tsync_rx_ctl = 0;
 660                 break;
 661         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 662                 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
 663                 tsync_rx_mtrl = IXGBE_RXMTRL_V1_SYNC_MSG;
 664                 is_l4 = true;
 665                 break;
 666         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 667                 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
 668                 tsync_rx_mtrl = IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
 669                 is_l4 = true;
 670                 break;
 671         case HWTSTAMP_FILTER_PTP_V2_EVENT:
 672         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 673         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 674         case HWTSTAMP_FILTER_PTP_V2_SYNC:
 675         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
 676         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 677         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 678         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
 679         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 680                 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
 681                 is_l2 = true;
 682                 is_l4 = true;
 683                 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 684                 break;
 685         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 686         case HWTSTAMP_FILTER_ALL:
 687         default:
 688                 /*
 689                  * register RXMTRL must be set in order to do V1 packets,
 690                  * therefore it is not possible to time stamp both V1 Sync and
 691                  * Delay_Req messages and hardware does not support
 692                  * timestamping all packets => return error
 693                  */
 694                 config.rx_filter = HWTSTAMP_FILTER_NONE;
 695                 return -ERANGE;
 696         }
 697
 698         if (hw->mac.type == ixgbe_mac_82598EB) {
 699                 if (tsync_rx_ctl | tsync_tx_ctl)
 700                         return -ERANGE;
 701                 return 0;
 702         }
 703
 704         /* Store filter value for later use */
 705         adapter->rx_hwtstamp_filter = config.rx_filter;
 706
 707         /* define ethertype filter for timestamped packets */
 708         if (is_l2)
 709                 IXGBE_WRITE_REG(hw, IXGBE_ETQF(3),
 710                                 (IXGBE_ETQF_FILTER_EN | /* enable filter */
 711                                  IXGBE_ETQF_1588 | /* enable timestamping */
 712                                  ETH_P_1588));     /* 1588 eth protocol type */
 713         else
 714                 IXGBE_WRITE_REG(hw, IXGBE_ETQF(3), 0);
 715
 716 #define PTP_PORT 319
 717         /* L4 Queue Filter[3]: filter by destination port and protocol */
 718         if (is_l4) {
 719                 u32 ftqf = (IXGBE_FTQF_PROTOCOL_UDP /* UDP */
 720                             | IXGBE_FTQF_POOL_MASK_EN /* Pool not compared */
 721                             | IXGBE_FTQF_QUEUE_ENABLE);
 722
 723                 ftqf |= ((IXGBE_FTQF_PROTOCOL_COMP_MASK /* protocol check */
 724                           & IXGBE_FTQF_DEST_PORT_MASK /* dest check */
 725                           & IXGBE_FTQF_SOURCE_PORT_MASK) /* source check */
 726                          << IXGBE_FTQF_5TUPLE_MASK_SHIFT);
 727
 728                 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(3),
 729                                 (3 << IXGBE_IMIR_RX_QUEUE_SHIFT_82599 |
 730                                  IXGBE_IMIR_SIZE_BP_82599));
 731
 732                 /* enable port check */
 733                 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(3),
 734                                 (htons(PTP_PORT) |
 735                                  htons(PTP_PORT) << 16));
 736
 737                 IXGBE_WRITE_REG(hw, IXGBE_FTQF(3), ftqf);
 738
 739                 tsync_rx_mtrl |= PTP_PORT << 16;
 740         } else {
 741                 IXGBE_WRITE_REG(hw, IXGBE_FTQF(3), 0);
 742         }
 743
 744         /* enable/disable TX */
 745         regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
 746         regval &= ~IXGBE_TSYNCTXCTL_ENABLED;
 747         regval |= tsync_tx_ctl;
 748         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);
 749
 750         /* enable/disable RX */
 751         regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
 752         regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);
 753         regval |= tsync_rx_ctl;
 754         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);
 755
 756         /* define which PTP packets are time stamped */
 757         IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl);
 758
 759         IXGBE_WRITE_FLUSH(hw);
 760
 761         /* clear TX/RX time stamp registers, just to be sure */
 762         regval = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
 763         regval = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
 764
 765         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 766                 -EFAULT : 0;
 767 }
 768
 769 /**
 770  * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw
 771  * @adapter: pointer to the adapter structure
 772  *
 773  * This function should be called to set the proper values for the TIMINCA
 774  * register and tell the cyclecounter structure what the tick rate of SYSTIME
 775  * is. It does not directly modify SYSTIME registers or the timecounter
 776  * structure. It should be called whenever a new TIMINCA value is necessary,
 777  * such as during initialization or when the link speed changes.
 778  */
 779 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
 780 {
 781         struct ixgbe_hw *hw = &adapter->hw;
 782         u32 incval = 0;
 783         u32 shift = 0;
 784         unsigned long flags;
 785
 786         /**
 787          * Scale the NIC cycle counter by a large factor so that
 788          * relatively small corrections to the frequency can be added
 789          * or subtracted. The drawbacks of a large factor include
 790          * (a) the clock register overflows more quickly, (b) the cycle
 791          * counter structure must be able to convert the systime value
 792          * to nanoseconds using only a multiplier and a right-shift,
 793          * and (c) the value must fit within the timinca register space
 794          * => math based on internal DMA clock rate and available bits
 795          *
 796          * Note that when there is no link, internal DMA clock is same as when
 797          * link speed is 10Gb. Set the registers correctly even when link is
 798          * down to preserve the clock setting
 799          */
 800         switch (adapter->link_speed) {
 801         case IXGBE_LINK_SPEED_100_FULL:
 802                 incval = IXGBE_INCVAL_100;
 803                 shift = IXGBE_INCVAL_SHIFT_100;
 804                 break;
 805         case IXGBE_LINK_SPEED_1GB_FULL:
 806                 incval = IXGBE_INCVAL_1GB;
 807                 shift = IXGBE_INCVAL_SHIFT_1GB;
 808                 break;
 809         case IXGBE_LINK_SPEED_10GB_FULL:
 810         default:
 811                 incval = IXGBE_INCVAL_10GB;
 812                 shift = IXGBE_INCVAL_SHIFT_10GB;
 813                 break;
 814         }
 815
 816         /**
 817          * Modify the calculated values to fit within the correct
 818          * number of bits specified by the hardware. The 82599 doesn't
 819          * have the same space as the X540, so bitshift the calculated
 820          * values to fit.
 821          */
 822         switch (hw->mac.type) {
 823         case ixgbe_mac_X540:
 824                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
 825                 break;
 826         case ixgbe_mac_82599EB:
 827                 incval >>= IXGBE_INCVAL_SHIFT_82599;
 828                 shift -= IXGBE_INCVAL_SHIFT_82599;
 829                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
 830                                 (1 << IXGBE_INCPER_SHIFT_82599) |
 831                                 incval);
 832                 break;
 833         default:
 834                 /* other devices aren't supported */
 835                 return;
 836         }
 837
 838         /* update the base incval used to calculate frequency adjustment */
 839         ACCESS_ONCE(adapter->base_incval) = incval;
 840         smp_mb();
 841
 842         /* need lock to prevent incorrect read while modifying cyclecounter */
 843         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 844
 845         memset(&adapter->cc, 0, sizeof(adapter->cc));
 846         adapter->cc.read = ixgbe_ptp_read;
 847         adapter->cc.mask = CLOCKSOURCE_MASK(64);
 848         adapter->cc.shift = shift;
 849         adapter->cc.mult = 1;
 850
 851         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 852 }
 853
 854 /**
 855  * ixgbe_ptp_reset
 856  * @adapter: the ixgbe private board structure
 857  *
 858  * When the MAC resets, all timesync features are reset. This function should be
 859  * called to re-enable the PTP clock structure. It will re-init the timecounter
 860  * structure based on the kernel time as well as setup the cycle counter data.
 861  */
 862 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter)
 863 {
 864         struct ixgbe_hw *hw = &adapter->hw;
 865         unsigned long flags;
 866
 867         /* set SYSTIME registers to 0 just in case */
 868         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x00000000);
 869         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x00000000);
 870         IXGBE_WRITE_FLUSH(hw);
 871
 872         ixgbe_ptp_start_cyclecounter(adapter);
 873
 874         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 875
 876         /* reset the ns time counter */
 877         timecounter_init(&adapter->tc, &adapter->cc,
 878                          ktime_to_ns(ktime_get_real()));
 879
 880         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 881
 882         /*
 883          * Now that the shift has been calculated and the systime
 884          * registers reset, (re-)enable the Clock out feature
 885          */
 886         ixgbe_ptp_setup_sdp(adapter);
 887 }
 888
 889 /**
 890  * ixgbe_ptp_init
 891  * @adapter: the ixgbe private adapter structure
 892  *
 893  * This function performs the required steps for enabling ptp
 894  * support. If ptp support has already been loaded it simply calls the
 895  * cyclecounter init routine and exits.
 896  */
 897 void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
 898 {
 899         struct net_device *netdev = adapter->netdev;
 900
 901         switch (adapter->hw.mac.type) {
 902         case ixgbe_mac_X540:
 903                 snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name);
 904                 adapter->ptp_caps.owner = THIS_MODULE;
 905                 adapter->ptp_caps.max_adj = 250000000;
 906                 adapter->ptp_caps.n_alarm = 0;
 907                 adapter->ptp_caps.n_ext_ts = 0;
 908                 adapter->ptp_caps.n_per_out = 0;
 909                 adapter->ptp_caps.pps = 1;
 910                 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
 911                 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
 912                 adapter->ptp_caps.gettime = ixgbe_ptp_gettime;
 913                 adapter->ptp_caps.settime = ixgbe_ptp_settime;
 914                 adapter->ptp_caps.enable = ixgbe_ptp_enable;
 915                 break;
 916         case ixgbe_mac_82599EB:
 917                 snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name);
 918                 adapter->ptp_caps.owner = THIS_MODULE;
 919                 adapter->ptp_caps.max_adj = 250000000;
 920                 adapter->ptp_caps.n_alarm = 0;
 921                 adapter->ptp_caps.n_ext_ts = 0;
 922                 adapter->ptp_caps.n_per_out = 0;
 923                 adapter->ptp_caps.pps = 0;
 924                 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
 925                 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
 926                 adapter->ptp_caps.gettime = ixgbe_ptp_gettime;
 927                 adapter->ptp_caps.settime = ixgbe_ptp_settime;
 928                 adapter->ptp_caps.enable = ixgbe_ptp_enable;
 929                 break;
 930         default:
 931                 adapter->ptp_clock = NULL;
 932                 return;
 933         }
 934
 935         /* initialize the ptp filter */
 936         if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter)))
 937                 e_dev_warn("ptp_filter_init failed\n");
 938
 939         spin_lock_init(&adapter->tmreg_lock);
 940
 941         adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
 942                                                 &adapter->pdev->dev);
 943         if (IS_ERR(adapter->ptp_clock)) {
 944                 adapter->ptp_clock = NULL;
 945                 e_dev_err("ptp_clock_register failed\n");
 946         } else
 947                 e_dev_info("registered PHC device on %s\n", netdev->name);
 948
 949         ixgbe_ptp_reset(adapter);
 950
 951         /* set the flag that PTP has been enabled */
 952         adapter->flags2 |= IXGBE_FLAG2_PTP_ENABLED;
 953
 954         return;
 955 }
 956
 957 /**
 958  * ixgbe_ptp_stop - disable ptp device and stop the overflow check
 959  * @adapter: pointer to adapter struct
 960  *
 961  * this function stops the ptp support, and cancels the delayed work.
 962  */
 963 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
 964 {
 965         /* stop the overflow check task */
 966         adapter->flags2 &= ~(IXGBE_FLAG2_PTP_ENABLED |
 967                              IXGBE_FLAG2_PTP_PPS_ENABLED);
 968
 969         ixgbe_ptp_setup_sdp(adapter);
 970
 971         if (adapter->ptp_clock) {
 972                 ptp_clock_unregister(adapter->ptp_clock);
 973                 adapter->ptp_clock = NULL;
 974                 e_dev_info("removed PHC on %s\n",
 975                            adapter->netdev->name);
 976         }
 977 }