drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27 #include "ixgbe.h"
  28 #include <linux/export.h>
  29 #include <linux/ptp_classify.h>
  30
  31 /*
  32  * The 82599 and the X540 do not have true 64bit nanosecond scale
  33  * counter registers. Instead, SYSTIME is defined by a fixed point
  34  * system which allows the user to define the scale counter increment
  35  * value at every level change of the oscillator driving the SYSTIME
  36  * value. For both devices the TIMINCA:IV field defines this
  37  * increment. On the X540 device, 31 bits are provided. However on the
  38  * 82599 only provides 24 bits. The time unit is determined by the
  39  * clock frequency of the oscillator in combination with the TIMINCA
  40  * register. When these devices link at 10Gb the oscillator has a
  41  * period of 6.4ns. In order to convert the scale counter into
  42  * nanoseconds the cyclecounter and timecounter structures are
  43  * used. The SYSTIME registers need to be converted to ns values by use
  44  * of only a right shift (division by power of 2). The following math
  45  * determines the largest incvalue that will fit into the available
  46  * bits in the TIMINCA register.
  47  *
  48  * PeriodWidth: Number of bits to store the clock period
  49  * MaxWidth: The maximum width value of the TIMINCA register
  50  * Period: The clock period for the oscillator
  51  * round(): discard the fractional portion of the calculation
  52  *
  53  * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
  54  *
  55  * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns
  56  * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns
  57  *
  58  * The period also changes based on the link speed:
  59  * At 10Gb link or no link, the period remains the same.
  60  * At 1Gb link, the period is multiplied by 10. (64ns)
  61  * At 100Mb link, the period is multiplied by 100. (640ns)
  62  *
  63  * The calculated value allows us to right shift the SYSTIME register
  64  * value in order to quickly convert it into a nanosecond clock,
  65  * while allowing for the maximum possible adjustment value.
  66  *
  67  * These diagrams are only for the 10Gb link period
  68  *
  69  *           SYSTIMEH            SYSTIMEL
  70  *       +--------------+  +--------------+
  71  * X540  |      32      |  | 1 | 3 |  28  |
  72  *       *--------------+  +--------------+
  73  *        \________ 36 bits ______/  fract
  74  *
  75  *       +--------------+  +--------------+
  76  * 82599 |      32      |  | 8 | 3 |  21  |
  77  *       *--------------+  +--------------+
  78  *        \________ 43 bits ______/  fract
  79  *
  80  * The 36 bit X540 SYSTIME overflows every
  81  *   2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
  82  *
  83  * The 43 bit 82599 SYSTIME overflows every
  84  *   2^43 * 10^-9 / 3600 = 2.4 hours
  85  */
  86 #define IXGBE_INCVAL_10GB 0x66666666
  87 #define IXGBE_INCVAL_1GB  0x40000000
  88 #define IXGBE_INCVAL_100  0x50000000
  89
  90 #define IXGBE_INCVAL_SHIFT_10GB  28
  91 #define IXGBE_INCVAL_SHIFT_1GB   24
  92 #define IXGBE_INCVAL_SHIFT_100   21
  93
  94 #define IXGBE_INCVAL_SHIFT_82599 7
  95 #define IXGBE_INCPER_SHIFT_82599 24
  96 #define IXGBE_MAX_TIMEADJ_VALUE  0x7FFFFFFFFFFFFFFFULL
  97
  98 #define IXGBE_OVERFLOW_PERIOD    (HZ * 30)
  99
 100 #ifndef NSECS_PER_SEC
 101 #define NSECS_PER_SEC 1000000000ULL
 102 #endif
 103
 104 /**
 105  * ixgbe_ptp_setup_sdp
 106  * @hw: the hardware private structure
 107  *
 108  * this function enables or disables the clock out feature on SDP0 for
 109  * the X540 device. It will create a 1second periodic output that can
 110  * be used as the PPS (via an interrupt).
 111  *
 112  * It calculates when the systime will be on an exact second, and then
 113  * aligns the start of the PPS signal to that value. The shift is
 114  * necessary because it can change based on the link speed.
 115  */
 116 static void ixgbe_ptp_setup_sdp(struct ixgbe_adapter *adapter)
 117 {
 118         struct ixgbe_hw *hw = &adapter->hw;
 119         int shift = adapter->cc.shift;
 120         u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
 121         u64 ns = 0, clock_edge = 0;
 122
 123         if ((adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED) &&
 124             (hw->mac.type == ixgbe_mac_X540)) {
 125
 126                 /* disable the pin first */
 127                 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
 128                 IXGBE_WRITE_FLUSH(hw);
 129
 130                 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 131
 132                 /*
 133                  * enable the SDP0 pin as output, and connected to the
 134                  * native function for Timesync (ClockOut)
 135                  */
 136                 esdp |= (IXGBE_ESDP_SDP0_DIR |
 137                          IXGBE_ESDP_SDP0_NATIVE);
 138
 139                 /*
 140                  * enable the Clock Out feature on SDP0, and allow
 141                  * interrupts to occur when the pin changes
 142                  */
 143                 tsauxc = (IXGBE_TSAUXC_EN_CLK |
 144                           IXGBE_TSAUXC_SYNCLK |
 145                           IXGBE_TSAUXC_SDP0_INT);
 146
 147                 /* clock period (or pulse length) */
 148                 clktiml = (u32)(NSECS_PER_SEC << shift);
 149                 clktimh = (u32)((NSECS_PER_SEC << shift) >> 32);
 150
 151                 /*
 152                  * Account for the cyclecounter wrap-around value by
 153                  * using the converted ns value of the current time to
 154                  * check for when the next aligned second would occur.
 155                  */
 156                 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
 157                 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
 158                 ns = timecounter_cyc2time(&adapter->tc, clock_edge);
 159
 160                 div_u64_rem(ns, NSECS_PER_SEC, &rem);
 161                 clock_edge += ((NSECS_PER_SEC - (u64)rem) << shift);
 162
 163                 /* specify the initial clock start time */
 164                 trgttiml = (u32)clock_edge;
 165                 trgttimh = (u32)(clock_edge >> 32);
 166
 167                 IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
 168                 IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
 169                 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
 170                 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
 171
 172                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 173                 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
 174         } else {
 175                 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
 176         }
 177
 178         IXGBE_WRITE_FLUSH(hw);
 179 }
 180
 181 /**
 182  * ixgbe_ptp_read - read raw cycle counter (to be used by time counter)
 183  * @cc: the cyclecounter structure
 184  *
 185  * this function reads the cyclecounter registers and is called by the
 186  * cyclecounter structure used to construct a ns counter from the
 187  * arbitrary fixed point registers
 188  */
 189 static cycle_t ixgbe_ptp_read(const struct cyclecounter *cc)
 190 {
 191         struct ixgbe_adapter *adapter =
 192                 container_of(cc, struct ixgbe_adapter, cc);
 193         struct ixgbe_hw *hw = &adapter->hw;
 194         u64 stamp = 0;
 195
 196         stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
 197         stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
 198
 199         return stamp;
 200 }
 201
 202 /**
 203  * ixgbe_ptp_adjfreq
 204  * @ptp: the ptp clock structure
 205  * @ppb: parts per billion adjustment from base
 206  *
 207  * adjust the frequency of the ptp cycle counter by the
 208  * indicated ppb from the base frequency.
 209  */
 210 static int ixgbe_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
 211 {
 212         struct ixgbe_adapter *adapter =
 213                 container_of(ptp, struct ixgbe_adapter, ptp_caps);
 214         struct ixgbe_hw *hw = &adapter->hw;
 215         u64 freq;
 216         u32 diff, incval;
 217         int neg_adj = 0;
 218
 219         if (ppb < 0) {
 220                 neg_adj = 1;
 221                 ppb = -ppb;
 222         }
 223
 224         smp_mb();
 225         incval = ACCESS_ONCE(adapter->base_incval);
 226
 227         freq = incval;
 228         freq *= ppb;
 229         diff = div_u64(freq, 1000000000ULL);
 230
 231         incval = neg_adj ? (incval - diff) : (incval + diff);
 232
 233         switch (hw->mac.type) {
 234         case ixgbe_mac_X540:
 235                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
 236                 break;
 237         case ixgbe_mac_82599EB:
 238                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
 239                                 (1 << IXGBE_INCPER_SHIFT_82599) |
 240                                 incval);
 241                 break;
 242         default:
 243                 break;
 244         }
 245
 246         return 0;
 247 }
 248
 249 /**
 250  * ixgbe_ptp_adjtime
 251  * @ptp: the ptp clock structure
 252  * @delta: offset to adjust the cycle counter by
 253  *
 254  * adjust the timer by resetting the timecounter structure.
 255  */
 256 static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
 257 {
 258         struct ixgbe_adapter *adapter =
 259                 container_of(ptp, struct ixgbe_adapter, ptp_caps);
 260         unsigned long flags;
 261         u64 now;
 262
 263         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 264
 265         now = timecounter_read(&adapter->tc);
 266         now += delta;
 267
 268         /* reset the timecounter */
 269         timecounter_init(&adapter->tc,
 270                          &adapter->cc,
 271                          now);
 272
 273         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 274
 275         ixgbe_ptp_setup_sdp(adapter);
 276
 277         return 0;
 278 }
 279
 280 /**
 281  * ixgbe_ptp_gettime
 282  * @ptp: the ptp clock structure
 283  * @ts: timespec structure to hold the current time value
 284  *
 285  * read the timecounter and return the correct value on ns,
 286  * after converting it into a struct timespec.
 287  */
 288 static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
 289 {
 290         struct ixgbe_adapter *adapter =
 291                 container_of(ptp, struct ixgbe_adapter, ptp_caps);
 292         u64 ns;
 293         u32 remainder;
 294         unsigned long flags;
 295
 296         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 297         ns = timecounter_read(&adapter->tc);
 298         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 299
 300         ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
 301         ts->tv_nsec = remainder;
 302
 303         return 0;
 304 }
 305
 306 /**
 307  * ixgbe_ptp_settime
 308  * @ptp: the ptp clock structure
 309  * @ts: the timespec containing the new time for the cycle counter
 310  *
 311  * reset the timecounter to use a new base value instead of the kernel
 312  * wall timer value.
 313  */
 314 static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
 315                              const struct timespec *ts)
 316 {
 317         struct ixgbe_adapter *adapter =
 318                 container_of(ptp, struct ixgbe_adapter, ptp_caps);
 319         u64 ns;
 320         unsigned long flags;
 321
 322         ns = ts->tv_sec * 1000000000ULL;
 323         ns += ts->tv_nsec;
 324
 325         /* reset the timecounter */
 326         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 327         timecounter_init(&adapter->tc, &adapter->cc, ns);
 328         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 329
 330         ixgbe_ptp_setup_sdp(adapter);
 331         return 0;
 332 }
 333
 334 /**
 335  * ixgbe_ptp_enable
 336  * @ptp: the ptp clock structure
 337  * @rq: the requested feature to change
 338  * @on: whether to enable or disable the feature
 339  *
 340  * enable (or disable) ancillary features of the phc subsystem.
 341  * our driver only supports the PPS feature on the X540
 342  */
 343 static int ixgbe_ptp_enable(struct ptp_clock_info *ptp,
 344                             struct ptp_clock_request *rq, int on)
 345 {
 346         struct ixgbe_adapter *adapter =
 347                 container_of(ptp, struct ixgbe_adapter, ptp_caps);
 348
 349         /**
 350          * When PPS is enabled, unmask the interrupt for the ClockOut
 351          * feature, so that the interrupt handler can send the PPS
 352          * event when the clock SDP triggers. Clear mask when PPS is
 353          * disabled
 354          */
 355         if (rq->type == PTP_CLK_REQ_PPS) {
 356                 switch (adapter->hw.mac.type) {
 357                 case ixgbe_mac_X540:
 358                         if (on)
 359                                 adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
 360                         else
 361                                 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
 362
 363                         ixgbe_ptp_setup_sdp(adapter);
 364                         return 0;
 365                 default:
 366                         break;
 367                 }
 368         }
 369
 370         return -ENOTSUPP;
 371 }
 372
 373 /**
 374  * ixgbe_ptp_check_pps_event
 375  * @adapter: the private adapter structure
 376  * @eicr: the interrupt cause register value
 377  *
 378  * This function is called by the interrupt routine when checking for
 379  * interrupts. It will check and handle a pps event.
 380  */
 381 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr)
 382 {
 383         struct ixgbe_hw *hw = &adapter->hw;
 384         struct ptp_clock_event event;
 385
 386         event.type = PTP_CLOCK_PPS;
 387
 388         /* this check is necessary in case the interrupt was enabled via some
 389          * alternative means (ex. debug_fs). Better to check here than
 390          * everywhere that calls this function.
 391          */
 392         if (!adapter->ptp_clock)
 393                 return;
 394
 395         switch (hw->mac.type) {
 396         case ixgbe_mac_X540:
 397                 ptp_clock_event(adapter->ptp_clock, &event);
 398                 break;
 399         default:
 400                 break;
 401         }
 402 }
 403
 404
 405 /**
 406  * ixgbe_ptp_overflow_check - watchdog task to detect SYSTIME overflow
 407  * @adapter: private adapter struct
 408  *
 409  * this watchdog task periodically reads the timecounter
 410  * in order to prevent missing when the system time registers wrap
 411  * around. This needs to be run approximately twice a minute.
 412  */
 413 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter)
 414 {
 415         bool timeout = time_is_before_jiffies(adapter->last_overflow_check +
 416                                              IXGBE_OVERFLOW_PERIOD);
 417         struct timespec ts;
 418
 419         if ((adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED) &&
 420             (timeout)) {
 421                 ixgbe_ptp_gettime(&adapter->ptp_caps, &ts);
 422                 adapter->last_overflow_check = jiffies;
 423         }
 424 }
 425
 426 /**
 427  * ixgbe_ptp_rx_hang - detect error case when Rx timestamp registers latched
 428  * @adapter: private network adapter structure
 429  *
 430  * this watchdog task is scheduled to detect error case where hardware has
 431  * dropped an Rx packet that was timestamped when the ring is full. The
 432  * particular error is rare but leaves the device in a state unable to timestamp
 433  * any future packets.
 434  */
 435 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter)
 436 {
 437         struct ixgbe_hw *hw = &adapter->hw;
 438         struct ixgbe_ring *rx_ring;
 439         u32 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
 440         unsigned long rx_event;
 441         int n;
 442
 443         /* if we don't have a valid timestamp in the registers, just update the
 444          * timeout counter and exit
 445          */
 446         if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) {
 447                 adapter->last_rx_ptp_check = jiffies;
 448                 return;
 449         }
 450
 451         /* determine the most recent watchdog or rx_timestamp event */
 452         rx_event = adapter->last_rx_ptp_check;
 453         for (n = 0; n < adapter->num_rx_queues; n++) {
 454                 rx_ring = adapter->rx_ring[n];
 455                 if (time_after(rx_ring->last_rx_timestamp, rx_event))
 456                         rx_event = rx_ring->last_rx_timestamp;
 457         }
 458
 459         /* only need to read the high RXSTMP register to clear the lock */
 460         if (time_is_before_jiffies(rx_event + 5*HZ)) {
 461                 IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
 462                 adapter->last_rx_ptp_check = jiffies;
 463
 464                 e_warn(drv, "clearing RX Timestamp hang");
 465         }
 466 }
 467
 468 /**
 469  * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp
 470  * @q_vector: structure containing interrupt and ring information
 471  * @skb: particular skb to send timestamp with
 472  *
 473  * if the timestamp is valid, we convert it into the timecounter ns
 474  * value, then store that result into the shhwtstamps structure which
 475  * is passed up the network stack
 476  */
 477 void ixgbe_ptp_tx_hwtstamp(struct ixgbe_q_vector *q_vector,
 478                            struct sk_buff *skb)
 479 {
 480         struct ixgbe_adapter *adapter;
 481         struct ixgbe_hw *hw;
 482         struct skb_shared_hwtstamps shhwtstamps;
 483         u64 regval = 0, ns;
 484         u32 tsynctxctl;
 485         unsigned long flags;
 486
 487         /* we cannot process timestamps on a ring without a q_vector */
 488         if (!q_vector || !q_vector->adapter)
 489                 return;
 490
 491         adapter = q_vector->adapter;
 492         hw = &adapter->hw;
 493
 494         tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
 495         regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
 496         regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
 497
 498         /*
 499          * if TX timestamp is not valid, exit after clearing the
 500          * timestamp registers
 501          */
 502         if (!(tsynctxctl & IXGBE_TSYNCTXCTL_VALID))
 503                 return;
 504
 505         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 506         ns = timecounter_cyc2time(&adapter->tc, regval);
 507         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 508
 509         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 510         shhwtstamps.hwtstamp = ns_to_ktime(ns);
 511         skb_tstamp_tx(skb, &shhwtstamps);
 512 }
 513
 514 /**
 515  * ixgbe_ptp_rx_hwtstamp - utility function which checks for RX time stamp
 516  * @q_vector: structure containing interrupt and ring information
 517  * @rx_desc: the rx descriptor
 518  * @skb: particular skb to send timestamp with
 519  *
 520  * if the timestamp is valid, we convert it into the timecounter ns
 521  * value, then store that result into the shhwtstamps structure which
 522  * is passed up the network stack
 523  */
 524 void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring,
 525                            union ixgbe_adv_rx_desc *rx_desc,
 526                            struct sk_buff *skb)
 527 {
 528         struct ixgbe_adapter *adapter;
 529         struct ixgbe_hw *hw;
 530         struct skb_shared_hwtstamps *shhwtstamps;
 531         u64 regval = 0, ns;
 532         u32 tsyncrxctl;
 533         unsigned long flags;
 534
 535         /* we cannot process timestamps on a ring without a q_vector */
 536         if (!rx_ring->q_vector || !rx_ring->q_vector->adapter)
 537                 return;
 538
 539         adapter = rx_ring->q_vector->adapter;
 540         hw = &adapter->hw;
 541
 542         if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
 543                 return;
 544
 545         /*
 546          * Read the tsyncrxctl register afterwards in order to prevent taking an
 547          * I/O hit on every packet.
 548          */
 549         tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
 550         if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID))
 551                 return;
 552
 553         /*
 554          * Update the last_rx_timestamp timer in order to enable watchdog check
 555          * for error case of latched timestamp on a dropped packet.
 556          */
 557         rx_ring->last_rx_timestamp = jiffies;
 558
 559         regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
 560         regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
 561
 562
 563         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 564         ns = timecounter_cyc2time(&adapter->tc, regval);
 565         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 566
 567         shhwtstamps = skb_hwtstamps(skb);
 568         shhwtstamps->hwtstamp = ns_to_ktime(ns);
 569 }
 570
 571 /**
 572  * ixgbe_ptp_hwtstamp_ioctl - control hardware time stamping
 573  * @adapter: pointer to adapter struct
 574  * @ifreq: ioctl data
 575  * @cmd: particular ioctl requested
 576  *
 577  * Outgoing time stamping can be enabled and disabled. Play nice and
 578  * disable it when requested, although it shouldn't case any overhead
 579  * when no packet needs it. At most one packet in the queue may be
 580  * marked for time stamping, otherwise it would be impossible to tell
 581  * for sure to which packet the hardware time stamp belongs.
 582  *
 583  * Incoming time stamping has to be configured via the hardware
 584  * filters. Not all combinations are supported, in particular event
 585  * type has to be specified. Matching the kind of event packet is
 586  * not supported, with the exception of "all V2 events regardless of
 587  * level 2 or 4".
 588  *
 589  * Since hardware always timestamps Path delay packets when timestamping V2
 590  * packets, regardless of the type specified in the register, only use V2
 591  * Event mode. This more accurately tells the user what the hardware is going
 592  * to do anyways.
 593  */
 594 int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter,
 595                              struct ifreq *ifr, int cmd)
 596 {
 597         struct ixgbe_hw *hw = &adapter->hw;
 598         struct hwtstamp_config config;
 599         u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
 600         u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
 601         u32 tsync_rx_mtrl = PTP_EV_PORT << 16;
 602         bool is_l2 = false;
 603         u32 regval;
 604
 605         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 606                 return -EFAULT;
 607
 608         /* reserved for future extensions */
 609         if (config.flags)
 610                 return -EINVAL;
 611
 612         switch (config.tx_type) {
 613         case HWTSTAMP_TX_OFF:
 614                 tsync_tx_ctl = 0;
 615         case HWTSTAMP_TX_ON:
 616                 break;
 617         default:
 618                 return -ERANGE;
 619         }
 620
 621         switch (config.rx_filter) {
 622         case HWTSTAMP_FILTER_NONE:
 623                 tsync_rx_ctl = 0;
 624                 tsync_rx_mtrl = 0;
 625                 break;
 626         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 627                 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
 628                 tsync_rx_mtrl = IXGBE_RXMTRL_V1_SYNC_MSG;
 629                 break;
 630         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 631                 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
 632                 tsync_rx_mtrl = IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
 633                 break;
 634         case HWTSTAMP_FILTER_PTP_V2_EVENT:
 635         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 636         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 637         case HWTSTAMP_FILTER_PTP_V2_SYNC:
 638         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
 639         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 640         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 641         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
 642         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 643                 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
 644                 is_l2 = true;
 645                 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 646                 break;
 647         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 648         case HWTSTAMP_FILTER_ALL:
 649         default:
 650                 /*
 651                  * register RXMTRL must be set in order to do V1 packets,
 652                  * therefore it is not possible to time stamp both V1 Sync and
 653                  * Delay_Req messages and hardware does not support
 654                  * timestamping all packets => return error
 655                  */
 656                 config.rx_filter = HWTSTAMP_FILTER_NONE;
 657                 return -ERANGE;
 658         }
 659
 660         if (hw->mac.type == ixgbe_mac_82598EB) {
 661                 if (tsync_rx_ctl | tsync_tx_ctl)
 662                         return -ERANGE;
 663                 return 0;
 664         }
 665
 666         /* define ethertype filter for timestamping L2 packets */
 667         if (is_l2)
 668                 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
 669                                 (IXGBE_ETQF_FILTER_EN | /* enable filter */
 670                                  IXGBE_ETQF_1588 | /* enable timestamping */
 671                                  ETH_P_1588));     /* 1588 eth protocol type */
 672         else
 673                 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
 674
 675
 676         /* enable/disable TX */
 677         regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
 678         regval &= ~IXGBE_TSYNCTXCTL_ENABLED;
 679         regval |= tsync_tx_ctl;
 680         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);
 681
 682         /* enable/disable RX */
 683         regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
 684         regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);
 685         regval |= tsync_rx_ctl;
 686         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);
 687
 688         /* define which PTP packets are time stamped */
 689         IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl);
 690
 691         IXGBE_WRITE_FLUSH(hw);
 692
 693         /* clear TX/RX time stamp registers, just to be sure */
 694         regval = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
 695         regval = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
 696
 697         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 698                 -EFAULT : 0;
 699 }
 700
 701 /**
 702  * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw
 703  * @adapter: pointer to the adapter structure
 704  *
 705  * This function should be called to set the proper values for the TIMINCA
 706  * register and tell the cyclecounter structure what the tick rate of SYSTIME
 707  * is. It does not directly modify SYSTIME registers or the timecounter
 708  * structure. It should be called whenever a new TIMINCA value is necessary,
 709  * such as during initialization or when the link speed changes.
 710  */
 711 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
 712 {
 713         struct ixgbe_hw *hw = &adapter->hw;
 714         u32 incval = 0;
 715         u32 shift = 0;
 716         unsigned long flags;
 717
 718         /**
 719          * Scale the NIC cycle counter by a large factor so that
 720          * relatively small corrections to the frequency can be added
 721          * or subtracted. The drawbacks of a large factor include
 722          * (a) the clock register overflows more quickly, (b) the cycle
 723          * counter structure must be able to convert the systime value
 724          * to nanoseconds using only a multiplier and a right-shift,
 725          * and (c) the value must fit within the timinca register space
 726          * => math based on internal DMA clock rate and available bits
 727          *
 728          * Note that when there is no link, internal DMA clock is same as when
 729          * link speed is 10Gb. Set the registers correctly even when link is
 730          * down to preserve the clock setting
 731          */
 732         switch (adapter->link_speed) {
 733         case IXGBE_LINK_SPEED_100_FULL:
 734                 incval = IXGBE_INCVAL_100;
 735                 shift = IXGBE_INCVAL_SHIFT_100;
 736                 break;
 737         case IXGBE_LINK_SPEED_1GB_FULL:
 738                 incval = IXGBE_INCVAL_1GB;
 739                 shift = IXGBE_INCVAL_SHIFT_1GB;
 740                 break;
 741         case IXGBE_LINK_SPEED_10GB_FULL:
 742         default:
 743                 incval = IXGBE_INCVAL_10GB;
 744                 shift = IXGBE_INCVAL_SHIFT_10GB;
 745                 break;
 746         }
 747
 748         /**
 749          * Modify the calculated values to fit within the correct
 750          * number of bits specified by the hardware. The 82599 doesn't
 751          * have the same space as the X540, so bitshift the calculated
 752          * values to fit.
 753          */
 754         switch (hw->mac.type) {
 755         case ixgbe_mac_X540:
 756                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
 757                 break;
 758         case ixgbe_mac_82599EB:
 759                 incval >>= IXGBE_INCVAL_SHIFT_82599;
 760                 shift -= IXGBE_INCVAL_SHIFT_82599;
 761                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
 762                                 (1 << IXGBE_INCPER_SHIFT_82599) |
 763                                 incval);
 764                 break;
 765         default:
 766                 /* other devices aren't supported */
 767                 return;
 768         }
 769
 770         /* update the base incval used to calculate frequency adjustment */
 771         ACCESS_ONCE(adapter->base_incval) = incval;
 772         smp_mb();
 773
 774         /* need lock to prevent incorrect read while modifying cyclecounter */
 775         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 776
 777         memset(&adapter->cc, 0, sizeof(adapter->cc));
 778         adapter->cc.read = ixgbe_ptp_read;
 779         adapter->cc.mask = CLOCKSOURCE_MASK(64);
 780         adapter->cc.shift = shift;
 781         adapter->cc.mult = 1;
 782
 783         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 784 }
 785
 786 /**
 787  * ixgbe_ptp_reset
 788  * @adapter: the ixgbe private board structure
 789  *
 790  * When the MAC resets, all timesync features are reset. This function should be
 791  * called to re-enable the PTP clock structure. It will re-init the timecounter
 792  * structure based on the kernel time as well as setup the cycle counter data.
 793  */
 794 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter)
 795 {
 796         struct ixgbe_hw *hw = &adapter->hw;
 797         unsigned long flags;
 798
 799         /* set SYSTIME registers to 0 just in case */
 800         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x00000000);
 801         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x00000000);
 802         IXGBE_WRITE_FLUSH(hw);
 803
 804         ixgbe_ptp_start_cyclecounter(adapter);
 805
 806         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 807
 808         /* reset the ns time counter */
 809         timecounter_init(&adapter->tc, &adapter->cc,
 810                          ktime_to_ns(ktime_get_real()));
 811
 812         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 813
 814         /*
 815          * Now that the shift has been calculated and the systime
 816          * registers reset, (re-)enable the Clock out feature
 817          */
 818         ixgbe_ptp_setup_sdp(adapter);
 819 }
 820
 821 /**
 822  * ixgbe_ptp_init
 823  * @adapter: the ixgbe private adapter structure
 824  *
 825  * This function performs the required steps for enabling ptp
 826  * support. If ptp support has already been loaded it simply calls the
 827  * cyclecounter init routine and exits.
 828  */
 829 void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
 830 {
 831         struct net_device *netdev = adapter->netdev;
 832
 833         switch (adapter->hw.mac.type) {
 834         case ixgbe_mac_X540:
 835                 snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name);
 836                 adapter->ptp_caps.owner = THIS_MODULE;
 837                 adapter->ptp_caps.max_adj = 250000000;
 838                 adapter->ptp_caps.n_alarm = 0;
 839                 adapter->ptp_caps.n_ext_ts = 0;
 840                 adapter->ptp_caps.n_per_out = 0;
 841                 adapter->ptp_caps.pps = 1;
 842                 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
 843                 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
 844                 adapter->ptp_caps.gettime = ixgbe_ptp_gettime;
 845                 adapter->ptp_caps.settime = ixgbe_ptp_settime;
 846                 adapter->ptp_caps.enable = ixgbe_ptp_enable;
 847                 break;
 848         case ixgbe_mac_82599EB:
 849                 snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name);
 850                 adapter->ptp_caps.owner = THIS_MODULE;
 851                 adapter->ptp_caps.max_adj = 250000000;
 852                 adapter->ptp_caps.n_alarm = 0;
 853                 adapter->ptp_caps.n_ext_ts = 0;
 854                 adapter->ptp_caps.n_per_out = 0;
 855                 adapter->ptp_caps.pps = 0;
 856                 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
 857                 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
 858                 adapter->ptp_caps.gettime = ixgbe_ptp_gettime;
 859                 adapter->ptp_caps.settime = ixgbe_ptp_settime;
 860                 adapter->ptp_caps.enable = ixgbe_ptp_enable;
 861                 break;
 862         default:
 863                 adapter->ptp_clock = NULL;
 864                 return;
 865         }
 866
 867         spin_lock_init(&adapter->tmreg_lock);
 868
 869         adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
 870                                                 &adapter->pdev->dev);
 871         if (IS_ERR(adapter->ptp_clock)) {
 872                 adapter->ptp_clock = NULL;
 873                 e_dev_err("ptp_clock_register failed\n");
 874         } else
 875                 e_dev_info("registered PHC device on %s\n", netdev->name);
 876
 877         ixgbe_ptp_reset(adapter);
 878
 879         /* set the flag that PTP has been enabled */
 880         adapter->flags2 |= IXGBE_FLAG2_PTP_ENABLED;
 881
 882         return;
 883 }
 884
 885 /**
 886  * ixgbe_ptp_stop - disable ptp device and stop the overflow check
 887  * @adapter: pointer to adapter struct
 888  *
 889  * this function stops the ptp support, and cancels the delayed work.
 890  */
 891 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
 892 {
 893         /* stop the overflow check task */
 894         adapter->flags2 &= ~(IXGBE_FLAG2_PTP_ENABLED |
 895                              IXGBE_FLAG2_PTP_PPS_ENABLED);
 896
 897         ixgbe_ptp_setup_sdp(adapter);
 898
 899         if (adapter->ptp_clock) {
 900                 ptp_clock_unregister(adapter->ptp_clock);
 901                 adapter->ptp_clock = NULL;
 902                 e_dev_info("removed PHC on %s\n",
 903                            adapter->netdev->name);
 904         }
 905 }