1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/export.h>
31 * The 82599 and the X540 do not have true 64bit nanosecond scale
32 * counter registers. Instead, SYSTIME is defined by a fixed point
33 * system which allows the user to define the scale counter increment
34 * value at every level change of the oscillator driving the SYSTIME
35 * value. For both devices the TIMINCA:IV field defines this
36 * increment. On the X540 device, 31 bits are provided. However on the
37 * 82599 only provides 24 bits. The time unit is determined by the
38 * clock frequency of the oscillator in combination with the TIMINCA
39 * register. When these devices link at 10Gb the oscillator has a
40 * period of 6.4ns. In order to convert the scale counter into
41 * nanoseconds the cyclecounter and timecounter structures are
42 * used. The SYSTIME registers need to be converted to ns values by use
43 * of only a right shift (division by power of 2). The following math
44 * determines the largest incvalue that will fit into the available
45 * bits in the TIMINCA register.
47 * PeriodWidth: Number of bits to store the clock period
48 * MaxWidth: The maximum width value of the TIMINCA register
49 * Period: The clock period for the oscillator
50 * round(): discard the fractional portion of the calculation
52 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
54 * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns
55 * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns
57 * The period also changes based on the link speed:
58 * At 10Gb link or no link, the period remains the same.
59 * At 1Gb link, the period is multiplied by 10. (64ns)
60 * At 100Mb link, the period is multiplied by 100. (640ns)
62 * The calculated value allows us to right shift the SYSTIME register
63 * value in order to quickly convert it into a nanosecond clock,
64 * while allowing for the maximum possible adjustment value.
66 * These diagrams are only for the 10Gb link period
69 * +--------------+ +--------------+
70 * X540 | 32 | | 1 | 3 | 28 |
71 * *--------------+ +--------------+
72 * \________ 36 bits ______/ fract
74 * +--------------+ +--------------+
75 * 82599 | 32 | | 8 | 3 | 21 |
76 * *--------------+ +--------------+
77 * \________ 43 bits ______/ fract
79 * The 36 bit X540 SYSTIME overflows every
80 * 2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
82 * The 43 bit 82599 SYSTIME overflows every
83 * 2^43 * 10^-9 / 3600 = 2.4 hours
85 #define IXGBE_INCVAL_10GB 0x66666666
86 #define IXGBE_INCVAL_1GB 0x40000000
87 #define IXGBE_INCVAL_100 0x50000000
89 #define IXGBE_INCVAL_SHIFT_10GB 28
90 #define IXGBE_INCVAL_SHIFT_1GB 24
91 #define IXGBE_INCVAL_SHIFT_100 21
93 #define IXGBE_INCVAL_SHIFT_82599 7
94 #define IXGBE_INCPER_SHIFT_82599 24
95 #define IXGBE_MAX_TIMEADJ_VALUE 0x7FFFFFFFFFFFFFFFULL
97 #define IXGBE_OVERFLOW_PERIOD (HZ * 30)
100 #define NSECS_PER_SEC 1000000000ULL
104 * ixgbe_ptp_read - read raw cycle counter (to be used by time counter)
105 * @cc - the cyclecounter structure
107 * this function reads the cyclecounter registers and is called by the
108 * cyclecounter structure used to construct a ns counter from the
109 * arbitrary fixed point registers
111 static cycle_t
ixgbe_ptp_read(const struct cyclecounter
*cc
)
113 struct ixgbe_adapter
*adapter
=
114 container_of(cc
, struct ixgbe_adapter
, cc
);
115 struct ixgbe_hw
*hw
= &adapter
->hw
;
118 stamp
|= (u64
)IXGBE_READ_REG(hw
, IXGBE_SYSTIML
);
119 stamp
|= (u64
)IXGBE_READ_REG(hw
, IXGBE_SYSTIMH
) << 32;
126 * @ptp - the ptp clock structure
127 * @ppb - parts per billion adjustment from base
129 * adjust the frequency of the ptp cycle counter by the
130 * indicated ppb from the base frequency.
132 static int ixgbe_ptp_adjfreq(struct ptp_clock_info
*ptp
, s32 ppb
)
134 struct ixgbe_adapter
*adapter
=
135 container_of(ptp
, struct ixgbe_adapter
, ptp_caps
);
136 struct ixgbe_hw
*hw
= &adapter
->hw
;
147 incval
= ACCESS_ONCE(adapter
->base_incval
);
151 diff
= div_u64(freq
, 1000000000ULL);
153 incval
= neg_adj
? (incval
- diff
) : (incval
+ diff
);
155 switch (hw
->mac
.type
) {
157 IXGBE_WRITE_REG(hw
, IXGBE_TIMINCA
, incval
);
159 case ixgbe_mac_82599EB
:
160 IXGBE_WRITE_REG(hw
, IXGBE_TIMINCA
,
161 (1 << IXGBE_INCPER_SHIFT_82599
) |
173 * @ptp - the ptp clock structure
174 * @delta - offset to adjust the cycle counter by
176 * adjust the timer by resetting the timecounter structure.
178 static int ixgbe_ptp_adjtime(struct ptp_clock_info
*ptp
, s64 delta
)
180 struct ixgbe_adapter
*adapter
=
181 container_of(ptp
, struct ixgbe_adapter
, ptp_caps
);
185 spin_lock_irqsave(&adapter
->tmreg_lock
, flags
);
187 now
= timecounter_read(&adapter
->tc
);
190 /* reset the timecounter */
191 timecounter_init(&adapter
->tc
,
195 spin_unlock_irqrestore(&adapter
->tmreg_lock
, flags
);
201 * @ptp - the ptp clock structure
202 * @ts - timespec structure to hold the current time value
204 * read the timecounter and return the correct value on ns,
205 * after converting it into a struct timespec.
207 static int ixgbe_ptp_gettime(struct ptp_clock_info
*ptp
, struct timespec
*ts
)
209 struct ixgbe_adapter
*adapter
=
210 container_of(ptp
, struct ixgbe_adapter
, ptp_caps
);
215 spin_lock_irqsave(&adapter
->tmreg_lock
, flags
);
216 ns
= timecounter_read(&adapter
->tc
);
217 spin_unlock_irqrestore(&adapter
->tmreg_lock
, flags
);
219 ts
->tv_sec
= div_u64_rem(ns
, 1000000000ULL, &remainder
);
220 ts
->tv_nsec
= remainder
;
227 * @ptp - the ptp clock structure
228 * @ts - the timespec containing the new time for the cycle counter
230 * reset the timecounter to use a new base value instead of the kernel
233 static int ixgbe_ptp_settime(struct ptp_clock_info
*ptp
,
234 const struct timespec
*ts
)
236 struct ixgbe_adapter
*adapter
=
237 container_of(ptp
, struct ixgbe_adapter
, ptp_caps
);
241 ns
= ts
->tv_sec
* 1000000000ULL;
244 /* reset the timecounter */
245 spin_lock_irqsave(&adapter
->tmreg_lock
, flags
);
246 timecounter_init(&adapter
->tc
, &adapter
->cc
, ns
);
247 spin_unlock_irqrestore(&adapter
->tmreg_lock
, flags
);
254 * @ptp - the ptp clock structure
255 * @rq - the requested feature to change
256 * @on - whether to enable or disable the feature
258 * enable (or disable) ancillary features of the phc subsystem.
259 * our driver only supports the PPS feature on the X540
261 static int ixgbe_ptp_enable(struct ptp_clock_info
*ptp
,
262 struct ptp_clock_request
*rq
, int on
)
264 struct ixgbe_adapter
*adapter
=
265 container_of(ptp
, struct ixgbe_adapter
, ptp_caps
);
268 * When PPS is enabled, unmask the interrupt for the ClockOut
269 * feature, so that the interrupt handler can send the PPS
270 * event when the clock SDP triggers. Clear mask when PPS is
273 if (rq
->type
== PTP_CLK_REQ_PPS
) {
274 switch (adapter
->hw
.mac
.type
) {
277 adapter
->flags2
|= IXGBE_FLAG2_PTP_PPS_ENABLED
;
280 ~IXGBE_FLAG2_PTP_PPS_ENABLED
;
291 * ixgbe_ptp_check_pps_event
292 * @adapter - the private adapter structure
293 * @eicr - the interrupt cause register value
295 * This function is called by the interrupt routine when checking for
296 * interrupts. It will check and handle a pps event.
298 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
300 struct ixgbe_hw
*hw
= &adapter
->hw
;
301 struct ptp_clock_event event
;
303 event
.type
= PTP_CLOCK_PPS
;
305 /* Make sure ptp clock is valid, and PPS event enabled */
306 if (!adapter
->ptp_clock
||
307 !(adapter
->flags2
& IXGBE_FLAG2_PTP_PPS_ENABLED
))
310 switch (hw
->mac
.type
) {
312 if (eicr
& IXGBE_EICR_TIMESYNC
)
313 ptp_clock_event(adapter
->ptp_clock
, &event
);
321 * ixgbe_ptp_enable_sdp
322 * @hw - the hardware private structure
323 * @shift - the clock shift for calculating nanoseconds
325 * this function enables the clock out feature on the sdp0 for the
326 * X540 device. It will create a 1second periodic output that can be
327 * used as the PPS (via an interrupt).
329 * It calculates when the systime will be on an exact second, and then
330 * aligns the start of the PPS signal to that value. The shift is
331 * necessary because it can change based on the link speed.
333 static void ixgbe_ptp_enable_sdp(struct ixgbe_hw
*hw
, int shift
)
335 u32 esdp
, tsauxc
, clktiml
, clktimh
, trgttiml
, trgttimh
;
339 switch (hw
->mac
.type
) {
341 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
344 * enable the SDP0 pin as output, and connected to the native
345 * function for Timesync (ClockOut)
347 esdp
|= (IXGBE_ESDP_SDP0_DIR
|
348 IXGBE_ESDP_SDP0_NATIVE
);
351 * enable the Clock Out feature on SDP0, and allow interrupts
352 * to occur when the pin changes
354 tsauxc
= (IXGBE_TSAUXC_EN_CLK
|
355 IXGBE_TSAUXC_SYNCLK
|
356 IXGBE_TSAUXC_SDP0_INT
);
358 /* clock period (or pulse length) */
359 clktiml
= (u32
)(NSECS_PER_SEC
<< shift
);
360 clktimh
= (u32
)((NSECS_PER_SEC
<< shift
) >> 32);
362 clock_edge
|= (u64
)IXGBE_READ_REG(hw
, IXGBE_SYSTIML
);
363 clock_edge
|= (u64
)IXGBE_READ_REG(hw
, IXGBE_SYSTIMH
) << 32;
366 * account for the fact that we can't do u64 division
367 * with remainder, by converting the clock values into
370 clock_edge
>>= shift
;
371 div_u64_rem(clock_edge
, NSECS_PER_SEC
, &rem
);
372 clock_edge
+= (NSECS_PER_SEC
- rem
);
373 clock_edge
<<= shift
;
375 /* specify the initial clock start time */
376 trgttiml
= (u32
)clock_edge
;
377 trgttimh
= (u32
)(clock_edge
>> 32);
379 IXGBE_WRITE_REG(hw
, IXGBE_CLKTIML
, clktiml
);
380 IXGBE_WRITE_REG(hw
, IXGBE_CLKTIMH
, clktimh
);
381 IXGBE_WRITE_REG(hw
, IXGBE_TRGTTIML0
, trgttiml
);
382 IXGBE_WRITE_REG(hw
, IXGBE_TRGTTIMH0
, trgttimh
);
384 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp
);
385 IXGBE_WRITE_REG(hw
, IXGBE_TSAUXC
, tsauxc
);
387 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EICR_TIMESYNC
);
395 * ixgbe_ptp_disable_sdp
396 * @hw - the private hardware structure
398 * this function disables the auxiliary SDP clock out feature
400 static void ixgbe_ptp_disable_sdp(struct ixgbe_hw
*hw
)
402 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EICR_TIMESYNC
);
403 IXGBE_WRITE_REG(hw
, IXGBE_TSAUXC
, 0);
407 * ixgbe_ptp_overflow_check - delayed work to detect SYSTIME overflow
408 * @work: structure containing information about this work task
410 * this work function is scheduled to continue reading the timecounter
411 * in order to prevent missing when the system time registers wrap
412 * around. This needs to be run approximately twice a minute when no
413 * PTP activity is occurring.
415 void ixgbe_ptp_overflow_check(struct ixgbe_adapter
*adapter
)
417 unsigned long elapsed_jiffies
= adapter
->last_overflow_check
- jiffies
;
420 if ((adapter
->flags2
& IXGBE_FLAG2_OVERFLOW_CHECK_ENABLED
) &&
421 (elapsed_jiffies
>= IXGBE_OVERFLOW_PERIOD
)) {
422 ixgbe_ptp_gettime(&adapter
->ptp_caps
, &ts
);
423 adapter
->last_overflow_check
= jiffies
;
428 * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp
429 * @q_vector: structure containing interrupt and ring information
430 * @skb: particular skb to send timestamp with
432 * if the timestamp is valid, we convert it into the timecounter ns
433 * value, then store that result into the shhwtstamps structure which
434 * is passed up the network stack
436 void ixgbe_ptp_tx_hwtstamp(struct ixgbe_q_vector
*q_vector
,
439 struct ixgbe_adapter
*adapter
;
441 struct skb_shared_hwtstamps shhwtstamps
;
446 /* we cannot process timestamps on a ring without a q_vector */
447 if (!q_vector
|| !q_vector
->adapter
)
450 adapter
= q_vector
->adapter
;
453 tsynctxctl
= IXGBE_READ_REG(hw
, IXGBE_TSYNCTXCTL
);
454 regval
|= (u64
)IXGBE_READ_REG(hw
, IXGBE_TXSTMPL
);
455 regval
|= (u64
)IXGBE_READ_REG(hw
, IXGBE_TXSTMPH
) << 32;
458 * if TX timestamp is not valid, exit after clearing the
459 * timestamp registers
461 if (!(tsynctxctl
& IXGBE_TSYNCTXCTL_VALID
))
464 spin_lock_irqsave(&adapter
->tmreg_lock
, flags
);
465 ns
= timecounter_cyc2time(&adapter
->tc
, regval
);
466 spin_unlock_irqrestore(&adapter
->tmreg_lock
, flags
);
468 memset(&shhwtstamps
, 0, sizeof(shhwtstamps
));
469 shhwtstamps
.hwtstamp
= ns_to_ktime(ns
);
470 skb_tstamp_tx(skb
, &shhwtstamps
);
474 * ixgbe_ptp_rx_hwtstamp - utility function which checks for RX time stamp
475 * @q_vector: structure containing interrupt and ring information
476 * @skb: particular skb to send timestamp with
478 * if the timestamp is valid, we convert it into the timecounter ns
479 * value, then store that result into the shhwtstamps structure which
480 * is passed up the network stack
482 void ixgbe_ptp_rx_hwtstamp(struct ixgbe_q_vector
*q_vector
,
485 struct ixgbe_adapter
*adapter
;
487 struct skb_shared_hwtstamps
*shhwtstamps
;
492 /* we cannot process timestamps on a ring without a q_vector */
493 if (!q_vector
|| !q_vector
->adapter
)
496 adapter
= q_vector
->adapter
;
499 tsyncrxctl
= IXGBE_READ_REG(hw
, IXGBE_TSYNCRXCTL
);
500 regval
|= (u64
)IXGBE_READ_REG(hw
, IXGBE_RXSTMPL
);
501 regval
|= (u64
)IXGBE_READ_REG(hw
, IXGBE_RXSTMPH
) << 32;
504 * If this bit is set, then the RX registers contain the time stamp. No
505 * other packet will be time stamped until we read these registers, so
506 * read the registers to make them available again. Because only one
507 * packet can be time stamped at a time, we know that the register
508 * values must belong to this one here and therefore we don't need to
509 * compare any of the additional attributes stored for it.
511 * If nothing went wrong, then it should have a skb_shared_tx that we
512 * can turn into a skb_shared_hwtstamps.
514 if (!(tsyncrxctl
& IXGBE_TSYNCRXCTL_VALID
))
517 spin_lock_irqsave(&adapter
->tmreg_lock
, flags
);
518 ns
= timecounter_cyc2time(&adapter
->tc
, regval
);
519 spin_unlock_irqrestore(&adapter
->tmreg_lock
, flags
);
521 shhwtstamps
= skb_hwtstamps(skb
);
522 shhwtstamps
->hwtstamp
= ns_to_ktime(ns
);
526 * ixgbe_ptp_hwtstamp_ioctl - control hardware time stamping
527 * @adapter: pointer to adapter struct
529 * @cmd: particular ioctl requested
531 * Outgoing time stamping can be enabled and disabled. Play nice and
532 * disable it when requested, although it shouldn't case any overhead
533 * when no packet needs it. At most one packet in the queue may be
534 * marked for time stamping, otherwise it would be impossible to tell
535 * for sure to which packet the hardware time stamp belongs.
537 * Incoming time stamping has to be configured via the hardware
538 * filters. Not all combinations are supported, in particular event
539 * type has to be specified. Matching the kind of event packet is
540 * not supported, with the exception of "all V2 events regardless of
543 int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter
*adapter
,
544 struct ifreq
*ifr
, int cmd
)
546 struct ixgbe_hw
*hw
= &adapter
->hw
;
547 struct hwtstamp_config config
;
548 u32 tsync_tx_ctl
= IXGBE_TSYNCTXCTL_ENABLED
;
549 u32 tsync_rx_ctl
= IXGBE_TSYNCRXCTL_ENABLED
;
550 u32 tsync_rx_mtrl
= 0;
555 if (copy_from_user(&config
, ifr
->ifr_data
, sizeof(config
)))
558 /* reserved for future extensions */
562 switch (config
.tx_type
) {
563 case HWTSTAMP_TX_OFF
:
571 switch (config
.rx_filter
) {
572 case HWTSTAMP_FILTER_NONE
:
575 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
576 tsync_rx_ctl
|= IXGBE_TSYNCRXCTL_TYPE_L4_V1
;
577 tsync_rx_mtrl
= IXGBE_RXMTRL_V1_SYNC_MSG
;
580 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
581 tsync_rx_ctl
|= IXGBE_TSYNCRXCTL_TYPE_L4_V1
;
582 tsync_rx_mtrl
= IXGBE_RXMTRL_V1_DELAY_REQ_MSG
;
585 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
586 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
587 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
588 tsync_rx_ctl
|= IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2
;
589 tsync_rx_mtrl
= IXGBE_RXMTRL_V2_SYNC_MSG
;
592 config
.rx_filter
= HWTSTAMP_FILTER_SOME
;
594 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
595 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
596 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
597 tsync_rx_ctl
|= IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2
;
598 tsync_rx_mtrl
= IXGBE_RXMTRL_V2_DELAY_REQ_MSG
;
601 config
.rx_filter
= HWTSTAMP_FILTER_SOME
;
603 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
604 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
605 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
606 tsync_rx_ctl
|= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2
;
607 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
611 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
612 case HWTSTAMP_FILTER_ALL
:
615 * register RXMTRL must be set, therefore it is not
616 * possible to time stamp both V1 Sync and Delay_Req messages
617 * and hardware does not support timestamping all packets
623 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
624 if (tsync_rx_ctl
| tsync_tx_ctl
)
629 /* define ethertype filter for timestamped packets */
631 IXGBE_WRITE_REG(hw
, IXGBE_ETQF(3),
632 (IXGBE_ETQF_FILTER_EN
| /* enable filter */
633 IXGBE_ETQF_1588
| /* enable timestamping */
634 ETH_P_1588
)); /* 1588 eth protocol type */
636 IXGBE_WRITE_REG(hw
, IXGBE_ETQF(3), 0);
639 /* L4 Queue Filter[3]: filter by destination port and protocol */
641 u32 ftqf
= (IXGBE_FTQF_PROTOCOL_UDP
/* UDP */
642 | IXGBE_FTQF_POOL_MASK_EN
/* Pool not compared */
643 | IXGBE_FTQF_QUEUE_ENABLE
);
645 ftqf
|= ((IXGBE_FTQF_PROTOCOL_COMP_MASK
/* protocol check */
646 & IXGBE_FTQF_DEST_PORT_MASK
/* dest check */
647 & IXGBE_FTQF_SOURCE_PORT_MASK
) /* source check */
648 << IXGBE_FTQF_5TUPLE_MASK_SHIFT
);
650 IXGBE_WRITE_REG(hw
, IXGBE_L34T_IMIR(3),
651 (3 << IXGBE_IMIR_RX_QUEUE_SHIFT_82599
|
652 IXGBE_IMIR_SIZE_BP_82599
));
654 /* enable port check */
655 IXGBE_WRITE_REG(hw
, IXGBE_SDPQF(3),
657 htons(PTP_PORT
) << 16));
659 IXGBE_WRITE_REG(hw
, IXGBE_FTQF(3), ftqf
);
661 tsync_rx_mtrl
|= PTP_PORT
<< 16;
663 IXGBE_WRITE_REG(hw
, IXGBE_FTQF(3), 0);
666 /* enable/disable TX */
667 regval
= IXGBE_READ_REG(hw
, IXGBE_TSYNCTXCTL
);
668 regval
&= ~IXGBE_TSYNCTXCTL_ENABLED
;
669 regval
|= tsync_tx_ctl
;
670 IXGBE_WRITE_REG(hw
, IXGBE_TSYNCTXCTL
, regval
);
672 /* enable/disable RX */
673 regval
= IXGBE_READ_REG(hw
, IXGBE_TSYNCRXCTL
);
674 regval
&= ~(IXGBE_TSYNCRXCTL_ENABLED
| IXGBE_TSYNCRXCTL_TYPE_MASK
);
675 regval
|= tsync_rx_ctl
;
676 IXGBE_WRITE_REG(hw
, IXGBE_TSYNCRXCTL
, regval
);
678 /* define which PTP packets are time stamped */
679 IXGBE_WRITE_REG(hw
, IXGBE_RXMTRL
, tsync_rx_mtrl
);
681 IXGBE_WRITE_FLUSH(hw
);
683 /* clear TX/RX time stamp registers, just to be sure */
684 regval
= IXGBE_READ_REG(hw
, IXGBE_TXSTMPH
);
685 regval
= IXGBE_READ_REG(hw
, IXGBE_RXSTMPH
);
687 return copy_to_user(ifr
->ifr_data
, &config
, sizeof(config
)) ?
692 * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw
693 * @adapter - pointer to the adapter structure
695 * this function initializes the timecounter and cyclecounter
696 * structures for use in generated a ns counter from the arbitrary
697 * fixed point cycles registers in the hardware.
699 * A change in link speed impacts the frequency of the DMA clock on
700 * the device, which is used to generate the cycle counter
701 * registers. Therefor this function is called whenever the link speed
704 * This function also turns on the SDP pin for clock out feature (X540
705 * only), because this is where the shift is first calculated.
707 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter
*adapter
)
709 struct ixgbe_hw
*hw
= &adapter
->hw
;
717 * Determine what speed we need to set the cyclecounter
718 * for. It should be different for 100Mb, 1Gb, and 10Gb. Treat
719 * unknown speeds as 10Gb. (Hence why we can't just copy the
722 switch (adapter
->link_speed
) {
723 case IXGBE_LINK_SPEED_100_FULL
:
724 case IXGBE_LINK_SPEED_1GB_FULL
:
725 case IXGBE_LINK_SPEED_10GB_FULL
:
726 cycle_speed
= adapter
->link_speed
;
729 /* cycle speed should be 10Gb when there is no link */
730 cycle_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
735 * grab the current TIMINCA value from the register so that it can be
736 * double checked. If the register value has been cleared, it must be
737 * reset to the correct value for generating a cyclecounter. If
738 * TIMINCA is zero, the SYSTIME registers do not increment at all.
740 timinca
= IXGBE_READ_REG(hw
, IXGBE_TIMINCA
);
742 /* Bail if the cycle speed didn't change and TIMINCA is non-zero */
743 if (adapter
->cycle_speed
== cycle_speed
&& timinca
)
746 /* disable the SDP clock out */
747 ixgbe_ptp_disable_sdp(hw
);
750 * Scale the NIC cycle counter by a large factor so that
751 * relatively small corrections to the frequency can be added
752 * or subtracted. The drawbacks of a large factor include
753 * (a) the clock register overflows more quickly, (b) the cycle
754 * counter structure must be able to convert the systime value
755 * to nanoseconds using only a multiplier and a right-shift,
756 * and (c) the value must fit within the timinca register space
757 * => math based on internal DMA clock rate and available bits
759 switch (cycle_speed
) {
760 case IXGBE_LINK_SPEED_100_FULL
:
761 incval
= IXGBE_INCVAL_100
;
762 shift
= IXGBE_INCVAL_SHIFT_100
;
764 case IXGBE_LINK_SPEED_1GB_FULL
:
765 incval
= IXGBE_INCVAL_1GB
;
766 shift
= IXGBE_INCVAL_SHIFT_1GB
;
768 case IXGBE_LINK_SPEED_10GB_FULL
:
769 incval
= IXGBE_INCVAL_10GB
;
770 shift
= IXGBE_INCVAL_SHIFT_10GB
;
775 * Modify the calculated values to fit within the correct
776 * number of bits specified by the hardware. The 82599 doesn't
777 * have the same space as the X540, so bitshift the calculated
780 switch (hw
->mac
.type
) {
782 IXGBE_WRITE_REG(hw
, IXGBE_TIMINCA
, incval
);
784 case ixgbe_mac_82599EB
:
785 incval
>>= IXGBE_INCVAL_SHIFT_82599
;
786 shift
-= IXGBE_INCVAL_SHIFT_82599
;
787 IXGBE_WRITE_REG(hw
, IXGBE_TIMINCA
,
788 (1 << IXGBE_INCPER_SHIFT_82599
) |
792 /* other devices aren't supported */
796 /* reset the system time registers */
797 IXGBE_WRITE_REG(hw
, IXGBE_SYSTIML
, 0x00000000);
798 IXGBE_WRITE_REG(hw
, IXGBE_SYSTIMH
, 0x00000000);
799 IXGBE_WRITE_FLUSH(hw
);
801 /* now that the shift has been calculated and the systime
802 * registers reset, (re-)enable the Clock out feature*/
803 ixgbe_ptp_enable_sdp(hw
, shift
);
805 /* store the new cycle speed */
806 adapter
->cycle_speed
= cycle_speed
;
808 ACCESS_ONCE(adapter
->base_incval
) = incval
;
811 /* grab the ptp lock */
812 spin_lock_irqsave(&adapter
->tmreg_lock
, flags
);
814 memset(&adapter
->cc
, 0, sizeof(adapter
->cc
));
815 adapter
->cc
.read
= ixgbe_ptp_read
;
816 adapter
->cc
.mask
= CLOCKSOURCE_MASK(64);
817 adapter
->cc
.shift
= shift
;
818 adapter
->cc
.mult
= 1;
820 /* reset the ns time counter */
821 timecounter_init(&adapter
->tc
, &adapter
->cc
,
822 ktime_to_ns(ktime_get_real()));
824 spin_unlock_irqrestore(&adapter
->tmreg_lock
, flags
);
829 * @adapter - the ixgbe private adapter structure
831 * This function performs the required steps for enabling ptp
832 * support. If ptp support has already been loaded it simply calls the
833 * cyclecounter init routine and exits.
835 void ixgbe_ptp_init(struct ixgbe_adapter
*adapter
)
837 struct net_device
*netdev
= adapter
->netdev
;
839 switch (adapter
->hw
.mac
.type
) {
841 snprintf(adapter
->ptp_caps
.name
, 16, "%pm", netdev
->dev_addr
);
842 adapter
->ptp_caps
.owner
= THIS_MODULE
;
843 adapter
->ptp_caps
.max_adj
= 250000000;
844 adapter
->ptp_caps
.n_alarm
= 0;
845 adapter
->ptp_caps
.n_ext_ts
= 0;
846 adapter
->ptp_caps
.n_per_out
= 0;
847 adapter
->ptp_caps
.pps
= 1;
848 adapter
->ptp_caps
.adjfreq
= ixgbe_ptp_adjfreq
;
849 adapter
->ptp_caps
.adjtime
= ixgbe_ptp_adjtime
;
850 adapter
->ptp_caps
.gettime
= ixgbe_ptp_gettime
;
851 adapter
->ptp_caps
.settime
= ixgbe_ptp_settime
;
852 adapter
->ptp_caps
.enable
= ixgbe_ptp_enable
;
854 case ixgbe_mac_82599EB
:
855 snprintf(adapter
->ptp_caps
.name
, 16, "%pm", netdev
->dev_addr
);
856 adapter
->ptp_caps
.owner
= THIS_MODULE
;
857 adapter
->ptp_caps
.max_adj
= 250000000;
858 adapter
->ptp_caps
.n_alarm
= 0;
859 adapter
->ptp_caps
.n_ext_ts
= 0;
860 adapter
->ptp_caps
.n_per_out
= 0;
861 adapter
->ptp_caps
.pps
= 0;
862 adapter
->ptp_caps
.adjfreq
= ixgbe_ptp_adjfreq
;
863 adapter
->ptp_caps
.adjtime
= ixgbe_ptp_adjtime
;
864 adapter
->ptp_caps
.gettime
= ixgbe_ptp_gettime
;
865 adapter
->ptp_caps
.settime
= ixgbe_ptp_settime
;
866 adapter
->ptp_caps
.enable
= ixgbe_ptp_enable
;
869 adapter
->ptp_clock
= NULL
;
873 spin_lock_init(&adapter
->tmreg_lock
);
875 ixgbe_ptp_start_cyclecounter(adapter
);
877 /* (Re)start the overflow check */
878 adapter
->flags2
|= IXGBE_FLAG2_OVERFLOW_CHECK_ENABLED
;
880 adapter
->ptp_clock
= ptp_clock_register(&adapter
->ptp_caps
);
881 if (IS_ERR(adapter
->ptp_clock
)) {
882 adapter
->ptp_clock
= NULL
;
883 e_dev_err("ptp_clock_register failed\n");
885 e_dev_info("registered PHC device on %s\n", netdev
->name
);
891 * ixgbe_ptp_stop - disable ptp device and stop the overflow check
892 * @adapter: pointer to adapter struct
894 * this function stops the ptp support, and cancels the delayed work.
896 void ixgbe_ptp_stop(struct ixgbe_adapter
*adapter
)
898 ixgbe_ptp_disable_sdp(&adapter
->hw
);
900 /* stop the overflow check task */
901 adapter
->flags2
&= ~IXGBE_FLAG2_OVERFLOW_CHECK_ENABLED
;
903 if (adapter
->ptp_clock
) {
904 ptp_clock_unregister(adapter
->ptp_clock
);
905 adapter
->ptp_clock
= NULL
;
906 e_dev_info("removed PHC on %s\n",
907 adapter
->netdev
->name
);