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[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_x540.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2014 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/pci.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
32
33 #include "ixgbe.h"
34 #include "ixgbe_phy.h"
35 #include "ixgbe_x540.h"
36
37 #define IXGBE_X540_MAX_TX_QUEUES 128
38 #define IXGBE_X540_MAX_RX_QUEUES 128
39 #define IXGBE_X540_RAR_ENTRIES 128
40 #define IXGBE_X540_MC_TBL_SIZE 128
41 #define IXGBE_X540_VFT_TBL_SIZE 128
42 #define IXGBE_X540_RX_PB_SIZE 384
43
44 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
45 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
46 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
47 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
48
49 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
50 {
51 return ixgbe_media_type_copper;
52 }
53
54 s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
55 {
56 struct ixgbe_mac_info *mac = &hw->mac;
57 struct ixgbe_phy_info *phy = &hw->phy;
58
59 /* set_phy_power was set by default to NULL */
60 if (!ixgbe_mng_present(hw))
61 phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
62
63 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
64 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
65 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
66 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
67 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
68 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
69 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
70
71 return 0;
72 }
73
74 /**
75 * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
76 * @hw: pointer to hardware structure
77 * @speed: new link speed
78 * @autoneg_wait_to_complete: true when waiting for completion is needed
79 **/
80 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed,
81 bool autoneg_wait_to_complete)
82 {
83 return hw->phy.ops.setup_link_speed(hw, speed,
84 autoneg_wait_to_complete);
85 }
86
87 /**
88 * ixgbe_reset_hw_X540 - Perform hardware reset
89 * @hw: pointer to hardware structure
90 *
91 * Resets the hardware by resetting the transmit and receive units, masks
92 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
93 * reset.
94 **/
95 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
96 {
97 s32 status;
98 u32 ctrl, i;
99
100 /* Call adapter stop to disable tx/rx and clear interrupts */
101 status = hw->mac.ops.stop_adapter(hw);
102 if (status)
103 return status;
104
105 /* flush pending Tx transactions */
106 ixgbe_clear_tx_pending(hw);
107
108 mac_reset_top:
109 ctrl = IXGBE_CTRL_RST;
110 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
111 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
112 IXGBE_WRITE_FLUSH(hw);
113 usleep_range(1000, 1200);
114
115 /* Poll for reset bit to self-clear indicating reset is complete */
116 for (i = 0; i < 10; i++) {
117 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
118 if (!(ctrl & IXGBE_CTRL_RST_MASK))
119 break;
120 udelay(1);
121 }
122
123 if (ctrl & IXGBE_CTRL_RST_MASK) {
124 status = IXGBE_ERR_RESET_FAILED;
125 hw_dbg(hw, "Reset polling failed to complete.\n");
126 }
127 msleep(100);
128
129 /*
130 * Double resets are required for recovery from certain error
131 * conditions. Between resets, it is necessary to stall to allow time
132 * for any pending HW events to complete.
133 */
134 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
135 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
136 goto mac_reset_top;
137 }
138
139 /* Set the Rx packet buffer size. */
140 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
141
142 /* Store the permanent mac address */
143 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
144
145 /*
146 * Store MAC address from RAR0, clear receive address registers, and
147 * clear the multicast table. Also reset num_rar_entries to 128,
148 * since we modify this value when programming the SAN MAC address.
149 */
150 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES;
151 hw->mac.ops.init_rx_addrs(hw);
152
153 /* Store the permanent SAN mac address */
154 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
155
156 /* Add the SAN MAC address to the RAR only if it's a valid address */
157 if (is_valid_ether_addr(hw->mac.san_addr)) {
158 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
159 hw->mac.san_addr, 0, IXGBE_RAH_AV);
160
161 /* Save the SAN MAC RAR index */
162 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
163
164 /* Reserve the last RAR for the SAN MAC address */
165 hw->mac.num_rar_entries--;
166 }
167
168 /* Store the alternative WWNN/WWPN prefix */
169 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
170 &hw->mac.wwpn_prefix);
171
172 return status;
173 }
174
175 /**
176 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
177 * @hw: pointer to hardware structure
178 *
179 * Starts the hardware using the generic start_hw function
180 * and the generation start_hw function.
181 * Then performs revision-specific operations, if any.
182 **/
183 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
184 {
185 s32 ret_val;
186
187 ret_val = ixgbe_start_hw_generic(hw);
188 if (ret_val)
189 return ret_val;
190
191 return ixgbe_start_hw_gen2(hw);
192 }
193
194 /**
195 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
196 * @hw: pointer to hardware structure
197 *
198 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
199 * ixgbe_hw struct in order to set up EEPROM access.
200 **/
201 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
202 {
203 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
204 u32 eec;
205 u16 eeprom_size;
206
207 if (eeprom->type == ixgbe_eeprom_uninitialized) {
208 eeprom->semaphore_delay = 10;
209 eeprom->type = ixgbe_flash;
210
211 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
212 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
213 IXGBE_EEC_SIZE_SHIFT);
214 eeprom->word_size = 1 << (eeprom_size +
215 IXGBE_EEPROM_WORD_SIZE_SHIFT);
216
217 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
218 eeprom->type, eeprom->word_size);
219 }
220
221 return 0;
222 }
223
224 /**
225 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
226 * @hw: pointer to hardware structure
227 * @offset: offset of word in the EEPROM to read
228 * @data: word read from the EEPROM
229 *
230 * Reads a 16 bit word from the EEPROM using the EERD register.
231 **/
232 static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
233 {
234 s32 status;
235
236 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
237 return IXGBE_ERR_SWFW_SYNC;
238
239 status = ixgbe_read_eerd_generic(hw, offset, data);
240
241 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
242 return status;
243 }
244
245 /**
246 * ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD
247 * @hw: pointer to hardware structure
248 * @offset: offset of word in the EEPROM to read
249 * @words: number of words
250 * @data: word(s) read from the EEPROM
251 *
252 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
253 **/
254 static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
255 u16 offset, u16 words, u16 *data)
256 {
257 s32 status;
258
259 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
260 return IXGBE_ERR_SWFW_SYNC;
261
262 status = ixgbe_read_eerd_buffer_generic(hw, offset, words, data);
263
264 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
265 return status;
266 }
267
268 /**
269 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
270 * @hw: pointer to hardware structure
271 * @offset: offset of word in the EEPROM to write
272 * @data: word write to the EEPROM
273 *
274 * Write a 16 bit word to the EEPROM using the EEWR register.
275 **/
276 static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
277 {
278 s32 status;
279
280 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
281 return IXGBE_ERR_SWFW_SYNC;
282
283 status = ixgbe_write_eewr_generic(hw, offset, data);
284
285 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
286 return status;
287 }
288
289 /**
290 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
291 * @hw: pointer to hardware structure
292 * @offset: offset of word in the EEPROM to write
293 * @words: number of words
294 * @data: word(s) write to the EEPROM
295 *
296 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
297 **/
298 static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
299 u16 offset, u16 words, u16 *data)
300 {
301 s32 status;
302
303 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
304 return IXGBE_ERR_SWFW_SYNC;
305
306 status = ixgbe_write_eewr_buffer_generic(hw, offset, words, data);
307
308 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
309 return status;
310 }
311
312 /**
313 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
314 *
315 * This function does not use synchronization for EERD and EEWR. It can
316 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
317 *
318 * @hw: pointer to hardware structure
319 **/
320 static s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
321 {
322 u16 i;
323 u16 j;
324 u16 checksum = 0;
325 u16 length = 0;
326 u16 pointer = 0;
327 u16 word = 0;
328 u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;
329 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
330
331 /*
332 * Do not use hw->eeprom.ops.read because we do not want to take
333 * the synchronization semaphores here. Instead use
334 * ixgbe_read_eerd_generic
335 */
336
337 /* Include 0x0-0x3F in the checksum */
338 for (i = 0; i < checksum_last_word; i++) {
339 if (ixgbe_read_eerd_generic(hw, i, &word)) {
340 hw_dbg(hw, "EEPROM read failed\n");
341 return IXGBE_ERR_EEPROM;
342 }
343 checksum += word;
344 }
345
346 /*
347 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
348 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
349 */
350 for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
351 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
352 continue;
353
354 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
355 hw_dbg(hw, "EEPROM read failed\n");
356 break;
357 }
358
359 /* Skip pointer section if the pointer is invalid. */
360 if (pointer == 0xFFFF || pointer == 0 ||
361 pointer >= hw->eeprom.word_size)
362 continue;
363
364 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
365 hw_dbg(hw, "EEPROM read failed\n");
366 return IXGBE_ERR_EEPROM;
367 break;
368 }
369
370 /* Skip pointer section if length is invalid. */
371 if (length == 0xFFFF || length == 0 ||
372 (pointer + length) >= hw->eeprom.word_size)
373 continue;
374
375 for (j = pointer + 1; j <= pointer + length; j++) {
376 if (ixgbe_read_eerd_generic(hw, j, &word)) {
377 hw_dbg(hw, "EEPROM read failed\n");
378 return IXGBE_ERR_EEPROM;
379 }
380 checksum += word;
381 }
382 }
383
384 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
385
386 return (s32)checksum;
387 }
388
389 /**
390 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
391 * @hw: pointer to hardware structure
392 * @checksum_val: calculated checksum
393 *
394 * Performs checksum calculation and validates the EEPROM checksum. If the
395 * caller does not need checksum_val, the value can be NULL.
396 **/
397 static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
398 u16 *checksum_val)
399 {
400 s32 status;
401 u16 checksum;
402 u16 read_checksum = 0;
403
404 /* Read the first word from the EEPROM. If this times out or fails, do
405 * not continue or we could be in for a very long wait while every
406 * EEPROM read fails
407 */
408 status = hw->eeprom.ops.read(hw, 0, &checksum);
409 if (status) {
410 hw_dbg(hw, "EEPROM read failed\n");
411 return status;
412 }
413
414 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
415 return IXGBE_ERR_SWFW_SYNC;
416
417 status = hw->eeprom.ops.calc_checksum(hw);
418 if (status < 0)
419 goto out;
420
421 checksum = (u16)(status & 0xffff);
422
423 /* Do not use hw->eeprom.ops.read because we do not want to take
424 * the synchronization semaphores twice here.
425 */
426 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
427 &read_checksum);
428 if (status)
429 goto out;
430
431 /* Verify read checksum from EEPROM is the same as
432 * calculated checksum
433 */
434 if (read_checksum != checksum) {
435 hw_dbg(hw, "Invalid EEPROM checksum");
436 status = IXGBE_ERR_EEPROM_CHECKSUM;
437 }
438
439 /* If the user cares, return the calculated checksum */
440 if (checksum_val)
441 *checksum_val = checksum;
442
443 out:
444 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
445
446 return status;
447 }
448
449 /**
450 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
451 * @hw: pointer to hardware structure
452 *
453 * After writing EEPROM to shadow RAM using EEWR register, software calculates
454 * checksum and updates the EEPROM and instructs the hardware to update
455 * the flash.
456 **/
457 static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
458 {
459 s32 status;
460 u16 checksum;
461
462 /* Read the first word from the EEPROM. If this times out or fails, do
463 * not continue or we could be in for a very long wait while every
464 * EEPROM read fails
465 */
466 status = hw->eeprom.ops.read(hw, 0, &checksum);
467 if (status) {
468 hw_dbg(hw, "EEPROM read failed\n");
469 return status;
470 }
471
472 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
473 return IXGBE_ERR_SWFW_SYNC;
474
475 status = hw->eeprom.ops.calc_checksum(hw);
476 if (status < 0)
477 goto out;
478
479 checksum = (u16)(status & 0xffff);
480
481 /* Do not use hw->eeprom.ops.write because we do not want to
482 * take the synchronization semaphores twice here.
483 */
484 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
485 if (status)
486 goto out;
487
488 status = ixgbe_update_flash_X540(hw);
489
490 out:
491 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
492 return status;
493 }
494
495 /**
496 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
497 * @hw: pointer to hardware structure
498 *
499 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
500 * EEPROM from shadow RAM to the flash device.
501 **/
502 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
503 {
504 u32 flup;
505 s32 status;
506
507 status = ixgbe_poll_flash_update_done_X540(hw);
508 if (status == IXGBE_ERR_EEPROM) {
509 hw_dbg(hw, "Flash update time out\n");
510 return status;
511 }
512
513 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw)) | IXGBE_EEC_FLUP;
514 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
515
516 status = ixgbe_poll_flash_update_done_X540(hw);
517 if (status == 0)
518 hw_dbg(hw, "Flash update complete\n");
519 else
520 hw_dbg(hw, "Flash update time out\n");
521
522 if (hw->revision_id == 0) {
523 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
524
525 if (flup & IXGBE_EEC_SEC1VAL) {
526 flup |= IXGBE_EEC_FLUP;
527 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
528 }
529
530 status = ixgbe_poll_flash_update_done_X540(hw);
531 if (status == 0)
532 hw_dbg(hw, "Flash update complete\n");
533 else
534 hw_dbg(hw, "Flash update time out\n");
535 }
536
537 return status;
538 }
539
540 /**
541 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
542 * @hw: pointer to hardware structure
543 *
544 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
545 * flash update is done.
546 **/
547 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
548 {
549 u32 i;
550 u32 reg;
551
552 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
553 reg = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
554 if (reg & IXGBE_EEC_FLUDONE)
555 return 0;
556 udelay(5);
557 }
558 return IXGBE_ERR_EEPROM;
559 }
560
561 /**
562 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
563 * @hw: pointer to hardware structure
564 * @mask: Mask to specify which semaphore to acquire
565 *
566 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
567 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
568 **/
569 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
570 {
571 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
572 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
573 u32 fwmask = swmask << 5;
574 u32 timeout = 200;
575 u32 hwmask = 0;
576 u32 swfw_sync;
577 u32 i;
578
579 if (swmask & IXGBE_GSSR_EEP_SM)
580 hwmask = IXGBE_GSSR_FLASH_SM;
581
582 /* SW only mask does not have FW bit pair */
583 if (mask & IXGBE_GSSR_SW_MNG_SM)
584 swmask |= IXGBE_GSSR_SW_MNG_SM;
585
586 swmask |= swi2c_mask;
587 fwmask |= swi2c_mask << 2;
588 for (i = 0; i < timeout; i++) {
589 /* SW NVM semaphore bit is used for access to all
590 * SW_FW_SYNC bits (not just NVM)
591 */
592 if (ixgbe_get_swfw_sync_semaphore(hw))
593 return IXGBE_ERR_SWFW_SYNC;
594
595 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
596 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
597 swfw_sync |= swmask;
598 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
599 ixgbe_release_swfw_sync_semaphore(hw);
600 usleep_range(5000, 6000);
601 return 0;
602 }
603 /* Firmware currently using resource (fwmask), hardware
604 * currently using resource (hwmask), or other software
605 * thread currently using resource (swmask)
606 */
607 ixgbe_release_swfw_sync_semaphore(hw);
608 usleep_range(5000, 10000);
609 }
610
611 /* Failed to get SW only semaphore */
612 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
613 hw_dbg(hw, "Failed to get SW only semaphore\n");
614 return IXGBE_ERR_SWFW_SYNC;
615 }
616
617 /* If the resource is not released by the FW/HW the SW can assume that
618 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
619 * of the requested resource(s) while ignoring the corresponding FW/HW
620 * bits in the SW_FW_SYNC register.
621 */
622 if (ixgbe_get_swfw_sync_semaphore(hw))
623 return IXGBE_ERR_SWFW_SYNC;
624 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
625 if (swfw_sync & (fwmask | hwmask)) {
626 swfw_sync |= swmask;
627 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
628 ixgbe_release_swfw_sync_semaphore(hw);
629 usleep_range(5000, 6000);
630 return 0;
631 }
632 /* If the resource is not released by other SW the SW can assume that
633 * the other SW malfunctions. In that case the SW should clear all SW
634 * flags that it does not own and then repeat the whole process once
635 * again.
636 */
637 if (swfw_sync & swmask) {
638 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
639 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM;
640
641 if (swi2c_mask)
642 rmask |= IXGBE_GSSR_I2C_MASK;
643 ixgbe_release_swfw_sync_X540(hw, rmask);
644 ixgbe_release_swfw_sync_semaphore(hw);
645 return IXGBE_ERR_SWFW_SYNC;
646 }
647 ixgbe_release_swfw_sync_semaphore(hw);
648
649 return IXGBE_ERR_SWFW_SYNC;
650 }
651
652 /**
653 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
654 * @hw: pointer to hardware structure
655 * @mask: Mask to specify which semaphore to release
656 *
657 * Releases the SWFW semaphore through the SW_FW_SYNC register
658 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
659 **/
660 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
661 {
662 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
663 u32 swfw_sync;
664
665 if (mask & IXGBE_GSSR_I2C_MASK)
666 swmask |= mask & IXGBE_GSSR_I2C_MASK;
667 ixgbe_get_swfw_sync_semaphore(hw);
668
669 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
670 swfw_sync &= ~swmask;
671 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
672
673 ixgbe_release_swfw_sync_semaphore(hw);
674 usleep_range(5000, 6000);
675 }
676
677 /**
678 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
679 * @hw: pointer to hardware structure
680 *
681 * Sets the hardware semaphores so SW/FW can gain control of shared resources
682 */
683 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
684 {
685 u32 timeout = 2000;
686 u32 i;
687 u32 swsm;
688
689 /* Get SMBI software semaphore between device drivers first */
690 for (i = 0; i < timeout; i++) {
691 /* If the SMBI bit is 0 when we read it, then the bit will be
692 * set and we have the semaphore
693 */
694 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
695 if (!(swsm & IXGBE_SWSM_SMBI))
696 break;
697 usleep_range(50, 100);
698 }
699
700 if (i == timeout) {
701 hw_dbg(hw,
702 "Software semaphore SMBI between device drivers not granted.\n");
703 return IXGBE_ERR_EEPROM;
704 }
705
706 /* Now get the semaphore between SW/FW through the REGSMP bit */
707 for (i = 0; i < timeout; i++) {
708 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
709 if (!(swsm & IXGBE_SWFW_REGSMP))
710 return 0;
711
712 usleep_range(50, 100);
713 }
714
715 /* Release semaphores and return error if SW NVM semaphore
716 * was not granted because we do not have access to the EEPROM
717 */
718 hw_dbg(hw, "REGSMP Software NVM semaphore not granted\n");
719 ixgbe_release_swfw_sync_semaphore(hw);
720 return IXGBE_ERR_EEPROM;
721 }
722
723 /**
724 * ixgbe_release_nvm_semaphore - Release hardware semaphore
725 * @hw: pointer to hardware structure
726 *
727 * This function clears hardware semaphore bits.
728 **/
729 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
730 {
731 u32 swsm;
732
733 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
734
735 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
736 swsm &= ~IXGBE_SWFW_REGSMP;
737 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swsm);
738
739 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
740 swsm &= ~IXGBE_SWSM_SMBI;
741 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
742
743 IXGBE_WRITE_FLUSH(hw);
744 }
745
746 /**
747 * ixgbe_blink_led_start_X540 - Blink LED based on index.
748 * @hw: pointer to hardware structure
749 * @index: led number to blink
750 *
751 * Devices that implement the version 2 interface:
752 * X540
753 **/
754 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
755 {
756 u32 macc_reg;
757 u32 ledctl_reg;
758 ixgbe_link_speed speed;
759 bool link_up;
760
761 /*
762 * Link should be up in order for the blink bit in the LED control
763 * register to work. Force link and speed in the MAC if link is down.
764 * This will be reversed when we stop the blinking.
765 */
766 hw->mac.ops.check_link(hw, &speed, &link_up, false);
767 if (!link_up) {
768 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
769 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
770 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
771 }
772 /* Set the LED to LINK_UP + BLINK. */
773 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
774 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
775 ledctl_reg |= IXGBE_LED_BLINK(index);
776 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
777 IXGBE_WRITE_FLUSH(hw);
778
779 return 0;
780 }
781
782 /**
783 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
784 * @hw: pointer to hardware structure
785 * @index: led number to stop blinking
786 *
787 * Devices that implement the version 2 interface:
788 * X540
789 **/
790 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
791 {
792 u32 macc_reg;
793 u32 ledctl_reg;
794
795 /* Restore the LED to its default value. */
796 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
797 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
798 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
799 ledctl_reg &= ~IXGBE_LED_BLINK(index);
800 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
801
802 /* Unforce link and speed in the MAC. */
803 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
804 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
805 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
806 IXGBE_WRITE_FLUSH(hw);
807
808 return 0;
809 }
810 static struct ixgbe_mac_operations mac_ops_X540 = {
811 .init_hw = &ixgbe_init_hw_generic,
812 .reset_hw = &ixgbe_reset_hw_X540,
813 .start_hw = &ixgbe_start_hw_X540,
814 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
815 .get_media_type = &ixgbe_get_media_type_X540,
816 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
817 .get_mac_addr = &ixgbe_get_mac_addr_generic,
818 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
819 .get_device_caps = &ixgbe_get_device_caps_generic,
820 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
821 .stop_adapter = &ixgbe_stop_adapter_generic,
822 .get_bus_info = &ixgbe_get_bus_info_generic,
823 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
824 .read_analog_reg8 = NULL,
825 .write_analog_reg8 = NULL,
826 .setup_link = &ixgbe_setup_mac_link_X540,
827 .set_rxpba = &ixgbe_set_rxpba_generic,
828 .check_link = &ixgbe_check_mac_link_generic,
829 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
830 .led_on = &ixgbe_led_on_generic,
831 .led_off = &ixgbe_led_off_generic,
832 .blink_led_start = &ixgbe_blink_led_start_X540,
833 .blink_led_stop = &ixgbe_blink_led_stop_X540,
834 .set_rar = &ixgbe_set_rar_generic,
835 .clear_rar = &ixgbe_clear_rar_generic,
836 .set_vmdq = &ixgbe_set_vmdq_generic,
837 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic,
838 .clear_vmdq = &ixgbe_clear_vmdq_generic,
839 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
840 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
841 .enable_mc = &ixgbe_enable_mc_generic,
842 .disable_mc = &ixgbe_disable_mc_generic,
843 .clear_vfta = &ixgbe_clear_vfta_generic,
844 .set_vfta = &ixgbe_set_vfta_generic,
845 .fc_enable = &ixgbe_fc_enable_generic,
846 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
847 .init_uta_tables = &ixgbe_init_uta_tables_generic,
848 .setup_sfp = NULL,
849 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
850 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
851 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
852 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
853 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
854 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
855 .get_thermal_sensor_data = NULL,
856 .init_thermal_sensor_thresh = NULL,
857 .prot_autoc_read = &prot_autoc_read_generic,
858 .prot_autoc_write = &prot_autoc_write_generic,
859 .enable_rx = &ixgbe_enable_rx_generic,
860 .disable_rx = &ixgbe_disable_rx_generic,
861 };
862
863 static struct ixgbe_eeprom_operations eeprom_ops_X540 = {
864 .init_params = &ixgbe_init_eeprom_params_X540,
865 .read = &ixgbe_read_eerd_X540,
866 .read_buffer = &ixgbe_read_eerd_buffer_X540,
867 .write = &ixgbe_write_eewr_X540,
868 .write_buffer = &ixgbe_write_eewr_buffer_X540,
869 .calc_checksum = &ixgbe_calc_eeprom_checksum_X540,
870 .validate_checksum = &ixgbe_validate_eeprom_checksum_X540,
871 .update_checksum = &ixgbe_update_eeprom_checksum_X540,
872 };
873
874 static struct ixgbe_phy_operations phy_ops_X540 = {
875 .identify = &ixgbe_identify_phy_generic,
876 .identify_sfp = &ixgbe_identify_sfp_module_generic,
877 .init = NULL,
878 .reset = NULL,
879 .read_reg = &ixgbe_read_phy_reg_generic,
880 .write_reg = &ixgbe_write_phy_reg_generic,
881 .setup_link = &ixgbe_setup_phy_link_generic,
882 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
883 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
884 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
885 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
886 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
887 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
888 .check_overtemp = &ixgbe_tn_check_overtemp,
889 .set_phy_power = &ixgbe_set_copper_phy_power,
890 .get_firmware_version = &ixgbe_get_phy_firmware_version_generic,
891 };
892
893 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = {
894 IXGBE_MVALS_INIT(X540)
895 };
896
897 struct ixgbe_info ixgbe_X540_info = {
898 .mac = ixgbe_mac_X540,
899 .get_invariants = &ixgbe_get_invariants_X540,
900 .mac_ops = &mac_ops_X540,
901 .eeprom_ops = &eeprom_ops_X540,
902 .phy_ops = &phy_ops_X540,
903 .mbx_ops = &mbx_ops_generic,
904 .mvals = ixgbe_mvals_X540,
905 };
Linux kernel - Deliverables
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