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phy: Centralise print about attached phy
[deliverable/linux.git] / drivers / net / ethernet / lantiq_etop.c
1 /*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, see <http://www.gnu.org/licenses/>.
13 *
14 * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/slab.h>
19 #include <linux/errno.h>
20 #include <linux/types.h>
21 #include <linux/interrupt.h>
22 #include <linux/uaccess.h>
23 #include <linux/in.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/phy.h>
27 #include <linux/ip.h>
28 #include <linux/tcp.h>
29 #include <linux/skbuff.h>
30 #include <linux/mm.h>
31 #include <linux/platform_device.h>
32 #include <linux/ethtool.h>
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/io.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/module.h>
38
39 #include <asm/checksum.h>
40
41 #include <lantiq_soc.h>
42 #include <xway_dma.h>
43 #include <lantiq_platform.h>
44
45 #define LTQ_ETOP_MDIO 0x11804
46 #define MDIO_REQUEST 0x80000000
47 #define MDIO_READ 0x40000000
48 #define MDIO_ADDR_MASK 0x1f
49 #define MDIO_ADDR_OFFSET 0x15
50 #define MDIO_REG_MASK 0x1f
51 #define MDIO_REG_OFFSET 0x10
52 #define MDIO_VAL_MASK 0xffff
53
54 #define PPE32_CGEN 0x800
55 #define LQ_PPE32_ENET_MAC_CFG 0x1840
56
57 #define LTQ_ETOP_ENETS0 0x11850
58 #define LTQ_ETOP_MAC_DA0 0x1186C
59 #define LTQ_ETOP_MAC_DA1 0x11870
60 #define LTQ_ETOP_CFG 0x16020
61 #define LTQ_ETOP_IGPLEN 0x16080
62
63 #define MAX_DMA_CHAN 0x8
64 #define MAX_DMA_CRC_LEN 0x4
65 #define MAX_DMA_DATA_LEN 0x600
66
67 #define ETOP_FTCU BIT(28)
68 #define ETOP_MII_MASK 0xf
69 #define ETOP_MII_NORMAL 0xd
70 #define ETOP_MII_REVERSE 0xe
71 #define ETOP_PLEN_UNDER 0x40
72 #define ETOP_CGEN 0x800
73
74 /* use 2 static channels for TX/RX */
75 #define LTQ_ETOP_TX_CHANNEL 1
76 #define LTQ_ETOP_RX_CHANNEL 6
77 #define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
78 #define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
79
80 #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
81 #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
82 #define ltq_etop_w32_mask(x, y, z) \
83 ltq_w32_mask(x, y, ltq_etop_membase + (z))
84
85 #define DRV_VERSION "1.0"
86
87 static void __iomem *ltq_etop_membase;
88
89 struct ltq_etop_chan {
90 int idx;
91 int tx_free;
92 struct net_device *netdev;
93 struct napi_struct napi;
94 struct ltq_dma_channel dma;
95 struct sk_buff *skb[LTQ_DESC_NUM];
96 };
97
98 struct ltq_etop_priv {
99 struct net_device *netdev;
100 struct platform_device *pdev;
101 struct ltq_eth_data *pldata;
102 struct resource *res;
103
104 struct mii_bus *mii_bus;
105 struct phy_device *phydev;
106
107 struct ltq_etop_chan ch[MAX_DMA_CHAN];
108 int tx_free[MAX_DMA_CHAN >> 1];
109
110 spinlock_t lock;
111 };
112
113 static int
114 ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
115 {
116 ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
117 if (!ch->skb[ch->dma.desc])
118 return -ENOMEM;
119 ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
120 ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN,
121 DMA_FROM_DEVICE);
122 ch->dma.desc_base[ch->dma.desc].addr =
123 CPHYSADDR(ch->skb[ch->dma.desc]->data);
124 ch->dma.desc_base[ch->dma.desc].ctl =
125 LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
126 MAX_DMA_DATA_LEN;
127 skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
128 return 0;
129 }
130
131 static void
132 ltq_etop_hw_receive(struct ltq_etop_chan *ch)
133 {
134 struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
135 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
136 struct sk_buff *skb = ch->skb[ch->dma.desc];
137 int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN;
138 unsigned long flags;
139
140 spin_lock_irqsave(&priv->lock, flags);
141 if (ltq_etop_alloc_skb(ch)) {
142 netdev_err(ch->netdev,
143 "failed to allocate new rx buffer, stopping DMA\n");
144 ltq_dma_close(&ch->dma);
145 }
146 ch->dma.desc++;
147 ch->dma.desc %= LTQ_DESC_NUM;
148 spin_unlock_irqrestore(&priv->lock, flags);
149
150 skb_put(skb, len);
151 skb->protocol = eth_type_trans(skb, ch->netdev);
152 netif_receive_skb(skb);
153 }
154
155 static int
156 ltq_etop_poll_rx(struct napi_struct *napi, int budget)
157 {
158 struct ltq_etop_chan *ch = container_of(napi,
159 struct ltq_etop_chan, napi);
160 int rx = 0;
161 int complete = 0;
162
163 while ((rx < budget) && !complete) {
164 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
165
166 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
167 ltq_etop_hw_receive(ch);
168 rx++;
169 } else {
170 complete = 1;
171 }
172 }
173 if (complete || !rx) {
174 napi_complete(&ch->napi);
175 ltq_dma_ack_irq(&ch->dma);
176 }
177 return rx;
178 }
179
180 static int
181 ltq_etop_poll_tx(struct napi_struct *napi, int budget)
182 {
183 struct ltq_etop_chan *ch =
184 container_of(napi, struct ltq_etop_chan, napi);
185 struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
186 struct netdev_queue *txq =
187 netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
188 unsigned long flags;
189
190 spin_lock_irqsave(&priv->lock, flags);
191 while ((ch->dma.desc_base[ch->tx_free].ctl &
192 (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
193 dev_kfree_skb_any(ch->skb[ch->tx_free]);
194 ch->skb[ch->tx_free] = NULL;
195 memset(&ch->dma.desc_base[ch->tx_free], 0,
196 sizeof(struct ltq_dma_desc));
197 ch->tx_free++;
198 ch->tx_free %= LTQ_DESC_NUM;
199 }
200 spin_unlock_irqrestore(&priv->lock, flags);
201
202 if (netif_tx_queue_stopped(txq))
203 netif_tx_start_queue(txq);
204 napi_complete(&ch->napi);
205 ltq_dma_ack_irq(&ch->dma);
206 return 1;
207 }
208
209 static irqreturn_t
210 ltq_etop_dma_irq(int irq, void *_priv)
211 {
212 struct ltq_etop_priv *priv = _priv;
213 int ch = irq - LTQ_DMA_CH0_INT;
214
215 napi_schedule(&priv->ch[ch].napi);
216 return IRQ_HANDLED;
217 }
218
219 static void
220 ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
221 {
222 struct ltq_etop_priv *priv = netdev_priv(dev);
223
224 ltq_dma_free(&ch->dma);
225 if (ch->dma.irq)
226 free_irq(ch->dma.irq, priv);
227 if (IS_RX(ch->idx)) {
228 int desc;
229 for (desc = 0; desc < LTQ_DESC_NUM; desc++)
230 dev_kfree_skb_any(ch->skb[ch->dma.desc]);
231 }
232 }
233
234 static void
235 ltq_etop_hw_exit(struct net_device *dev)
236 {
237 struct ltq_etop_priv *priv = netdev_priv(dev);
238 int i;
239
240 ltq_pmu_disable(PMU_PPE);
241 for (i = 0; i < MAX_DMA_CHAN; i++)
242 if (IS_TX(i) || IS_RX(i))
243 ltq_etop_free_channel(dev, &priv->ch[i]);
244 }
245
246 static int
247 ltq_etop_hw_init(struct net_device *dev)
248 {
249 struct ltq_etop_priv *priv = netdev_priv(dev);
250 int i;
251
252 ltq_pmu_enable(PMU_PPE);
253
254 switch (priv->pldata->mii_mode) {
255 case PHY_INTERFACE_MODE_RMII:
256 ltq_etop_w32_mask(ETOP_MII_MASK,
257 ETOP_MII_REVERSE, LTQ_ETOP_CFG);
258 break;
259
260 case PHY_INTERFACE_MODE_MII:
261 ltq_etop_w32_mask(ETOP_MII_MASK,
262 ETOP_MII_NORMAL, LTQ_ETOP_CFG);
263 break;
264
265 default:
266 netdev_err(dev, "unknown mii mode %d\n",
267 priv->pldata->mii_mode);
268 return -ENOTSUPP;
269 }
270
271 /* enable crc generation */
272 ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
273
274 ltq_dma_init_port(DMA_PORT_ETOP);
275
276 for (i = 0; i < MAX_DMA_CHAN; i++) {
277 int irq = LTQ_DMA_CH0_INT + i;
278 struct ltq_etop_chan *ch = &priv->ch[i];
279
280 ch->idx = ch->dma.nr = i;
281
282 if (IS_TX(i)) {
283 ltq_dma_alloc_tx(&ch->dma);
284 request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
285 } else if (IS_RX(i)) {
286 ltq_dma_alloc_rx(&ch->dma);
287 for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
288 ch->dma.desc++)
289 if (ltq_etop_alloc_skb(ch))
290 return -ENOMEM;
291 ch->dma.desc = 0;
292 request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
293 }
294 ch->dma.irq = irq;
295 }
296 return 0;
297 }
298
299 static void
300 ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
301 {
302 strlcpy(info->driver, "Lantiq ETOP", sizeof(info->driver));
303 strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
304 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
305 }
306
307 static int
308 ltq_etop_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
309 {
310 struct ltq_etop_priv *priv = netdev_priv(dev);
311
312 return phy_ethtool_gset(priv->phydev, cmd);
313 }
314
315 static int
316 ltq_etop_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
317 {
318 struct ltq_etop_priv *priv = netdev_priv(dev);
319
320 return phy_ethtool_sset(priv->phydev, cmd);
321 }
322
323 static int
324 ltq_etop_nway_reset(struct net_device *dev)
325 {
326 struct ltq_etop_priv *priv = netdev_priv(dev);
327
328 return phy_start_aneg(priv->phydev);
329 }
330
331 static const struct ethtool_ops ltq_etop_ethtool_ops = {
332 .get_drvinfo = ltq_etop_get_drvinfo,
333 .get_settings = ltq_etop_get_settings,
334 .set_settings = ltq_etop_set_settings,
335 .nway_reset = ltq_etop_nway_reset,
336 };
337
338 static int
339 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
340 {
341 u32 val = MDIO_REQUEST |
342 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
343 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
344 phy_data;
345
346 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
347 ;
348 ltq_etop_w32(val, LTQ_ETOP_MDIO);
349 return 0;
350 }
351
352 static int
353 ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg)
354 {
355 u32 val = MDIO_REQUEST | MDIO_READ |
356 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
357 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
358
359 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
360 ;
361 ltq_etop_w32(val, LTQ_ETOP_MDIO);
362 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
363 ;
364 val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
365 return val;
366 }
367
368 static void
369 ltq_etop_mdio_link(struct net_device *dev)
370 {
371 /* nothing to do */
372 }
373
374 static int
375 ltq_etop_mdio_probe(struct net_device *dev)
376 {
377 struct ltq_etop_priv *priv = netdev_priv(dev);
378 struct phy_device *phydev = NULL;
379 int phy_addr;
380
381 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
382 if (priv->mii_bus->phy_map[phy_addr]) {
383 phydev = priv->mii_bus->phy_map[phy_addr];
384 break;
385 }
386 }
387
388 if (!phydev) {
389 netdev_err(dev, "no PHY found\n");
390 return -ENODEV;
391 }
392
393 phydev = phy_connect(dev, phydev_name(phydev),
394 &ltq_etop_mdio_link, priv->pldata->mii_mode);
395
396 if (IS_ERR(phydev)) {
397 netdev_err(dev, "Could not attach to PHY\n");
398 return PTR_ERR(phydev);
399 }
400
401 phydev->supported &= (SUPPORTED_10baseT_Half
402 | SUPPORTED_10baseT_Full
403 | SUPPORTED_100baseT_Half
404 | SUPPORTED_100baseT_Full
405 | SUPPORTED_Autoneg
406 | SUPPORTED_MII
407 | SUPPORTED_TP);
408
409 phydev->advertising = phydev->supported;
410 priv->phydev = phydev;
411 phy_attached_info(phydev);
412
413 return 0;
414 }
415
416 static int
417 ltq_etop_mdio_init(struct net_device *dev)
418 {
419 struct ltq_etop_priv *priv = netdev_priv(dev);
420 int i;
421 int err;
422
423 priv->mii_bus = mdiobus_alloc();
424 if (!priv->mii_bus) {
425 netdev_err(dev, "failed to allocate mii bus\n");
426 err = -ENOMEM;
427 goto err_out;
428 }
429
430 priv->mii_bus->priv = dev;
431 priv->mii_bus->read = ltq_etop_mdio_rd;
432 priv->mii_bus->write = ltq_etop_mdio_wr;
433 priv->mii_bus->name = "ltq_mii";
434 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
435 priv->pdev->name, priv->pdev->id);
436 priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
437 if (!priv->mii_bus->irq) {
438 err = -ENOMEM;
439 goto err_out_free_mdiobus;
440 }
441
442 for (i = 0; i < PHY_MAX_ADDR; ++i)
443 priv->mii_bus->irq[i] = PHY_POLL;
444
445 if (mdiobus_register(priv->mii_bus)) {
446 err = -ENXIO;
447 goto err_out_free_mdio_irq;
448 }
449
450 if (ltq_etop_mdio_probe(dev)) {
451 err = -ENXIO;
452 goto err_out_unregister_bus;
453 }
454 return 0;
455
456 err_out_unregister_bus:
457 mdiobus_unregister(priv->mii_bus);
458 err_out_free_mdio_irq:
459 kfree(priv->mii_bus->irq);
460 err_out_free_mdiobus:
461 mdiobus_free(priv->mii_bus);
462 err_out:
463 return err;
464 }
465
466 static void
467 ltq_etop_mdio_cleanup(struct net_device *dev)
468 {
469 struct ltq_etop_priv *priv = netdev_priv(dev);
470
471 phy_disconnect(priv->phydev);
472 mdiobus_unregister(priv->mii_bus);
473 kfree(priv->mii_bus->irq);
474 mdiobus_free(priv->mii_bus);
475 }
476
477 static int
478 ltq_etop_open(struct net_device *dev)
479 {
480 struct ltq_etop_priv *priv = netdev_priv(dev);
481 int i;
482
483 for (i = 0; i < MAX_DMA_CHAN; i++) {
484 struct ltq_etop_chan *ch = &priv->ch[i];
485
486 if (!IS_TX(i) && (!IS_RX(i)))
487 continue;
488 ltq_dma_open(&ch->dma);
489 napi_enable(&ch->napi);
490 }
491 phy_start(priv->phydev);
492 netif_tx_start_all_queues(dev);
493 return 0;
494 }
495
496 static int
497 ltq_etop_stop(struct net_device *dev)
498 {
499 struct ltq_etop_priv *priv = netdev_priv(dev);
500 int i;
501
502 netif_tx_stop_all_queues(dev);
503 phy_stop(priv->phydev);
504 for (i = 0; i < MAX_DMA_CHAN; i++) {
505 struct ltq_etop_chan *ch = &priv->ch[i];
506
507 if (!IS_RX(i) && !IS_TX(i))
508 continue;
509 napi_disable(&ch->napi);
510 ltq_dma_close(&ch->dma);
511 }
512 return 0;
513 }
514
515 static int
516 ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
517 {
518 int queue = skb_get_queue_mapping(skb);
519 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
520 struct ltq_etop_priv *priv = netdev_priv(dev);
521 struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
522 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
523 int len;
524 unsigned long flags;
525 u32 byte_offset;
526
527 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
528
529 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
530 dev_kfree_skb_any(skb);
531 netdev_err(dev, "tx ring full\n");
532 netif_tx_stop_queue(txq);
533 return NETDEV_TX_BUSY;
534 }
535
536 /* dma needs to start on a 16 byte aligned address */
537 byte_offset = CPHYSADDR(skb->data) % 16;
538 ch->skb[ch->dma.desc] = skb;
539
540 dev->trans_start = jiffies;
541
542 spin_lock_irqsave(&priv->lock, flags);
543 desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len,
544 DMA_TO_DEVICE)) - byte_offset;
545 wmb();
546 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
547 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
548 ch->dma.desc++;
549 ch->dma.desc %= LTQ_DESC_NUM;
550 spin_unlock_irqrestore(&priv->lock, flags);
551
552 if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
553 netif_tx_stop_queue(txq);
554
555 return NETDEV_TX_OK;
556 }
557
558 static int
559 ltq_etop_change_mtu(struct net_device *dev, int new_mtu)
560 {
561 int ret = eth_change_mtu(dev, new_mtu);
562
563 if (!ret) {
564 struct ltq_etop_priv *priv = netdev_priv(dev);
565 unsigned long flags;
566
567 spin_lock_irqsave(&priv->lock, flags);
568 ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu,
569 LTQ_ETOP_IGPLEN);
570 spin_unlock_irqrestore(&priv->lock, flags);
571 }
572 return ret;
573 }
574
575 static int
576 ltq_etop_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
577 {
578 struct ltq_etop_priv *priv = netdev_priv(dev);
579
580 /* TODO: mii-toll reports "No MII transceiver present!." ?!*/
581 return phy_mii_ioctl(priv->phydev, rq, cmd);
582 }
583
584 static int
585 ltq_etop_set_mac_address(struct net_device *dev, void *p)
586 {
587 int ret = eth_mac_addr(dev, p);
588
589 if (!ret) {
590 struct ltq_etop_priv *priv = netdev_priv(dev);
591 unsigned long flags;
592
593 /* store the mac for the unicast filter */
594 spin_lock_irqsave(&priv->lock, flags);
595 ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0);
596 ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16,
597 LTQ_ETOP_MAC_DA1);
598 spin_unlock_irqrestore(&priv->lock, flags);
599 }
600 return ret;
601 }
602
603 static void
604 ltq_etop_set_multicast_list(struct net_device *dev)
605 {
606 struct ltq_etop_priv *priv = netdev_priv(dev);
607 unsigned long flags;
608
609 /* ensure that the unicast filter is not enabled in promiscious mode */
610 spin_lock_irqsave(&priv->lock, flags);
611 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI))
612 ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0);
613 else
614 ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0);
615 spin_unlock_irqrestore(&priv->lock, flags);
616 }
617
618 static u16
619 ltq_etop_select_queue(struct net_device *dev, struct sk_buff *skb,
620 void *accel_priv, select_queue_fallback_t fallback)
621 {
622 /* we are currently only using the first queue */
623 return 0;
624 }
625
626 static int
627 ltq_etop_init(struct net_device *dev)
628 {
629 struct ltq_etop_priv *priv = netdev_priv(dev);
630 struct sockaddr mac;
631 int err;
632 bool random_mac = false;
633
634 dev->watchdog_timeo = 10 * HZ;
635 err = ltq_etop_hw_init(dev);
636 if (err)
637 goto err_hw;
638 ltq_etop_change_mtu(dev, 1500);
639
640 memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
641 if (!is_valid_ether_addr(mac.sa_data)) {
642 pr_warn("etop: invalid MAC, using random\n");
643 eth_random_addr(mac.sa_data);
644 random_mac = true;
645 }
646
647 err = ltq_etop_set_mac_address(dev, &mac);
648 if (err)
649 goto err_netdev;
650
651 /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
652 if (random_mac)
653 dev->addr_assign_type = NET_ADDR_RANDOM;
654
655 ltq_etop_set_multicast_list(dev);
656 err = ltq_etop_mdio_init(dev);
657 if (err)
658 goto err_netdev;
659 return 0;
660
661 err_netdev:
662 unregister_netdev(dev);
663 free_netdev(dev);
664 err_hw:
665 ltq_etop_hw_exit(dev);
666 return err;
667 }
668
669 static void
670 ltq_etop_tx_timeout(struct net_device *dev)
671 {
672 int err;
673
674 ltq_etop_hw_exit(dev);
675 err = ltq_etop_hw_init(dev);
676 if (err)
677 goto err_hw;
678 dev->trans_start = jiffies;
679 netif_wake_queue(dev);
680 return;
681
682 err_hw:
683 ltq_etop_hw_exit(dev);
684 netdev_err(dev, "failed to restart etop after TX timeout\n");
685 }
686
687 static const struct net_device_ops ltq_eth_netdev_ops = {
688 .ndo_open = ltq_etop_open,
689 .ndo_stop = ltq_etop_stop,
690 .ndo_start_xmit = ltq_etop_tx,
691 .ndo_change_mtu = ltq_etop_change_mtu,
692 .ndo_do_ioctl = ltq_etop_ioctl,
693 .ndo_set_mac_address = ltq_etop_set_mac_address,
694 .ndo_validate_addr = eth_validate_addr,
695 .ndo_set_rx_mode = ltq_etop_set_multicast_list,
696 .ndo_select_queue = ltq_etop_select_queue,
697 .ndo_init = ltq_etop_init,
698 .ndo_tx_timeout = ltq_etop_tx_timeout,
699 };
700
701 static int __init
702 ltq_etop_probe(struct platform_device *pdev)
703 {
704 struct net_device *dev;
705 struct ltq_etop_priv *priv;
706 struct resource *res;
707 int err;
708 int i;
709
710 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
711 if (!res) {
712 dev_err(&pdev->dev, "failed to get etop resource\n");
713 err = -ENOENT;
714 goto err_out;
715 }
716
717 res = devm_request_mem_region(&pdev->dev, res->start,
718 resource_size(res), dev_name(&pdev->dev));
719 if (!res) {
720 dev_err(&pdev->dev, "failed to request etop resource\n");
721 err = -EBUSY;
722 goto err_out;
723 }
724
725 ltq_etop_membase = devm_ioremap_nocache(&pdev->dev,
726 res->start, resource_size(res));
727 if (!ltq_etop_membase) {
728 dev_err(&pdev->dev, "failed to remap etop engine %d\n",
729 pdev->id);
730 err = -ENOMEM;
731 goto err_out;
732 }
733
734 dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
735 if (!dev) {
736 err = -ENOMEM;
737 goto err_out;
738 }
739 strcpy(dev->name, "eth%d");
740 dev->netdev_ops = &ltq_eth_netdev_ops;
741 dev->ethtool_ops = &ltq_etop_ethtool_ops;
742 priv = netdev_priv(dev);
743 priv->res = res;
744 priv->pdev = pdev;
745 priv->pldata = dev_get_platdata(&pdev->dev);
746 priv->netdev = dev;
747 spin_lock_init(&priv->lock);
748
749 for (i = 0; i < MAX_DMA_CHAN; i++) {
750 if (IS_TX(i))
751 netif_napi_add(dev, &priv->ch[i].napi,
752 ltq_etop_poll_tx, 8);
753 else if (IS_RX(i))
754 netif_napi_add(dev, &priv->ch[i].napi,
755 ltq_etop_poll_rx, 32);
756 priv->ch[i].netdev = dev;
757 }
758
759 err = register_netdev(dev);
760 if (err)
761 goto err_free;
762
763 platform_set_drvdata(pdev, dev);
764 return 0;
765
766 err_free:
767 free_netdev(dev);
768 err_out:
769 return err;
770 }
771
772 static int
773 ltq_etop_remove(struct platform_device *pdev)
774 {
775 struct net_device *dev = platform_get_drvdata(pdev);
776
777 if (dev) {
778 netif_tx_stop_all_queues(dev);
779 ltq_etop_hw_exit(dev);
780 ltq_etop_mdio_cleanup(dev);
781 unregister_netdev(dev);
782 }
783 return 0;
784 }
785
786 static struct platform_driver ltq_mii_driver = {
787 .remove = ltq_etop_remove,
788 .driver = {
789 .name = "ltq_etop",
790 },
791 };
792
793 int __init
794 init_ltq_etop(void)
795 {
796 int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
797
798 if (ret)
799 pr_err("ltq_etop: Error registering platform driver!");
800 return ret;
801 }
802
803 static void __exit
804 exit_ltq_etop(void)
805 {
806 platform_driver_unregister(&ltq_mii_driver);
807 }
808
809 module_init(init_ltq_etop);
810 module_exit(exit_ltq_etop);
811
812 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
813 MODULE_DESCRIPTION("Lantiq SoC ETOP");
814 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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