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[deliverable/linux.git] / drivers / net / ethernet / marvell / mv643xx_eth.c
1 /*
2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
37
38 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
39
40 #include <linux/init.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/in.h>
43 #include <linux/ip.h>
44 #include <linux/tcp.h>
45 #include <linux/udp.h>
46 #include <linux/etherdevice.h>
47 #include <linux/delay.h>
48 #include <linux/ethtool.h>
49 #include <linux/platform_device.h>
50 #include <linux/module.h>
51 #include <linux/kernel.h>
52 #include <linux/spinlock.h>
53 #include <linux/workqueue.h>
54 #include <linux/phy.h>
55 #include <linux/mv643xx_eth.h>
56 #include <linux/io.h>
57 #include <linux/types.h>
58 #include <linux/inet_lro.h>
59 #include <linux/slab.h>
60 #include <asm/system.h>
61
62 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
63 static char mv643xx_eth_driver_version[] = "1.4";
64
65
66 /*
67 * Registers shared between all ports.
68 */
69 #define PHY_ADDR 0x0000
70 #define SMI_REG 0x0004
71 #define SMI_BUSY 0x10000000
72 #define SMI_READ_VALID 0x08000000
73 #define SMI_OPCODE_READ 0x04000000
74 #define SMI_OPCODE_WRITE 0x00000000
75 #define ERR_INT_CAUSE 0x0080
76 #define ERR_INT_SMI_DONE 0x00000010
77 #define ERR_INT_MASK 0x0084
78 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
79 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
80 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
81 #define WINDOW_BAR_ENABLE 0x0290
82 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
83
84 /*
85 * Main per-port registers. These live at offset 0x0400 for
86 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
87 */
88 #define PORT_CONFIG 0x0000
89 #define UNICAST_PROMISCUOUS_MODE 0x00000001
90 #define PORT_CONFIG_EXT 0x0004
91 #define MAC_ADDR_LOW 0x0014
92 #define MAC_ADDR_HIGH 0x0018
93 #define SDMA_CONFIG 0x001c
94 #define TX_BURST_SIZE_16_64BIT 0x01000000
95 #define TX_BURST_SIZE_4_64BIT 0x00800000
96 #define BLM_TX_NO_SWAP 0x00000020
97 #define BLM_RX_NO_SWAP 0x00000010
98 #define RX_BURST_SIZE_16_64BIT 0x00000008
99 #define RX_BURST_SIZE_4_64BIT 0x00000004
100 #define PORT_SERIAL_CONTROL 0x003c
101 #define SET_MII_SPEED_TO_100 0x01000000
102 #define SET_GMII_SPEED_TO_1000 0x00800000
103 #define SET_FULL_DUPLEX_MODE 0x00200000
104 #define MAX_RX_PACKET_9700BYTE 0x000a0000
105 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
106 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
107 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
108 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
109 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
110 #define FORCE_LINK_PASS 0x00000002
111 #define SERIAL_PORT_ENABLE 0x00000001
112 #define PORT_STATUS 0x0044
113 #define TX_FIFO_EMPTY 0x00000400
114 #define TX_IN_PROGRESS 0x00000080
115 #define PORT_SPEED_MASK 0x00000030
116 #define PORT_SPEED_1000 0x00000010
117 #define PORT_SPEED_100 0x00000020
118 #define PORT_SPEED_10 0x00000000
119 #define FLOW_CONTROL_ENABLED 0x00000008
120 #define FULL_DUPLEX 0x00000004
121 #define LINK_UP 0x00000002
122 #define TXQ_COMMAND 0x0048
123 #define TXQ_FIX_PRIO_CONF 0x004c
124 #define TX_BW_RATE 0x0050
125 #define TX_BW_MTU 0x0058
126 #define TX_BW_BURST 0x005c
127 #define INT_CAUSE 0x0060
128 #define INT_TX_END 0x07f80000
129 #define INT_TX_END_0 0x00080000
130 #define INT_RX 0x000003fc
131 #define INT_RX_0 0x00000004
132 #define INT_EXT 0x00000002
133 #define INT_CAUSE_EXT 0x0064
134 #define INT_EXT_LINK_PHY 0x00110000
135 #define INT_EXT_TX 0x000000ff
136 #define INT_MASK 0x0068
137 #define INT_MASK_EXT 0x006c
138 #define TX_FIFO_URGENT_THRESHOLD 0x0074
139 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
140 #define TX_BW_RATE_MOVED 0x00e0
141 #define TX_BW_MTU_MOVED 0x00e8
142 #define TX_BW_BURST_MOVED 0x00ec
143 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
144 #define RXQ_COMMAND 0x0280
145 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
146 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
147 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
148 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
149
150 /*
151 * Misc per-port registers.
152 */
153 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
154 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
155 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
156 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
157
158
159 /*
160 * SDMA configuration register default value.
161 */
162 #if defined(__BIG_ENDIAN)
163 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
164 (RX_BURST_SIZE_4_64BIT | \
165 TX_BURST_SIZE_4_64BIT)
166 #elif defined(__LITTLE_ENDIAN)
167 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
168 (RX_BURST_SIZE_4_64BIT | \
169 BLM_RX_NO_SWAP | \
170 BLM_TX_NO_SWAP | \
171 TX_BURST_SIZE_4_64BIT)
172 #else
173 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
174 #endif
175
176
177 /*
178 * Misc definitions.
179 */
180 #define DEFAULT_RX_QUEUE_SIZE 128
181 #define DEFAULT_TX_QUEUE_SIZE 256
182 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
183
184
185 /*
186 * RX/TX descriptors.
187 */
188 #if defined(__BIG_ENDIAN)
189 struct rx_desc {
190 u16 byte_cnt; /* Descriptor buffer byte count */
191 u16 buf_size; /* Buffer size */
192 u32 cmd_sts; /* Descriptor command status */
193 u32 next_desc_ptr; /* Next descriptor pointer */
194 u32 buf_ptr; /* Descriptor buffer pointer */
195 };
196
197 struct tx_desc {
198 u16 byte_cnt; /* buffer byte count */
199 u16 l4i_chk; /* CPU provided TCP checksum */
200 u32 cmd_sts; /* Command/status field */
201 u32 next_desc_ptr; /* Pointer to next descriptor */
202 u32 buf_ptr; /* pointer to buffer for this descriptor*/
203 };
204 #elif defined(__LITTLE_ENDIAN)
205 struct rx_desc {
206 u32 cmd_sts; /* Descriptor command status */
207 u16 buf_size; /* Buffer size */
208 u16 byte_cnt; /* Descriptor buffer byte count */
209 u32 buf_ptr; /* Descriptor buffer pointer */
210 u32 next_desc_ptr; /* Next descriptor pointer */
211 };
212
213 struct tx_desc {
214 u32 cmd_sts; /* Command/status field */
215 u16 l4i_chk; /* CPU provided TCP checksum */
216 u16 byte_cnt; /* buffer byte count */
217 u32 buf_ptr; /* pointer to buffer for this descriptor*/
218 u32 next_desc_ptr; /* Pointer to next descriptor */
219 };
220 #else
221 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
222 #endif
223
224 /* RX & TX descriptor command */
225 #define BUFFER_OWNED_BY_DMA 0x80000000
226
227 /* RX & TX descriptor status */
228 #define ERROR_SUMMARY 0x00000001
229
230 /* RX descriptor status */
231 #define LAYER_4_CHECKSUM_OK 0x40000000
232 #define RX_ENABLE_INTERRUPT 0x20000000
233 #define RX_FIRST_DESC 0x08000000
234 #define RX_LAST_DESC 0x04000000
235 #define RX_IP_HDR_OK 0x02000000
236 #define RX_PKT_IS_IPV4 0x01000000
237 #define RX_PKT_IS_ETHERNETV2 0x00800000
238 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
239 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
240 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
241
242 /* TX descriptor command */
243 #define TX_ENABLE_INTERRUPT 0x00800000
244 #define GEN_CRC 0x00400000
245 #define TX_FIRST_DESC 0x00200000
246 #define TX_LAST_DESC 0x00100000
247 #define ZERO_PADDING 0x00080000
248 #define GEN_IP_V4_CHECKSUM 0x00040000
249 #define GEN_TCP_UDP_CHECKSUM 0x00020000
250 #define UDP_FRAME 0x00010000
251 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
252 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
253
254 #define TX_IHL_SHIFT 11
255
256
257 /* global *******************************************************************/
258 struct mv643xx_eth_shared_private {
259 /*
260 * Ethernet controller base address.
261 */
262 void __iomem *base;
263
264 /*
265 * Points at the right SMI instance to use.
266 */
267 struct mv643xx_eth_shared_private *smi;
268
269 /*
270 * Provides access to local SMI interface.
271 */
272 struct mii_bus *smi_bus;
273
274 /*
275 * If we have access to the error interrupt pin (which is
276 * somewhat misnamed as it not only reflects internal errors
277 * but also reflects SMI completion), use that to wait for
278 * SMI access completion instead of polling the SMI busy bit.
279 */
280 int err_interrupt;
281 wait_queue_head_t smi_busy_wait;
282
283 /*
284 * Per-port MBUS window access register value.
285 */
286 u32 win_protect;
287
288 /*
289 * Hardware-specific parameters.
290 */
291 unsigned int t_clk;
292 int extended_rx_coal_limit;
293 int tx_bw_control;
294 int tx_csum_limit;
295 };
296
297 #define TX_BW_CONTROL_ABSENT 0
298 #define TX_BW_CONTROL_OLD_LAYOUT 1
299 #define TX_BW_CONTROL_NEW_LAYOUT 2
300
301 static int mv643xx_eth_open(struct net_device *dev);
302 static int mv643xx_eth_stop(struct net_device *dev);
303
304
305 /* per-port *****************************************************************/
306 struct mib_counters {
307 u64 good_octets_received;
308 u32 bad_octets_received;
309 u32 internal_mac_transmit_err;
310 u32 good_frames_received;
311 u32 bad_frames_received;
312 u32 broadcast_frames_received;
313 u32 multicast_frames_received;
314 u32 frames_64_octets;
315 u32 frames_65_to_127_octets;
316 u32 frames_128_to_255_octets;
317 u32 frames_256_to_511_octets;
318 u32 frames_512_to_1023_octets;
319 u32 frames_1024_to_max_octets;
320 u64 good_octets_sent;
321 u32 good_frames_sent;
322 u32 excessive_collision;
323 u32 multicast_frames_sent;
324 u32 broadcast_frames_sent;
325 u32 unrec_mac_control_received;
326 u32 fc_sent;
327 u32 good_fc_received;
328 u32 bad_fc_received;
329 u32 undersize_received;
330 u32 fragments_received;
331 u32 oversize_received;
332 u32 jabber_received;
333 u32 mac_receive_error;
334 u32 bad_crc_event;
335 u32 collision;
336 u32 late_collision;
337 };
338
339 struct lro_counters {
340 u32 lro_aggregated;
341 u32 lro_flushed;
342 u32 lro_no_desc;
343 };
344
345 struct rx_queue {
346 int index;
347
348 int rx_ring_size;
349
350 int rx_desc_count;
351 int rx_curr_desc;
352 int rx_used_desc;
353
354 struct rx_desc *rx_desc_area;
355 dma_addr_t rx_desc_dma;
356 int rx_desc_area_size;
357 struct sk_buff **rx_skb;
358
359 struct net_lro_mgr lro_mgr;
360 struct net_lro_desc lro_arr[8];
361 };
362
363 struct tx_queue {
364 int index;
365
366 int tx_ring_size;
367
368 int tx_desc_count;
369 int tx_curr_desc;
370 int tx_used_desc;
371
372 struct tx_desc *tx_desc_area;
373 dma_addr_t tx_desc_dma;
374 int tx_desc_area_size;
375
376 struct sk_buff_head tx_skb;
377
378 unsigned long tx_packets;
379 unsigned long tx_bytes;
380 unsigned long tx_dropped;
381 };
382
383 struct mv643xx_eth_private {
384 struct mv643xx_eth_shared_private *shared;
385 void __iomem *base;
386 int port_num;
387
388 struct net_device *dev;
389
390 struct phy_device *phy;
391
392 struct timer_list mib_counters_timer;
393 spinlock_t mib_counters_lock;
394 struct mib_counters mib_counters;
395
396 struct lro_counters lro_counters;
397
398 struct work_struct tx_timeout_task;
399
400 struct napi_struct napi;
401 u32 int_mask;
402 u8 oom;
403 u8 work_link;
404 u8 work_tx;
405 u8 work_tx_end;
406 u8 work_rx;
407 u8 work_rx_refill;
408
409 int skb_size;
410 struct sk_buff_head rx_recycle;
411
412 /*
413 * RX state.
414 */
415 int rx_ring_size;
416 unsigned long rx_desc_sram_addr;
417 int rx_desc_sram_size;
418 int rxq_count;
419 struct timer_list rx_oom;
420 struct rx_queue rxq[8];
421
422 /*
423 * TX state.
424 */
425 int tx_ring_size;
426 unsigned long tx_desc_sram_addr;
427 int tx_desc_sram_size;
428 int txq_count;
429 struct tx_queue txq[8];
430 };
431
432
433 /* port register accessors **************************************************/
434 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
435 {
436 return readl(mp->shared->base + offset);
437 }
438
439 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
440 {
441 return readl(mp->base + offset);
442 }
443
444 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
445 {
446 writel(data, mp->shared->base + offset);
447 }
448
449 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
450 {
451 writel(data, mp->base + offset);
452 }
453
454
455 /* rxq/txq helper functions *************************************************/
456 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
457 {
458 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
459 }
460
461 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
462 {
463 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
464 }
465
466 static void rxq_enable(struct rx_queue *rxq)
467 {
468 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
469 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
470 }
471
472 static void rxq_disable(struct rx_queue *rxq)
473 {
474 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
475 u8 mask = 1 << rxq->index;
476
477 wrlp(mp, RXQ_COMMAND, mask << 8);
478 while (rdlp(mp, RXQ_COMMAND) & mask)
479 udelay(10);
480 }
481
482 static void txq_reset_hw_ptr(struct tx_queue *txq)
483 {
484 struct mv643xx_eth_private *mp = txq_to_mp(txq);
485 u32 addr;
486
487 addr = (u32)txq->tx_desc_dma;
488 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
489 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
490 }
491
492 static void txq_enable(struct tx_queue *txq)
493 {
494 struct mv643xx_eth_private *mp = txq_to_mp(txq);
495 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
496 }
497
498 static void txq_disable(struct tx_queue *txq)
499 {
500 struct mv643xx_eth_private *mp = txq_to_mp(txq);
501 u8 mask = 1 << txq->index;
502
503 wrlp(mp, TXQ_COMMAND, mask << 8);
504 while (rdlp(mp, TXQ_COMMAND) & mask)
505 udelay(10);
506 }
507
508 static void txq_maybe_wake(struct tx_queue *txq)
509 {
510 struct mv643xx_eth_private *mp = txq_to_mp(txq);
511 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
512
513 if (netif_tx_queue_stopped(nq)) {
514 __netif_tx_lock(nq, smp_processor_id());
515 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
516 netif_tx_wake_queue(nq);
517 __netif_tx_unlock(nq);
518 }
519 }
520
521
522 /* rx napi ******************************************************************/
523 static int
524 mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
525 u64 *hdr_flags, void *priv)
526 {
527 unsigned long cmd_sts = (unsigned long)priv;
528
529 /*
530 * Make sure that this packet is Ethernet II, is not VLAN
531 * tagged, is IPv4, has a valid IP header, and is TCP.
532 */
533 if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
534 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
535 RX_PKT_IS_VLAN_TAGGED)) !=
536 (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
537 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
538 return -1;
539
540 skb_reset_network_header(skb);
541 skb_set_transport_header(skb, ip_hdrlen(skb));
542 *iphdr = ip_hdr(skb);
543 *tcph = tcp_hdr(skb);
544 *hdr_flags = LRO_IPV4 | LRO_TCP;
545
546 return 0;
547 }
548
549 static int rxq_process(struct rx_queue *rxq, int budget)
550 {
551 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
552 struct net_device_stats *stats = &mp->dev->stats;
553 int lro_flush_needed;
554 int rx;
555
556 lro_flush_needed = 0;
557 rx = 0;
558 while (rx < budget && rxq->rx_desc_count) {
559 struct rx_desc *rx_desc;
560 unsigned int cmd_sts;
561 struct sk_buff *skb;
562 u16 byte_cnt;
563
564 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
565
566 cmd_sts = rx_desc->cmd_sts;
567 if (cmd_sts & BUFFER_OWNED_BY_DMA)
568 break;
569 rmb();
570
571 skb = rxq->rx_skb[rxq->rx_curr_desc];
572 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
573
574 rxq->rx_curr_desc++;
575 if (rxq->rx_curr_desc == rxq->rx_ring_size)
576 rxq->rx_curr_desc = 0;
577
578 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
579 rx_desc->buf_size, DMA_FROM_DEVICE);
580 rxq->rx_desc_count--;
581 rx++;
582
583 mp->work_rx_refill |= 1 << rxq->index;
584
585 byte_cnt = rx_desc->byte_cnt;
586
587 /*
588 * Update statistics.
589 *
590 * Note that the descriptor byte count includes 2 dummy
591 * bytes automatically inserted by the hardware at the
592 * start of the packet (which we don't count), and a 4
593 * byte CRC at the end of the packet (which we do count).
594 */
595 stats->rx_packets++;
596 stats->rx_bytes += byte_cnt - 2;
597
598 /*
599 * In case we received a packet without first / last bits
600 * on, or the error summary bit is set, the packet needs
601 * to be dropped.
602 */
603 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
604 != (RX_FIRST_DESC | RX_LAST_DESC))
605 goto err;
606
607 /*
608 * The -4 is for the CRC in the trailer of the
609 * received packet
610 */
611 skb_put(skb, byte_cnt - 2 - 4);
612
613 if (cmd_sts & LAYER_4_CHECKSUM_OK)
614 skb->ip_summed = CHECKSUM_UNNECESSARY;
615 skb->protocol = eth_type_trans(skb, mp->dev);
616
617 if (skb->dev->features & NETIF_F_LRO &&
618 skb->ip_summed == CHECKSUM_UNNECESSARY) {
619 lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
620 lro_flush_needed = 1;
621 } else
622 netif_receive_skb(skb);
623
624 continue;
625
626 err:
627 stats->rx_dropped++;
628
629 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
630 (RX_FIRST_DESC | RX_LAST_DESC)) {
631 if (net_ratelimit())
632 netdev_err(mp->dev,
633 "received packet spanning multiple descriptors\n");
634 }
635
636 if (cmd_sts & ERROR_SUMMARY)
637 stats->rx_errors++;
638
639 dev_kfree_skb(skb);
640 }
641
642 if (lro_flush_needed)
643 lro_flush_all(&rxq->lro_mgr);
644
645 if (rx < budget)
646 mp->work_rx &= ~(1 << rxq->index);
647
648 return rx;
649 }
650
651 static int rxq_refill(struct rx_queue *rxq, int budget)
652 {
653 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
654 int refilled;
655
656 refilled = 0;
657 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
658 struct sk_buff *skb;
659 int rx;
660 struct rx_desc *rx_desc;
661 int size;
662
663 skb = __skb_dequeue(&mp->rx_recycle);
664 if (skb == NULL)
665 skb = dev_alloc_skb(mp->skb_size);
666
667 if (skb == NULL) {
668 mp->oom = 1;
669 goto oom;
670 }
671
672 if (SKB_DMA_REALIGN)
673 skb_reserve(skb, SKB_DMA_REALIGN);
674
675 refilled++;
676 rxq->rx_desc_count++;
677
678 rx = rxq->rx_used_desc++;
679 if (rxq->rx_used_desc == rxq->rx_ring_size)
680 rxq->rx_used_desc = 0;
681
682 rx_desc = rxq->rx_desc_area + rx;
683
684 size = skb->end - skb->data;
685 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
686 skb->data, size,
687 DMA_FROM_DEVICE);
688 rx_desc->buf_size = size;
689 rxq->rx_skb[rx] = skb;
690 wmb();
691 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
692 wmb();
693
694 /*
695 * The hardware automatically prepends 2 bytes of
696 * dummy data to each received packet, so that the
697 * IP header ends up 16-byte aligned.
698 */
699 skb_reserve(skb, 2);
700 }
701
702 if (refilled < budget)
703 mp->work_rx_refill &= ~(1 << rxq->index);
704
705 oom:
706 return refilled;
707 }
708
709
710 /* tx ***********************************************************************/
711 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
712 {
713 int frag;
714
715 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
716 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
717
718 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
719 return 1;
720 }
721
722 return 0;
723 }
724
725 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
726 {
727 struct mv643xx_eth_private *mp = txq_to_mp(txq);
728 int nr_frags = skb_shinfo(skb)->nr_frags;
729 int frag;
730
731 for (frag = 0; frag < nr_frags; frag++) {
732 skb_frag_t *this_frag;
733 int tx_index;
734 struct tx_desc *desc;
735
736 this_frag = &skb_shinfo(skb)->frags[frag];
737 tx_index = txq->tx_curr_desc++;
738 if (txq->tx_curr_desc == txq->tx_ring_size)
739 txq->tx_curr_desc = 0;
740 desc = &txq->tx_desc_area[tx_index];
741
742 /*
743 * The last fragment will generate an interrupt
744 * which will free the skb on TX completion.
745 */
746 if (frag == nr_frags - 1) {
747 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
748 ZERO_PADDING | TX_LAST_DESC |
749 TX_ENABLE_INTERRUPT;
750 } else {
751 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
752 }
753
754 desc->l4i_chk = 0;
755 desc->byte_cnt = skb_frag_size(this_frag);
756 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
757 this_frag, 0,
758 skb_frag_size(this_frag),
759 DMA_TO_DEVICE);
760 }
761 }
762
763 static inline __be16 sum16_as_be(__sum16 sum)
764 {
765 return (__force __be16)sum;
766 }
767
768 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
769 {
770 struct mv643xx_eth_private *mp = txq_to_mp(txq);
771 int nr_frags = skb_shinfo(skb)->nr_frags;
772 int tx_index;
773 struct tx_desc *desc;
774 u32 cmd_sts;
775 u16 l4i_chk;
776 int length;
777
778 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
779 l4i_chk = 0;
780
781 if (skb->ip_summed == CHECKSUM_PARTIAL) {
782 int hdr_len;
783 int tag_bytes;
784
785 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
786 skb->protocol != htons(ETH_P_8021Q));
787
788 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
789 tag_bytes = hdr_len - ETH_HLEN;
790 if (skb->len - hdr_len > mp->shared->tx_csum_limit ||
791 unlikely(tag_bytes & ~12)) {
792 if (skb_checksum_help(skb) == 0)
793 goto no_csum;
794 kfree_skb(skb);
795 return 1;
796 }
797
798 if (tag_bytes & 4)
799 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
800 if (tag_bytes & 8)
801 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
802
803 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
804 GEN_IP_V4_CHECKSUM |
805 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
806
807 switch (ip_hdr(skb)->protocol) {
808 case IPPROTO_UDP:
809 cmd_sts |= UDP_FRAME;
810 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
811 break;
812 case IPPROTO_TCP:
813 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
814 break;
815 default:
816 BUG();
817 }
818 } else {
819 no_csum:
820 /* Errata BTS #50, IHL must be 5 if no HW checksum */
821 cmd_sts |= 5 << TX_IHL_SHIFT;
822 }
823
824 tx_index = txq->tx_curr_desc++;
825 if (txq->tx_curr_desc == txq->tx_ring_size)
826 txq->tx_curr_desc = 0;
827 desc = &txq->tx_desc_area[tx_index];
828
829 if (nr_frags) {
830 txq_submit_frag_skb(txq, skb);
831 length = skb_headlen(skb);
832 } else {
833 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
834 length = skb->len;
835 }
836
837 desc->l4i_chk = l4i_chk;
838 desc->byte_cnt = length;
839 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
840 length, DMA_TO_DEVICE);
841
842 __skb_queue_tail(&txq->tx_skb, skb);
843
844 skb_tx_timestamp(skb);
845
846 /* ensure all other descriptors are written before first cmd_sts */
847 wmb();
848 desc->cmd_sts = cmd_sts;
849
850 /* clear TX_END status */
851 mp->work_tx_end &= ~(1 << txq->index);
852
853 /* ensure all descriptors are written before poking hardware */
854 wmb();
855 txq_enable(txq);
856
857 txq->tx_desc_count += nr_frags + 1;
858
859 return 0;
860 }
861
862 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
863 {
864 struct mv643xx_eth_private *mp = netdev_priv(dev);
865 int length, queue;
866 struct tx_queue *txq;
867 struct netdev_queue *nq;
868
869 queue = skb_get_queue_mapping(skb);
870 txq = mp->txq + queue;
871 nq = netdev_get_tx_queue(dev, queue);
872
873 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
874 txq->tx_dropped++;
875 netdev_printk(KERN_DEBUG, dev,
876 "failed to linearize skb with tiny unaligned fragment\n");
877 return NETDEV_TX_BUSY;
878 }
879
880 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
881 if (net_ratelimit())
882 netdev_err(dev, "tx queue full?!\n");
883 kfree_skb(skb);
884 return NETDEV_TX_OK;
885 }
886
887 length = skb->len;
888
889 if (!txq_submit_skb(txq, skb)) {
890 int entries_left;
891
892 txq->tx_bytes += length;
893 txq->tx_packets++;
894
895 entries_left = txq->tx_ring_size - txq->tx_desc_count;
896 if (entries_left < MAX_SKB_FRAGS + 1)
897 netif_tx_stop_queue(nq);
898 }
899
900 return NETDEV_TX_OK;
901 }
902
903
904 /* tx napi ******************************************************************/
905 static void txq_kick(struct tx_queue *txq)
906 {
907 struct mv643xx_eth_private *mp = txq_to_mp(txq);
908 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
909 u32 hw_desc_ptr;
910 u32 expected_ptr;
911
912 __netif_tx_lock(nq, smp_processor_id());
913
914 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
915 goto out;
916
917 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
918 expected_ptr = (u32)txq->tx_desc_dma +
919 txq->tx_curr_desc * sizeof(struct tx_desc);
920
921 if (hw_desc_ptr != expected_ptr)
922 txq_enable(txq);
923
924 out:
925 __netif_tx_unlock(nq);
926
927 mp->work_tx_end &= ~(1 << txq->index);
928 }
929
930 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
931 {
932 struct mv643xx_eth_private *mp = txq_to_mp(txq);
933 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
934 int reclaimed;
935
936 __netif_tx_lock(nq, smp_processor_id());
937
938 reclaimed = 0;
939 while (reclaimed < budget && txq->tx_desc_count > 0) {
940 int tx_index;
941 struct tx_desc *desc;
942 u32 cmd_sts;
943 struct sk_buff *skb;
944
945 tx_index = txq->tx_used_desc;
946 desc = &txq->tx_desc_area[tx_index];
947 cmd_sts = desc->cmd_sts;
948
949 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
950 if (!force)
951 break;
952 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
953 }
954
955 txq->tx_used_desc = tx_index + 1;
956 if (txq->tx_used_desc == txq->tx_ring_size)
957 txq->tx_used_desc = 0;
958
959 reclaimed++;
960 txq->tx_desc_count--;
961
962 skb = NULL;
963 if (cmd_sts & TX_LAST_DESC)
964 skb = __skb_dequeue(&txq->tx_skb);
965
966 if (cmd_sts & ERROR_SUMMARY) {
967 netdev_info(mp->dev, "tx error\n");
968 mp->dev->stats.tx_errors++;
969 }
970
971 if (cmd_sts & TX_FIRST_DESC) {
972 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
973 desc->byte_cnt, DMA_TO_DEVICE);
974 } else {
975 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
976 desc->byte_cnt, DMA_TO_DEVICE);
977 }
978
979 if (skb != NULL) {
980 if (skb_queue_len(&mp->rx_recycle) <
981 mp->rx_ring_size &&
982 skb_recycle_check(skb, mp->skb_size))
983 __skb_queue_head(&mp->rx_recycle, skb);
984 else
985 dev_kfree_skb(skb);
986 }
987 }
988
989 __netif_tx_unlock(nq);
990
991 if (reclaimed < budget)
992 mp->work_tx &= ~(1 << txq->index);
993
994 return reclaimed;
995 }
996
997
998 /* tx rate control **********************************************************/
999 /*
1000 * Set total maximum TX rate (shared by all TX queues for this port)
1001 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1002 */
1003 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1004 {
1005 int token_rate;
1006 int mtu;
1007 int bucket_size;
1008
1009 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1010 if (token_rate > 1023)
1011 token_rate = 1023;
1012
1013 mtu = (mp->dev->mtu + 255) >> 8;
1014 if (mtu > 63)
1015 mtu = 63;
1016
1017 bucket_size = (burst + 255) >> 8;
1018 if (bucket_size > 65535)
1019 bucket_size = 65535;
1020
1021 switch (mp->shared->tx_bw_control) {
1022 case TX_BW_CONTROL_OLD_LAYOUT:
1023 wrlp(mp, TX_BW_RATE, token_rate);
1024 wrlp(mp, TX_BW_MTU, mtu);
1025 wrlp(mp, TX_BW_BURST, bucket_size);
1026 break;
1027 case TX_BW_CONTROL_NEW_LAYOUT:
1028 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1029 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1030 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1031 break;
1032 }
1033 }
1034
1035 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1036 {
1037 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1038 int token_rate;
1039 int bucket_size;
1040
1041 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1042 if (token_rate > 1023)
1043 token_rate = 1023;
1044
1045 bucket_size = (burst + 255) >> 8;
1046 if (bucket_size > 65535)
1047 bucket_size = 65535;
1048
1049 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1050 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1051 }
1052
1053 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1054 {
1055 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1056 int off;
1057 u32 val;
1058
1059 /*
1060 * Turn on fixed priority mode.
1061 */
1062 off = 0;
1063 switch (mp->shared->tx_bw_control) {
1064 case TX_BW_CONTROL_OLD_LAYOUT:
1065 off = TXQ_FIX_PRIO_CONF;
1066 break;
1067 case TX_BW_CONTROL_NEW_LAYOUT:
1068 off = TXQ_FIX_PRIO_CONF_MOVED;
1069 break;
1070 }
1071
1072 if (off) {
1073 val = rdlp(mp, off);
1074 val |= 1 << txq->index;
1075 wrlp(mp, off, val);
1076 }
1077 }
1078
1079
1080 /* mii management interface *************************************************/
1081 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1082 {
1083 struct mv643xx_eth_shared_private *msp = dev_id;
1084
1085 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1086 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1087 wake_up(&msp->smi_busy_wait);
1088 return IRQ_HANDLED;
1089 }
1090
1091 return IRQ_NONE;
1092 }
1093
1094 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1095 {
1096 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1097 }
1098
1099 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1100 {
1101 if (msp->err_interrupt == NO_IRQ) {
1102 int i;
1103
1104 for (i = 0; !smi_is_done(msp); i++) {
1105 if (i == 10)
1106 return -ETIMEDOUT;
1107 msleep(10);
1108 }
1109
1110 return 0;
1111 }
1112
1113 if (!smi_is_done(msp)) {
1114 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1115 msecs_to_jiffies(100));
1116 if (!smi_is_done(msp))
1117 return -ETIMEDOUT;
1118 }
1119
1120 return 0;
1121 }
1122
1123 static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
1124 {
1125 struct mv643xx_eth_shared_private *msp = bus->priv;
1126 void __iomem *smi_reg = msp->base + SMI_REG;
1127 int ret;
1128
1129 if (smi_wait_ready(msp)) {
1130 pr_warn("SMI bus busy timeout\n");
1131 return -ETIMEDOUT;
1132 }
1133
1134 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1135
1136 if (smi_wait_ready(msp)) {
1137 pr_warn("SMI bus busy timeout\n");
1138 return -ETIMEDOUT;
1139 }
1140
1141 ret = readl(smi_reg);
1142 if (!(ret & SMI_READ_VALID)) {
1143 pr_warn("SMI bus read not valid\n");
1144 return -ENODEV;
1145 }
1146
1147 return ret & 0xffff;
1148 }
1149
1150 static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1151 {
1152 struct mv643xx_eth_shared_private *msp = bus->priv;
1153 void __iomem *smi_reg = msp->base + SMI_REG;
1154
1155 if (smi_wait_ready(msp)) {
1156 pr_warn("SMI bus busy timeout\n");
1157 return -ETIMEDOUT;
1158 }
1159
1160 writel(SMI_OPCODE_WRITE | (reg << 21) |
1161 (addr << 16) | (val & 0xffff), smi_reg);
1162
1163 if (smi_wait_ready(msp)) {
1164 pr_warn("SMI bus busy timeout\n");
1165 return -ETIMEDOUT;
1166 }
1167
1168 return 0;
1169 }
1170
1171
1172 /* statistics ***************************************************************/
1173 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1174 {
1175 struct mv643xx_eth_private *mp = netdev_priv(dev);
1176 struct net_device_stats *stats = &dev->stats;
1177 unsigned long tx_packets = 0;
1178 unsigned long tx_bytes = 0;
1179 unsigned long tx_dropped = 0;
1180 int i;
1181
1182 for (i = 0; i < mp->txq_count; i++) {
1183 struct tx_queue *txq = mp->txq + i;
1184
1185 tx_packets += txq->tx_packets;
1186 tx_bytes += txq->tx_bytes;
1187 tx_dropped += txq->tx_dropped;
1188 }
1189
1190 stats->tx_packets = tx_packets;
1191 stats->tx_bytes = tx_bytes;
1192 stats->tx_dropped = tx_dropped;
1193
1194 return stats;
1195 }
1196
1197 static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
1198 {
1199 u32 lro_aggregated = 0;
1200 u32 lro_flushed = 0;
1201 u32 lro_no_desc = 0;
1202 int i;
1203
1204 for (i = 0; i < mp->rxq_count; i++) {
1205 struct rx_queue *rxq = mp->rxq + i;
1206
1207 lro_aggregated += rxq->lro_mgr.stats.aggregated;
1208 lro_flushed += rxq->lro_mgr.stats.flushed;
1209 lro_no_desc += rxq->lro_mgr.stats.no_desc;
1210 }
1211
1212 mp->lro_counters.lro_aggregated = lro_aggregated;
1213 mp->lro_counters.lro_flushed = lro_flushed;
1214 mp->lro_counters.lro_no_desc = lro_no_desc;
1215 }
1216
1217 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1218 {
1219 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1220 }
1221
1222 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1223 {
1224 int i;
1225
1226 for (i = 0; i < 0x80; i += 4)
1227 mib_read(mp, i);
1228 }
1229
1230 static void mib_counters_update(struct mv643xx_eth_private *mp)
1231 {
1232 struct mib_counters *p = &mp->mib_counters;
1233
1234 spin_lock_bh(&mp->mib_counters_lock);
1235 p->good_octets_received += mib_read(mp, 0x00);
1236 p->bad_octets_received += mib_read(mp, 0x08);
1237 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1238 p->good_frames_received += mib_read(mp, 0x10);
1239 p->bad_frames_received += mib_read(mp, 0x14);
1240 p->broadcast_frames_received += mib_read(mp, 0x18);
1241 p->multicast_frames_received += mib_read(mp, 0x1c);
1242 p->frames_64_octets += mib_read(mp, 0x20);
1243 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1244 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1245 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1246 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1247 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1248 p->good_octets_sent += mib_read(mp, 0x38);
1249 p->good_frames_sent += mib_read(mp, 0x40);
1250 p->excessive_collision += mib_read(mp, 0x44);
1251 p->multicast_frames_sent += mib_read(mp, 0x48);
1252 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1253 p->unrec_mac_control_received += mib_read(mp, 0x50);
1254 p->fc_sent += mib_read(mp, 0x54);
1255 p->good_fc_received += mib_read(mp, 0x58);
1256 p->bad_fc_received += mib_read(mp, 0x5c);
1257 p->undersize_received += mib_read(mp, 0x60);
1258 p->fragments_received += mib_read(mp, 0x64);
1259 p->oversize_received += mib_read(mp, 0x68);
1260 p->jabber_received += mib_read(mp, 0x6c);
1261 p->mac_receive_error += mib_read(mp, 0x70);
1262 p->bad_crc_event += mib_read(mp, 0x74);
1263 p->collision += mib_read(mp, 0x78);
1264 p->late_collision += mib_read(mp, 0x7c);
1265 spin_unlock_bh(&mp->mib_counters_lock);
1266
1267 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1268 }
1269
1270 static void mib_counters_timer_wrapper(unsigned long _mp)
1271 {
1272 struct mv643xx_eth_private *mp = (void *)_mp;
1273
1274 mib_counters_update(mp);
1275 }
1276
1277
1278 /* interrupt coalescing *****************************************************/
1279 /*
1280 * Hardware coalescing parameters are set in units of 64 t_clk
1281 * cycles. I.e.:
1282 *
1283 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1284 *
1285 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1286 *
1287 * In the ->set*() methods, we round the computed register value
1288 * to the nearest integer.
1289 */
1290 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1291 {
1292 u32 val = rdlp(mp, SDMA_CONFIG);
1293 u64 temp;
1294
1295 if (mp->shared->extended_rx_coal_limit)
1296 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1297 else
1298 temp = (val & 0x003fff00) >> 8;
1299
1300 temp *= 64000000;
1301 do_div(temp, mp->shared->t_clk);
1302
1303 return (unsigned int)temp;
1304 }
1305
1306 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1307 {
1308 u64 temp;
1309 u32 val;
1310
1311 temp = (u64)usec * mp->shared->t_clk;
1312 temp += 31999999;
1313 do_div(temp, 64000000);
1314
1315 val = rdlp(mp, SDMA_CONFIG);
1316 if (mp->shared->extended_rx_coal_limit) {
1317 if (temp > 0xffff)
1318 temp = 0xffff;
1319 val &= ~0x023fff80;
1320 val |= (temp & 0x8000) << 10;
1321 val |= (temp & 0x7fff) << 7;
1322 } else {
1323 if (temp > 0x3fff)
1324 temp = 0x3fff;
1325 val &= ~0x003fff00;
1326 val |= (temp & 0x3fff) << 8;
1327 }
1328 wrlp(mp, SDMA_CONFIG, val);
1329 }
1330
1331 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1332 {
1333 u64 temp;
1334
1335 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1336 temp *= 64000000;
1337 do_div(temp, mp->shared->t_clk);
1338
1339 return (unsigned int)temp;
1340 }
1341
1342 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1343 {
1344 u64 temp;
1345
1346 temp = (u64)usec * mp->shared->t_clk;
1347 temp += 31999999;
1348 do_div(temp, 64000000);
1349
1350 if (temp > 0x3fff)
1351 temp = 0x3fff;
1352
1353 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1354 }
1355
1356
1357 /* ethtool ******************************************************************/
1358 struct mv643xx_eth_stats {
1359 char stat_string[ETH_GSTRING_LEN];
1360 int sizeof_stat;
1361 int netdev_off;
1362 int mp_off;
1363 };
1364
1365 #define SSTAT(m) \
1366 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1367 offsetof(struct net_device, stats.m), -1 }
1368
1369 #define MIBSTAT(m) \
1370 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1371 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1372
1373 #define LROSTAT(m) \
1374 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1375 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1376
1377 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1378 SSTAT(rx_packets),
1379 SSTAT(tx_packets),
1380 SSTAT(rx_bytes),
1381 SSTAT(tx_bytes),
1382 SSTAT(rx_errors),
1383 SSTAT(tx_errors),
1384 SSTAT(rx_dropped),
1385 SSTAT(tx_dropped),
1386 MIBSTAT(good_octets_received),
1387 MIBSTAT(bad_octets_received),
1388 MIBSTAT(internal_mac_transmit_err),
1389 MIBSTAT(good_frames_received),
1390 MIBSTAT(bad_frames_received),
1391 MIBSTAT(broadcast_frames_received),
1392 MIBSTAT(multicast_frames_received),
1393 MIBSTAT(frames_64_octets),
1394 MIBSTAT(frames_65_to_127_octets),
1395 MIBSTAT(frames_128_to_255_octets),
1396 MIBSTAT(frames_256_to_511_octets),
1397 MIBSTAT(frames_512_to_1023_octets),
1398 MIBSTAT(frames_1024_to_max_octets),
1399 MIBSTAT(good_octets_sent),
1400 MIBSTAT(good_frames_sent),
1401 MIBSTAT(excessive_collision),
1402 MIBSTAT(multicast_frames_sent),
1403 MIBSTAT(broadcast_frames_sent),
1404 MIBSTAT(unrec_mac_control_received),
1405 MIBSTAT(fc_sent),
1406 MIBSTAT(good_fc_received),
1407 MIBSTAT(bad_fc_received),
1408 MIBSTAT(undersize_received),
1409 MIBSTAT(fragments_received),
1410 MIBSTAT(oversize_received),
1411 MIBSTAT(jabber_received),
1412 MIBSTAT(mac_receive_error),
1413 MIBSTAT(bad_crc_event),
1414 MIBSTAT(collision),
1415 MIBSTAT(late_collision),
1416 LROSTAT(lro_aggregated),
1417 LROSTAT(lro_flushed),
1418 LROSTAT(lro_no_desc),
1419 };
1420
1421 static int
1422 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1423 struct ethtool_cmd *cmd)
1424 {
1425 int err;
1426
1427 err = phy_read_status(mp->phy);
1428 if (err == 0)
1429 err = phy_ethtool_gset(mp->phy, cmd);
1430
1431 /*
1432 * The MAC does not support 1000baseT_Half.
1433 */
1434 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1435 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1436
1437 return err;
1438 }
1439
1440 static int
1441 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1442 struct ethtool_cmd *cmd)
1443 {
1444 u32 port_status;
1445
1446 port_status = rdlp(mp, PORT_STATUS);
1447
1448 cmd->supported = SUPPORTED_MII;
1449 cmd->advertising = ADVERTISED_MII;
1450 switch (port_status & PORT_SPEED_MASK) {
1451 case PORT_SPEED_10:
1452 ethtool_cmd_speed_set(cmd, SPEED_10);
1453 break;
1454 case PORT_SPEED_100:
1455 ethtool_cmd_speed_set(cmd, SPEED_100);
1456 break;
1457 case PORT_SPEED_1000:
1458 ethtool_cmd_speed_set(cmd, SPEED_1000);
1459 break;
1460 default:
1461 cmd->speed = -1;
1462 break;
1463 }
1464 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1465 cmd->port = PORT_MII;
1466 cmd->phy_address = 0;
1467 cmd->transceiver = XCVR_INTERNAL;
1468 cmd->autoneg = AUTONEG_DISABLE;
1469 cmd->maxtxpkt = 1;
1470 cmd->maxrxpkt = 1;
1471
1472 return 0;
1473 }
1474
1475 static int
1476 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1477 {
1478 struct mv643xx_eth_private *mp = netdev_priv(dev);
1479
1480 if (mp->phy != NULL)
1481 return mv643xx_eth_get_settings_phy(mp, cmd);
1482 else
1483 return mv643xx_eth_get_settings_phyless(mp, cmd);
1484 }
1485
1486 static int
1487 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1488 {
1489 struct mv643xx_eth_private *mp = netdev_priv(dev);
1490
1491 if (mp->phy == NULL)
1492 return -EINVAL;
1493
1494 /*
1495 * The MAC does not support 1000baseT_Half.
1496 */
1497 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1498
1499 return phy_ethtool_sset(mp->phy, cmd);
1500 }
1501
1502 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1503 struct ethtool_drvinfo *drvinfo)
1504 {
1505 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1506 sizeof(drvinfo->driver));
1507 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1508 sizeof(drvinfo->version));
1509 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1510 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1511 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1512 }
1513
1514 static int mv643xx_eth_nway_reset(struct net_device *dev)
1515 {
1516 struct mv643xx_eth_private *mp = netdev_priv(dev);
1517
1518 if (mp->phy == NULL)
1519 return -EINVAL;
1520
1521 return genphy_restart_aneg(mp->phy);
1522 }
1523
1524 static int
1525 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1526 {
1527 struct mv643xx_eth_private *mp = netdev_priv(dev);
1528
1529 ec->rx_coalesce_usecs = get_rx_coal(mp);
1530 ec->tx_coalesce_usecs = get_tx_coal(mp);
1531
1532 return 0;
1533 }
1534
1535 static int
1536 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1537 {
1538 struct mv643xx_eth_private *mp = netdev_priv(dev);
1539
1540 set_rx_coal(mp, ec->rx_coalesce_usecs);
1541 set_tx_coal(mp, ec->tx_coalesce_usecs);
1542
1543 return 0;
1544 }
1545
1546 static void
1547 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1548 {
1549 struct mv643xx_eth_private *mp = netdev_priv(dev);
1550
1551 er->rx_max_pending = 4096;
1552 er->tx_max_pending = 4096;
1553
1554 er->rx_pending = mp->rx_ring_size;
1555 er->tx_pending = mp->tx_ring_size;
1556 }
1557
1558 static int
1559 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1560 {
1561 struct mv643xx_eth_private *mp = netdev_priv(dev);
1562
1563 if (er->rx_mini_pending || er->rx_jumbo_pending)
1564 return -EINVAL;
1565
1566 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1567 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1568
1569 if (netif_running(dev)) {
1570 mv643xx_eth_stop(dev);
1571 if (mv643xx_eth_open(dev)) {
1572 netdev_err(dev,
1573 "fatal error on re-opening device after ring param change\n");
1574 return -ENOMEM;
1575 }
1576 }
1577
1578 return 0;
1579 }
1580
1581
1582 static int
1583 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1584 {
1585 struct mv643xx_eth_private *mp = netdev_priv(dev);
1586 bool rx_csum = features & NETIF_F_RXCSUM;
1587
1588 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1589
1590 return 0;
1591 }
1592
1593 static void mv643xx_eth_get_strings(struct net_device *dev,
1594 uint32_t stringset, uint8_t *data)
1595 {
1596 int i;
1597
1598 if (stringset == ETH_SS_STATS) {
1599 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1600 memcpy(data + i * ETH_GSTRING_LEN,
1601 mv643xx_eth_stats[i].stat_string,
1602 ETH_GSTRING_LEN);
1603 }
1604 }
1605 }
1606
1607 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1608 struct ethtool_stats *stats,
1609 uint64_t *data)
1610 {
1611 struct mv643xx_eth_private *mp = netdev_priv(dev);
1612 int i;
1613
1614 mv643xx_eth_get_stats(dev);
1615 mib_counters_update(mp);
1616 mv643xx_eth_grab_lro_stats(mp);
1617
1618 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1619 const struct mv643xx_eth_stats *stat;
1620 void *p;
1621
1622 stat = mv643xx_eth_stats + i;
1623
1624 if (stat->netdev_off >= 0)
1625 p = ((void *)mp->dev) + stat->netdev_off;
1626 else
1627 p = ((void *)mp) + stat->mp_off;
1628
1629 data[i] = (stat->sizeof_stat == 8) ?
1630 *(uint64_t *)p : *(uint32_t *)p;
1631 }
1632 }
1633
1634 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1635 {
1636 if (sset == ETH_SS_STATS)
1637 return ARRAY_SIZE(mv643xx_eth_stats);
1638
1639 return -EOPNOTSUPP;
1640 }
1641
1642 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1643 .get_settings = mv643xx_eth_get_settings,
1644 .set_settings = mv643xx_eth_set_settings,
1645 .get_drvinfo = mv643xx_eth_get_drvinfo,
1646 .nway_reset = mv643xx_eth_nway_reset,
1647 .get_link = ethtool_op_get_link,
1648 .get_coalesce = mv643xx_eth_get_coalesce,
1649 .set_coalesce = mv643xx_eth_set_coalesce,
1650 .get_ringparam = mv643xx_eth_get_ringparam,
1651 .set_ringparam = mv643xx_eth_set_ringparam,
1652 .get_strings = mv643xx_eth_get_strings,
1653 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1654 .get_sset_count = mv643xx_eth_get_sset_count,
1655 };
1656
1657
1658 /* address handling *********************************************************/
1659 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1660 {
1661 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1662 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1663
1664 addr[0] = (mac_h >> 24) & 0xff;
1665 addr[1] = (mac_h >> 16) & 0xff;
1666 addr[2] = (mac_h >> 8) & 0xff;
1667 addr[3] = mac_h & 0xff;
1668 addr[4] = (mac_l >> 8) & 0xff;
1669 addr[5] = mac_l & 0xff;
1670 }
1671
1672 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1673 {
1674 wrlp(mp, MAC_ADDR_HIGH,
1675 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1676 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1677 }
1678
1679 static u32 uc_addr_filter_mask(struct net_device *dev)
1680 {
1681 struct netdev_hw_addr *ha;
1682 u32 nibbles;
1683
1684 if (dev->flags & IFF_PROMISC)
1685 return 0;
1686
1687 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1688 netdev_for_each_uc_addr(ha, dev) {
1689 if (memcmp(dev->dev_addr, ha->addr, 5))
1690 return 0;
1691 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1692 return 0;
1693
1694 nibbles |= 1 << (ha->addr[5] & 0x0f);
1695 }
1696
1697 return nibbles;
1698 }
1699
1700 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1701 {
1702 struct mv643xx_eth_private *mp = netdev_priv(dev);
1703 u32 port_config;
1704 u32 nibbles;
1705 int i;
1706
1707 uc_addr_set(mp, dev->dev_addr);
1708
1709 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1710
1711 nibbles = uc_addr_filter_mask(dev);
1712 if (!nibbles) {
1713 port_config |= UNICAST_PROMISCUOUS_MODE;
1714 nibbles = 0xffff;
1715 }
1716
1717 for (i = 0; i < 16; i += 4) {
1718 int off = UNICAST_TABLE(mp->port_num) + i;
1719 u32 v;
1720
1721 v = 0;
1722 if (nibbles & 1)
1723 v |= 0x00000001;
1724 if (nibbles & 2)
1725 v |= 0x00000100;
1726 if (nibbles & 4)
1727 v |= 0x00010000;
1728 if (nibbles & 8)
1729 v |= 0x01000000;
1730 nibbles >>= 4;
1731
1732 wrl(mp, off, v);
1733 }
1734
1735 wrlp(mp, PORT_CONFIG, port_config);
1736 }
1737
1738 static int addr_crc(unsigned char *addr)
1739 {
1740 int crc = 0;
1741 int i;
1742
1743 for (i = 0; i < 6; i++) {
1744 int j;
1745
1746 crc = (crc ^ addr[i]) << 8;
1747 for (j = 7; j >= 0; j--) {
1748 if (crc & (0x100 << j))
1749 crc ^= 0x107 << j;
1750 }
1751 }
1752
1753 return crc;
1754 }
1755
1756 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1757 {
1758 struct mv643xx_eth_private *mp = netdev_priv(dev);
1759 u32 *mc_spec;
1760 u32 *mc_other;
1761 struct netdev_hw_addr *ha;
1762 int i;
1763
1764 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1765 int port_num;
1766 u32 accept;
1767
1768 oom:
1769 port_num = mp->port_num;
1770 accept = 0x01010101;
1771 for (i = 0; i < 0x100; i += 4) {
1772 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1773 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1774 }
1775 return;
1776 }
1777
1778 mc_spec = kmalloc(0x200, GFP_ATOMIC);
1779 if (mc_spec == NULL)
1780 goto oom;
1781 mc_other = mc_spec + (0x100 >> 2);
1782
1783 memset(mc_spec, 0, 0x100);
1784 memset(mc_other, 0, 0x100);
1785
1786 netdev_for_each_mc_addr(ha, dev) {
1787 u8 *a = ha->addr;
1788 u32 *table;
1789 int entry;
1790
1791 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1792 table = mc_spec;
1793 entry = a[5];
1794 } else {
1795 table = mc_other;
1796 entry = addr_crc(a);
1797 }
1798
1799 table[entry >> 2] |= 1 << (8 * (entry & 3));
1800 }
1801
1802 for (i = 0; i < 0x100; i += 4) {
1803 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1804 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1805 }
1806
1807 kfree(mc_spec);
1808 }
1809
1810 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1811 {
1812 mv643xx_eth_program_unicast_filter(dev);
1813 mv643xx_eth_program_multicast_filter(dev);
1814 }
1815
1816 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1817 {
1818 struct sockaddr *sa = addr;
1819
1820 if (!is_valid_ether_addr(sa->sa_data))
1821 return -EINVAL;
1822
1823 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1824
1825 netif_addr_lock_bh(dev);
1826 mv643xx_eth_program_unicast_filter(dev);
1827 netif_addr_unlock_bh(dev);
1828
1829 return 0;
1830 }
1831
1832
1833 /* rx/tx queue initialisation ***********************************************/
1834 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1835 {
1836 struct rx_queue *rxq = mp->rxq + index;
1837 struct rx_desc *rx_desc;
1838 int size;
1839 int i;
1840
1841 rxq->index = index;
1842
1843 rxq->rx_ring_size = mp->rx_ring_size;
1844
1845 rxq->rx_desc_count = 0;
1846 rxq->rx_curr_desc = 0;
1847 rxq->rx_used_desc = 0;
1848
1849 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1850
1851 if (index == 0 && size <= mp->rx_desc_sram_size) {
1852 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1853 mp->rx_desc_sram_size);
1854 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1855 } else {
1856 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1857 size, &rxq->rx_desc_dma,
1858 GFP_KERNEL);
1859 }
1860
1861 if (rxq->rx_desc_area == NULL) {
1862 netdev_err(mp->dev,
1863 "can't allocate rx ring (%d bytes)\n", size);
1864 goto out;
1865 }
1866 memset(rxq->rx_desc_area, 0, size);
1867
1868 rxq->rx_desc_area_size = size;
1869 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1870 GFP_KERNEL);
1871 if (rxq->rx_skb == NULL) {
1872 netdev_err(mp->dev, "can't allocate rx skb ring\n");
1873 goto out_free;
1874 }
1875
1876 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1877 for (i = 0; i < rxq->rx_ring_size; i++) {
1878 int nexti;
1879
1880 nexti = i + 1;
1881 if (nexti == rxq->rx_ring_size)
1882 nexti = 0;
1883
1884 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1885 nexti * sizeof(struct rx_desc);
1886 }
1887
1888 rxq->lro_mgr.dev = mp->dev;
1889 memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
1890 rxq->lro_mgr.features = LRO_F_NAPI;
1891 rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1892 rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1893 rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
1894 rxq->lro_mgr.max_aggr = 32;
1895 rxq->lro_mgr.frag_align_pad = 0;
1896 rxq->lro_mgr.lro_arr = rxq->lro_arr;
1897 rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
1898
1899 memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
1900
1901 return 0;
1902
1903
1904 out_free:
1905 if (index == 0 && size <= mp->rx_desc_sram_size)
1906 iounmap(rxq->rx_desc_area);
1907 else
1908 dma_free_coherent(mp->dev->dev.parent, size,
1909 rxq->rx_desc_area,
1910 rxq->rx_desc_dma);
1911
1912 out:
1913 return -ENOMEM;
1914 }
1915
1916 static void rxq_deinit(struct rx_queue *rxq)
1917 {
1918 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1919 int i;
1920
1921 rxq_disable(rxq);
1922
1923 for (i = 0; i < rxq->rx_ring_size; i++) {
1924 if (rxq->rx_skb[i]) {
1925 dev_kfree_skb(rxq->rx_skb[i]);
1926 rxq->rx_desc_count--;
1927 }
1928 }
1929
1930 if (rxq->rx_desc_count) {
1931 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
1932 rxq->rx_desc_count);
1933 }
1934
1935 if (rxq->index == 0 &&
1936 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1937 iounmap(rxq->rx_desc_area);
1938 else
1939 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
1940 rxq->rx_desc_area, rxq->rx_desc_dma);
1941
1942 kfree(rxq->rx_skb);
1943 }
1944
1945 static int txq_init(struct mv643xx_eth_private *mp, int index)
1946 {
1947 struct tx_queue *txq = mp->txq + index;
1948 struct tx_desc *tx_desc;
1949 int size;
1950 int i;
1951
1952 txq->index = index;
1953
1954 txq->tx_ring_size = mp->tx_ring_size;
1955
1956 txq->tx_desc_count = 0;
1957 txq->tx_curr_desc = 0;
1958 txq->tx_used_desc = 0;
1959
1960 size = txq->tx_ring_size * sizeof(struct tx_desc);
1961
1962 if (index == 0 && size <= mp->tx_desc_sram_size) {
1963 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1964 mp->tx_desc_sram_size);
1965 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1966 } else {
1967 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1968 size, &txq->tx_desc_dma,
1969 GFP_KERNEL);
1970 }
1971
1972 if (txq->tx_desc_area == NULL) {
1973 netdev_err(mp->dev,
1974 "can't allocate tx ring (%d bytes)\n", size);
1975 return -ENOMEM;
1976 }
1977 memset(txq->tx_desc_area, 0, size);
1978
1979 txq->tx_desc_area_size = size;
1980
1981 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1982 for (i = 0; i < txq->tx_ring_size; i++) {
1983 struct tx_desc *txd = tx_desc + i;
1984 int nexti;
1985
1986 nexti = i + 1;
1987 if (nexti == txq->tx_ring_size)
1988 nexti = 0;
1989
1990 txd->cmd_sts = 0;
1991 txd->next_desc_ptr = txq->tx_desc_dma +
1992 nexti * sizeof(struct tx_desc);
1993 }
1994
1995 skb_queue_head_init(&txq->tx_skb);
1996
1997 return 0;
1998 }
1999
2000 static void txq_deinit(struct tx_queue *txq)
2001 {
2002 struct mv643xx_eth_private *mp = txq_to_mp(txq);
2003
2004 txq_disable(txq);
2005 txq_reclaim(txq, txq->tx_ring_size, 1);
2006
2007 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2008
2009 if (txq->index == 0 &&
2010 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2011 iounmap(txq->tx_desc_area);
2012 else
2013 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2014 txq->tx_desc_area, txq->tx_desc_dma);
2015 }
2016
2017
2018 /* netdev ops and related ***************************************************/
2019 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2020 {
2021 u32 int_cause;
2022 u32 int_cause_ext;
2023
2024 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
2025 if (int_cause == 0)
2026 return 0;
2027
2028 int_cause_ext = 0;
2029 if (int_cause & INT_EXT) {
2030 int_cause &= ~INT_EXT;
2031 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2032 }
2033
2034 if (int_cause) {
2035 wrlp(mp, INT_CAUSE, ~int_cause);
2036 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2037 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
2038 mp->work_rx |= (int_cause & INT_RX) >> 2;
2039 }
2040
2041 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2042 if (int_cause_ext) {
2043 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2044 if (int_cause_ext & INT_EXT_LINK_PHY)
2045 mp->work_link = 1;
2046 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2047 }
2048
2049 return 1;
2050 }
2051
2052 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2053 {
2054 struct net_device *dev = (struct net_device *)dev_id;
2055 struct mv643xx_eth_private *mp = netdev_priv(dev);
2056
2057 if (unlikely(!mv643xx_eth_collect_events(mp)))
2058 return IRQ_NONE;
2059
2060 wrlp(mp, INT_MASK, 0);
2061 napi_schedule(&mp->napi);
2062
2063 return IRQ_HANDLED;
2064 }
2065
2066 static void handle_link_event(struct mv643xx_eth_private *mp)
2067 {
2068 struct net_device *dev = mp->dev;
2069 u32 port_status;
2070 int speed;
2071 int duplex;
2072 int fc;
2073
2074 port_status = rdlp(mp, PORT_STATUS);
2075 if (!(port_status & LINK_UP)) {
2076 if (netif_carrier_ok(dev)) {
2077 int i;
2078
2079 netdev_info(dev, "link down\n");
2080
2081 netif_carrier_off(dev);
2082
2083 for (i = 0; i < mp->txq_count; i++) {
2084 struct tx_queue *txq = mp->txq + i;
2085
2086 txq_reclaim(txq, txq->tx_ring_size, 1);
2087 txq_reset_hw_ptr(txq);
2088 }
2089 }
2090 return;
2091 }
2092
2093 switch (port_status & PORT_SPEED_MASK) {
2094 case PORT_SPEED_10:
2095 speed = 10;
2096 break;
2097 case PORT_SPEED_100:
2098 speed = 100;
2099 break;
2100 case PORT_SPEED_1000:
2101 speed = 1000;
2102 break;
2103 default:
2104 speed = -1;
2105 break;
2106 }
2107 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2108 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2109
2110 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2111 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2112
2113 if (!netif_carrier_ok(dev))
2114 netif_carrier_on(dev);
2115 }
2116
2117 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2118 {
2119 struct mv643xx_eth_private *mp;
2120 int work_done;
2121
2122 mp = container_of(napi, struct mv643xx_eth_private, napi);
2123
2124 if (unlikely(mp->oom)) {
2125 mp->oom = 0;
2126 del_timer(&mp->rx_oom);
2127 }
2128
2129 work_done = 0;
2130 while (work_done < budget) {
2131 u8 queue_mask;
2132 int queue;
2133 int work_tbd;
2134
2135 if (mp->work_link) {
2136 mp->work_link = 0;
2137 handle_link_event(mp);
2138 work_done++;
2139 continue;
2140 }
2141
2142 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2143 if (likely(!mp->oom))
2144 queue_mask |= mp->work_rx_refill;
2145
2146 if (!queue_mask) {
2147 if (mv643xx_eth_collect_events(mp))
2148 continue;
2149 break;
2150 }
2151
2152 queue = fls(queue_mask) - 1;
2153 queue_mask = 1 << queue;
2154
2155 work_tbd = budget - work_done;
2156 if (work_tbd > 16)
2157 work_tbd = 16;
2158
2159 if (mp->work_tx_end & queue_mask) {
2160 txq_kick(mp->txq + queue);
2161 } else if (mp->work_tx & queue_mask) {
2162 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2163 txq_maybe_wake(mp->txq + queue);
2164 } else if (mp->work_rx & queue_mask) {
2165 work_done += rxq_process(mp->rxq + queue, work_tbd);
2166 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2167 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2168 } else {
2169 BUG();
2170 }
2171 }
2172
2173 if (work_done < budget) {
2174 if (mp->oom)
2175 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2176 napi_complete(napi);
2177 wrlp(mp, INT_MASK, mp->int_mask);
2178 }
2179
2180 return work_done;
2181 }
2182
2183 static inline void oom_timer_wrapper(unsigned long data)
2184 {
2185 struct mv643xx_eth_private *mp = (void *)data;
2186
2187 napi_schedule(&mp->napi);
2188 }
2189
2190 static void phy_reset(struct mv643xx_eth_private *mp)
2191 {
2192 int data;
2193
2194 data = phy_read(mp->phy, MII_BMCR);
2195 if (data < 0)
2196 return;
2197
2198 data |= BMCR_RESET;
2199 if (phy_write(mp->phy, MII_BMCR, data) < 0)
2200 return;
2201
2202 do {
2203 data = phy_read(mp->phy, MII_BMCR);
2204 } while (data >= 0 && data & BMCR_RESET);
2205 }
2206
2207 static void port_start(struct mv643xx_eth_private *mp)
2208 {
2209 u32 pscr;
2210 int i;
2211
2212 /*
2213 * Perform PHY reset, if there is a PHY.
2214 */
2215 if (mp->phy != NULL) {
2216 struct ethtool_cmd cmd;
2217
2218 mv643xx_eth_get_settings(mp->dev, &cmd);
2219 phy_reset(mp);
2220 mv643xx_eth_set_settings(mp->dev, &cmd);
2221 }
2222
2223 /*
2224 * Configure basic link parameters.
2225 */
2226 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2227
2228 pscr |= SERIAL_PORT_ENABLE;
2229 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2230
2231 pscr |= DO_NOT_FORCE_LINK_FAIL;
2232 if (mp->phy == NULL)
2233 pscr |= FORCE_LINK_PASS;
2234 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2235
2236 /*
2237 * Configure TX path and queues.
2238 */
2239 tx_set_rate(mp, 1000000000, 16777216);
2240 for (i = 0; i < mp->txq_count; i++) {
2241 struct tx_queue *txq = mp->txq + i;
2242
2243 txq_reset_hw_ptr(txq);
2244 txq_set_rate(txq, 1000000000, 16777216);
2245 txq_set_fixed_prio_mode(txq);
2246 }
2247
2248 /*
2249 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2250 * frames to RX queue #0, and include the pseudo-header when
2251 * calculating receive checksums.
2252 */
2253 mv643xx_eth_set_features(mp->dev, mp->dev->features);
2254
2255 /*
2256 * Treat BPDUs as normal multicasts, and disable partition mode.
2257 */
2258 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2259
2260 /*
2261 * Add configured unicast addresses to address filter table.
2262 */
2263 mv643xx_eth_program_unicast_filter(mp->dev);
2264
2265 /*
2266 * Enable the receive queues.
2267 */
2268 for (i = 0; i < mp->rxq_count; i++) {
2269 struct rx_queue *rxq = mp->rxq + i;
2270 u32 addr;
2271
2272 addr = (u32)rxq->rx_desc_dma;
2273 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2274 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2275
2276 rxq_enable(rxq);
2277 }
2278 }
2279
2280 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2281 {
2282 int skb_size;
2283
2284 /*
2285 * Reserve 2+14 bytes for an ethernet header (the hardware
2286 * automatically prepends 2 bytes of dummy data to each
2287 * received packet), 16 bytes for up to four VLAN tags, and
2288 * 4 bytes for the trailing FCS -- 36 bytes total.
2289 */
2290 skb_size = mp->dev->mtu + 36;
2291
2292 /*
2293 * Make sure that the skb size is a multiple of 8 bytes, as
2294 * the lower three bits of the receive descriptor's buffer
2295 * size field are ignored by the hardware.
2296 */
2297 mp->skb_size = (skb_size + 7) & ~7;
2298
2299 /*
2300 * If NET_SKB_PAD is smaller than a cache line,
2301 * netdev_alloc_skb() will cause skb->data to be misaligned
2302 * to a cache line boundary. If this is the case, include
2303 * some extra space to allow re-aligning the data area.
2304 */
2305 mp->skb_size += SKB_DMA_REALIGN;
2306 }
2307
2308 static int mv643xx_eth_open(struct net_device *dev)
2309 {
2310 struct mv643xx_eth_private *mp = netdev_priv(dev);
2311 int err;
2312 int i;
2313
2314 wrlp(mp, INT_CAUSE, 0);
2315 wrlp(mp, INT_CAUSE_EXT, 0);
2316 rdlp(mp, INT_CAUSE_EXT);
2317
2318 err = request_irq(dev->irq, mv643xx_eth_irq,
2319 IRQF_SHARED, dev->name, dev);
2320 if (err) {
2321 netdev_err(dev, "can't assign irq\n");
2322 return -EAGAIN;
2323 }
2324
2325 mv643xx_eth_recalc_skb_size(mp);
2326
2327 napi_enable(&mp->napi);
2328
2329 skb_queue_head_init(&mp->rx_recycle);
2330
2331 mp->int_mask = INT_EXT;
2332
2333 for (i = 0; i < mp->rxq_count; i++) {
2334 err = rxq_init(mp, i);
2335 if (err) {
2336 while (--i >= 0)
2337 rxq_deinit(mp->rxq + i);
2338 goto out;
2339 }
2340
2341 rxq_refill(mp->rxq + i, INT_MAX);
2342 mp->int_mask |= INT_RX_0 << i;
2343 }
2344
2345 if (mp->oom) {
2346 mp->rx_oom.expires = jiffies + (HZ / 10);
2347 add_timer(&mp->rx_oom);
2348 }
2349
2350 for (i = 0; i < mp->txq_count; i++) {
2351 err = txq_init(mp, i);
2352 if (err) {
2353 while (--i >= 0)
2354 txq_deinit(mp->txq + i);
2355 goto out_free;
2356 }
2357 mp->int_mask |= INT_TX_END_0 << i;
2358 }
2359
2360 port_start(mp);
2361
2362 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2363 wrlp(mp, INT_MASK, mp->int_mask);
2364
2365 return 0;
2366
2367
2368 out_free:
2369 for (i = 0; i < mp->rxq_count; i++)
2370 rxq_deinit(mp->rxq + i);
2371 out:
2372 free_irq(dev->irq, dev);
2373
2374 return err;
2375 }
2376
2377 static void port_reset(struct mv643xx_eth_private *mp)
2378 {
2379 unsigned int data;
2380 int i;
2381
2382 for (i = 0; i < mp->rxq_count; i++)
2383 rxq_disable(mp->rxq + i);
2384 for (i = 0; i < mp->txq_count; i++)
2385 txq_disable(mp->txq + i);
2386
2387 while (1) {
2388 u32 ps = rdlp(mp, PORT_STATUS);
2389
2390 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2391 break;
2392 udelay(10);
2393 }
2394
2395 /* Reset the Enable bit in the Configuration Register */
2396 data = rdlp(mp, PORT_SERIAL_CONTROL);
2397 data &= ~(SERIAL_PORT_ENABLE |
2398 DO_NOT_FORCE_LINK_FAIL |
2399 FORCE_LINK_PASS);
2400 wrlp(mp, PORT_SERIAL_CONTROL, data);
2401 }
2402
2403 static int mv643xx_eth_stop(struct net_device *dev)
2404 {
2405 struct mv643xx_eth_private *mp = netdev_priv(dev);
2406 int i;
2407
2408 wrlp(mp, INT_MASK_EXT, 0x00000000);
2409 wrlp(mp, INT_MASK, 0x00000000);
2410 rdlp(mp, INT_MASK);
2411
2412 napi_disable(&mp->napi);
2413
2414 del_timer_sync(&mp->rx_oom);
2415
2416 netif_carrier_off(dev);
2417
2418 free_irq(dev->irq, dev);
2419
2420 port_reset(mp);
2421 mv643xx_eth_get_stats(dev);
2422 mib_counters_update(mp);
2423 del_timer_sync(&mp->mib_counters_timer);
2424
2425 skb_queue_purge(&mp->rx_recycle);
2426
2427 for (i = 0; i < mp->rxq_count; i++)
2428 rxq_deinit(mp->rxq + i);
2429 for (i = 0; i < mp->txq_count; i++)
2430 txq_deinit(mp->txq + i);
2431
2432 return 0;
2433 }
2434
2435 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2436 {
2437 struct mv643xx_eth_private *mp = netdev_priv(dev);
2438
2439 if (mp->phy != NULL)
2440 return phy_mii_ioctl(mp->phy, ifr, cmd);
2441
2442 return -EOPNOTSUPP;
2443 }
2444
2445 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2446 {
2447 struct mv643xx_eth_private *mp = netdev_priv(dev);
2448
2449 if (new_mtu < 64 || new_mtu > 9500)
2450 return -EINVAL;
2451
2452 dev->mtu = new_mtu;
2453 mv643xx_eth_recalc_skb_size(mp);
2454 tx_set_rate(mp, 1000000000, 16777216);
2455
2456 if (!netif_running(dev))
2457 return 0;
2458
2459 /*
2460 * Stop and then re-open the interface. This will allocate RX
2461 * skbs of the new MTU.
2462 * There is a possible danger that the open will not succeed,
2463 * due to memory being full.
2464 */
2465 mv643xx_eth_stop(dev);
2466 if (mv643xx_eth_open(dev)) {
2467 netdev_err(dev,
2468 "fatal error on re-opening device after MTU change\n");
2469 }
2470
2471 return 0;
2472 }
2473
2474 static void tx_timeout_task(struct work_struct *ugly)
2475 {
2476 struct mv643xx_eth_private *mp;
2477
2478 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2479 if (netif_running(mp->dev)) {
2480 netif_tx_stop_all_queues(mp->dev);
2481 port_reset(mp);
2482 port_start(mp);
2483 netif_tx_wake_all_queues(mp->dev);
2484 }
2485 }
2486
2487 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2488 {
2489 struct mv643xx_eth_private *mp = netdev_priv(dev);
2490
2491 netdev_info(dev, "tx timeout\n");
2492
2493 schedule_work(&mp->tx_timeout_task);
2494 }
2495
2496 #ifdef CONFIG_NET_POLL_CONTROLLER
2497 static void mv643xx_eth_netpoll(struct net_device *dev)
2498 {
2499 struct mv643xx_eth_private *mp = netdev_priv(dev);
2500
2501 wrlp(mp, INT_MASK, 0x00000000);
2502 rdlp(mp, INT_MASK);
2503
2504 mv643xx_eth_irq(dev->irq, dev);
2505
2506 wrlp(mp, INT_MASK, mp->int_mask);
2507 }
2508 #endif
2509
2510
2511 /* platform glue ************************************************************/
2512 static void
2513 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2514 const struct mbus_dram_target_info *dram)
2515 {
2516 void __iomem *base = msp->base;
2517 u32 win_enable;
2518 u32 win_protect;
2519 int i;
2520
2521 for (i = 0; i < 6; i++) {
2522 writel(0, base + WINDOW_BASE(i));
2523 writel(0, base + WINDOW_SIZE(i));
2524 if (i < 4)
2525 writel(0, base + WINDOW_REMAP_HIGH(i));
2526 }
2527
2528 win_enable = 0x3f;
2529 win_protect = 0;
2530
2531 for (i = 0; i < dram->num_cs; i++) {
2532 const struct mbus_dram_window *cs = dram->cs + i;
2533
2534 writel((cs->base & 0xffff0000) |
2535 (cs->mbus_attr << 8) |
2536 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2537 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2538
2539 win_enable &= ~(1 << i);
2540 win_protect |= 3 << (2 * i);
2541 }
2542
2543 writel(win_enable, base + WINDOW_BAR_ENABLE);
2544 msp->win_protect = win_protect;
2545 }
2546
2547 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2548 {
2549 /*
2550 * Check whether we have a 14-bit coal limit field in bits
2551 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2552 * SDMA config register.
2553 */
2554 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2555 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2556 msp->extended_rx_coal_limit = 1;
2557 else
2558 msp->extended_rx_coal_limit = 0;
2559
2560 /*
2561 * Check whether the MAC supports TX rate control, and if
2562 * yes, whether its associated registers are in the old or
2563 * the new place.
2564 */
2565 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2566 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2567 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2568 } else {
2569 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2570 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2571 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2572 else
2573 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2574 }
2575 }
2576
2577 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2578 {
2579 static int mv643xx_eth_version_printed;
2580 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2581 struct mv643xx_eth_shared_private *msp;
2582 const struct mbus_dram_target_info *dram;
2583 struct resource *res;
2584 int ret;
2585
2586 if (!mv643xx_eth_version_printed++)
2587 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2588 mv643xx_eth_driver_version);
2589
2590 ret = -EINVAL;
2591 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2592 if (res == NULL)
2593 goto out;
2594
2595 ret = -ENOMEM;
2596 msp = kzalloc(sizeof(*msp), GFP_KERNEL);
2597 if (msp == NULL)
2598 goto out;
2599
2600 msp->base = ioremap(res->start, resource_size(res));
2601 if (msp->base == NULL)
2602 goto out_free;
2603
2604 /*
2605 * Set up and register SMI bus.
2606 */
2607 if (pd == NULL || pd->shared_smi == NULL) {
2608 msp->smi_bus = mdiobus_alloc();
2609 if (msp->smi_bus == NULL)
2610 goto out_unmap;
2611
2612 msp->smi_bus->priv = msp;
2613 msp->smi_bus->name = "mv643xx_eth smi";
2614 msp->smi_bus->read = smi_bus_read;
2615 msp->smi_bus->write = smi_bus_write,
2616 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d",
2617 pdev->name, pdev->id);
2618 msp->smi_bus->parent = &pdev->dev;
2619 msp->smi_bus->phy_mask = 0xffffffff;
2620 if (mdiobus_register(msp->smi_bus) < 0)
2621 goto out_free_mii_bus;
2622 msp->smi = msp;
2623 } else {
2624 msp->smi = platform_get_drvdata(pd->shared_smi);
2625 }
2626
2627 msp->err_interrupt = NO_IRQ;
2628 init_waitqueue_head(&msp->smi_busy_wait);
2629
2630 /*
2631 * Check whether the error interrupt is hooked up.
2632 */
2633 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2634 if (res != NULL) {
2635 int err;
2636
2637 err = request_irq(res->start, mv643xx_eth_err_irq,
2638 IRQF_SHARED, "mv643xx_eth", msp);
2639 if (!err) {
2640 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2641 msp->err_interrupt = res->start;
2642 }
2643 }
2644
2645 /*
2646 * (Re-)program MBUS remapping windows if we are asked to.
2647 */
2648 dram = mv_mbus_dram_info();
2649 if (dram)
2650 mv643xx_eth_conf_mbus_windows(msp, dram);
2651
2652 /*
2653 * Detect hardware parameters.
2654 */
2655 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2656 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2657 pd->tx_csum_limit : 9 * 1024;
2658 infer_hw_params(msp);
2659
2660 platform_set_drvdata(pdev, msp);
2661
2662 return 0;
2663
2664 out_free_mii_bus:
2665 mdiobus_free(msp->smi_bus);
2666 out_unmap:
2667 iounmap(msp->base);
2668 out_free:
2669 kfree(msp);
2670 out:
2671 return ret;
2672 }
2673
2674 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2675 {
2676 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2677 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2678
2679 if (pd == NULL || pd->shared_smi == NULL) {
2680 mdiobus_unregister(msp->smi_bus);
2681 mdiobus_free(msp->smi_bus);
2682 }
2683 if (msp->err_interrupt != NO_IRQ)
2684 free_irq(msp->err_interrupt, msp);
2685 iounmap(msp->base);
2686 kfree(msp);
2687
2688 return 0;
2689 }
2690
2691 static struct platform_driver mv643xx_eth_shared_driver = {
2692 .probe = mv643xx_eth_shared_probe,
2693 .remove = mv643xx_eth_shared_remove,
2694 .driver = {
2695 .name = MV643XX_ETH_SHARED_NAME,
2696 .owner = THIS_MODULE,
2697 },
2698 };
2699
2700 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2701 {
2702 int addr_shift = 5 * mp->port_num;
2703 u32 data;
2704
2705 data = rdl(mp, PHY_ADDR);
2706 data &= ~(0x1f << addr_shift);
2707 data |= (phy_addr & 0x1f) << addr_shift;
2708 wrl(mp, PHY_ADDR, data);
2709 }
2710
2711 static int phy_addr_get(struct mv643xx_eth_private *mp)
2712 {
2713 unsigned int data;
2714
2715 data = rdl(mp, PHY_ADDR);
2716
2717 return (data >> (5 * mp->port_num)) & 0x1f;
2718 }
2719
2720 static void set_params(struct mv643xx_eth_private *mp,
2721 struct mv643xx_eth_platform_data *pd)
2722 {
2723 struct net_device *dev = mp->dev;
2724
2725 if (is_valid_ether_addr(pd->mac_addr))
2726 memcpy(dev->dev_addr, pd->mac_addr, 6);
2727 else
2728 uc_addr_get(mp, dev->dev_addr);
2729
2730 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2731 if (pd->rx_queue_size)
2732 mp->rx_ring_size = pd->rx_queue_size;
2733 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2734 mp->rx_desc_sram_size = pd->rx_sram_size;
2735
2736 mp->rxq_count = pd->rx_queue_count ? : 1;
2737
2738 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2739 if (pd->tx_queue_size)
2740 mp->tx_ring_size = pd->tx_queue_size;
2741 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2742 mp->tx_desc_sram_size = pd->tx_sram_size;
2743
2744 mp->txq_count = pd->tx_queue_count ? : 1;
2745 }
2746
2747 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2748 int phy_addr)
2749 {
2750 struct mii_bus *bus = mp->shared->smi->smi_bus;
2751 struct phy_device *phydev;
2752 int start;
2753 int num;
2754 int i;
2755
2756 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2757 start = phy_addr_get(mp) & 0x1f;
2758 num = 32;
2759 } else {
2760 start = phy_addr & 0x1f;
2761 num = 1;
2762 }
2763
2764 phydev = NULL;
2765 for (i = 0; i < num; i++) {
2766 int addr = (start + i) & 0x1f;
2767
2768 if (bus->phy_map[addr] == NULL)
2769 mdiobus_scan(bus, addr);
2770
2771 if (phydev == NULL) {
2772 phydev = bus->phy_map[addr];
2773 if (phydev != NULL)
2774 phy_addr_set(mp, addr);
2775 }
2776 }
2777
2778 return phydev;
2779 }
2780
2781 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2782 {
2783 struct phy_device *phy = mp->phy;
2784
2785 phy_reset(mp);
2786
2787 phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
2788
2789 if (speed == 0) {
2790 phy->autoneg = AUTONEG_ENABLE;
2791 phy->speed = 0;
2792 phy->duplex = 0;
2793 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2794 } else {
2795 phy->autoneg = AUTONEG_DISABLE;
2796 phy->advertising = 0;
2797 phy->speed = speed;
2798 phy->duplex = duplex;
2799 }
2800 phy_start_aneg(phy);
2801 }
2802
2803 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2804 {
2805 u32 pscr;
2806
2807 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2808 if (pscr & SERIAL_PORT_ENABLE) {
2809 pscr &= ~SERIAL_PORT_ENABLE;
2810 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2811 }
2812
2813 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2814 if (mp->phy == NULL) {
2815 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2816 if (speed == SPEED_1000)
2817 pscr |= SET_GMII_SPEED_TO_1000;
2818 else if (speed == SPEED_100)
2819 pscr |= SET_MII_SPEED_TO_100;
2820
2821 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2822
2823 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2824 if (duplex == DUPLEX_FULL)
2825 pscr |= SET_FULL_DUPLEX_MODE;
2826 }
2827
2828 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2829 }
2830
2831 static const struct net_device_ops mv643xx_eth_netdev_ops = {
2832 .ndo_open = mv643xx_eth_open,
2833 .ndo_stop = mv643xx_eth_stop,
2834 .ndo_start_xmit = mv643xx_eth_xmit,
2835 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2836 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2837 .ndo_validate_addr = eth_validate_addr,
2838 .ndo_do_ioctl = mv643xx_eth_ioctl,
2839 .ndo_change_mtu = mv643xx_eth_change_mtu,
2840 .ndo_set_features = mv643xx_eth_set_features,
2841 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2842 .ndo_get_stats = mv643xx_eth_get_stats,
2843 #ifdef CONFIG_NET_POLL_CONTROLLER
2844 .ndo_poll_controller = mv643xx_eth_netpoll,
2845 #endif
2846 };
2847
2848 static int mv643xx_eth_probe(struct platform_device *pdev)
2849 {
2850 struct mv643xx_eth_platform_data *pd;
2851 struct mv643xx_eth_private *mp;
2852 struct net_device *dev;
2853 struct resource *res;
2854 int err;
2855
2856 pd = pdev->dev.platform_data;
2857 if (pd == NULL) {
2858 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
2859 return -ENODEV;
2860 }
2861
2862 if (pd->shared == NULL) {
2863 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
2864 return -ENODEV;
2865 }
2866
2867 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2868 if (!dev)
2869 return -ENOMEM;
2870
2871 mp = netdev_priv(dev);
2872 platform_set_drvdata(pdev, mp);
2873
2874 mp->shared = platform_get_drvdata(pd->shared);
2875 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
2876 mp->port_num = pd->port_number;
2877
2878 mp->dev = dev;
2879
2880 set_params(mp, pd);
2881 netif_set_real_num_tx_queues(dev, mp->txq_count);
2882 netif_set_real_num_rx_queues(dev, mp->rxq_count);
2883
2884 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2885 mp->phy = phy_scan(mp, pd->phy_addr);
2886
2887 if (mp->phy != NULL)
2888 phy_init(mp, pd->speed, pd->duplex);
2889
2890 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2891
2892 init_pscr(mp, pd->speed, pd->duplex);
2893
2894
2895 mib_counters_clear(mp);
2896
2897 init_timer(&mp->mib_counters_timer);
2898 mp->mib_counters_timer.data = (unsigned long)mp;
2899 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2900 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2901 add_timer(&mp->mib_counters_timer);
2902
2903 spin_lock_init(&mp->mib_counters_lock);
2904
2905 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2906
2907 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2908
2909 init_timer(&mp->rx_oom);
2910 mp->rx_oom.data = (unsigned long)mp;
2911 mp->rx_oom.function = oom_timer_wrapper;
2912
2913
2914 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2915 BUG_ON(!res);
2916 dev->irq = res->start;
2917
2918 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2919
2920 dev->watchdog_timeo = 2 * HZ;
2921 dev->base_addr = 0;
2922
2923 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
2924 NETIF_F_RXCSUM | NETIF_F_LRO;
2925 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
2926 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2927
2928 dev->priv_flags |= IFF_UNICAST_FLT;
2929
2930 SET_NETDEV_DEV(dev, &pdev->dev);
2931
2932 if (mp->shared->win_protect)
2933 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2934
2935 netif_carrier_off(dev);
2936
2937 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2938
2939 set_rx_coal(mp, 250);
2940 set_tx_coal(mp, 0);
2941
2942 err = register_netdev(dev);
2943 if (err)
2944 goto out;
2945
2946 netdev_notice(dev, "port %d with MAC address %pM\n",
2947 mp->port_num, dev->dev_addr);
2948
2949 if (mp->tx_desc_sram_size > 0)
2950 netdev_notice(dev, "configured with sram\n");
2951
2952 return 0;
2953
2954 out:
2955 free_netdev(dev);
2956
2957 return err;
2958 }
2959
2960 static int mv643xx_eth_remove(struct platform_device *pdev)
2961 {
2962 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2963
2964 unregister_netdev(mp->dev);
2965 if (mp->phy != NULL)
2966 phy_detach(mp->phy);
2967 cancel_work_sync(&mp->tx_timeout_task);
2968 free_netdev(mp->dev);
2969
2970 platform_set_drvdata(pdev, NULL);
2971
2972 return 0;
2973 }
2974
2975 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2976 {
2977 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2978
2979 /* Mask all interrupts on ethernet port */
2980 wrlp(mp, INT_MASK, 0);
2981 rdlp(mp, INT_MASK);
2982
2983 if (netif_running(mp->dev))
2984 port_reset(mp);
2985 }
2986
2987 static struct platform_driver mv643xx_eth_driver = {
2988 .probe = mv643xx_eth_probe,
2989 .remove = mv643xx_eth_remove,
2990 .shutdown = mv643xx_eth_shutdown,
2991 .driver = {
2992 .name = MV643XX_ETH_NAME,
2993 .owner = THIS_MODULE,
2994 },
2995 };
2996
2997 static int __init mv643xx_eth_init_module(void)
2998 {
2999 int rc;
3000
3001 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3002 if (!rc) {
3003 rc = platform_driver_register(&mv643xx_eth_driver);
3004 if (rc)
3005 platform_driver_unregister(&mv643xx_eth_shared_driver);
3006 }
3007
3008 return rc;
3009 }
3010 module_init(mv643xx_eth_init_module);
3011
3012 static void __exit mv643xx_eth_cleanup_module(void)
3013 {
3014 platform_driver_unregister(&mv643xx_eth_driver);
3015 platform_driver_unregister(&mv643xx_eth_shared_driver);
3016 }
3017 module_exit(mv643xx_eth_cleanup_module);
3018
3019 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3020 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3021 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3022 MODULE_LICENSE("GPL");
3023 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3024 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux kernel - Deliverables
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