2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
40 #include <linux/init.h>
41 #include <linux/dma-mapping.h>
44 #include <linux/tcp.h>
45 #include <linux/udp.h>
46 #include <linux/etherdevice.h>
47 #include <linux/delay.h>
48 #include <linux/ethtool.h>
49 #include <linux/platform_device.h>
50 #include <linux/module.h>
51 #include <linux/kernel.h>
52 #include <linux/spinlock.h>
53 #include <linux/workqueue.h>
54 #include <linux/phy.h>
55 #include <linux/mv643xx_eth.h>
57 #include <linux/types.h>
58 #include <linux/inet_lro.h>
59 #include <linux/slab.h>
60 #include <linux/clk.h>
62 static char mv643xx_eth_driver_name
[] = "mv643xx_eth";
63 static char mv643xx_eth_driver_version
[] = "1.4";
67 * Registers shared between all ports.
69 #define PHY_ADDR 0x0000
70 #define SMI_REG 0x0004
71 #define SMI_BUSY 0x10000000
72 #define SMI_READ_VALID 0x08000000
73 #define SMI_OPCODE_READ 0x04000000
74 #define SMI_OPCODE_WRITE 0x00000000
75 #define ERR_INT_CAUSE 0x0080
76 #define ERR_INT_SMI_DONE 0x00000010
77 #define ERR_INT_MASK 0x0084
78 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
79 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
80 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
81 #define WINDOW_BAR_ENABLE 0x0290
82 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
85 * Main per-port registers. These live at offset 0x0400 for
86 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
88 #define PORT_CONFIG 0x0000
89 #define UNICAST_PROMISCUOUS_MODE 0x00000001
90 #define PORT_CONFIG_EXT 0x0004
91 #define MAC_ADDR_LOW 0x0014
92 #define MAC_ADDR_HIGH 0x0018
93 #define SDMA_CONFIG 0x001c
94 #define TX_BURST_SIZE_16_64BIT 0x01000000
95 #define TX_BURST_SIZE_4_64BIT 0x00800000
96 #define BLM_TX_NO_SWAP 0x00000020
97 #define BLM_RX_NO_SWAP 0x00000010
98 #define RX_BURST_SIZE_16_64BIT 0x00000008
99 #define RX_BURST_SIZE_4_64BIT 0x00000004
100 #define PORT_SERIAL_CONTROL 0x003c
101 #define SET_MII_SPEED_TO_100 0x01000000
102 #define SET_GMII_SPEED_TO_1000 0x00800000
103 #define SET_FULL_DUPLEX_MODE 0x00200000
104 #define MAX_RX_PACKET_9700BYTE 0x000a0000
105 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
106 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
107 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
108 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
109 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
110 #define FORCE_LINK_PASS 0x00000002
111 #define SERIAL_PORT_ENABLE 0x00000001
112 #define PORT_STATUS 0x0044
113 #define TX_FIFO_EMPTY 0x00000400
114 #define TX_IN_PROGRESS 0x00000080
115 #define PORT_SPEED_MASK 0x00000030
116 #define PORT_SPEED_1000 0x00000010
117 #define PORT_SPEED_100 0x00000020
118 #define PORT_SPEED_10 0x00000000
119 #define FLOW_CONTROL_ENABLED 0x00000008
120 #define FULL_DUPLEX 0x00000004
121 #define LINK_UP 0x00000002
122 #define TXQ_COMMAND 0x0048
123 #define TXQ_FIX_PRIO_CONF 0x004c
124 #define TX_BW_RATE 0x0050
125 #define TX_BW_MTU 0x0058
126 #define TX_BW_BURST 0x005c
127 #define INT_CAUSE 0x0060
128 #define INT_TX_END 0x07f80000
129 #define INT_TX_END_0 0x00080000
130 #define INT_RX 0x000003fc
131 #define INT_RX_0 0x00000004
132 #define INT_EXT 0x00000002
133 #define INT_CAUSE_EXT 0x0064
134 #define INT_EXT_LINK_PHY 0x00110000
135 #define INT_EXT_TX 0x000000ff
136 #define INT_MASK 0x0068
137 #define INT_MASK_EXT 0x006c
138 #define TX_FIFO_URGENT_THRESHOLD 0x0074
139 #define RX_DISCARD_FRAME_CNT 0x0084
140 #define RX_OVERRUN_FRAME_CNT 0x0088
141 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
142 #define TX_BW_RATE_MOVED 0x00e0
143 #define TX_BW_MTU_MOVED 0x00e8
144 #define TX_BW_BURST_MOVED 0x00ec
145 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
146 #define RXQ_COMMAND 0x0280
147 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
148 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
149 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
150 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
153 * Misc per-port registers.
155 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
156 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
157 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
158 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
162 * SDMA configuration register default value.
164 #if defined(__BIG_ENDIAN)
165 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
166 (RX_BURST_SIZE_4_64BIT | \
167 TX_BURST_SIZE_4_64BIT)
168 #elif defined(__LITTLE_ENDIAN)
169 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
170 (RX_BURST_SIZE_4_64BIT | \
173 TX_BURST_SIZE_4_64BIT)
175 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
182 #define DEFAULT_RX_QUEUE_SIZE 128
183 #define DEFAULT_TX_QUEUE_SIZE 256
184 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
190 #if defined(__BIG_ENDIAN)
192 u16 byte_cnt
; /* Descriptor buffer byte count */
193 u16 buf_size
; /* Buffer size */
194 u32 cmd_sts
; /* Descriptor command status */
195 u32 next_desc_ptr
; /* Next descriptor pointer */
196 u32 buf_ptr
; /* Descriptor buffer pointer */
200 u16 byte_cnt
; /* buffer byte count */
201 u16 l4i_chk
; /* CPU provided TCP checksum */
202 u32 cmd_sts
; /* Command/status field */
203 u32 next_desc_ptr
; /* Pointer to next descriptor */
204 u32 buf_ptr
; /* pointer to buffer for this descriptor*/
206 #elif defined(__LITTLE_ENDIAN)
208 u32 cmd_sts
; /* Descriptor command status */
209 u16 buf_size
; /* Buffer size */
210 u16 byte_cnt
; /* Descriptor buffer byte count */
211 u32 buf_ptr
; /* Descriptor buffer pointer */
212 u32 next_desc_ptr
; /* Next descriptor pointer */
216 u32 cmd_sts
; /* Command/status field */
217 u16 l4i_chk
; /* CPU provided TCP checksum */
218 u16 byte_cnt
; /* buffer byte count */
219 u32 buf_ptr
; /* pointer to buffer for this descriptor*/
220 u32 next_desc_ptr
; /* Pointer to next descriptor */
223 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
226 /* RX & TX descriptor command */
227 #define BUFFER_OWNED_BY_DMA 0x80000000
229 /* RX & TX descriptor status */
230 #define ERROR_SUMMARY 0x00000001
232 /* RX descriptor status */
233 #define LAYER_4_CHECKSUM_OK 0x40000000
234 #define RX_ENABLE_INTERRUPT 0x20000000
235 #define RX_FIRST_DESC 0x08000000
236 #define RX_LAST_DESC 0x04000000
237 #define RX_IP_HDR_OK 0x02000000
238 #define RX_PKT_IS_IPV4 0x01000000
239 #define RX_PKT_IS_ETHERNETV2 0x00800000
240 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
241 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
242 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
244 /* TX descriptor command */
245 #define TX_ENABLE_INTERRUPT 0x00800000
246 #define GEN_CRC 0x00400000
247 #define TX_FIRST_DESC 0x00200000
248 #define TX_LAST_DESC 0x00100000
249 #define ZERO_PADDING 0x00080000
250 #define GEN_IP_V4_CHECKSUM 0x00040000
251 #define GEN_TCP_UDP_CHECKSUM 0x00020000
252 #define UDP_FRAME 0x00010000
253 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
254 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
256 #define TX_IHL_SHIFT 11
259 /* global *******************************************************************/
260 struct mv643xx_eth_shared_private
{
262 * Ethernet controller base address.
267 * Points at the right SMI instance to use.
269 struct mv643xx_eth_shared_private
*smi
;
272 * Provides access to local SMI interface.
274 struct mii_bus
*smi_bus
;
277 * If we have access to the error interrupt pin (which is
278 * somewhat misnamed as it not only reflects internal errors
279 * but also reflects SMI completion), use that to wait for
280 * SMI access completion instead of polling the SMI busy bit.
283 wait_queue_head_t smi_busy_wait
;
286 * Per-port MBUS window access register value.
291 * Hardware-specific parameters.
293 int extended_rx_coal_limit
;
299 #define TX_BW_CONTROL_ABSENT 0
300 #define TX_BW_CONTROL_OLD_LAYOUT 1
301 #define TX_BW_CONTROL_NEW_LAYOUT 2
303 static int mv643xx_eth_open(struct net_device
*dev
);
304 static int mv643xx_eth_stop(struct net_device
*dev
);
307 /* per-port *****************************************************************/
308 struct mib_counters
{
309 u64 good_octets_received
;
310 u32 bad_octets_received
;
311 u32 internal_mac_transmit_err
;
312 u32 good_frames_received
;
313 u32 bad_frames_received
;
314 u32 broadcast_frames_received
;
315 u32 multicast_frames_received
;
316 u32 frames_64_octets
;
317 u32 frames_65_to_127_octets
;
318 u32 frames_128_to_255_octets
;
319 u32 frames_256_to_511_octets
;
320 u32 frames_512_to_1023_octets
;
321 u32 frames_1024_to_max_octets
;
322 u64 good_octets_sent
;
323 u32 good_frames_sent
;
324 u32 excessive_collision
;
325 u32 multicast_frames_sent
;
326 u32 broadcast_frames_sent
;
327 u32 unrec_mac_control_received
;
329 u32 good_fc_received
;
331 u32 undersize_received
;
332 u32 fragments_received
;
333 u32 oversize_received
;
335 u32 mac_receive_error
;
339 /* Non MIB hardware counters */
344 struct lro_counters
{
359 struct rx_desc
*rx_desc_area
;
360 dma_addr_t rx_desc_dma
;
361 int rx_desc_area_size
;
362 struct sk_buff
**rx_skb
;
364 struct net_lro_mgr lro_mgr
;
365 struct net_lro_desc lro_arr
[8];
377 struct tx_desc
*tx_desc_area
;
378 dma_addr_t tx_desc_dma
;
379 int tx_desc_area_size
;
381 struct sk_buff_head tx_skb
;
383 unsigned long tx_packets
;
384 unsigned long tx_bytes
;
385 unsigned long tx_dropped
;
388 struct mv643xx_eth_private
{
389 struct mv643xx_eth_shared_private
*shared
;
393 struct net_device
*dev
;
395 struct phy_device
*phy
;
397 struct timer_list mib_counters_timer
;
398 spinlock_t mib_counters_lock
;
399 struct mib_counters mib_counters
;
401 struct lro_counters lro_counters
;
403 struct work_struct tx_timeout_task
;
405 struct napi_struct napi
;
415 struct sk_buff_head rx_recycle
;
421 unsigned long rx_desc_sram_addr
;
422 int rx_desc_sram_size
;
424 struct timer_list rx_oom
;
425 struct rx_queue rxq
[8];
431 unsigned long tx_desc_sram_addr
;
432 int tx_desc_sram_size
;
434 struct tx_queue txq
[8];
437 * Hardware-specific parameters.
444 /* port register accessors **************************************************/
445 static inline u32
rdl(struct mv643xx_eth_private
*mp
, int offset
)
447 return readl(mp
->shared
->base
+ offset
);
450 static inline u32
rdlp(struct mv643xx_eth_private
*mp
, int offset
)
452 return readl(mp
->base
+ offset
);
455 static inline void wrl(struct mv643xx_eth_private
*mp
, int offset
, u32 data
)
457 writel(data
, mp
->shared
->base
+ offset
);
460 static inline void wrlp(struct mv643xx_eth_private
*mp
, int offset
, u32 data
)
462 writel(data
, mp
->base
+ offset
);
466 /* rxq/txq helper functions *************************************************/
467 static struct mv643xx_eth_private
*rxq_to_mp(struct rx_queue
*rxq
)
469 return container_of(rxq
, struct mv643xx_eth_private
, rxq
[rxq
->index
]);
472 static struct mv643xx_eth_private
*txq_to_mp(struct tx_queue
*txq
)
474 return container_of(txq
, struct mv643xx_eth_private
, txq
[txq
->index
]);
477 static void rxq_enable(struct rx_queue
*rxq
)
479 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
480 wrlp(mp
, RXQ_COMMAND
, 1 << rxq
->index
);
483 static void rxq_disable(struct rx_queue
*rxq
)
485 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
486 u8 mask
= 1 << rxq
->index
;
488 wrlp(mp
, RXQ_COMMAND
, mask
<< 8);
489 while (rdlp(mp
, RXQ_COMMAND
) & mask
)
493 static void txq_reset_hw_ptr(struct tx_queue
*txq
)
495 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
498 addr
= (u32
)txq
->tx_desc_dma
;
499 addr
+= txq
->tx_curr_desc
* sizeof(struct tx_desc
);
500 wrlp(mp
, TXQ_CURRENT_DESC_PTR(txq
->index
), addr
);
503 static void txq_enable(struct tx_queue
*txq
)
505 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
506 wrlp(mp
, TXQ_COMMAND
, 1 << txq
->index
);
509 static void txq_disable(struct tx_queue
*txq
)
511 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
512 u8 mask
= 1 << txq
->index
;
514 wrlp(mp
, TXQ_COMMAND
, mask
<< 8);
515 while (rdlp(mp
, TXQ_COMMAND
) & mask
)
519 static void txq_maybe_wake(struct tx_queue
*txq
)
521 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
522 struct netdev_queue
*nq
= netdev_get_tx_queue(mp
->dev
, txq
->index
);
524 if (netif_tx_queue_stopped(nq
)) {
525 __netif_tx_lock(nq
, smp_processor_id());
526 if (txq
->tx_ring_size
- txq
->tx_desc_count
>= MAX_SKB_FRAGS
+ 1)
527 netif_tx_wake_queue(nq
);
528 __netif_tx_unlock(nq
);
533 /* rx napi ******************************************************************/
535 mv643xx_get_skb_header(struct sk_buff
*skb
, void **iphdr
, void **tcph
,
536 u64
*hdr_flags
, void *priv
)
538 unsigned long cmd_sts
= (unsigned long)priv
;
541 * Make sure that this packet is Ethernet II, is not VLAN
542 * tagged, is IPv4, has a valid IP header, and is TCP.
544 if ((cmd_sts
& (RX_IP_HDR_OK
| RX_PKT_IS_IPV4
|
545 RX_PKT_IS_ETHERNETV2
| RX_PKT_LAYER4_TYPE_MASK
|
546 RX_PKT_IS_VLAN_TAGGED
)) !=
547 (RX_IP_HDR_OK
| RX_PKT_IS_IPV4
|
548 RX_PKT_IS_ETHERNETV2
| RX_PKT_LAYER4_TYPE_TCP_IPV4
))
551 skb_reset_network_header(skb
);
552 skb_set_transport_header(skb
, ip_hdrlen(skb
));
553 *iphdr
= ip_hdr(skb
);
554 *tcph
= tcp_hdr(skb
);
555 *hdr_flags
= LRO_IPV4
| LRO_TCP
;
560 static int rxq_process(struct rx_queue
*rxq
, int budget
)
562 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
563 struct net_device_stats
*stats
= &mp
->dev
->stats
;
564 int lro_flush_needed
;
567 lro_flush_needed
= 0;
569 while (rx
< budget
&& rxq
->rx_desc_count
) {
570 struct rx_desc
*rx_desc
;
571 unsigned int cmd_sts
;
575 rx_desc
= &rxq
->rx_desc_area
[rxq
->rx_curr_desc
];
577 cmd_sts
= rx_desc
->cmd_sts
;
578 if (cmd_sts
& BUFFER_OWNED_BY_DMA
)
582 skb
= rxq
->rx_skb
[rxq
->rx_curr_desc
];
583 rxq
->rx_skb
[rxq
->rx_curr_desc
] = NULL
;
586 if (rxq
->rx_curr_desc
== rxq
->rx_ring_size
)
587 rxq
->rx_curr_desc
= 0;
589 dma_unmap_single(mp
->dev
->dev
.parent
, rx_desc
->buf_ptr
,
590 rx_desc
->buf_size
, DMA_FROM_DEVICE
);
591 rxq
->rx_desc_count
--;
594 mp
->work_rx_refill
|= 1 << rxq
->index
;
596 byte_cnt
= rx_desc
->byte_cnt
;
601 * Note that the descriptor byte count includes 2 dummy
602 * bytes automatically inserted by the hardware at the
603 * start of the packet (which we don't count), and a 4
604 * byte CRC at the end of the packet (which we do count).
607 stats
->rx_bytes
+= byte_cnt
- 2;
610 * In case we received a packet without first / last bits
611 * on, or the error summary bit is set, the packet needs
614 if ((cmd_sts
& (RX_FIRST_DESC
| RX_LAST_DESC
| ERROR_SUMMARY
))
615 != (RX_FIRST_DESC
| RX_LAST_DESC
))
619 * The -4 is for the CRC in the trailer of the
622 skb_put(skb
, byte_cnt
- 2 - 4);
624 if (cmd_sts
& LAYER_4_CHECKSUM_OK
)
625 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
626 skb
->protocol
= eth_type_trans(skb
, mp
->dev
);
628 if (skb
->dev
->features
& NETIF_F_LRO
&&
629 skb
->ip_summed
== CHECKSUM_UNNECESSARY
) {
630 lro_receive_skb(&rxq
->lro_mgr
, skb
, (void *)cmd_sts
);
631 lro_flush_needed
= 1;
633 netif_receive_skb(skb
);
640 if ((cmd_sts
& (RX_FIRST_DESC
| RX_LAST_DESC
)) !=
641 (RX_FIRST_DESC
| RX_LAST_DESC
)) {
644 "received packet spanning multiple descriptors\n");
647 if (cmd_sts
& ERROR_SUMMARY
)
653 if (lro_flush_needed
)
654 lro_flush_all(&rxq
->lro_mgr
);
657 mp
->work_rx
&= ~(1 << rxq
->index
);
662 static int rxq_refill(struct rx_queue
*rxq
, int budget
)
664 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
668 while (refilled
< budget
&& rxq
->rx_desc_count
< rxq
->rx_ring_size
) {
671 struct rx_desc
*rx_desc
;
674 skb
= __skb_dequeue(&mp
->rx_recycle
);
676 skb
= netdev_alloc_skb(mp
->dev
, mp
->skb_size
);
684 skb_reserve(skb
, SKB_DMA_REALIGN
);
687 rxq
->rx_desc_count
++;
689 rx
= rxq
->rx_used_desc
++;
690 if (rxq
->rx_used_desc
== rxq
->rx_ring_size
)
691 rxq
->rx_used_desc
= 0;
693 rx_desc
= rxq
->rx_desc_area
+ rx
;
695 size
= skb
->end
- skb
->data
;
696 rx_desc
->buf_ptr
= dma_map_single(mp
->dev
->dev
.parent
,
699 rx_desc
->buf_size
= size
;
700 rxq
->rx_skb
[rx
] = skb
;
702 rx_desc
->cmd_sts
= BUFFER_OWNED_BY_DMA
| RX_ENABLE_INTERRUPT
;
706 * The hardware automatically prepends 2 bytes of
707 * dummy data to each received packet, so that the
708 * IP header ends up 16-byte aligned.
713 if (refilled
< budget
)
714 mp
->work_rx_refill
&= ~(1 << rxq
->index
);
721 /* tx ***********************************************************************/
722 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff
*skb
)
726 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
727 const skb_frag_t
*fragp
= &skb_shinfo(skb
)->frags
[frag
];
729 if (skb_frag_size(fragp
) <= 8 && fragp
->page_offset
& 7)
736 static void txq_submit_frag_skb(struct tx_queue
*txq
, struct sk_buff
*skb
)
738 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
739 int nr_frags
= skb_shinfo(skb
)->nr_frags
;
742 for (frag
= 0; frag
< nr_frags
; frag
++) {
743 skb_frag_t
*this_frag
;
745 struct tx_desc
*desc
;
747 this_frag
= &skb_shinfo(skb
)->frags
[frag
];
748 tx_index
= txq
->tx_curr_desc
++;
749 if (txq
->tx_curr_desc
== txq
->tx_ring_size
)
750 txq
->tx_curr_desc
= 0;
751 desc
= &txq
->tx_desc_area
[tx_index
];
754 * The last fragment will generate an interrupt
755 * which will free the skb on TX completion.
757 if (frag
== nr_frags
- 1) {
758 desc
->cmd_sts
= BUFFER_OWNED_BY_DMA
|
759 ZERO_PADDING
| TX_LAST_DESC
|
762 desc
->cmd_sts
= BUFFER_OWNED_BY_DMA
;
766 desc
->byte_cnt
= skb_frag_size(this_frag
);
767 desc
->buf_ptr
= skb_frag_dma_map(mp
->dev
->dev
.parent
,
769 skb_frag_size(this_frag
),
774 static inline __be16
sum16_as_be(__sum16 sum
)
776 return (__force __be16
)sum
;
779 static int txq_submit_skb(struct tx_queue
*txq
, struct sk_buff
*skb
)
781 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
782 int nr_frags
= skb_shinfo(skb
)->nr_frags
;
784 struct tx_desc
*desc
;
789 cmd_sts
= TX_FIRST_DESC
| GEN_CRC
| BUFFER_OWNED_BY_DMA
;
792 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
796 BUG_ON(skb
->protocol
!= htons(ETH_P_IP
) &&
797 skb
->protocol
!= htons(ETH_P_8021Q
));
799 hdr_len
= (void *)ip_hdr(skb
) - (void *)skb
->data
;
800 tag_bytes
= hdr_len
- ETH_HLEN
;
801 if (skb
->len
- hdr_len
> mp
->shared
->tx_csum_limit
||
802 unlikely(tag_bytes
& ~12)) {
803 if (skb_checksum_help(skb
) == 0)
810 cmd_sts
|= MAC_HDR_EXTRA_4_BYTES
;
812 cmd_sts
|= MAC_HDR_EXTRA_8_BYTES
;
814 cmd_sts
|= GEN_TCP_UDP_CHECKSUM
|
816 ip_hdr(skb
)->ihl
<< TX_IHL_SHIFT
;
818 switch (ip_hdr(skb
)->protocol
) {
820 cmd_sts
|= UDP_FRAME
;
821 l4i_chk
= ntohs(sum16_as_be(udp_hdr(skb
)->check
));
824 l4i_chk
= ntohs(sum16_as_be(tcp_hdr(skb
)->check
));
831 /* Errata BTS #50, IHL must be 5 if no HW checksum */
832 cmd_sts
|= 5 << TX_IHL_SHIFT
;
835 tx_index
= txq
->tx_curr_desc
++;
836 if (txq
->tx_curr_desc
== txq
->tx_ring_size
)
837 txq
->tx_curr_desc
= 0;
838 desc
= &txq
->tx_desc_area
[tx_index
];
841 txq_submit_frag_skb(txq
, skb
);
842 length
= skb_headlen(skb
);
844 cmd_sts
|= ZERO_PADDING
| TX_LAST_DESC
| TX_ENABLE_INTERRUPT
;
848 desc
->l4i_chk
= l4i_chk
;
849 desc
->byte_cnt
= length
;
850 desc
->buf_ptr
= dma_map_single(mp
->dev
->dev
.parent
, skb
->data
,
851 length
, DMA_TO_DEVICE
);
853 __skb_queue_tail(&txq
->tx_skb
, skb
);
855 skb_tx_timestamp(skb
);
857 /* ensure all other descriptors are written before first cmd_sts */
859 desc
->cmd_sts
= cmd_sts
;
861 /* clear TX_END status */
862 mp
->work_tx_end
&= ~(1 << txq
->index
);
864 /* ensure all descriptors are written before poking hardware */
868 txq
->tx_desc_count
+= nr_frags
+ 1;
873 static netdev_tx_t
mv643xx_eth_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
875 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
877 struct tx_queue
*txq
;
878 struct netdev_queue
*nq
;
880 queue
= skb_get_queue_mapping(skb
);
881 txq
= mp
->txq
+ queue
;
882 nq
= netdev_get_tx_queue(dev
, queue
);
884 if (has_tiny_unaligned_frags(skb
) && __skb_linearize(skb
)) {
886 netdev_printk(KERN_DEBUG
, dev
,
887 "failed to linearize skb with tiny unaligned fragment\n");
888 return NETDEV_TX_BUSY
;
891 if (txq
->tx_ring_size
- txq
->tx_desc_count
< MAX_SKB_FRAGS
+ 1) {
893 netdev_err(dev
, "tx queue full?!\n");
900 if (!txq_submit_skb(txq
, skb
)) {
903 txq
->tx_bytes
+= length
;
906 entries_left
= txq
->tx_ring_size
- txq
->tx_desc_count
;
907 if (entries_left
< MAX_SKB_FRAGS
+ 1)
908 netif_tx_stop_queue(nq
);
915 /* tx napi ******************************************************************/
916 static void txq_kick(struct tx_queue
*txq
)
918 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
919 struct netdev_queue
*nq
= netdev_get_tx_queue(mp
->dev
, txq
->index
);
923 __netif_tx_lock(nq
, smp_processor_id());
925 if (rdlp(mp
, TXQ_COMMAND
) & (1 << txq
->index
))
928 hw_desc_ptr
= rdlp(mp
, TXQ_CURRENT_DESC_PTR(txq
->index
));
929 expected_ptr
= (u32
)txq
->tx_desc_dma
+
930 txq
->tx_curr_desc
* sizeof(struct tx_desc
);
932 if (hw_desc_ptr
!= expected_ptr
)
936 __netif_tx_unlock(nq
);
938 mp
->work_tx_end
&= ~(1 << txq
->index
);
941 static int txq_reclaim(struct tx_queue
*txq
, int budget
, int force
)
943 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
944 struct netdev_queue
*nq
= netdev_get_tx_queue(mp
->dev
, txq
->index
);
947 __netif_tx_lock(nq
, smp_processor_id());
950 while (reclaimed
< budget
&& txq
->tx_desc_count
> 0) {
952 struct tx_desc
*desc
;
956 tx_index
= txq
->tx_used_desc
;
957 desc
= &txq
->tx_desc_area
[tx_index
];
958 cmd_sts
= desc
->cmd_sts
;
960 if (cmd_sts
& BUFFER_OWNED_BY_DMA
) {
963 desc
->cmd_sts
= cmd_sts
& ~BUFFER_OWNED_BY_DMA
;
966 txq
->tx_used_desc
= tx_index
+ 1;
967 if (txq
->tx_used_desc
== txq
->tx_ring_size
)
968 txq
->tx_used_desc
= 0;
971 txq
->tx_desc_count
--;
974 if (cmd_sts
& TX_LAST_DESC
)
975 skb
= __skb_dequeue(&txq
->tx_skb
);
977 if (cmd_sts
& ERROR_SUMMARY
) {
978 netdev_info(mp
->dev
, "tx error\n");
979 mp
->dev
->stats
.tx_errors
++;
982 if (cmd_sts
& TX_FIRST_DESC
) {
983 dma_unmap_single(mp
->dev
->dev
.parent
, desc
->buf_ptr
,
984 desc
->byte_cnt
, DMA_TO_DEVICE
);
986 dma_unmap_page(mp
->dev
->dev
.parent
, desc
->buf_ptr
,
987 desc
->byte_cnt
, DMA_TO_DEVICE
);
991 if (skb_queue_len(&mp
->rx_recycle
) <
993 skb_recycle_check(skb
, mp
->skb_size
))
994 __skb_queue_head(&mp
->rx_recycle
, skb
);
1000 __netif_tx_unlock(nq
);
1002 if (reclaimed
< budget
)
1003 mp
->work_tx
&= ~(1 << txq
->index
);
1009 /* tx rate control **********************************************************/
1011 * Set total maximum TX rate (shared by all TX queues for this port)
1012 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1014 static void tx_set_rate(struct mv643xx_eth_private
*mp
, int rate
, int burst
)
1020 token_rate
= ((rate
/ 1000) * 64) / (mp
->t_clk
/ 1000);
1021 if (token_rate
> 1023)
1024 mtu
= (mp
->dev
->mtu
+ 255) >> 8;
1028 bucket_size
= (burst
+ 255) >> 8;
1029 if (bucket_size
> 65535)
1030 bucket_size
= 65535;
1032 switch (mp
->shared
->tx_bw_control
) {
1033 case TX_BW_CONTROL_OLD_LAYOUT
:
1034 wrlp(mp
, TX_BW_RATE
, token_rate
);
1035 wrlp(mp
, TX_BW_MTU
, mtu
);
1036 wrlp(mp
, TX_BW_BURST
, bucket_size
);
1038 case TX_BW_CONTROL_NEW_LAYOUT
:
1039 wrlp(mp
, TX_BW_RATE_MOVED
, token_rate
);
1040 wrlp(mp
, TX_BW_MTU_MOVED
, mtu
);
1041 wrlp(mp
, TX_BW_BURST_MOVED
, bucket_size
);
1046 static void txq_set_rate(struct tx_queue
*txq
, int rate
, int burst
)
1048 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
1052 token_rate
= ((rate
/ 1000) * 64) / (mp
->t_clk
/ 1000);
1053 if (token_rate
> 1023)
1056 bucket_size
= (burst
+ 255) >> 8;
1057 if (bucket_size
> 65535)
1058 bucket_size
= 65535;
1060 wrlp(mp
, TXQ_BW_TOKENS(txq
->index
), token_rate
<< 14);
1061 wrlp(mp
, TXQ_BW_CONF(txq
->index
), (bucket_size
<< 10) | token_rate
);
1064 static void txq_set_fixed_prio_mode(struct tx_queue
*txq
)
1066 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
1071 * Turn on fixed priority mode.
1074 switch (mp
->shared
->tx_bw_control
) {
1075 case TX_BW_CONTROL_OLD_LAYOUT
:
1076 off
= TXQ_FIX_PRIO_CONF
;
1078 case TX_BW_CONTROL_NEW_LAYOUT
:
1079 off
= TXQ_FIX_PRIO_CONF_MOVED
;
1084 val
= rdlp(mp
, off
);
1085 val
|= 1 << txq
->index
;
1091 /* mii management interface *************************************************/
1092 static irqreturn_t
mv643xx_eth_err_irq(int irq
, void *dev_id
)
1094 struct mv643xx_eth_shared_private
*msp
= dev_id
;
1096 if (readl(msp
->base
+ ERR_INT_CAUSE
) & ERR_INT_SMI_DONE
) {
1097 writel(~ERR_INT_SMI_DONE
, msp
->base
+ ERR_INT_CAUSE
);
1098 wake_up(&msp
->smi_busy_wait
);
1105 static int smi_is_done(struct mv643xx_eth_shared_private
*msp
)
1107 return !(readl(msp
->base
+ SMI_REG
) & SMI_BUSY
);
1110 static int smi_wait_ready(struct mv643xx_eth_shared_private
*msp
)
1112 if (msp
->err_interrupt
== NO_IRQ
) {
1115 for (i
= 0; !smi_is_done(msp
); i
++) {
1124 if (!smi_is_done(msp
)) {
1125 wait_event_timeout(msp
->smi_busy_wait
, smi_is_done(msp
),
1126 msecs_to_jiffies(100));
1127 if (!smi_is_done(msp
))
1134 static int smi_bus_read(struct mii_bus
*bus
, int addr
, int reg
)
1136 struct mv643xx_eth_shared_private
*msp
= bus
->priv
;
1137 void __iomem
*smi_reg
= msp
->base
+ SMI_REG
;
1140 if (smi_wait_ready(msp
)) {
1141 pr_warn("SMI bus busy timeout\n");
1145 writel(SMI_OPCODE_READ
| (reg
<< 21) | (addr
<< 16), smi_reg
);
1147 if (smi_wait_ready(msp
)) {
1148 pr_warn("SMI bus busy timeout\n");
1152 ret
= readl(smi_reg
);
1153 if (!(ret
& SMI_READ_VALID
)) {
1154 pr_warn("SMI bus read not valid\n");
1158 return ret
& 0xffff;
1161 static int smi_bus_write(struct mii_bus
*bus
, int addr
, int reg
, u16 val
)
1163 struct mv643xx_eth_shared_private
*msp
= bus
->priv
;
1164 void __iomem
*smi_reg
= msp
->base
+ SMI_REG
;
1166 if (smi_wait_ready(msp
)) {
1167 pr_warn("SMI bus busy timeout\n");
1171 writel(SMI_OPCODE_WRITE
| (reg
<< 21) |
1172 (addr
<< 16) | (val
& 0xffff), smi_reg
);
1174 if (smi_wait_ready(msp
)) {
1175 pr_warn("SMI bus busy timeout\n");
1183 /* statistics ***************************************************************/
1184 static struct net_device_stats
*mv643xx_eth_get_stats(struct net_device
*dev
)
1186 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1187 struct net_device_stats
*stats
= &dev
->stats
;
1188 unsigned long tx_packets
= 0;
1189 unsigned long tx_bytes
= 0;
1190 unsigned long tx_dropped
= 0;
1193 for (i
= 0; i
< mp
->txq_count
; i
++) {
1194 struct tx_queue
*txq
= mp
->txq
+ i
;
1196 tx_packets
+= txq
->tx_packets
;
1197 tx_bytes
+= txq
->tx_bytes
;
1198 tx_dropped
+= txq
->tx_dropped
;
1201 stats
->tx_packets
= tx_packets
;
1202 stats
->tx_bytes
= tx_bytes
;
1203 stats
->tx_dropped
= tx_dropped
;
1208 static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private
*mp
)
1210 u32 lro_aggregated
= 0;
1211 u32 lro_flushed
= 0;
1212 u32 lro_no_desc
= 0;
1215 for (i
= 0; i
< mp
->rxq_count
; i
++) {
1216 struct rx_queue
*rxq
= mp
->rxq
+ i
;
1218 lro_aggregated
+= rxq
->lro_mgr
.stats
.aggregated
;
1219 lro_flushed
+= rxq
->lro_mgr
.stats
.flushed
;
1220 lro_no_desc
+= rxq
->lro_mgr
.stats
.no_desc
;
1223 mp
->lro_counters
.lro_aggregated
= lro_aggregated
;
1224 mp
->lro_counters
.lro_flushed
= lro_flushed
;
1225 mp
->lro_counters
.lro_no_desc
= lro_no_desc
;
1228 static inline u32
mib_read(struct mv643xx_eth_private
*mp
, int offset
)
1230 return rdl(mp
, MIB_COUNTERS(mp
->port_num
) + offset
);
1233 static void mib_counters_clear(struct mv643xx_eth_private
*mp
)
1237 for (i
= 0; i
< 0x80; i
+= 4)
1240 /* Clear non MIB hw counters also */
1241 rdlp(mp
, RX_DISCARD_FRAME_CNT
);
1242 rdlp(mp
, RX_OVERRUN_FRAME_CNT
);
1245 static void mib_counters_update(struct mv643xx_eth_private
*mp
)
1247 struct mib_counters
*p
= &mp
->mib_counters
;
1249 spin_lock_bh(&mp
->mib_counters_lock
);
1250 p
->good_octets_received
+= mib_read(mp
, 0x00);
1251 p
->bad_octets_received
+= mib_read(mp
, 0x08);
1252 p
->internal_mac_transmit_err
+= mib_read(mp
, 0x0c);
1253 p
->good_frames_received
+= mib_read(mp
, 0x10);
1254 p
->bad_frames_received
+= mib_read(mp
, 0x14);
1255 p
->broadcast_frames_received
+= mib_read(mp
, 0x18);
1256 p
->multicast_frames_received
+= mib_read(mp
, 0x1c);
1257 p
->frames_64_octets
+= mib_read(mp
, 0x20);
1258 p
->frames_65_to_127_octets
+= mib_read(mp
, 0x24);
1259 p
->frames_128_to_255_octets
+= mib_read(mp
, 0x28);
1260 p
->frames_256_to_511_octets
+= mib_read(mp
, 0x2c);
1261 p
->frames_512_to_1023_octets
+= mib_read(mp
, 0x30);
1262 p
->frames_1024_to_max_octets
+= mib_read(mp
, 0x34);
1263 p
->good_octets_sent
+= mib_read(mp
, 0x38);
1264 p
->good_frames_sent
+= mib_read(mp
, 0x40);
1265 p
->excessive_collision
+= mib_read(mp
, 0x44);
1266 p
->multicast_frames_sent
+= mib_read(mp
, 0x48);
1267 p
->broadcast_frames_sent
+= mib_read(mp
, 0x4c);
1268 p
->unrec_mac_control_received
+= mib_read(mp
, 0x50);
1269 p
->fc_sent
+= mib_read(mp
, 0x54);
1270 p
->good_fc_received
+= mib_read(mp
, 0x58);
1271 p
->bad_fc_received
+= mib_read(mp
, 0x5c);
1272 p
->undersize_received
+= mib_read(mp
, 0x60);
1273 p
->fragments_received
+= mib_read(mp
, 0x64);
1274 p
->oversize_received
+= mib_read(mp
, 0x68);
1275 p
->jabber_received
+= mib_read(mp
, 0x6c);
1276 p
->mac_receive_error
+= mib_read(mp
, 0x70);
1277 p
->bad_crc_event
+= mib_read(mp
, 0x74);
1278 p
->collision
+= mib_read(mp
, 0x78);
1279 p
->late_collision
+= mib_read(mp
, 0x7c);
1280 /* Non MIB hardware counters */
1281 p
->rx_discard
+= rdlp(mp
, RX_DISCARD_FRAME_CNT
);
1282 p
->rx_overrun
+= rdlp(mp
, RX_OVERRUN_FRAME_CNT
);
1283 spin_unlock_bh(&mp
->mib_counters_lock
);
1285 mod_timer(&mp
->mib_counters_timer
, jiffies
+ 30 * HZ
);
1288 static void mib_counters_timer_wrapper(unsigned long _mp
)
1290 struct mv643xx_eth_private
*mp
= (void *)_mp
;
1292 mib_counters_update(mp
);
1296 /* interrupt coalescing *****************************************************/
1298 * Hardware coalescing parameters are set in units of 64 t_clk
1301 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1303 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1305 * In the ->set*() methods, we round the computed register value
1306 * to the nearest integer.
1308 static unsigned int get_rx_coal(struct mv643xx_eth_private
*mp
)
1310 u32 val
= rdlp(mp
, SDMA_CONFIG
);
1313 if (mp
->shared
->extended_rx_coal_limit
)
1314 temp
= ((val
& 0x02000000) >> 10) | ((val
& 0x003fff80) >> 7);
1316 temp
= (val
& 0x003fff00) >> 8;
1319 do_div(temp
, mp
->t_clk
);
1321 return (unsigned int)temp
;
1324 static void set_rx_coal(struct mv643xx_eth_private
*mp
, unsigned int usec
)
1329 temp
= (u64
)usec
* mp
->t_clk
;
1331 do_div(temp
, 64000000);
1333 val
= rdlp(mp
, SDMA_CONFIG
);
1334 if (mp
->shared
->extended_rx_coal_limit
) {
1338 val
|= (temp
& 0x8000) << 10;
1339 val
|= (temp
& 0x7fff) << 7;
1344 val
|= (temp
& 0x3fff) << 8;
1346 wrlp(mp
, SDMA_CONFIG
, val
);
1349 static unsigned int get_tx_coal(struct mv643xx_eth_private
*mp
)
1353 temp
= (rdlp(mp
, TX_FIFO_URGENT_THRESHOLD
) & 0x3fff0) >> 4;
1355 do_div(temp
, mp
->t_clk
);
1357 return (unsigned int)temp
;
1360 static void set_tx_coal(struct mv643xx_eth_private
*mp
, unsigned int usec
)
1364 temp
= (u64
)usec
* mp
->t_clk
;
1366 do_div(temp
, 64000000);
1371 wrlp(mp
, TX_FIFO_URGENT_THRESHOLD
, temp
<< 4);
1375 /* ethtool ******************************************************************/
1376 struct mv643xx_eth_stats
{
1377 char stat_string
[ETH_GSTRING_LEN
];
1384 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1385 offsetof(struct net_device, stats.m), -1 }
1387 #define MIBSTAT(m) \
1388 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1389 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1391 #define LROSTAT(m) \
1392 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1393 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1395 static const struct mv643xx_eth_stats mv643xx_eth_stats
[] = {
1404 MIBSTAT(good_octets_received
),
1405 MIBSTAT(bad_octets_received
),
1406 MIBSTAT(internal_mac_transmit_err
),
1407 MIBSTAT(good_frames_received
),
1408 MIBSTAT(bad_frames_received
),
1409 MIBSTAT(broadcast_frames_received
),
1410 MIBSTAT(multicast_frames_received
),
1411 MIBSTAT(frames_64_octets
),
1412 MIBSTAT(frames_65_to_127_octets
),
1413 MIBSTAT(frames_128_to_255_octets
),
1414 MIBSTAT(frames_256_to_511_octets
),
1415 MIBSTAT(frames_512_to_1023_octets
),
1416 MIBSTAT(frames_1024_to_max_octets
),
1417 MIBSTAT(good_octets_sent
),
1418 MIBSTAT(good_frames_sent
),
1419 MIBSTAT(excessive_collision
),
1420 MIBSTAT(multicast_frames_sent
),
1421 MIBSTAT(broadcast_frames_sent
),
1422 MIBSTAT(unrec_mac_control_received
),
1424 MIBSTAT(good_fc_received
),
1425 MIBSTAT(bad_fc_received
),
1426 MIBSTAT(undersize_received
),
1427 MIBSTAT(fragments_received
),
1428 MIBSTAT(oversize_received
),
1429 MIBSTAT(jabber_received
),
1430 MIBSTAT(mac_receive_error
),
1431 MIBSTAT(bad_crc_event
),
1433 MIBSTAT(late_collision
),
1434 MIBSTAT(rx_discard
),
1435 MIBSTAT(rx_overrun
),
1436 LROSTAT(lro_aggregated
),
1437 LROSTAT(lro_flushed
),
1438 LROSTAT(lro_no_desc
),
1442 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private
*mp
,
1443 struct ethtool_cmd
*cmd
)
1447 err
= phy_read_status(mp
->phy
);
1449 err
= phy_ethtool_gset(mp
->phy
, cmd
);
1452 * The MAC does not support 1000baseT_Half.
1454 cmd
->supported
&= ~SUPPORTED_1000baseT_Half
;
1455 cmd
->advertising
&= ~ADVERTISED_1000baseT_Half
;
1461 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private
*mp
,
1462 struct ethtool_cmd
*cmd
)
1466 port_status
= rdlp(mp
, PORT_STATUS
);
1468 cmd
->supported
= SUPPORTED_MII
;
1469 cmd
->advertising
= ADVERTISED_MII
;
1470 switch (port_status
& PORT_SPEED_MASK
) {
1472 ethtool_cmd_speed_set(cmd
, SPEED_10
);
1474 case PORT_SPEED_100
:
1475 ethtool_cmd_speed_set(cmd
, SPEED_100
);
1477 case PORT_SPEED_1000
:
1478 ethtool_cmd_speed_set(cmd
, SPEED_1000
);
1484 cmd
->duplex
= (port_status
& FULL_DUPLEX
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1485 cmd
->port
= PORT_MII
;
1486 cmd
->phy_address
= 0;
1487 cmd
->transceiver
= XCVR_INTERNAL
;
1488 cmd
->autoneg
= AUTONEG_DISABLE
;
1496 mv643xx_eth_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1498 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1500 if (mp
->phy
!= NULL
)
1501 return mv643xx_eth_get_settings_phy(mp
, cmd
);
1503 return mv643xx_eth_get_settings_phyless(mp
, cmd
);
1507 mv643xx_eth_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1509 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1511 if (mp
->phy
== NULL
)
1515 * The MAC does not support 1000baseT_Half.
1517 cmd
->advertising
&= ~ADVERTISED_1000baseT_Half
;
1519 return phy_ethtool_sset(mp
->phy
, cmd
);
1522 static void mv643xx_eth_get_drvinfo(struct net_device
*dev
,
1523 struct ethtool_drvinfo
*drvinfo
)
1525 strlcpy(drvinfo
->driver
, mv643xx_eth_driver_name
,
1526 sizeof(drvinfo
->driver
));
1527 strlcpy(drvinfo
->version
, mv643xx_eth_driver_version
,
1528 sizeof(drvinfo
->version
));
1529 strlcpy(drvinfo
->fw_version
, "N/A", sizeof(drvinfo
->fw_version
));
1530 strlcpy(drvinfo
->bus_info
, "platform", sizeof(drvinfo
->bus_info
));
1531 drvinfo
->n_stats
= ARRAY_SIZE(mv643xx_eth_stats
);
1534 static int mv643xx_eth_nway_reset(struct net_device
*dev
)
1536 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1538 if (mp
->phy
== NULL
)
1541 return genphy_restart_aneg(mp
->phy
);
1545 mv643xx_eth_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
1547 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1549 ec
->rx_coalesce_usecs
= get_rx_coal(mp
);
1550 ec
->tx_coalesce_usecs
= get_tx_coal(mp
);
1556 mv643xx_eth_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
1558 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1560 set_rx_coal(mp
, ec
->rx_coalesce_usecs
);
1561 set_tx_coal(mp
, ec
->tx_coalesce_usecs
);
1567 mv643xx_eth_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*er
)
1569 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1571 er
->rx_max_pending
= 4096;
1572 er
->tx_max_pending
= 4096;
1574 er
->rx_pending
= mp
->rx_ring_size
;
1575 er
->tx_pending
= mp
->tx_ring_size
;
1579 mv643xx_eth_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*er
)
1581 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1583 if (er
->rx_mini_pending
|| er
->rx_jumbo_pending
)
1586 mp
->rx_ring_size
= er
->rx_pending
< 4096 ? er
->rx_pending
: 4096;
1587 mp
->tx_ring_size
= er
->tx_pending
< 4096 ? er
->tx_pending
: 4096;
1589 if (netif_running(dev
)) {
1590 mv643xx_eth_stop(dev
);
1591 if (mv643xx_eth_open(dev
)) {
1593 "fatal error on re-opening device after ring param change\n");
1603 mv643xx_eth_set_features(struct net_device
*dev
, netdev_features_t features
)
1605 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1606 bool rx_csum
= features
& NETIF_F_RXCSUM
;
1608 wrlp(mp
, PORT_CONFIG
, rx_csum
? 0x02000000 : 0x00000000);
1613 static void mv643xx_eth_get_strings(struct net_device
*dev
,
1614 uint32_t stringset
, uint8_t *data
)
1618 if (stringset
== ETH_SS_STATS
) {
1619 for (i
= 0; i
< ARRAY_SIZE(mv643xx_eth_stats
); i
++) {
1620 memcpy(data
+ i
* ETH_GSTRING_LEN
,
1621 mv643xx_eth_stats
[i
].stat_string
,
1627 static void mv643xx_eth_get_ethtool_stats(struct net_device
*dev
,
1628 struct ethtool_stats
*stats
,
1631 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1634 mv643xx_eth_get_stats(dev
);
1635 mib_counters_update(mp
);
1636 mv643xx_eth_grab_lro_stats(mp
);
1638 for (i
= 0; i
< ARRAY_SIZE(mv643xx_eth_stats
); i
++) {
1639 const struct mv643xx_eth_stats
*stat
;
1642 stat
= mv643xx_eth_stats
+ i
;
1644 if (stat
->netdev_off
>= 0)
1645 p
= ((void *)mp
->dev
) + stat
->netdev_off
;
1647 p
= ((void *)mp
) + stat
->mp_off
;
1649 data
[i
] = (stat
->sizeof_stat
== 8) ?
1650 *(uint64_t *)p
: *(uint32_t *)p
;
1654 static int mv643xx_eth_get_sset_count(struct net_device
*dev
, int sset
)
1656 if (sset
== ETH_SS_STATS
)
1657 return ARRAY_SIZE(mv643xx_eth_stats
);
1662 static const struct ethtool_ops mv643xx_eth_ethtool_ops
= {
1663 .get_settings
= mv643xx_eth_get_settings
,
1664 .set_settings
= mv643xx_eth_set_settings
,
1665 .get_drvinfo
= mv643xx_eth_get_drvinfo
,
1666 .nway_reset
= mv643xx_eth_nway_reset
,
1667 .get_link
= ethtool_op_get_link
,
1668 .get_coalesce
= mv643xx_eth_get_coalesce
,
1669 .set_coalesce
= mv643xx_eth_set_coalesce
,
1670 .get_ringparam
= mv643xx_eth_get_ringparam
,
1671 .set_ringparam
= mv643xx_eth_set_ringparam
,
1672 .get_strings
= mv643xx_eth_get_strings
,
1673 .get_ethtool_stats
= mv643xx_eth_get_ethtool_stats
,
1674 .get_sset_count
= mv643xx_eth_get_sset_count
,
1675 .get_ts_info
= ethtool_op_get_ts_info
,
1679 /* address handling *********************************************************/
1680 static void uc_addr_get(struct mv643xx_eth_private
*mp
, unsigned char *addr
)
1682 unsigned int mac_h
= rdlp(mp
, MAC_ADDR_HIGH
);
1683 unsigned int mac_l
= rdlp(mp
, MAC_ADDR_LOW
);
1685 addr
[0] = (mac_h
>> 24) & 0xff;
1686 addr
[1] = (mac_h
>> 16) & 0xff;
1687 addr
[2] = (mac_h
>> 8) & 0xff;
1688 addr
[3] = mac_h
& 0xff;
1689 addr
[4] = (mac_l
>> 8) & 0xff;
1690 addr
[5] = mac_l
& 0xff;
1693 static void uc_addr_set(struct mv643xx_eth_private
*mp
, unsigned char *addr
)
1695 wrlp(mp
, MAC_ADDR_HIGH
,
1696 (addr
[0] << 24) | (addr
[1] << 16) | (addr
[2] << 8) | addr
[3]);
1697 wrlp(mp
, MAC_ADDR_LOW
, (addr
[4] << 8) | addr
[5]);
1700 static u32
uc_addr_filter_mask(struct net_device
*dev
)
1702 struct netdev_hw_addr
*ha
;
1705 if (dev
->flags
& IFF_PROMISC
)
1708 nibbles
= 1 << (dev
->dev_addr
[5] & 0x0f);
1709 netdev_for_each_uc_addr(ha
, dev
) {
1710 if (memcmp(dev
->dev_addr
, ha
->addr
, 5))
1712 if ((dev
->dev_addr
[5] ^ ha
->addr
[5]) & 0xf0)
1715 nibbles
|= 1 << (ha
->addr
[5] & 0x0f);
1721 static void mv643xx_eth_program_unicast_filter(struct net_device
*dev
)
1723 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1728 uc_addr_set(mp
, dev
->dev_addr
);
1730 port_config
= rdlp(mp
, PORT_CONFIG
) & ~UNICAST_PROMISCUOUS_MODE
;
1732 nibbles
= uc_addr_filter_mask(dev
);
1734 port_config
|= UNICAST_PROMISCUOUS_MODE
;
1738 for (i
= 0; i
< 16; i
+= 4) {
1739 int off
= UNICAST_TABLE(mp
->port_num
) + i
;
1756 wrlp(mp
, PORT_CONFIG
, port_config
);
1759 static int addr_crc(unsigned char *addr
)
1764 for (i
= 0; i
< 6; i
++) {
1767 crc
= (crc
^ addr
[i
]) << 8;
1768 for (j
= 7; j
>= 0; j
--) {
1769 if (crc
& (0x100 << j
))
1777 static void mv643xx_eth_program_multicast_filter(struct net_device
*dev
)
1779 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1782 struct netdev_hw_addr
*ha
;
1785 if (dev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
)) {
1790 port_num
= mp
->port_num
;
1791 accept
= 0x01010101;
1792 for (i
= 0; i
< 0x100; i
+= 4) {
1793 wrl(mp
, SPECIAL_MCAST_TABLE(port_num
) + i
, accept
);
1794 wrl(mp
, OTHER_MCAST_TABLE(port_num
) + i
, accept
);
1799 mc_spec
= kmalloc(0x200, GFP_ATOMIC
);
1800 if (mc_spec
== NULL
)
1802 mc_other
= mc_spec
+ (0x100 >> 2);
1804 memset(mc_spec
, 0, 0x100);
1805 memset(mc_other
, 0, 0x100);
1807 netdev_for_each_mc_addr(ha
, dev
) {
1812 if (memcmp(a
, "\x01\x00\x5e\x00\x00", 5) == 0) {
1817 entry
= addr_crc(a
);
1820 table
[entry
>> 2] |= 1 << (8 * (entry
& 3));
1823 for (i
= 0; i
< 0x100; i
+= 4) {
1824 wrl(mp
, SPECIAL_MCAST_TABLE(mp
->port_num
) + i
, mc_spec
[i
>> 2]);
1825 wrl(mp
, OTHER_MCAST_TABLE(mp
->port_num
) + i
, mc_other
[i
>> 2]);
1831 static void mv643xx_eth_set_rx_mode(struct net_device
*dev
)
1833 mv643xx_eth_program_unicast_filter(dev
);
1834 mv643xx_eth_program_multicast_filter(dev
);
1837 static int mv643xx_eth_set_mac_address(struct net_device
*dev
, void *addr
)
1839 struct sockaddr
*sa
= addr
;
1841 if (!is_valid_ether_addr(sa
->sa_data
))
1842 return -EADDRNOTAVAIL
;
1844 memcpy(dev
->dev_addr
, sa
->sa_data
, ETH_ALEN
);
1846 netif_addr_lock_bh(dev
);
1847 mv643xx_eth_program_unicast_filter(dev
);
1848 netif_addr_unlock_bh(dev
);
1854 /* rx/tx queue initialisation ***********************************************/
1855 static int rxq_init(struct mv643xx_eth_private
*mp
, int index
)
1857 struct rx_queue
*rxq
= mp
->rxq
+ index
;
1858 struct rx_desc
*rx_desc
;
1864 rxq
->rx_ring_size
= mp
->rx_ring_size
;
1866 rxq
->rx_desc_count
= 0;
1867 rxq
->rx_curr_desc
= 0;
1868 rxq
->rx_used_desc
= 0;
1870 size
= rxq
->rx_ring_size
* sizeof(struct rx_desc
);
1872 if (index
== 0 && size
<= mp
->rx_desc_sram_size
) {
1873 rxq
->rx_desc_area
= ioremap(mp
->rx_desc_sram_addr
,
1874 mp
->rx_desc_sram_size
);
1875 rxq
->rx_desc_dma
= mp
->rx_desc_sram_addr
;
1877 rxq
->rx_desc_area
= dma_alloc_coherent(mp
->dev
->dev
.parent
,
1878 size
, &rxq
->rx_desc_dma
,
1882 if (rxq
->rx_desc_area
== NULL
) {
1884 "can't allocate rx ring (%d bytes)\n", size
);
1887 memset(rxq
->rx_desc_area
, 0, size
);
1889 rxq
->rx_desc_area_size
= size
;
1890 rxq
->rx_skb
= kmalloc(rxq
->rx_ring_size
* sizeof(*rxq
->rx_skb
),
1892 if (rxq
->rx_skb
== NULL
) {
1893 netdev_err(mp
->dev
, "can't allocate rx skb ring\n");
1897 rx_desc
= (struct rx_desc
*)rxq
->rx_desc_area
;
1898 for (i
= 0; i
< rxq
->rx_ring_size
; i
++) {
1902 if (nexti
== rxq
->rx_ring_size
)
1905 rx_desc
[i
].next_desc_ptr
= rxq
->rx_desc_dma
+
1906 nexti
* sizeof(struct rx_desc
);
1909 rxq
->lro_mgr
.dev
= mp
->dev
;
1910 memset(&rxq
->lro_mgr
.stats
, 0, sizeof(rxq
->lro_mgr
.stats
));
1911 rxq
->lro_mgr
.features
= LRO_F_NAPI
;
1912 rxq
->lro_mgr
.ip_summed
= CHECKSUM_UNNECESSARY
;
1913 rxq
->lro_mgr
.ip_summed_aggr
= CHECKSUM_UNNECESSARY
;
1914 rxq
->lro_mgr
.max_desc
= ARRAY_SIZE(rxq
->lro_arr
);
1915 rxq
->lro_mgr
.max_aggr
= 32;
1916 rxq
->lro_mgr
.frag_align_pad
= 0;
1917 rxq
->lro_mgr
.lro_arr
= rxq
->lro_arr
;
1918 rxq
->lro_mgr
.get_skb_header
= mv643xx_get_skb_header
;
1920 memset(&rxq
->lro_arr
, 0, sizeof(rxq
->lro_arr
));
1926 if (index
== 0 && size
<= mp
->rx_desc_sram_size
)
1927 iounmap(rxq
->rx_desc_area
);
1929 dma_free_coherent(mp
->dev
->dev
.parent
, size
,
1937 static void rxq_deinit(struct rx_queue
*rxq
)
1939 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
1944 for (i
= 0; i
< rxq
->rx_ring_size
; i
++) {
1945 if (rxq
->rx_skb
[i
]) {
1946 dev_kfree_skb(rxq
->rx_skb
[i
]);
1947 rxq
->rx_desc_count
--;
1951 if (rxq
->rx_desc_count
) {
1952 netdev_err(mp
->dev
, "error freeing rx ring -- %d skbs stuck\n",
1953 rxq
->rx_desc_count
);
1956 if (rxq
->index
== 0 &&
1957 rxq
->rx_desc_area_size
<= mp
->rx_desc_sram_size
)
1958 iounmap(rxq
->rx_desc_area
);
1960 dma_free_coherent(mp
->dev
->dev
.parent
, rxq
->rx_desc_area_size
,
1961 rxq
->rx_desc_area
, rxq
->rx_desc_dma
);
1966 static int txq_init(struct mv643xx_eth_private
*mp
, int index
)
1968 struct tx_queue
*txq
= mp
->txq
+ index
;
1969 struct tx_desc
*tx_desc
;
1975 txq
->tx_ring_size
= mp
->tx_ring_size
;
1977 txq
->tx_desc_count
= 0;
1978 txq
->tx_curr_desc
= 0;
1979 txq
->tx_used_desc
= 0;
1981 size
= txq
->tx_ring_size
* sizeof(struct tx_desc
);
1983 if (index
== 0 && size
<= mp
->tx_desc_sram_size
) {
1984 txq
->tx_desc_area
= ioremap(mp
->tx_desc_sram_addr
,
1985 mp
->tx_desc_sram_size
);
1986 txq
->tx_desc_dma
= mp
->tx_desc_sram_addr
;
1988 txq
->tx_desc_area
= dma_alloc_coherent(mp
->dev
->dev
.parent
,
1989 size
, &txq
->tx_desc_dma
,
1993 if (txq
->tx_desc_area
== NULL
) {
1995 "can't allocate tx ring (%d bytes)\n", size
);
1998 memset(txq
->tx_desc_area
, 0, size
);
2000 txq
->tx_desc_area_size
= size
;
2002 tx_desc
= (struct tx_desc
*)txq
->tx_desc_area
;
2003 for (i
= 0; i
< txq
->tx_ring_size
; i
++) {
2004 struct tx_desc
*txd
= tx_desc
+ i
;
2008 if (nexti
== txq
->tx_ring_size
)
2012 txd
->next_desc_ptr
= txq
->tx_desc_dma
+
2013 nexti
* sizeof(struct tx_desc
);
2016 skb_queue_head_init(&txq
->tx_skb
);
2021 static void txq_deinit(struct tx_queue
*txq
)
2023 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
2026 txq_reclaim(txq
, txq
->tx_ring_size
, 1);
2028 BUG_ON(txq
->tx_used_desc
!= txq
->tx_curr_desc
);
2030 if (txq
->index
== 0 &&
2031 txq
->tx_desc_area_size
<= mp
->tx_desc_sram_size
)
2032 iounmap(txq
->tx_desc_area
);
2034 dma_free_coherent(mp
->dev
->dev
.parent
, txq
->tx_desc_area_size
,
2035 txq
->tx_desc_area
, txq
->tx_desc_dma
);
2039 /* netdev ops and related ***************************************************/
2040 static int mv643xx_eth_collect_events(struct mv643xx_eth_private
*mp
)
2045 int_cause
= rdlp(mp
, INT_CAUSE
) & mp
->int_mask
;
2050 if (int_cause
& INT_EXT
) {
2051 int_cause
&= ~INT_EXT
;
2052 int_cause_ext
= rdlp(mp
, INT_CAUSE_EXT
);
2056 wrlp(mp
, INT_CAUSE
, ~int_cause
);
2057 mp
->work_tx_end
|= ((int_cause
& INT_TX_END
) >> 19) &
2058 ~(rdlp(mp
, TXQ_COMMAND
) & 0xff);
2059 mp
->work_rx
|= (int_cause
& INT_RX
) >> 2;
2062 int_cause_ext
&= INT_EXT_LINK_PHY
| INT_EXT_TX
;
2063 if (int_cause_ext
) {
2064 wrlp(mp
, INT_CAUSE_EXT
, ~int_cause_ext
);
2065 if (int_cause_ext
& INT_EXT_LINK_PHY
)
2067 mp
->work_tx
|= int_cause_ext
& INT_EXT_TX
;
2073 static irqreturn_t
mv643xx_eth_irq(int irq
, void *dev_id
)
2075 struct net_device
*dev
= (struct net_device
*)dev_id
;
2076 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2078 if (unlikely(!mv643xx_eth_collect_events(mp
)))
2081 wrlp(mp
, INT_MASK
, 0);
2082 napi_schedule(&mp
->napi
);
2087 static void handle_link_event(struct mv643xx_eth_private
*mp
)
2089 struct net_device
*dev
= mp
->dev
;
2095 port_status
= rdlp(mp
, PORT_STATUS
);
2096 if (!(port_status
& LINK_UP
)) {
2097 if (netif_carrier_ok(dev
)) {
2100 netdev_info(dev
, "link down\n");
2102 netif_carrier_off(dev
);
2104 for (i
= 0; i
< mp
->txq_count
; i
++) {
2105 struct tx_queue
*txq
= mp
->txq
+ i
;
2107 txq_reclaim(txq
, txq
->tx_ring_size
, 1);
2108 txq_reset_hw_ptr(txq
);
2114 switch (port_status
& PORT_SPEED_MASK
) {
2118 case PORT_SPEED_100
:
2121 case PORT_SPEED_1000
:
2128 duplex
= (port_status
& FULL_DUPLEX
) ? 1 : 0;
2129 fc
= (port_status
& FLOW_CONTROL_ENABLED
) ? 1 : 0;
2131 netdev_info(dev
, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2132 speed
, duplex
? "full" : "half", fc
? "en" : "dis");
2134 if (!netif_carrier_ok(dev
))
2135 netif_carrier_on(dev
);
2138 static int mv643xx_eth_poll(struct napi_struct
*napi
, int budget
)
2140 struct mv643xx_eth_private
*mp
;
2143 mp
= container_of(napi
, struct mv643xx_eth_private
, napi
);
2145 if (unlikely(mp
->oom
)) {
2147 del_timer(&mp
->rx_oom
);
2151 while (work_done
< budget
) {
2156 if (mp
->work_link
) {
2158 handle_link_event(mp
);
2163 queue_mask
= mp
->work_tx
| mp
->work_tx_end
| mp
->work_rx
;
2164 if (likely(!mp
->oom
))
2165 queue_mask
|= mp
->work_rx_refill
;
2168 if (mv643xx_eth_collect_events(mp
))
2173 queue
= fls(queue_mask
) - 1;
2174 queue_mask
= 1 << queue
;
2176 work_tbd
= budget
- work_done
;
2180 if (mp
->work_tx_end
& queue_mask
) {
2181 txq_kick(mp
->txq
+ queue
);
2182 } else if (mp
->work_tx
& queue_mask
) {
2183 work_done
+= txq_reclaim(mp
->txq
+ queue
, work_tbd
, 0);
2184 txq_maybe_wake(mp
->txq
+ queue
);
2185 } else if (mp
->work_rx
& queue_mask
) {
2186 work_done
+= rxq_process(mp
->rxq
+ queue
, work_tbd
);
2187 } else if (!mp
->oom
&& (mp
->work_rx_refill
& queue_mask
)) {
2188 work_done
+= rxq_refill(mp
->rxq
+ queue
, work_tbd
);
2194 if (work_done
< budget
) {
2196 mod_timer(&mp
->rx_oom
, jiffies
+ (HZ
/ 10));
2197 napi_complete(napi
);
2198 wrlp(mp
, INT_MASK
, mp
->int_mask
);
2204 static inline void oom_timer_wrapper(unsigned long data
)
2206 struct mv643xx_eth_private
*mp
= (void *)data
;
2208 napi_schedule(&mp
->napi
);
2211 static void phy_reset(struct mv643xx_eth_private
*mp
)
2215 data
= phy_read(mp
->phy
, MII_BMCR
);
2220 if (phy_write(mp
->phy
, MII_BMCR
, data
) < 0)
2224 data
= phy_read(mp
->phy
, MII_BMCR
);
2225 } while (data
>= 0 && data
& BMCR_RESET
);
2228 static void port_start(struct mv643xx_eth_private
*mp
)
2234 * Perform PHY reset, if there is a PHY.
2236 if (mp
->phy
!= NULL
) {
2237 struct ethtool_cmd cmd
;
2239 mv643xx_eth_get_settings(mp
->dev
, &cmd
);
2241 mv643xx_eth_set_settings(mp
->dev
, &cmd
);
2245 * Configure basic link parameters.
2247 pscr
= rdlp(mp
, PORT_SERIAL_CONTROL
);
2249 pscr
|= SERIAL_PORT_ENABLE
;
2250 wrlp(mp
, PORT_SERIAL_CONTROL
, pscr
);
2252 pscr
|= DO_NOT_FORCE_LINK_FAIL
;
2253 if (mp
->phy
== NULL
)
2254 pscr
|= FORCE_LINK_PASS
;
2255 wrlp(mp
, PORT_SERIAL_CONTROL
, pscr
);
2258 * Configure TX path and queues.
2260 tx_set_rate(mp
, 1000000000, 16777216);
2261 for (i
= 0; i
< mp
->txq_count
; i
++) {
2262 struct tx_queue
*txq
= mp
->txq
+ i
;
2264 txq_reset_hw_ptr(txq
);
2265 txq_set_rate(txq
, 1000000000, 16777216);
2266 txq_set_fixed_prio_mode(txq
);
2270 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2271 * frames to RX queue #0, and include the pseudo-header when
2272 * calculating receive checksums.
2274 mv643xx_eth_set_features(mp
->dev
, mp
->dev
->features
);
2277 * Treat BPDUs as normal multicasts, and disable partition mode.
2279 wrlp(mp
, PORT_CONFIG_EXT
, 0x00000000);
2282 * Add configured unicast addresses to address filter table.
2284 mv643xx_eth_program_unicast_filter(mp
->dev
);
2287 * Enable the receive queues.
2289 for (i
= 0; i
< mp
->rxq_count
; i
++) {
2290 struct rx_queue
*rxq
= mp
->rxq
+ i
;
2293 addr
= (u32
)rxq
->rx_desc_dma
;
2294 addr
+= rxq
->rx_curr_desc
* sizeof(struct rx_desc
);
2295 wrlp(mp
, RXQ_CURRENT_DESC_PTR(i
), addr
);
2301 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private
*mp
)
2306 * Reserve 2+14 bytes for an ethernet header (the hardware
2307 * automatically prepends 2 bytes of dummy data to each
2308 * received packet), 16 bytes for up to four VLAN tags, and
2309 * 4 bytes for the trailing FCS -- 36 bytes total.
2311 skb_size
= mp
->dev
->mtu
+ 36;
2314 * Make sure that the skb size is a multiple of 8 bytes, as
2315 * the lower three bits of the receive descriptor's buffer
2316 * size field are ignored by the hardware.
2318 mp
->skb_size
= (skb_size
+ 7) & ~7;
2321 * If NET_SKB_PAD is smaller than a cache line,
2322 * netdev_alloc_skb() will cause skb->data to be misaligned
2323 * to a cache line boundary. If this is the case, include
2324 * some extra space to allow re-aligning the data area.
2326 mp
->skb_size
+= SKB_DMA_REALIGN
;
2329 static int mv643xx_eth_open(struct net_device
*dev
)
2331 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2335 wrlp(mp
, INT_CAUSE
, 0);
2336 wrlp(mp
, INT_CAUSE_EXT
, 0);
2337 rdlp(mp
, INT_CAUSE_EXT
);
2339 err
= request_irq(dev
->irq
, mv643xx_eth_irq
,
2340 IRQF_SHARED
, dev
->name
, dev
);
2342 netdev_err(dev
, "can't assign irq\n");
2346 mv643xx_eth_recalc_skb_size(mp
);
2348 napi_enable(&mp
->napi
);
2350 skb_queue_head_init(&mp
->rx_recycle
);
2352 mp
->int_mask
= INT_EXT
;
2354 for (i
= 0; i
< mp
->rxq_count
; i
++) {
2355 err
= rxq_init(mp
, i
);
2358 rxq_deinit(mp
->rxq
+ i
);
2362 rxq_refill(mp
->rxq
+ i
, INT_MAX
);
2363 mp
->int_mask
|= INT_RX_0
<< i
;
2367 mp
->rx_oom
.expires
= jiffies
+ (HZ
/ 10);
2368 add_timer(&mp
->rx_oom
);
2371 for (i
= 0; i
< mp
->txq_count
; i
++) {
2372 err
= txq_init(mp
, i
);
2375 txq_deinit(mp
->txq
+ i
);
2378 mp
->int_mask
|= INT_TX_END_0
<< i
;
2383 wrlp(mp
, INT_MASK_EXT
, INT_EXT_LINK_PHY
| INT_EXT_TX
);
2384 wrlp(mp
, INT_MASK
, mp
->int_mask
);
2390 for (i
= 0; i
< mp
->rxq_count
; i
++)
2391 rxq_deinit(mp
->rxq
+ i
);
2393 free_irq(dev
->irq
, dev
);
2398 static void port_reset(struct mv643xx_eth_private
*mp
)
2403 for (i
= 0; i
< mp
->rxq_count
; i
++)
2404 rxq_disable(mp
->rxq
+ i
);
2405 for (i
= 0; i
< mp
->txq_count
; i
++)
2406 txq_disable(mp
->txq
+ i
);
2409 u32 ps
= rdlp(mp
, PORT_STATUS
);
2411 if ((ps
& (TX_IN_PROGRESS
| TX_FIFO_EMPTY
)) == TX_FIFO_EMPTY
)
2416 /* Reset the Enable bit in the Configuration Register */
2417 data
= rdlp(mp
, PORT_SERIAL_CONTROL
);
2418 data
&= ~(SERIAL_PORT_ENABLE
|
2419 DO_NOT_FORCE_LINK_FAIL
|
2421 wrlp(mp
, PORT_SERIAL_CONTROL
, data
);
2424 static int mv643xx_eth_stop(struct net_device
*dev
)
2426 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2429 wrlp(mp
, INT_MASK_EXT
, 0x00000000);
2430 wrlp(mp
, INT_MASK
, 0x00000000);
2433 napi_disable(&mp
->napi
);
2435 del_timer_sync(&mp
->rx_oom
);
2437 netif_carrier_off(dev
);
2439 free_irq(dev
->irq
, dev
);
2442 mv643xx_eth_get_stats(dev
);
2443 mib_counters_update(mp
);
2444 del_timer_sync(&mp
->mib_counters_timer
);
2446 skb_queue_purge(&mp
->rx_recycle
);
2448 for (i
= 0; i
< mp
->rxq_count
; i
++)
2449 rxq_deinit(mp
->rxq
+ i
);
2450 for (i
= 0; i
< mp
->txq_count
; i
++)
2451 txq_deinit(mp
->txq
+ i
);
2456 static int mv643xx_eth_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2458 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2460 if (mp
->phy
!= NULL
)
2461 return phy_mii_ioctl(mp
->phy
, ifr
, cmd
);
2466 static int mv643xx_eth_change_mtu(struct net_device
*dev
, int new_mtu
)
2468 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2470 if (new_mtu
< 64 || new_mtu
> 9500)
2474 mv643xx_eth_recalc_skb_size(mp
);
2475 tx_set_rate(mp
, 1000000000, 16777216);
2477 if (!netif_running(dev
))
2481 * Stop and then re-open the interface. This will allocate RX
2482 * skbs of the new MTU.
2483 * There is a possible danger that the open will not succeed,
2484 * due to memory being full.
2486 mv643xx_eth_stop(dev
);
2487 if (mv643xx_eth_open(dev
)) {
2489 "fatal error on re-opening device after MTU change\n");
2495 static void tx_timeout_task(struct work_struct
*ugly
)
2497 struct mv643xx_eth_private
*mp
;
2499 mp
= container_of(ugly
, struct mv643xx_eth_private
, tx_timeout_task
);
2500 if (netif_running(mp
->dev
)) {
2501 netif_tx_stop_all_queues(mp
->dev
);
2504 netif_tx_wake_all_queues(mp
->dev
);
2508 static void mv643xx_eth_tx_timeout(struct net_device
*dev
)
2510 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2512 netdev_info(dev
, "tx timeout\n");
2514 schedule_work(&mp
->tx_timeout_task
);
2517 #ifdef CONFIG_NET_POLL_CONTROLLER
2518 static void mv643xx_eth_netpoll(struct net_device
*dev
)
2520 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2522 wrlp(mp
, INT_MASK
, 0x00000000);
2525 mv643xx_eth_irq(dev
->irq
, dev
);
2527 wrlp(mp
, INT_MASK
, mp
->int_mask
);
2532 /* platform glue ************************************************************/
2534 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private
*msp
,
2535 const struct mbus_dram_target_info
*dram
)
2537 void __iomem
*base
= msp
->base
;
2542 for (i
= 0; i
< 6; i
++) {
2543 writel(0, base
+ WINDOW_BASE(i
));
2544 writel(0, base
+ WINDOW_SIZE(i
));
2546 writel(0, base
+ WINDOW_REMAP_HIGH(i
));
2552 for (i
= 0; i
< dram
->num_cs
; i
++) {
2553 const struct mbus_dram_window
*cs
= dram
->cs
+ i
;
2555 writel((cs
->base
& 0xffff0000) |
2556 (cs
->mbus_attr
<< 8) |
2557 dram
->mbus_dram_target_id
, base
+ WINDOW_BASE(i
));
2558 writel((cs
->size
- 1) & 0xffff0000, base
+ WINDOW_SIZE(i
));
2560 win_enable
&= ~(1 << i
);
2561 win_protect
|= 3 << (2 * i
);
2564 writel(win_enable
, base
+ WINDOW_BAR_ENABLE
);
2565 msp
->win_protect
= win_protect
;
2568 static void infer_hw_params(struct mv643xx_eth_shared_private
*msp
)
2571 * Check whether we have a 14-bit coal limit field in bits
2572 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2573 * SDMA config register.
2575 writel(0x02000000, msp
->base
+ 0x0400 + SDMA_CONFIG
);
2576 if (readl(msp
->base
+ 0x0400 + SDMA_CONFIG
) & 0x02000000)
2577 msp
->extended_rx_coal_limit
= 1;
2579 msp
->extended_rx_coal_limit
= 0;
2582 * Check whether the MAC supports TX rate control, and if
2583 * yes, whether its associated registers are in the old or
2586 writel(1, msp
->base
+ 0x0400 + TX_BW_MTU_MOVED
);
2587 if (readl(msp
->base
+ 0x0400 + TX_BW_MTU_MOVED
) & 1) {
2588 msp
->tx_bw_control
= TX_BW_CONTROL_NEW_LAYOUT
;
2590 writel(7, msp
->base
+ 0x0400 + TX_BW_RATE
);
2591 if (readl(msp
->base
+ 0x0400 + TX_BW_RATE
) & 7)
2592 msp
->tx_bw_control
= TX_BW_CONTROL_OLD_LAYOUT
;
2594 msp
->tx_bw_control
= TX_BW_CONTROL_ABSENT
;
2598 static int mv643xx_eth_shared_probe(struct platform_device
*pdev
)
2600 static int mv643xx_eth_version_printed
;
2601 struct mv643xx_eth_shared_platform_data
*pd
= pdev
->dev
.platform_data
;
2602 struct mv643xx_eth_shared_private
*msp
;
2603 const struct mbus_dram_target_info
*dram
;
2604 struct resource
*res
;
2607 if (!mv643xx_eth_version_printed
++)
2608 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2609 mv643xx_eth_driver_version
);
2612 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2617 msp
= kzalloc(sizeof(*msp
), GFP_KERNEL
);
2621 msp
->base
= ioremap(res
->start
, resource_size(res
));
2622 if (msp
->base
== NULL
)
2626 * Set up and register SMI bus.
2628 if (pd
== NULL
|| pd
->shared_smi
== NULL
) {
2629 msp
->smi_bus
= mdiobus_alloc();
2630 if (msp
->smi_bus
== NULL
)
2633 msp
->smi_bus
->priv
= msp
;
2634 msp
->smi_bus
->name
= "mv643xx_eth smi";
2635 msp
->smi_bus
->read
= smi_bus_read
;
2636 msp
->smi_bus
->write
= smi_bus_write
,
2637 snprintf(msp
->smi_bus
->id
, MII_BUS_ID_SIZE
, "%s-%d",
2638 pdev
->name
, pdev
->id
);
2639 msp
->smi_bus
->parent
= &pdev
->dev
;
2640 msp
->smi_bus
->phy_mask
= 0xffffffff;
2641 if (mdiobus_register(msp
->smi_bus
) < 0)
2642 goto out_free_mii_bus
;
2645 msp
->smi
= platform_get_drvdata(pd
->shared_smi
);
2648 msp
->err_interrupt
= NO_IRQ
;
2649 init_waitqueue_head(&msp
->smi_busy_wait
);
2652 * Check whether the error interrupt is hooked up.
2654 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
2658 err
= request_irq(res
->start
, mv643xx_eth_err_irq
,
2659 IRQF_SHARED
, "mv643xx_eth", msp
);
2661 writel(ERR_INT_SMI_DONE
, msp
->base
+ ERR_INT_MASK
);
2662 msp
->err_interrupt
= res
->start
;
2667 * (Re-)program MBUS remapping windows if we are asked to.
2669 dram
= mv_mbus_dram_info();
2671 mv643xx_eth_conf_mbus_windows(msp
, dram
);
2673 msp
->tx_csum_limit
= (pd
!= NULL
&& pd
->tx_csum_limit
) ?
2674 pd
->tx_csum_limit
: 9 * 1024;
2675 infer_hw_params(msp
);
2677 platform_set_drvdata(pdev
, msp
);
2682 mdiobus_free(msp
->smi_bus
);
2691 static int mv643xx_eth_shared_remove(struct platform_device
*pdev
)
2693 struct mv643xx_eth_shared_private
*msp
= platform_get_drvdata(pdev
);
2694 struct mv643xx_eth_shared_platform_data
*pd
= pdev
->dev
.platform_data
;
2696 if (pd
== NULL
|| pd
->shared_smi
== NULL
) {
2697 mdiobus_unregister(msp
->smi_bus
);
2698 mdiobus_free(msp
->smi_bus
);
2700 if (msp
->err_interrupt
!= NO_IRQ
)
2701 free_irq(msp
->err_interrupt
, msp
);
2708 static struct platform_driver mv643xx_eth_shared_driver
= {
2709 .probe
= mv643xx_eth_shared_probe
,
2710 .remove
= mv643xx_eth_shared_remove
,
2712 .name
= MV643XX_ETH_SHARED_NAME
,
2713 .owner
= THIS_MODULE
,
2717 static void phy_addr_set(struct mv643xx_eth_private
*mp
, int phy_addr
)
2719 int addr_shift
= 5 * mp
->port_num
;
2722 data
= rdl(mp
, PHY_ADDR
);
2723 data
&= ~(0x1f << addr_shift
);
2724 data
|= (phy_addr
& 0x1f) << addr_shift
;
2725 wrl(mp
, PHY_ADDR
, data
);
2728 static int phy_addr_get(struct mv643xx_eth_private
*mp
)
2732 data
= rdl(mp
, PHY_ADDR
);
2734 return (data
>> (5 * mp
->port_num
)) & 0x1f;
2737 static void set_params(struct mv643xx_eth_private
*mp
,
2738 struct mv643xx_eth_platform_data
*pd
)
2740 struct net_device
*dev
= mp
->dev
;
2742 if (is_valid_ether_addr(pd
->mac_addr
))
2743 memcpy(dev
->dev_addr
, pd
->mac_addr
, 6);
2745 uc_addr_get(mp
, dev
->dev_addr
);
2747 mp
->rx_ring_size
= DEFAULT_RX_QUEUE_SIZE
;
2748 if (pd
->rx_queue_size
)
2749 mp
->rx_ring_size
= pd
->rx_queue_size
;
2750 mp
->rx_desc_sram_addr
= pd
->rx_sram_addr
;
2751 mp
->rx_desc_sram_size
= pd
->rx_sram_size
;
2753 mp
->rxq_count
= pd
->rx_queue_count
? : 1;
2755 mp
->tx_ring_size
= DEFAULT_TX_QUEUE_SIZE
;
2756 if (pd
->tx_queue_size
)
2757 mp
->tx_ring_size
= pd
->tx_queue_size
;
2758 mp
->tx_desc_sram_addr
= pd
->tx_sram_addr
;
2759 mp
->tx_desc_sram_size
= pd
->tx_sram_size
;
2761 mp
->txq_count
= pd
->tx_queue_count
? : 1;
2764 static struct phy_device
*phy_scan(struct mv643xx_eth_private
*mp
,
2767 struct mii_bus
*bus
= mp
->shared
->smi
->smi_bus
;
2768 struct phy_device
*phydev
;
2773 if (phy_addr
== MV643XX_ETH_PHY_ADDR_DEFAULT
) {
2774 start
= phy_addr_get(mp
) & 0x1f;
2777 start
= phy_addr
& 0x1f;
2782 for (i
= 0; i
< num
; i
++) {
2783 int addr
= (start
+ i
) & 0x1f;
2785 if (bus
->phy_map
[addr
] == NULL
)
2786 mdiobus_scan(bus
, addr
);
2788 if (phydev
== NULL
) {
2789 phydev
= bus
->phy_map
[addr
];
2791 phy_addr_set(mp
, addr
);
2798 static void phy_init(struct mv643xx_eth_private
*mp
, int speed
, int duplex
)
2800 struct phy_device
*phy
= mp
->phy
;
2804 phy_attach(mp
->dev
, dev_name(&phy
->dev
), 0, PHY_INTERFACE_MODE_GMII
);
2807 phy
->autoneg
= AUTONEG_ENABLE
;
2810 phy
->advertising
= phy
->supported
| ADVERTISED_Autoneg
;
2812 phy
->autoneg
= AUTONEG_DISABLE
;
2813 phy
->advertising
= 0;
2815 phy
->duplex
= duplex
;
2817 phy_start_aneg(phy
);
2820 static void init_pscr(struct mv643xx_eth_private
*mp
, int speed
, int duplex
)
2824 pscr
= rdlp(mp
, PORT_SERIAL_CONTROL
);
2825 if (pscr
& SERIAL_PORT_ENABLE
) {
2826 pscr
&= ~SERIAL_PORT_ENABLE
;
2827 wrlp(mp
, PORT_SERIAL_CONTROL
, pscr
);
2830 pscr
= MAX_RX_PACKET_9700BYTE
| SERIAL_PORT_CONTROL_RESERVED
;
2831 if (mp
->phy
== NULL
) {
2832 pscr
|= DISABLE_AUTO_NEG_SPEED_GMII
;
2833 if (speed
== SPEED_1000
)
2834 pscr
|= SET_GMII_SPEED_TO_1000
;
2835 else if (speed
== SPEED_100
)
2836 pscr
|= SET_MII_SPEED_TO_100
;
2838 pscr
|= DISABLE_AUTO_NEG_FOR_FLOW_CTRL
;
2840 pscr
|= DISABLE_AUTO_NEG_FOR_DUPLEX
;
2841 if (duplex
== DUPLEX_FULL
)
2842 pscr
|= SET_FULL_DUPLEX_MODE
;
2845 wrlp(mp
, PORT_SERIAL_CONTROL
, pscr
);
2848 static const struct net_device_ops mv643xx_eth_netdev_ops
= {
2849 .ndo_open
= mv643xx_eth_open
,
2850 .ndo_stop
= mv643xx_eth_stop
,
2851 .ndo_start_xmit
= mv643xx_eth_xmit
,
2852 .ndo_set_rx_mode
= mv643xx_eth_set_rx_mode
,
2853 .ndo_set_mac_address
= mv643xx_eth_set_mac_address
,
2854 .ndo_validate_addr
= eth_validate_addr
,
2855 .ndo_do_ioctl
= mv643xx_eth_ioctl
,
2856 .ndo_change_mtu
= mv643xx_eth_change_mtu
,
2857 .ndo_set_features
= mv643xx_eth_set_features
,
2858 .ndo_tx_timeout
= mv643xx_eth_tx_timeout
,
2859 .ndo_get_stats
= mv643xx_eth_get_stats
,
2860 #ifdef CONFIG_NET_POLL_CONTROLLER
2861 .ndo_poll_controller
= mv643xx_eth_netpoll
,
2865 static int mv643xx_eth_probe(struct platform_device
*pdev
)
2867 struct mv643xx_eth_platform_data
*pd
;
2868 struct mv643xx_eth_private
*mp
;
2869 struct net_device
*dev
;
2870 struct resource
*res
;
2873 pd
= pdev
->dev
.platform_data
;
2875 dev_err(&pdev
->dev
, "no mv643xx_eth_platform_data\n");
2879 if (pd
->shared
== NULL
) {
2880 dev_err(&pdev
->dev
, "no mv643xx_eth_platform_data->shared\n");
2884 dev
= alloc_etherdev_mq(sizeof(struct mv643xx_eth_private
), 8);
2888 mp
= netdev_priv(dev
);
2889 platform_set_drvdata(pdev
, mp
);
2891 mp
->shared
= platform_get_drvdata(pd
->shared
);
2892 mp
->base
= mp
->shared
->base
+ 0x0400 + (pd
->port_number
<< 10);
2893 mp
->port_num
= pd
->port_number
;
2898 * Get the clk rate, if there is one, otherwise use the default.
2900 mp
->clk
= clk_get(&pdev
->dev
, (pdev
->id
? "1" : "0"));
2901 if (!IS_ERR(mp
->clk
)) {
2902 clk_prepare_enable(mp
->clk
);
2903 mp
->t_clk
= clk_get_rate(mp
->clk
);
2905 mp
->t_clk
= 133000000;
2906 printk(KERN_WARNING
"Unable to get clock");
2910 netif_set_real_num_tx_queues(dev
, mp
->txq_count
);
2911 netif_set_real_num_rx_queues(dev
, mp
->rxq_count
);
2913 if (pd
->phy_addr
!= MV643XX_ETH_PHY_NONE
)
2914 mp
->phy
= phy_scan(mp
, pd
->phy_addr
);
2916 if (mp
->phy
!= NULL
)
2917 phy_init(mp
, pd
->speed
, pd
->duplex
);
2919 SET_ETHTOOL_OPS(dev
, &mv643xx_eth_ethtool_ops
);
2921 init_pscr(mp
, pd
->speed
, pd
->duplex
);
2924 mib_counters_clear(mp
);
2926 init_timer(&mp
->mib_counters_timer
);
2927 mp
->mib_counters_timer
.data
= (unsigned long)mp
;
2928 mp
->mib_counters_timer
.function
= mib_counters_timer_wrapper
;
2929 mp
->mib_counters_timer
.expires
= jiffies
+ 30 * HZ
;
2930 add_timer(&mp
->mib_counters_timer
);
2932 spin_lock_init(&mp
->mib_counters_lock
);
2934 INIT_WORK(&mp
->tx_timeout_task
, tx_timeout_task
);
2936 netif_napi_add(dev
, &mp
->napi
, mv643xx_eth_poll
, 128);
2938 init_timer(&mp
->rx_oom
);
2939 mp
->rx_oom
.data
= (unsigned long)mp
;
2940 mp
->rx_oom
.function
= oom_timer_wrapper
;
2943 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
2945 dev
->irq
= res
->start
;
2947 dev
->netdev_ops
= &mv643xx_eth_netdev_ops
;
2949 dev
->watchdog_timeo
= 2 * HZ
;
2952 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
|
2953 NETIF_F_RXCSUM
| NETIF_F_LRO
;
2954 dev
->features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_RXCSUM
;
2955 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
;
2957 dev
->priv_flags
|= IFF_UNICAST_FLT
;
2959 SET_NETDEV_DEV(dev
, &pdev
->dev
);
2961 if (mp
->shared
->win_protect
)
2962 wrl(mp
, WINDOW_PROTECT(mp
->port_num
), mp
->shared
->win_protect
);
2964 netif_carrier_off(dev
);
2966 wrlp(mp
, SDMA_CONFIG
, PORT_SDMA_CONFIG_DEFAULT_VALUE
);
2968 set_rx_coal(mp
, 250);
2971 err
= register_netdev(dev
);
2975 netdev_notice(dev
, "port %d with MAC address %pM\n",
2976 mp
->port_num
, dev
->dev_addr
);
2978 if (mp
->tx_desc_sram_size
> 0)
2979 netdev_notice(dev
, "configured with sram\n");
2989 static int mv643xx_eth_remove(struct platform_device
*pdev
)
2991 struct mv643xx_eth_private
*mp
= platform_get_drvdata(pdev
);
2993 unregister_netdev(mp
->dev
);
2994 if (mp
->phy
!= NULL
)
2995 phy_detach(mp
->phy
);
2996 cancel_work_sync(&mp
->tx_timeout_task
);
2998 if (!IS_ERR(mp
->clk
)) {
2999 clk_disable_unprepare(mp
->clk
);
3002 free_netdev(mp
->dev
);
3004 platform_set_drvdata(pdev
, NULL
);
3009 static void mv643xx_eth_shutdown(struct platform_device
*pdev
)
3011 struct mv643xx_eth_private
*mp
= platform_get_drvdata(pdev
);
3013 /* Mask all interrupts on ethernet port */
3014 wrlp(mp
, INT_MASK
, 0);
3017 if (netif_running(mp
->dev
))
3021 static struct platform_driver mv643xx_eth_driver
= {
3022 .probe
= mv643xx_eth_probe
,
3023 .remove
= mv643xx_eth_remove
,
3024 .shutdown
= mv643xx_eth_shutdown
,
3026 .name
= MV643XX_ETH_NAME
,
3027 .owner
= THIS_MODULE
,
3031 static int __init
mv643xx_eth_init_module(void)
3035 rc
= platform_driver_register(&mv643xx_eth_shared_driver
);
3037 rc
= platform_driver_register(&mv643xx_eth_driver
);
3039 platform_driver_unregister(&mv643xx_eth_shared_driver
);
3044 module_init(mv643xx_eth_init_module
);
3046 static void __exit
mv643xx_eth_cleanup_module(void)
3048 platform_driver_unregister(&mv643xx_eth_driver
);
3049 platform_driver_unregister(&mv643xx_eth_shared_driver
);
3051 module_exit(mv643xx_eth_cleanup_module
);
3053 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3054 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3055 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3056 MODULE_LICENSE("GPL");
3057 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME
);
3058 MODULE_ALIAS("platform:" MV643XX_ETH_NAME
);