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net: pxa168_eth: Prepare proper libphy handling
[deliverable/linux.git] / drivers / net / ethernet / marvell / pxa168_eth.c
1 /*
2 * PXA168 ethernet driver.
3 * Most of the code is derived from mv643xx ethernet driver.
4 *
5 * Copyright (C) 2010 Marvell International Ltd.
6 * Sachin Sanap <ssanap@marvell.com>
7 * Zhangfei Gao <zgao6@marvell.com>
8 * Philip Rakity <prakity@marvell.com>
9 * Mark Brown <markb@marvell.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version 2
14 * of the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include <linux/bitops.h>
26 #include <linux/clk.h>
27 #include <linux/delay.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/etherdevice.h>
30 #include <linux/ethtool.h>
31 #include <linux/in.h>
32 #include <linux/interrupt.h>
33 #include <linux/io.h>
34 #include <linux/ip.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/of.h>
38 #include <linux/of_net.h>
39 #include <linux/phy.h>
40 #include <linux/platform_device.h>
41 #include <linux/pxa168_eth.h>
42 #include <linux/tcp.h>
43 #include <linux/types.h>
44 #include <linux/udp.h>
45 #include <linux/workqueue.h>
46
47 #include <asm/pgtable.h>
48 #include <asm/cacheflush.h>
49
50 #define DRIVER_NAME "pxa168-eth"
51 #define DRIVER_VERSION "0.3"
52
53 /*
54 * Registers
55 */
56
57 #define PHY_ADDRESS 0x0000
58 #define SMI 0x0010
59 #define PORT_CONFIG 0x0400
60 #define PORT_CONFIG_EXT 0x0408
61 #define PORT_COMMAND 0x0410
62 #define PORT_STATUS 0x0418
63 #define HTPR 0x0428
64 #define MAC_ADDR_LOW 0x0430
65 #define MAC_ADDR_HIGH 0x0438
66 #define SDMA_CONFIG 0x0440
67 #define SDMA_CMD 0x0448
68 #define INT_CAUSE 0x0450
69 #define INT_W_CLEAR 0x0454
70 #define INT_MASK 0x0458
71 #define ETH_F_RX_DESC_0 0x0480
72 #define ETH_C_RX_DESC_0 0x04A0
73 #define ETH_C_TX_DESC_1 0x04E4
74
75 /* smi register */
76 #define SMI_BUSY (1 << 28) /* 0 - Write, 1 - Read */
77 #define SMI_R_VALID (1 << 27) /* 0 - Write, 1 - Read */
78 #define SMI_OP_W (0 << 26) /* Write operation */
79 #define SMI_OP_R (1 << 26) /* Read operation */
80
81 #define PHY_WAIT_ITERATIONS 10
82
83 #define PXA168_ETH_PHY_ADDR_DEFAULT 0
84 /* RX & TX descriptor command */
85 #define BUF_OWNED_BY_DMA (1 << 31)
86
87 /* RX descriptor status */
88 #define RX_EN_INT (1 << 23)
89 #define RX_FIRST_DESC (1 << 17)
90 #define RX_LAST_DESC (1 << 16)
91 #define RX_ERROR (1 << 15)
92
93 /* TX descriptor command */
94 #define TX_EN_INT (1 << 23)
95 #define TX_GEN_CRC (1 << 22)
96 #define TX_ZERO_PADDING (1 << 18)
97 #define TX_FIRST_DESC (1 << 17)
98 #define TX_LAST_DESC (1 << 16)
99 #define TX_ERROR (1 << 15)
100
101 /* SDMA_CMD */
102 #define SDMA_CMD_AT (1 << 31)
103 #define SDMA_CMD_TXDL (1 << 24)
104 #define SDMA_CMD_TXDH (1 << 23)
105 #define SDMA_CMD_AR (1 << 15)
106 #define SDMA_CMD_ERD (1 << 7)
107
108 /* Bit definitions of the Port Config Reg */
109 #define PCR_HS (1 << 12)
110 #define PCR_EN (1 << 7)
111 #define PCR_PM (1 << 0)
112
113 /* Bit definitions of the Port Config Extend Reg */
114 #define PCXR_2BSM (1 << 28)
115 #define PCXR_DSCP_EN (1 << 21)
116 #define PCXR_MFL_1518 (0 << 14)
117 #define PCXR_MFL_1536 (1 << 14)
118 #define PCXR_MFL_2048 (2 << 14)
119 #define PCXR_MFL_64K (3 << 14)
120 #define PCXR_FLP (1 << 11)
121 #define PCXR_PRIO_TX_OFF 3
122 #define PCXR_TX_HIGH_PRI (7 << PCXR_PRIO_TX_OFF)
123
124 /* Bit definitions of the SDMA Config Reg */
125 #define SDCR_BSZ_OFF 12
126 #define SDCR_BSZ8 (3 << SDCR_BSZ_OFF)
127 #define SDCR_BSZ4 (2 << SDCR_BSZ_OFF)
128 #define SDCR_BSZ2 (1 << SDCR_BSZ_OFF)
129 #define SDCR_BSZ1 (0 << SDCR_BSZ_OFF)
130 #define SDCR_BLMR (1 << 6)
131 #define SDCR_BLMT (1 << 7)
132 #define SDCR_RIFB (1 << 9)
133 #define SDCR_RC_OFF 2
134 #define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF)
135
136 /*
137 * Bit definitions of the Interrupt Cause Reg
138 * and Interrupt MASK Reg is the same
139 */
140 #define ICR_RXBUF (1 << 0)
141 #define ICR_TXBUF_H (1 << 2)
142 #define ICR_TXBUF_L (1 << 3)
143 #define ICR_TXEND_H (1 << 6)
144 #define ICR_TXEND_L (1 << 7)
145 #define ICR_RXERR (1 << 8)
146 #define ICR_TXERR_H (1 << 10)
147 #define ICR_TXERR_L (1 << 11)
148 #define ICR_TX_UDR (1 << 13)
149 #define ICR_MII_CH (1 << 28)
150
151 #define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\
152 ICR_TXERR_H | ICR_TXERR_L |\
153 ICR_TXEND_H | ICR_TXEND_L |\
154 ICR_RXBUF | ICR_RXERR | ICR_MII_CH)
155
156 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
157
158 #define NUM_RX_DESCS 64
159 #define NUM_TX_DESCS 64
160
161 #define HASH_ADD 0
162 #define HASH_DELETE 1
163 #define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */
164 #define HOP_NUMBER 12
165
166 /* Bit definitions for Port status */
167 #define PORT_SPEED_100 (1 << 0)
168 #define FULL_DUPLEX (1 << 1)
169 #define FLOW_CONTROL_DISABLED (1 << 2)
170 #define LINK_UP (1 << 3)
171
172 /* Bit definitions for work to be done */
173 #define WORK_LINK (1 << 0)
174 #define WORK_TX_DONE (1 << 1)
175
176 /*
177 * Misc definitions.
178 */
179 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
180
181 struct rx_desc {
182 u32 cmd_sts; /* Descriptor command status */
183 u16 byte_cnt; /* Descriptor buffer byte count */
184 u16 buf_size; /* Buffer size */
185 u32 buf_ptr; /* Descriptor buffer pointer */
186 u32 next_desc_ptr; /* Next descriptor pointer */
187 };
188
189 struct tx_desc {
190 u32 cmd_sts; /* Command/status field */
191 u16 reserved;
192 u16 byte_cnt; /* buffer byte count */
193 u32 buf_ptr; /* pointer to buffer for this descriptor */
194 u32 next_desc_ptr; /* Pointer to next descriptor */
195 };
196
197 struct pxa168_eth_private {
198 int port_num; /* User Ethernet port number */
199 int phy_addr;
200 int phy_speed;
201 int phy_duplex;
202 phy_interface_t phy_intf;
203
204 int rx_resource_err; /* Rx ring resource error flag */
205
206 /* Next available and first returning Rx resource */
207 int rx_curr_desc_q, rx_used_desc_q;
208
209 /* Next available and first returning Tx resource */
210 int tx_curr_desc_q, tx_used_desc_q;
211
212 struct rx_desc *p_rx_desc_area;
213 dma_addr_t rx_desc_dma;
214 int rx_desc_area_size;
215 struct sk_buff **rx_skb;
216
217 struct tx_desc *p_tx_desc_area;
218 dma_addr_t tx_desc_dma;
219 int tx_desc_area_size;
220 struct sk_buff **tx_skb;
221
222 struct work_struct tx_timeout_task;
223
224 struct net_device *dev;
225 struct napi_struct napi;
226 u8 work_todo;
227 int skb_size;
228
229 /* Size of Tx Ring per queue */
230 int tx_ring_size;
231 /* Number of tx descriptors in use */
232 int tx_desc_count;
233 /* Size of Rx Ring per queue */
234 int rx_ring_size;
235 /* Number of rx descriptors in use */
236 int rx_desc_count;
237
238 /*
239 * Used in case RX Ring is empty, which can occur when
240 * system does not have resources (skb's)
241 */
242 struct timer_list timeout;
243 struct mii_bus *smi_bus;
244 struct phy_device *phy;
245
246 /* clock */
247 struct clk *clk;
248 struct pxa168_eth_platform_data *pd;
249 /*
250 * Ethernet controller base address.
251 */
252 void __iomem *base;
253
254 /* Pointer to the hardware address filter table */
255 void *htpr;
256 dma_addr_t htpr_dma;
257 };
258
259 struct addr_table_entry {
260 __le32 lo;
261 __le32 hi;
262 };
263
264 /* Bit fields of a Hash Table Entry */
265 enum hash_table_entry {
266 HASH_ENTRY_VALID = 1,
267 SKIP = 2,
268 HASH_ENTRY_RECEIVE_DISCARD = 4,
269 HASH_ENTRY_RECEIVE_DISCARD_BIT = 2
270 };
271
272 static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd);
273 static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd);
274 static int pxa168_init_hw(struct pxa168_eth_private *pep);
275 static void eth_port_reset(struct net_device *dev);
276 static void eth_port_start(struct net_device *dev);
277 static int pxa168_eth_open(struct net_device *dev);
278 static int pxa168_eth_stop(struct net_device *dev);
279 static int ethernet_phy_setup(struct net_device *dev);
280
281 static inline u32 rdl(struct pxa168_eth_private *pep, int offset)
282 {
283 return readl(pep->base + offset);
284 }
285
286 static inline void wrl(struct pxa168_eth_private *pep, int offset, u32 data)
287 {
288 writel(data, pep->base + offset);
289 }
290
291 static void abort_dma(struct pxa168_eth_private *pep)
292 {
293 int delay;
294 int max_retries = 40;
295
296 do {
297 wrl(pep, SDMA_CMD, SDMA_CMD_AR | SDMA_CMD_AT);
298 udelay(100);
299
300 delay = 10;
301 while ((rdl(pep, SDMA_CMD) & (SDMA_CMD_AR | SDMA_CMD_AT))
302 && delay-- > 0) {
303 udelay(10);
304 }
305 } while (max_retries-- > 0 && delay <= 0);
306
307 if (max_retries <= 0)
308 netdev_err(pep->dev, "%s : DMA Stuck\n", __func__);
309 }
310
311 static int ethernet_phy_get(struct pxa168_eth_private *pep)
312 {
313 unsigned int reg_data;
314
315 reg_data = rdl(pep, PHY_ADDRESS);
316
317 return (reg_data >> (5 * pep->port_num)) & 0x1f;
318 }
319
320 static void ethernet_phy_set_addr(struct pxa168_eth_private *pep, int phy_addr)
321 {
322 u32 reg_data;
323 int addr_shift = 5 * pep->port_num;
324
325 reg_data = rdl(pep, PHY_ADDRESS);
326 reg_data &= ~(0x1f << addr_shift);
327 reg_data |= (phy_addr & 0x1f) << addr_shift;
328 wrl(pep, PHY_ADDRESS, reg_data);
329 }
330
331 static void rxq_refill(struct net_device *dev)
332 {
333 struct pxa168_eth_private *pep = netdev_priv(dev);
334 struct sk_buff *skb;
335 struct rx_desc *p_used_rx_desc;
336 int used_rx_desc;
337
338 while (pep->rx_desc_count < pep->rx_ring_size) {
339 int size;
340
341 skb = netdev_alloc_skb(dev, pep->skb_size);
342 if (!skb)
343 break;
344 if (SKB_DMA_REALIGN)
345 skb_reserve(skb, SKB_DMA_REALIGN);
346 pep->rx_desc_count++;
347 /* Get 'used' Rx descriptor */
348 used_rx_desc = pep->rx_used_desc_q;
349 p_used_rx_desc = &pep->p_rx_desc_area[used_rx_desc];
350 size = skb_end_pointer(skb) - skb->data;
351 p_used_rx_desc->buf_ptr = dma_map_single(NULL,
352 skb->data,
353 size,
354 DMA_FROM_DEVICE);
355 p_used_rx_desc->buf_size = size;
356 pep->rx_skb[used_rx_desc] = skb;
357
358 /* Return the descriptor to DMA ownership */
359 wmb();
360 p_used_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
361 wmb();
362
363 /* Move the used descriptor pointer to the next descriptor */
364 pep->rx_used_desc_q = (used_rx_desc + 1) % pep->rx_ring_size;
365
366 /* Any Rx return cancels the Rx resource error status */
367 pep->rx_resource_err = 0;
368
369 skb_reserve(skb, ETH_HW_IP_ALIGN);
370 }
371
372 /*
373 * If RX ring is empty of SKB, set a timer to try allocating
374 * again at a later time.
375 */
376 if (pep->rx_desc_count == 0) {
377 pep->timeout.expires = jiffies + (HZ / 10);
378 add_timer(&pep->timeout);
379 }
380 }
381
382 static inline void rxq_refill_timer_wrapper(unsigned long data)
383 {
384 struct pxa168_eth_private *pep = (void *)data;
385 napi_schedule(&pep->napi);
386 }
387
388 static inline u8 flip_8_bits(u8 x)
389 {
390 return (((x) & 0x01) << 3) | (((x) & 0x02) << 1)
391 | (((x) & 0x04) >> 1) | (((x) & 0x08) >> 3)
392 | (((x) & 0x10) << 3) | (((x) & 0x20) << 1)
393 | (((x) & 0x40) >> 1) | (((x) & 0x80) >> 3);
394 }
395
396 static void nibble_swap_every_byte(unsigned char *mac_addr)
397 {
398 int i;
399 for (i = 0; i < ETH_ALEN; i++) {
400 mac_addr[i] = ((mac_addr[i] & 0x0f) << 4) |
401 ((mac_addr[i] & 0xf0) >> 4);
402 }
403 }
404
405 static void inverse_every_nibble(unsigned char *mac_addr)
406 {
407 int i;
408 for (i = 0; i < ETH_ALEN; i++)
409 mac_addr[i] = flip_8_bits(mac_addr[i]);
410 }
411
412 /*
413 * ----------------------------------------------------------------------------
414 * This function will calculate the hash function of the address.
415 * Inputs
416 * mac_addr_orig - MAC address.
417 * Outputs
418 * return the calculated entry.
419 */
420 static u32 hash_function(unsigned char *mac_addr_orig)
421 {
422 u32 hash_result;
423 u32 addr0;
424 u32 addr1;
425 u32 addr2;
426 u32 addr3;
427 unsigned char mac_addr[ETH_ALEN];
428
429 /* Make a copy of MAC address since we are going to performe bit
430 * operations on it
431 */
432 memcpy(mac_addr, mac_addr_orig, ETH_ALEN);
433
434 nibble_swap_every_byte(mac_addr);
435 inverse_every_nibble(mac_addr);
436
437 addr0 = (mac_addr[5] >> 2) & 0x3f;
438 addr1 = (mac_addr[5] & 0x03) | (((mac_addr[4] & 0x7f)) << 2);
439 addr2 = ((mac_addr[4] & 0x80) >> 7) | mac_addr[3] << 1;
440 addr3 = (mac_addr[2] & 0xff) | ((mac_addr[1] & 1) << 8);
441
442 hash_result = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
443 hash_result = hash_result & 0x07ff;
444 return hash_result;
445 }
446
447 /*
448 * ----------------------------------------------------------------------------
449 * This function will add/del an entry to the address table.
450 * Inputs
451 * pep - ETHERNET .
452 * mac_addr - MAC address.
453 * skip - if 1, skip this address.Used in case of deleting an entry which is a
454 * part of chain in the hash table.We can't just delete the entry since
455 * that will break the chain.We need to defragment the tables time to
456 * time.
457 * rd - 0 Discard packet upon match.
458 * - 1 Receive packet upon match.
459 * Outputs
460 * address table entry is added/deleted.
461 * 0 if success.
462 * -ENOSPC if table full
463 */
464 static int add_del_hash_entry(struct pxa168_eth_private *pep,
465 unsigned char *mac_addr,
466 u32 rd, u32 skip, int del)
467 {
468 struct addr_table_entry *entry, *start;
469 u32 new_high;
470 u32 new_low;
471 u32 i;
472
473 new_low = (((mac_addr[1] >> 4) & 0xf) << 15)
474 | (((mac_addr[1] >> 0) & 0xf) << 11)
475 | (((mac_addr[0] >> 4) & 0xf) << 7)
476 | (((mac_addr[0] >> 0) & 0xf) << 3)
477 | (((mac_addr[3] >> 4) & 0x1) << 31)
478 | (((mac_addr[3] >> 0) & 0xf) << 27)
479 | (((mac_addr[2] >> 4) & 0xf) << 23)
480 | (((mac_addr[2] >> 0) & 0xf) << 19)
481 | (skip << SKIP) | (rd << HASH_ENTRY_RECEIVE_DISCARD_BIT)
482 | HASH_ENTRY_VALID;
483
484 new_high = (((mac_addr[5] >> 4) & 0xf) << 15)
485 | (((mac_addr[5] >> 0) & 0xf) << 11)
486 | (((mac_addr[4] >> 4) & 0xf) << 7)
487 | (((mac_addr[4] >> 0) & 0xf) << 3)
488 | (((mac_addr[3] >> 5) & 0x7) << 0);
489
490 /*
491 * Pick the appropriate table, start scanning for free/reusable
492 * entries at the index obtained by hashing the specified MAC address
493 */
494 start = pep->htpr;
495 entry = start + hash_function(mac_addr);
496 for (i = 0; i < HOP_NUMBER; i++) {
497 if (!(le32_to_cpu(entry->lo) & HASH_ENTRY_VALID)) {
498 break;
499 } else {
500 /* if same address put in same position */
501 if (((le32_to_cpu(entry->lo) & 0xfffffff8) ==
502 (new_low & 0xfffffff8)) &&
503 (le32_to_cpu(entry->hi) == new_high)) {
504 break;
505 }
506 }
507 if (entry == start + 0x7ff)
508 entry = start;
509 else
510 entry++;
511 }
512
513 if (((le32_to_cpu(entry->lo) & 0xfffffff8) != (new_low & 0xfffffff8)) &&
514 (le32_to_cpu(entry->hi) != new_high) && del)
515 return 0;
516
517 if (i == HOP_NUMBER) {
518 if (!del) {
519 netdev_info(pep->dev,
520 "%s: table section is full, need to "
521 "move to 16kB implementation?\n",
522 __FILE__);
523 return -ENOSPC;
524 } else
525 return 0;
526 }
527
528 /*
529 * Update the selected entry
530 */
531 if (del) {
532 entry->hi = 0;
533 entry->lo = 0;
534 } else {
535 entry->hi = cpu_to_le32(new_high);
536 entry->lo = cpu_to_le32(new_low);
537 }
538
539 return 0;
540 }
541
542 /*
543 * ----------------------------------------------------------------------------
544 * Create an addressTable entry from MAC address info
545 * found in the specifed net_device struct
546 *
547 * Input : pointer to ethernet interface network device structure
548 * Output : N/A
549 */
550 static void update_hash_table_mac_address(struct pxa168_eth_private *pep,
551 unsigned char *oaddr,
552 unsigned char *addr)
553 {
554 /* Delete old entry */
555 if (oaddr)
556 add_del_hash_entry(pep, oaddr, 1, 0, HASH_DELETE);
557 /* Add new entry */
558 add_del_hash_entry(pep, addr, 1, 0, HASH_ADD);
559 }
560
561 static int init_hash_table(struct pxa168_eth_private *pep)
562 {
563 /*
564 * Hardware expects CPU to build a hash table based on a predefined
565 * hash function and populate it based on hardware address. The
566 * location of the hash table is identified by 32-bit pointer stored
567 * in HTPR internal register. Two possible sizes exists for the hash
568 * table 8kB (256kB of DRAM required (4 x 64 kB banks)) and 1/2kB
569 * (16kB of DRAM required (4 x 4 kB banks)).We currently only support
570 * 1/2kB.
571 */
572 /* TODO: Add support for 8kB hash table and alternative hash
573 * function.Driver can dynamically switch to them if the 1/2kB hash
574 * table is full.
575 */
576 if (pep->htpr == NULL) {
577 pep->htpr = dma_zalloc_coherent(pep->dev->dev.parent,
578 HASH_ADDR_TABLE_SIZE,
579 &pep->htpr_dma, GFP_KERNEL);
580 if (pep->htpr == NULL)
581 return -ENOMEM;
582 } else {
583 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE);
584 }
585 wrl(pep, HTPR, pep->htpr_dma);
586 return 0;
587 }
588
589 static void pxa168_eth_set_rx_mode(struct net_device *dev)
590 {
591 struct pxa168_eth_private *pep = netdev_priv(dev);
592 struct netdev_hw_addr *ha;
593 u32 val;
594
595 val = rdl(pep, PORT_CONFIG);
596 if (dev->flags & IFF_PROMISC)
597 val |= PCR_PM;
598 else
599 val &= ~PCR_PM;
600 wrl(pep, PORT_CONFIG, val);
601
602 /*
603 * Remove the old list of MAC address and add dev->addr
604 * and multicast address.
605 */
606 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE);
607 update_hash_table_mac_address(pep, NULL, dev->dev_addr);
608
609 netdev_for_each_mc_addr(ha, dev)
610 update_hash_table_mac_address(pep, NULL, ha->addr);
611 }
612
613 static void pxa168_eth_get_mac_address(struct net_device *dev,
614 unsigned char *addr)
615 {
616 struct pxa168_eth_private *pep = netdev_priv(dev);
617 unsigned int mac_h = rdl(pep, MAC_ADDR_HIGH);
618 unsigned int mac_l = rdl(pep, MAC_ADDR_LOW);
619
620 addr[0] = (mac_h >> 24) & 0xff;
621 addr[1] = (mac_h >> 16) & 0xff;
622 addr[2] = (mac_h >> 8) & 0xff;
623 addr[3] = mac_h & 0xff;
624 addr[4] = (mac_l >> 8) & 0xff;
625 addr[5] = mac_l & 0xff;
626 }
627
628 static int pxa168_eth_set_mac_address(struct net_device *dev, void *addr)
629 {
630 struct sockaddr *sa = addr;
631 struct pxa168_eth_private *pep = netdev_priv(dev);
632 unsigned char oldMac[ETH_ALEN];
633 u32 mac_h, mac_l;
634
635 if (!is_valid_ether_addr(sa->sa_data))
636 return -EADDRNOTAVAIL;
637 memcpy(oldMac, dev->dev_addr, ETH_ALEN);
638 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
639
640 mac_h = dev->dev_addr[0] << 24;
641 mac_h |= dev->dev_addr[1] << 16;
642 mac_h |= dev->dev_addr[2] << 8;
643 mac_h |= dev->dev_addr[3];
644 mac_l = dev->dev_addr[4] << 8;
645 mac_l |= dev->dev_addr[5];
646 wrl(pep, MAC_ADDR_HIGH, mac_h);
647 wrl(pep, MAC_ADDR_LOW, mac_l);
648
649 netif_addr_lock_bh(dev);
650 update_hash_table_mac_address(pep, oldMac, dev->dev_addr);
651 netif_addr_unlock_bh(dev);
652 return 0;
653 }
654
655 static void eth_port_start(struct net_device *dev)
656 {
657 unsigned int val = 0;
658 struct pxa168_eth_private *pep = netdev_priv(dev);
659 int tx_curr_desc, rx_curr_desc;
660
661 /* Perform PHY reset, if there is a PHY. */
662 if (pep->phy != NULL) {
663 struct ethtool_cmd cmd;
664
665 pxa168_get_settings(pep->dev, &cmd);
666 phy_init_hw(pep->phy);
667 pxa168_set_settings(pep->dev, &cmd);
668 }
669
670 /* Assignment of Tx CTRP of given queue */
671 tx_curr_desc = pep->tx_curr_desc_q;
672 wrl(pep, ETH_C_TX_DESC_1,
673 (u32) (pep->tx_desc_dma + tx_curr_desc * sizeof(struct tx_desc)));
674
675 /* Assignment of Rx CRDP of given queue */
676 rx_curr_desc = pep->rx_curr_desc_q;
677 wrl(pep, ETH_C_RX_DESC_0,
678 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc)));
679
680 wrl(pep, ETH_F_RX_DESC_0,
681 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc)));
682
683 /* Clear all interrupts */
684 wrl(pep, INT_CAUSE, 0);
685
686 /* Enable all interrupts for receive, transmit and error. */
687 wrl(pep, INT_MASK, ALL_INTS);
688
689 val = rdl(pep, PORT_CONFIG);
690 val |= PCR_EN;
691 wrl(pep, PORT_CONFIG, val);
692
693 /* Start RX DMA engine */
694 val = rdl(pep, SDMA_CMD);
695 val |= SDMA_CMD_ERD;
696 wrl(pep, SDMA_CMD, val);
697 }
698
699 static void eth_port_reset(struct net_device *dev)
700 {
701 struct pxa168_eth_private *pep = netdev_priv(dev);
702 unsigned int val = 0;
703
704 /* Stop all interrupts for receive, transmit and error. */
705 wrl(pep, INT_MASK, 0);
706
707 /* Clear all interrupts */
708 wrl(pep, INT_CAUSE, 0);
709
710 /* Stop RX DMA */
711 val = rdl(pep, SDMA_CMD);
712 val &= ~SDMA_CMD_ERD; /* abort dma command */
713
714 /* Abort any transmit and receive operations and put DMA
715 * in idle state.
716 */
717 abort_dma(pep);
718
719 /* Disable port */
720 val = rdl(pep, PORT_CONFIG);
721 val &= ~PCR_EN;
722 wrl(pep, PORT_CONFIG, val);
723 }
724
725 /*
726 * txq_reclaim - Free the tx desc data for completed descriptors
727 * If force is non-zero, frees uncompleted descriptors as well
728 */
729 static int txq_reclaim(struct net_device *dev, int force)
730 {
731 struct pxa168_eth_private *pep = netdev_priv(dev);
732 struct tx_desc *desc;
733 u32 cmd_sts;
734 struct sk_buff *skb;
735 int tx_index;
736 dma_addr_t addr;
737 int count;
738 int released = 0;
739
740 netif_tx_lock(dev);
741
742 pep->work_todo &= ~WORK_TX_DONE;
743 while (pep->tx_desc_count > 0) {
744 tx_index = pep->tx_used_desc_q;
745 desc = &pep->p_tx_desc_area[tx_index];
746 cmd_sts = desc->cmd_sts;
747 if (!force && (cmd_sts & BUF_OWNED_BY_DMA)) {
748 if (released > 0) {
749 goto txq_reclaim_end;
750 } else {
751 released = -1;
752 goto txq_reclaim_end;
753 }
754 }
755 pep->tx_used_desc_q = (tx_index + 1) % pep->tx_ring_size;
756 pep->tx_desc_count--;
757 addr = desc->buf_ptr;
758 count = desc->byte_cnt;
759 skb = pep->tx_skb[tx_index];
760 if (skb)
761 pep->tx_skb[tx_index] = NULL;
762
763 if (cmd_sts & TX_ERROR) {
764 if (net_ratelimit())
765 netdev_err(dev, "Error in TX\n");
766 dev->stats.tx_errors++;
767 }
768 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
769 if (skb)
770 dev_kfree_skb_irq(skb);
771 released++;
772 }
773 txq_reclaim_end:
774 netif_tx_unlock(dev);
775 return released;
776 }
777
778 static void pxa168_eth_tx_timeout(struct net_device *dev)
779 {
780 struct pxa168_eth_private *pep = netdev_priv(dev);
781
782 netdev_info(dev, "TX timeout desc_count %d\n", pep->tx_desc_count);
783
784 schedule_work(&pep->tx_timeout_task);
785 }
786
787 static void pxa168_eth_tx_timeout_task(struct work_struct *work)
788 {
789 struct pxa168_eth_private *pep = container_of(work,
790 struct pxa168_eth_private,
791 tx_timeout_task);
792 struct net_device *dev = pep->dev;
793 pxa168_eth_stop(dev);
794 pxa168_eth_open(dev);
795 }
796
797 static int rxq_process(struct net_device *dev, int budget)
798 {
799 struct pxa168_eth_private *pep = netdev_priv(dev);
800 struct net_device_stats *stats = &dev->stats;
801 unsigned int received_packets = 0;
802 struct sk_buff *skb;
803
804 while (budget-- > 0) {
805 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
806 struct rx_desc *rx_desc;
807 unsigned int cmd_sts;
808
809 /* Do not process Rx ring in case of Rx ring resource error */
810 if (pep->rx_resource_err)
811 break;
812 rx_curr_desc = pep->rx_curr_desc_q;
813 rx_used_desc = pep->rx_used_desc_q;
814 rx_desc = &pep->p_rx_desc_area[rx_curr_desc];
815 cmd_sts = rx_desc->cmd_sts;
816 rmb();
817 if (cmd_sts & (BUF_OWNED_BY_DMA))
818 break;
819 skb = pep->rx_skb[rx_curr_desc];
820 pep->rx_skb[rx_curr_desc] = NULL;
821
822 rx_next_curr_desc = (rx_curr_desc + 1) % pep->rx_ring_size;
823 pep->rx_curr_desc_q = rx_next_curr_desc;
824
825 /* Rx descriptors exhausted. */
826 /* Set the Rx ring resource error flag */
827 if (rx_next_curr_desc == rx_used_desc)
828 pep->rx_resource_err = 1;
829 pep->rx_desc_count--;
830 dma_unmap_single(NULL, rx_desc->buf_ptr,
831 rx_desc->buf_size,
832 DMA_FROM_DEVICE);
833 received_packets++;
834 /*
835 * Update statistics.
836 * Note byte count includes 4 byte CRC count
837 */
838 stats->rx_packets++;
839 stats->rx_bytes += rx_desc->byte_cnt;
840 /*
841 * In case received a packet without first / last bits on OR
842 * the error summary bit is on, the packets needs to be droped.
843 */
844 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
845 (RX_FIRST_DESC | RX_LAST_DESC))
846 || (cmd_sts & RX_ERROR)) {
847
848 stats->rx_dropped++;
849 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
850 (RX_FIRST_DESC | RX_LAST_DESC)) {
851 if (net_ratelimit())
852 netdev_err(dev,
853 "Rx pkt on multiple desc\n");
854 }
855 if (cmd_sts & RX_ERROR)
856 stats->rx_errors++;
857 dev_kfree_skb_irq(skb);
858 } else {
859 /*
860 * The -4 is for the CRC in the trailer of the
861 * received packet
862 */
863 skb_put(skb, rx_desc->byte_cnt - 4);
864 skb->protocol = eth_type_trans(skb, dev);
865 netif_receive_skb(skb);
866 }
867 }
868 /* Fill RX ring with skb's */
869 rxq_refill(dev);
870 return received_packets;
871 }
872
873 static int pxa168_eth_collect_events(struct pxa168_eth_private *pep,
874 struct net_device *dev)
875 {
876 u32 icr;
877 int ret = 0;
878
879 icr = rdl(pep, INT_CAUSE);
880 if (icr == 0)
881 return IRQ_NONE;
882
883 wrl(pep, INT_CAUSE, ~icr);
884 if (icr & (ICR_TXBUF_H | ICR_TXBUF_L)) {
885 pep->work_todo |= WORK_TX_DONE;
886 ret = 1;
887 }
888 if (icr & ICR_RXBUF)
889 ret = 1;
890 if (icr & ICR_MII_CH) {
891 pep->work_todo |= WORK_LINK;
892 ret = 1;
893 }
894 return ret;
895 }
896
897 static void handle_link_event(struct pxa168_eth_private *pep)
898 {
899 struct net_device *dev = pep->dev;
900 u32 port_status;
901 int speed;
902 int duplex;
903 int fc;
904
905 port_status = rdl(pep, PORT_STATUS);
906 if (!(port_status & LINK_UP)) {
907 if (netif_carrier_ok(dev)) {
908 netdev_info(dev, "link down\n");
909 netif_carrier_off(dev);
910 txq_reclaim(dev, 1);
911 }
912 return;
913 }
914 if (port_status & PORT_SPEED_100)
915 speed = 100;
916 else
917 speed = 10;
918
919 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
920 fc = (port_status & FLOW_CONTROL_DISABLED) ? 0 : 1;
921 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
922 speed, duplex ? "full" : "half", fc ? "en" : "dis");
923 if (!netif_carrier_ok(dev))
924 netif_carrier_on(dev);
925 }
926
927 static irqreturn_t pxa168_eth_int_handler(int irq, void *dev_id)
928 {
929 struct net_device *dev = (struct net_device *)dev_id;
930 struct pxa168_eth_private *pep = netdev_priv(dev);
931
932 if (unlikely(!pxa168_eth_collect_events(pep, dev)))
933 return IRQ_NONE;
934 /* Disable interrupts */
935 wrl(pep, INT_MASK, 0);
936 napi_schedule(&pep->napi);
937 return IRQ_HANDLED;
938 }
939
940 static void pxa168_eth_recalc_skb_size(struct pxa168_eth_private *pep)
941 {
942 int skb_size;
943
944 /*
945 * Reserve 2+14 bytes for an ethernet header (the hardware
946 * automatically prepends 2 bytes of dummy data to each
947 * received packet), 16 bytes for up to four VLAN tags, and
948 * 4 bytes for the trailing FCS -- 36 bytes total.
949 */
950 skb_size = pep->dev->mtu + 36;
951
952 /*
953 * Make sure that the skb size is a multiple of 8 bytes, as
954 * the lower three bits of the receive descriptor's buffer
955 * size field are ignored by the hardware.
956 */
957 pep->skb_size = (skb_size + 7) & ~7;
958
959 /*
960 * If NET_SKB_PAD is smaller than a cache line,
961 * netdev_alloc_skb() will cause skb->data to be misaligned
962 * to a cache line boundary. If this is the case, include
963 * some extra space to allow re-aligning the data area.
964 */
965 pep->skb_size += SKB_DMA_REALIGN;
966
967 }
968
969 static int set_port_config_ext(struct pxa168_eth_private *pep)
970 {
971 int skb_size;
972
973 pxa168_eth_recalc_skb_size(pep);
974 if (pep->skb_size <= 1518)
975 skb_size = PCXR_MFL_1518;
976 else if (pep->skb_size <= 1536)
977 skb_size = PCXR_MFL_1536;
978 else if (pep->skb_size <= 2048)
979 skb_size = PCXR_MFL_2048;
980 else
981 skb_size = PCXR_MFL_64K;
982
983 /* Extended Port Configuration */
984 wrl(pep,
985 PORT_CONFIG_EXT, PCXR_2BSM | /* Two byte prefix aligns IP hdr */
986 PCXR_DSCP_EN | /* Enable DSCP in IP */
987 skb_size | PCXR_FLP | /* do not force link pass */
988 PCXR_TX_HIGH_PRI); /* Transmit - high priority queue */
989
990 return 0;
991 }
992
993 static int pxa168_init_hw(struct pxa168_eth_private *pep)
994 {
995 int err = 0;
996
997 /* Disable interrupts */
998 wrl(pep, INT_MASK, 0);
999 wrl(pep, INT_CAUSE, 0);
1000 /* Write to ICR to clear interrupts. */
1001 wrl(pep, INT_W_CLEAR, 0);
1002 /* Abort any transmit and receive operations and put DMA
1003 * in idle state.
1004 */
1005 abort_dma(pep);
1006 /* Initialize address hash table */
1007 err = init_hash_table(pep);
1008 if (err)
1009 return err;
1010 /* SDMA configuration */
1011 wrl(pep, SDMA_CONFIG, SDCR_BSZ8 | /* Burst size = 32 bytes */
1012 SDCR_RIFB | /* Rx interrupt on frame */
1013 SDCR_BLMT | /* Little endian transmit */
1014 SDCR_BLMR | /* Little endian receive */
1015 SDCR_RC_MAX_RETRANS); /* Max retransmit count */
1016 /* Port Configuration */
1017 wrl(pep, PORT_CONFIG, PCR_HS); /* Hash size is 1/2kb */
1018 set_port_config_ext(pep);
1019
1020 return err;
1021 }
1022
1023 static int rxq_init(struct net_device *dev)
1024 {
1025 struct pxa168_eth_private *pep = netdev_priv(dev);
1026 struct rx_desc *p_rx_desc;
1027 int size = 0, i = 0;
1028 int rx_desc_num = pep->rx_ring_size;
1029
1030 /* Allocate RX skb rings */
1031 pep->rx_skb = kzalloc(sizeof(*pep->rx_skb) * pep->rx_ring_size,
1032 GFP_KERNEL);
1033 if (!pep->rx_skb)
1034 return -ENOMEM;
1035
1036 /* Allocate RX ring */
1037 pep->rx_desc_count = 0;
1038 size = pep->rx_ring_size * sizeof(struct rx_desc);
1039 pep->rx_desc_area_size = size;
1040 pep->p_rx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size,
1041 &pep->rx_desc_dma,
1042 GFP_KERNEL);
1043 if (!pep->p_rx_desc_area)
1044 goto out;
1045
1046 /* initialize the next_desc_ptr links in the Rx descriptors ring */
1047 p_rx_desc = pep->p_rx_desc_area;
1048 for (i = 0; i < rx_desc_num; i++) {
1049 p_rx_desc[i].next_desc_ptr = pep->rx_desc_dma +
1050 ((i + 1) % rx_desc_num) * sizeof(struct rx_desc);
1051 }
1052 /* Save Rx desc pointer to driver struct. */
1053 pep->rx_curr_desc_q = 0;
1054 pep->rx_used_desc_q = 0;
1055 pep->rx_desc_area_size = rx_desc_num * sizeof(struct rx_desc);
1056 return 0;
1057 out:
1058 kfree(pep->rx_skb);
1059 return -ENOMEM;
1060 }
1061
1062 static void rxq_deinit(struct net_device *dev)
1063 {
1064 struct pxa168_eth_private *pep = netdev_priv(dev);
1065 int curr;
1066
1067 /* Free preallocated skb's on RX rings */
1068 for (curr = 0; pep->rx_desc_count && curr < pep->rx_ring_size; curr++) {
1069 if (pep->rx_skb[curr]) {
1070 dev_kfree_skb(pep->rx_skb[curr]);
1071 pep->rx_desc_count--;
1072 }
1073 }
1074 if (pep->rx_desc_count)
1075 netdev_err(dev, "Error in freeing Rx Ring. %d skb's still\n",
1076 pep->rx_desc_count);
1077 /* Free RX ring */
1078 if (pep->p_rx_desc_area)
1079 dma_free_coherent(pep->dev->dev.parent, pep->rx_desc_area_size,
1080 pep->p_rx_desc_area, pep->rx_desc_dma);
1081 kfree(pep->rx_skb);
1082 }
1083
1084 static int txq_init(struct net_device *dev)
1085 {
1086 struct pxa168_eth_private *pep = netdev_priv(dev);
1087 struct tx_desc *p_tx_desc;
1088 int size = 0, i = 0;
1089 int tx_desc_num = pep->tx_ring_size;
1090
1091 pep->tx_skb = kzalloc(sizeof(*pep->tx_skb) * pep->tx_ring_size,
1092 GFP_KERNEL);
1093 if (!pep->tx_skb)
1094 return -ENOMEM;
1095
1096 /* Allocate TX ring */
1097 pep->tx_desc_count = 0;
1098 size = pep->tx_ring_size * sizeof(struct tx_desc);
1099 pep->tx_desc_area_size = size;
1100 pep->p_tx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size,
1101 &pep->tx_desc_dma,
1102 GFP_KERNEL);
1103 if (!pep->p_tx_desc_area)
1104 goto out;
1105 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
1106 p_tx_desc = pep->p_tx_desc_area;
1107 for (i = 0; i < tx_desc_num; i++) {
1108 p_tx_desc[i].next_desc_ptr = pep->tx_desc_dma +
1109 ((i + 1) % tx_desc_num) * sizeof(struct tx_desc);
1110 }
1111 pep->tx_curr_desc_q = 0;
1112 pep->tx_used_desc_q = 0;
1113 pep->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc);
1114 return 0;
1115 out:
1116 kfree(pep->tx_skb);
1117 return -ENOMEM;
1118 }
1119
1120 static void txq_deinit(struct net_device *dev)
1121 {
1122 struct pxa168_eth_private *pep = netdev_priv(dev);
1123
1124 /* Free outstanding skb's on TX ring */
1125 txq_reclaim(dev, 1);
1126 BUG_ON(pep->tx_used_desc_q != pep->tx_curr_desc_q);
1127 /* Free TX ring */
1128 if (pep->p_tx_desc_area)
1129 dma_free_coherent(pep->dev->dev.parent, pep->tx_desc_area_size,
1130 pep->p_tx_desc_area, pep->tx_desc_dma);
1131 kfree(pep->tx_skb);
1132 }
1133
1134 static int pxa168_eth_open(struct net_device *dev)
1135 {
1136 struct pxa168_eth_private *pep = netdev_priv(dev);
1137 int err;
1138
1139 err = request_irq(dev->irq, pxa168_eth_int_handler, 0, dev->name, dev);
1140 if (err) {
1141 dev_err(&dev->dev, "can't assign irq\n");
1142 return -EAGAIN;
1143 }
1144 pep->rx_resource_err = 0;
1145 err = rxq_init(dev);
1146 if (err != 0)
1147 goto out_free_irq;
1148 err = txq_init(dev);
1149 if (err != 0)
1150 goto out_free_rx_skb;
1151 pep->rx_used_desc_q = 0;
1152 pep->rx_curr_desc_q = 0;
1153
1154 /* Fill RX ring with skb's */
1155 rxq_refill(dev);
1156 pep->rx_used_desc_q = 0;
1157 pep->rx_curr_desc_q = 0;
1158 netif_carrier_off(dev);
1159 eth_port_start(dev);
1160 napi_enable(&pep->napi);
1161 return 0;
1162 out_free_rx_skb:
1163 rxq_deinit(dev);
1164 out_free_irq:
1165 free_irq(dev->irq, dev);
1166 return err;
1167 }
1168
1169 static int pxa168_eth_stop(struct net_device *dev)
1170 {
1171 struct pxa168_eth_private *pep = netdev_priv(dev);
1172 eth_port_reset(dev);
1173
1174 /* Disable interrupts */
1175 wrl(pep, INT_MASK, 0);
1176 wrl(pep, INT_CAUSE, 0);
1177 /* Write to ICR to clear interrupts. */
1178 wrl(pep, INT_W_CLEAR, 0);
1179 napi_disable(&pep->napi);
1180 del_timer_sync(&pep->timeout);
1181 netif_carrier_off(dev);
1182 free_irq(dev->irq, dev);
1183 rxq_deinit(dev);
1184 txq_deinit(dev);
1185
1186 return 0;
1187 }
1188
1189 static int pxa168_eth_change_mtu(struct net_device *dev, int mtu)
1190 {
1191 int retval;
1192 struct pxa168_eth_private *pep = netdev_priv(dev);
1193
1194 if ((mtu > 9500) || (mtu < 68))
1195 return -EINVAL;
1196
1197 dev->mtu = mtu;
1198 retval = set_port_config_ext(pep);
1199
1200 if (!netif_running(dev))
1201 return 0;
1202
1203 /*
1204 * Stop and then re-open the interface. This will allocate RX
1205 * skbs of the new MTU.
1206 * There is a possible danger that the open will not succeed,
1207 * due to memory being full.
1208 */
1209 pxa168_eth_stop(dev);
1210 if (pxa168_eth_open(dev)) {
1211 dev_err(&dev->dev,
1212 "fatal error on re-opening device after MTU change\n");
1213 }
1214
1215 return 0;
1216 }
1217
1218 static int eth_alloc_tx_desc_index(struct pxa168_eth_private *pep)
1219 {
1220 int tx_desc_curr;
1221
1222 tx_desc_curr = pep->tx_curr_desc_q;
1223 pep->tx_curr_desc_q = (tx_desc_curr + 1) % pep->tx_ring_size;
1224 BUG_ON(pep->tx_curr_desc_q == pep->tx_used_desc_q);
1225 pep->tx_desc_count++;
1226
1227 return tx_desc_curr;
1228 }
1229
1230 static int pxa168_rx_poll(struct napi_struct *napi, int budget)
1231 {
1232 struct pxa168_eth_private *pep =
1233 container_of(napi, struct pxa168_eth_private, napi);
1234 struct net_device *dev = pep->dev;
1235 int work_done = 0;
1236
1237 if (unlikely(pep->work_todo & WORK_LINK)) {
1238 pep->work_todo &= ~(WORK_LINK);
1239 handle_link_event(pep);
1240 }
1241 /*
1242 * We call txq_reclaim every time since in NAPI interupts are disabled
1243 * and due to this we miss the TX_DONE interrupt,which is not updated in
1244 * interrupt status register.
1245 */
1246 txq_reclaim(dev, 0);
1247 if (netif_queue_stopped(dev)
1248 && pep->tx_ring_size - pep->tx_desc_count > 1) {
1249 netif_wake_queue(dev);
1250 }
1251 work_done = rxq_process(dev, budget);
1252 if (work_done < budget) {
1253 napi_complete(napi);
1254 wrl(pep, INT_MASK, ALL_INTS);
1255 }
1256
1257 return work_done;
1258 }
1259
1260 static int pxa168_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1261 {
1262 struct pxa168_eth_private *pep = netdev_priv(dev);
1263 struct net_device_stats *stats = &dev->stats;
1264 struct tx_desc *desc;
1265 int tx_index;
1266 int length;
1267
1268 tx_index = eth_alloc_tx_desc_index(pep);
1269 desc = &pep->p_tx_desc_area[tx_index];
1270 length = skb->len;
1271 pep->tx_skb[tx_index] = skb;
1272 desc->byte_cnt = length;
1273 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1274
1275 skb_tx_timestamp(skb);
1276
1277 wmb();
1278 desc->cmd_sts = BUF_OWNED_BY_DMA | TX_GEN_CRC | TX_FIRST_DESC |
1279 TX_ZERO_PADDING | TX_LAST_DESC | TX_EN_INT;
1280 wmb();
1281 wrl(pep, SDMA_CMD, SDMA_CMD_TXDH | SDMA_CMD_ERD);
1282
1283 stats->tx_bytes += length;
1284 stats->tx_packets++;
1285 dev->trans_start = jiffies;
1286 if (pep->tx_ring_size - pep->tx_desc_count <= 1) {
1287 /* We handled the current skb, but now we are out of space.*/
1288 netif_stop_queue(dev);
1289 }
1290
1291 return NETDEV_TX_OK;
1292 }
1293
1294 static int smi_wait_ready(struct pxa168_eth_private *pep)
1295 {
1296 int i = 0;
1297
1298 /* wait for the SMI register to become available */
1299 for (i = 0; rdl(pep, SMI) & SMI_BUSY; i++) {
1300 if (i == PHY_WAIT_ITERATIONS)
1301 return -ETIMEDOUT;
1302 msleep(10);
1303 }
1304
1305 return 0;
1306 }
1307
1308 static int pxa168_smi_read(struct mii_bus *bus, int phy_addr, int regnum)
1309 {
1310 struct pxa168_eth_private *pep = bus->priv;
1311 int i = 0;
1312 int val;
1313
1314 if (smi_wait_ready(pep)) {
1315 netdev_warn(pep->dev, "pxa168_eth: SMI bus busy timeout\n");
1316 return -ETIMEDOUT;
1317 }
1318 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R);
1319 /* now wait for the data to be valid */
1320 for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) {
1321 if (i == PHY_WAIT_ITERATIONS) {
1322 netdev_warn(pep->dev,
1323 "pxa168_eth: SMI bus read not valid\n");
1324 return -ENODEV;
1325 }
1326 msleep(10);
1327 }
1328
1329 return val & 0xffff;
1330 }
1331
1332 static int pxa168_smi_write(struct mii_bus *bus, int phy_addr, int regnum,
1333 u16 value)
1334 {
1335 struct pxa168_eth_private *pep = bus->priv;
1336
1337 if (smi_wait_ready(pep)) {
1338 netdev_warn(pep->dev, "pxa168_eth: SMI bus busy timeout\n");
1339 return -ETIMEDOUT;
1340 }
1341
1342 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) |
1343 SMI_OP_W | (value & 0xffff));
1344
1345 if (smi_wait_ready(pep)) {
1346 netdev_err(pep->dev, "pxa168_eth: SMI bus busy timeout\n");
1347 return -ETIMEDOUT;
1348 }
1349
1350 return 0;
1351 }
1352
1353 static int pxa168_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr,
1354 int cmd)
1355 {
1356 struct pxa168_eth_private *pep = netdev_priv(dev);
1357 if (pep->phy != NULL)
1358 return phy_mii_ioctl(pep->phy, ifr, cmd);
1359
1360 return -EOPNOTSUPP;
1361 }
1362
1363 static struct phy_device *phy_scan(struct pxa168_eth_private *pep, int phy_addr)
1364 {
1365 struct mii_bus *bus = pep->smi_bus;
1366 struct phy_device *phydev;
1367 int start;
1368 int num;
1369 int i;
1370
1371 if (phy_addr == PXA168_ETH_PHY_ADDR_DEFAULT) {
1372 /* Scan entire range */
1373 start = ethernet_phy_get(pep);
1374 num = 32;
1375 } else {
1376 /* Use phy addr specific to platform */
1377 start = phy_addr & 0x1f;
1378 num = 1;
1379 }
1380 phydev = NULL;
1381 for (i = 0; i < num; i++) {
1382 int addr = (start + i) & 0x1f;
1383 if (bus->phy_map[addr] == NULL)
1384 mdiobus_scan(bus, addr);
1385
1386 if (phydev == NULL) {
1387 phydev = bus->phy_map[addr];
1388 if (phydev != NULL)
1389 ethernet_phy_set_addr(pep, addr);
1390 }
1391 }
1392
1393 return phydev;
1394 }
1395
1396 static void phy_init(struct pxa168_eth_private *pep)
1397 {
1398 struct phy_device *phy = pep->phy;
1399
1400 phy_attach(pep->dev, dev_name(&phy->dev), pep->phy_intf);
1401
1402 phy->speed = pep->phy_speed;
1403 phy->duplex = pep->phy_duplex;
1404 phy->autoneg = AUTONEG_ENABLE;
1405 phy->supported &= PHY_BASIC_FEATURES;
1406 phy->advertising = phy->supported | ADVERTISED_Autoneg;
1407
1408 if (pep->phy_speed != 0) {
1409 phy->autoneg = AUTONEG_DISABLE;
1410 phy->advertising = 0;
1411 }
1412
1413 phy_start_aneg(phy);
1414 }
1415
1416 static int ethernet_phy_setup(struct net_device *dev)
1417 {
1418 struct pxa168_eth_private *pep = netdev_priv(dev);
1419
1420 pep->phy = phy_scan(pep, pep->phy_addr & 0x1f);
1421 if (pep->phy != NULL)
1422 phy_init(pep);
1423
1424 update_hash_table_mac_address(pep, NULL, dev->dev_addr);
1425
1426 return 0;
1427 }
1428
1429 static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1430 {
1431 struct pxa168_eth_private *pep = netdev_priv(dev);
1432 int err;
1433
1434 err = phy_read_status(pep->phy);
1435 if (err == 0)
1436 err = phy_ethtool_gset(pep->phy, cmd);
1437
1438 return err;
1439 }
1440
1441 static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1442 {
1443 struct pxa168_eth_private *pep = netdev_priv(dev);
1444
1445 return phy_ethtool_sset(pep->phy, cmd);
1446 }
1447
1448 static void pxa168_get_drvinfo(struct net_device *dev,
1449 struct ethtool_drvinfo *info)
1450 {
1451 strlcpy(info->driver, DRIVER_NAME, sizeof(info->driver));
1452 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
1453 strlcpy(info->fw_version, "N/A", sizeof(info->fw_version));
1454 strlcpy(info->bus_info, "N/A", sizeof(info->bus_info));
1455 }
1456
1457 static const struct ethtool_ops pxa168_ethtool_ops = {
1458 .get_settings = pxa168_get_settings,
1459 .set_settings = pxa168_set_settings,
1460 .get_drvinfo = pxa168_get_drvinfo,
1461 .get_link = ethtool_op_get_link,
1462 .get_ts_info = ethtool_op_get_ts_info,
1463 };
1464
1465 static const struct net_device_ops pxa168_eth_netdev_ops = {
1466 .ndo_open = pxa168_eth_open,
1467 .ndo_stop = pxa168_eth_stop,
1468 .ndo_start_xmit = pxa168_eth_start_xmit,
1469 .ndo_set_rx_mode = pxa168_eth_set_rx_mode,
1470 .ndo_set_mac_address = pxa168_eth_set_mac_address,
1471 .ndo_validate_addr = eth_validate_addr,
1472 .ndo_do_ioctl = pxa168_eth_do_ioctl,
1473 .ndo_change_mtu = pxa168_eth_change_mtu,
1474 .ndo_tx_timeout = pxa168_eth_tx_timeout,
1475 };
1476
1477 static int pxa168_eth_probe(struct platform_device *pdev)
1478 {
1479 struct pxa168_eth_private *pep = NULL;
1480 struct net_device *dev = NULL;
1481 struct resource *res;
1482 struct clk *clk;
1483 struct device_node *np;
1484 const unsigned char *mac_addr = NULL;
1485 int err;
1486
1487 printk(KERN_NOTICE "PXA168 10/100 Ethernet Driver\n");
1488
1489 clk = devm_clk_get(&pdev->dev, NULL);
1490 if (IS_ERR(clk)) {
1491 dev_err(&pdev->dev, "Fast Ethernet failed to get clock\n");
1492 return -ENODEV;
1493 }
1494 clk_prepare_enable(clk);
1495
1496 dev = alloc_etherdev(sizeof(struct pxa168_eth_private));
1497 if (!dev) {
1498 err = -ENOMEM;
1499 goto err_clk;
1500 }
1501
1502 platform_set_drvdata(pdev, dev);
1503 pep = netdev_priv(dev);
1504 pep->dev = dev;
1505 pep->clk = clk;
1506 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1507 if (res == NULL) {
1508 err = -ENODEV;
1509 goto err_netdev;
1510 }
1511 pep->base = devm_ioremap_resource(&pdev->dev, res);
1512 if (IS_ERR(pep->base)) {
1513 err = -ENOMEM;
1514 goto err_netdev;
1515 }
1516 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1517 BUG_ON(!res);
1518 dev->irq = res->start;
1519 dev->netdev_ops = &pxa168_eth_netdev_ops;
1520 dev->watchdog_timeo = 2 * HZ;
1521 dev->base_addr = 0;
1522 dev->ethtool_ops = &pxa168_ethtool_ops;
1523
1524 INIT_WORK(&pep->tx_timeout_task, pxa168_eth_tx_timeout_task);
1525
1526 if (pdev->dev.of_node)
1527 mac_addr = of_get_mac_address(pdev->dev.of_node);
1528
1529 if (mac_addr && is_valid_ether_addr(mac_addr)) {
1530 ether_addr_copy(dev->dev_addr, mac_addr);
1531 } else {
1532 /* try reading the mac address, if set by the bootloader */
1533 pxa168_eth_get_mac_address(dev, dev->dev_addr);
1534 if (!is_valid_ether_addr(dev->dev_addr)) {
1535 dev_info(&pdev->dev, "Using random mac address\n");
1536 eth_hw_addr_random(dev);
1537 }
1538 }
1539
1540 pep->rx_ring_size = NUM_RX_DESCS;
1541 pep->tx_ring_size = NUM_TX_DESCS;
1542
1543 pep->pd = dev_get_platdata(&pdev->dev);
1544 if (pep->pd) {
1545 if (pep->pd->rx_queue_size)
1546 pep->rx_ring_size = pep->pd->rx_queue_size;
1547
1548 if (pep->pd->tx_queue_size)
1549 pep->tx_ring_size = pep->pd->tx_queue_size;
1550
1551 pep->port_num = pep->pd->port_number;
1552 pep->phy_addr = pep->pd->phy_addr;
1553 pep->phy_speed = pep->pd->speed;
1554 pep->phy_duplex = pep->pd->duplex;
1555 pep->phy_intf = pep->pd->intf;
1556
1557 if (pep->pd->init)
1558 pep->pd->init();
1559 } else if (pdev->dev.of_node) {
1560 of_property_read_u32(pdev->dev.of_node, "port-id",
1561 &pep->port_num);
1562
1563 np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1564 if (!np) {
1565 dev_err(&pdev->dev, "missing phy-handle\n");
1566 return -EINVAL;
1567 }
1568 of_property_read_u32(np, "reg", &pep->phy_addr);
1569 pep->phy_intf = of_get_phy_mode(pdev->dev.of_node);
1570 }
1571
1572 /* Hardware supports only 3 ports */
1573 BUG_ON(pep->port_num > 2);
1574 netif_napi_add(dev, &pep->napi, pxa168_rx_poll, pep->rx_ring_size);
1575
1576 memset(&pep->timeout, 0, sizeof(struct timer_list));
1577 init_timer(&pep->timeout);
1578 pep->timeout.function = rxq_refill_timer_wrapper;
1579 pep->timeout.data = (unsigned long)pep;
1580
1581 pep->smi_bus = mdiobus_alloc();
1582 if (pep->smi_bus == NULL) {
1583 err = -ENOMEM;
1584 goto err_base;
1585 }
1586 pep->smi_bus->priv = pep;
1587 pep->smi_bus->name = "pxa168_eth smi";
1588 pep->smi_bus->read = pxa168_smi_read;
1589 pep->smi_bus->write = pxa168_smi_write;
1590 snprintf(pep->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1591 pdev->name, pdev->id);
1592 pep->smi_bus->parent = &pdev->dev;
1593 pep->smi_bus->phy_mask = 0xffffffff;
1594 err = mdiobus_register(pep->smi_bus);
1595 if (err)
1596 goto err_free_mdio;
1597
1598 pxa168_init_hw(pep);
1599 err = ethernet_phy_setup(dev);
1600 if (err)
1601 goto err_mdiobus;
1602 SET_NETDEV_DEV(dev, &pdev->dev);
1603 err = register_netdev(dev);
1604 if (err)
1605 goto err_mdiobus;
1606 return 0;
1607
1608 err_mdiobus:
1609 mdiobus_unregister(pep->smi_bus);
1610 err_free_mdio:
1611 mdiobus_free(pep->smi_bus);
1612 err_base:
1613 iounmap(pep->base);
1614 err_netdev:
1615 free_netdev(dev);
1616 err_clk:
1617 clk_disable(clk);
1618 clk_put(clk);
1619 return err;
1620 }
1621
1622 static int pxa168_eth_remove(struct platform_device *pdev)
1623 {
1624 struct net_device *dev = platform_get_drvdata(pdev);
1625 struct pxa168_eth_private *pep = netdev_priv(dev);
1626
1627 if (pep->htpr) {
1628 dma_free_coherent(pep->dev->dev.parent, HASH_ADDR_TABLE_SIZE,
1629 pep->htpr, pep->htpr_dma);
1630 pep->htpr = NULL;
1631 }
1632 if (pep->clk) {
1633 clk_disable(pep->clk);
1634 clk_put(pep->clk);
1635 pep->clk = NULL;
1636 }
1637 if (pep->phy != NULL)
1638 phy_detach(pep->phy);
1639
1640 iounmap(pep->base);
1641 pep->base = NULL;
1642 mdiobus_unregister(pep->smi_bus);
1643 mdiobus_free(pep->smi_bus);
1644 unregister_netdev(dev);
1645 cancel_work_sync(&pep->tx_timeout_task);
1646 free_netdev(dev);
1647 return 0;
1648 }
1649
1650 static void pxa168_eth_shutdown(struct platform_device *pdev)
1651 {
1652 struct net_device *dev = platform_get_drvdata(pdev);
1653 eth_port_reset(dev);
1654 }
1655
1656 #ifdef CONFIG_PM
1657 static int pxa168_eth_resume(struct platform_device *pdev)
1658 {
1659 return -ENOSYS;
1660 }
1661
1662 static int pxa168_eth_suspend(struct platform_device *pdev, pm_message_t state)
1663 {
1664 return -ENOSYS;
1665 }
1666
1667 #else
1668 #define pxa168_eth_resume NULL
1669 #define pxa168_eth_suspend NULL
1670 #endif
1671
1672 static const struct of_device_id pxa168_eth_of_match[] = {
1673 { .compatible = "marvell,pxa168-eth" },
1674 { },
1675 };
1676 MODULE_DEVICE_TABLE(of, pxa168_eth_of_match);
1677
1678 static struct platform_driver pxa168_eth_driver = {
1679 .probe = pxa168_eth_probe,
1680 .remove = pxa168_eth_remove,
1681 .shutdown = pxa168_eth_shutdown,
1682 .resume = pxa168_eth_resume,
1683 .suspend = pxa168_eth_suspend,
1684 .driver = {
1685 .name = DRIVER_NAME,
1686 .of_match_table = of_match_ptr(pxa168_eth_of_match),
1687 },
1688 };
1689
1690 module_platform_driver(pxa168_eth_driver);
1691
1692 MODULE_LICENSE("GPL");
1693 MODULE_DESCRIPTION("Ethernet driver for Marvell PXA168");
1694 MODULE_ALIAS("platform:pxa168_eth");
Linux kernel - Deliverables
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