2 * PXA168 ethernet driver.
3 * Most of the code is derived from mv643xx ethernet driver.
5 * Copyright (C) 2010 Marvell International Ltd.
6 * Sachin Sanap <ssanap@marvell.com>
7 * Zhangfei Gao <zgao6@marvell.com>
8 * Philip Rakity <prakity@marvell.com>
9 * Mark Brown <markb@marvell.com>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version 2
14 * of the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 #include <linux/init.h>
27 #include <linux/dma-mapping.h>
30 #include <linux/tcp.h>
31 #include <linux/udp.h>
32 #include <linux/etherdevice.h>
33 #include <linux/bitops.h>
34 #include <linux/delay.h>
35 #include <linux/ethtool.h>
36 #include <linux/platform_device.h>
37 #include <linux/module.h>
38 #include <linux/kernel.h>
39 #include <linux/workqueue.h>
40 #include <linux/clk.h>
41 #include <linux/phy.h>
43 #include <linux/interrupt.h>
44 #include <linux/types.h>
45 #include <asm/pgtable.h>
46 #include <asm/system.h>
47 #include <asm/cacheflush.h>
48 #include <linux/pxa168_eth.h>
50 #define DRIVER_NAME "pxa168-eth"
51 #define DRIVER_VERSION "0.3"
57 #define PHY_ADDRESS 0x0000
59 #define PORT_CONFIG 0x0400
60 #define PORT_CONFIG_EXT 0x0408
61 #define PORT_COMMAND 0x0410
62 #define PORT_STATUS 0x0418
64 #define SDMA_CONFIG 0x0440
65 #define SDMA_CMD 0x0448
66 #define INT_CAUSE 0x0450
67 #define INT_W_CLEAR 0x0454
68 #define INT_MASK 0x0458
69 #define ETH_F_RX_DESC_0 0x0480
70 #define ETH_C_RX_DESC_0 0x04A0
71 #define ETH_C_TX_DESC_1 0x04E4
74 #define SMI_BUSY (1 << 28) /* 0 - Write, 1 - Read */
75 #define SMI_R_VALID (1 << 27) /* 0 - Write, 1 - Read */
76 #define SMI_OP_W (0 << 26) /* Write operation */
77 #define SMI_OP_R (1 << 26) /* Read operation */
79 #define PHY_WAIT_ITERATIONS 10
81 #define PXA168_ETH_PHY_ADDR_DEFAULT 0
82 /* RX & TX descriptor command */
83 #define BUF_OWNED_BY_DMA (1 << 31)
85 /* RX descriptor status */
86 #define RX_EN_INT (1 << 23)
87 #define RX_FIRST_DESC (1 << 17)
88 #define RX_LAST_DESC (1 << 16)
89 #define RX_ERROR (1 << 15)
91 /* TX descriptor command */
92 #define TX_EN_INT (1 << 23)
93 #define TX_GEN_CRC (1 << 22)
94 #define TX_ZERO_PADDING (1 << 18)
95 #define TX_FIRST_DESC (1 << 17)
96 #define TX_LAST_DESC (1 << 16)
97 #define TX_ERROR (1 << 15)
100 #define SDMA_CMD_AT (1 << 31)
101 #define SDMA_CMD_TXDL (1 << 24)
102 #define SDMA_CMD_TXDH (1 << 23)
103 #define SDMA_CMD_AR (1 << 15)
104 #define SDMA_CMD_ERD (1 << 7)
106 /* Bit definitions of the Port Config Reg */
107 #define PCR_HS (1 << 12)
108 #define PCR_EN (1 << 7)
109 #define PCR_PM (1 << 0)
111 /* Bit definitions of the Port Config Extend Reg */
112 #define PCXR_2BSM (1 << 28)
113 #define PCXR_DSCP_EN (1 << 21)
114 #define PCXR_MFL_1518 (0 << 14)
115 #define PCXR_MFL_1536 (1 << 14)
116 #define PCXR_MFL_2048 (2 << 14)
117 #define PCXR_MFL_64K (3 << 14)
118 #define PCXR_FLP (1 << 11)
119 #define PCXR_PRIO_TX_OFF 3
120 #define PCXR_TX_HIGH_PRI (7 << PCXR_PRIO_TX_OFF)
122 /* Bit definitions of the SDMA Config Reg */
123 #define SDCR_BSZ_OFF 12
124 #define SDCR_BSZ8 (3 << SDCR_BSZ_OFF)
125 #define SDCR_BSZ4 (2 << SDCR_BSZ_OFF)
126 #define SDCR_BSZ2 (1 << SDCR_BSZ_OFF)
127 #define SDCR_BSZ1 (0 << SDCR_BSZ_OFF)
128 #define SDCR_BLMR (1 << 6)
129 #define SDCR_BLMT (1 << 7)
130 #define SDCR_RIFB (1 << 9)
131 #define SDCR_RC_OFF 2
132 #define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF)
135 * Bit definitions of the Interrupt Cause Reg
136 * and Interrupt MASK Reg is the same
138 #define ICR_RXBUF (1 << 0)
139 #define ICR_TXBUF_H (1 << 2)
140 #define ICR_TXBUF_L (1 << 3)
141 #define ICR_TXEND_H (1 << 6)
142 #define ICR_TXEND_L (1 << 7)
143 #define ICR_RXERR (1 << 8)
144 #define ICR_TXERR_H (1 << 10)
145 #define ICR_TXERR_L (1 << 11)
146 #define ICR_TX_UDR (1 << 13)
147 #define ICR_MII_CH (1 << 28)
149 #define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\
150 ICR_TXERR_H | ICR_TXERR_L |\
151 ICR_TXEND_H | ICR_TXEND_L |\
152 ICR_RXBUF | ICR_RXERR | ICR_MII_CH)
154 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
156 #define NUM_RX_DESCS 64
157 #define NUM_TX_DESCS 64
160 #define HASH_DELETE 1
161 #define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */
162 #define HOP_NUMBER 12
164 /* Bit definitions for Port status */
165 #define PORT_SPEED_100 (1 << 0)
166 #define FULL_DUPLEX (1 << 1)
167 #define FLOW_CONTROL_ENABLED (1 << 2)
168 #define LINK_UP (1 << 3)
170 /* Bit definitions for work to be done */
171 #define WORK_LINK (1 << 0)
172 #define WORK_TX_DONE (1 << 1)
177 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
180 u32 cmd_sts
; /* Descriptor command status */
181 u16 byte_cnt
; /* Descriptor buffer byte count */
182 u16 buf_size
; /* Buffer size */
183 u32 buf_ptr
; /* Descriptor buffer pointer */
184 u32 next_desc_ptr
; /* Next descriptor pointer */
188 u32 cmd_sts
; /* Command/status field */
190 u16 byte_cnt
; /* buffer byte count */
191 u32 buf_ptr
; /* pointer to buffer for this descriptor */
192 u32 next_desc_ptr
; /* Pointer to next descriptor */
195 struct pxa168_eth_private
{
196 int port_num
; /* User Ethernet port number */
198 int rx_resource_err
; /* Rx ring resource error flag */
200 /* Next available and first returning Rx resource */
201 int rx_curr_desc_q
, rx_used_desc_q
;
203 /* Next available and first returning Tx resource */
204 int tx_curr_desc_q
, tx_used_desc_q
;
206 struct rx_desc
*p_rx_desc_area
;
207 dma_addr_t rx_desc_dma
;
208 int rx_desc_area_size
;
209 struct sk_buff
**rx_skb
;
211 struct tx_desc
*p_tx_desc_area
;
212 dma_addr_t tx_desc_dma
;
213 int tx_desc_area_size
;
214 struct sk_buff
**tx_skb
;
216 struct work_struct tx_timeout_task
;
218 struct net_device
*dev
;
219 struct napi_struct napi
;
223 struct net_device_stats stats
;
224 /* Size of Tx Ring per queue */
226 /* Number of tx descriptors in use */
228 /* Size of Rx Ring per queue */
230 /* Number of rx descriptors in use */
234 * Used in case RX Ring is empty, which can occur when
235 * system does not have resources (skb's)
237 struct timer_list timeout
;
238 struct mii_bus
*smi_bus
;
239 struct phy_device
*phy
;
243 struct pxa168_eth_platform_data
*pd
;
245 * Ethernet controller base address.
249 /* Pointer to the hardware address filter table */
254 struct addr_table_entry
{
259 /* Bit fields of a Hash Table Entry */
260 enum hash_table_entry
{
261 HASH_ENTRY_VALID
= 1,
263 HASH_ENTRY_RECEIVE_DISCARD
= 4,
264 HASH_ENTRY_RECEIVE_DISCARD_BIT
= 2
267 static int pxa168_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
);
268 static int pxa168_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
);
269 static int pxa168_init_hw(struct pxa168_eth_private
*pep
);
270 static void eth_port_reset(struct net_device
*dev
);
271 static void eth_port_start(struct net_device
*dev
);
272 static int pxa168_eth_open(struct net_device
*dev
);
273 static int pxa168_eth_stop(struct net_device
*dev
);
274 static int ethernet_phy_setup(struct net_device
*dev
);
276 static inline u32
rdl(struct pxa168_eth_private
*pep
, int offset
)
278 return readl(pep
->base
+ offset
);
281 static inline void wrl(struct pxa168_eth_private
*pep
, int offset
, u32 data
)
283 writel(data
, pep
->base
+ offset
);
286 static void abort_dma(struct pxa168_eth_private
*pep
)
289 int max_retries
= 40;
292 wrl(pep
, SDMA_CMD
, SDMA_CMD_AR
| SDMA_CMD_AT
);
296 while ((rdl(pep
, SDMA_CMD
) & (SDMA_CMD_AR
| SDMA_CMD_AT
))
300 } while (max_retries
-- > 0 && delay
<= 0);
302 if (max_retries
<= 0)
303 printk(KERN_ERR
"%s : DMA Stuck\n", __func__
);
306 static int ethernet_phy_get(struct pxa168_eth_private
*pep
)
308 unsigned int reg_data
;
310 reg_data
= rdl(pep
, PHY_ADDRESS
);
312 return (reg_data
>> (5 * pep
->port_num
)) & 0x1f;
315 static void ethernet_phy_set_addr(struct pxa168_eth_private
*pep
, int phy_addr
)
318 int addr_shift
= 5 * pep
->port_num
;
320 reg_data
= rdl(pep
, PHY_ADDRESS
);
321 reg_data
&= ~(0x1f << addr_shift
);
322 reg_data
|= (phy_addr
& 0x1f) << addr_shift
;
323 wrl(pep
, PHY_ADDRESS
, reg_data
);
326 static void ethernet_phy_reset(struct pxa168_eth_private
*pep
)
330 data
= phy_read(pep
->phy
, MII_BMCR
);
335 if (phy_write(pep
->phy
, MII_BMCR
, data
) < 0)
339 data
= phy_read(pep
->phy
, MII_BMCR
);
340 } while (data
>= 0 && data
& BMCR_RESET
);
343 static void rxq_refill(struct net_device
*dev
)
345 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
347 struct rx_desc
*p_used_rx_desc
;
350 while (pep
->rx_desc_count
< pep
->rx_ring_size
) {
353 skb
= netdev_alloc_skb(dev
, pep
->skb_size
);
357 skb_reserve(skb
, SKB_DMA_REALIGN
);
358 pep
->rx_desc_count
++;
359 /* Get 'used' Rx descriptor */
360 used_rx_desc
= pep
->rx_used_desc_q
;
361 p_used_rx_desc
= &pep
->p_rx_desc_area
[used_rx_desc
];
362 size
= skb
->end
- skb
->data
;
363 p_used_rx_desc
->buf_ptr
= dma_map_single(NULL
,
367 p_used_rx_desc
->buf_size
= size
;
368 pep
->rx_skb
[used_rx_desc
] = skb
;
370 /* Return the descriptor to DMA ownership */
372 p_used_rx_desc
->cmd_sts
= BUF_OWNED_BY_DMA
| RX_EN_INT
;
375 /* Move the used descriptor pointer to the next descriptor */
376 pep
->rx_used_desc_q
= (used_rx_desc
+ 1) % pep
->rx_ring_size
;
378 /* Any Rx return cancels the Rx resource error status */
379 pep
->rx_resource_err
= 0;
381 skb_reserve(skb
, ETH_HW_IP_ALIGN
);
385 * If RX ring is empty of SKB, set a timer to try allocating
386 * again at a later time.
388 if (pep
->rx_desc_count
== 0) {
389 pep
->timeout
.expires
= jiffies
+ (HZ
/ 10);
390 add_timer(&pep
->timeout
);
394 static inline void rxq_refill_timer_wrapper(unsigned long data
)
396 struct pxa168_eth_private
*pep
= (void *)data
;
397 napi_schedule(&pep
->napi
);
400 static inline u8
flip_8_bits(u8 x
)
402 return (((x
) & 0x01) << 3) | (((x
) & 0x02) << 1)
403 | (((x
) & 0x04) >> 1) | (((x
) & 0x08) >> 3)
404 | (((x
) & 0x10) << 3) | (((x
) & 0x20) << 1)
405 | (((x
) & 0x40) >> 1) | (((x
) & 0x80) >> 3);
408 static void nibble_swap_every_byte(unsigned char *mac_addr
)
411 for (i
= 0; i
< ETH_ALEN
; i
++) {
412 mac_addr
[i
] = ((mac_addr
[i
] & 0x0f) << 4) |
413 ((mac_addr
[i
] & 0xf0) >> 4);
417 static void inverse_every_nibble(unsigned char *mac_addr
)
420 for (i
= 0; i
< ETH_ALEN
; i
++)
421 mac_addr
[i
] = flip_8_bits(mac_addr
[i
]);
425 * ----------------------------------------------------------------------------
426 * This function will calculate the hash function of the address.
428 * mac_addr_orig - MAC address.
430 * return the calculated entry.
432 static u32
hash_function(unsigned char *mac_addr_orig
)
439 unsigned char mac_addr
[ETH_ALEN
];
441 /* Make a copy of MAC address since we are going to performe bit
444 memcpy(mac_addr
, mac_addr_orig
, ETH_ALEN
);
446 nibble_swap_every_byte(mac_addr
);
447 inverse_every_nibble(mac_addr
);
449 addr0
= (mac_addr
[5] >> 2) & 0x3f;
450 addr1
= (mac_addr
[5] & 0x03) | (((mac_addr
[4] & 0x7f)) << 2);
451 addr2
= ((mac_addr
[4] & 0x80) >> 7) | mac_addr
[3] << 1;
452 addr3
= (mac_addr
[2] & 0xff) | ((mac_addr
[1] & 1) << 8);
454 hash_result
= (addr0
<< 9) | (addr1
^ addr2
^ addr3
);
455 hash_result
= hash_result
& 0x07ff;
460 * ----------------------------------------------------------------------------
461 * This function will add/del an entry to the address table.
464 * mac_addr - MAC address.
465 * skip - if 1, skip this address.Used in case of deleting an entry which is a
466 * part of chain in the hash table.We can't just delete the entry since
467 * that will break the chain.We need to defragment the tables time to
469 * rd - 0 Discard packet upon match.
470 * - 1 Receive packet upon match.
472 * address table entry is added/deleted.
474 * -ENOSPC if table full
476 static int add_del_hash_entry(struct pxa168_eth_private
*pep
,
477 unsigned char *mac_addr
,
478 u32 rd
, u32 skip
, int del
)
480 struct addr_table_entry
*entry
, *start
;
485 new_low
= (((mac_addr
[1] >> 4) & 0xf) << 15)
486 | (((mac_addr
[1] >> 0) & 0xf) << 11)
487 | (((mac_addr
[0] >> 4) & 0xf) << 7)
488 | (((mac_addr
[0] >> 0) & 0xf) << 3)
489 | (((mac_addr
[3] >> 4) & 0x1) << 31)
490 | (((mac_addr
[3] >> 0) & 0xf) << 27)
491 | (((mac_addr
[2] >> 4) & 0xf) << 23)
492 | (((mac_addr
[2] >> 0) & 0xf) << 19)
493 | (skip
<< SKIP
) | (rd
<< HASH_ENTRY_RECEIVE_DISCARD_BIT
)
496 new_high
= (((mac_addr
[5] >> 4) & 0xf) << 15)
497 | (((mac_addr
[5] >> 0) & 0xf) << 11)
498 | (((mac_addr
[4] >> 4) & 0xf) << 7)
499 | (((mac_addr
[4] >> 0) & 0xf) << 3)
500 | (((mac_addr
[3] >> 5) & 0x7) << 0);
503 * Pick the appropriate table, start scanning for free/reusable
504 * entries at the index obtained by hashing the specified MAC address
507 entry
= start
+ hash_function(mac_addr
);
508 for (i
= 0; i
< HOP_NUMBER
; i
++) {
509 if (!(le32_to_cpu(entry
->lo
) & HASH_ENTRY_VALID
)) {
512 /* if same address put in same position */
513 if (((le32_to_cpu(entry
->lo
) & 0xfffffff8) ==
514 (new_low
& 0xfffffff8)) &&
515 (le32_to_cpu(entry
->hi
) == new_high
)) {
519 if (entry
== start
+ 0x7ff)
525 if (((le32_to_cpu(entry
->lo
) & 0xfffffff8) != (new_low
& 0xfffffff8)) &&
526 (le32_to_cpu(entry
->hi
) != new_high
) && del
)
529 if (i
== HOP_NUMBER
) {
531 printk(KERN_INFO
"%s: table section is full, need to "
532 "move to 16kB implementation?\n",
540 * Update the selected entry
546 entry
->hi
= cpu_to_le32(new_high
);
547 entry
->lo
= cpu_to_le32(new_low
);
554 * ----------------------------------------------------------------------------
555 * Create an addressTable entry from MAC address info
556 * found in the specifed net_device struct
558 * Input : pointer to ethernet interface network device structure
561 static void update_hash_table_mac_address(struct pxa168_eth_private
*pep
,
562 unsigned char *oaddr
,
565 /* Delete old entry */
567 add_del_hash_entry(pep
, oaddr
, 1, 0, HASH_DELETE
);
569 add_del_hash_entry(pep
, addr
, 1, 0, HASH_ADD
);
572 static int init_hash_table(struct pxa168_eth_private
*pep
)
575 * Hardware expects CPU to build a hash table based on a predefined
576 * hash function and populate it based on hardware address. The
577 * location of the hash table is identified by 32-bit pointer stored
578 * in HTPR internal register. Two possible sizes exists for the hash
579 * table 8kB (256kB of DRAM required (4 x 64 kB banks)) and 1/2kB
580 * (16kB of DRAM required (4 x 4 kB banks)).We currently only support
583 /* TODO: Add support for 8kB hash table and alternative hash
584 * function.Driver can dynamically switch to them if the 1/2kB hash
587 if (pep
->htpr
== NULL
) {
588 pep
->htpr
= dma_alloc_coherent(pep
->dev
->dev
.parent
,
589 HASH_ADDR_TABLE_SIZE
,
590 &pep
->htpr_dma
, GFP_KERNEL
);
591 if (pep
->htpr
== NULL
)
594 memset(pep
->htpr
, 0, HASH_ADDR_TABLE_SIZE
);
595 wrl(pep
, HTPR
, pep
->htpr_dma
);
599 static void pxa168_eth_set_rx_mode(struct net_device
*dev
)
601 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
602 struct netdev_hw_addr
*ha
;
605 val
= rdl(pep
, PORT_CONFIG
);
606 if (dev
->flags
& IFF_PROMISC
)
610 wrl(pep
, PORT_CONFIG
, val
);
613 * Remove the old list of MAC address and add dev->addr
614 * and multicast address.
616 memset(pep
->htpr
, 0, HASH_ADDR_TABLE_SIZE
);
617 update_hash_table_mac_address(pep
, NULL
, dev
->dev_addr
);
619 netdev_for_each_mc_addr(ha
, dev
)
620 update_hash_table_mac_address(pep
, NULL
, ha
->addr
);
623 static int pxa168_eth_set_mac_address(struct net_device
*dev
, void *addr
)
625 struct sockaddr
*sa
= addr
;
626 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
627 unsigned char oldMac
[ETH_ALEN
];
629 if (!is_valid_ether_addr(sa
->sa_data
))
631 memcpy(oldMac
, dev
->dev_addr
, ETH_ALEN
);
632 dev
->addr_assign_type
&= ~NET_ADDR_RANDOM
;
633 memcpy(dev
->dev_addr
, sa
->sa_data
, ETH_ALEN
);
634 netif_addr_lock_bh(dev
);
635 update_hash_table_mac_address(pep
, oldMac
, dev
->dev_addr
);
636 netif_addr_unlock_bh(dev
);
640 static void eth_port_start(struct net_device
*dev
)
642 unsigned int val
= 0;
643 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
644 int tx_curr_desc
, rx_curr_desc
;
646 /* Perform PHY reset, if there is a PHY. */
647 if (pep
->phy
!= NULL
) {
648 struct ethtool_cmd cmd
;
650 pxa168_get_settings(pep
->dev
, &cmd
);
651 ethernet_phy_reset(pep
);
652 pxa168_set_settings(pep
->dev
, &cmd
);
655 /* Assignment of Tx CTRP of given queue */
656 tx_curr_desc
= pep
->tx_curr_desc_q
;
657 wrl(pep
, ETH_C_TX_DESC_1
,
658 (u32
) (pep
->tx_desc_dma
+ tx_curr_desc
* sizeof(struct tx_desc
)));
660 /* Assignment of Rx CRDP of given queue */
661 rx_curr_desc
= pep
->rx_curr_desc_q
;
662 wrl(pep
, ETH_C_RX_DESC_0
,
663 (u32
) (pep
->rx_desc_dma
+ rx_curr_desc
* sizeof(struct rx_desc
)));
665 wrl(pep
, ETH_F_RX_DESC_0
,
666 (u32
) (pep
->rx_desc_dma
+ rx_curr_desc
* sizeof(struct rx_desc
)));
668 /* Clear all interrupts */
669 wrl(pep
, INT_CAUSE
, 0);
671 /* Enable all interrupts for receive, transmit and error. */
672 wrl(pep
, INT_MASK
, ALL_INTS
);
674 val
= rdl(pep
, PORT_CONFIG
);
676 wrl(pep
, PORT_CONFIG
, val
);
678 /* Start RX DMA engine */
679 val
= rdl(pep
, SDMA_CMD
);
681 wrl(pep
, SDMA_CMD
, val
);
684 static void eth_port_reset(struct net_device
*dev
)
686 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
687 unsigned int val
= 0;
689 /* Stop all interrupts for receive, transmit and error. */
690 wrl(pep
, INT_MASK
, 0);
692 /* Clear all interrupts */
693 wrl(pep
, INT_CAUSE
, 0);
696 val
= rdl(pep
, SDMA_CMD
);
697 val
&= ~SDMA_CMD_ERD
; /* abort dma command */
699 /* Abort any transmit and receive operations and put DMA
705 val
= rdl(pep
, PORT_CONFIG
);
707 wrl(pep
, PORT_CONFIG
, val
);
711 * txq_reclaim - Free the tx desc data for completed descriptors
712 * If force is non-zero, frees uncompleted descriptors as well
714 static int txq_reclaim(struct net_device
*dev
, int force
)
716 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
717 struct tx_desc
*desc
;
727 pep
->work_todo
&= ~WORK_TX_DONE
;
728 while (pep
->tx_desc_count
> 0) {
729 tx_index
= pep
->tx_used_desc_q
;
730 desc
= &pep
->p_tx_desc_area
[tx_index
];
731 cmd_sts
= desc
->cmd_sts
;
732 if (!force
&& (cmd_sts
& BUF_OWNED_BY_DMA
)) {
734 goto txq_reclaim_end
;
737 goto txq_reclaim_end
;
740 pep
->tx_used_desc_q
= (tx_index
+ 1) % pep
->tx_ring_size
;
741 pep
->tx_desc_count
--;
742 addr
= desc
->buf_ptr
;
743 count
= desc
->byte_cnt
;
744 skb
= pep
->tx_skb
[tx_index
];
746 pep
->tx_skb
[tx_index
] = NULL
;
748 if (cmd_sts
& TX_ERROR
) {
750 printk(KERN_ERR
"%s: Error in TX\n", dev
->name
);
751 dev
->stats
.tx_errors
++;
753 dma_unmap_single(NULL
, addr
, count
, DMA_TO_DEVICE
);
755 dev_kfree_skb_irq(skb
);
759 netif_tx_unlock(dev
);
763 static void pxa168_eth_tx_timeout(struct net_device
*dev
)
765 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
767 printk(KERN_INFO
"%s: TX timeout desc_count %d\n",
768 dev
->name
, pep
->tx_desc_count
);
770 schedule_work(&pep
->tx_timeout_task
);
773 static void pxa168_eth_tx_timeout_task(struct work_struct
*work
)
775 struct pxa168_eth_private
*pep
= container_of(work
,
776 struct pxa168_eth_private
,
778 struct net_device
*dev
= pep
->dev
;
779 pxa168_eth_stop(dev
);
780 pxa168_eth_open(dev
);
783 static int rxq_process(struct net_device
*dev
, int budget
)
785 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
786 struct net_device_stats
*stats
= &dev
->stats
;
787 unsigned int received_packets
= 0;
790 while (budget
-- > 0) {
791 int rx_next_curr_desc
, rx_curr_desc
, rx_used_desc
;
792 struct rx_desc
*rx_desc
;
793 unsigned int cmd_sts
;
795 /* Do not process Rx ring in case of Rx ring resource error */
796 if (pep
->rx_resource_err
)
798 rx_curr_desc
= pep
->rx_curr_desc_q
;
799 rx_used_desc
= pep
->rx_used_desc_q
;
800 rx_desc
= &pep
->p_rx_desc_area
[rx_curr_desc
];
801 cmd_sts
= rx_desc
->cmd_sts
;
803 if (cmd_sts
& (BUF_OWNED_BY_DMA
))
805 skb
= pep
->rx_skb
[rx_curr_desc
];
806 pep
->rx_skb
[rx_curr_desc
] = NULL
;
808 rx_next_curr_desc
= (rx_curr_desc
+ 1) % pep
->rx_ring_size
;
809 pep
->rx_curr_desc_q
= rx_next_curr_desc
;
811 /* Rx descriptors exhausted. */
812 /* Set the Rx ring resource error flag */
813 if (rx_next_curr_desc
== rx_used_desc
)
814 pep
->rx_resource_err
= 1;
815 pep
->rx_desc_count
--;
816 dma_unmap_single(NULL
, rx_desc
->buf_ptr
,
822 * Note byte count includes 4 byte CRC count
825 stats
->rx_bytes
+= rx_desc
->byte_cnt
;
827 * In case received a packet without first / last bits on OR
828 * the error summary bit is on, the packets needs to be droped.
830 if (((cmd_sts
& (RX_FIRST_DESC
| RX_LAST_DESC
)) !=
831 (RX_FIRST_DESC
| RX_LAST_DESC
))
832 || (cmd_sts
& RX_ERROR
)) {
835 if ((cmd_sts
& (RX_FIRST_DESC
| RX_LAST_DESC
)) !=
836 (RX_FIRST_DESC
| RX_LAST_DESC
)) {
839 "%s: Rx pkt on multiple desc\n",
842 if (cmd_sts
& RX_ERROR
)
844 dev_kfree_skb_irq(skb
);
847 * The -4 is for the CRC in the trailer of the
850 skb_put(skb
, rx_desc
->byte_cnt
- 4);
851 skb
->protocol
= eth_type_trans(skb
, dev
);
852 netif_receive_skb(skb
);
855 /* Fill RX ring with skb's */
857 return received_packets
;
860 static int pxa168_eth_collect_events(struct pxa168_eth_private
*pep
,
861 struct net_device
*dev
)
866 icr
= rdl(pep
, INT_CAUSE
);
870 wrl(pep
, INT_CAUSE
, ~icr
);
871 if (icr
& (ICR_TXBUF_H
| ICR_TXBUF_L
)) {
872 pep
->work_todo
|= WORK_TX_DONE
;
877 if (icr
& ICR_MII_CH
) {
878 pep
->work_todo
|= WORK_LINK
;
884 static void handle_link_event(struct pxa168_eth_private
*pep
)
886 struct net_device
*dev
= pep
->dev
;
892 port_status
= rdl(pep
, PORT_STATUS
);
893 if (!(port_status
& LINK_UP
)) {
894 if (netif_carrier_ok(dev
)) {
895 printk(KERN_INFO
"%s: link down\n", dev
->name
);
896 netif_carrier_off(dev
);
901 if (port_status
& PORT_SPEED_100
)
906 duplex
= (port_status
& FULL_DUPLEX
) ? 1 : 0;
907 fc
= (port_status
& FLOW_CONTROL_ENABLED
) ? 1 : 0;
908 printk(KERN_INFO
"%s: link up, %d Mb/s, %s duplex, "
909 "flow control %sabled\n", dev
->name
,
910 speed
, duplex
? "full" : "half", fc
? "en" : "dis");
911 if (!netif_carrier_ok(dev
))
912 netif_carrier_on(dev
);
915 static irqreturn_t
pxa168_eth_int_handler(int irq
, void *dev_id
)
917 struct net_device
*dev
= (struct net_device
*)dev_id
;
918 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
920 if (unlikely(!pxa168_eth_collect_events(pep
, dev
)))
922 /* Disable interrupts */
923 wrl(pep
, INT_MASK
, 0);
924 napi_schedule(&pep
->napi
);
928 static void pxa168_eth_recalc_skb_size(struct pxa168_eth_private
*pep
)
933 * Reserve 2+14 bytes for an ethernet header (the hardware
934 * automatically prepends 2 bytes of dummy data to each
935 * received packet), 16 bytes for up to four VLAN tags, and
936 * 4 bytes for the trailing FCS -- 36 bytes total.
938 skb_size
= pep
->dev
->mtu
+ 36;
941 * Make sure that the skb size is a multiple of 8 bytes, as
942 * the lower three bits of the receive descriptor's buffer
943 * size field are ignored by the hardware.
945 pep
->skb_size
= (skb_size
+ 7) & ~7;
948 * If NET_SKB_PAD is smaller than a cache line,
949 * netdev_alloc_skb() will cause skb->data to be misaligned
950 * to a cache line boundary. If this is the case, include
951 * some extra space to allow re-aligning the data area.
953 pep
->skb_size
+= SKB_DMA_REALIGN
;
957 static int set_port_config_ext(struct pxa168_eth_private
*pep
)
961 pxa168_eth_recalc_skb_size(pep
);
962 if (pep
->skb_size
<= 1518)
963 skb_size
= PCXR_MFL_1518
;
964 else if (pep
->skb_size
<= 1536)
965 skb_size
= PCXR_MFL_1536
;
966 else if (pep
->skb_size
<= 2048)
967 skb_size
= PCXR_MFL_2048
;
969 skb_size
= PCXR_MFL_64K
;
971 /* Extended Port Configuration */
973 PORT_CONFIG_EXT
, PCXR_2BSM
| /* Two byte prefix aligns IP hdr */
974 PCXR_DSCP_EN
| /* Enable DSCP in IP */
975 skb_size
| PCXR_FLP
| /* do not force link pass */
976 PCXR_TX_HIGH_PRI
); /* Transmit - high priority queue */
981 static int pxa168_init_hw(struct pxa168_eth_private
*pep
)
985 /* Disable interrupts */
986 wrl(pep
, INT_MASK
, 0);
987 wrl(pep
, INT_CAUSE
, 0);
988 /* Write to ICR to clear interrupts. */
989 wrl(pep
, INT_W_CLEAR
, 0);
990 /* Abort any transmit and receive operations and put DMA
994 /* Initialize address hash table */
995 err
= init_hash_table(pep
);
998 /* SDMA configuration */
999 wrl(pep
, SDMA_CONFIG
, SDCR_BSZ8
| /* Burst size = 32 bytes */
1000 SDCR_RIFB
| /* Rx interrupt on frame */
1001 SDCR_BLMT
| /* Little endian transmit */
1002 SDCR_BLMR
| /* Little endian receive */
1003 SDCR_RC_MAX_RETRANS
); /* Max retransmit count */
1004 /* Port Configuration */
1005 wrl(pep
, PORT_CONFIG
, PCR_HS
); /* Hash size is 1/2kb */
1006 set_port_config_ext(pep
);
1011 static int rxq_init(struct net_device
*dev
)
1013 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
1014 struct rx_desc
*p_rx_desc
;
1015 int size
= 0, i
= 0;
1016 int rx_desc_num
= pep
->rx_ring_size
;
1018 /* Allocate RX skb rings */
1019 pep
->rx_skb
= kmalloc(sizeof(*pep
->rx_skb
) * pep
->rx_ring_size
,
1024 /* Allocate RX ring */
1025 pep
->rx_desc_count
= 0;
1026 size
= pep
->rx_ring_size
* sizeof(struct rx_desc
);
1027 pep
->rx_desc_area_size
= size
;
1028 pep
->p_rx_desc_area
= dma_alloc_coherent(pep
->dev
->dev
.parent
, size
,
1029 &pep
->rx_desc_dma
, GFP_KERNEL
);
1030 if (!pep
->p_rx_desc_area
) {
1031 printk(KERN_ERR
"%s: Cannot alloc RX ring (size %d bytes)\n",
1035 memset((void *)pep
->p_rx_desc_area
, 0, size
);
1036 /* initialize the next_desc_ptr links in the Rx descriptors ring */
1037 p_rx_desc
= (struct rx_desc
*)pep
->p_rx_desc_area
;
1038 for (i
= 0; i
< rx_desc_num
; i
++) {
1039 p_rx_desc
[i
].next_desc_ptr
= pep
->rx_desc_dma
+
1040 ((i
+ 1) % rx_desc_num
) * sizeof(struct rx_desc
);
1042 /* Save Rx desc pointer to driver struct. */
1043 pep
->rx_curr_desc_q
= 0;
1044 pep
->rx_used_desc_q
= 0;
1045 pep
->rx_desc_area_size
= rx_desc_num
* sizeof(struct rx_desc
);
1052 static void rxq_deinit(struct net_device
*dev
)
1054 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
1057 /* Free preallocated skb's on RX rings */
1058 for (curr
= 0; pep
->rx_desc_count
&& curr
< pep
->rx_ring_size
; curr
++) {
1059 if (pep
->rx_skb
[curr
]) {
1060 dev_kfree_skb(pep
->rx_skb
[curr
]);
1061 pep
->rx_desc_count
--;
1064 if (pep
->rx_desc_count
)
1066 "Error in freeing Rx Ring. %d skb's still\n",
1067 pep
->rx_desc_count
);
1069 if (pep
->p_rx_desc_area
)
1070 dma_free_coherent(pep
->dev
->dev
.parent
, pep
->rx_desc_area_size
,
1071 pep
->p_rx_desc_area
, pep
->rx_desc_dma
);
1075 static int txq_init(struct net_device
*dev
)
1077 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
1078 struct tx_desc
*p_tx_desc
;
1079 int size
= 0, i
= 0;
1080 int tx_desc_num
= pep
->tx_ring_size
;
1082 pep
->tx_skb
= kmalloc(sizeof(*pep
->tx_skb
) * pep
->tx_ring_size
,
1087 /* Allocate TX ring */
1088 pep
->tx_desc_count
= 0;
1089 size
= pep
->tx_ring_size
* sizeof(struct tx_desc
);
1090 pep
->tx_desc_area_size
= size
;
1091 pep
->p_tx_desc_area
= dma_alloc_coherent(pep
->dev
->dev
.parent
, size
,
1092 &pep
->tx_desc_dma
, GFP_KERNEL
);
1093 if (!pep
->p_tx_desc_area
) {
1094 printk(KERN_ERR
"%s: Cannot allocate Tx Ring (size %d bytes)\n",
1098 memset((void *)pep
->p_tx_desc_area
, 0, pep
->tx_desc_area_size
);
1099 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
1100 p_tx_desc
= (struct tx_desc
*)pep
->p_tx_desc_area
;
1101 for (i
= 0; i
< tx_desc_num
; i
++) {
1102 p_tx_desc
[i
].next_desc_ptr
= pep
->tx_desc_dma
+
1103 ((i
+ 1) % tx_desc_num
) * sizeof(struct tx_desc
);
1105 pep
->tx_curr_desc_q
= 0;
1106 pep
->tx_used_desc_q
= 0;
1107 pep
->tx_desc_area_size
= tx_desc_num
* sizeof(struct tx_desc
);
1114 static void txq_deinit(struct net_device
*dev
)
1116 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
1118 /* Free outstanding skb's on TX ring */
1119 txq_reclaim(dev
, 1);
1120 BUG_ON(pep
->tx_used_desc_q
!= pep
->tx_curr_desc_q
);
1122 if (pep
->p_tx_desc_area
)
1123 dma_free_coherent(pep
->dev
->dev
.parent
, pep
->tx_desc_area_size
,
1124 pep
->p_tx_desc_area
, pep
->tx_desc_dma
);
1128 static int pxa168_eth_open(struct net_device
*dev
)
1130 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
1133 err
= request_irq(dev
->irq
, pxa168_eth_int_handler
,
1134 IRQF_DISABLED
, dev
->name
, dev
);
1136 dev_printk(KERN_ERR
, &dev
->dev
, "can't assign irq\n");
1139 pep
->rx_resource_err
= 0;
1140 err
= rxq_init(dev
);
1143 err
= txq_init(dev
);
1145 goto out_free_rx_skb
;
1146 pep
->rx_used_desc_q
= 0;
1147 pep
->rx_curr_desc_q
= 0;
1149 /* Fill RX ring with skb's */
1151 pep
->rx_used_desc_q
= 0;
1152 pep
->rx_curr_desc_q
= 0;
1153 netif_carrier_off(dev
);
1154 eth_port_start(dev
);
1155 napi_enable(&pep
->napi
);
1160 free_irq(dev
->irq
, dev
);
1164 static int pxa168_eth_stop(struct net_device
*dev
)
1166 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
1167 eth_port_reset(dev
);
1169 /* Disable interrupts */
1170 wrl(pep
, INT_MASK
, 0);
1171 wrl(pep
, INT_CAUSE
, 0);
1172 /* Write to ICR to clear interrupts. */
1173 wrl(pep
, INT_W_CLEAR
, 0);
1174 napi_disable(&pep
->napi
);
1175 del_timer_sync(&pep
->timeout
);
1176 netif_carrier_off(dev
);
1177 free_irq(dev
->irq
, dev
);
1184 static int pxa168_eth_change_mtu(struct net_device
*dev
, int mtu
)
1187 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
1189 if ((mtu
> 9500) || (mtu
< 68))
1193 retval
= set_port_config_ext(pep
);
1195 if (!netif_running(dev
))
1199 * Stop and then re-open the interface. This will allocate RX
1200 * skbs of the new MTU.
1201 * There is a possible danger that the open will not succeed,
1202 * due to memory being full.
1204 pxa168_eth_stop(dev
);
1205 if (pxa168_eth_open(dev
)) {
1206 dev_printk(KERN_ERR
, &dev
->dev
,
1207 "fatal error on re-opening device after "
1214 static int eth_alloc_tx_desc_index(struct pxa168_eth_private
*pep
)
1218 tx_desc_curr
= pep
->tx_curr_desc_q
;
1219 pep
->tx_curr_desc_q
= (tx_desc_curr
+ 1) % pep
->tx_ring_size
;
1220 BUG_ON(pep
->tx_curr_desc_q
== pep
->tx_used_desc_q
);
1221 pep
->tx_desc_count
++;
1223 return tx_desc_curr
;
1226 static int pxa168_rx_poll(struct napi_struct
*napi
, int budget
)
1228 struct pxa168_eth_private
*pep
=
1229 container_of(napi
, struct pxa168_eth_private
, napi
);
1230 struct net_device
*dev
= pep
->dev
;
1233 if (unlikely(pep
->work_todo
& WORK_LINK
)) {
1234 pep
->work_todo
&= ~(WORK_LINK
);
1235 handle_link_event(pep
);
1238 * We call txq_reclaim every time since in NAPI interupts are disabled
1239 * and due to this we miss the TX_DONE interrupt,which is not updated in
1240 * interrupt status register.
1242 txq_reclaim(dev
, 0);
1243 if (netif_queue_stopped(dev
)
1244 && pep
->tx_ring_size
- pep
->tx_desc_count
> 1) {
1245 netif_wake_queue(dev
);
1247 work_done
= rxq_process(dev
, budget
);
1248 if (work_done
< budget
) {
1249 napi_complete(napi
);
1250 wrl(pep
, INT_MASK
, ALL_INTS
);
1256 static int pxa168_eth_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1258 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
1259 struct net_device_stats
*stats
= &dev
->stats
;
1260 struct tx_desc
*desc
;
1264 tx_index
= eth_alloc_tx_desc_index(pep
);
1265 desc
= &pep
->p_tx_desc_area
[tx_index
];
1267 pep
->tx_skb
[tx_index
] = skb
;
1268 desc
->byte_cnt
= length
;
1269 desc
->buf_ptr
= dma_map_single(NULL
, skb
->data
, length
, DMA_TO_DEVICE
);
1271 skb_tx_timestamp(skb
);
1274 desc
->cmd_sts
= BUF_OWNED_BY_DMA
| TX_GEN_CRC
| TX_FIRST_DESC
|
1275 TX_ZERO_PADDING
| TX_LAST_DESC
| TX_EN_INT
;
1277 wrl(pep
, SDMA_CMD
, SDMA_CMD_TXDH
| SDMA_CMD_ERD
);
1279 stats
->tx_bytes
+= length
;
1280 stats
->tx_packets
++;
1281 dev
->trans_start
= jiffies
;
1282 if (pep
->tx_ring_size
- pep
->tx_desc_count
<= 1) {
1283 /* We handled the current skb, but now we are out of space.*/
1284 netif_stop_queue(dev
);
1287 return NETDEV_TX_OK
;
1290 static int smi_wait_ready(struct pxa168_eth_private
*pep
)
1294 /* wait for the SMI register to become available */
1295 for (i
= 0; rdl(pep
, SMI
) & SMI_BUSY
; i
++) {
1296 if (i
== PHY_WAIT_ITERATIONS
)
1304 static int pxa168_smi_read(struct mii_bus
*bus
, int phy_addr
, int regnum
)
1306 struct pxa168_eth_private
*pep
= bus
->priv
;
1310 if (smi_wait_ready(pep
)) {
1311 printk(KERN_WARNING
"pxa168_eth: SMI bus busy timeout\n");
1314 wrl(pep
, SMI
, (phy_addr
<< 16) | (regnum
<< 21) | SMI_OP_R
);
1315 /* now wait for the data to be valid */
1316 for (i
= 0; !((val
= rdl(pep
, SMI
)) & SMI_R_VALID
); i
++) {
1317 if (i
== PHY_WAIT_ITERATIONS
) {
1319 "pxa168_eth: SMI bus read not valid\n");
1325 return val
& 0xffff;
1328 static int pxa168_smi_write(struct mii_bus
*bus
, int phy_addr
, int regnum
,
1331 struct pxa168_eth_private
*pep
= bus
->priv
;
1333 if (smi_wait_ready(pep
)) {
1334 printk(KERN_WARNING
"pxa168_eth: SMI bus busy timeout\n");
1338 wrl(pep
, SMI
, (phy_addr
<< 16) | (regnum
<< 21) |
1339 SMI_OP_W
| (value
& 0xffff));
1341 if (smi_wait_ready(pep
)) {
1342 printk(KERN_ERR
"pxa168_eth: SMI bus busy timeout\n");
1349 static int pxa168_eth_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
,
1352 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
1353 if (pep
->phy
!= NULL
)
1354 return phy_mii_ioctl(pep
->phy
, ifr
, cmd
);
1359 static struct phy_device
*phy_scan(struct pxa168_eth_private
*pep
, int phy_addr
)
1361 struct mii_bus
*bus
= pep
->smi_bus
;
1362 struct phy_device
*phydev
;
1367 if (phy_addr
== PXA168_ETH_PHY_ADDR_DEFAULT
) {
1368 /* Scan entire range */
1369 start
= ethernet_phy_get(pep
);
1372 /* Use phy addr specific to platform */
1373 start
= phy_addr
& 0x1f;
1377 for (i
= 0; i
< num
; i
++) {
1378 int addr
= (start
+ i
) & 0x1f;
1379 if (bus
->phy_map
[addr
] == NULL
)
1380 mdiobus_scan(bus
, addr
);
1382 if (phydev
== NULL
) {
1383 phydev
= bus
->phy_map
[addr
];
1385 ethernet_phy_set_addr(pep
, addr
);
1392 static void phy_init(struct pxa168_eth_private
*pep
, int speed
, int duplex
)
1394 struct phy_device
*phy
= pep
->phy
;
1395 ethernet_phy_reset(pep
);
1397 phy_attach(pep
->dev
, dev_name(&phy
->dev
), 0, PHY_INTERFACE_MODE_MII
);
1400 phy
->autoneg
= AUTONEG_ENABLE
;
1403 phy
->supported
&= PHY_BASIC_FEATURES
;
1404 phy
->advertising
= phy
->supported
| ADVERTISED_Autoneg
;
1406 phy
->autoneg
= AUTONEG_DISABLE
;
1407 phy
->advertising
= 0;
1409 phy
->duplex
= duplex
;
1411 phy_start_aneg(phy
);
1414 static int ethernet_phy_setup(struct net_device
*dev
)
1416 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
1420 pep
->phy
= phy_scan(pep
, pep
->pd
->phy_addr
& 0x1f);
1421 if (pep
->phy
!= NULL
)
1422 phy_init(pep
, pep
->pd
->speed
, pep
->pd
->duplex
);
1423 update_hash_table_mac_address(pep
, NULL
, dev
->dev_addr
);
1428 static int pxa168_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1430 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
1433 err
= phy_read_status(pep
->phy
);
1435 err
= phy_ethtool_gset(pep
->phy
, cmd
);
1440 static int pxa168_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1442 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
1444 return phy_ethtool_sset(pep
->phy
, cmd
);
1447 static void pxa168_get_drvinfo(struct net_device
*dev
,
1448 struct ethtool_drvinfo
*info
)
1450 strncpy(info
->driver
, DRIVER_NAME
, 32);
1451 strncpy(info
->version
, DRIVER_VERSION
, 32);
1452 strncpy(info
->fw_version
, "N/A", 32);
1453 strncpy(info
->bus_info
, "N/A", 32);
1456 static const struct ethtool_ops pxa168_ethtool_ops
= {
1457 .get_settings
= pxa168_get_settings
,
1458 .set_settings
= pxa168_set_settings
,
1459 .get_drvinfo
= pxa168_get_drvinfo
,
1460 .get_link
= ethtool_op_get_link
,
1463 static const struct net_device_ops pxa168_eth_netdev_ops
= {
1464 .ndo_open
= pxa168_eth_open
,
1465 .ndo_stop
= pxa168_eth_stop
,
1466 .ndo_start_xmit
= pxa168_eth_start_xmit
,
1467 .ndo_set_rx_mode
= pxa168_eth_set_rx_mode
,
1468 .ndo_set_mac_address
= pxa168_eth_set_mac_address
,
1469 .ndo_validate_addr
= eth_validate_addr
,
1470 .ndo_do_ioctl
= pxa168_eth_do_ioctl
,
1471 .ndo_change_mtu
= pxa168_eth_change_mtu
,
1472 .ndo_tx_timeout
= pxa168_eth_tx_timeout
,
1475 static int pxa168_eth_probe(struct platform_device
*pdev
)
1477 struct pxa168_eth_private
*pep
= NULL
;
1478 struct net_device
*dev
= NULL
;
1479 struct resource
*res
;
1483 printk(KERN_NOTICE
"PXA168 10/100 Ethernet Driver\n");
1485 clk
= clk_get(&pdev
->dev
, "MFUCLK");
1487 printk(KERN_ERR
"%s: Fast Ethernet failed to get clock\n",
1493 dev
= alloc_etherdev(sizeof(struct pxa168_eth_private
));
1499 platform_set_drvdata(pdev
, dev
);
1500 pep
= netdev_priv(dev
);
1503 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1508 pep
->base
= ioremap(res
->start
, resource_size(res
));
1509 if (pep
->base
== NULL
) {
1513 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1515 dev
->irq
= res
->start
;
1516 dev
->netdev_ops
= &pxa168_eth_netdev_ops
;
1517 dev
->watchdog_timeo
= 2 * HZ
;
1519 SET_ETHTOOL_OPS(dev
, &pxa168_ethtool_ops
);
1521 INIT_WORK(&pep
->tx_timeout_task
, pxa168_eth_tx_timeout_task
);
1523 printk(KERN_INFO
"%s:Using random mac address\n", DRIVER_NAME
);
1524 eth_hw_addr_random(dev
);
1526 pep
->pd
= pdev
->dev
.platform_data
;
1527 pep
->rx_ring_size
= NUM_RX_DESCS
;
1528 if (pep
->pd
->rx_queue_size
)
1529 pep
->rx_ring_size
= pep
->pd
->rx_queue_size
;
1531 pep
->tx_ring_size
= NUM_TX_DESCS
;
1532 if (pep
->pd
->tx_queue_size
)
1533 pep
->tx_ring_size
= pep
->pd
->tx_queue_size
;
1535 pep
->port_num
= pep
->pd
->port_number
;
1536 /* Hardware supports only 3 ports */
1537 BUG_ON(pep
->port_num
> 2);
1538 netif_napi_add(dev
, &pep
->napi
, pxa168_rx_poll
, pep
->rx_ring_size
);
1540 memset(&pep
->timeout
, 0, sizeof(struct timer_list
));
1541 init_timer(&pep
->timeout
);
1542 pep
->timeout
.function
= rxq_refill_timer_wrapper
;
1543 pep
->timeout
.data
= (unsigned long)pep
;
1545 pep
->smi_bus
= mdiobus_alloc();
1546 if (pep
->smi_bus
== NULL
) {
1550 pep
->smi_bus
->priv
= pep
;
1551 pep
->smi_bus
->name
= "pxa168_eth smi";
1552 pep
->smi_bus
->read
= pxa168_smi_read
;
1553 pep
->smi_bus
->write
= pxa168_smi_write
;
1554 snprintf(pep
->smi_bus
->id
, MII_BUS_ID_SIZE
, "%s-%d",
1555 pdev
->name
, pdev
->id
);
1556 pep
->smi_bus
->parent
= &pdev
->dev
;
1557 pep
->smi_bus
->phy_mask
= 0xffffffff;
1558 err
= mdiobus_register(pep
->smi_bus
);
1562 pxa168_init_hw(pep
);
1563 err
= ethernet_phy_setup(dev
);
1566 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1567 err
= register_netdev(dev
);
1573 mdiobus_unregister(pep
->smi_bus
);
1575 mdiobus_free(pep
->smi_bus
);
1586 static int pxa168_eth_remove(struct platform_device
*pdev
)
1588 struct net_device
*dev
= platform_get_drvdata(pdev
);
1589 struct pxa168_eth_private
*pep
= netdev_priv(dev
);
1592 dma_free_coherent(pep
->dev
->dev
.parent
, HASH_ADDR_TABLE_SIZE
,
1593 pep
->htpr
, pep
->htpr_dma
);
1597 clk_disable(pep
->clk
);
1601 if (pep
->phy
!= NULL
)
1602 phy_detach(pep
->phy
);
1606 mdiobus_unregister(pep
->smi_bus
);
1607 mdiobus_free(pep
->smi_bus
);
1608 unregister_netdev(dev
);
1609 cancel_work_sync(&pep
->tx_timeout_task
);
1611 platform_set_drvdata(pdev
, NULL
);
1615 static void pxa168_eth_shutdown(struct platform_device
*pdev
)
1617 struct net_device
*dev
= platform_get_drvdata(pdev
);
1618 eth_port_reset(dev
);
1622 static int pxa168_eth_resume(struct platform_device
*pdev
)
1627 static int pxa168_eth_suspend(struct platform_device
*pdev
, pm_message_t state
)
1633 #define pxa168_eth_resume NULL
1634 #define pxa168_eth_suspend NULL
1637 static struct platform_driver pxa168_eth_driver
= {
1638 .probe
= pxa168_eth_probe
,
1639 .remove
= pxa168_eth_remove
,
1640 .shutdown
= pxa168_eth_shutdown
,
1641 .resume
= pxa168_eth_resume
,
1642 .suspend
= pxa168_eth_suspend
,
1644 .name
= DRIVER_NAME
,
1648 module_platform_driver(pxa168_eth_driver
);
1650 MODULE_LICENSE("GPL");
1651 MODULE_DESCRIPTION("Ethernet driver for Marvell PXA168");
1652 MODULE_ALIAS("platform:pxa168_eth");