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net-next: mediatek: fix gigabit and flow control advertisement
[deliverable/linux.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15 #include <linux/of_device.h>
16 #include <linux/of_mdio.h>
17 #include <linux/of_net.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
20 #include <linux/clk.h>
21 #include <linux/if_vlan.h>
22 #include <linux/reset.h>
23 #include <linux/tcp.h>
24
25 #include "mtk_eth_soc.h"
26
27 static int mtk_msg_level = -1;
28 module_param_named(msg_level, mtk_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 #define MTK_ETHTOOL_STAT(x) { #x, \
32 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
33
34 /* strings used by ethtool */
35 static const struct mtk_ethtool_stats {
36 char str[ETH_GSTRING_LEN];
37 u32 offset;
38 } mtk_ethtool_stats[] = {
39 MTK_ETHTOOL_STAT(tx_bytes),
40 MTK_ETHTOOL_STAT(tx_packets),
41 MTK_ETHTOOL_STAT(tx_skip),
42 MTK_ETHTOOL_STAT(tx_collisions),
43 MTK_ETHTOOL_STAT(rx_bytes),
44 MTK_ETHTOOL_STAT(rx_packets),
45 MTK_ETHTOOL_STAT(rx_overflow),
46 MTK_ETHTOOL_STAT(rx_fcs_errors),
47 MTK_ETHTOOL_STAT(rx_short_errors),
48 MTK_ETHTOOL_STAT(rx_long_errors),
49 MTK_ETHTOOL_STAT(rx_checksum_errors),
50 MTK_ETHTOOL_STAT(rx_flow_control_packets),
51 };
52
53 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
54 {
55 __raw_writel(val, eth->base + reg);
56 }
57
58 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
59 {
60 return __raw_readl(eth->base + reg);
61 }
62
63 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
64 {
65 unsigned long t_start = jiffies;
66
67 while (1) {
68 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
69 return 0;
70 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
71 break;
72 usleep_range(10, 20);
73 }
74
75 dev_err(eth->dev, "mdio: MDIO timeout\n");
76 return -1;
77 }
78
79 u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
80 u32 phy_register, u32 write_data)
81 {
82 if (mtk_mdio_busy_wait(eth))
83 return -1;
84
85 write_data &= 0xffff;
86
87 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
88 (phy_register << PHY_IAC_REG_SHIFT) |
89 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
90 MTK_PHY_IAC);
91
92 if (mtk_mdio_busy_wait(eth))
93 return -1;
94
95 return 0;
96 }
97
98 u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
99 {
100 u32 d;
101
102 if (mtk_mdio_busy_wait(eth))
103 return 0xffff;
104
105 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
106 (phy_reg << PHY_IAC_REG_SHIFT) |
107 (phy_addr << PHY_IAC_ADDR_SHIFT),
108 MTK_PHY_IAC);
109
110 if (mtk_mdio_busy_wait(eth))
111 return 0xffff;
112
113 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
114
115 return d;
116 }
117
118 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
119 int phy_reg, u16 val)
120 {
121 struct mtk_eth *eth = bus->priv;
122
123 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
124 }
125
126 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
127 {
128 struct mtk_eth *eth = bus->priv;
129
130 return _mtk_mdio_read(eth, phy_addr, phy_reg);
131 }
132
133 static void mtk_phy_link_adjust(struct net_device *dev)
134 {
135 struct mtk_mac *mac = netdev_priv(dev);
136 u16 lcl_adv = 0, rmt_adv = 0;
137 u8 flowctrl;
138 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
139 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
140 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
141 MAC_MCR_BACKPR_EN;
142
143 switch (mac->phy_dev->speed) {
144 case SPEED_1000:
145 mcr |= MAC_MCR_SPEED_1000;
146 break;
147 case SPEED_100:
148 mcr |= MAC_MCR_SPEED_100;
149 break;
150 };
151
152 if (mac->phy_dev->link)
153 mcr |= MAC_MCR_FORCE_LINK;
154
155 if (mac->phy_dev->duplex) {
156 mcr |= MAC_MCR_FORCE_DPX;
157
158 if (mac->phy_dev->pause)
159 rmt_adv = LPA_PAUSE_CAP;
160 if (mac->phy_dev->asym_pause)
161 rmt_adv |= LPA_PAUSE_ASYM;
162
163 if (mac->phy_dev->advertising & ADVERTISED_Pause)
164 lcl_adv |= ADVERTISE_PAUSE_CAP;
165 if (mac->phy_dev->advertising & ADVERTISED_Asym_Pause)
166 lcl_adv |= ADVERTISE_PAUSE_ASYM;
167
168 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
169
170 if (flowctrl & FLOW_CTRL_TX)
171 mcr |= MAC_MCR_FORCE_TX_FC;
172 if (flowctrl & FLOW_CTRL_RX)
173 mcr |= MAC_MCR_FORCE_RX_FC;
174
175 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
176 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
177 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
178 }
179
180 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
181
182 if (mac->phy_dev->link)
183 netif_carrier_on(dev);
184 else
185 netif_carrier_off(dev);
186 }
187
188 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
189 struct device_node *phy_node)
190 {
191 const __be32 *_addr = NULL;
192 struct phy_device *phydev;
193 int phy_mode, addr;
194
195 _addr = of_get_property(phy_node, "reg", NULL);
196
197 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) {
198 pr_err("%s: invalid phy address\n", phy_node->name);
199 return -EINVAL;
200 }
201 addr = be32_to_cpu(*_addr);
202 phy_mode = of_get_phy_mode(phy_node);
203 if (phy_mode < 0) {
204 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
205 return -EINVAL;
206 }
207
208 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
209 mtk_phy_link_adjust, 0, phy_mode);
210 if (!phydev) {
211 dev_err(eth->dev, "could not connect to PHY\n");
212 return -ENODEV;
213 }
214
215 dev_info(eth->dev,
216 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
217 mac->id, phydev_name(phydev), phydev->phy_id,
218 phydev->drv->name);
219
220 mac->phy_dev = phydev;
221
222 return 0;
223 }
224
225 static int mtk_phy_connect(struct mtk_mac *mac)
226 {
227 struct mtk_eth *eth = mac->hw;
228 struct device_node *np;
229 u32 val, ge_mode;
230
231 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
232 if (!np)
233 return -ENODEV;
234
235 switch (of_get_phy_mode(np)) {
236 case PHY_INTERFACE_MODE_RGMII:
237 ge_mode = 0;
238 break;
239 case PHY_INTERFACE_MODE_MII:
240 ge_mode = 1;
241 break;
242 case PHY_INTERFACE_MODE_RMII:
243 ge_mode = 2;
244 break;
245 default:
246 dev_err(eth->dev, "invalid phy_mode\n");
247 return -1;
248 }
249
250 /* put the gmac into the right mode */
251 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
252 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
253 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
254 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
255
256 mtk_phy_connect_node(eth, mac, np);
257 mac->phy_dev->autoneg = AUTONEG_ENABLE;
258 mac->phy_dev->speed = 0;
259 mac->phy_dev->duplex = 0;
260 mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
261 SUPPORTED_Asym_Pause;
262 mac->phy_dev->advertising = mac->phy_dev->supported |
263 ADVERTISED_Autoneg;
264 phy_start_aneg(mac->phy_dev);
265
266 return 0;
267 }
268
269 static int mtk_mdio_init(struct mtk_eth *eth)
270 {
271 struct device_node *mii_np;
272 int err;
273
274 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
275 if (!mii_np) {
276 dev_err(eth->dev, "no %s child node found", "mdio-bus");
277 return -ENODEV;
278 }
279
280 if (!of_device_is_available(mii_np)) {
281 err = 0;
282 goto err_put_node;
283 }
284
285 eth->mii_bus = mdiobus_alloc();
286 if (!eth->mii_bus) {
287 err = -ENOMEM;
288 goto err_put_node;
289 }
290
291 eth->mii_bus->name = "mdio";
292 eth->mii_bus->read = mtk_mdio_read;
293 eth->mii_bus->write = mtk_mdio_write;
294 eth->mii_bus->priv = eth;
295 eth->mii_bus->parent = eth->dev;
296
297 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
298 err = of_mdiobus_register(eth->mii_bus, mii_np);
299 if (err)
300 goto err_free_bus;
301
302 return 0;
303
304 err_free_bus:
305 mdiobus_free(eth->mii_bus);
306
307 err_put_node:
308 of_node_put(mii_np);
309 eth->mii_bus = NULL;
310 return err;
311 }
312
313 static void mtk_mdio_cleanup(struct mtk_eth *eth)
314 {
315 if (!eth->mii_bus)
316 return;
317
318 mdiobus_unregister(eth->mii_bus);
319 of_node_put(eth->mii_bus->dev.of_node);
320 mdiobus_free(eth->mii_bus);
321 }
322
323 static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask)
324 {
325 u32 val;
326
327 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
328 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
329 /* flush write */
330 mtk_r32(eth, MTK_QDMA_INT_MASK);
331 }
332
333 static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask)
334 {
335 u32 val;
336
337 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
338 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
339 /* flush write */
340 mtk_r32(eth, MTK_QDMA_INT_MASK);
341 }
342
343 static int mtk_set_mac_address(struct net_device *dev, void *p)
344 {
345 int ret = eth_mac_addr(dev, p);
346 struct mtk_mac *mac = netdev_priv(dev);
347 const char *macaddr = dev->dev_addr;
348 unsigned long flags;
349
350 if (ret)
351 return ret;
352
353 spin_lock_irqsave(&mac->hw->page_lock, flags);
354 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
355 MTK_GDMA_MAC_ADRH(mac->id));
356 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
357 (macaddr[4] << 8) | macaddr[5],
358 MTK_GDMA_MAC_ADRL(mac->id));
359 spin_unlock_irqrestore(&mac->hw->page_lock, flags);
360
361 return 0;
362 }
363
364 void mtk_stats_update_mac(struct mtk_mac *mac)
365 {
366 struct mtk_hw_stats *hw_stats = mac->hw_stats;
367 unsigned int base = MTK_GDM1_TX_GBCNT;
368 u64 stats;
369
370 base += hw_stats->reg_offset;
371
372 u64_stats_update_begin(&hw_stats->syncp);
373
374 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
375 stats = mtk_r32(mac->hw, base + 0x04);
376 if (stats)
377 hw_stats->rx_bytes += (stats << 32);
378 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
379 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
380 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
381 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
382 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
383 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
384 hw_stats->rx_flow_control_packets +=
385 mtk_r32(mac->hw, base + 0x24);
386 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
387 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
388 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
389 stats = mtk_r32(mac->hw, base + 0x34);
390 if (stats)
391 hw_stats->tx_bytes += (stats << 32);
392 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
393 u64_stats_update_end(&hw_stats->syncp);
394 }
395
396 static void mtk_stats_update(struct mtk_eth *eth)
397 {
398 int i;
399
400 for (i = 0; i < MTK_MAC_COUNT; i++) {
401 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
402 continue;
403 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
404 mtk_stats_update_mac(eth->mac[i]);
405 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
406 }
407 }
408 }
409
410 static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
411 struct rtnl_link_stats64 *storage)
412 {
413 struct mtk_mac *mac = netdev_priv(dev);
414 struct mtk_hw_stats *hw_stats = mac->hw_stats;
415 unsigned int start;
416
417 if (netif_running(dev) && netif_device_present(dev)) {
418 if (spin_trylock(&hw_stats->stats_lock)) {
419 mtk_stats_update_mac(mac);
420 spin_unlock(&hw_stats->stats_lock);
421 }
422 }
423
424 do {
425 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
426 storage->rx_packets = hw_stats->rx_packets;
427 storage->tx_packets = hw_stats->tx_packets;
428 storage->rx_bytes = hw_stats->rx_bytes;
429 storage->tx_bytes = hw_stats->tx_bytes;
430 storage->collisions = hw_stats->tx_collisions;
431 storage->rx_length_errors = hw_stats->rx_short_errors +
432 hw_stats->rx_long_errors;
433 storage->rx_over_errors = hw_stats->rx_overflow;
434 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
435 storage->rx_errors = hw_stats->rx_checksum_errors;
436 storage->tx_aborted_errors = hw_stats->tx_skip;
437 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
438
439 storage->tx_errors = dev->stats.tx_errors;
440 storage->rx_dropped = dev->stats.rx_dropped;
441 storage->tx_dropped = dev->stats.tx_dropped;
442
443 return storage;
444 }
445
446 static inline int mtk_max_frag_size(int mtu)
447 {
448 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
449 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
450 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
451
452 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
453 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
454 }
455
456 static inline int mtk_max_buf_size(int frag_size)
457 {
458 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
459 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
460
461 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
462
463 return buf_size;
464 }
465
466 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
467 struct mtk_rx_dma *dma_rxd)
468 {
469 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
470 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
471 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
472 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
473 }
474
475 /* the qdma core needs scratch memory to be setup */
476 static int mtk_init_fq_dma(struct mtk_eth *eth)
477 {
478 dma_addr_t phy_ring_head, phy_ring_tail;
479 int cnt = MTK_DMA_SIZE;
480 dma_addr_t dma_addr;
481 int i;
482
483 eth->scratch_ring = dma_alloc_coherent(eth->dev,
484 cnt * sizeof(struct mtk_tx_dma),
485 &phy_ring_head,
486 GFP_ATOMIC | __GFP_ZERO);
487 if (unlikely(!eth->scratch_ring))
488 return -ENOMEM;
489
490 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
491 GFP_KERNEL);
492 dma_addr = dma_map_single(eth->dev,
493 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
494 DMA_FROM_DEVICE);
495 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
496 return -ENOMEM;
497
498 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
499 phy_ring_tail = phy_ring_head +
500 (sizeof(struct mtk_tx_dma) * (cnt - 1));
501
502 for (i = 0; i < cnt; i++) {
503 eth->scratch_ring[i].txd1 =
504 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
505 if (i < cnt - 1)
506 eth->scratch_ring[i].txd2 = (phy_ring_head +
507 ((i + 1) * sizeof(struct mtk_tx_dma)));
508 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
509 }
510
511 mtk_w32(eth, phy_ring_head, MTK_QDMA_FQ_HEAD);
512 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
513 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
514 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
515
516 return 0;
517 }
518
519 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
520 {
521 void *ret = ring->dma;
522
523 return ret + (desc - ring->phys);
524 }
525
526 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
527 struct mtk_tx_dma *txd)
528 {
529 int idx = txd - ring->dma;
530
531 return &ring->buf[idx];
532 }
533
534 static void mtk_tx_unmap(struct device *dev, struct mtk_tx_buf *tx_buf)
535 {
536 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
537 dma_unmap_single(dev,
538 dma_unmap_addr(tx_buf, dma_addr0),
539 dma_unmap_len(tx_buf, dma_len0),
540 DMA_TO_DEVICE);
541 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
542 dma_unmap_page(dev,
543 dma_unmap_addr(tx_buf, dma_addr0),
544 dma_unmap_len(tx_buf, dma_len0),
545 DMA_TO_DEVICE);
546 }
547 tx_buf->flags = 0;
548 if (tx_buf->skb &&
549 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
550 dev_kfree_skb_any(tx_buf->skb);
551 tx_buf->skb = NULL;
552 }
553
554 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
555 int tx_num, struct mtk_tx_ring *ring, bool gso)
556 {
557 struct mtk_mac *mac = netdev_priv(dev);
558 struct mtk_eth *eth = mac->hw;
559 struct mtk_tx_dma *itxd, *txd;
560 struct mtk_tx_buf *tx_buf;
561 dma_addr_t mapped_addr;
562 unsigned int nr_frags;
563 int i, n_desc = 1;
564 u32 txd4 = 0;
565
566 itxd = ring->next_free;
567 if (itxd == ring->last_free)
568 return -ENOMEM;
569
570 /* set the forward port */
571 txd4 |= (mac->id + 1) << TX_DMA_FPORT_SHIFT;
572
573 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
574 memset(tx_buf, 0, sizeof(*tx_buf));
575
576 if (gso)
577 txd4 |= TX_DMA_TSO;
578
579 /* TX Checksum offload */
580 if (skb->ip_summed == CHECKSUM_PARTIAL)
581 txd4 |= TX_DMA_CHKSUM;
582
583 /* VLAN header offload */
584 if (skb_vlan_tag_present(skb))
585 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
586
587 mapped_addr = dma_map_single(&dev->dev, skb->data,
588 skb_headlen(skb), DMA_TO_DEVICE);
589 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
590 return -ENOMEM;
591
592 WRITE_ONCE(itxd->txd1, mapped_addr);
593 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
594 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
595 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
596
597 /* TX SG offload */
598 txd = itxd;
599 nr_frags = skb_shinfo(skb)->nr_frags;
600 for (i = 0; i < nr_frags; i++) {
601 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
602 unsigned int offset = 0;
603 int frag_size = skb_frag_size(frag);
604
605 while (frag_size) {
606 bool last_frag = false;
607 unsigned int frag_map_size;
608
609 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
610 if (txd == ring->last_free)
611 goto err_dma;
612
613 n_desc++;
614 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
615 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
616 frag_map_size,
617 DMA_TO_DEVICE);
618 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
619 goto err_dma;
620
621 if (i == nr_frags - 1 &&
622 (frag_size - frag_map_size) == 0)
623 last_frag = true;
624
625 WRITE_ONCE(txd->txd1, mapped_addr);
626 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
627 TX_DMA_PLEN0(frag_map_size) |
628 last_frag * TX_DMA_LS0));
629 WRITE_ONCE(txd->txd4, 0);
630
631 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
632 tx_buf = mtk_desc_to_tx_buf(ring, txd);
633 memset(tx_buf, 0, sizeof(*tx_buf));
634
635 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
636 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
637 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
638 frag_size -= frag_map_size;
639 offset += frag_map_size;
640 }
641 }
642
643 /* store skb to cleanup */
644 tx_buf->skb = skb;
645
646 WRITE_ONCE(itxd->txd4, txd4);
647 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
648 (!nr_frags * TX_DMA_LS0)));
649
650 netdev_sent_queue(dev, skb->len);
651 skb_tx_timestamp(skb);
652
653 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
654 atomic_sub(n_desc, &ring->free_count);
655
656 /* make sure that all changes to the dma ring are flushed before we
657 * continue
658 */
659 wmb();
660
661 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
662 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
663
664 return 0;
665
666 err_dma:
667 do {
668 tx_buf = mtk_desc_to_tx_buf(ring, txd);
669
670 /* unmap dma */
671 mtk_tx_unmap(&dev->dev, tx_buf);
672
673 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
674 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
675 } while (itxd != txd);
676
677 return -ENOMEM;
678 }
679
680 static inline int mtk_cal_txd_req(struct sk_buff *skb)
681 {
682 int i, nfrags;
683 struct skb_frag_struct *frag;
684
685 nfrags = 1;
686 if (skb_is_gso(skb)) {
687 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
688 frag = &skb_shinfo(skb)->frags[i];
689 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
690 }
691 } else {
692 nfrags += skb_shinfo(skb)->nr_frags;
693 }
694
695 return nfrags;
696 }
697
698 static void mtk_wake_queue(struct mtk_eth *eth)
699 {
700 int i;
701
702 for (i = 0; i < MTK_MAC_COUNT; i++) {
703 if (!eth->netdev[i])
704 continue;
705 netif_wake_queue(eth->netdev[i]);
706 }
707 }
708
709 static void mtk_stop_queue(struct mtk_eth *eth)
710 {
711 int i;
712
713 for (i = 0; i < MTK_MAC_COUNT; i++) {
714 if (!eth->netdev[i])
715 continue;
716 netif_stop_queue(eth->netdev[i]);
717 }
718 }
719
720 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
721 {
722 struct mtk_mac *mac = netdev_priv(dev);
723 struct mtk_eth *eth = mac->hw;
724 struct mtk_tx_ring *ring = &eth->tx_ring;
725 struct net_device_stats *stats = &dev->stats;
726 unsigned long flags;
727 bool gso = false;
728 int tx_num;
729
730 /* normally we can rely on the stack not calling this more than once,
731 * however we have 2 queues running on the same ring so we need to lock
732 * the ring access
733 */
734 spin_lock_irqsave(&eth->page_lock, flags);
735
736 tx_num = mtk_cal_txd_req(skb);
737 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
738 mtk_stop_queue(eth);
739 netif_err(eth, tx_queued, dev,
740 "Tx Ring full when queue awake!\n");
741 spin_unlock_irqrestore(&eth->page_lock, flags);
742 return NETDEV_TX_BUSY;
743 }
744
745 /* TSO: fill MSS info in tcp checksum field */
746 if (skb_is_gso(skb)) {
747 if (skb_cow_head(skb, 0)) {
748 netif_warn(eth, tx_err, dev,
749 "GSO expand head fail.\n");
750 goto drop;
751 }
752
753 if (skb_shinfo(skb)->gso_type &
754 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
755 gso = true;
756 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
757 }
758 }
759
760 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
761 goto drop;
762
763 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) {
764 mtk_stop_queue(eth);
765 if (unlikely(atomic_read(&ring->free_count) >
766 ring->thresh))
767 mtk_wake_queue(eth);
768 }
769 spin_unlock_irqrestore(&eth->page_lock, flags);
770
771 return NETDEV_TX_OK;
772
773 drop:
774 spin_unlock_irqrestore(&eth->page_lock, flags);
775 stats->tx_dropped++;
776 dev_kfree_skb(skb);
777 return NETDEV_TX_OK;
778 }
779
780 static int mtk_poll_rx(struct napi_struct *napi, int budget,
781 struct mtk_eth *eth, u32 rx_intr)
782 {
783 struct mtk_rx_ring *ring = &eth->rx_ring;
784 int idx = ring->calc_idx;
785 struct sk_buff *skb;
786 u8 *data, *new_data;
787 struct mtk_rx_dma *rxd, trxd;
788 int done = 0;
789
790 while (done < budget) {
791 struct net_device *netdev;
792 unsigned int pktlen;
793 dma_addr_t dma_addr;
794 int mac = 0;
795
796 idx = NEXT_RX_DESP_IDX(idx);
797 rxd = &ring->dma[idx];
798 data = ring->data[idx];
799
800 mtk_rx_get_desc(&trxd, rxd);
801 if (!(trxd.rxd2 & RX_DMA_DONE))
802 break;
803
804 /* find out which mac the packet come from. values start at 1 */
805 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
806 RX_DMA_FPORT_MASK;
807 mac--;
808
809 netdev = eth->netdev[mac];
810
811 /* alloc new buffer */
812 new_data = napi_alloc_frag(ring->frag_size);
813 if (unlikely(!new_data)) {
814 netdev->stats.rx_dropped++;
815 goto release_desc;
816 }
817 dma_addr = dma_map_single(&eth->netdev[mac]->dev,
818 new_data + NET_SKB_PAD,
819 ring->buf_size,
820 DMA_FROM_DEVICE);
821 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
822 skb_free_frag(new_data);
823 goto release_desc;
824 }
825
826 /* receive data */
827 skb = build_skb(data, ring->frag_size);
828 if (unlikely(!skb)) {
829 put_page(virt_to_head_page(new_data));
830 goto release_desc;
831 }
832 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
833
834 dma_unmap_single(&netdev->dev, trxd.rxd1,
835 ring->buf_size, DMA_FROM_DEVICE);
836 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
837 skb->dev = netdev;
838 skb_put(skb, pktlen);
839 if (trxd.rxd4 & RX_DMA_L4_VALID)
840 skb->ip_summed = CHECKSUM_UNNECESSARY;
841 else
842 skb_checksum_none_assert(skb);
843 skb->protocol = eth_type_trans(skb, netdev);
844
845 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
846 RX_DMA_VID(trxd.rxd3))
847 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
848 RX_DMA_VID(trxd.rxd3));
849 napi_gro_receive(napi, skb);
850
851 ring->data[idx] = new_data;
852 rxd->rxd1 = (unsigned int)dma_addr;
853
854 release_desc:
855 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
856
857 ring->calc_idx = idx;
858 /* make sure that all changes to the dma ring are flushed before
859 * we continue
860 */
861 wmb();
862 mtk_w32(eth, ring->calc_idx, MTK_QRX_CRX_IDX0);
863 done++;
864 }
865
866 if (done < budget)
867 mtk_w32(eth, rx_intr, MTK_QMTK_INT_STATUS);
868
869 return done;
870 }
871
872 static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
873 {
874 struct mtk_tx_ring *ring = &eth->tx_ring;
875 struct mtk_tx_dma *desc;
876 struct sk_buff *skb;
877 struct mtk_tx_buf *tx_buf;
878 int total = 0, done[MTK_MAX_DEVS];
879 unsigned int bytes[MTK_MAX_DEVS];
880 u32 cpu, dma;
881 static int condition;
882 int i;
883
884 memset(done, 0, sizeof(done));
885 memset(bytes, 0, sizeof(bytes));
886
887 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
888 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
889
890 desc = mtk_qdma_phys_to_virt(ring, cpu);
891
892 while ((cpu != dma) && budget) {
893 u32 next_cpu = desc->txd2;
894 int mac;
895
896 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
897 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
898 break;
899
900 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
901 TX_DMA_FPORT_MASK;
902 mac--;
903
904 tx_buf = mtk_desc_to_tx_buf(ring, desc);
905 skb = tx_buf->skb;
906 if (!skb) {
907 condition = 1;
908 break;
909 }
910
911 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
912 bytes[mac] += skb->len;
913 done[mac]++;
914 budget--;
915 }
916 mtk_tx_unmap(eth->dev, tx_buf);
917
918 ring->last_free->txd2 = next_cpu;
919 ring->last_free = desc;
920 atomic_inc(&ring->free_count);
921
922 cpu = next_cpu;
923 }
924
925 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
926
927 for (i = 0; i < MTK_MAC_COUNT; i++) {
928 if (!eth->netdev[i] || !done[i])
929 continue;
930 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
931 total += done[i];
932 }
933
934 /* read hw index again make sure no new tx packet */
935 if (cpu != dma || cpu != mtk_r32(eth, MTK_QTX_DRX_PTR))
936 *tx_again = true;
937 else
938 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
939
940 if (!total)
941 return 0;
942
943 if (atomic_read(&ring->free_count) > ring->thresh)
944 mtk_wake_queue(eth);
945
946 return total;
947 }
948
949 static int mtk_poll(struct napi_struct *napi, int budget)
950 {
951 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
952 u32 status, status2, mask, tx_intr, rx_intr, status_intr;
953 int tx_done, rx_done;
954 bool tx_again = false;
955
956 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
957 status2 = mtk_r32(eth, MTK_INT_STATUS2);
958 tx_intr = MTK_TX_DONE_INT;
959 rx_intr = MTK_RX_DONE_INT;
960 status_intr = (MTK_GDM1_AF | MTK_GDM2_AF);
961 tx_done = 0;
962 rx_done = 0;
963 tx_again = 0;
964
965 if (status & tx_intr)
966 tx_done = mtk_poll_tx(eth, budget, &tx_again);
967
968 if (status & rx_intr)
969 rx_done = mtk_poll_rx(napi, budget, eth, rx_intr);
970
971 if (unlikely(status2 & status_intr)) {
972 mtk_stats_update(eth);
973 mtk_w32(eth, status_intr, MTK_INT_STATUS2);
974 }
975
976 if (unlikely(netif_msg_intr(eth))) {
977 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
978 netdev_info(eth->netdev[0],
979 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
980 tx_done, rx_done, status, mask);
981 }
982
983 if (tx_again || rx_done == budget)
984 return budget;
985
986 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
987 if (status & (tx_intr | rx_intr))
988 return budget;
989
990 napi_complete(napi);
991 mtk_irq_enable(eth, tx_intr | rx_intr);
992
993 return rx_done;
994 }
995
996 static int mtk_tx_alloc(struct mtk_eth *eth)
997 {
998 struct mtk_tx_ring *ring = &eth->tx_ring;
999 int i, sz = sizeof(*ring->dma);
1000
1001 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1002 GFP_KERNEL);
1003 if (!ring->buf)
1004 goto no_tx_mem;
1005
1006 ring->dma = dma_alloc_coherent(eth->dev,
1007 MTK_DMA_SIZE * sz,
1008 &ring->phys,
1009 GFP_ATOMIC | __GFP_ZERO);
1010 if (!ring->dma)
1011 goto no_tx_mem;
1012
1013 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
1014 for (i = 0; i < MTK_DMA_SIZE; i++) {
1015 int next = (i + 1) % MTK_DMA_SIZE;
1016 u32 next_ptr = ring->phys + next * sz;
1017
1018 ring->dma[i].txd2 = next_ptr;
1019 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1020 }
1021
1022 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1023 ring->next_free = &ring->dma[0];
1024 ring->last_free = &ring->dma[MTK_DMA_SIZE - 2];
1025 ring->thresh = max((unsigned long)MTK_DMA_SIZE >> 2,
1026 MAX_SKB_FRAGS);
1027
1028 /* make sure that all changes to the dma ring are flushed before we
1029 * continue
1030 */
1031 wmb();
1032
1033 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1034 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1035 mtk_w32(eth,
1036 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1037 MTK_QTX_CRX_PTR);
1038 mtk_w32(eth,
1039 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1040 MTK_QTX_DRX_PTR);
1041
1042 return 0;
1043
1044 no_tx_mem:
1045 return -ENOMEM;
1046 }
1047
1048 static void mtk_tx_clean(struct mtk_eth *eth)
1049 {
1050 struct mtk_tx_ring *ring = &eth->tx_ring;
1051 int i;
1052
1053 if (ring->buf) {
1054 for (i = 0; i < MTK_DMA_SIZE; i++)
1055 mtk_tx_unmap(eth->dev, &ring->buf[i]);
1056 kfree(ring->buf);
1057 ring->buf = NULL;
1058 }
1059
1060 if (ring->dma) {
1061 dma_free_coherent(eth->dev,
1062 MTK_DMA_SIZE * sizeof(*ring->dma),
1063 ring->dma,
1064 ring->phys);
1065 ring->dma = NULL;
1066 }
1067 }
1068
1069 static int mtk_rx_alloc(struct mtk_eth *eth)
1070 {
1071 struct mtk_rx_ring *ring = &eth->rx_ring;
1072 int i;
1073
1074 ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN);
1075 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1076 ring->data = kcalloc(MTK_DMA_SIZE, sizeof(*ring->data),
1077 GFP_KERNEL);
1078 if (!ring->data)
1079 return -ENOMEM;
1080
1081 for (i = 0; i < MTK_DMA_SIZE; i++) {
1082 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1083 if (!ring->data[i])
1084 return -ENOMEM;
1085 }
1086
1087 ring->dma = dma_alloc_coherent(eth->dev,
1088 MTK_DMA_SIZE * sizeof(*ring->dma),
1089 &ring->phys,
1090 GFP_ATOMIC | __GFP_ZERO);
1091 if (!ring->dma)
1092 return -ENOMEM;
1093
1094 for (i = 0; i < MTK_DMA_SIZE; i++) {
1095 dma_addr_t dma_addr = dma_map_single(eth->dev,
1096 ring->data[i] + NET_SKB_PAD,
1097 ring->buf_size,
1098 DMA_FROM_DEVICE);
1099 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1100 return -ENOMEM;
1101 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1102
1103 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1104 }
1105 ring->calc_idx = MTK_DMA_SIZE - 1;
1106 /* make sure that all changes to the dma ring are flushed before we
1107 * continue
1108 */
1109 wmb();
1110
1111 mtk_w32(eth, eth->rx_ring.phys, MTK_QRX_BASE_PTR0);
1112 mtk_w32(eth, MTK_DMA_SIZE, MTK_QRX_MAX_CNT0);
1113 mtk_w32(eth, eth->rx_ring.calc_idx, MTK_QRX_CRX_IDX0);
1114 mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_QDMA_RST_IDX);
1115 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1116
1117 return 0;
1118 }
1119
1120 static void mtk_rx_clean(struct mtk_eth *eth)
1121 {
1122 struct mtk_rx_ring *ring = &eth->rx_ring;
1123 int i;
1124
1125 if (ring->data && ring->dma) {
1126 for (i = 0; i < MTK_DMA_SIZE; i++) {
1127 if (!ring->data[i])
1128 continue;
1129 if (!ring->dma[i].rxd1)
1130 continue;
1131 dma_unmap_single(eth->dev,
1132 ring->dma[i].rxd1,
1133 ring->buf_size,
1134 DMA_FROM_DEVICE);
1135 skb_free_frag(ring->data[i]);
1136 }
1137 kfree(ring->data);
1138 ring->data = NULL;
1139 }
1140
1141 if (ring->dma) {
1142 dma_free_coherent(eth->dev,
1143 MTK_DMA_SIZE * sizeof(*ring->dma),
1144 ring->dma,
1145 ring->phys);
1146 ring->dma = NULL;
1147 }
1148 }
1149
1150 /* wait for DMA to finish whatever it is doing before we start using it again */
1151 static int mtk_dma_busy_wait(struct mtk_eth *eth)
1152 {
1153 unsigned long t_start = jiffies;
1154
1155 while (1) {
1156 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1157 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1158 return 0;
1159 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1160 break;
1161 }
1162
1163 dev_err(eth->dev, "DMA init timeout\n");
1164 return -1;
1165 }
1166
1167 static int mtk_dma_init(struct mtk_eth *eth)
1168 {
1169 int err;
1170
1171 if (mtk_dma_busy_wait(eth))
1172 return -EBUSY;
1173
1174 /* QDMA needs scratch memory for internal reordering of the
1175 * descriptors
1176 */
1177 err = mtk_init_fq_dma(eth);
1178 if (err)
1179 return err;
1180
1181 err = mtk_tx_alloc(eth);
1182 if (err)
1183 return err;
1184
1185 err = mtk_rx_alloc(eth);
1186 if (err)
1187 return err;
1188
1189 /* Enable random early drop and set drop threshold automatically */
1190 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1191 MTK_QDMA_FC_THRES);
1192 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1193
1194 return 0;
1195 }
1196
1197 static void mtk_dma_free(struct mtk_eth *eth)
1198 {
1199 int i;
1200
1201 for (i = 0; i < MTK_MAC_COUNT; i++)
1202 if (eth->netdev[i])
1203 netdev_reset_queue(eth->netdev[i]);
1204 mtk_tx_clean(eth);
1205 mtk_rx_clean(eth);
1206 kfree(eth->scratch_head);
1207 }
1208
1209 static void mtk_tx_timeout(struct net_device *dev)
1210 {
1211 struct mtk_mac *mac = netdev_priv(dev);
1212 struct mtk_eth *eth = mac->hw;
1213
1214 eth->netdev[mac->id]->stats.tx_errors++;
1215 netif_err(eth, tx_err, dev,
1216 "transmit timed out\n");
1217 schedule_work(&eth->pending_work);
1218 }
1219
1220 static irqreturn_t mtk_handle_irq(int irq, void *_eth)
1221 {
1222 struct mtk_eth *eth = _eth;
1223 u32 status;
1224
1225 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1226 if (unlikely(!status))
1227 return IRQ_NONE;
1228
1229 if (likely(status & (MTK_RX_DONE_INT | MTK_TX_DONE_INT))) {
1230 if (likely(napi_schedule_prep(&eth->rx_napi)))
1231 __napi_schedule(&eth->rx_napi);
1232 } else {
1233 mtk_w32(eth, status, MTK_QMTK_INT_STATUS);
1234 }
1235 mtk_irq_disable(eth, (MTK_RX_DONE_INT | MTK_TX_DONE_INT));
1236
1237 return IRQ_HANDLED;
1238 }
1239
1240 #ifdef CONFIG_NET_POLL_CONTROLLER
1241 static void mtk_poll_controller(struct net_device *dev)
1242 {
1243 struct mtk_mac *mac = netdev_priv(dev);
1244 struct mtk_eth *eth = mac->hw;
1245 u32 int_mask = MTK_TX_DONE_INT | MTK_RX_DONE_INT;
1246
1247 mtk_irq_disable(eth, int_mask);
1248 mtk_handle_irq(dev->irq, dev);
1249 mtk_irq_enable(eth, int_mask);
1250 }
1251 #endif
1252
1253 static int mtk_start_dma(struct mtk_eth *eth)
1254 {
1255 int err;
1256
1257 err = mtk_dma_init(eth);
1258 if (err) {
1259 mtk_dma_free(eth);
1260 return err;
1261 }
1262
1263 mtk_w32(eth,
1264 MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN |
1265 MTK_RX_2B_OFFSET | MTK_DMA_SIZE_16DWORDS |
1266 MTK_RX_BT_32DWORDS,
1267 MTK_QDMA_GLO_CFG);
1268
1269 return 0;
1270 }
1271
1272 static int mtk_open(struct net_device *dev)
1273 {
1274 struct mtk_mac *mac = netdev_priv(dev);
1275 struct mtk_eth *eth = mac->hw;
1276
1277 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1278 if (!atomic_read(&eth->dma_refcnt)) {
1279 int err = mtk_start_dma(eth);
1280
1281 if (err)
1282 return err;
1283
1284 napi_enable(&eth->rx_napi);
1285 mtk_irq_enable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1286 }
1287 atomic_inc(&eth->dma_refcnt);
1288
1289 phy_start(mac->phy_dev);
1290 netif_start_queue(dev);
1291
1292 return 0;
1293 }
1294
1295 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1296 {
1297 unsigned long flags;
1298 u32 val;
1299 int i;
1300
1301 /* stop the dma engine */
1302 spin_lock_irqsave(&eth->page_lock, flags);
1303 val = mtk_r32(eth, glo_cfg);
1304 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1305 glo_cfg);
1306 spin_unlock_irqrestore(&eth->page_lock, flags);
1307
1308 /* wait for dma stop */
1309 for (i = 0; i < 10; i++) {
1310 val = mtk_r32(eth, glo_cfg);
1311 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1312 msleep(20);
1313 continue;
1314 }
1315 break;
1316 }
1317 }
1318
1319 static int mtk_stop(struct net_device *dev)
1320 {
1321 struct mtk_mac *mac = netdev_priv(dev);
1322 struct mtk_eth *eth = mac->hw;
1323
1324 netif_tx_disable(dev);
1325 phy_stop(mac->phy_dev);
1326
1327 /* only shutdown DMA if this is the last user */
1328 if (!atomic_dec_and_test(&eth->dma_refcnt))
1329 return 0;
1330
1331 mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1332 napi_disable(&eth->rx_napi);
1333
1334 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1335
1336 mtk_dma_free(eth);
1337
1338 return 0;
1339 }
1340
1341 static int __init mtk_hw_init(struct mtk_eth *eth)
1342 {
1343 int err, i;
1344
1345 /* reset the frame engine */
1346 reset_control_assert(eth->rstc);
1347 usleep_range(10, 20);
1348 reset_control_deassert(eth->rstc);
1349 usleep_range(10, 20);
1350
1351 /* Set GE2 driving and slew rate */
1352 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1353
1354 /* set GE2 TDSEL */
1355 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1356
1357 /* set GE2 TUNE */
1358 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1359
1360 /* GE1, Force 1000M/FD, FC ON */
1361 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1362
1363 /* GE2, Force 1000M/FD, FC ON */
1364 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1365
1366 /* Enable RX VLan Offloading */
1367 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1368
1369 err = devm_request_irq(eth->dev, eth->irq, mtk_handle_irq, 0,
1370 dev_name(eth->dev), eth);
1371 if (err)
1372 return err;
1373
1374 err = mtk_mdio_init(eth);
1375 if (err)
1376 return err;
1377
1378 /* disable delay and normal interrupt */
1379 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
1380 mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1381 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1382 mtk_w32(eth, 0, MTK_RST_GL);
1383
1384 /* FE int grouping */
1385 mtk_w32(eth, 0, MTK_FE_INT_GRP);
1386
1387 for (i = 0; i < 2; i++) {
1388 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1389
1390 /* setup the forward port to send frame to QDMA */
1391 val &= ~0xffff;
1392 val |= 0x5555;
1393
1394 /* Enable RX checksum */
1395 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1396
1397 /* setup the mac dma */
1398 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1399 }
1400
1401 return 0;
1402 }
1403
1404 static int __init mtk_init(struct net_device *dev)
1405 {
1406 struct mtk_mac *mac = netdev_priv(dev);
1407 struct mtk_eth *eth = mac->hw;
1408 const char *mac_addr;
1409
1410 mac_addr = of_get_mac_address(mac->of_node);
1411 if (mac_addr)
1412 ether_addr_copy(dev->dev_addr, mac_addr);
1413
1414 /* If the mac address is invalid, use random mac address */
1415 if (!is_valid_ether_addr(dev->dev_addr)) {
1416 random_ether_addr(dev->dev_addr);
1417 dev_err(eth->dev, "generated random MAC address %pM\n",
1418 dev->dev_addr);
1419 dev->addr_assign_type = NET_ADDR_RANDOM;
1420 }
1421
1422 return mtk_phy_connect(mac);
1423 }
1424
1425 static void mtk_uninit(struct net_device *dev)
1426 {
1427 struct mtk_mac *mac = netdev_priv(dev);
1428 struct mtk_eth *eth = mac->hw;
1429
1430 phy_disconnect(mac->phy_dev);
1431 mtk_mdio_cleanup(eth);
1432 mtk_irq_disable(eth, ~0);
1433 free_irq(dev->irq, dev);
1434 }
1435
1436 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1437 {
1438 struct mtk_mac *mac = netdev_priv(dev);
1439
1440 switch (cmd) {
1441 case SIOCGMIIPHY:
1442 case SIOCGMIIREG:
1443 case SIOCSMIIREG:
1444 return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
1445 default:
1446 break;
1447 }
1448
1449 return -EOPNOTSUPP;
1450 }
1451
1452 static void mtk_pending_work(struct work_struct *work)
1453 {
1454 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
1455 int err, i;
1456 unsigned long restart = 0;
1457
1458 rtnl_lock();
1459
1460 /* stop all devices to make sure that dma is properly shut down */
1461 for (i = 0; i < MTK_MAC_COUNT; i++) {
1462 if (!eth->netdev[i])
1463 continue;
1464 mtk_stop(eth->netdev[i]);
1465 __set_bit(i, &restart);
1466 }
1467
1468 /* restart DMA and enable IRQs */
1469 for (i = 0; i < MTK_MAC_COUNT; i++) {
1470 if (!test_bit(i, &restart))
1471 continue;
1472 err = mtk_open(eth->netdev[i]);
1473 if (err) {
1474 netif_alert(eth, ifup, eth->netdev[i],
1475 "Driver up/down cycle failed, closing device.\n");
1476 dev_close(eth->netdev[i]);
1477 }
1478 }
1479 rtnl_unlock();
1480 }
1481
1482 static int mtk_cleanup(struct mtk_eth *eth)
1483 {
1484 int i;
1485
1486 for (i = 0; i < MTK_MAC_COUNT; i++) {
1487 if (!eth->netdev[i])
1488 continue;
1489
1490 unregister_netdev(eth->netdev[i]);
1491 free_netdev(eth->netdev[i]);
1492 }
1493 cancel_work_sync(&eth->pending_work);
1494
1495 return 0;
1496 }
1497
1498 static int mtk_get_settings(struct net_device *dev,
1499 struct ethtool_cmd *cmd)
1500 {
1501 struct mtk_mac *mac = netdev_priv(dev);
1502 int err;
1503
1504 err = phy_read_status(mac->phy_dev);
1505 if (err)
1506 return -ENODEV;
1507
1508 return phy_ethtool_gset(mac->phy_dev, cmd);
1509 }
1510
1511 static int mtk_set_settings(struct net_device *dev,
1512 struct ethtool_cmd *cmd)
1513 {
1514 struct mtk_mac *mac = netdev_priv(dev);
1515
1516 if (cmd->phy_address != mac->phy_dev->mdio.addr) {
1517 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
1518 cmd->phy_address);
1519 if (!mac->phy_dev)
1520 return -ENODEV;
1521 }
1522
1523 return phy_ethtool_sset(mac->phy_dev, cmd);
1524 }
1525
1526 static void mtk_get_drvinfo(struct net_device *dev,
1527 struct ethtool_drvinfo *info)
1528 {
1529 struct mtk_mac *mac = netdev_priv(dev);
1530
1531 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
1532 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
1533 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
1534 }
1535
1536 static u32 mtk_get_msglevel(struct net_device *dev)
1537 {
1538 struct mtk_mac *mac = netdev_priv(dev);
1539
1540 return mac->hw->msg_enable;
1541 }
1542
1543 static void mtk_set_msglevel(struct net_device *dev, u32 value)
1544 {
1545 struct mtk_mac *mac = netdev_priv(dev);
1546
1547 mac->hw->msg_enable = value;
1548 }
1549
1550 static int mtk_nway_reset(struct net_device *dev)
1551 {
1552 struct mtk_mac *mac = netdev_priv(dev);
1553
1554 return genphy_restart_aneg(mac->phy_dev);
1555 }
1556
1557 static u32 mtk_get_link(struct net_device *dev)
1558 {
1559 struct mtk_mac *mac = netdev_priv(dev);
1560 int err;
1561
1562 err = genphy_update_link(mac->phy_dev);
1563 if (err)
1564 return ethtool_op_get_link(dev);
1565
1566 return mac->phy_dev->link;
1567 }
1568
1569 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1570 {
1571 int i;
1572
1573 switch (stringset) {
1574 case ETH_SS_STATS:
1575 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
1576 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
1577 data += ETH_GSTRING_LEN;
1578 }
1579 break;
1580 }
1581 }
1582
1583 static int mtk_get_sset_count(struct net_device *dev, int sset)
1584 {
1585 switch (sset) {
1586 case ETH_SS_STATS:
1587 return ARRAY_SIZE(mtk_ethtool_stats);
1588 default:
1589 return -EOPNOTSUPP;
1590 }
1591 }
1592
1593 static void mtk_get_ethtool_stats(struct net_device *dev,
1594 struct ethtool_stats *stats, u64 *data)
1595 {
1596 struct mtk_mac *mac = netdev_priv(dev);
1597 struct mtk_hw_stats *hwstats = mac->hw_stats;
1598 u64 *data_src, *data_dst;
1599 unsigned int start;
1600 int i;
1601
1602 if (netif_running(dev) && netif_device_present(dev)) {
1603 if (spin_trylock(&hwstats->stats_lock)) {
1604 mtk_stats_update_mac(mac);
1605 spin_unlock(&hwstats->stats_lock);
1606 }
1607 }
1608
1609 do {
1610 data_src = (u64*)hwstats;
1611 data_dst = data;
1612 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
1613
1614 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
1615 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
1616 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
1617 }
1618
1619 static struct ethtool_ops mtk_ethtool_ops = {
1620 .get_settings = mtk_get_settings,
1621 .set_settings = mtk_set_settings,
1622 .get_drvinfo = mtk_get_drvinfo,
1623 .get_msglevel = mtk_get_msglevel,
1624 .set_msglevel = mtk_set_msglevel,
1625 .nway_reset = mtk_nway_reset,
1626 .get_link = mtk_get_link,
1627 .get_strings = mtk_get_strings,
1628 .get_sset_count = mtk_get_sset_count,
1629 .get_ethtool_stats = mtk_get_ethtool_stats,
1630 };
1631
1632 static const struct net_device_ops mtk_netdev_ops = {
1633 .ndo_init = mtk_init,
1634 .ndo_uninit = mtk_uninit,
1635 .ndo_open = mtk_open,
1636 .ndo_stop = mtk_stop,
1637 .ndo_start_xmit = mtk_start_xmit,
1638 .ndo_set_mac_address = mtk_set_mac_address,
1639 .ndo_validate_addr = eth_validate_addr,
1640 .ndo_do_ioctl = mtk_do_ioctl,
1641 .ndo_change_mtu = eth_change_mtu,
1642 .ndo_tx_timeout = mtk_tx_timeout,
1643 .ndo_get_stats64 = mtk_get_stats64,
1644 #ifdef CONFIG_NET_POLL_CONTROLLER
1645 .ndo_poll_controller = mtk_poll_controller,
1646 #endif
1647 };
1648
1649 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
1650 {
1651 struct mtk_mac *mac;
1652 const __be32 *_id = of_get_property(np, "reg", NULL);
1653 int id, err;
1654
1655 if (!_id) {
1656 dev_err(eth->dev, "missing mac id\n");
1657 return -EINVAL;
1658 }
1659
1660 id = be32_to_cpup(_id);
1661 if (id >= MTK_MAC_COUNT) {
1662 dev_err(eth->dev, "%d is not a valid mac id\n", id);
1663 return -EINVAL;
1664 }
1665
1666 if (eth->netdev[id]) {
1667 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
1668 return -EINVAL;
1669 }
1670
1671 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
1672 if (!eth->netdev[id]) {
1673 dev_err(eth->dev, "alloc_etherdev failed\n");
1674 return -ENOMEM;
1675 }
1676 mac = netdev_priv(eth->netdev[id]);
1677 eth->mac[id] = mac;
1678 mac->id = id;
1679 mac->hw = eth;
1680 mac->of_node = np;
1681
1682 mac->hw_stats = devm_kzalloc(eth->dev,
1683 sizeof(*mac->hw_stats),
1684 GFP_KERNEL);
1685 if (!mac->hw_stats) {
1686 dev_err(eth->dev, "failed to allocate counter memory\n");
1687 err = -ENOMEM;
1688 goto free_netdev;
1689 }
1690 spin_lock_init(&mac->hw_stats->stats_lock);
1691 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
1692
1693 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
1694 eth->netdev[id]->watchdog_timeo = HZ;
1695 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
1696 eth->netdev[id]->base_addr = (unsigned long)eth->base;
1697 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
1698 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1699 eth->netdev[id]->features |= MTK_HW_FEATURES;
1700 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
1701
1702 err = register_netdev(eth->netdev[id]);
1703 if (err) {
1704 dev_err(eth->dev, "error bringing up device\n");
1705 goto free_netdev;
1706 }
1707 eth->netdev[id]->irq = eth->irq;
1708 netif_info(eth, probe, eth->netdev[id],
1709 "mediatek frame engine at 0x%08lx, irq %d\n",
1710 eth->netdev[id]->base_addr, eth->netdev[id]->irq);
1711
1712 return 0;
1713
1714 free_netdev:
1715 free_netdev(eth->netdev[id]);
1716 return err;
1717 }
1718
1719 static int mtk_probe(struct platform_device *pdev)
1720 {
1721 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1722 struct device_node *mac_np;
1723 const struct of_device_id *match;
1724 struct mtk_soc_data *soc;
1725 struct mtk_eth *eth;
1726 int err;
1727
1728 match = of_match_device(of_mtk_match, &pdev->dev);
1729 soc = (struct mtk_soc_data *)match->data;
1730
1731 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
1732 if (!eth)
1733 return -ENOMEM;
1734
1735 eth->base = devm_ioremap_resource(&pdev->dev, res);
1736 if (IS_ERR(eth->base))
1737 return PTR_ERR(eth->base);
1738
1739 spin_lock_init(&eth->page_lock);
1740
1741 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1742 "mediatek,ethsys");
1743 if (IS_ERR(eth->ethsys)) {
1744 dev_err(&pdev->dev, "no ethsys regmap found\n");
1745 return PTR_ERR(eth->ethsys);
1746 }
1747
1748 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1749 "mediatek,pctl");
1750 if (IS_ERR(eth->pctl)) {
1751 dev_err(&pdev->dev, "no pctl regmap found\n");
1752 return PTR_ERR(eth->pctl);
1753 }
1754
1755 eth->rstc = devm_reset_control_get(&pdev->dev, "eth");
1756 if (IS_ERR(eth->rstc)) {
1757 dev_err(&pdev->dev, "no eth reset found\n");
1758 return PTR_ERR(eth->rstc);
1759 }
1760
1761 eth->irq = platform_get_irq(pdev, 0);
1762 if (eth->irq < 0) {
1763 dev_err(&pdev->dev, "no IRQ resource found\n");
1764 return -ENXIO;
1765 }
1766
1767 eth->clk_ethif = devm_clk_get(&pdev->dev, "ethif");
1768 eth->clk_esw = devm_clk_get(&pdev->dev, "esw");
1769 eth->clk_gp1 = devm_clk_get(&pdev->dev, "gp1");
1770 eth->clk_gp2 = devm_clk_get(&pdev->dev, "gp2");
1771 if (IS_ERR(eth->clk_esw) || IS_ERR(eth->clk_gp1) ||
1772 IS_ERR(eth->clk_gp2) || IS_ERR(eth->clk_ethif))
1773 return -ENODEV;
1774
1775 clk_prepare_enable(eth->clk_ethif);
1776 clk_prepare_enable(eth->clk_esw);
1777 clk_prepare_enable(eth->clk_gp1);
1778 clk_prepare_enable(eth->clk_gp2);
1779
1780 eth->dev = &pdev->dev;
1781 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
1782 INIT_WORK(&eth->pending_work, mtk_pending_work);
1783
1784 err = mtk_hw_init(eth);
1785 if (err)
1786 return err;
1787
1788 for_each_child_of_node(pdev->dev.of_node, mac_np) {
1789 if (!of_device_is_compatible(mac_np,
1790 "mediatek,eth-mac"))
1791 continue;
1792
1793 if (!of_device_is_available(mac_np))
1794 continue;
1795
1796 err = mtk_add_mac(eth, mac_np);
1797 if (err)
1798 goto err_free_dev;
1799 }
1800
1801 /* we run 2 devices on the same DMA ring so we need a dummy device
1802 * for NAPI to work
1803 */
1804 init_dummy_netdev(&eth->dummy_dev);
1805 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_poll,
1806 MTK_NAPI_WEIGHT);
1807
1808 platform_set_drvdata(pdev, eth);
1809
1810 return 0;
1811
1812 err_free_dev:
1813 mtk_cleanup(eth);
1814 return err;
1815 }
1816
1817 static int mtk_remove(struct platform_device *pdev)
1818 {
1819 struct mtk_eth *eth = platform_get_drvdata(pdev);
1820
1821 clk_disable_unprepare(eth->clk_ethif);
1822 clk_disable_unprepare(eth->clk_esw);
1823 clk_disable_unprepare(eth->clk_gp1);
1824 clk_disable_unprepare(eth->clk_gp2);
1825
1826 netif_napi_del(&eth->rx_napi);
1827 mtk_cleanup(eth);
1828 platform_set_drvdata(pdev, NULL);
1829
1830 return 0;
1831 }
1832
1833 const struct of_device_id of_mtk_match[] = {
1834 { .compatible = "mediatek,mt7623-eth" },
1835 {},
1836 };
1837
1838 static struct platform_driver mtk_driver = {
1839 .probe = mtk_probe,
1840 .remove = mtk_remove,
1841 .driver = {
1842 .name = "mtk_soc_eth",
1843 .owner = THIS_MODULE,
1844 .of_match_table = of_mtk_match,
1845 },
1846 };
1847
1848 module_platform_driver(mtk_driver);
1849
1850 MODULE_LICENSE("GPL");
1851 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1852 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
Linux kernel - Deliverables
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