projects / deliverable / linux.git / blob
? search:


d6c3a17a0d5c16715a1094a6559a40cdcd88d417
[deliverable/linux.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15 #include <linux/of_device.h>
16 #include <linux/of_mdio.h>
17 #include <linux/of_net.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
20 #include <linux/clk.h>
21 #include <linux/if_vlan.h>
22 #include <linux/reset.h>
23 #include <linux/tcp.h>
24
25 #include "mtk_eth_soc.h"
26
27 static int mtk_msg_level = -1;
28 module_param_named(msg_level, mtk_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 #define MTK_ETHTOOL_STAT(x) { #x, \
32 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
33
34 /* strings used by ethtool */
35 static const struct mtk_ethtool_stats {
36 char str[ETH_GSTRING_LEN];
37 u32 offset;
38 } mtk_ethtool_stats[] = {
39 MTK_ETHTOOL_STAT(tx_bytes),
40 MTK_ETHTOOL_STAT(tx_packets),
41 MTK_ETHTOOL_STAT(tx_skip),
42 MTK_ETHTOOL_STAT(tx_collisions),
43 MTK_ETHTOOL_STAT(rx_bytes),
44 MTK_ETHTOOL_STAT(rx_packets),
45 MTK_ETHTOOL_STAT(rx_overflow),
46 MTK_ETHTOOL_STAT(rx_fcs_errors),
47 MTK_ETHTOOL_STAT(rx_short_errors),
48 MTK_ETHTOOL_STAT(rx_long_errors),
49 MTK_ETHTOOL_STAT(rx_checksum_errors),
50 MTK_ETHTOOL_STAT(rx_flow_control_packets),
51 };
52
53 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
54 {
55 __raw_writel(val, eth->base + reg);
56 }
57
58 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
59 {
60 return __raw_readl(eth->base + reg);
61 }
62
63 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
64 {
65 unsigned long t_start = jiffies;
66
67 while (1) {
68 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
69 return 0;
70 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
71 break;
72 usleep_range(10, 20);
73 }
74
75 dev_err(eth->dev, "mdio: MDIO timeout\n");
76 return -1;
77 }
78
79 u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
80 u32 phy_register, u32 write_data)
81 {
82 if (mtk_mdio_busy_wait(eth))
83 return -1;
84
85 write_data &= 0xffff;
86
87 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
88 (phy_register << PHY_IAC_REG_SHIFT) |
89 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
90 MTK_PHY_IAC);
91
92 if (mtk_mdio_busy_wait(eth))
93 return -1;
94
95 return 0;
96 }
97
98 u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
99 {
100 u32 d;
101
102 if (mtk_mdio_busy_wait(eth))
103 return 0xffff;
104
105 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
106 (phy_reg << PHY_IAC_REG_SHIFT) |
107 (phy_addr << PHY_IAC_ADDR_SHIFT),
108 MTK_PHY_IAC);
109
110 if (mtk_mdio_busy_wait(eth))
111 return 0xffff;
112
113 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
114
115 return d;
116 }
117
118 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
119 int phy_reg, u16 val)
120 {
121 struct mtk_eth *eth = bus->priv;
122
123 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
124 }
125
126 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
127 {
128 struct mtk_eth *eth = bus->priv;
129
130 return _mtk_mdio_read(eth, phy_addr, phy_reg);
131 }
132
133 static void mtk_phy_link_adjust(struct net_device *dev)
134 {
135 struct mtk_mac *mac = netdev_priv(dev);
136 u16 lcl_adv = 0, rmt_adv = 0;
137 u8 flowctrl;
138 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
139 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
140 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
141 MAC_MCR_BACKPR_EN;
142
143 switch (mac->phy_dev->speed) {
144 case SPEED_1000:
145 mcr |= MAC_MCR_SPEED_1000;
146 break;
147 case SPEED_100:
148 mcr |= MAC_MCR_SPEED_100;
149 break;
150 };
151
152 if (mac->phy_dev->link)
153 mcr |= MAC_MCR_FORCE_LINK;
154
155 if (mac->phy_dev->duplex) {
156 mcr |= MAC_MCR_FORCE_DPX;
157
158 if (mac->phy_dev->pause)
159 rmt_adv = LPA_PAUSE_CAP;
160 if (mac->phy_dev->asym_pause)
161 rmt_adv |= LPA_PAUSE_ASYM;
162
163 if (mac->phy_dev->advertising & ADVERTISED_Pause)
164 lcl_adv |= ADVERTISE_PAUSE_CAP;
165 if (mac->phy_dev->advertising & ADVERTISED_Asym_Pause)
166 lcl_adv |= ADVERTISE_PAUSE_ASYM;
167
168 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
169
170 if (flowctrl & FLOW_CTRL_TX)
171 mcr |= MAC_MCR_FORCE_TX_FC;
172 if (flowctrl & FLOW_CTRL_RX)
173 mcr |= MAC_MCR_FORCE_RX_FC;
174
175 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
176 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
177 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
178 }
179
180 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
181
182 if (mac->phy_dev->link)
183 netif_carrier_on(dev);
184 else
185 netif_carrier_off(dev);
186 }
187
188 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
189 struct device_node *phy_node)
190 {
191 const __be32 *_addr = NULL;
192 struct phy_device *phydev;
193 int phy_mode, addr;
194
195 _addr = of_get_property(phy_node, "reg", NULL);
196
197 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) {
198 pr_err("%s: invalid phy address\n", phy_node->name);
199 return -EINVAL;
200 }
201 addr = be32_to_cpu(*_addr);
202 phy_mode = of_get_phy_mode(phy_node);
203 if (phy_mode < 0) {
204 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
205 return -EINVAL;
206 }
207
208 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
209 mtk_phy_link_adjust, 0, phy_mode);
210 if (!phydev) {
211 dev_err(eth->dev, "could not connect to PHY\n");
212 return -ENODEV;
213 }
214
215 dev_info(eth->dev,
216 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
217 mac->id, phydev_name(phydev), phydev->phy_id,
218 phydev->drv->name);
219
220 mac->phy_dev = phydev;
221
222 return 0;
223 }
224
225 static int mtk_phy_connect(struct mtk_mac *mac)
226 {
227 struct mtk_eth *eth = mac->hw;
228 struct device_node *np;
229 u32 val, ge_mode;
230
231 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
232 if (!np && of_phy_is_fixed_link(mac->of_node))
233 if (!of_phy_register_fixed_link(mac->of_node))
234 np = of_node_get(mac->of_node);
235 if (!np)
236 return -ENODEV;
237
238 switch (of_get_phy_mode(np)) {
239 case PHY_INTERFACE_MODE_RGMII_TXID:
240 case PHY_INTERFACE_MODE_RGMII_RXID:
241 case PHY_INTERFACE_MODE_RGMII_ID:
242 case PHY_INTERFACE_MODE_RGMII:
243 ge_mode = 0;
244 break;
245 case PHY_INTERFACE_MODE_MII:
246 ge_mode = 1;
247 break;
248 case PHY_INTERFACE_MODE_RMII:
249 ge_mode = 2;
250 break;
251 default:
252 dev_err(eth->dev, "invalid phy_mode\n");
253 return -1;
254 }
255
256 /* put the gmac into the right mode */
257 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
258 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
259 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
260 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
261
262 mtk_phy_connect_node(eth, mac, np);
263 mac->phy_dev->autoneg = AUTONEG_ENABLE;
264 mac->phy_dev->speed = 0;
265 mac->phy_dev->duplex = 0;
266 mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
267 SUPPORTED_Asym_Pause;
268 mac->phy_dev->advertising = mac->phy_dev->supported |
269 ADVERTISED_Autoneg;
270 phy_start_aneg(mac->phy_dev);
271
272 return 0;
273 }
274
275 static int mtk_mdio_init(struct mtk_eth *eth)
276 {
277 struct device_node *mii_np;
278 int err;
279
280 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
281 if (!mii_np) {
282 dev_err(eth->dev, "no %s child node found", "mdio-bus");
283 return -ENODEV;
284 }
285
286 if (!of_device_is_available(mii_np)) {
287 err = 0;
288 goto err_put_node;
289 }
290
291 eth->mii_bus = mdiobus_alloc();
292 if (!eth->mii_bus) {
293 err = -ENOMEM;
294 goto err_put_node;
295 }
296
297 eth->mii_bus->name = "mdio";
298 eth->mii_bus->read = mtk_mdio_read;
299 eth->mii_bus->write = mtk_mdio_write;
300 eth->mii_bus->priv = eth;
301 eth->mii_bus->parent = eth->dev;
302
303 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
304 err = of_mdiobus_register(eth->mii_bus, mii_np);
305 if (err)
306 goto err_free_bus;
307
308 return 0;
309
310 err_free_bus:
311 mdiobus_free(eth->mii_bus);
312
313 err_put_node:
314 of_node_put(mii_np);
315 eth->mii_bus = NULL;
316 return err;
317 }
318
319 static void mtk_mdio_cleanup(struct mtk_eth *eth)
320 {
321 if (!eth->mii_bus)
322 return;
323
324 mdiobus_unregister(eth->mii_bus);
325 of_node_put(eth->mii_bus->dev.of_node);
326 mdiobus_free(eth->mii_bus);
327 }
328
329 static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask)
330 {
331 u32 val;
332
333 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
334 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
335 }
336
337 static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask)
338 {
339 u32 val;
340
341 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
342 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
343 }
344
345 static int mtk_set_mac_address(struct net_device *dev, void *p)
346 {
347 int ret = eth_mac_addr(dev, p);
348 struct mtk_mac *mac = netdev_priv(dev);
349 const char *macaddr = dev->dev_addr;
350 unsigned long flags;
351
352 if (ret)
353 return ret;
354
355 spin_lock_irqsave(&mac->hw->page_lock, flags);
356 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
357 MTK_GDMA_MAC_ADRH(mac->id));
358 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
359 (macaddr[4] << 8) | macaddr[5],
360 MTK_GDMA_MAC_ADRL(mac->id));
361 spin_unlock_irqrestore(&mac->hw->page_lock, flags);
362
363 return 0;
364 }
365
366 void mtk_stats_update_mac(struct mtk_mac *mac)
367 {
368 struct mtk_hw_stats *hw_stats = mac->hw_stats;
369 unsigned int base = MTK_GDM1_TX_GBCNT;
370 u64 stats;
371
372 base += hw_stats->reg_offset;
373
374 u64_stats_update_begin(&hw_stats->syncp);
375
376 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
377 stats = mtk_r32(mac->hw, base + 0x04);
378 if (stats)
379 hw_stats->rx_bytes += (stats << 32);
380 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
381 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
382 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
383 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
384 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
385 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
386 hw_stats->rx_flow_control_packets +=
387 mtk_r32(mac->hw, base + 0x24);
388 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
389 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
390 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
391 stats = mtk_r32(mac->hw, base + 0x34);
392 if (stats)
393 hw_stats->tx_bytes += (stats << 32);
394 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
395 u64_stats_update_end(&hw_stats->syncp);
396 }
397
398 static void mtk_stats_update(struct mtk_eth *eth)
399 {
400 int i;
401
402 for (i = 0; i < MTK_MAC_COUNT; i++) {
403 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
404 continue;
405 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
406 mtk_stats_update_mac(eth->mac[i]);
407 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
408 }
409 }
410 }
411
412 static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
413 struct rtnl_link_stats64 *storage)
414 {
415 struct mtk_mac *mac = netdev_priv(dev);
416 struct mtk_hw_stats *hw_stats = mac->hw_stats;
417 unsigned int start;
418
419 if (netif_running(dev) && netif_device_present(dev)) {
420 if (spin_trylock(&hw_stats->stats_lock)) {
421 mtk_stats_update_mac(mac);
422 spin_unlock(&hw_stats->stats_lock);
423 }
424 }
425
426 do {
427 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
428 storage->rx_packets = hw_stats->rx_packets;
429 storage->tx_packets = hw_stats->tx_packets;
430 storage->rx_bytes = hw_stats->rx_bytes;
431 storage->tx_bytes = hw_stats->tx_bytes;
432 storage->collisions = hw_stats->tx_collisions;
433 storage->rx_length_errors = hw_stats->rx_short_errors +
434 hw_stats->rx_long_errors;
435 storage->rx_over_errors = hw_stats->rx_overflow;
436 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
437 storage->rx_errors = hw_stats->rx_checksum_errors;
438 storage->tx_aborted_errors = hw_stats->tx_skip;
439 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
440
441 storage->tx_errors = dev->stats.tx_errors;
442 storage->rx_dropped = dev->stats.rx_dropped;
443 storage->tx_dropped = dev->stats.tx_dropped;
444
445 return storage;
446 }
447
448 static inline int mtk_max_frag_size(int mtu)
449 {
450 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
451 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
452 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
453
454 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
455 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
456 }
457
458 static inline int mtk_max_buf_size(int frag_size)
459 {
460 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
461 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
462
463 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
464
465 return buf_size;
466 }
467
468 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
469 struct mtk_rx_dma *dma_rxd)
470 {
471 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
472 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
473 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
474 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
475 }
476
477 /* the qdma core needs scratch memory to be setup */
478 static int mtk_init_fq_dma(struct mtk_eth *eth)
479 {
480 dma_addr_t phy_ring_tail;
481 int cnt = MTK_DMA_SIZE;
482 dma_addr_t dma_addr;
483 int i;
484
485 eth->scratch_ring = dma_alloc_coherent(eth->dev,
486 cnt * sizeof(struct mtk_tx_dma),
487 &eth->phy_scratch_ring,
488 GFP_ATOMIC | __GFP_ZERO);
489 if (unlikely(!eth->scratch_ring))
490 return -ENOMEM;
491
492 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
493 GFP_KERNEL);
494 if (unlikely(!eth->scratch_head))
495 return -ENOMEM;
496
497 dma_addr = dma_map_single(eth->dev,
498 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
499 DMA_FROM_DEVICE);
500 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
501 return -ENOMEM;
502
503 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
504 phy_ring_tail = eth->phy_scratch_ring +
505 (sizeof(struct mtk_tx_dma) * (cnt - 1));
506
507 for (i = 0; i < cnt; i++) {
508 eth->scratch_ring[i].txd1 =
509 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
510 if (i < cnt - 1)
511 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
512 ((i + 1) * sizeof(struct mtk_tx_dma)));
513 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
514 }
515
516 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
517 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
518 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
519 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
520
521 return 0;
522 }
523
524 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
525 {
526 void *ret = ring->dma;
527
528 return ret + (desc - ring->phys);
529 }
530
531 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
532 struct mtk_tx_dma *txd)
533 {
534 int idx = txd - ring->dma;
535
536 return &ring->buf[idx];
537 }
538
539 static void mtk_tx_unmap(struct device *dev, struct mtk_tx_buf *tx_buf)
540 {
541 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
542 dma_unmap_single(dev,
543 dma_unmap_addr(tx_buf, dma_addr0),
544 dma_unmap_len(tx_buf, dma_len0),
545 DMA_TO_DEVICE);
546 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
547 dma_unmap_page(dev,
548 dma_unmap_addr(tx_buf, dma_addr0),
549 dma_unmap_len(tx_buf, dma_len0),
550 DMA_TO_DEVICE);
551 }
552 tx_buf->flags = 0;
553 if (tx_buf->skb &&
554 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
555 dev_kfree_skb_any(tx_buf->skb);
556 tx_buf->skb = NULL;
557 }
558
559 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
560 int tx_num, struct mtk_tx_ring *ring, bool gso)
561 {
562 struct mtk_mac *mac = netdev_priv(dev);
563 struct mtk_eth *eth = mac->hw;
564 struct mtk_tx_dma *itxd, *txd;
565 struct mtk_tx_buf *tx_buf;
566 dma_addr_t mapped_addr;
567 unsigned int nr_frags;
568 int i, n_desc = 1;
569 u32 txd4 = 0;
570
571 itxd = ring->next_free;
572 if (itxd == ring->last_free)
573 return -ENOMEM;
574
575 /* set the forward port */
576 txd4 |= (mac->id + 1) << TX_DMA_FPORT_SHIFT;
577
578 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
579 memset(tx_buf, 0, sizeof(*tx_buf));
580
581 if (gso)
582 txd4 |= TX_DMA_TSO;
583
584 /* TX Checksum offload */
585 if (skb->ip_summed == CHECKSUM_PARTIAL)
586 txd4 |= TX_DMA_CHKSUM;
587
588 /* VLAN header offload */
589 if (skb_vlan_tag_present(skb))
590 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
591
592 mapped_addr = dma_map_single(&dev->dev, skb->data,
593 skb_headlen(skb), DMA_TO_DEVICE);
594 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
595 return -ENOMEM;
596
597 WRITE_ONCE(itxd->txd1, mapped_addr);
598 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
599 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
600 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
601
602 /* TX SG offload */
603 txd = itxd;
604 nr_frags = skb_shinfo(skb)->nr_frags;
605 for (i = 0; i < nr_frags; i++) {
606 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
607 unsigned int offset = 0;
608 int frag_size = skb_frag_size(frag);
609
610 while (frag_size) {
611 bool last_frag = false;
612 unsigned int frag_map_size;
613
614 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
615 if (txd == ring->last_free)
616 goto err_dma;
617
618 n_desc++;
619 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
620 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
621 frag_map_size,
622 DMA_TO_DEVICE);
623 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
624 goto err_dma;
625
626 if (i == nr_frags - 1 &&
627 (frag_size - frag_map_size) == 0)
628 last_frag = true;
629
630 WRITE_ONCE(txd->txd1, mapped_addr);
631 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
632 TX_DMA_PLEN0(frag_map_size) |
633 last_frag * TX_DMA_LS0));
634 WRITE_ONCE(txd->txd4, 0);
635
636 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
637 tx_buf = mtk_desc_to_tx_buf(ring, txd);
638 memset(tx_buf, 0, sizeof(*tx_buf));
639
640 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
641 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
642 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
643 frag_size -= frag_map_size;
644 offset += frag_map_size;
645 }
646 }
647
648 /* store skb to cleanup */
649 tx_buf->skb = skb;
650
651 WRITE_ONCE(itxd->txd4, txd4);
652 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
653 (!nr_frags * TX_DMA_LS0)));
654
655 netdev_sent_queue(dev, skb->len);
656 skb_tx_timestamp(skb);
657
658 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
659 atomic_sub(n_desc, &ring->free_count);
660
661 /* make sure that all changes to the dma ring are flushed before we
662 * continue
663 */
664 wmb();
665
666 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
667 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
668
669 return 0;
670
671 err_dma:
672 do {
673 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
674
675 /* unmap dma */
676 mtk_tx_unmap(&dev->dev, tx_buf);
677
678 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
679 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
680 } while (itxd != txd);
681
682 return -ENOMEM;
683 }
684
685 static inline int mtk_cal_txd_req(struct sk_buff *skb)
686 {
687 int i, nfrags;
688 struct skb_frag_struct *frag;
689
690 nfrags = 1;
691 if (skb_is_gso(skb)) {
692 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
693 frag = &skb_shinfo(skb)->frags[i];
694 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
695 }
696 } else {
697 nfrags += skb_shinfo(skb)->nr_frags;
698 }
699
700 return nfrags;
701 }
702
703 static int mtk_queue_stopped(struct mtk_eth *eth)
704 {
705 int i;
706
707 for (i = 0; i < MTK_MAC_COUNT; i++) {
708 if (!eth->netdev[i])
709 continue;
710 if (netif_queue_stopped(eth->netdev[i]))
711 return 1;
712 }
713
714 return 0;
715 }
716
717 static void mtk_wake_queue(struct mtk_eth *eth)
718 {
719 int i;
720
721 for (i = 0; i < MTK_MAC_COUNT; i++) {
722 if (!eth->netdev[i])
723 continue;
724 netif_wake_queue(eth->netdev[i]);
725 }
726 }
727
728 static void mtk_stop_queue(struct mtk_eth *eth)
729 {
730 int i;
731
732 for (i = 0; i < MTK_MAC_COUNT; i++) {
733 if (!eth->netdev[i])
734 continue;
735 netif_stop_queue(eth->netdev[i]);
736 }
737 }
738
739 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
740 {
741 struct mtk_mac *mac = netdev_priv(dev);
742 struct mtk_eth *eth = mac->hw;
743 struct mtk_tx_ring *ring = &eth->tx_ring;
744 struct net_device_stats *stats = &dev->stats;
745 unsigned long flags;
746 bool gso = false;
747 int tx_num;
748
749 /* normally we can rely on the stack not calling this more than once,
750 * however we have 2 queues running on the same ring so we need to lock
751 * the ring access
752 */
753 spin_lock_irqsave(&eth->page_lock, flags);
754
755 tx_num = mtk_cal_txd_req(skb);
756 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
757 mtk_stop_queue(eth);
758 netif_err(eth, tx_queued, dev,
759 "Tx Ring full when queue awake!\n");
760 spin_unlock_irqrestore(&eth->page_lock, flags);
761 return NETDEV_TX_BUSY;
762 }
763
764 /* TSO: fill MSS info in tcp checksum field */
765 if (skb_is_gso(skb)) {
766 if (skb_cow_head(skb, 0)) {
767 netif_warn(eth, tx_err, dev,
768 "GSO expand head fail.\n");
769 goto drop;
770 }
771
772 if (skb_shinfo(skb)->gso_type &
773 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
774 gso = true;
775 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
776 }
777 }
778
779 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
780 goto drop;
781
782 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
783 mtk_stop_queue(eth);
784
785 spin_unlock_irqrestore(&eth->page_lock, flags);
786
787 return NETDEV_TX_OK;
788
789 drop:
790 spin_unlock_irqrestore(&eth->page_lock, flags);
791 stats->tx_dropped++;
792 dev_kfree_skb(skb);
793 return NETDEV_TX_OK;
794 }
795
796 static int mtk_poll_rx(struct napi_struct *napi, int budget,
797 struct mtk_eth *eth)
798 {
799 struct mtk_rx_ring *ring = &eth->rx_ring;
800 int idx = ring->calc_idx;
801 struct sk_buff *skb;
802 u8 *data, *new_data;
803 struct mtk_rx_dma *rxd, trxd;
804 int done = 0;
805
806 while (done < budget) {
807 struct net_device *netdev;
808 unsigned int pktlen;
809 dma_addr_t dma_addr;
810 int mac = 0;
811
812 idx = NEXT_RX_DESP_IDX(idx);
813 rxd = &ring->dma[idx];
814 data = ring->data[idx];
815
816 mtk_rx_get_desc(&trxd, rxd);
817 if (!(trxd.rxd2 & RX_DMA_DONE))
818 break;
819
820 /* find out which mac the packet come from. values start at 1 */
821 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
822 RX_DMA_FPORT_MASK;
823 mac--;
824
825 netdev = eth->netdev[mac];
826
827 /* alloc new buffer */
828 new_data = napi_alloc_frag(ring->frag_size);
829 if (unlikely(!new_data)) {
830 netdev->stats.rx_dropped++;
831 goto release_desc;
832 }
833 dma_addr = dma_map_single(&eth->netdev[mac]->dev,
834 new_data + NET_SKB_PAD,
835 ring->buf_size,
836 DMA_FROM_DEVICE);
837 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
838 skb_free_frag(new_data);
839 netdev->stats.rx_dropped++;
840 goto release_desc;
841 }
842
843 /* receive data */
844 skb = build_skb(data, ring->frag_size);
845 if (unlikely(!skb)) {
846 put_page(virt_to_head_page(new_data));
847 netdev->stats.rx_dropped++;
848 goto release_desc;
849 }
850 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
851
852 dma_unmap_single(&netdev->dev, trxd.rxd1,
853 ring->buf_size, DMA_FROM_DEVICE);
854 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
855 skb->dev = netdev;
856 skb_put(skb, pktlen);
857 if (trxd.rxd4 & RX_DMA_L4_VALID)
858 skb->ip_summed = CHECKSUM_UNNECESSARY;
859 else
860 skb_checksum_none_assert(skb);
861 skb->protocol = eth_type_trans(skb, netdev);
862
863 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
864 RX_DMA_VID(trxd.rxd3))
865 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
866 RX_DMA_VID(trxd.rxd3));
867 napi_gro_receive(napi, skb);
868
869 ring->data[idx] = new_data;
870 rxd->rxd1 = (unsigned int)dma_addr;
871
872 release_desc:
873 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
874
875 ring->calc_idx = idx;
876 /* make sure that all changes to the dma ring are flushed before
877 * we continue
878 */
879 wmb();
880 mtk_w32(eth, ring->calc_idx, MTK_QRX_CRX_IDX0);
881 done++;
882 }
883
884 if (done < budget)
885 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QMTK_INT_STATUS);
886
887 return done;
888 }
889
890 static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
891 {
892 struct mtk_tx_ring *ring = &eth->tx_ring;
893 struct mtk_tx_dma *desc;
894 struct sk_buff *skb;
895 struct mtk_tx_buf *tx_buf;
896 int total = 0, done[MTK_MAX_DEVS];
897 unsigned int bytes[MTK_MAX_DEVS];
898 u32 cpu, dma;
899 static int condition;
900 int i;
901
902 memset(done, 0, sizeof(done));
903 memset(bytes, 0, sizeof(bytes));
904
905 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
906 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
907
908 desc = mtk_qdma_phys_to_virt(ring, cpu);
909
910 while ((cpu != dma) && budget) {
911 u32 next_cpu = desc->txd2;
912 int mac;
913
914 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
915 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
916 break;
917
918 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
919 TX_DMA_FPORT_MASK;
920 mac--;
921
922 tx_buf = mtk_desc_to_tx_buf(ring, desc);
923 skb = tx_buf->skb;
924 if (!skb) {
925 condition = 1;
926 break;
927 }
928
929 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
930 bytes[mac] += skb->len;
931 done[mac]++;
932 budget--;
933 }
934 mtk_tx_unmap(eth->dev, tx_buf);
935
936 ring->last_free = desc;
937 atomic_inc(&ring->free_count);
938
939 cpu = next_cpu;
940 }
941
942 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
943
944 for (i = 0; i < MTK_MAC_COUNT; i++) {
945 if (!eth->netdev[i] || !done[i])
946 continue;
947 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
948 total += done[i];
949 }
950
951 /* read hw index again make sure no new tx packet */
952 if (cpu != dma || cpu != mtk_r32(eth, MTK_QTX_DRX_PTR))
953 *tx_again = true;
954 else
955 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
956
957 if (!total)
958 return 0;
959
960 if (mtk_queue_stopped(eth) &&
961 (atomic_read(&ring->free_count) > ring->thresh))
962 mtk_wake_queue(eth);
963
964 return total;
965 }
966
967 static int mtk_poll(struct napi_struct *napi, int budget)
968 {
969 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
970 u32 status, status2, mask;
971 int tx_done, rx_done;
972 bool tx_again = false;
973
974 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
975 status2 = mtk_r32(eth, MTK_INT_STATUS2);
976 tx_done = 0;
977 rx_done = 0;
978 tx_again = 0;
979
980 if (status & MTK_TX_DONE_INT)
981 tx_done = mtk_poll_tx(eth, budget, &tx_again);
982
983 if (status & MTK_RX_DONE_INT)
984 rx_done = mtk_poll_rx(napi, budget, eth);
985
986 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
987 mtk_stats_update(eth);
988 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
989 MTK_INT_STATUS2);
990 }
991
992 if (unlikely(netif_msg_intr(eth))) {
993 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
994 netdev_info(eth->netdev[0],
995 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
996 tx_done, rx_done, status, mask);
997 }
998
999 if (tx_again || rx_done == budget)
1000 return budget;
1001
1002 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1003 if (status & (tx_intr | rx_intr))
1004 return budget;
1005
1006 napi_complete(napi);
1007 mtk_irq_enable(eth, MTK_RX_DONE_INT | MTK_RX_DONE_INT);
1008
1009 return rx_done;
1010 }
1011
1012 static int mtk_tx_alloc(struct mtk_eth *eth)
1013 {
1014 struct mtk_tx_ring *ring = &eth->tx_ring;
1015 int i, sz = sizeof(*ring->dma);
1016
1017 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1018 GFP_KERNEL);
1019 if (!ring->buf)
1020 goto no_tx_mem;
1021
1022 ring->dma = dma_alloc_coherent(eth->dev,
1023 MTK_DMA_SIZE * sz,
1024 &ring->phys,
1025 GFP_ATOMIC | __GFP_ZERO);
1026 if (!ring->dma)
1027 goto no_tx_mem;
1028
1029 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
1030 for (i = 0; i < MTK_DMA_SIZE; i++) {
1031 int next = (i + 1) % MTK_DMA_SIZE;
1032 u32 next_ptr = ring->phys + next * sz;
1033
1034 ring->dma[i].txd2 = next_ptr;
1035 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1036 }
1037
1038 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1039 ring->next_free = &ring->dma[0];
1040 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
1041 ring->thresh = MAX_SKB_FRAGS;
1042
1043 /* make sure that all changes to the dma ring are flushed before we
1044 * continue
1045 */
1046 wmb();
1047
1048 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1049 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1050 mtk_w32(eth,
1051 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1052 MTK_QTX_CRX_PTR);
1053 mtk_w32(eth,
1054 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1055 MTK_QTX_DRX_PTR);
1056
1057 return 0;
1058
1059 no_tx_mem:
1060 return -ENOMEM;
1061 }
1062
1063 static void mtk_tx_clean(struct mtk_eth *eth)
1064 {
1065 struct mtk_tx_ring *ring = &eth->tx_ring;
1066 int i;
1067
1068 if (ring->buf) {
1069 for (i = 0; i < MTK_DMA_SIZE; i++)
1070 mtk_tx_unmap(eth->dev, &ring->buf[i]);
1071 kfree(ring->buf);
1072 ring->buf = NULL;
1073 }
1074
1075 if (ring->dma) {
1076 dma_free_coherent(eth->dev,
1077 MTK_DMA_SIZE * sizeof(*ring->dma),
1078 ring->dma,
1079 ring->phys);
1080 ring->dma = NULL;
1081 }
1082 }
1083
1084 static int mtk_rx_alloc(struct mtk_eth *eth)
1085 {
1086 struct mtk_rx_ring *ring = &eth->rx_ring;
1087 int i;
1088
1089 ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN);
1090 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1091 ring->data = kcalloc(MTK_DMA_SIZE, sizeof(*ring->data),
1092 GFP_KERNEL);
1093 if (!ring->data)
1094 return -ENOMEM;
1095
1096 for (i = 0; i < MTK_DMA_SIZE; i++) {
1097 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1098 if (!ring->data[i])
1099 return -ENOMEM;
1100 }
1101
1102 ring->dma = dma_alloc_coherent(eth->dev,
1103 MTK_DMA_SIZE * sizeof(*ring->dma),
1104 &ring->phys,
1105 GFP_ATOMIC | __GFP_ZERO);
1106 if (!ring->dma)
1107 return -ENOMEM;
1108
1109 for (i = 0; i < MTK_DMA_SIZE; i++) {
1110 dma_addr_t dma_addr = dma_map_single(eth->dev,
1111 ring->data[i] + NET_SKB_PAD,
1112 ring->buf_size,
1113 DMA_FROM_DEVICE);
1114 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1115 return -ENOMEM;
1116 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1117
1118 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1119 }
1120 ring->calc_idx = MTK_DMA_SIZE - 1;
1121 /* make sure that all changes to the dma ring are flushed before we
1122 * continue
1123 */
1124 wmb();
1125
1126 mtk_w32(eth, eth->rx_ring.phys, MTK_QRX_BASE_PTR0);
1127 mtk_w32(eth, MTK_DMA_SIZE, MTK_QRX_MAX_CNT0);
1128 mtk_w32(eth, eth->rx_ring.calc_idx, MTK_QRX_CRX_IDX0);
1129 mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_QDMA_RST_IDX);
1130 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1131
1132 return 0;
1133 }
1134
1135 static void mtk_rx_clean(struct mtk_eth *eth)
1136 {
1137 struct mtk_rx_ring *ring = &eth->rx_ring;
1138 int i;
1139
1140 if (ring->data && ring->dma) {
1141 for (i = 0; i < MTK_DMA_SIZE; i++) {
1142 if (!ring->data[i])
1143 continue;
1144 if (!ring->dma[i].rxd1)
1145 continue;
1146 dma_unmap_single(eth->dev,
1147 ring->dma[i].rxd1,
1148 ring->buf_size,
1149 DMA_FROM_DEVICE);
1150 skb_free_frag(ring->data[i]);
1151 }
1152 kfree(ring->data);
1153 ring->data = NULL;
1154 }
1155
1156 if (ring->dma) {
1157 dma_free_coherent(eth->dev,
1158 MTK_DMA_SIZE * sizeof(*ring->dma),
1159 ring->dma,
1160 ring->phys);
1161 ring->dma = NULL;
1162 }
1163 }
1164
1165 /* wait for DMA to finish whatever it is doing before we start using it again */
1166 static int mtk_dma_busy_wait(struct mtk_eth *eth)
1167 {
1168 unsigned long t_start = jiffies;
1169
1170 while (1) {
1171 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1172 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1173 return 0;
1174 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1175 break;
1176 }
1177
1178 dev_err(eth->dev, "DMA init timeout\n");
1179 return -1;
1180 }
1181
1182 static int mtk_dma_init(struct mtk_eth *eth)
1183 {
1184 int err;
1185
1186 if (mtk_dma_busy_wait(eth))
1187 return -EBUSY;
1188
1189 /* QDMA needs scratch memory for internal reordering of the
1190 * descriptors
1191 */
1192 err = mtk_init_fq_dma(eth);
1193 if (err)
1194 return err;
1195
1196 err = mtk_tx_alloc(eth);
1197 if (err)
1198 return err;
1199
1200 err = mtk_rx_alloc(eth);
1201 if (err)
1202 return err;
1203
1204 /* Enable random early drop and set drop threshold automatically */
1205 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1206 MTK_QDMA_FC_THRES);
1207 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1208
1209 return 0;
1210 }
1211
1212 static void mtk_dma_free(struct mtk_eth *eth)
1213 {
1214 int i;
1215
1216 for (i = 0; i < MTK_MAC_COUNT; i++)
1217 if (eth->netdev[i])
1218 netdev_reset_queue(eth->netdev[i]);
1219 if (eth->scratch_ring) {
1220 dma_free_coherent(eth->dev,
1221 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1222 eth->scratch_ring,
1223 eth->phy_scratch_ring);
1224 eth->scratch_ring = NULL;
1225 eth->phy_scratch_ring = 0;
1226 }
1227 mtk_tx_clean(eth);
1228 mtk_rx_clean(eth);
1229 kfree(eth->scratch_head);
1230 }
1231
1232 static void mtk_tx_timeout(struct net_device *dev)
1233 {
1234 struct mtk_mac *mac = netdev_priv(dev);
1235 struct mtk_eth *eth = mac->hw;
1236
1237 eth->netdev[mac->id]->stats.tx_errors++;
1238 netif_err(eth, tx_err, dev,
1239 "transmit timed out\n");
1240 schedule_work(&eth->pending_work);
1241 }
1242
1243 static irqreturn_t mtk_handle_irq(int irq, void *_eth)
1244 {
1245 struct mtk_eth *eth = _eth;
1246 u32 status;
1247
1248 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1249 if (unlikely(!status))
1250 return IRQ_NONE;
1251
1252 if (likely(status & (MTK_RX_DONE_INT | MTK_TX_DONE_INT))) {
1253 if (likely(napi_schedule_prep(&eth->rx_napi)))
1254 __napi_schedule(&eth->rx_napi);
1255 } else {
1256 mtk_w32(eth, status, MTK_QMTK_INT_STATUS);
1257 }
1258 mtk_irq_disable(eth, (MTK_RX_DONE_INT | MTK_TX_DONE_INT));
1259
1260 return IRQ_HANDLED;
1261 }
1262
1263 #ifdef CONFIG_NET_POLL_CONTROLLER
1264 static void mtk_poll_controller(struct net_device *dev)
1265 {
1266 struct mtk_mac *mac = netdev_priv(dev);
1267 struct mtk_eth *eth = mac->hw;
1268 u32 int_mask = MTK_TX_DONE_INT | MTK_RX_DONE_INT;
1269
1270 mtk_irq_disable(eth, int_mask);
1271 mtk_handle_irq(dev->irq, dev);
1272 mtk_irq_enable(eth, int_mask);
1273 }
1274 #endif
1275
1276 static int mtk_start_dma(struct mtk_eth *eth)
1277 {
1278 int err;
1279
1280 err = mtk_dma_init(eth);
1281 if (err) {
1282 mtk_dma_free(eth);
1283 return err;
1284 }
1285
1286 mtk_w32(eth,
1287 MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN |
1288 MTK_RX_2B_OFFSET | MTK_DMA_SIZE_16DWORDS |
1289 MTK_RX_BT_32DWORDS | MTK_NDP_CO_PRO,
1290 MTK_QDMA_GLO_CFG);
1291
1292 return 0;
1293 }
1294
1295 static int mtk_open(struct net_device *dev)
1296 {
1297 struct mtk_mac *mac = netdev_priv(dev);
1298 struct mtk_eth *eth = mac->hw;
1299
1300 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1301 if (!atomic_read(&eth->dma_refcnt)) {
1302 int err = mtk_start_dma(eth);
1303
1304 if (err)
1305 return err;
1306
1307 napi_enable(&eth->rx_napi);
1308 mtk_irq_enable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1309 }
1310 atomic_inc(&eth->dma_refcnt);
1311
1312 phy_start(mac->phy_dev);
1313 netif_start_queue(dev);
1314
1315 return 0;
1316 }
1317
1318 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1319 {
1320 unsigned long flags;
1321 u32 val;
1322 int i;
1323
1324 /* stop the dma engine */
1325 spin_lock_irqsave(&eth->page_lock, flags);
1326 val = mtk_r32(eth, glo_cfg);
1327 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1328 glo_cfg);
1329 spin_unlock_irqrestore(&eth->page_lock, flags);
1330
1331 /* wait for dma stop */
1332 for (i = 0; i < 10; i++) {
1333 val = mtk_r32(eth, glo_cfg);
1334 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1335 msleep(20);
1336 continue;
1337 }
1338 break;
1339 }
1340 }
1341
1342 static int mtk_stop(struct net_device *dev)
1343 {
1344 struct mtk_mac *mac = netdev_priv(dev);
1345 struct mtk_eth *eth = mac->hw;
1346
1347 netif_tx_disable(dev);
1348 phy_stop(mac->phy_dev);
1349
1350 /* only shutdown DMA if this is the last user */
1351 if (!atomic_dec_and_test(&eth->dma_refcnt))
1352 return 0;
1353
1354 mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1355 napi_disable(&eth->rx_napi);
1356
1357 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1358
1359 mtk_dma_free(eth);
1360
1361 return 0;
1362 }
1363
1364 static int __init mtk_hw_init(struct mtk_eth *eth)
1365 {
1366 int err, i;
1367
1368 /* reset the frame engine */
1369 reset_control_assert(eth->rstc);
1370 usleep_range(10, 20);
1371 reset_control_deassert(eth->rstc);
1372 usleep_range(10, 20);
1373
1374 /* Set GE2 driving and slew rate */
1375 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1376
1377 /* set GE2 TDSEL */
1378 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1379
1380 /* set GE2 TUNE */
1381 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1382
1383 /* GE1, Force 1000M/FD, FC ON */
1384 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1385
1386 /* GE2, Force 1000M/FD, FC ON */
1387 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1388
1389 /* Enable RX VLan Offloading */
1390 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1391
1392 err = devm_request_irq(eth->dev, eth->irq, mtk_handle_irq, 0,
1393 dev_name(eth->dev), eth);
1394 if (err)
1395 return err;
1396
1397 err = mtk_mdio_init(eth);
1398 if (err)
1399 return err;
1400
1401 /* disable delay and normal interrupt */
1402 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
1403 mtk_irq_disable(eth, ~0);
1404 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1405 mtk_w32(eth, 0, MTK_RST_GL);
1406
1407 /* FE int grouping */
1408 mtk_w32(eth, 0, MTK_FE_INT_GRP);
1409
1410 for (i = 0; i < 2; i++) {
1411 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1412
1413 /* setup the forward port to send frame to QDMA */
1414 val &= ~0xffff;
1415 val |= 0x5555;
1416
1417 /* Enable RX checksum */
1418 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1419
1420 /* setup the mac dma */
1421 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1422 }
1423
1424 return 0;
1425 }
1426
1427 static int __init mtk_init(struct net_device *dev)
1428 {
1429 struct mtk_mac *mac = netdev_priv(dev);
1430 struct mtk_eth *eth = mac->hw;
1431 const char *mac_addr;
1432
1433 mac_addr = of_get_mac_address(mac->of_node);
1434 if (mac_addr)
1435 ether_addr_copy(dev->dev_addr, mac_addr);
1436
1437 /* If the mac address is invalid, use random mac address */
1438 if (!is_valid_ether_addr(dev->dev_addr)) {
1439 random_ether_addr(dev->dev_addr);
1440 dev_err(eth->dev, "generated random MAC address %pM\n",
1441 dev->dev_addr);
1442 dev->addr_assign_type = NET_ADDR_RANDOM;
1443 }
1444
1445 return mtk_phy_connect(mac);
1446 }
1447
1448 static void mtk_uninit(struct net_device *dev)
1449 {
1450 struct mtk_mac *mac = netdev_priv(dev);
1451 struct mtk_eth *eth = mac->hw;
1452
1453 phy_disconnect(mac->phy_dev);
1454 mtk_mdio_cleanup(eth);
1455 mtk_irq_disable(eth, ~0);
1456 free_irq(dev->irq, dev);
1457 }
1458
1459 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1460 {
1461 struct mtk_mac *mac = netdev_priv(dev);
1462
1463 switch (cmd) {
1464 case SIOCGMIIPHY:
1465 case SIOCGMIIREG:
1466 case SIOCSMIIREG:
1467 return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
1468 default:
1469 break;
1470 }
1471
1472 return -EOPNOTSUPP;
1473 }
1474
1475 static void mtk_pending_work(struct work_struct *work)
1476 {
1477 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
1478 int err, i;
1479 unsigned long restart = 0;
1480
1481 rtnl_lock();
1482
1483 /* stop all devices to make sure that dma is properly shut down */
1484 for (i = 0; i < MTK_MAC_COUNT; i++) {
1485 if (!eth->netdev[i])
1486 continue;
1487 mtk_stop(eth->netdev[i]);
1488 __set_bit(i, &restart);
1489 }
1490
1491 /* restart DMA and enable IRQs */
1492 for (i = 0; i < MTK_MAC_COUNT; i++) {
1493 if (!test_bit(i, &restart))
1494 continue;
1495 err = mtk_open(eth->netdev[i]);
1496 if (err) {
1497 netif_alert(eth, ifup, eth->netdev[i],
1498 "Driver up/down cycle failed, closing device.\n");
1499 dev_close(eth->netdev[i]);
1500 }
1501 }
1502 rtnl_unlock();
1503 }
1504
1505 static int mtk_cleanup(struct mtk_eth *eth)
1506 {
1507 int i;
1508
1509 for (i = 0; i < MTK_MAC_COUNT; i++) {
1510 if (!eth->netdev[i])
1511 continue;
1512
1513 unregister_netdev(eth->netdev[i]);
1514 free_netdev(eth->netdev[i]);
1515 }
1516 cancel_work_sync(&eth->pending_work);
1517
1518 return 0;
1519 }
1520
1521 static int mtk_get_settings(struct net_device *dev,
1522 struct ethtool_cmd *cmd)
1523 {
1524 struct mtk_mac *mac = netdev_priv(dev);
1525 int err;
1526
1527 err = phy_read_status(mac->phy_dev);
1528 if (err)
1529 return -ENODEV;
1530
1531 return phy_ethtool_gset(mac->phy_dev, cmd);
1532 }
1533
1534 static int mtk_set_settings(struct net_device *dev,
1535 struct ethtool_cmd *cmd)
1536 {
1537 struct mtk_mac *mac = netdev_priv(dev);
1538
1539 if (cmd->phy_address != mac->phy_dev->mdio.addr) {
1540 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
1541 cmd->phy_address);
1542 if (!mac->phy_dev)
1543 return -ENODEV;
1544 }
1545
1546 return phy_ethtool_sset(mac->phy_dev, cmd);
1547 }
1548
1549 static void mtk_get_drvinfo(struct net_device *dev,
1550 struct ethtool_drvinfo *info)
1551 {
1552 struct mtk_mac *mac = netdev_priv(dev);
1553
1554 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
1555 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
1556 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
1557 }
1558
1559 static u32 mtk_get_msglevel(struct net_device *dev)
1560 {
1561 struct mtk_mac *mac = netdev_priv(dev);
1562
1563 return mac->hw->msg_enable;
1564 }
1565
1566 static void mtk_set_msglevel(struct net_device *dev, u32 value)
1567 {
1568 struct mtk_mac *mac = netdev_priv(dev);
1569
1570 mac->hw->msg_enable = value;
1571 }
1572
1573 static int mtk_nway_reset(struct net_device *dev)
1574 {
1575 struct mtk_mac *mac = netdev_priv(dev);
1576
1577 return genphy_restart_aneg(mac->phy_dev);
1578 }
1579
1580 static u32 mtk_get_link(struct net_device *dev)
1581 {
1582 struct mtk_mac *mac = netdev_priv(dev);
1583 int err;
1584
1585 err = genphy_update_link(mac->phy_dev);
1586 if (err)
1587 return ethtool_op_get_link(dev);
1588
1589 return mac->phy_dev->link;
1590 }
1591
1592 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1593 {
1594 int i;
1595
1596 switch (stringset) {
1597 case ETH_SS_STATS:
1598 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
1599 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
1600 data += ETH_GSTRING_LEN;
1601 }
1602 break;
1603 }
1604 }
1605
1606 static int mtk_get_sset_count(struct net_device *dev, int sset)
1607 {
1608 switch (sset) {
1609 case ETH_SS_STATS:
1610 return ARRAY_SIZE(mtk_ethtool_stats);
1611 default:
1612 return -EOPNOTSUPP;
1613 }
1614 }
1615
1616 static void mtk_get_ethtool_stats(struct net_device *dev,
1617 struct ethtool_stats *stats, u64 *data)
1618 {
1619 struct mtk_mac *mac = netdev_priv(dev);
1620 struct mtk_hw_stats *hwstats = mac->hw_stats;
1621 u64 *data_src, *data_dst;
1622 unsigned int start;
1623 int i;
1624
1625 if (netif_running(dev) && netif_device_present(dev)) {
1626 if (spin_trylock(&hwstats->stats_lock)) {
1627 mtk_stats_update_mac(mac);
1628 spin_unlock(&hwstats->stats_lock);
1629 }
1630 }
1631
1632 do {
1633 data_src = (u64*)hwstats;
1634 data_dst = data;
1635 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
1636
1637 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
1638 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
1639 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
1640 }
1641
1642 static struct ethtool_ops mtk_ethtool_ops = {
1643 .get_settings = mtk_get_settings,
1644 .set_settings = mtk_set_settings,
1645 .get_drvinfo = mtk_get_drvinfo,
1646 .get_msglevel = mtk_get_msglevel,
1647 .set_msglevel = mtk_set_msglevel,
1648 .nway_reset = mtk_nway_reset,
1649 .get_link = mtk_get_link,
1650 .get_strings = mtk_get_strings,
1651 .get_sset_count = mtk_get_sset_count,
1652 .get_ethtool_stats = mtk_get_ethtool_stats,
1653 };
1654
1655 static const struct net_device_ops mtk_netdev_ops = {
1656 .ndo_init = mtk_init,
1657 .ndo_uninit = mtk_uninit,
1658 .ndo_open = mtk_open,
1659 .ndo_stop = mtk_stop,
1660 .ndo_start_xmit = mtk_start_xmit,
1661 .ndo_set_mac_address = mtk_set_mac_address,
1662 .ndo_validate_addr = eth_validate_addr,
1663 .ndo_do_ioctl = mtk_do_ioctl,
1664 .ndo_change_mtu = eth_change_mtu,
1665 .ndo_tx_timeout = mtk_tx_timeout,
1666 .ndo_get_stats64 = mtk_get_stats64,
1667 #ifdef CONFIG_NET_POLL_CONTROLLER
1668 .ndo_poll_controller = mtk_poll_controller,
1669 #endif
1670 };
1671
1672 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
1673 {
1674 struct mtk_mac *mac;
1675 const __be32 *_id = of_get_property(np, "reg", NULL);
1676 int id, err;
1677
1678 if (!_id) {
1679 dev_err(eth->dev, "missing mac id\n");
1680 return -EINVAL;
1681 }
1682
1683 id = be32_to_cpup(_id);
1684 if (id >= MTK_MAC_COUNT) {
1685 dev_err(eth->dev, "%d is not a valid mac id\n", id);
1686 return -EINVAL;
1687 }
1688
1689 if (eth->netdev[id]) {
1690 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
1691 return -EINVAL;
1692 }
1693
1694 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
1695 if (!eth->netdev[id]) {
1696 dev_err(eth->dev, "alloc_etherdev failed\n");
1697 return -ENOMEM;
1698 }
1699 mac = netdev_priv(eth->netdev[id]);
1700 eth->mac[id] = mac;
1701 mac->id = id;
1702 mac->hw = eth;
1703 mac->of_node = np;
1704
1705 mac->hw_stats = devm_kzalloc(eth->dev,
1706 sizeof(*mac->hw_stats),
1707 GFP_KERNEL);
1708 if (!mac->hw_stats) {
1709 dev_err(eth->dev, "failed to allocate counter memory\n");
1710 err = -ENOMEM;
1711 goto free_netdev;
1712 }
1713 spin_lock_init(&mac->hw_stats->stats_lock);
1714 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
1715
1716 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
1717 eth->netdev[id]->watchdog_timeo = 5 * HZ;
1718 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
1719 eth->netdev[id]->base_addr = (unsigned long)eth->base;
1720 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
1721 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1722 eth->netdev[id]->features |= MTK_HW_FEATURES;
1723 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
1724
1725 err = register_netdev(eth->netdev[id]);
1726 if (err) {
1727 dev_err(eth->dev, "error bringing up device\n");
1728 goto free_netdev;
1729 }
1730 eth->netdev[id]->irq = eth->irq;
1731 netif_info(eth, probe, eth->netdev[id],
1732 "mediatek frame engine at 0x%08lx, irq %d\n",
1733 eth->netdev[id]->base_addr, eth->netdev[id]->irq);
1734
1735 return 0;
1736
1737 free_netdev:
1738 free_netdev(eth->netdev[id]);
1739 return err;
1740 }
1741
1742 static int mtk_probe(struct platform_device *pdev)
1743 {
1744 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1745 struct device_node *mac_np;
1746 const struct of_device_id *match;
1747 struct mtk_soc_data *soc;
1748 struct mtk_eth *eth;
1749 int err;
1750
1751 match = of_match_device(of_mtk_match, &pdev->dev);
1752 soc = (struct mtk_soc_data *)match->data;
1753
1754 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
1755 if (!eth)
1756 return -ENOMEM;
1757
1758 eth->base = devm_ioremap_resource(&pdev->dev, res);
1759 if (IS_ERR(eth->base))
1760 return PTR_ERR(eth->base);
1761
1762 spin_lock_init(&eth->page_lock);
1763
1764 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1765 "mediatek,ethsys");
1766 if (IS_ERR(eth->ethsys)) {
1767 dev_err(&pdev->dev, "no ethsys regmap found\n");
1768 return PTR_ERR(eth->ethsys);
1769 }
1770
1771 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1772 "mediatek,pctl");
1773 if (IS_ERR(eth->pctl)) {
1774 dev_err(&pdev->dev, "no pctl regmap found\n");
1775 return PTR_ERR(eth->pctl);
1776 }
1777
1778 eth->rstc = devm_reset_control_get(&pdev->dev, "eth");
1779 if (IS_ERR(eth->rstc)) {
1780 dev_err(&pdev->dev, "no eth reset found\n");
1781 return PTR_ERR(eth->rstc);
1782 }
1783
1784 eth->irq = platform_get_irq(pdev, 0);
1785 if (eth->irq < 0) {
1786 dev_err(&pdev->dev, "no IRQ resource found\n");
1787 return -ENXIO;
1788 }
1789
1790 eth->clk_ethif = devm_clk_get(&pdev->dev, "ethif");
1791 eth->clk_esw = devm_clk_get(&pdev->dev, "esw");
1792 eth->clk_gp1 = devm_clk_get(&pdev->dev, "gp1");
1793 eth->clk_gp2 = devm_clk_get(&pdev->dev, "gp2");
1794 if (IS_ERR(eth->clk_esw) || IS_ERR(eth->clk_gp1) ||
1795 IS_ERR(eth->clk_gp2) || IS_ERR(eth->clk_ethif))
1796 return -ENODEV;
1797
1798 clk_prepare_enable(eth->clk_ethif);
1799 clk_prepare_enable(eth->clk_esw);
1800 clk_prepare_enable(eth->clk_gp1);
1801 clk_prepare_enable(eth->clk_gp2);
1802
1803 eth->dev = &pdev->dev;
1804 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
1805 INIT_WORK(&eth->pending_work, mtk_pending_work);
1806
1807 err = mtk_hw_init(eth);
1808 if (err)
1809 return err;
1810
1811 for_each_child_of_node(pdev->dev.of_node, mac_np) {
1812 if (!of_device_is_compatible(mac_np,
1813 "mediatek,eth-mac"))
1814 continue;
1815
1816 if (!of_device_is_available(mac_np))
1817 continue;
1818
1819 err = mtk_add_mac(eth, mac_np);
1820 if (err)
1821 goto err_free_dev;
1822 }
1823
1824 /* we run 2 devices on the same DMA ring so we need a dummy device
1825 * for NAPI to work
1826 */
1827 init_dummy_netdev(&eth->dummy_dev);
1828 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_poll,
1829 MTK_NAPI_WEIGHT);
1830
1831 platform_set_drvdata(pdev, eth);
1832
1833 return 0;
1834
1835 err_free_dev:
1836 mtk_cleanup(eth);
1837 return err;
1838 }
1839
1840 static int mtk_remove(struct platform_device *pdev)
1841 {
1842 struct mtk_eth *eth = platform_get_drvdata(pdev);
1843
1844 clk_disable_unprepare(eth->clk_ethif);
1845 clk_disable_unprepare(eth->clk_esw);
1846 clk_disable_unprepare(eth->clk_gp1);
1847 clk_disable_unprepare(eth->clk_gp2);
1848
1849 netif_napi_del(&eth->rx_napi);
1850 mtk_cleanup(eth);
1851 platform_set_drvdata(pdev, NULL);
1852
1853 return 0;
1854 }
1855
1856 const struct of_device_id of_mtk_match[] = {
1857 { .compatible = "mediatek,mt7623-eth" },
1858 {},
1859 };
1860
1861 static struct platform_driver mtk_driver = {
1862 .probe = mtk_probe,
1863 .remove = mtk_remove,
1864 .driver = {
1865 .name = "mtk_soc_eth",
1866 .owner = THIS_MODULE,
1867 .of_match_table = of_mtk_match,
1868 },
1869 };
1870
1871 module_platform_driver(mtk_driver);
1872
1873 MODULE_LICENSE("GPL");
1874 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1875 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
Linux kernel - Deliverables
This page took 0.067527 seconds and 4 git commands to generate.