1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
15 #include <linux/of_device.h>
16 #include <linux/of_mdio.h>
17 #include <linux/of_net.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
20 #include <linux/clk.h>
21 #include <linux/if_vlan.h>
22 #include <linux/reset.h>
23 #include <linux/tcp.h>
25 #include "mtk_eth_soc.h"
27 static int mtk_msg_level
= -1;
28 module_param_named(msg_level
, mtk_msg_level
, int, 0);
29 MODULE_PARM_DESC(msg_level
, "Message level (-1=defaults,0=none,...,16=all)");
31 #define MTK_ETHTOOL_STAT(x) { #x, \
32 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
34 /* strings used by ethtool */
35 static const struct mtk_ethtool_stats
{
36 char str
[ETH_GSTRING_LEN
];
38 } mtk_ethtool_stats
[] = {
39 MTK_ETHTOOL_STAT(tx_bytes
),
40 MTK_ETHTOOL_STAT(tx_packets
),
41 MTK_ETHTOOL_STAT(tx_skip
),
42 MTK_ETHTOOL_STAT(tx_collisions
),
43 MTK_ETHTOOL_STAT(rx_bytes
),
44 MTK_ETHTOOL_STAT(rx_packets
),
45 MTK_ETHTOOL_STAT(rx_overflow
),
46 MTK_ETHTOOL_STAT(rx_fcs_errors
),
47 MTK_ETHTOOL_STAT(rx_short_errors
),
48 MTK_ETHTOOL_STAT(rx_long_errors
),
49 MTK_ETHTOOL_STAT(rx_checksum_errors
),
50 MTK_ETHTOOL_STAT(rx_flow_control_packets
),
53 static const char * const mtk_clks_source_name
[] = {
54 "ethif", "esw", "gp1", "gp2"
57 void mtk_w32(struct mtk_eth
*eth
, u32 val
, unsigned reg
)
59 __raw_writel(val
, eth
->base
+ reg
);
62 u32
mtk_r32(struct mtk_eth
*eth
, unsigned reg
)
64 return __raw_readl(eth
->base
+ reg
);
67 static int mtk_mdio_busy_wait(struct mtk_eth
*eth
)
69 unsigned long t_start
= jiffies
;
72 if (!(mtk_r32(eth
, MTK_PHY_IAC
) & PHY_IAC_ACCESS
))
74 if (time_after(jiffies
, t_start
+ PHY_IAC_TIMEOUT
))
79 dev_err(eth
->dev
, "mdio: MDIO timeout\n");
83 static u32
_mtk_mdio_write(struct mtk_eth
*eth
, u32 phy_addr
,
84 u32 phy_register
, u32 write_data
)
86 if (mtk_mdio_busy_wait(eth
))
91 mtk_w32(eth
, PHY_IAC_ACCESS
| PHY_IAC_START
| PHY_IAC_WRITE
|
92 (phy_register
<< PHY_IAC_REG_SHIFT
) |
93 (phy_addr
<< PHY_IAC_ADDR_SHIFT
) | write_data
,
96 if (mtk_mdio_busy_wait(eth
))
102 static u32
_mtk_mdio_read(struct mtk_eth
*eth
, int phy_addr
, int phy_reg
)
106 if (mtk_mdio_busy_wait(eth
))
109 mtk_w32(eth
, PHY_IAC_ACCESS
| PHY_IAC_START
| PHY_IAC_READ
|
110 (phy_reg
<< PHY_IAC_REG_SHIFT
) |
111 (phy_addr
<< PHY_IAC_ADDR_SHIFT
),
114 if (mtk_mdio_busy_wait(eth
))
117 d
= mtk_r32(eth
, MTK_PHY_IAC
) & 0xffff;
122 static int mtk_mdio_write(struct mii_bus
*bus
, int phy_addr
,
123 int phy_reg
, u16 val
)
125 struct mtk_eth
*eth
= bus
->priv
;
127 return _mtk_mdio_write(eth
, phy_addr
, phy_reg
, val
);
130 static int mtk_mdio_read(struct mii_bus
*bus
, int phy_addr
, int phy_reg
)
132 struct mtk_eth
*eth
= bus
->priv
;
134 return _mtk_mdio_read(eth
, phy_addr
, phy_reg
);
137 static void mtk_phy_link_adjust(struct net_device
*dev
)
139 struct mtk_mac
*mac
= netdev_priv(dev
);
140 u16 lcl_adv
= 0, rmt_adv
= 0;
142 u32 mcr
= MAC_MCR_MAX_RX_1536
| MAC_MCR_IPG_CFG
|
143 MAC_MCR_FORCE_MODE
| MAC_MCR_TX_EN
|
144 MAC_MCR_RX_EN
| MAC_MCR_BACKOFF_EN
|
147 switch (mac
->phy_dev
->speed
) {
149 mcr
|= MAC_MCR_SPEED_1000
;
152 mcr
|= MAC_MCR_SPEED_100
;
156 if (mac
->phy_dev
->link
)
157 mcr
|= MAC_MCR_FORCE_LINK
;
159 if (mac
->phy_dev
->duplex
) {
160 mcr
|= MAC_MCR_FORCE_DPX
;
162 if (mac
->phy_dev
->pause
)
163 rmt_adv
= LPA_PAUSE_CAP
;
164 if (mac
->phy_dev
->asym_pause
)
165 rmt_adv
|= LPA_PAUSE_ASYM
;
167 if (mac
->phy_dev
->advertising
& ADVERTISED_Pause
)
168 lcl_adv
|= ADVERTISE_PAUSE_CAP
;
169 if (mac
->phy_dev
->advertising
& ADVERTISED_Asym_Pause
)
170 lcl_adv
|= ADVERTISE_PAUSE_ASYM
;
172 flowctrl
= mii_resolve_flowctrl_fdx(lcl_adv
, rmt_adv
);
174 if (flowctrl
& FLOW_CTRL_TX
)
175 mcr
|= MAC_MCR_FORCE_TX_FC
;
176 if (flowctrl
& FLOW_CTRL_RX
)
177 mcr
|= MAC_MCR_FORCE_RX_FC
;
179 netif_dbg(mac
->hw
, link
, dev
, "rx pause %s, tx pause %s\n",
180 flowctrl
& FLOW_CTRL_RX
? "enabled" : "disabled",
181 flowctrl
& FLOW_CTRL_TX
? "enabled" : "disabled");
184 mtk_w32(mac
->hw
, mcr
, MTK_MAC_MCR(mac
->id
));
186 if (mac
->phy_dev
->link
)
187 netif_carrier_on(dev
);
189 netif_carrier_off(dev
);
192 static int mtk_phy_connect_node(struct mtk_eth
*eth
, struct mtk_mac
*mac
,
193 struct device_node
*phy_node
)
195 const __be32
*_addr
= NULL
;
196 struct phy_device
*phydev
;
199 _addr
= of_get_property(phy_node
, "reg", NULL
);
201 if (!_addr
|| (be32_to_cpu(*_addr
) >= 0x20)) {
202 pr_err("%s: invalid phy address\n", phy_node
->name
);
205 addr
= be32_to_cpu(*_addr
);
206 phy_mode
= of_get_phy_mode(phy_node
);
208 dev_err(eth
->dev
, "incorrect phy-mode %d\n", phy_mode
);
212 phydev
= of_phy_connect(eth
->netdev
[mac
->id
], phy_node
,
213 mtk_phy_link_adjust
, 0, phy_mode
);
215 dev_err(eth
->dev
, "could not connect to PHY\n");
220 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
221 mac
->id
, phydev_name(phydev
), phydev
->phy_id
,
224 mac
->phy_dev
= phydev
;
229 static int mtk_phy_connect(struct mtk_mac
*mac
)
231 struct mtk_eth
*eth
= mac
->hw
;
232 struct device_node
*np
;
235 np
= of_parse_phandle(mac
->of_node
, "phy-handle", 0);
236 if (!np
&& of_phy_is_fixed_link(mac
->of_node
))
237 if (!of_phy_register_fixed_link(mac
->of_node
))
238 np
= of_node_get(mac
->of_node
);
242 switch (of_get_phy_mode(np
)) {
243 case PHY_INTERFACE_MODE_RGMII_TXID
:
244 case PHY_INTERFACE_MODE_RGMII_RXID
:
245 case PHY_INTERFACE_MODE_RGMII_ID
:
246 case PHY_INTERFACE_MODE_RGMII
:
249 case PHY_INTERFACE_MODE_MII
:
252 case PHY_INTERFACE_MODE_REVMII
:
255 case PHY_INTERFACE_MODE_RMII
:
264 /* put the gmac into the right mode */
265 regmap_read(eth
->ethsys
, ETHSYS_SYSCFG0
, &val
);
266 val
&= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK
, mac
->id
);
267 val
|= SYSCFG0_GE_MODE(ge_mode
, mac
->id
);
268 regmap_write(eth
->ethsys
, ETHSYS_SYSCFG0
, val
);
270 mtk_phy_connect_node(eth
, mac
, np
);
271 mac
->phy_dev
->autoneg
= AUTONEG_ENABLE
;
272 mac
->phy_dev
->speed
= 0;
273 mac
->phy_dev
->duplex
= 0;
275 if (of_phy_is_fixed_link(mac
->of_node
))
276 mac
->phy_dev
->supported
|=
277 SUPPORTED_Pause
| SUPPORTED_Asym_Pause
;
279 mac
->phy_dev
->supported
&= PHY_GBIT_FEATURES
| SUPPORTED_Pause
|
280 SUPPORTED_Asym_Pause
;
281 mac
->phy_dev
->advertising
= mac
->phy_dev
->supported
|
283 phy_start_aneg(mac
->phy_dev
);
291 dev_err(eth
->dev
, "invalid phy_mode\n");
295 static int mtk_mdio_init(struct mtk_eth
*eth
)
297 struct device_node
*mii_np
;
300 mii_np
= of_get_child_by_name(eth
->dev
->of_node
, "mdio-bus");
302 dev_err(eth
->dev
, "no %s child node found", "mdio-bus");
306 if (!of_device_is_available(mii_np
)) {
311 eth
->mii_bus
= devm_mdiobus_alloc(eth
->dev
);
317 eth
->mii_bus
->name
= "mdio";
318 eth
->mii_bus
->read
= mtk_mdio_read
;
319 eth
->mii_bus
->write
= mtk_mdio_write
;
320 eth
->mii_bus
->priv
= eth
;
321 eth
->mii_bus
->parent
= eth
->dev
;
323 snprintf(eth
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s", mii_np
->name
);
324 ret
= of_mdiobus_register(eth
->mii_bus
, mii_np
);
331 static void mtk_mdio_cleanup(struct mtk_eth
*eth
)
336 mdiobus_unregister(eth
->mii_bus
);
339 static inline void mtk_irq_disable(struct mtk_eth
*eth
, u32 mask
)
344 spin_lock_irqsave(ð
->irq_lock
, flags
);
345 val
= mtk_r32(eth
, MTK_QDMA_INT_MASK
);
346 mtk_w32(eth
, val
& ~mask
, MTK_QDMA_INT_MASK
);
347 spin_unlock_irqrestore(ð
->irq_lock
, flags
);
350 static inline void mtk_irq_enable(struct mtk_eth
*eth
, u32 mask
)
355 spin_lock_irqsave(ð
->irq_lock
, flags
);
356 val
= mtk_r32(eth
, MTK_QDMA_INT_MASK
);
357 mtk_w32(eth
, val
| mask
, MTK_QDMA_INT_MASK
);
358 spin_unlock_irqrestore(ð
->irq_lock
, flags
);
361 static int mtk_set_mac_address(struct net_device
*dev
, void *p
)
363 int ret
= eth_mac_addr(dev
, p
);
364 struct mtk_mac
*mac
= netdev_priv(dev
);
365 const char *macaddr
= dev
->dev_addr
;
371 spin_lock_irqsave(&mac
->hw
->page_lock
, flags
);
372 mtk_w32(mac
->hw
, (macaddr
[0] << 8) | macaddr
[1],
373 MTK_GDMA_MAC_ADRH(mac
->id
));
374 mtk_w32(mac
->hw
, (macaddr
[2] << 24) | (macaddr
[3] << 16) |
375 (macaddr
[4] << 8) | macaddr
[5],
376 MTK_GDMA_MAC_ADRL(mac
->id
));
377 spin_unlock_irqrestore(&mac
->hw
->page_lock
, flags
);
382 void mtk_stats_update_mac(struct mtk_mac
*mac
)
384 struct mtk_hw_stats
*hw_stats
= mac
->hw_stats
;
385 unsigned int base
= MTK_GDM1_TX_GBCNT
;
388 base
+= hw_stats
->reg_offset
;
390 u64_stats_update_begin(&hw_stats
->syncp
);
392 hw_stats
->rx_bytes
+= mtk_r32(mac
->hw
, base
);
393 stats
= mtk_r32(mac
->hw
, base
+ 0x04);
395 hw_stats
->rx_bytes
+= (stats
<< 32);
396 hw_stats
->rx_packets
+= mtk_r32(mac
->hw
, base
+ 0x08);
397 hw_stats
->rx_overflow
+= mtk_r32(mac
->hw
, base
+ 0x10);
398 hw_stats
->rx_fcs_errors
+= mtk_r32(mac
->hw
, base
+ 0x14);
399 hw_stats
->rx_short_errors
+= mtk_r32(mac
->hw
, base
+ 0x18);
400 hw_stats
->rx_long_errors
+= mtk_r32(mac
->hw
, base
+ 0x1c);
401 hw_stats
->rx_checksum_errors
+= mtk_r32(mac
->hw
, base
+ 0x20);
402 hw_stats
->rx_flow_control_packets
+=
403 mtk_r32(mac
->hw
, base
+ 0x24);
404 hw_stats
->tx_skip
+= mtk_r32(mac
->hw
, base
+ 0x28);
405 hw_stats
->tx_collisions
+= mtk_r32(mac
->hw
, base
+ 0x2c);
406 hw_stats
->tx_bytes
+= mtk_r32(mac
->hw
, base
+ 0x30);
407 stats
= mtk_r32(mac
->hw
, base
+ 0x34);
409 hw_stats
->tx_bytes
+= (stats
<< 32);
410 hw_stats
->tx_packets
+= mtk_r32(mac
->hw
, base
+ 0x38);
411 u64_stats_update_end(&hw_stats
->syncp
);
414 static void mtk_stats_update(struct mtk_eth
*eth
)
418 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
419 if (!eth
->mac
[i
] || !eth
->mac
[i
]->hw_stats
)
421 if (spin_trylock(ð
->mac
[i
]->hw_stats
->stats_lock
)) {
422 mtk_stats_update_mac(eth
->mac
[i
]);
423 spin_unlock(ð
->mac
[i
]->hw_stats
->stats_lock
);
428 static struct rtnl_link_stats64
*mtk_get_stats64(struct net_device
*dev
,
429 struct rtnl_link_stats64
*storage
)
431 struct mtk_mac
*mac
= netdev_priv(dev
);
432 struct mtk_hw_stats
*hw_stats
= mac
->hw_stats
;
435 if (netif_running(dev
) && netif_device_present(dev
)) {
436 if (spin_trylock(&hw_stats
->stats_lock
)) {
437 mtk_stats_update_mac(mac
);
438 spin_unlock(&hw_stats
->stats_lock
);
443 start
= u64_stats_fetch_begin_irq(&hw_stats
->syncp
);
444 storage
->rx_packets
= hw_stats
->rx_packets
;
445 storage
->tx_packets
= hw_stats
->tx_packets
;
446 storage
->rx_bytes
= hw_stats
->rx_bytes
;
447 storage
->tx_bytes
= hw_stats
->tx_bytes
;
448 storage
->collisions
= hw_stats
->tx_collisions
;
449 storage
->rx_length_errors
= hw_stats
->rx_short_errors
+
450 hw_stats
->rx_long_errors
;
451 storage
->rx_over_errors
= hw_stats
->rx_overflow
;
452 storage
->rx_crc_errors
= hw_stats
->rx_fcs_errors
;
453 storage
->rx_errors
= hw_stats
->rx_checksum_errors
;
454 storage
->tx_aborted_errors
= hw_stats
->tx_skip
;
455 } while (u64_stats_fetch_retry_irq(&hw_stats
->syncp
, start
));
457 storage
->tx_errors
= dev
->stats
.tx_errors
;
458 storage
->rx_dropped
= dev
->stats
.rx_dropped
;
459 storage
->tx_dropped
= dev
->stats
.tx_dropped
;
464 static inline int mtk_max_frag_size(int mtu
)
466 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
467 if (mtu
+ MTK_RX_ETH_HLEN
< MTK_MAX_RX_LENGTH
)
468 mtu
= MTK_MAX_RX_LENGTH
- MTK_RX_ETH_HLEN
;
470 return SKB_DATA_ALIGN(MTK_RX_HLEN
+ mtu
) +
471 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
474 static inline int mtk_max_buf_size(int frag_size
)
476 int buf_size
= frag_size
- NET_SKB_PAD
- NET_IP_ALIGN
-
477 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
479 WARN_ON(buf_size
< MTK_MAX_RX_LENGTH
);
484 static inline void mtk_rx_get_desc(struct mtk_rx_dma
*rxd
,
485 struct mtk_rx_dma
*dma_rxd
)
487 rxd
->rxd1
= READ_ONCE(dma_rxd
->rxd1
);
488 rxd
->rxd2
= READ_ONCE(dma_rxd
->rxd2
);
489 rxd
->rxd3
= READ_ONCE(dma_rxd
->rxd3
);
490 rxd
->rxd4
= READ_ONCE(dma_rxd
->rxd4
);
493 /* the qdma core needs scratch memory to be setup */
494 static int mtk_init_fq_dma(struct mtk_eth
*eth
)
496 dma_addr_t phy_ring_tail
;
497 int cnt
= MTK_DMA_SIZE
;
501 eth
->scratch_ring
= dma_alloc_coherent(eth
->dev
,
502 cnt
* sizeof(struct mtk_tx_dma
),
503 ð
->phy_scratch_ring
,
504 GFP_ATOMIC
| __GFP_ZERO
);
505 if (unlikely(!eth
->scratch_ring
))
508 eth
->scratch_head
= kcalloc(cnt
, MTK_QDMA_PAGE_SIZE
,
510 if (unlikely(!eth
->scratch_head
))
513 dma_addr
= dma_map_single(eth
->dev
,
514 eth
->scratch_head
, cnt
* MTK_QDMA_PAGE_SIZE
,
516 if (unlikely(dma_mapping_error(eth
->dev
, dma_addr
)))
519 memset(eth
->scratch_ring
, 0x0, sizeof(struct mtk_tx_dma
) * cnt
);
520 phy_ring_tail
= eth
->phy_scratch_ring
+
521 (sizeof(struct mtk_tx_dma
) * (cnt
- 1));
523 for (i
= 0; i
< cnt
; i
++) {
524 eth
->scratch_ring
[i
].txd1
=
525 (dma_addr
+ (i
* MTK_QDMA_PAGE_SIZE
));
527 eth
->scratch_ring
[i
].txd2
= (eth
->phy_scratch_ring
+
528 ((i
+ 1) * sizeof(struct mtk_tx_dma
)));
529 eth
->scratch_ring
[i
].txd3
= TX_DMA_SDL(MTK_QDMA_PAGE_SIZE
);
532 mtk_w32(eth
, eth
->phy_scratch_ring
, MTK_QDMA_FQ_HEAD
);
533 mtk_w32(eth
, phy_ring_tail
, MTK_QDMA_FQ_TAIL
);
534 mtk_w32(eth
, (cnt
<< 16) | cnt
, MTK_QDMA_FQ_CNT
);
535 mtk_w32(eth
, MTK_QDMA_PAGE_SIZE
<< 16, MTK_QDMA_FQ_BLEN
);
540 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring
*ring
, u32 desc
)
542 void *ret
= ring
->dma
;
544 return ret
+ (desc
- ring
->phys
);
547 static inline struct mtk_tx_buf
*mtk_desc_to_tx_buf(struct mtk_tx_ring
*ring
,
548 struct mtk_tx_dma
*txd
)
550 int idx
= txd
- ring
->dma
;
552 return &ring
->buf
[idx
];
555 static void mtk_tx_unmap(struct mtk_eth
*eth
, struct mtk_tx_buf
*tx_buf
)
557 if (tx_buf
->flags
& MTK_TX_FLAGS_SINGLE0
) {
558 dma_unmap_single(eth
->dev
,
559 dma_unmap_addr(tx_buf
, dma_addr0
),
560 dma_unmap_len(tx_buf
, dma_len0
),
562 } else if (tx_buf
->flags
& MTK_TX_FLAGS_PAGE0
) {
563 dma_unmap_page(eth
->dev
,
564 dma_unmap_addr(tx_buf
, dma_addr0
),
565 dma_unmap_len(tx_buf
, dma_len0
),
570 (tx_buf
->skb
!= (struct sk_buff
*)MTK_DMA_DUMMY_DESC
))
571 dev_kfree_skb_any(tx_buf
->skb
);
575 static int mtk_tx_map(struct sk_buff
*skb
, struct net_device
*dev
,
576 int tx_num
, struct mtk_tx_ring
*ring
, bool gso
)
578 struct mtk_mac
*mac
= netdev_priv(dev
);
579 struct mtk_eth
*eth
= mac
->hw
;
580 struct mtk_tx_dma
*itxd
, *txd
;
581 struct mtk_tx_buf
*tx_buf
;
582 dma_addr_t mapped_addr
;
583 unsigned int nr_frags
;
587 itxd
= ring
->next_free
;
588 if (itxd
== ring
->last_free
)
591 /* set the forward port */
592 fport
= (mac
->id
+ 1) << TX_DMA_FPORT_SHIFT
;
595 tx_buf
= mtk_desc_to_tx_buf(ring
, itxd
);
596 memset(tx_buf
, 0, sizeof(*tx_buf
));
601 /* TX Checksum offload */
602 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
603 txd4
|= TX_DMA_CHKSUM
;
605 /* VLAN header offload */
606 if (skb_vlan_tag_present(skb
))
607 txd4
|= TX_DMA_INS_VLAN
| skb_vlan_tag_get(skb
);
609 mapped_addr
= dma_map_single(eth
->dev
, skb
->data
,
610 skb_headlen(skb
), DMA_TO_DEVICE
);
611 if (unlikely(dma_mapping_error(eth
->dev
, mapped_addr
)))
614 WRITE_ONCE(itxd
->txd1
, mapped_addr
);
615 tx_buf
->flags
|= MTK_TX_FLAGS_SINGLE0
;
616 dma_unmap_addr_set(tx_buf
, dma_addr0
, mapped_addr
);
617 dma_unmap_len_set(tx_buf
, dma_len0
, skb_headlen(skb
));
621 nr_frags
= skb_shinfo(skb
)->nr_frags
;
622 for (i
= 0; i
< nr_frags
; i
++) {
623 struct skb_frag_struct
*frag
= &skb_shinfo(skb
)->frags
[i
];
624 unsigned int offset
= 0;
625 int frag_size
= skb_frag_size(frag
);
628 bool last_frag
= false;
629 unsigned int frag_map_size
;
631 txd
= mtk_qdma_phys_to_virt(ring
, txd
->txd2
);
632 if (txd
== ring
->last_free
)
636 frag_map_size
= min(frag_size
, MTK_TX_DMA_BUF_LEN
);
637 mapped_addr
= skb_frag_dma_map(eth
->dev
, frag
, offset
,
640 if (unlikely(dma_mapping_error(eth
->dev
, mapped_addr
)))
643 if (i
== nr_frags
- 1 &&
644 (frag_size
- frag_map_size
) == 0)
647 WRITE_ONCE(txd
->txd1
, mapped_addr
);
648 WRITE_ONCE(txd
->txd3
, (TX_DMA_SWC
|
649 TX_DMA_PLEN0(frag_map_size
) |
650 last_frag
* TX_DMA_LS0
));
651 WRITE_ONCE(txd
->txd4
, fport
);
653 tx_buf
->skb
= (struct sk_buff
*)MTK_DMA_DUMMY_DESC
;
654 tx_buf
= mtk_desc_to_tx_buf(ring
, txd
);
655 memset(tx_buf
, 0, sizeof(*tx_buf
));
657 tx_buf
->flags
|= MTK_TX_FLAGS_PAGE0
;
658 dma_unmap_addr_set(tx_buf
, dma_addr0
, mapped_addr
);
659 dma_unmap_len_set(tx_buf
, dma_len0
, frag_map_size
);
660 frag_size
-= frag_map_size
;
661 offset
+= frag_map_size
;
665 /* store skb to cleanup */
668 WRITE_ONCE(itxd
->txd4
, txd4
);
669 WRITE_ONCE(itxd
->txd3
, (TX_DMA_SWC
| TX_DMA_PLEN0(skb_headlen(skb
)) |
670 (!nr_frags
* TX_DMA_LS0
)));
672 netdev_sent_queue(dev
, skb
->len
);
673 skb_tx_timestamp(skb
);
675 ring
->next_free
= mtk_qdma_phys_to_virt(ring
, txd
->txd2
);
676 atomic_sub(n_desc
, &ring
->free_count
);
678 /* make sure that all changes to the dma ring are flushed before we
683 if (netif_xmit_stopped(netdev_get_tx_queue(dev
, 0)) || !skb
->xmit_more
)
684 mtk_w32(eth
, txd
->txd2
, MTK_QTX_CTX_PTR
);
690 tx_buf
= mtk_desc_to_tx_buf(ring
, itxd
);
693 mtk_tx_unmap(eth
, tx_buf
);
695 itxd
->txd3
= TX_DMA_LS0
| TX_DMA_OWNER_CPU
;
696 itxd
= mtk_qdma_phys_to_virt(ring
, itxd
->txd2
);
697 } while (itxd
!= txd
);
702 static inline int mtk_cal_txd_req(struct sk_buff
*skb
)
705 struct skb_frag_struct
*frag
;
708 if (skb_is_gso(skb
)) {
709 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
710 frag
= &skb_shinfo(skb
)->frags
[i
];
711 nfrags
+= DIV_ROUND_UP(frag
->size
, MTK_TX_DMA_BUF_LEN
);
714 nfrags
+= skb_shinfo(skb
)->nr_frags
;
720 static int mtk_queue_stopped(struct mtk_eth
*eth
)
724 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
727 if (netif_queue_stopped(eth
->netdev
[i
]))
734 static void mtk_wake_queue(struct mtk_eth
*eth
)
738 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
741 netif_wake_queue(eth
->netdev
[i
]);
745 static void mtk_stop_queue(struct mtk_eth
*eth
)
749 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
752 netif_stop_queue(eth
->netdev
[i
]);
756 static int mtk_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
758 struct mtk_mac
*mac
= netdev_priv(dev
);
759 struct mtk_eth
*eth
= mac
->hw
;
760 struct mtk_tx_ring
*ring
= ð
->tx_ring
;
761 struct net_device_stats
*stats
= &dev
->stats
;
766 /* normally we can rely on the stack not calling this more than once,
767 * however we have 2 queues running on the same ring so we need to lock
770 spin_lock_irqsave(ð
->page_lock
, flags
);
772 tx_num
= mtk_cal_txd_req(skb
);
773 if (unlikely(atomic_read(&ring
->free_count
) <= tx_num
)) {
775 netif_err(eth
, tx_queued
, dev
,
776 "Tx Ring full when queue awake!\n");
777 spin_unlock_irqrestore(ð
->page_lock
, flags
);
778 return NETDEV_TX_BUSY
;
781 /* TSO: fill MSS info in tcp checksum field */
782 if (skb_is_gso(skb
)) {
783 if (skb_cow_head(skb
, 0)) {
784 netif_warn(eth
, tx_err
, dev
,
785 "GSO expand head fail.\n");
789 if (skb_shinfo(skb
)->gso_type
&
790 (SKB_GSO_TCPV4
| SKB_GSO_TCPV6
)) {
792 tcp_hdr(skb
)->check
= htons(skb_shinfo(skb
)->gso_size
);
796 if (mtk_tx_map(skb
, dev
, tx_num
, ring
, gso
) < 0)
799 if (unlikely(atomic_read(&ring
->free_count
) <= ring
->thresh
))
802 spin_unlock_irqrestore(ð
->page_lock
, flags
);
807 spin_unlock_irqrestore(ð
->page_lock
, flags
);
813 static int mtk_poll_rx(struct napi_struct
*napi
, int budget
,
816 struct mtk_rx_ring
*ring
= ð
->rx_ring
;
817 int idx
= ring
->calc_idx
;
820 struct mtk_rx_dma
*rxd
, trxd
;
823 while (done
< budget
) {
824 struct net_device
*netdev
;
829 idx
= NEXT_RX_DESP_IDX(idx
);
830 rxd
= &ring
->dma
[idx
];
831 data
= ring
->data
[idx
];
833 mtk_rx_get_desc(&trxd
, rxd
);
834 if (!(trxd
.rxd2
& RX_DMA_DONE
))
837 /* find out which mac the packet come from. values start at 1 */
838 mac
= (trxd
.rxd4
>> RX_DMA_FPORT_SHIFT
) &
842 netdev
= eth
->netdev
[mac
];
844 /* alloc new buffer */
845 new_data
= napi_alloc_frag(ring
->frag_size
);
846 if (unlikely(!new_data
)) {
847 netdev
->stats
.rx_dropped
++;
850 dma_addr
= dma_map_single(eth
->dev
,
851 new_data
+ NET_SKB_PAD
,
854 if (unlikely(dma_mapping_error(eth
->dev
, dma_addr
))) {
855 skb_free_frag(new_data
);
856 netdev
->stats
.rx_dropped
++;
861 skb
= build_skb(data
, ring
->frag_size
);
862 if (unlikely(!skb
)) {
863 skb_free_frag(new_data
);
864 netdev
->stats
.rx_dropped
++;
867 skb_reserve(skb
, NET_SKB_PAD
+ NET_IP_ALIGN
);
869 dma_unmap_single(eth
->dev
, trxd
.rxd1
,
870 ring
->buf_size
, DMA_FROM_DEVICE
);
871 pktlen
= RX_DMA_GET_PLEN0(trxd
.rxd2
);
873 skb_put(skb
, pktlen
);
874 if (trxd
.rxd4
& RX_DMA_L4_VALID
)
875 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
877 skb_checksum_none_assert(skb
);
878 skb
->protocol
= eth_type_trans(skb
, netdev
);
880 if (netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
&&
881 RX_DMA_VID(trxd
.rxd3
))
882 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
),
883 RX_DMA_VID(trxd
.rxd3
));
884 napi_gro_receive(napi
, skb
);
886 ring
->data
[idx
] = new_data
;
887 rxd
->rxd1
= (unsigned int)dma_addr
;
890 rxd
->rxd2
= RX_DMA_PLEN0(ring
->buf_size
);
892 ring
->calc_idx
= idx
;
893 /* make sure that all changes to the dma ring are flushed before
897 mtk_w32(eth
, ring
->calc_idx
, MTK_QRX_CRX_IDX0
);
902 mtk_w32(eth
, MTK_RX_DONE_INT
, MTK_QMTK_INT_STATUS
);
907 static int mtk_poll_tx(struct mtk_eth
*eth
, int budget
)
909 struct mtk_tx_ring
*ring
= ð
->tx_ring
;
910 struct mtk_tx_dma
*desc
;
912 struct mtk_tx_buf
*tx_buf
;
913 unsigned int done
[MTK_MAX_DEVS
];
914 unsigned int bytes
[MTK_MAX_DEVS
];
916 static int condition
;
919 memset(done
, 0, sizeof(done
));
920 memset(bytes
, 0, sizeof(bytes
));
922 cpu
= mtk_r32(eth
, MTK_QTX_CRX_PTR
);
923 dma
= mtk_r32(eth
, MTK_QTX_DRX_PTR
);
925 desc
= mtk_qdma_phys_to_virt(ring
, cpu
);
927 while ((cpu
!= dma
) && budget
) {
928 u32 next_cpu
= desc
->txd2
;
931 desc
= mtk_qdma_phys_to_virt(ring
, desc
->txd2
);
932 if ((desc
->txd3
& TX_DMA_OWNER_CPU
) == 0)
935 mac
= (desc
->txd4
>> TX_DMA_FPORT_SHIFT
) &
939 tx_buf
= mtk_desc_to_tx_buf(ring
, desc
);
946 if (skb
!= (struct sk_buff
*)MTK_DMA_DUMMY_DESC
) {
947 bytes
[mac
] += skb
->len
;
951 mtk_tx_unmap(eth
, tx_buf
);
953 ring
->last_free
= desc
;
954 atomic_inc(&ring
->free_count
);
959 mtk_w32(eth
, cpu
, MTK_QTX_CRX_PTR
);
961 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
962 if (!eth
->netdev
[i
] || !done
[i
])
964 netdev_completed_queue(eth
->netdev
[i
], done
[i
], bytes
[i
]);
968 if (mtk_queue_stopped(eth
) &&
969 (atomic_read(&ring
->free_count
) > ring
->thresh
))
975 static void mtk_handle_status_irq(struct mtk_eth
*eth
)
977 u32 status2
= mtk_r32(eth
, MTK_INT_STATUS2
);
979 if (unlikely(status2
& (MTK_GDM1_AF
| MTK_GDM2_AF
))) {
980 mtk_stats_update(eth
);
981 mtk_w32(eth
, (MTK_GDM1_AF
| MTK_GDM2_AF
),
986 static int mtk_napi_tx(struct napi_struct
*napi
, int budget
)
988 struct mtk_eth
*eth
= container_of(napi
, struct mtk_eth
, tx_napi
);
992 mtk_handle_status_irq(eth
);
993 mtk_w32(eth
, MTK_TX_DONE_INT
, MTK_QMTK_INT_STATUS
);
994 tx_done
= mtk_poll_tx(eth
, budget
);
996 if (unlikely(netif_msg_intr(eth
))) {
997 status
= mtk_r32(eth
, MTK_QMTK_INT_STATUS
);
998 mask
= mtk_r32(eth
, MTK_QDMA_INT_MASK
);
1000 "done tx %d, intr 0x%08x/0x%x\n",
1001 tx_done
, status
, mask
);
1004 if (tx_done
== budget
)
1007 status
= mtk_r32(eth
, MTK_QMTK_INT_STATUS
);
1008 if (status
& MTK_TX_DONE_INT
)
1011 napi_complete(napi
);
1012 mtk_irq_enable(eth
, MTK_TX_DONE_INT
);
1017 static int mtk_napi_rx(struct napi_struct
*napi
, int budget
)
1019 struct mtk_eth
*eth
= container_of(napi
, struct mtk_eth
, rx_napi
);
1023 mtk_handle_status_irq(eth
);
1024 mtk_w32(eth
, MTK_RX_DONE_INT
, MTK_QMTK_INT_STATUS
);
1025 rx_done
= mtk_poll_rx(napi
, budget
, eth
);
1027 if (unlikely(netif_msg_intr(eth
))) {
1028 status
= mtk_r32(eth
, MTK_QMTK_INT_STATUS
);
1029 mask
= mtk_r32(eth
, MTK_QDMA_INT_MASK
);
1031 "done rx %d, intr 0x%08x/0x%x\n",
1032 rx_done
, status
, mask
);
1035 if (rx_done
== budget
)
1038 status
= mtk_r32(eth
, MTK_QMTK_INT_STATUS
);
1039 if (status
& MTK_RX_DONE_INT
)
1042 napi_complete(napi
);
1043 mtk_irq_enable(eth
, MTK_RX_DONE_INT
);
1048 static int mtk_tx_alloc(struct mtk_eth
*eth
)
1050 struct mtk_tx_ring
*ring
= ð
->tx_ring
;
1051 int i
, sz
= sizeof(*ring
->dma
);
1053 ring
->buf
= kcalloc(MTK_DMA_SIZE
, sizeof(*ring
->buf
),
1058 ring
->dma
= dma_alloc_coherent(eth
->dev
,
1061 GFP_ATOMIC
| __GFP_ZERO
);
1065 memset(ring
->dma
, 0, MTK_DMA_SIZE
* sz
);
1066 for (i
= 0; i
< MTK_DMA_SIZE
; i
++) {
1067 int next
= (i
+ 1) % MTK_DMA_SIZE
;
1068 u32 next_ptr
= ring
->phys
+ next
* sz
;
1070 ring
->dma
[i
].txd2
= next_ptr
;
1071 ring
->dma
[i
].txd3
= TX_DMA_LS0
| TX_DMA_OWNER_CPU
;
1074 atomic_set(&ring
->free_count
, MTK_DMA_SIZE
- 2);
1075 ring
->next_free
= &ring
->dma
[0];
1076 ring
->last_free
= &ring
->dma
[MTK_DMA_SIZE
- 1];
1077 ring
->thresh
= MAX_SKB_FRAGS
;
1079 /* make sure that all changes to the dma ring are flushed before we
1084 mtk_w32(eth
, ring
->phys
, MTK_QTX_CTX_PTR
);
1085 mtk_w32(eth
, ring
->phys
, MTK_QTX_DTX_PTR
);
1087 ring
->phys
+ ((MTK_DMA_SIZE
- 1) * sz
),
1090 ring
->phys
+ ((MTK_DMA_SIZE
- 1) * sz
),
1099 static void mtk_tx_clean(struct mtk_eth
*eth
)
1101 struct mtk_tx_ring
*ring
= ð
->tx_ring
;
1105 for (i
= 0; i
< MTK_DMA_SIZE
; i
++)
1106 mtk_tx_unmap(eth
, &ring
->buf
[i
]);
1112 dma_free_coherent(eth
->dev
,
1113 MTK_DMA_SIZE
* sizeof(*ring
->dma
),
1120 static int mtk_rx_alloc(struct mtk_eth
*eth
)
1122 struct mtk_rx_ring
*ring
= ð
->rx_ring
;
1125 ring
->frag_size
= mtk_max_frag_size(ETH_DATA_LEN
);
1126 ring
->buf_size
= mtk_max_buf_size(ring
->frag_size
);
1127 ring
->data
= kcalloc(MTK_DMA_SIZE
, sizeof(*ring
->data
),
1132 for (i
= 0; i
< MTK_DMA_SIZE
; i
++) {
1133 ring
->data
[i
] = netdev_alloc_frag(ring
->frag_size
);
1138 ring
->dma
= dma_alloc_coherent(eth
->dev
,
1139 MTK_DMA_SIZE
* sizeof(*ring
->dma
),
1141 GFP_ATOMIC
| __GFP_ZERO
);
1145 for (i
= 0; i
< MTK_DMA_SIZE
; i
++) {
1146 dma_addr_t dma_addr
= dma_map_single(eth
->dev
,
1147 ring
->data
[i
] + NET_SKB_PAD
,
1150 if (unlikely(dma_mapping_error(eth
->dev
, dma_addr
)))
1152 ring
->dma
[i
].rxd1
= (unsigned int)dma_addr
;
1154 ring
->dma
[i
].rxd2
= RX_DMA_PLEN0(ring
->buf_size
);
1156 ring
->calc_idx
= MTK_DMA_SIZE
- 1;
1157 /* make sure that all changes to the dma ring are flushed before we
1162 mtk_w32(eth
, eth
->rx_ring
.phys
, MTK_QRX_BASE_PTR0
);
1163 mtk_w32(eth
, MTK_DMA_SIZE
, MTK_QRX_MAX_CNT0
);
1164 mtk_w32(eth
, eth
->rx_ring
.calc_idx
, MTK_QRX_CRX_IDX0
);
1165 mtk_w32(eth
, MTK_PST_DRX_IDX0
, MTK_QDMA_RST_IDX
);
1166 mtk_w32(eth
, (QDMA_RES_THRES
<< 8) | QDMA_RES_THRES
, MTK_QTX_CFG(0));
1171 static void mtk_rx_clean(struct mtk_eth
*eth
)
1173 struct mtk_rx_ring
*ring
= ð
->rx_ring
;
1176 if (ring
->data
&& ring
->dma
) {
1177 for (i
= 0; i
< MTK_DMA_SIZE
; i
++) {
1180 if (!ring
->dma
[i
].rxd1
)
1182 dma_unmap_single(eth
->dev
,
1186 skb_free_frag(ring
->data
[i
]);
1193 dma_free_coherent(eth
->dev
,
1194 MTK_DMA_SIZE
* sizeof(*ring
->dma
),
1201 /* wait for DMA to finish whatever it is doing before we start using it again */
1202 static int mtk_dma_busy_wait(struct mtk_eth
*eth
)
1204 unsigned long t_start
= jiffies
;
1207 if (!(mtk_r32(eth
, MTK_QDMA_GLO_CFG
) &
1208 (MTK_RX_DMA_BUSY
| MTK_TX_DMA_BUSY
)))
1210 if (time_after(jiffies
, t_start
+ MTK_DMA_BUSY_TIMEOUT
))
1214 dev_err(eth
->dev
, "DMA init timeout\n");
1218 static int mtk_dma_init(struct mtk_eth
*eth
)
1222 if (mtk_dma_busy_wait(eth
))
1225 /* QDMA needs scratch memory for internal reordering of the
1228 err
= mtk_init_fq_dma(eth
);
1232 err
= mtk_tx_alloc(eth
);
1236 err
= mtk_rx_alloc(eth
);
1240 /* Enable random early drop and set drop threshold automatically */
1241 mtk_w32(eth
, FC_THRES_DROP_MODE
| FC_THRES_DROP_EN
| FC_THRES_MIN
,
1243 mtk_w32(eth
, 0x0, MTK_QDMA_HRED2
);
1248 static void mtk_dma_free(struct mtk_eth
*eth
)
1252 for (i
= 0; i
< MTK_MAC_COUNT
; i
++)
1254 netdev_reset_queue(eth
->netdev
[i
]);
1255 if (eth
->scratch_ring
) {
1256 dma_free_coherent(eth
->dev
,
1257 MTK_DMA_SIZE
* sizeof(struct mtk_tx_dma
),
1259 eth
->phy_scratch_ring
);
1260 eth
->scratch_ring
= NULL
;
1261 eth
->phy_scratch_ring
= 0;
1265 kfree(eth
->scratch_head
);
1268 static void mtk_tx_timeout(struct net_device
*dev
)
1270 struct mtk_mac
*mac
= netdev_priv(dev
);
1271 struct mtk_eth
*eth
= mac
->hw
;
1273 eth
->netdev
[mac
->id
]->stats
.tx_errors
++;
1274 netif_err(eth
, tx_err
, dev
,
1275 "transmit timed out\n");
1276 schedule_work(ð
->pending_work
);
1279 static irqreturn_t
mtk_handle_irq_rx(int irq
, void *_eth
)
1281 struct mtk_eth
*eth
= _eth
;
1283 if (likely(napi_schedule_prep(ð
->rx_napi
))) {
1284 __napi_schedule(ð
->rx_napi
);
1285 mtk_irq_disable(eth
, MTK_RX_DONE_INT
);
1291 static irqreturn_t
mtk_handle_irq_tx(int irq
, void *_eth
)
1293 struct mtk_eth
*eth
= _eth
;
1295 if (likely(napi_schedule_prep(ð
->tx_napi
))) {
1296 __napi_schedule(ð
->tx_napi
);
1297 mtk_irq_disable(eth
, MTK_TX_DONE_INT
);
1303 #ifdef CONFIG_NET_POLL_CONTROLLER
1304 static void mtk_poll_controller(struct net_device
*dev
)
1306 struct mtk_mac
*mac
= netdev_priv(dev
);
1307 struct mtk_eth
*eth
= mac
->hw
;
1308 u32 int_mask
= MTK_TX_DONE_INT
| MTK_RX_DONE_INT
;
1310 mtk_irq_disable(eth
, int_mask
);
1311 mtk_handle_irq_rx(eth
->irq
[2], dev
);
1312 mtk_irq_enable(eth
, int_mask
);
1316 static int mtk_start_dma(struct mtk_eth
*eth
)
1320 err
= mtk_dma_init(eth
);
1327 MTK_TX_WB_DDONE
| MTK_RX_DMA_EN
| MTK_TX_DMA_EN
|
1328 MTK_RX_2B_OFFSET
| MTK_DMA_SIZE_16DWORDS
|
1329 MTK_RX_BT_32DWORDS
| MTK_NDP_CO_PRO
,
1335 static int mtk_open(struct net_device
*dev
)
1337 struct mtk_mac
*mac
= netdev_priv(dev
);
1338 struct mtk_eth
*eth
= mac
->hw
;
1340 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1341 if (!atomic_read(ð
->dma_refcnt
)) {
1342 int err
= mtk_start_dma(eth
);
1347 napi_enable(ð
->tx_napi
);
1348 napi_enable(ð
->rx_napi
);
1349 mtk_irq_enable(eth
, MTK_TX_DONE_INT
| MTK_RX_DONE_INT
);
1351 atomic_inc(ð
->dma_refcnt
);
1353 phy_start(mac
->phy_dev
);
1354 netif_start_queue(dev
);
1359 static void mtk_stop_dma(struct mtk_eth
*eth
, u32 glo_cfg
)
1361 unsigned long flags
;
1365 /* stop the dma engine */
1366 spin_lock_irqsave(ð
->page_lock
, flags
);
1367 val
= mtk_r32(eth
, glo_cfg
);
1368 mtk_w32(eth
, val
& ~(MTK_TX_WB_DDONE
| MTK_RX_DMA_EN
| MTK_TX_DMA_EN
),
1370 spin_unlock_irqrestore(ð
->page_lock
, flags
);
1372 /* wait for dma stop */
1373 for (i
= 0; i
< 10; i
++) {
1374 val
= mtk_r32(eth
, glo_cfg
);
1375 if (val
& (MTK_TX_DMA_BUSY
| MTK_RX_DMA_BUSY
)) {
1383 static int mtk_stop(struct net_device
*dev
)
1385 struct mtk_mac
*mac
= netdev_priv(dev
);
1386 struct mtk_eth
*eth
= mac
->hw
;
1388 netif_tx_disable(dev
);
1389 phy_stop(mac
->phy_dev
);
1391 /* only shutdown DMA if this is the last user */
1392 if (!atomic_dec_and_test(ð
->dma_refcnt
))
1395 mtk_irq_disable(eth
, MTK_TX_DONE_INT
| MTK_RX_DONE_INT
);
1396 napi_disable(ð
->tx_napi
);
1397 napi_disable(ð
->rx_napi
);
1399 mtk_stop_dma(eth
, MTK_QDMA_GLO_CFG
);
1406 static int __init
mtk_hw_init(struct mtk_eth
*eth
)
1410 /* reset the frame engine */
1411 reset_control_assert(eth
->rstc
);
1412 usleep_range(10, 20);
1413 reset_control_deassert(eth
->rstc
);
1414 usleep_range(10, 20);
1416 /* Set GE2 driving and slew rate */
1417 regmap_write(eth
->pctl
, GPIO_DRV_SEL10
, 0xa00);
1420 regmap_write(eth
->pctl
, GPIO_OD33_CTRL8
, 0x5);
1423 regmap_write(eth
->pctl
, GPIO_BIAS_CTRL
, 0x0);
1425 /* GE1, Force 1000M/FD, FC ON */
1426 mtk_w32(eth
, MAC_MCR_FIXED_LINK
, MTK_MAC_MCR(0));
1428 /* GE2, Force 1000M/FD, FC ON */
1429 mtk_w32(eth
, MAC_MCR_FIXED_LINK
, MTK_MAC_MCR(1));
1431 /* Enable RX VLan Offloading */
1432 mtk_w32(eth
, 1, MTK_CDMP_EG_CTRL
);
1434 err
= devm_request_irq(eth
->dev
, eth
->irq
[1], mtk_handle_irq_tx
, 0,
1435 dev_name(eth
->dev
), eth
);
1438 err
= devm_request_irq(eth
->dev
, eth
->irq
[2], mtk_handle_irq_rx
, 0,
1439 dev_name(eth
->dev
), eth
);
1443 err
= mtk_mdio_init(eth
);
1447 /* disable delay and normal interrupt */
1448 mtk_w32(eth
, 0, MTK_QDMA_DELAY_INT
);
1449 mtk_irq_disable(eth
, ~0);
1450 mtk_w32(eth
, RST_GL_PSE
, MTK_RST_GL
);
1451 mtk_w32(eth
, 0, MTK_RST_GL
);
1453 /* FE int grouping */
1454 mtk_w32(eth
, MTK_TX_DONE_INT
, MTK_PDMA_INT_GRP1
);
1455 mtk_w32(eth
, MTK_RX_DONE_INT
, MTK_PDMA_INT_GRP2
);
1456 mtk_w32(eth
, MTK_TX_DONE_INT
, MTK_QDMA_INT_GRP1
);
1457 mtk_w32(eth
, MTK_RX_DONE_INT
, MTK_QDMA_INT_GRP2
);
1458 mtk_w32(eth
, 0x21021000, MTK_FE_INT_GRP
);
1460 for (i
= 0; i
< 2; i
++) {
1461 u32 val
= mtk_r32(eth
, MTK_GDMA_FWD_CFG(i
));
1463 /* setup the forward port to send frame to QDMA */
1467 /* Enable RX checksum */
1468 val
|= MTK_GDMA_ICS_EN
| MTK_GDMA_TCS_EN
| MTK_GDMA_UCS_EN
;
1470 /* setup the mac dma */
1471 mtk_w32(eth
, val
, MTK_GDMA_FWD_CFG(i
));
1477 static int __init
mtk_init(struct net_device
*dev
)
1479 struct mtk_mac
*mac
= netdev_priv(dev
);
1480 struct mtk_eth
*eth
= mac
->hw
;
1481 const char *mac_addr
;
1483 mac_addr
= of_get_mac_address(mac
->of_node
);
1485 ether_addr_copy(dev
->dev_addr
, mac_addr
);
1487 /* If the mac address is invalid, use random mac address */
1488 if (!is_valid_ether_addr(dev
->dev_addr
)) {
1489 random_ether_addr(dev
->dev_addr
);
1490 dev_err(eth
->dev
, "generated random MAC address %pM\n",
1492 dev
->addr_assign_type
= NET_ADDR_RANDOM
;
1495 return mtk_phy_connect(mac
);
1498 static void mtk_uninit(struct net_device
*dev
)
1500 struct mtk_mac
*mac
= netdev_priv(dev
);
1501 struct mtk_eth
*eth
= mac
->hw
;
1503 phy_disconnect(mac
->phy_dev
);
1504 mtk_irq_disable(eth
, ~0);
1507 static int mtk_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1509 struct mtk_mac
*mac
= netdev_priv(dev
);
1515 return phy_mii_ioctl(mac
->phy_dev
, ifr
, cmd
);
1523 static void mtk_pending_work(struct work_struct
*work
)
1525 struct mtk_eth
*eth
= container_of(work
, struct mtk_eth
, pending_work
);
1527 unsigned long restart
= 0;
1531 /* stop all devices to make sure that dma is properly shut down */
1532 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
1533 if (!eth
->netdev
[i
])
1535 mtk_stop(eth
->netdev
[i
]);
1536 __set_bit(i
, &restart
);
1539 /* restart DMA and enable IRQs */
1540 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
1541 if (!test_bit(i
, &restart
))
1543 err
= mtk_open(eth
->netdev
[i
]);
1545 netif_alert(eth
, ifup
, eth
->netdev
[i
],
1546 "Driver up/down cycle failed, closing device.\n");
1547 dev_close(eth
->netdev
[i
]);
1553 static int mtk_cleanup(struct mtk_eth
*eth
)
1557 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
1558 if (!eth
->netdev
[i
])
1561 unregister_netdev(eth
->netdev
[i
]);
1562 free_netdev(eth
->netdev
[i
]);
1564 cancel_work_sync(ð
->pending_work
);
1569 static int mtk_get_settings(struct net_device
*dev
,
1570 struct ethtool_cmd
*cmd
)
1572 struct mtk_mac
*mac
= netdev_priv(dev
);
1575 err
= phy_read_status(mac
->phy_dev
);
1579 return phy_ethtool_gset(mac
->phy_dev
, cmd
);
1582 static int mtk_set_settings(struct net_device
*dev
,
1583 struct ethtool_cmd
*cmd
)
1585 struct mtk_mac
*mac
= netdev_priv(dev
);
1587 if (cmd
->phy_address
!= mac
->phy_dev
->mdio
.addr
) {
1588 mac
->phy_dev
= mdiobus_get_phy(mac
->hw
->mii_bus
,
1594 return phy_ethtool_sset(mac
->phy_dev
, cmd
);
1597 static void mtk_get_drvinfo(struct net_device
*dev
,
1598 struct ethtool_drvinfo
*info
)
1600 struct mtk_mac
*mac
= netdev_priv(dev
);
1602 strlcpy(info
->driver
, mac
->hw
->dev
->driver
->name
, sizeof(info
->driver
));
1603 strlcpy(info
->bus_info
, dev_name(mac
->hw
->dev
), sizeof(info
->bus_info
));
1604 info
->n_stats
= ARRAY_SIZE(mtk_ethtool_stats
);
1607 static u32
mtk_get_msglevel(struct net_device
*dev
)
1609 struct mtk_mac
*mac
= netdev_priv(dev
);
1611 return mac
->hw
->msg_enable
;
1614 static void mtk_set_msglevel(struct net_device
*dev
, u32 value
)
1616 struct mtk_mac
*mac
= netdev_priv(dev
);
1618 mac
->hw
->msg_enable
= value
;
1621 static int mtk_nway_reset(struct net_device
*dev
)
1623 struct mtk_mac
*mac
= netdev_priv(dev
);
1625 return genphy_restart_aneg(mac
->phy_dev
);
1628 static u32
mtk_get_link(struct net_device
*dev
)
1630 struct mtk_mac
*mac
= netdev_priv(dev
);
1633 err
= genphy_update_link(mac
->phy_dev
);
1635 return ethtool_op_get_link(dev
);
1637 return mac
->phy_dev
->link
;
1640 static void mtk_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1644 switch (stringset
) {
1646 for (i
= 0; i
< ARRAY_SIZE(mtk_ethtool_stats
); i
++) {
1647 memcpy(data
, mtk_ethtool_stats
[i
].str
, ETH_GSTRING_LEN
);
1648 data
+= ETH_GSTRING_LEN
;
1654 static int mtk_get_sset_count(struct net_device
*dev
, int sset
)
1658 return ARRAY_SIZE(mtk_ethtool_stats
);
1664 static void mtk_get_ethtool_stats(struct net_device
*dev
,
1665 struct ethtool_stats
*stats
, u64
*data
)
1667 struct mtk_mac
*mac
= netdev_priv(dev
);
1668 struct mtk_hw_stats
*hwstats
= mac
->hw_stats
;
1669 u64
*data_src
, *data_dst
;
1673 if (netif_running(dev
) && netif_device_present(dev
)) {
1674 if (spin_trylock(&hwstats
->stats_lock
)) {
1675 mtk_stats_update_mac(mac
);
1676 spin_unlock(&hwstats
->stats_lock
);
1681 data_src
= (u64
*)hwstats
;
1683 start
= u64_stats_fetch_begin_irq(&hwstats
->syncp
);
1685 for (i
= 0; i
< ARRAY_SIZE(mtk_ethtool_stats
); i
++)
1686 *data_dst
++ = *(data_src
+ mtk_ethtool_stats
[i
].offset
);
1687 } while (u64_stats_fetch_retry_irq(&hwstats
->syncp
, start
));
1690 static struct ethtool_ops mtk_ethtool_ops
= {
1691 .get_settings
= mtk_get_settings
,
1692 .set_settings
= mtk_set_settings
,
1693 .get_drvinfo
= mtk_get_drvinfo
,
1694 .get_msglevel
= mtk_get_msglevel
,
1695 .set_msglevel
= mtk_set_msglevel
,
1696 .nway_reset
= mtk_nway_reset
,
1697 .get_link
= mtk_get_link
,
1698 .get_strings
= mtk_get_strings
,
1699 .get_sset_count
= mtk_get_sset_count
,
1700 .get_ethtool_stats
= mtk_get_ethtool_stats
,
1703 static const struct net_device_ops mtk_netdev_ops
= {
1704 .ndo_init
= mtk_init
,
1705 .ndo_uninit
= mtk_uninit
,
1706 .ndo_open
= mtk_open
,
1707 .ndo_stop
= mtk_stop
,
1708 .ndo_start_xmit
= mtk_start_xmit
,
1709 .ndo_set_mac_address
= mtk_set_mac_address
,
1710 .ndo_validate_addr
= eth_validate_addr
,
1711 .ndo_do_ioctl
= mtk_do_ioctl
,
1712 .ndo_change_mtu
= eth_change_mtu
,
1713 .ndo_tx_timeout
= mtk_tx_timeout
,
1714 .ndo_get_stats64
= mtk_get_stats64
,
1715 #ifdef CONFIG_NET_POLL_CONTROLLER
1716 .ndo_poll_controller
= mtk_poll_controller
,
1720 static int mtk_add_mac(struct mtk_eth
*eth
, struct device_node
*np
)
1722 struct mtk_mac
*mac
;
1723 const __be32
*_id
= of_get_property(np
, "reg", NULL
);
1727 dev_err(eth
->dev
, "missing mac id\n");
1731 id
= be32_to_cpup(_id
);
1732 if (id
>= MTK_MAC_COUNT
) {
1733 dev_err(eth
->dev
, "%d is not a valid mac id\n", id
);
1737 if (eth
->netdev
[id
]) {
1738 dev_err(eth
->dev
, "duplicate mac id found: %d\n", id
);
1742 eth
->netdev
[id
] = alloc_etherdev(sizeof(*mac
));
1743 if (!eth
->netdev
[id
]) {
1744 dev_err(eth
->dev
, "alloc_etherdev failed\n");
1747 mac
= netdev_priv(eth
->netdev
[id
]);
1753 mac
->hw_stats
= devm_kzalloc(eth
->dev
,
1754 sizeof(*mac
->hw_stats
),
1756 if (!mac
->hw_stats
) {
1757 dev_err(eth
->dev
, "failed to allocate counter memory\n");
1761 spin_lock_init(&mac
->hw_stats
->stats_lock
);
1762 u64_stats_init(&mac
->hw_stats
->syncp
);
1763 mac
->hw_stats
->reg_offset
= id
* MTK_STAT_OFFSET
;
1765 SET_NETDEV_DEV(eth
->netdev
[id
], eth
->dev
);
1766 eth
->netdev
[id
]->watchdog_timeo
= 5 * HZ
;
1767 eth
->netdev
[id
]->netdev_ops
= &mtk_netdev_ops
;
1768 eth
->netdev
[id
]->base_addr
= (unsigned long)eth
->base
;
1769 eth
->netdev
[id
]->vlan_features
= MTK_HW_FEATURES
&
1770 ~(NETIF_F_HW_VLAN_CTAG_TX
| NETIF_F_HW_VLAN_CTAG_RX
);
1771 eth
->netdev
[id
]->features
|= MTK_HW_FEATURES
;
1772 eth
->netdev
[id
]->ethtool_ops
= &mtk_ethtool_ops
;
1774 err
= register_netdev(eth
->netdev
[id
]);
1776 dev_err(eth
->dev
, "error bringing up device\n");
1779 eth
->netdev
[id
]->irq
= eth
->irq
[0];
1780 netif_info(eth
, probe
, eth
->netdev
[id
],
1781 "mediatek frame engine at 0x%08lx, irq %d\n",
1782 eth
->netdev
[id
]->base_addr
, eth
->irq
[0]);
1787 free_netdev(eth
->netdev
[id
]);
1791 static int mtk_probe(struct platform_device
*pdev
)
1793 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1794 struct device_node
*mac_np
;
1795 const struct of_device_id
*match
;
1796 struct mtk_soc_data
*soc
;
1797 struct mtk_eth
*eth
;
1801 match
= of_match_device(of_mtk_match
, &pdev
->dev
);
1802 soc
= (struct mtk_soc_data
*)match
->data
;
1804 eth
= devm_kzalloc(&pdev
->dev
, sizeof(*eth
), GFP_KERNEL
);
1808 eth
->dev
= &pdev
->dev
;
1809 eth
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
1810 if (IS_ERR(eth
->base
))
1811 return PTR_ERR(eth
->base
);
1813 spin_lock_init(ð
->page_lock
);
1814 spin_lock_init(ð
->irq_lock
);
1816 eth
->ethsys
= syscon_regmap_lookup_by_phandle(pdev
->dev
.of_node
,
1818 if (IS_ERR(eth
->ethsys
)) {
1819 dev_err(&pdev
->dev
, "no ethsys regmap found\n");
1820 return PTR_ERR(eth
->ethsys
);
1823 eth
->pctl
= syscon_regmap_lookup_by_phandle(pdev
->dev
.of_node
,
1825 if (IS_ERR(eth
->pctl
)) {
1826 dev_err(&pdev
->dev
, "no pctl regmap found\n");
1827 return PTR_ERR(eth
->pctl
);
1830 eth
->rstc
= devm_reset_control_get(&pdev
->dev
, "eth");
1831 if (IS_ERR(eth
->rstc
)) {
1832 dev_err(&pdev
->dev
, "no eth reset found\n");
1833 return PTR_ERR(eth
->rstc
);
1836 for (i
= 0; i
< 3; i
++) {
1837 eth
->irq
[i
] = platform_get_irq(pdev
, i
);
1838 if (eth
->irq
[i
] < 0) {
1839 dev_err(&pdev
->dev
, "no IRQ%d resource found\n", i
);
1843 for (i
= 0; i
< ARRAY_SIZE(eth
->clks
); i
++) {
1844 eth
->clks
[i
] = devm_clk_get(eth
->dev
,
1845 mtk_clks_source_name
[i
]);
1846 if (IS_ERR(eth
->clks
[i
])) {
1847 if (PTR_ERR(eth
->clks
[i
]) == -EPROBE_DEFER
)
1848 return -EPROBE_DEFER
;
1853 clk_prepare_enable(eth
->clks
[MTK_CLK_ETHIF
]);
1854 clk_prepare_enable(eth
->clks
[MTK_CLK_ESW
]);
1855 clk_prepare_enable(eth
->clks
[MTK_CLK_GP1
]);
1856 clk_prepare_enable(eth
->clks
[MTK_CLK_GP2
]);
1858 eth
->msg_enable
= netif_msg_init(mtk_msg_level
, MTK_DEFAULT_MSG_ENABLE
);
1859 INIT_WORK(ð
->pending_work
, mtk_pending_work
);
1861 err
= mtk_hw_init(eth
);
1865 for_each_child_of_node(pdev
->dev
.of_node
, mac_np
) {
1866 if (!of_device_is_compatible(mac_np
,
1867 "mediatek,eth-mac"))
1870 if (!of_device_is_available(mac_np
))
1873 err
= mtk_add_mac(eth
, mac_np
);
1878 /* we run 2 devices on the same DMA ring so we need a dummy device
1881 init_dummy_netdev(ð
->dummy_dev
);
1882 netif_napi_add(ð
->dummy_dev
, ð
->tx_napi
, mtk_napi_tx
,
1884 netif_napi_add(ð
->dummy_dev
, ð
->rx_napi
, mtk_napi_rx
,
1887 platform_set_drvdata(pdev
, eth
);
1896 static int mtk_remove(struct platform_device
*pdev
)
1898 struct mtk_eth
*eth
= platform_get_drvdata(pdev
);
1901 /* stop all devices to make sure that dma is properly shut down */
1902 for (i
= 0; i
< MTK_MAC_COUNT
; i
++) {
1903 if (!eth
->netdev
[i
])
1905 mtk_stop(eth
->netdev
[i
]);
1908 clk_disable_unprepare(eth
->clks
[MTK_CLK_ETHIF
]);
1909 clk_disable_unprepare(eth
->clks
[MTK_CLK_ESW
]);
1910 clk_disable_unprepare(eth
->clks
[MTK_CLK_GP1
]);
1911 clk_disable_unprepare(eth
->clks
[MTK_CLK_GP2
]);
1913 netif_napi_del(ð
->tx_napi
);
1914 netif_napi_del(ð
->rx_napi
);
1916 mtk_mdio_cleanup(eth
);
1917 platform_set_drvdata(pdev
, NULL
);
1922 const struct of_device_id of_mtk_match
[] = {
1923 { .compatible
= "mediatek,mt7623-eth" },
1927 static struct platform_driver mtk_driver
= {
1929 .remove
= mtk_remove
,
1931 .name
= "mtk_soc_eth",
1932 .of_match_table
= of_mtk_match
,
1936 module_platform_driver(mtk_driver
);
1938 MODULE_LICENSE("GPL");
1939 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1940 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");