projects / deliverable / linux.git / blob
? search:


78fdbd653fa937a26663580d48db6df869102317
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / cmd.c
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/export.h>
38 #include <linux/pci.h>
39 #include <linux/errno.h>
40
41 #include <linux/mlx4/cmd.h>
42 #include <linux/semaphore.h>
43 #include <rdma/ib_smi.h>
44
45 #include <asm/io.h>
46
47 #include "mlx4.h"
48 #include "fw.h"
49
50 #define CMD_POLL_TOKEN 0xffff
51 #define INBOX_MASK 0xffffffffffffff00ULL
52
53 #define CMD_CHAN_VER 1
54 #define CMD_CHAN_IF_REV 1
55
56 enum {
57 /* command completed successfully: */
58 CMD_STAT_OK = 0x00,
59 /* Internal error (such as a bus error) occurred while processing command: */
60 CMD_STAT_INTERNAL_ERR = 0x01,
61 /* Operation/command not supported or opcode modifier not supported: */
62 CMD_STAT_BAD_OP = 0x02,
63 /* Parameter not supported or parameter out of range: */
64 CMD_STAT_BAD_PARAM = 0x03,
65 /* System not enabled or bad system state: */
66 CMD_STAT_BAD_SYS_STATE = 0x04,
67 /* Attempt to access reserved or unallocaterd resource: */
68 CMD_STAT_BAD_RESOURCE = 0x05,
69 /* Requested resource is currently executing a command, or is otherwise busy: */
70 CMD_STAT_RESOURCE_BUSY = 0x06,
71 /* Required capability exceeds device limits: */
72 CMD_STAT_EXCEED_LIM = 0x08,
73 /* Resource is not in the appropriate state or ownership: */
74 CMD_STAT_BAD_RES_STATE = 0x09,
75 /* Index out of range: */
76 CMD_STAT_BAD_INDEX = 0x0a,
77 /* FW image corrupted: */
78 CMD_STAT_BAD_NVMEM = 0x0b,
79 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
80 CMD_STAT_ICM_ERROR = 0x0c,
81 /* Attempt to modify a QP/EE which is not in the presumed state: */
82 CMD_STAT_BAD_QP_STATE = 0x10,
83 /* Bad segment parameters (Address/Size): */
84 CMD_STAT_BAD_SEG_PARAM = 0x20,
85 /* Memory Region has Memory Windows bound to: */
86 CMD_STAT_REG_BOUND = 0x21,
87 /* HCA local attached memory not present: */
88 CMD_STAT_LAM_NOT_PRE = 0x22,
89 /* Bad management packet (silently discarded): */
90 CMD_STAT_BAD_PKT = 0x30,
91 /* More outstanding CQEs in CQ than new CQ size: */
92 CMD_STAT_BAD_SIZE = 0x40,
93 /* Multi Function device support required: */
94 CMD_STAT_MULTI_FUNC_REQ = 0x50,
95 };
96
97 enum {
98 HCR_IN_PARAM_OFFSET = 0x00,
99 HCR_IN_MODIFIER_OFFSET = 0x08,
100 HCR_OUT_PARAM_OFFSET = 0x0c,
101 HCR_TOKEN_OFFSET = 0x14,
102 HCR_STATUS_OFFSET = 0x18,
103
104 HCR_OPMOD_SHIFT = 12,
105 HCR_T_BIT = 21,
106 HCR_E_BIT = 22,
107 HCR_GO_BIT = 23
108 };
109
110 enum {
111 GO_BIT_TIMEOUT_MSECS = 10000
112 };
113
114 struct mlx4_cmd_context {
115 struct completion done;
116 int result;
117 int next;
118 u64 out_param;
119 u16 token;
120 u8 fw_status;
121 };
122
123 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
124 struct mlx4_vhcr_cmd *in_vhcr);
125
126 static int mlx4_status_to_errno(u8 status)
127 {
128 static const int trans_table[] = {
129 [CMD_STAT_INTERNAL_ERR] = -EIO,
130 [CMD_STAT_BAD_OP] = -EPERM,
131 [CMD_STAT_BAD_PARAM] = -EINVAL,
132 [CMD_STAT_BAD_SYS_STATE] = -ENXIO,
133 [CMD_STAT_BAD_RESOURCE] = -EBADF,
134 [CMD_STAT_RESOURCE_BUSY] = -EBUSY,
135 [CMD_STAT_EXCEED_LIM] = -ENOMEM,
136 [CMD_STAT_BAD_RES_STATE] = -EBADF,
137 [CMD_STAT_BAD_INDEX] = -EBADF,
138 [CMD_STAT_BAD_NVMEM] = -EFAULT,
139 [CMD_STAT_ICM_ERROR] = -ENFILE,
140 [CMD_STAT_BAD_QP_STATE] = -EINVAL,
141 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
142 [CMD_STAT_REG_BOUND] = -EBUSY,
143 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
144 [CMD_STAT_BAD_PKT] = -EINVAL,
145 [CMD_STAT_BAD_SIZE] = -ENOMEM,
146 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
147 };
148
149 if (status >= ARRAY_SIZE(trans_table) ||
150 (status != CMD_STAT_OK && trans_table[status] == 0))
151 return -EIO;
152
153 return trans_table[status];
154 }
155
156 static u8 mlx4_errno_to_status(int errno)
157 {
158 switch (errno) {
159 case -EPERM:
160 return CMD_STAT_BAD_OP;
161 case -EINVAL:
162 return CMD_STAT_BAD_PARAM;
163 case -ENXIO:
164 return CMD_STAT_BAD_SYS_STATE;
165 case -EBUSY:
166 return CMD_STAT_RESOURCE_BUSY;
167 case -ENOMEM:
168 return CMD_STAT_EXCEED_LIM;
169 case -ENFILE:
170 return CMD_STAT_ICM_ERROR;
171 default:
172 return CMD_STAT_INTERNAL_ERR;
173 }
174 }
175
176 static int comm_pending(struct mlx4_dev *dev)
177 {
178 struct mlx4_priv *priv = mlx4_priv(dev);
179 u32 status = readl(&priv->mfunc.comm->slave_read);
180
181 return (swab32(status) >> 31) != priv->cmd.comm_toggle;
182 }
183
184 static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
185 {
186 struct mlx4_priv *priv = mlx4_priv(dev);
187 u32 val;
188
189 priv->cmd.comm_toggle ^= 1;
190 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
191 __raw_writel((__force u32) cpu_to_be32(val),
192 &priv->mfunc.comm->slave_write);
193 mmiowb();
194 }
195
196 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
197 unsigned long timeout)
198 {
199 struct mlx4_priv *priv = mlx4_priv(dev);
200 unsigned long end;
201 int err = 0;
202 int ret_from_pending = 0;
203
204 /* First, verify that the master reports correct status */
205 if (comm_pending(dev)) {
206 mlx4_warn(dev, "Communication channel is not idle."
207 "my toggle is %d (cmd:0x%x)\n",
208 priv->cmd.comm_toggle, cmd);
209 return -EAGAIN;
210 }
211
212 /* Write command */
213 down(&priv->cmd.poll_sem);
214 mlx4_comm_cmd_post(dev, cmd, param);
215
216 end = msecs_to_jiffies(timeout) + jiffies;
217 while (comm_pending(dev) && time_before(jiffies, end))
218 cond_resched();
219 ret_from_pending = comm_pending(dev);
220 if (ret_from_pending) {
221 /* check if the slave is trying to boot in the middle of
222 * FLR process. The only non-zero result in the RESET command
223 * is MLX4_DELAY_RESET_SLAVE*/
224 if ((MLX4_COMM_CMD_RESET == cmd)) {
225 mlx4_warn(dev, "Got slave FLRed from Communication"
226 " channel (ret:0x%x)\n", ret_from_pending);
227 err = MLX4_DELAY_RESET_SLAVE;
228 } else {
229 mlx4_warn(dev, "Communication channel timed out\n");
230 err = -ETIMEDOUT;
231 }
232 }
233
234 up(&priv->cmd.poll_sem);
235 return err;
236 }
237
238 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op,
239 u16 param, unsigned long timeout)
240 {
241 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
242 struct mlx4_cmd_context *context;
243 unsigned long end;
244 int err = 0;
245
246 down(&cmd->event_sem);
247
248 spin_lock(&cmd->context_lock);
249 BUG_ON(cmd->free_head < 0);
250 context = &cmd->context[cmd->free_head];
251 context->token += cmd->token_mask + 1;
252 cmd->free_head = context->next;
253 spin_unlock(&cmd->context_lock);
254
255 init_completion(&context->done);
256
257 mlx4_comm_cmd_post(dev, op, param);
258
259 if (!wait_for_completion_timeout(&context->done,
260 msecs_to_jiffies(timeout))) {
261 err = -EBUSY;
262 goto out;
263 }
264
265 err = context->result;
266 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
267 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
268 op, context->fw_status);
269 goto out;
270 }
271
272 out:
273 /* wait for comm channel ready
274 * this is necessary for prevention the race
275 * when switching between event to polling mode
276 */
277 end = msecs_to_jiffies(timeout) + jiffies;
278 while (comm_pending(dev) && time_before(jiffies, end))
279 cond_resched();
280
281 spin_lock(&cmd->context_lock);
282 context->next = cmd->free_head;
283 cmd->free_head = context - cmd->context;
284 spin_unlock(&cmd->context_lock);
285
286 up(&cmd->event_sem);
287 return err;
288 }
289
290 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
291 unsigned long timeout)
292 {
293 if (mlx4_priv(dev)->cmd.use_events)
294 return mlx4_comm_cmd_wait(dev, cmd, param, timeout);
295 return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
296 }
297
298 static int cmd_pending(struct mlx4_dev *dev)
299 {
300 u32 status;
301
302 if (pci_channel_offline(dev->pdev))
303 return -EIO;
304
305 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
306
307 return (status & swab32(1 << HCR_GO_BIT)) ||
308 (mlx4_priv(dev)->cmd.toggle ==
309 !!(status & swab32(1 << HCR_T_BIT)));
310 }
311
312 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
313 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
314 int event)
315 {
316 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
317 u32 __iomem *hcr = cmd->hcr;
318 int ret = -EAGAIN;
319 unsigned long end;
320
321 mutex_lock(&cmd->hcr_mutex);
322
323 if (pci_channel_offline(dev->pdev)) {
324 /*
325 * Device is going through error recovery
326 * and cannot accept commands.
327 */
328 ret = -EIO;
329 goto out;
330 }
331
332 end = jiffies;
333 if (event)
334 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
335
336 while (cmd_pending(dev)) {
337 if (pci_channel_offline(dev->pdev)) {
338 /*
339 * Device is going through error recovery
340 * and cannot accept commands.
341 */
342 ret = -EIO;
343 goto out;
344 }
345
346 if (time_after_eq(jiffies, end)) {
347 mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
348 goto out;
349 }
350 cond_resched();
351 }
352
353 /*
354 * We use writel (instead of something like memcpy_toio)
355 * because writes of less than 32 bits to the HCR don't work
356 * (and some architectures such as ia64 implement memcpy_toio
357 * in terms of writeb).
358 */
359 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
360 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
361 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
362 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
363 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
364 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
365
366 /* __raw_writel may not order writes. */
367 wmb();
368
369 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
370 (cmd->toggle << HCR_T_BIT) |
371 (event ? (1 << HCR_E_BIT) : 0) |
372 (op_modifier << HCR_OPMOD_SHIFT) |
373 op), hcr + 6);
374
375 /*
376 * Make sure that our HCR writes don't get mixed in with
377 * writes from another CPU starting a FW command.
378 */
379 mmiowb();
380
381 cmd->toggle = cmd->toggle ^ 1;
382
383 ret = 0;
384
385 out:
386 mutex_unlock(&cmd->hcr_mutex);
387 return ret;
388 }
389
390 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
391 int out_is_imm, u32 in_modifier, u8 op_modifier,
392 u16 op, unsigned long timeout)
393 {
394 struct mlx4_priv *priv = mlx4_priv(dev);
395 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
396 int ret;
397
398 down(&priv->cmd.slave_sem);
399 vhcr->in_param = cpu_to_be64(in_param);
400 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
401 vhcr->in_modifier = cpu_to_be32(in_modifier);
402 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
403 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
404 vhcr->status = 0;
405 vhcr->flags = !!(priv->cmd.use_events) << 6;
406 if (mlx4_is_master(dev)) {
407 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
408 if (!ret) {
409 if (out_is_imm) {
410 if (out_param)
411 *out_param =
412 be64_to_cpu(vhcr->out_param);
413 else {
414 mlx4_err(dev, "response expected while"
415 "output mailbox is NULL for "
416 "command 0x%x\n", op);
417 vhcr->status = CMD_STAT_BAD_PARAM;
418 }
419 }
420 ret = mlx4_status_to_errno(vhcr->status);
421 }
422 } else {
423 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0,
424 MLX4_COMM_TIME + timeout);
425 if (!ret) {
426 if (out_is_imm) {
427 if (out_param)
428 *out_param =
429 be64_to_cpu(vhcr->out_param);
430 else {
431 mlx4_err(dev, "response expected while"
432 "output mailbox is NULL for "
433 "command 0x%x\n", op);
434 vhcr->status = CMD_STAT_BAD_PARAM;
435 }
436 }
437 ret = mlx4_status_to_errno(vhcr->status);
438 } else
439 mlx4_err(dev, "failed execution of VHCR_POST command"
440 "opcode 0x%x\n", op);
441 }
442 up(&priv->cmd.slave_sem);
443 return ret;
444 }
445
446 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
447 int out_is_imm, u32 in_modifier, u8 op_modifier,
448 u16 op, unsigned long timeout)
449 {
450 struct mlx4_priv *priv = mlx4_priv(dev);
451 void __iomem *hcr = priv->cmd.hcr;
452 int err = 0;
453 unsigned long end;
454 u32 stat;
455
456 down(&priv->cmd.poll_sem);
457
458 if (pci_channel_offline(dev->pdev)) {
459 /*
460 * Device is going through error recovery
461 * and cannot accept commands.
462 */
463 err = -EIO;
464 goto out;
465 }
466
467 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
468 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
469 if (err)
470 goto out;
471
472 end = msecs_to_jiffies(timeout) + jiffies;
473 while (cmd_pending(dev) && time_before(jiffies, end)) {
474 if (pci_channel_offline(dev->pdev)) {
475 /*
476 * Device is going through error recovery
477 * and cannot accept commands.
478 */
479 err = -EIO;
480 goto out;
481 }
482
483 cond_resched();
484 }
485
486 if (cmd_pending(dev)) {
487 err = -ETIMEDOUT;
488 goto out;
489 }
490
491 if (out_is_imm)
492 *out_param =
493 (u64) be32_to_cpu((__force __be32)
494 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
495 (u64) be32_to_cpu((__force __be32)
496 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
497 stat = be32_to_cpu((__force __be32)
498 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
499 err = mlx4_status_to_errno(stat);
500 if (err)
501 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
502 op, stat);
503
504 out:
505 up(&priv->cmd.poll_sem);
506 return err;
507 }
508
509 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
510 {
511 struct mlx4_priv *priv = mlx4_priv(dev);
512 struct mlx4_cmd_context *context =
513 &priv->cmd.context[token & priv->cmd.token_mask];
514
515 /* previously timed out command completing at long last */
516 if (token != context->token)
517 return;
518
519 context->fw_status = status;
520 context->result = mlx4_status_to_errno(status);
521 context->out_param = out_param;
522
523 complete(&context->done);
524 }
525
526 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
527 int out_is_imm, u32 in_modifier, u8 op_modifier,
528 u16 op, unsigned long timeout)
529 {
530 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
531 struct mlx4_cmd_context *context;
532 int err = 0;
533
534 down(&cmd->event_sem);
535
536 spin_lock(&cmd->context_lock);
537 BUG_ON(cmd->free_head < 0);
538 context = &cmd->context[cmd->free_head];
539 context->token += cmd->token_mask + 1;
540 cmd->free_head = context->next;
541 spin_unlock(&cmd->context_lock);
542
543 init_completion(&context->done);
544
545 mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
546 in_modifier, op_modifier, op, context->token, 1);
547
548 if (!wait_for_completion_timeout(&context->done,
549 msecs_to_jiffies(timeout))) {
550 err = -EBUSY;
551 goto out;
552 }
553
554 err = context->result;
555 if (err) {
556 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
557 op, context->fw_status);
558 goto out;
559 }
560
561 if (out_is_imm)
562 *out_param = context->out_param;
563
564 out:
565 spin_lock(&cmd->context_lock);
566 context->next = cmd->free_head;
567 cmd->free_head = context - cmd->context;
568 spin_unlock(&cmd->context_lock);
569
570 up(&cmd->event_sem);
571 return err;
572 }
573
574 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
575 int out_is_imm, u32 in_modifier, u8 op_modifier,
576 u16 op, unsigned long timeout, int native)
577 {
578 if (pci_channel_offline(dev->pdev))
579 return -EIO;
580
581 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
582 if (mlx4_priv(dev)->cmd.use_events)
583 return mlx4_cmd_wait(dev, in_param, out_param,
584 out_is_imm, in_modifier,
585 op_modifier, op, timeout);
586 else
587 return mlx4_cmd_poll(dev, in_param, out_param,
588 out_is_imm, in_modifier,
589 op_modifier, op, timeout);
590 }
591 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
592 in_modifier, op_modifier, op, timeout);
593 }
594 EXPORT_SYMBOL_GPL(__mlx4_cmd);
595
596
597 static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
598 {
599 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
600 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
601 }
602
603 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
604 int slave, u64 slave_addr,
605 int size, int is_read)
606 {
607 u64 in_param;
608 u64 out_param;
609
610 if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
611 (slave & ~0x7f) | (size & 0xff)) {
612 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx "
613 "master_addr:0x%llx slave_id:%d size:%d\n",
614 slave_addr, master_addr, slave, size);
615 return -EINVAL;
616 }
617
618 if (is_read) {
619 in_param = (u64) slave | slave_addr;
620 out_param = (u64) dev->caps.function | master_addr;
621 } else {
622 in_param = (u64) dev->caps.function | master_addr;
623 out_param = (u64) slave | slave_addr;
624 }
625
626 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
627 MLX4_CMD_ACCESS_MEM,
628 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
629 }
630
631 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
632 struct mlx4_cmd_mailbox *inbox,
633 struct mlx4_cmd_mailbox *outbox)
634 {
635 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
636 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
637 int err;
638 int i;
639
640 if (index & 0x1f)
641 return -EINVAL;
642
643 in_mad->attr_mod = cpu_to_be32(index / 32);
644
645 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
646 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
647 MLX4_CMD_NATIVE);
648 if (err)
649 return err;
650
651 for (i = 0; i < 32; ++i)
652 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
653
654 return err;
655 }
656
657 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
658 struct mlx4_cmd_mailbox *inbox,
659 struct mlx4_cmd_mailbox *outbox)
660 {
661 int i;
662 int err;
663
664 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
665 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
666 if (err)
667 return err;
668 }
669
670 return 0;
671 }
672 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
673 #define PORT_STATE_OFFSET 32
674
675 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
676 {
677 if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
678 return IB_PORT_ACTIVE;
679 else
680 return IB_PORT_DOWN;
681 }
682
683 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
684 struct mlx4_vhcr *vhcr,
685 struct mlx4_cmd_mailbox *inbox,
686 struct mlx4_cmd_mailbox *outbox,
687 struct mlx4_cmd_info *cmd)
688 {
689 struct ib_smp *smp = inbox->buf;
690 u32 index;
691 u8 port;
692 u16 *table;
693 int err;
694 int vidx, pidx;
695 struct mlx4_priv *priv = mlx4_priv(dev);
696 struct ib_smp *outsmp = outbox->buf;
697 __be16 *outtab = (__be16 *)(outsmp->data);
698 __be32 slave_cap_mask;
699 port = vhcr->in_modifier;
700
701 if (smp->base_version == 1 &&
702 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
703 smp->class_version == 1) {
704 if (smp->method == IB_MGMT_METHOD_GET) {
705 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
706 index = be32_to_cpu(smp->attr_mod);
707 if (port < 1 || port > dev->caps.num_ports)
708 return -EINVAL;
709 table = kcalloc(dev->caps.pkey_table_len[port], sizeof *table, GFP_KERNEL);
710 if (!table)
711 return -ENOMEM;
712 /* need to get the full pkey table because the paravirtualized
713 * pkeys may be scattered among several pkey blocks.
714 */
715 err = get_full_pkey_table(dev, port, table, inbox, outbox);
716 if (!err) {
717 for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
718 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
719 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
720 }
721 }
722 kfree(table);
723 return err;
724 }
725 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
726 /*get the slave specific caps:*/
727 /*do the command */
728 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
729 vhcr->in_modifier, vhcr->op_modifier,
730 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
731 /* modify the response for slaves */
732 if (!err && slave != mlx4_master_func_num(dev)) {
733 u8 *state = outsmp->data + PORT_STATE_OFFSET;
734
735 *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
736 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
737 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
738 }
739 return err;
740 }
741 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
742 /* compute slave's gid block */
743 smp->attr_mod = cpu_to_be32(slave / 8);
744 /* execute cmd */
745 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
746 vhcr->in_modifier, vhcr->op_modifier,
747 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
748 if (!err) {
749 /* if needed, move slave gid to index 0 */
750 if (slave % 8)
751 memcpy(outsmp->data,
752 outsmp->data + (slave % 8) * 8, 8);
753 /* delete all other gids */
754 memset(outsmp->data + 8, 0, 56);
755 }
756 return err;
757 }
758 }
759 }
760 if (slave != mlx4_master_func_num(dev) &&
761 ((smp->mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) ||
762 (smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
763 smp->method == IB_MGMT_METHOD_SET))) {
764 mlx4_err(dev, "slave %d is trying to execute a Subnet MGMT MAD, "
765 "class 0x%x, method 0x%x for attr 0x%x. Rejecting\n",
766 slave, smp->method, smp->mgmt_class,
767 be16_to_cpu(smp->attr_id));
768 return -EPERM;
769 }
770 /*default:*/
771 return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
772 vhcr->in_modifier, vhcr->op_modifier,
773 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
774 }
775
776 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
777 struct mlx4_vhcr *vhcr,
778 struct mlx4_cmd_mailbox *inbox,
779 struct mlx4_cmd_mailbox *outbox,
780 struct mlx4_cmd_info *cmd)
781 {
782 u64 in_param;
783 u64 out_param;
784 int err;
785
786 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
787 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
788 if (cmd->encode_slave_id) {
789 in_param &= 0xffffffffffffff00ll;
790 in_param |= slave;
791 }
792
793 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
794 vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
795 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
796
797 if (cmd->out_is_imm)
798 vhcr->out_param = out_param;
799
800 return err;
801 }
802
803 static struct mlx4_cmd_info cmd_info[] = {
804 {
805 .opcode = MLX4_CMD_QUERY_FW,
806 .has_inbox = false,
807 .has_outbox = true,
808 .out_is_imm = false,
809 .encode_slave_id = false,
810 .verify = NULL,
811 .wrapper = mlx4_QUERY_FW_wrapper
812 },
813 {
814 .opcode = MLX4_CMD_QUERY_HCA,
815 .has_inbox = false,
816 .has_outbox = true,
817 .out_is_imm = false,
818 .encode_slave_id = false,
819 .verify = NULL,
820 .wrapper = NULL
821 },
822 {
823 .opcode = MLX4_CMD_QUERY_DEV_CAP,
824 .has_inbox = false,
825 .has_outbox = true,
826 .out_is_imm = false,
827 .encode_slave_id = false,
828 .verify = NULL,
829 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
830 },
831 {
832 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
833 .has_inbox = false,
834 .has_outbox = true,
835 .out_is_imm = false,
836 .encode_slave_id = false,
837 .verify = NULL,
838 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
839 },
840 {
841 .opcode = MLX4_CMD_QUERY_ADAPTER,
842 .has_inbox = false,
843 .has_outbox = true,
844 .out_is_imm = false,
845 .encode_slave_id = false,
846 .verify = NULL,
847 .wrapper = NULL
848 },
849 {
850 .opcode = MLX4_CMD_INIT_PORT,
851 .has_inbox = false,
852 .has_outbox = false,
853 .out_is_imm = false,
854 .encode_slave_id = false,
855 .verify = NULL,
856 .wrapper = mlx4_INIT_PORT_wrapper
857 },
858 {
859 .opcode = MLX4_CMD_CLOSE_PORT,
860 .has_inbox = false,
861 .has_outbox = false,
862 .out_is_imm = false,
863 .encode_slave_id = false,
864 .verify = NULL,
865 .wrapper = mlx4_CLOSE_PORT_wrapper
866 },
867 {
868 .opcode = MLX4_CMD_QUERY_PORT,
869 .has_inbox = false,
870 .has_outbox = true,
871 .out_is_imm = false,
872 .encode_slave_id = false,
873 .verify = NULL,
874 .wrapper = mlx4_QUERY_PORT_wrapper
875 },
876 {
877 .opcode = MLX4_CMD_SET_PORT,
878 .has_inbox = true,
879 .has_outbox = false,
880 .out_is_imm = false,
881 .encode_slave_id = false,
882 .verify = NULL,
883 .wrapper = mlx4_SET_PORT_wrapper
884 },
885 {
886 .opcode = MLX4_CMD_MAP_EQ,
887 .has_inbox = false,
888 .has_outbox = false,
889 .out_is_imm = false,
890 .encode_slave_id = false,
891 .verify = NULL,
892 .wrapper = mlx4_MAP_EQ_wrapper
893 },
894 {
895 .opcode = MLX4_CMD_SW2HW_EQ,
896 .has_inbox = true,
897 .has_outbox = false,
898 .out_is_imm = false,
899 .encode_slave_id = true,
900 .verify = NULL,
901 .wrapper = mlx4_SW2HW_EQ_wrapper
902 },
903 {
904 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
905 .has_inbox = false,
906 .has_outbox = false,
907 .out_is_imm = false,
908 .encode_slave_id = false,
909 .verify = NULL,
910 .wrapper = NULL
911 },
912 {
913 .opcode = MLX4_CMD_NOP,
914 .has_inbox = false,
915 .has_outbox = false,
916 .out_is_imm = false,
917 .encode_slave_id = false,
918 .verify = NULL,
919 .wrapper = NULL
920 },
921 {
922 .opcode = MLX4_CMD_ALLOC_RES,
923 .has_inbox = false,
924 .has_outbox = false,
925 .out_is_imm = true,
926 .encode_slave_id = false,
927 .verify = NULL,
928 .wrapper = mlx4_ALLOC_RES_wrapper
929 },
930 {
931 .opcode = MLX4_CMD_FREE_RES,
932 .has_inbox = false,
933 .has_outbox = false,
934 .out_is_imm = false,
935 .encode_slave_id = false,
936 .verify = NULL,
937 .wrapper = mlx4_FREE_RES_wrapper
938 },
939 {
940 .opcode = MLX4_CMD_SW2HW_MPT,
941 .has_inbox = true,
942 .has_outbox = false,
943 .out_is_imm = false,
944 .encode_slave_id = true,
945 .verify = NULL,
946 .wrapper = mlx4_SW2HW_MPT_wrapper
947 },
948 {
949 .opcode = MLX4_CMD_QUERY_MPT,
950 .has_inbox = false,
951 .has_outbox = true,
952 .out_is_imm = false,
953 .encode_slave_id = false,
954 .verify = NULL,
955 .wrapper = mlx4_QUERY_MPT_wrapper
956 },
957 {
958 .opcode = MLX4_CMD_HW2SW_MPT,
959 .has_inbox = false,
960 .has_outbox = false,
961 .out_is_imm = false,
962 .encode_slave_id = false,
963 .verify = NULL,
964 .wrapper = mlx4_HW2SW_MPT_wrapper
965 },
966 {
967 .opcode = MLX4_CMD_READ_MTT,
968 .has_inbox = false,
969 .has_outbox = true,
970 .out_is_imm = false,
971 .encode_slave_id = false,
972 .verify = NULL,
973 .wrapper = NULL
974 },
975 {
976 .opcode = MLX4_CMD_WRITE_MTT,
977 .has_inbox = true,
978 .has_outbox = false,
979 .out_is_imm = false,
980 .encode_slave_id = false,
981 .verify = NULL,
982 .wrapper = mlx4_WRITE_MTT_wrapper
983 },
984 {
985 .opcode = MLX4_CMD_SYNC_TPT,
986 .has_inbox = true,
987 .has_outbox = false,
988 .out_is_imm = false,
989 .encode_slave_id = false,
990 .verify = NULL,
991 .wrapper = NULL
992 },
993 {
994 .opcode = MLX4_CMD_HW2SW_EQ,
995 .has_inbox = false,
996 .has_outbox = true,
997 .out_is_imm = false,
998 .encode_slave_id = true,
999 .verify = NULL,
1000 .wrapper = mlx4_HW2SW_EQ_wrapper
1001 },
1002 {
1003 .opcode = MLX4_CMD_QUERY_EQ,
1004 .has_inbox = false,
1005 .has_outbox = true,
1006 .out_is_imm = false,
1007 .encode_slave_id = true,
1008 .verify = NULL,
1009 .wrapper = mlx4_QUERY_EQ_wrapper
1010 },
1011 {
1012 .opcode = MLX4_CMD_SW2HW_CQ,
1013 .has_inbox = true,
1014 .has_outbox = false,
1015 .out_is_imm = false,
1016 .encode_slave_id = true,
1017 .verify = NULL,
1018 .wrapper = mlx4_SW2HW_CQ_wrapper
1019 },
1020 {
1021 .opcode = MLX4_CMD_HW2SW_CQ,
1022 .has_inbox = false,
1023 .has_outbox = false,
1024 .out_is_imm = false,
1025 .encode_slave_id = false,
1026 .verify = NULL,
1027 .wrapper = mlx4_HW2SW_CQ_wrapper
1028 },
1029 {
1030 .opcode = MLX4_CMD_QUERY_CQ,
1031 .has_inbox = false,
1032 .has_outbox = true,
1033 .out_is_imm = false,
1034 .encode_slave_id = false,
1035 .verify = NULL,
1036 .wrapper = mlx4_QUERY_CQ_wrapper
1037 },
1038 {
1039 .opcode = MLX4_CMD_MODIFY_CQ,
1040 .has_inbox = true,
1041 .has_outbox = false,
1042 .out_is_imm = true,
1043 .encode_slave_id = false,
1044 .verify = NULL,
1045 .wrapper = mlx4_MODIFY_CQ_wrapper
1046 },
1047 {
1048 .opcode = MLX4_CMD_SW2HW_SRQ,
1049 .has_inbox = true,
1050 .has_outbox = false,
1051 .out_is_imm = false,
1052 .encode_slave_id = true,
1053 .verify = NULL,
1054 .wrapper = mlx4_SW2HW_SRQ_wrapper
1055 },
1056 {
1057 .opcode = MLX4_CMD_HW2SW_SRQ,
1058 .has_inbox = false,
1059 .has_outbox = false,
1060 .out_is_imm = false,
1061 .encode_slave_id = false,
1062 .verify = NULL,
1063 .wrapper = mlx4_HW2SW_SRQ_wrapper
1064 },
1065 {
1066 .opcode = MLX4_CMD_QUERY_SRQ,
1067 .has_inbox = false,
1068 .has_outbox = true,
1069 .out_is_imm = false,
1070 .encode_slave_id = false,
1071 .verify = NULL,
1072 .wrapper = mlx4_QUERY_SRQ_wrapper
1073 },
1074 {
1075 .opcode = MLX4_CMD_ARM_SRQ,
1076 .has_inbox = false,
1077 .has_outbox = false,
1078 .out_is_imm = false,
1079 .encode_slave_id = false,
1080 .verify = NULL,
1081 .wrapper = mlx4_ARM_SRQ_wrapper
1082 },
1083 {
1084 .opcode = MLX4_CMD_RST2INIT_QP,
1085 .has_inbox = true,
1086 .has_outbox = false,
1087 .out_is_imm = false,
1088 .encode_slave_id = true,
1089 .verify = NULL,
1090 .wrapper = mlx4_RST2INIT_QP_wrapper
1091 },
1092 {
1093 .opcode = MLX4_CMD_INIT2INIT_QP,
1094 .has_inbox = true,
1095 .has_outbox = false,
1096 .out_is_imm = false,
1097 .encode_slave_id = false,
1098 .verify = NULL,
1099 .wrapper = mlx4_INIT2INIT_QP_wrapper
1100 },
1101 {
1102 .opcode = MLX4_CMD_INIT2RTR_QP,
1103 .has_inbox = true,
1104 .has_outbox = false,
1105 .out_is_imm = false,
1106 .encode_slave_id = false,
1107 .verify = NULL,
1108 .wrapper = mlx4_INIT2RTR_QP_wrapper
1109 },
1110 {
1111 .opcode = MLX4_CMD_RTR2RTS_QP,
1112 .has_inbox = true,
1113 .has_outbox = false,
1114 .out_is_imm = false,
1115 .encode_slave_id = false,
1116 .verify = NULL,
1117 .wrapper = mlx4_RTR2RTS_QP_wrapper
1118 },
1119 {
1120 .opcode = MLX4_CMD_RTS2RTS_QP,
1121 .has_inbox = true,
1122 .has_outbox = false,
1123 .out_is_imm = false,
1124 .encode_slave_id = false,
1125 .verify = NULL,
1126 .wrapper = mlx4_RTS2RTS_QP_wrapper
1127 },
1128 {
1129 .opcode = MLX4_CMD_SQERR2RTS_QP,
1130 .has_inbox = true,
1131 .has_outbox = false,
1132 .out_is_imm = false,
1133 .encode_slave_id = false,
1134 .verify = NULL,
1135 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1136 },
1137 {
1138 .opcode = MLX4_CMD_2ERR_QP,
1139 .has_inbox = false,
1140 .has_outbox = false,
1141 .out_is_imm = false,
1142 .encode_slave_id = false,
1143 .verify = NULL,
1144 .wrapper = mlx4_GEN_QP_wrapper
1145 },
1146 {
1147 .opcode = MLX4_CMD_RTS2SQD_QP,
1148 .has_inbox = false,
1149 .has_outbox = false,
1150 .out_is_imm = false,
1151 .encode_slave_id = false,
1152 .verify = NULL,
1153 .wrapper = mlx4_GEN_QP_wrapper
1154 },
1155 {
1156 .opcode = MLX4_CMD_SQD2SQD_QP,
1157 .has_inbox = true,
1158 .has_outbox = false,
1159 .out_is_imm = false,
1160 .encode_slave_id = false,
1161 .verify = NULL,
1162 .wrapper = mlx4_SQD2SQD_QP_wrapper
1163 },
1164 {
1165 .opcode = MLX4_CMD_SQD2RTS_QP,
1166 .has_inbox = true,
1167 .has_outbox = false,
1168 .out_is_imm = false,
1169 .encode_slave_id = false,
1170 .verify = NULL,
1171 .wrapper = mlx4_SQD2RTS_QP_wrapper
1172 },
1173 {
1174 .opcode = MLX4_CMD_2RST_QP,
1175 .has_inbox = false,
1176 .has_outbox = false,
1177 .out_is_imm = false,
1178 .encode_slave_id = false,
1179 .verify = NULL,
1180 .wrapper = mlx4_2RST_QP_wrapper
1181 },
1182 {
1183 .opcode = MLX4_CMD_QUERY_QP,
1184 .has_inbox = false,
1185 .has_outbox = true,
1186 .out_is_imm = false,
1187 .encode_slave_id = false,
1188 .verify = NULL,
1189 .wrapper = mlx4_GEN_QP_wrapper
1190 },
1191 {
1192 .opcode = MLX4_CMD_SUSPEND_QP,
1193 .has_inbox = false,
1194 .has_outbox = false,
1195 .out_is_imm = false,
1196 .encode_slave_id = false,
1197 .verify = NULL,
1198 .wrapper = mlx4_GEN_QP_wrapper
1199 },
1200 {
1201 .opcode = MLX4_CMD_UNSUSPEND_QP,
1202 .has_inbox = false,
1203 .has_outbox = false,
1204 .out_is_imm = false,
1205 .encode_slave_id = false,
1206 .verify = NULL,
1207 .wrapper = mlx4_GEN_QP_wrapper
1208 },
1209 {
1210 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1211 .has_inbox = false,
1212 .has_outbox = false,
1213 .out_is_imm = false,
1214 .encode_slave_id = false,
1215 .verify = NULL, /* XXX verify: only demux can do this */
1216 .wrapper = NULL
1217 },
1218 {
1219 .opcode = MLX4_CMD_MAD_IFC,
1220 .has_inbox = true,
1221 .has_outbox = true,
1222 .out_is_imm = false,
1223 .encode_slave_id = false,
1224 .verify = NULL,
1225 .wrapper = mlx4_MAD_IFC_wrapper
1226 },
1227 {
1228 .opcode = MLX4_CMD_QUERY_IF_STAT,
1229 .has_inbox = false,
1230 .has_outbox = true,
1231 .out_is_imm = false,
1232 .encode_slave_id = false,
1233 .verify = NULL,
1234 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1235 },
1236 /* Native multicast commands are not available for guests */
1237 {
1238 .opcode = MLX4_CMD_QP_ATTACH,
1239 .has_inbox = true,
1240 .has_outbox = false,
1241 .out_is_imm = false,
1242 .encode_slave_id = false,
1243 .verify = NULL,
1244 .wrapper = mlx4_QP_ATTACH_wrapper
1245 },
1246 {
1247 .opcode = MLX4_CMD_PROMISC,
1248 .has_inbox = false,
1249 .has_outbox = false,
1250 .out_is_imm = false,
1251 .encode_slave_id = false,
1252 .verify = NULL,
1253 .wrapper = mlx4_PROMISC_wrapper
1254 },
1255 /* Ethernet specific commands */
1256 {
1257 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1258 .has_inbox = true,
1259 .has_outbox = false,
1260 .out_is_imm = false,
1261 .encode_slave_id = false,
1262 .verify = NULL,
1263 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1264 },
1265 {
1266 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1267 .has_inbox = false,
1268 .has_outbox = false,
1269 .out_is_imm = false,
1270 .encode_slave_id = false,
1271 .verify = NULL,
1272 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1273 },
1274 {
1275 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1276 .has_inbox = false,
1277 .has_outbox = true,
1278 .out_is_imm = false,
1279 .encode_slave_id = false,
1280 .verify = NULL,
1281 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1282 },
1283 {
1284 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1285 .has_inbox = false,
1286 .has_outbox = false,
1287 .out_is_imm = false,
1288 .encode_slave_id = false,
1289 .verify = NULL,
1290 .wrapper = NULL
1291 },
1292 /* flow steering commands */
1293 {
1294 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1295 .has_inbox = true,
1296 .has_outbox = false,
1297 .out_is_imm = true,
1298 .encode_slave_id = false,
1299 .verify = NULL,
1300 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1301 },
1302 {
1303 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1304 .has_inbox = false,
1305 .has_outbox = false,
1306 .out_is_imm = false,
1307 .encode_slave_id = false,
1308 .verify = NULL,
1309 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1310 },
1311 };
1312
1313 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1314 struct mlx4_vhcr_cmd *in_vhcr)
1315 {
1316 struct mlx4_priv *priv = mlx4_priv(dev);
1317 struct mlx4_cmd_info *cmd = NULL;
1318 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1319 struct mlx4_vhcr *vhcr;
1320 struct mlx4_cmd_mailbox *inbox = NULL;
1321 struct mlx4_cmd_mailbox *outbox = NULL;
1322 u64 in_param;
1323 u64 out_param;
1324 int ret = 0;
1325 int i;
1326 int err = 0;
1327
1328 /* Create sw representation of Virtual HCR */
1329 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1330 if (!vhcr)
1331 return -ENOMEM;
1332
1333 /* DMA in the vHCR */
1334 if (!in_vhcr) {
1335 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1336 priv->mfunc.master.slave_state[slave].vhcr_dma,
1337 ALIGN(sizeof(struct mlx4_vhcr_cmd),
1338 MLX4_ACCESS_MEM_ALIGN), 1);
1339 if (ret) {
1340 mlx4_err(dev, "%s:Failed reading vhcr"
1341 "ret: 0x%x\n", __func__, ret);
1342 kfree(vhcr);
1343 return ret;
1344 }
1345 }
1346
1347 /* Fill SW VHCR fields */
1348 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1349 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1350 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1351 vhcr->token = be16_to_cpu(vhcr_cmd->token);
1352 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1353 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1354 vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1355
1356 /* Lookup command */
1357 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1358 if (vhcr->op == cmd_info[i].opcode) {
1359 cmd = &cmd_info[i];
1360 break;
1361 }
1362 }
1363 if (!cmd) {
1364 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1365 vhcr->op, slave);
1366 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1367 goto out_status;
1368 }
1369
1370 /* Read inbox */
1371 if (cmd->has_inbox) {
1372 vhcr->in_param &= INBOX_MASK;
1373 inbox = mlx4_alloc_cmd_mailbox(dev);
1374 if (IS_ERR(inbox)) {
1375 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1376 inbox = NULL;
1377 goto out_status;
1378 }
1379
1380 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1381 vhcr->in_param,
1382 MLX4_MAILBOX_SIZE, 1)) {
1383 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1384 __func__, cmd->opcode);
1385 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1386 goto out_status;
1387 }
1388 }
1389
1390 /* Apply permission and bound checks if applicable */
1391 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1392 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection "
1393 "checks for resource_id:%d\n", vhcr->op, slave,
1394 vhcr->in_modifier);
1395 vhcr_cmd->status = CMD_STAT_BAD_OP;
1396 goto out_status;
1397 }
1398
1399 /* Allocate outbox */
1400 if (cmd->has_outbox) {
1401 outbox = mlx4_alloc_cmd_mailbox(dev);
1402 if (IS_ERR(outbox)) {
1403 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1404 outbox = NULL;
1405 goto out_status;
1406 }
1407 }
1408
1409 /* Execute the command! */
1410 if (cmd->wrapper) {
1411 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1412 cmd);
1413 if (cmd->out_is_imm)
1414 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1415 } else {
1416 in_param = cmd->has_inbox ? (u64) inbox->dma :
1417 vhcr->in_param;
1418 out_param = cmd->has_outbox ? (u64) outbox->dma :
1419 vhcr->out_param;
1420 err = __mlx4_cmd(dev, in_param, &out_param,
1421 cmd->out_is_imm, vhcr->in_modifier,
1422 vhcr->op_modifier, vhcr->op,
1423 MLX4_CMD_TIME_CLASS_A,
1424 MLX4_CMD_NATIVE);
1425
1426 if (cmd->out_is_imm) {
1427 vhcr->out_param = out_param;
1428 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1429 }
1430 }
1431
1432 if (err) {
1433 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with"
1434 " error:%d, status %d\n",
1435 vhcr->op, slave, vhcr->errno, err);
1436 vhcr_cmd->status = mlx4_errno_to_status(err);
1437 goto out_status;
1438 }
1439
1440
1441 /* Write outbox if command completed successfully */
1442 if (cmd->has_outbox && !vhcr_cmd->status) {
1443 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1444 vhcr->out_param,
1445 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1446 if (ret) {
1447 /* If we failed to write back the outbox after the
1448 *command was successfully executed, we must fail this
1449 * slave, as it is now in undefined state */
1450 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1451 goto out;
1452 }
1453 }
1454
1455 out_status:
1456 /* DMA back vhcr result */
1457 if (!in_vhcr) {
1458 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1459 priv->mfunc.master.slave_state[slave].vhcr_dma,
1460 ALIGN(sizeof(struct mlx4_vhcr),
1461 MLX4_ACCESS_MEM_ALIGN),
1462 MLX4_CMD_WRAPPED);
1463 if (ret)
1464 mlx4_err(dev, "%s:Failed writing vhcr result\n",
1465 __func__);
1466 else if (vhcr->e_bit &&
1467 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1468 mlx4_warn(dev, "Failed to generate command completion "
1469 "eqe for slave %d\n", slave);
1470 }
1471
1472 out:
1473 kfree(vhcr);
1474 mlx4_free_cmd_mailbox(dev, inbox);
1475 mlx4_free_cmd_mailbox(dev, outbox);
1476 return ret;
1477 }
1478
1479 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1480 u16 param, u8 toggle)
1481 {
1482 struct mlx4_priv *priv = mlx4_priv(dev);
1483 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1484 u32 reply;
1485 u8 is_going_down = 0;
1486 int i;
1487
1488 slave_state[slave].comm_toggle ^= 1;
1489 reply = (u32) slave_state[slave].comm_toggle << 31;
1490 if (toggle != slave_state[slave].comm_toggle) {
1491 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER"
1492 "STATE COMPROMISIED ***\n", toggle, slave);
1493 goto reset_slave;
1494 }
1495 if (cmd == MLX4_COMM_CMD_RESET) {
1496 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1497 slave_state[slave].active = false;
1498 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1499 slave_state[slave].event_eq[i].eqn = -1;
1500 slave_state[slave].event_eq[i].token = 0;
1501 }
1502 /*check if we are in the middle of FLR process,
1503 if so return "retry" status to the slave*/
1504 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
1505 goto inform_slave_state;
1506
1507 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
1508
1509 /* write the version in the event field */
1510 reply |= mlx4_comm_get_version();
1511
1512 goto reset_slave;
1513 }
1514 /*command from slave in the middle of FLR*/
1515 if (cmd != MLX4_COMM_CMD_RESET &&
1516 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1517 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) "
1518 "in the middle of FLR\n", slave, cmd);
1519 return;
1520 }
1521
1522 switch (cmd) {
1523 case MLX4_COMM_CMD_VHCR0:
1524 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1525 goto reset_slave;
1526 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1527 priv->mfunc.master.slave_state[slave].cookie = 0;
1528 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1529 break;
1530 case MLX4_COMM_CMD_VHCR1:
1531 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1532 goto reset_slave;
1533 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1534 break;
1535 case MLX4_COMM_CMD_VHCR2:
1536 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1537 goto reset_slave;
1538 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1539 break;
1540 case MLX4_COMM_CMD_VHCR_EN:
1541 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
1542 goto reset_slave;
1543 slave_state[slave].vhcr_dma |= param;
1544 slave_state[slave].active = true;
1545 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
1546 break;
1547 case MLX4_COMM_CMD_VHCR_POST:
1548 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
1549 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST))
1550 goto reset_slave;
1551 down(&priv->cmd.slave_sem);
1552 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1553 mlx4_err(dev, "Failed processing vhcr for slave:%d,"
1554 " resetting slave.\n", slave);
1555 up(&priv->cmd.slave_sem);
1556 goto reset_slave;
1557 }
1558 up(&priv->cmd.slave_sem);
1559 break;
1560 default:
1561 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
1562 goto reset_slave;
1563 }
1564 spin_lock(&priv->mfunc.master.slave_state_lock);
1565 if (!slave_state[slave].is_slave_going_down)
1566 slave_state[slave].last_cmd = cmd;
1567 else
1568 is_going_down = 1;
1569 spin_unlock(&priv->mfunc.master.slave_state_lock);
1570 if (is_going_down) {
1571 mlx4_warn(dev, "Slave is going down aborting command(%d)"
1572 " executing from slave:%d\n",
1573 cmd, slave);
1574 return;
1575 }
1576 __raw_writel((__force u32) cpu_to_be32(reply),
1577 &priv->mfunc.comm[slave].slave_read);
1578 mmiowb();
1579
1580 return;
1581
1582 reset_slave:
1583 /* cleanup any slave resources */
1584 mlx4_delete_all_resources_for_slave(dev, slave);
1585 spin_lock(&priv->mfunc.master.slave_state_lock);
1586 if (!slave_state[slave].is_slave_going_down)
1587 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
1588 spin_unlock(&priv->mfunc.master.slave_state_lock);
1589 /*with slave in the middle of flr, no need to clean resources again.*/
1590 inform_slave_state:
1591 memset(&slave_state[slave].event_eq, 0,
1592 sizeof(struct mlx4_slave_event_eq_info));
1593 __raw_writel((__force u32) cpu_to_be32(reply),
1594 &priv->mfunc.comm[slave].slave_read);
1595 wmb();
1596 }
1597
1598 /* master command processing */
1599 void mlx4_master_comm_channel(struct work_struct *work)
1600 {
1601 struct mlx4_mfunc_master_ctx *master =
1602 container_of(work,
1603 struct mlx4_mfunc_master_ctx,
1604 comm_work);
1605 struct mlx4_mfunc *mfunc =
1606 container_of(master, struct mlx4_mfunc, master);
1607 struct mlx4_priv *priv =
1608 container_of(mfunc, struct mlx4_priv, mfunc);
1609 struct mlx4_dev *dev = &priv->dev;
1610 __be32 *bit_vec;
1611 u32 comm_cmd;
1612 u32 vec;
1613 int i, j, slave;
1614 int toggle;
1615 int served = 0;
1616 int reported = 0;
1617 u32 slt;
1618
1619 bit_vec = master->comm_arm_bit_vector;
1620 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
1621 vec = be32_to_cpu(bit_vec[i]);
1622 for (j = 0; j < 32; j++) {
1623 if (!(vec & (1 << j)))
1624 continue;
1625 ++reported;
1626 slave = (i * 32) + j;
1627 comm_cmd = swab32(readl(
1628 &mfunc->comm[slave].slave_write));
1629 slt = swab32(readl(&mfunc->comm[slave].slave_read))
1630 >> 31;
1631 toggle = comm_cmd >> 31;
1632 if (toggle != slt) {
1633 if (master->slave_state[slave].comm_toggle
1634 != slt) {
1635 printk(KERN_INFO "slave %d out of sync."
1636 " read toggle %d, state toggle %d. "
1637 "Resynching.\n", slave, slt,
1638 master->slave_state[slave].comm_toggle);
1639 master->slave_state[slave].comm_toggle =
1640 slt;
1641 }
1642 mlx4_master_do_cmd(dev, slave,
1643 comm_cmd >> 16 & 0xff,
1644 comm_cmd & 0xffff, toggle);
1645 ++served;
1646 }
1647 }
1648 }
1649
1650 if (reported && reported != served)
1651 mlx4_warn(dev, "Got command event with bitmask from %d slaves"
1652 " but %d were served\n",
1653 reported, served);
1654
1655 if (mlx4_ARM_COMM_CHANNEL(dev))
1656 mlx4_warn(dev, "Failed to arm comm channel events\n");
1657 }
1658
1659 static int sync_toggles(struct mlx4_dev *dev)
1660 {
1661 struct mlx4_priv *priv = mlx4_priv(dev);
1662 int wr_toggle;
1663 int rd_toggle;
1664 unsigned long end;
1665
1666 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
1667 end = jiffies + msecs_to_jiffies(5000);
1668
1669 while (time_before(jiffies, end)) {
1670 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
1671 if (rd_toggle == wr_toggle) {
1672 priv->cmd.comm_toggle = rd_toggle;
1673 return 0;
1674 }
1675
1676 cond_resched();
1677 }
1678
1679 /*
1680 * we could reach here if for example the previous VM using this
1681 * function misbehaved and left the channel with unsynced state. We
1682 * should fix this here and give this VM a chance to use a properly
1683 * synced channel
1684 */
1685 mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
1686 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
1687 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
1688 priv->cmd.comm_toggle = 0;
1689
1690 return 0;
1691 }
1692
1693 int mlx4_multi_func_init(struct mlx4_dev *dev)
1694 {
1695 struct mlx4_priv *priv = mlx4_priv(dev);
1696 struct mlx4_slave_state *s_state;
1697 int i, j, err, port;
1698
1699 priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
1700 &priv->mfunc.vhcr_dma,
1701 GFP_KERNEL);
1702 if (!priv->mfunc.vhcr) {
1703 mlx4_err(dev, "Couldn't allocate vhcr.\n");
1704 return -ENOMEM;
1705 }
1706
1707 if (mlx4_is_master(dev))
1708 priv->mfunc.comm =
1709 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) +
1710 priv->fw.comm_base, MLX4_COMM_PAGESIZE);
1711 else
1712 priv->mfunc.comm =
1713 ioremap(pci_resource_start(dev->pdev, 2) +
1714 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
1715 if (!priv->mfunc.comm) {
1716 mlx4_err(dev, "Couldn't map communication vector.\n");
1717 goto err_vhcr;
1718 }
1719
1720 if (mlx4_is_master(dev)) {
1721 priv->mfunc.master.slave_state =
1722 kzalloc(dev->num_slaves *
1723 sizeof(struct mlx4_slave_state), GFP_KERNEL);
1724 if (!priv->mfunc.master.slave_state)
1725 goto err_comm;
1726
1727 for (i = 0; i < dev->num_slaves; ++i) {
1728 s_state = &priv->mfunc.master.slave_state[i];
1729 s_state->last_cmd = MLX4_COMM_CMD_RESET;
1730 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
1731 s_state->event_eq[j].eqn = -1;
1732 __raw_writel((__force u32) 0,
1733 &priv->mfunc.comm[i].slave_write);
1734 __raw_writel((__force u32) 0,
1735 &priv->mfunc.comm[i].slave_read);
1736 mmiowb();
1737 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1738 s_state->vlan_filter[port] =
1739 kzalloc(sizeof(struct mlx4_vlan_fltr),
1740 GFP_KERNEL);
1741 if (!s_state->vlan_filter[port]) {
1742 if (--port)
1743 kfree(s_state->vlan_filter[port]);
1744 goto err_slaves;
1745 }
1746 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
1747 }
1748 spin_lock_init(&s_state->lock);
1749 }
1750
1751 memset(&priv->mfunc.master.cmd_eqe, 0, sizeof(struct mlx4_eqe));
1752 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
1753 INIT_WORK(&priv->mfunc.master.comm_work,
1754 mlx4_master_comm_channel);
1755 INIT_WORK(&priv->mfunc.master.slave_event_work,
1756 mlx4_gen_slave_eqe);
1757 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
1758 mlx4_master_handle_slave_flr);
1759 spin_lock_init(&priv->mfunc.master.slave_state_lock);
1760 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
1761 priv->mfunc.master.comm_wq =
1762 create_singlethread_workqueue("mlx4_comm");
1763 if (!priv->mfunc.master.comm_wq)
1764 goto err_slaves;
1765
1766 if (mlx4_init_resource_tracker(dev))
1767 goto err_thread;
1768
1769 sema_init(&priv->cmd.slave_sem, 1);
1770 err = mlx4_ARM_COMM_CHANNEL(dev);
1771 if (err) {
1772 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
1773 err);
1774 goto err_resource;
1775 }
1776
1777 } else {
1778 err = sync_toggles(dev);
1779 if (err) {
1780 mlx4_err(dev, "Couldn't sync toggles\n");
1781 goto err_comm;
1782 }
1783
1784 sema_init(&priv->cmd.slave_sem, 1);
1785 }
1786 return 0;
1787
1788 err_resource:
1789 mlx4_free_resource_tracker(dev, RES_TR_FREE_ALL);
1790 err_thread:
1791 flush_workqueue(priv->mfunc.master.comm_wq);
1792 destroy_workqueue(priv->mfunc.master.comm_wq);
1793 err_slaves:
1794 while (--i) {
1795 for (port = 1; port <= MLX4_MAX_PORTS; port++)
1796 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1797 }
1798 kfree(priv->mfunc.master.slave_state);
1799 err_comm:
1800 iounmap(priv->mfunc.comm);
1801 err_vhcr:
1802 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1803 priv->mfunc.vhcr,
1804 priv->mfunc.vhcr_dma);
1805 priv->mfunc.vhcr = NULL;
1806 return -ENOMEM;
1807 }
1808
1809 int mlx4_cmd_init(struct mlx4_dev *dev)
1810 {
1811 struct mlx4_priv *priv = mlx4_priv(dev);
1812
1813 mutex_init(&priv->cmd.hcr_mutex);
1814 sema_init(&priv->cmd.poll_sem, 1);
1815 priv->cmd.use_events = 0;
1816 priv->cmd.toggle = 1;
1817
1818 priv->cmd.hcr = NULL;
1819 priv->mfunc.vhcr = NULL;
1820
1821 if (!mlx4_is_slave(dev)) {
1822 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) +
1823 MLX4_HCR_BASE, MLX4_HCR_SIZE);
1824 if (!priv->cmd.hcr) {
1825 mlx4_err(dev, "Couldn't map command register.\n");
1826 return -ENOMEM;
1827 }
1828 }
1829
1830 priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
1831 MLX4_MAILBOX_SIZE,
1832 MLX4_MAILBOX_SIZE, 0);
1833 if (!priv->cmd.pool)
1834 goto err_hcr;
1835
1836 return 0;
1837
1838 err_hcr:
1839 if (!mlx4_is_slave(dev))
1840 iounmap(priv->cmd.hcr);
1841 return -ENOMEM;
1842 }
1843
1844 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
1845 {
1846 struct mlx4_priv *priv = mlx4_priv(dev);
1847 int i, port;
1848
1849 if (mlx4_is_master(dev)) {
1850 flush_workqueue(priv->mfunc.master.comm_wq);
1851 destroy_workqueue(priv->mfunc.master.comm_wq);
1852 for (i = 0; i < dev->num_slaves; i++) {
1853 for (port = 1; port <= MLX4_MAX_PORTS; port++)
1854 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1855 }
1856 kfree(priv->mfunc.master.slave_state);
1857 }
1858
1859 iounmap(priv->mfunc.comm);
1860 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1861 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
1862 priv->mfunc.vhcr = NULL;
1863 }
1864
1865 void mlx4_cmd_cleanup(struct mlx4_dev *dev)
1866 {
1867 struct mlx4_priv *priv = mlx4_priv(dev);
1868
1869 pci_pool_destroy(priv->cmd.pool);
1870
1871 if (!mlx4_is_slave(dev))
1872 iounmap(priv->cmd.hcr);
1873 }
1874
1875 /*
1876 * Switch to using events to issue FW commands (can only be called
1877 * after event queue for command events has been initialized).
1878 */
1879 int mlx4_cmd_use_events(struct mlx4_dev *dev)
1880 {
1881 struct mlx4_priv *priv = mlx4_priv(dev);
1882 int i;
1883 int err = 0;
1884
1885 priv->cmd.context = kmalloc(priv->cmd.max_cmds *
1886 sizeof (struct mlx4_cmd_context),
1887 GFP_KERNEL);
1888 if (!priv->cmd.context)
1889 return -ENOMEM;
1890
1891 for (i = 0; i < priv->cmd.max_cmds; ++i) {
1892 priv->cmd.context[i].token = i;
1893 priv->cmd.context[i].next = i + 1;
1894 }
1895
1896 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
1897 priv->cmd.free_head = 0;
1898
1899 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
1900 spin_lock_init(&priv->cmd.context_lock);
1901
1902 for (priv->cmd.token_mask = 1;
1903 priv->cmd.token_mask < priv->cmd.max_cmds;
1904 priv->cmd.token_mask <<= 1)
1905 ; /* nothing */
1906 --priv->cmd.token_mask;
1907
1908 down(&priv->cmd.poll_sem);
1909 priv->cmd.use_events = 1;
1910
1911 return err;
1912 }
1913
1914 /*
1915 * Switch back to polling (used when shutting down the device)
1916 */
1917 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
1918 {
1919 struct mlx4_priv *priv = mlx4_priv(dev);
1920 int i;
1921
1922 priv->cmd.use_events = 0;
1923
1924 for (i = 0; i < priv->cmd.max_cmds; ++i)
1925 down(&priv->cmd.event_sem);
1926
1927 kfree(priv->cmd.context);
1928
1929 up(&priv->cmd.poll_sem);
1930 }
1931
1932 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
1933 {
1934 struct mlx4_cmd_mailbox *mailbox;
1935
1936 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
1937 if (!mailbox)
1938 return ERR_PTR(-ENOMEM);
1939
1940 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
1941 &mailbox->dma);
1942 if (!mailbox->buf) {
1943 kfree(mailbox);
1944 return ERR_PTR(-ENOMEM);
1945 }
1946
1947 return mailbox;
1948 }
1949 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
1950
1951 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
1952 struct mlx4_cmd_mailbox *mailbox)
1953 {
1954 if (!mailbox)
1955 return;
1956
1957 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
1958 kfree(mailbox);
1959 }
1960 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
1961
1962 u32 mlx4_comm_get_version(void)
1963 {
1964 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
1965 }
Linux kernel - Deliverables
This page took 0.138827 seconds and 4 git commands to generate.