2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/export.h>
38 #include <linux/pci.h>
39 #include <linux/errno.h>
41 #include <linux/mlx4/cmd.h>
42 #include <linux/semaphore.h>
43 #include <rdma/ib_smi.h>
50 #define CMD_POLL_TOKEN 0xffff
51 #define INBOX_MASK 0xffffffffffffff00ULL
53 #define CMD_CHAN_VER 1
54 #define CMD_CHAN_IF_REV 1
57 /* command completed successfully: */
59 /* Internal error (such as a bus error) occurred while processing command: */
60 CMD_STAT_INTERNAL_ERR
= 0x01,
61 /* Operation/command not supported or opcode modifier not supported: */
62 CMD_STAT_BAD_OP
= 0x02,
63 /* Parameter not supported or parameter out of range: */
64 CMD_STAT_BAD_PARAM
= 0x03,
65 /* System not enabled or bad system state: */
66 CMD_STAT_BAD_SYS_STATE
= 0x04,
67 /* Attempt to access reserved or unallocaterd resource: */
68 CMD_STAT_BAD_RESOURCE
= 0x05,
69 /* Requested resource is currently executing a command, or is otherwise busy: */
70 CMD_STAT_RESOURCE_BUSY
= 0x06,
71 /* Required capability exceeds device limits: */
72 CMD_STAT_EXCEED_LIM
= 0x08,
73 /* Resource is not in the appropriate state or ownership: */
74 CMD_STAT_BAD_RES_STATE
= 0x09,
75 /* Index out of range: */
76 CMD_STAT_BAD_INDEX
= 0x0a,
77 /* FW image corrupted: */
78 CMD_STAT_BAD_NVMEM
= 0x0b,
79 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
80 CMD_STAT_ICM_ERROR
= 0x0c,
81 /* Attempt to modify a QP/EE which is not in the presumed state: */
82 CMD_STAT_BAD_QP_STATE
= 0x10,
83 /* Bad segment parameters (Address/Size): */
84 CMD_STAT_BAD_SEG_PARAM
= 0x20,
85 /* Memory Region has Memory Windows bound to: */
86 CMD_STAT_REG_BOUND
= 0x21,
87 /* HCA local attached memory not present: */
88 CMD_STAT_LAM_NOT_PRE
= 0x22,
89 /* Bad management packet (silently discarded): */
90 CMD_STAT_BAD_PKT
= 0x30,
91 /* More outstanding CQEs in CQ than new CQ size: */
92 CMD_STAT_BAD_SIZE
= 0x40,
93 /* Multi Function device support required: */
94 CMD_STAT_MULTI_FUNC_REQ
= 0x50,
98 HCR_IN_PARAM_OFFSET
= 0x00,
99 HCR_IN_MODIFIER_OFFSET
= 0x08,
100 HCR_OUT_PARAM_OFFSET
= 0x0c,
101 HCR_TOKEN_OFFSET
= 0x14,
102 HCR_STATUS_OFFSET
= 0x18,
104 HCR_OPMOD_SHIFT
= 12,
111 GO_BIT_TIMEOUT_MSECS
= 10000
114 struct mlx4_cmd_context
{
115 struct completion done
;
123 static int mlx4_master_process_vhcr(struct mlx4_dev
*dev
, int slave
,
124 struct mlx4_vhcr_cmd
*in_vhcr
);
126 static int mlx4_status_to_errno(u8 status
)
128 static const int trans_table
[] = {
129 [CMD_STAT_INTERNAL_ERR
] = -EIO
,
130 [CMD_STAT_BAD_OP
] = -EPERM
,
131 [CMD_STAT_BAD_PARAM
] = -EINVAL
,
132 [CMD_STAT_BAD_SYS_STATE
] = -ENXIO
,
133 [CMD_STAT_BAD_RESOURCE
] = -EBADF
,
134 [CMD_STAT_RESOURCE_BUSY
] = -EBUSY
,
135 [CMD_STAT_EXCEED_LIM
] = -ENOMEM
,
136 [CMD_STAT_BAD_RES_STATE
] = -EBADF
,
137 [CMD_STAT_BAD_INDEX
] = -EBADF
,
138 [CMD_STAT_BAD_NVMEM
] = -EFAULT
,
139 [CMD_STAT_ICM_ERROR
] = -ENFILE
,
140 [CMD_STAT_BAD_QP_STATE
] = -EINVAL
,
141 [CMD_STAT_BAD_SEG_PARAM
] = -EFAULT
,
142 [CMD_STAT_REG_BOUND
] = -EBUSY
,
143 [CMD_STAT_LAM_NOT_PRE
] = -EAGAIN
,
144 [CMD_STAT_BAD_PKT
] = -EINVAL
,
145 [CMD_STAT_BAD_SIZE
] = -ENOMEM
,
146 [CMD_STAT_MULTI_FUNC_REQ
] = -EACCES
,
149 if (status
>= ARRAY_SIZE(trans_table
) ||
150 (status
!= CMD_STAT_OK
&& trans_table
[status
] == 0))
153 return trans_table
[status
];
156 static u8
mlx4_errno_to_status(int errno
)
160 return CMD_STAT_BAD_OP
;
162 return CMD_STAT_BAD_PARAM
;
164 return CMD_STAT_BAD_SYS_STATE
;
166 return CMD_STAT_RESOURCE_BUSY
;
168 return CMD_STAT_EXCEED_LIM
;
170 return CMD_STAT_ICM_ERROR
;
172 return CMD_STAT_INTERNAL_ERR
;
176 static int comm_pending(struct mlx4_dev
*dev
)
178 struct mlx4_priv
*priv
= mlx4_priv(dev
);
179 u32 status
= readl(&priv
->mfunc
.comm
->slave_read
);
181 return (swab32(status
) >> 31) != priv
->cmd
.comm_toggle
;
184 static void mlx4_comm_cmd_post(struct mlx4_dev
*dev
, u8 cmd
, u16 param
)
186 struct mlx4_priv
*priv
= mlx4_priv(dev
);
189 priv
->cmd
.comm_toggle
^= 1;
190 val
= param
| (cmd
<< 16) | (priv
->cmd
.comm_toggle
<< 31);
191 __raw_writel((__force u32
) cpu_to_be32(val
),
192 &priv
->mfunc
.comm
->slave_write
);
196 static int mlx4_comm_cmd_poll(struct mlx4_dev
*dev
, u8 cmd
, u16 param
,
197 unsigned long timeout
)
199 struct mlx4_priv
*priv
= mlx4_priv(dev
);
202 int ret_from_pending
= 0;
204 /* First, verify that the master reports correct status */
205 if (comm_pending(dev
)) {
206 mlx4_warn(dev
, "Communication channel is not idle."
207 "my toggle is %d (cmd:0x%x)\n",
208 priv
->cmd
.comm_toggle
, cmd
);
213 down(&priv
->cmd
.poll_sem
);
214 mlx4_comm_cmd_post(dev
, cmd
, param
);
216 end
= msecs_to_jiffies(timeout
) + jiffies
;
217 while (comm_pending(dev
) && time_before(jiffies
, end
))
219 ret_from_pending
= comm_pending(dev
);
220 if (ret_from_pending
) {
221 /* check if the slave is trying to boot in the middle of
222 * FLR process. The only non-zero result in the RESET command
223 * is MLX4_DELAY_RESET_SLAVE*/
224 if ((MLX4_COMM_CMD_RESET
== cmd
)) {
225 mlx4_warn(dev
, "Got slave FLRed from Communication"
226 " channel (ret:0x%x)\n", ret_from_pending
);
227 err
= MLX4_DELAY_RESET_SLAVE
;
229 mlx4_warn(dev
, "Communication channel timed out\n");
234 up(&priv
->cmd
.poll_sem
);
238 static int mlx4_comm_cmd_wait(struct mlx4_dev
*dev
, u8 op
,
239 u16 param
, unsigned long timeout
)
241 struct mlx4_cmd
*cmd
= &mlx4_priv(dev
)->cmd
;
242 struct mlx4_cmd_context
*context
;
246 down(&cmd
->event_sem
);
248 spin_lock(&cmd
->context_lock
);
249 BUG_ON(cmd
->free_head
< 0);
250 context
= &cmd
->context
[cmd
->free_head
];
251 context
->token
+= cmd
->token_mask
+ 1;
252 cmd
->free_head
= context
->next
;
253 spin_unlock(&cmd
->context_lock
);
255 init_completion(&context
->done
);
257 mlx4_comm_cmd_post(dev
, op
, param
);
259 if (!wait_for_completion_timeout(&context
->done
,
260 msecs_to_jiffies(timeout
))) {
265 err
= context
->result
;
266 if (err
&& context
->fw_status
!= CMD_STAT_MULTI_FUNC_REQ
) {
267 mlx4_err(dev
, "command 0x%x failed: fw status = 0x%x\n",
268 op
, context
->fw_status
);
273 /* wait for comm channel ready
274 * this is necessary for prevention the race
275 * when switching between event to polling mode
277 end
= msecs_to_jiffies(timeout
) + jiffies
;
278 while (comm_pending(dev
) && time_before(jiffies
, end
))
281 spin_lock(&cmd
->context_lock
);
282 context
->next
= cmd
->free_head
;
283 cmd
->free_head
= context
- cmd
->context
;
284 spin_unlock(&cmd
->context_lock
);
290 int mlx4_comm_cmd(struct mlx4_dev
*dev
, u8 cmd
, u16 param
,
291 unsigned long timeout
)
293 if (mlx4_priv(dev
)->cmd
.use_events
)
294 return mlx4_comm_cmd_wait(dev
, cmd
, param
, timeout
);
295 return mlx4_comm_cmd_poll(dev
, cmd
, param
, timeout
);
298 static int cmd_pending(struct mlx4_dev
*dev
)
302 if (pci_channel_offline(dev
->pdev
))
305 status
= readl(mlx4_priv(dev
)->cmd
.hcr
+ HCR_STATUS_OFFSET
);
307 return (status
& swab32(1 << HCR_GO_BIT
)) ||
308 (mlx4_priv(dev
)->cmd
.toggle
==
309 !!(status
& swab32(1 << HCR_T_BIT
)));
312 static int mlx4_cmd_post(struct mlx4_dev
*dev
, u64 in_param
, u64 out_param
,
313 u32 in_modifier
, u8 op_modifier
, u16 op
, u16 token
,
316 struct mlx4_cmd
*cmd
= &mlx4_priv(dev
)->cmd
;
317 u32 __iomem
*hcr
= cmd
->hcr
;
321 mutex_lock(&cmd
->hcr_mutex
);
323 if (pci_channel_offline(dev
->pdev
)) {
325 * Device is going through error recovery
326 * and cannot accept commands.
334 end
+= msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS
);
336 while (cmd_pending(dev
)) {
337 if (pci_channel_offline(dev
->pdev
)) {
339 * Device is going through error recovery
340 * and cannot accept commands.
346 if (time_after_eq(jiffies
, end
)) {
347 mlx4_err(dev
, "%s:cmd_pending failed\n", __func__
);
354 * We use writel (instead of something like memcpy_toio)
355 * because writes of less than 32 bits to the HCR don't work
356 * (and some architectures such as ia64 implement memcpy_toio
357 * in terms of writeb).
359 __raw_writel((__force u32
) cpu_to_be32(in_param
>> 32), hcr
+ 0);
360 __raw_writel((__force u32
) cpu_to_be32(in_param
& 0xfffffffful
), hcr
+ 1);
361 __raw_writel((__force u32
) cpu_to_be32(in_modifier
), hcr
+ 2);
362 __raw_writel((__force u32
) cpu_to_be32(out_param
>> 32), hcr
+ 3);
363 __raw_writel((__force u32
) cpu_to_be32(out_param
& 0xfffffffful
), hcr
+ 4);
364 __raw_writel((__force u32
) cpu_to_be32(token
<< 16), hcr
+ 5);
366 /* __raw_writel may not order writes. */
369 __raw_writel((__force u32
) cpu_to_be32((1 << HCR_GO_BIT
) |
370 (cmd
->toggle
<< HCR_T_BIT
) |
371 (event
? (1 << HCR_E_BIT
) : 0) |
372 (op_modifier
<< HCR_OPMOD_SHIFT
) |
376 * Make sure that our HCR writes don't get mixed in with
377 * writes from another CPU starting a FW command.
381 cmd
->toggle
= cmd
->toggle
^ 1;
386 mutex_unlock(&cmd
->hcr_mutex
);
390 static int mlx4_slave_cmd(struct mlx4_dev
*dev
, u64 in_param
, u64
*out_param
,
391 int out_is_imm
, u32 in_modifier
, u8 op_modifier
,
392 u16 op
, unsigned long timeout
)
394 struct mlx4_priv
*priv
= mlx4_priv(dev
);
395 struct mlx4_vhcr_cmd
*vhcr
= priv
->mfunc
.vhcr
;
398 down(&priv
->cmd
.slave_sem
);
399 vhcr
->in_param
= cpu_to_be64(in_param
);
400 vhcr
->out_param
= out_param
? cpu_to_be64(*out_param
) : 0;
401 vhcr
->in_modifier
= cpu_to_be32(in_modifier
);
402 vhcr
->opcode
= cpu_to_be16((((u16
) op_modifier
) << 12) | (op
& 0xfff));
403 vhcr
->token
= cpu_to_be16(CMD_POLL_TOKEN
);
405 vhcr
->flags
= !!(priv
->cmd
.use_events
) << 6;
406 if (mlx4_is_master(dev
)) {
407 ret
= mlx4_master_process_vhcr(dev
, dev
->caps
.function
, vhcr
);
412 be64_to_cpu(vhcr
->out_param
);
414 mlx4_err(dev
, "response expected while"
415 "output mailbox is NULL for "
416 "command 0x%x\n", op
);
417 vhcr
->status
= CMD_STAT_BAD_PARAM
;
420 ret
= mlx4_status_to_errno(vhcr
->status
);
423 ret
= mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR_POST
, 0,
424 MLX4_COMM_TIME
+ timeout
);
429 be64_to_cpu(vhcr
->out_param
);
431 mlx4_err(dev
, "response expected while"
432 "output mailbox is NULL for "
433 "command 0x%x\n", op
);
434 vhcr
->status
= CMD_STAT_BAD_PARAM
;
437 ret
= mlx4_status_to_errno(vhcr
->status
);
439 mlx4_err(dev
, "failed execution of VHCR_POST command"
440 "opcode 0x%x\n", op
);
442 up(&priv
->cmd
.slave_sem
);
446 static int mlx4_cmd_poll(struct mlx4_dev
*dev
, u64 in_param
, u64
*out_param
,
447 int out_is_imm
, u32 in_modifier
, u8 op_modifier
,
448 u16 op
, unsigned long timeout
)
450 struct mlx4_priv
*priv
= mlx4_priv(dev
);
451 void __iomem
*hcr
= priv
->cmd
.hcr
;
456 down(&priv
->cmd
.poll_sem
);
458 if (pci_channel_offline(dev
->pdev
)) {
460 * Device is going through error recovery
461 * and cannot accept commands.
467 err
= mlx4_cmd_post(dev
, in_param
, out_param
? *out_param
: 0,
468 in_modifier
, op_modifier
, op
, CMD_POLL_TOKEN
, 0);
472 end
= msecs_to_jiffies(timeout
) + jiffies
;
473 while (cmd_pending(dev
) && time_before(jiffies
, end
)) {
474 if (pci_channel_offline(dev
->pdev
)) {
476 * Device is going through error recovery
477 * and cannot accept commands.
486 if (cmd_pending(dev
)) {
493 (u64
) be32_to_cpu((__force __be32
)
494 __raw_readl(hcr
+ HCR_OUT_PARAM_OFFSET
)) << 32 |
495 (u64
) be32_to_cpu((__force __be32
)
496 __raw_readl(hcr
+ HCR_OUT_PARAM_OFFSET
+ 4));
497 stat
= be32_to_cpu((__force __be32
)
498 __raw_readl(hcr
+ HCR_STATUS_OFFSET
)) >> 24;
499 err
= mlx4_status_to_errno(stat
);
501 mlx4_err(dev
, "command 0x%x failed: fw status = 0x%x\n",
505 up(&priv
->cmd
.poll_sem
);
509 void mlx4_cmd_event(struct mlx4_dev
*dev
, u16 token
, u8 status
, u64 out_param
)
511 struct mlx4_priv
*priv
= mlx4_priv(dev
);
512 struct mlx4_cmd_context
*context
=
513 &priv
->cmd
.context
[token
& priv
->cmd
.token_mask
];
515 /* previously timed out command completing at long last */
516 if (token
!= context
->token
)
519 context
->fw_status
= status
;
520 context
->result
= mlx4_status_to_errno(status
);
521 context
->out_param
= out_param
;
523 complete(&context
->done
);
526 static int mlx4_cmd_wait(struct mlx4_dev
*dev
, u64 in_param
, u64
*out_param
,
527 int out_is_imm
, u32 in_modifier
, u8 op_modifier
,
528 u16 op
, unsigned long timeout
)
530 struct mlx4_cmd
*cmd
= &mlx4_priv(dev
)->cmd
;
531 struct mlx4_cmd_context
*context
;
534 down(&cmd
->event_sem
);
536 spin_lock(&cmd
->context_lock
);
537 BUG_ON(cmd
->free_head
< 0);
538 context
= &cmd
->context
[cmd
->free_head
];
539 context
->token
+= cmd
->token_mask
+ 1;
540 cmd
->free_head
= context
->next
;
541 spin_unlock(&cmd
->context_lock
);
543 init_completion(&context
->done
);
545 mlx4_cmd_post(dev
, in_param
, out_param
? *out_param
: 0,
546 in_modifier
, op_modifier
, op
, context
->token
, 1);
548 if (!wait_for_completion_timeout(&context
->done
,
549 msecs_to_jiffies(timeout
))) {
554 err
= context
->result
;
556 mlx4_err(dev
, "command 0x%x failed: fw status = 0x%x\n",
557 op
, context
->fw_status
);
562 *out_param
= context
->out_param
;
565 spin_lock(&cmd
->context_lock
);
566 context
->next
= cmd
->free_head
;
567 cmd
->free_head
= context
- cmd
->context
;
568 spin_unlock(&cmd
->context_lock
);
574 int __mlx4_cmd(struct mlx4_dev
*dev
, u64 in_param
, u64
*out_param
,
575 int out_is_imm
, u32 in_modifier
, u8 op_modifier
,
576 u16 op
, unsigned long timeout
, int native
)
578 if (pci_channel_offline(dev
->pdev
))
581 if (!mlx4_is_mfunc(dev
) || (native
&& mlx4_is_master(dev
))) {
582 if (mlx4_priv(dev
)->cmd
.use_events
)
583 return mlx4_cmd_wait(dev
, in_param
, out_param
,
584 out_is_imm
, in_modifier
,
585 op_modifier
, op
, timeout
);
587 return mlx4_cmd_poll(dev
, in_param
, out_param
,
588 out_is_imm
, in_modifier
,
589 op_modifier
, op
, timeout
);
591 return mlx4_slave_cmd(dev
, in_param
, out_param
, out_is_imm
,
592 in_modifier
, op_modifier
, op
, timeout
);
594 EXPORT_SYMBOL_GPL(__mlx4_cmd
);
597 static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev
*dev
)
599 return mlx4_cmd(dev
, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL
,
600 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
603 static int mlx4_ACCESS_MEM(struct mlx4_dev
*dev
, u64 master_addr
,
604 int slave
, u64 slave_addr
,
605 int size
, int is_read
)
610 if ((slave_addr
& 0xfff) | (master_addr
& 0xfff) |
611 (slave
& ~0x7f) | (size
& 0xff)) {
612 mlx4_err(dev
, "Bad access mem params - slave_addr:0x%llx "
613 "master_addr:0x%llx slave_id:%d size:%d\n",
614 slave_addr
, master_addr
, slave
, size
);
619 in_param
= (u64
) slave
| slave_addr
;
620 out_param
= (u64
) dev
->caps
.function
| master_addr
;
622 in_param
= (u64
) dev
->caps
.function
| master_addr
;
623 out_param
= (u64
) slave
| slave_addr
;
626 return mlx4_cmd_imm(dev
, in_param
, &out_param
, size
, 0,
628 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
631 static int query_pkey_block(struct mlx4_dev
*dev
, u8 port
, u16 index
, u16
*pkey
,
632 struct mlx4_cmd_mailbox
*inbox
,
633 struct mlx4_cmd_mailbox
*outbox
)
635 struct ib_smp
*in_mad
= (struct ib_smp
*)(inbox
->buf
);
636 struct ib_smp
*out_mad
= (struct ib_smp
*)(outbox
->buf
);
643 in_mad
->attr_mod
= cpu_to_be32(index
/ 32);
645 err
= mlx4_cmd_box(dev
, inbox
->dma
, outbox
->dma
, port
, 3,
646 MLX4_CMD_MAD_IFC
, MLX4_CMD_TIME_CLASS_C
,
651 for (i
= 0; i
< 32; ++i
)
652 pkey
[i
] = be16_to_cpu(((__be16
*) out_mad
->data
)[i
]);
657 static int get_full_pkey_table(struct mlx4_dev
*dev
, u8 port
, u16
*table
,
658 struct mlx4_cmd_mailbox
*inbox
,
659 struct mlx4_cmd_mailbox
*outbox
)
664 for (i
= 0; i
< dev
->caps
.pkey_table_len
[port
]; i
+= 32) {
665 err
= query_pkey_block(dev
, port
, i
, table
+ i
, inbox
, outbox
);
672 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
673 #define PORT_STATE_OFFSET 32
675 static enum ib_port_state
vf_port_state(struct mlx4_dev
*dev
, int port
, int vf
)
677 if (mlx4_get_slave_port_state(dev
, vf
, port
) == SLAVE_PORT_UP
)
678 return IB_PORT_ACTIVE
;
683 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev
*dev
, int slave
,
684 struct mlx4_vhcr
*vhcr
,
685 struct mlx4_cmd_mailbox
*inbox
,
686 struct mlx4_cmd_mailbox
*outbox
,
687 struct mlx4_cmd_info
*cmd
)
689 struct ib_smp
*smp
= inbox
->buf
;
695 struct mlx4_priv
*priv
= mlx4_priv(dev
);
696 struct ib_smp
*outsmp
= outbox
->buf
;
697 __be16
*outtab
= (__be16
*)(outsmp
->data
);
698 __be32 slave_cap_mask
;
699 port
= vhcr
->in_modifier
;
701 if (smp
->base_version
== 1 &&
702 smp
->mgmt_class
== IB_MGMT_CLASS_SUBN_LID_ROUTED
&&
703 smp
->class_version
== 1) {
704 if (smp
->method
== IB_MGMT_METHOD_GET
) {
705 if (smp
->attr_id
== IB_SMP_ATTR_PKEY_TABLE
) {
706 index
= be32_to_cpu(smp
->attr_mod
);
707 if (port
< 1 || port
> dev
->caps
.num_ports
)
709 table
= kcalloc(dev
->caps
.pkey_table_len
[port
], sizeof *table
, GFP_KERNEL
);
712 /* need to get the full pkey table because the paravirtualized
713 * pkeys may be scattered among several pkey blocks.
715 err
= get_full_pkey_table(dev
, port
, table
, inbox
, outbox
);
717 for (vidx
= index
* 32; vidx
< (index
+ 1) * 32; ++vidx
) {
718 pidx
= priv
->virt2phys_pkey
[slave
][port
- 1][vidx
];
719 outtab
[vidx
% 32] = cpu_to_be16(table
[pidx
]);
725 if (smp
->attr_id
== IB_SMP_ATTR_PORT_INFO
) {
726 /*get the slave specific caps:*/
728 err
= mlx4_cmd_box(dev
, inbox
->dma
, outbox
->dma
,
729 vhcr
->in_modifier
, vhcr
->op_modifier
,
730 vhcr
->op
, MLX4_CMD_TIME_CLASS_C
, MLX4_CMD_NATIVE
);
731 /* modify the response for slaves */
732 if (!err
&& slave
!= mlx4_master_func_num(dev
)) {
733 u8
*state
= outsmp
->data
+ PORT_STATE_OFFSET
;
735 *state
= (*state
& 0xf0) | vf_port_state(dev
, port
, slave
);
736 slave_cap_mask
= priv
->mfunc
.master
.slave_state
[slave
].ib_cap_mask
[port
];
737 memcpy(outsmp
->data
+ PORT_CAPABILITY_LOCATION_IN_SMP
, &slave_cap_mask
, 4);
741 if (smp
->attr_id
== IB_SMP_ATTR_GUID_INFO
) {
742 /* compute slave's gid block */
743 smp
->attr_mod
= cpu_to_be32(slave
/ 8);
745 err
= mlx4_cmd_box(dev
, inbox
->dma
, outbox
->dma
,
746 vhcr
->in_modifier
, vhcr
->op_modifier
,
747 vhcr
->op
, MLX4_CMD_TIME_CLASS_C
, MLX4_CMD_NATIVE
);
749 /* if needed, move slave gid to index 0 */
752 outsmp
->data
+ (slave
% 8) * 8, 8);
753 /* delete all other gids */
754 memset(outsmp
->data
+ 8, 0, 56);
760 if (slave
!= mlx4_master_func_num(dev
) &&
761 ((smp
->mgmt_class
== IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE
) ||
762 (smp
->mgmt_class
== IB_MGMT_CLASS_SUBN_LID_ROUTED
&&
763 smp
->method
== IB_MGMT_METHOD_SET
))) {
764 mlx4_err(dev
, "slave %d is trying to execute a Subnet MGMT MAD, "
765 "class 0x%x, method 0x%x for attr 0x%x. Rejecting\n",
766 slave
, smp
->method
, smp
->mgmt_class
,
767 be16_to_cpu(smp
->attr_id
));
771 return mlx4_cmd_box(dev
, inbox
->dma
, outbox
->dma
,
772 vhcr
->in_modifier
, vhcr
->op_modifier
,
773 vhcr
->op
, MLX4_CMD_TIME_CLASS_C
, MLX4_CMD_NATIVE
);
776 int mlx4_DMA_wrapper(struct mlx4_dev
*dev
, int slave
,
777 struct mlx4_vhcr
*vhcr
,
778 struct mlx4_cmd_mailbox
*inbox
,
779 struct mlx4_cmd_mailbox
*outbox
,
780 struct mlx4_cmd_info
*cmd
)
786 in_param
= cmd
->has_inbox
? (u64
) inbox
->dma
: vhcr
->in_param
;
787 out_param
= cmd
->has_outbox
? (u64
) outbox
->dma
: vhcr
->out_param
;
788 if (cmd
->encode_slave_id
) {
789 in_param
&= 0xffffffffffffff00ll
;
793 err
= __mlx4_cmd(dev
, in_param
, &out_param
, cmd
->out_is_imm
,
794 vhcr
->in_modifier
, vhcr
->op_modifier
, vhcr
->op
,
795 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
798 vhcr
->out_param
= out_param
;
803 static struct mlx4_cmd_info cmd_info
[] = {
805 .opcode
= MLX4_CMD_QUERY_FW
,
809 .encode_slave_id
= false,
811 .wrapper
= mlx4_QUERY_FW_wrapper
814 .opcode
= MLX4_CMD_QUERY_HCA
,
818 .encode_slave_id
= false,
823 .opcode
= MLX4_CMD_QUERY_DEV_CAP
,
827 .encode_slave_id
= false,
829 .wrapper
= mlx4_QUERY_DEV_CAP_wrapper
832 .opcode
= MLX4_CMD_QUERY_FUNC_CAP
,
836 .encode_slave_id
= false,
838 .wrapper
= mlx4_QUERY_FUNC_CAP_wrapper
841 .opcode
= MLX4_CMD_QUERY_ADAPTER
,
845 .encode_slave_id
= false,
850 .opcode
= MLX4_CMD_INIT_PORT
,
854 .encode_slave_id
= false,
856 .wrapper
= mlx4_INIT_PORT_wrapper
859 .opcode
= MLX4_CMD_CLOSE_PORT
,
863 .encode_slave_id
= false,
865 .wrapper
= mlx4_CLOSE_PORT_wrapper
868 .opcode
= MLX4_CMD_QUERY_PORT
,
872 .encode_slave_id
= false,
874 .wrapper
= mlx4_QUERY_PORT_wrapper
877 .opcode
= MLX4_CMD_SET_PORT
,
881 .encode_slave_id
= false,
883 .wrapper
= mlx4_SET_PORT_wrapper
886 .opcode
= MLX4_CMD_MAP_EQ
,
890 .encode_slave_id
= false,
892 .wrapper
= mlx4_MAP_EQ_wrapper
895 .opcode
= MLX4_CMD_SW2HW_EQ
,
899 .encode_slave_id
= true,
901 .wrapper
= mlx4_SW2HW_EQ_wrapper
904 .opcode
= MLX4_CMD_HW_HEALTH_CHECK
,
908 .encode_slave_id
= false,
913 .opcode
= MLX4_CMD_NOP
,
917 .encode_slave_id
= false,
922 .opcode
= MLX4_CMD_ALLOC_RES
,
926 .encode_slave_id
= false,
928 .wrapper
= mlx4_ALLOC_RES_wrapper
931 .opcode
= MLX4_CMD_FREE_RES
,
935 .encode_slave_id
= false,
937 .wrapper
= mlx4_FREE_RES_wrapper
940 .opcode
= MLX4_CMD_SW2HW_MPT
,
944 .encode_slave_id
= true,
946 .wrapper
= mlx4_SW2HW_MPT_wrapper
949 .opcode
= MLX4_CMD_QUERY_MPT
,
953 .encode_slave_id
= false,
955 .wrapper
= mlx4_QUERY_MPT_wrapper
958 .opcode
= MLX4_CMD_HW2SW_MPT
,
962 .encode_slave_id
= false,
964 .wrapper
= mlx4_HW2SW_MPT_wrapper
967 .opcode
= MLX4_CMD_READ_MTT
,
971 .encode_slave_id
= false,
976 .opcode
= MLX4_CMD_WRITE_MTT
,
980 .encode_slave_id
= false,
982 .wrapper
= mlx4_WRITE_MTT_wrapper
985 .opcode
= MLX4_CMD_SYNC_TPT
,
989 .encode_slave_id
= false,
994 .opcode
= MLX4_CMD_HW2SW_EQ
,
998 .encode_slave_id
= true,
1000 .wrapper
= mlx4_HW2SW_EQ_wrapper
1003 .opcode
= MLX4_CMD_QUERY_EQ
,
1006 .out_is_imm
= false,
1007 .encode_slave_id
= true,
1009 .wrapper
= mlx4_QUERY_EQ_wrapper
1012 .opcode
= MLX4_CMD_SW2HW_CQ
,
1014 .has_outbox
= false,
1015 .out_is_imm
= false,
1016 .encode_slave_id
= true,
1018 .wrapper
= mlx4_SW2HW_CQ_wrapper
1021 .opcode
= MLX4_CMD_HW2SW_CQ
,
1023 .has_outbox
= false,
1024 .out_is_imm
= false,
1025 .encode_slave_id
= false,
1027 .wrapper
= mlx4_HW2SW_CQ_wrapper
1030 .opcode
= MLX4_CMD_QUERY_CQ
,
1033 .out_is_imm
= false,
1034 .encode_slave_id
= false,
1036 .wrapper
= mlx4_QUERY_CQ_wrapper
1039 .opcode
= MLX4_CMD_MODIFY_CQ
,
1041 .has_outbox
= false,
1043 .encode_slave_id
= false,
1045 .wrapper
= mlx4_MODIFY_CQ_wrapper
1048 .opcode
= MLX4_CMD_SW2HW_SRQ
,
1050 .has_outbox
= false,
1051 .out_is_imm
= false,
1052 .encode_slave_id
= true,
1054 .wrapper
= mlx4_SW2HW_SRQ_wrapper
1057 .opcode
= MLX4_CMD_HW2SW_SRQ
,
1059 .has_outbox
= false,
1060 .out_is_imm
= false,
1061 .encode_slave_id
= false,
1063 .wrapper
= mlx4_HW2SW_SRQ_wrapper
1066 .opcode
= MLX4_CMD_QUERY_SRQ
,
1069 .out_is_imm
= false,
1070 .encode_slave_id
= false,
1072 .wrapper
= mlx4_QUERY_SRQ_wrapper
1075 .opcode
= MLX4_CMD_ARM_SRQ
,
1077 .has_outbox
= false,
1078 .out_is_imm
= false,
1079 .encode_slave_id
= false,
1081 .wrapper
= mlx4_ARM_SRQ_wrapper
1084 .opcode
= MLX4_CMD_RST2INIT_QP
,
1086 .has_outbox
= false,
1087 .out_is_imm
= false,
1088 .encode_slave_id
= true,
1090 .wrapper
= mlx4_RST2INIT_QP_wrapper
1093 .opcode
= MLX4_CMD_INIT2INIT_QP
,
1095 .has_outbox
= false,
1096 .out_is_imm
= false,
1097 .encode_slave_id
= false,
1099 .wrapper
= mlx4_INIT2INIT_QP_wrapper
1102 .opcode
= MLX4_CMD_INIT2RTR_QP
,
1104 .has_outbox
= false,
1105 .out_is_imm
= false,
1106 .encode_slave_id
= false,
1108 .wrapper
= mlx4_INIT2RTR_QP_wrapper
1111 .opcode
= MLX4_CMD_RTR2RTS_QP
,
1113 .has_outbox
= false,
1114 .out_is_imm
= false,
1115 .encode_slave_id
= false,
1117 .wrapper
= mlx4_RTR2RTS_QP_wrapper
1120 .opcode
= MLX4_CMD_RTS2RTS_QP
,
1122 .has_outbox
= false,
1123 .out_is_imm
= false,
1124 .encode_slave_id
= false,
1126 .wrapper
= mlx4_RTS2RTS_QP_wrapper
1129 .opcode
= MLX4_CMD_SQERR2RTS_QP
,
1131 .has_outbox
= false,
1132 .out_is_imm
= false,
1133 .encode_slave_id
= false,
1135 .wrapper
= mlx4_SQERR2RTS_QP_wrapper
1138 .opcode
= MLX4_CMD_2ERR_QP
,
1140 .has_outbox
= false,
1141 .out_is_imm
= false,
1142 .encode_slave_id
= false,
1144 .wrapper
= mlx4_GEN_QP_wrapper
1147 .opcode
= MLX4_CMD_RTS2SQD_QP
,
1149 .has_outbox
= false,
1150 .out_is_imm
= false,
1151 .encode_slave_id
= false,
1153 .wrapper
= mlx4_GEN_QP_wrapper
1156 .opcode
= MLX4_CMD_SQD2SQD_QP
,
1158 .has_outbox
= false,
1159 .out_is_imm
= false,
1160 .encode_slave_id
= false,
1162 .wrapper
= mlx4_SQD2SQD_QP_wrapper
1165 .opcode
= MLX4_CMD_SQD2RTS_QP
,
1167 .has_outbox
= false,
1168 .out_is_imm
= false,
1169 .encode_slave_id
= false,
1171 .wrapper
= mlx4_SQD2RTS_QP_wrapper
1174 .opcode
= MLX4_CMD_2RST_QP
,
1176 .has_outbox
= false,
1177 .out_is_imm
= false,
1178 .encode_slave_id
= false,
1180 .wrapper
= mlx4_2RST_QP_wrapper
1183 .opcode
= MLX4_CMD_QUERY_QP
,
1186 .out_is_imm
= false,
1187 .encode_slave_id
= false,
1189 .wrapper
= mlx4_GEN_QP_wrapper
1192 .opcode
= MLX4_CMD_SUSPEND_QP
,
1194 .has_outbox
= false,
1195 .out_is_imm
= false,
1196 .encode_slave_id
= false,
1198 .wrapper
= mlx4_GEN_QP_wrapper
1201 .opcode
= MLX4_CMD_UNSUSPEND_QP
,
1203 .has_outbox
= false,
1204 .out_is_imm
= false,
1205 .encode_slave_id
= false,
1207 .wrapper
= mlx4_GEN_QP_wrapper
1210 .opcode
= MLX4_CMD_CONF_SPECIAL_QP
,
1212 .has_outbox
= false,
1213 .out_is_imm
= false,
1214 .encode_slave_id
= false,
1215 .verify
= NULL
, /* XXX verify: only demux can do this */
1219 .opcode
= MLX4_CMD_MAD_IFC
,
1222 .out_is_imm
= false,
1223 .encode_slave_id
= false,
1225 .wrapper
= mlx4_MAD_IFC_wrapper
1228 .opcode
= MLX4_CMD_QUERY_IF_STAT
,
1231 .out_is_imm
= false,
1232 .encode_slave_id
= false,
1234 .wrapper
= mlx4_QUERY_IF_STAT_wrapper
1236 /* Native multicast commands are not available for guests */
1238 .opcode
= MLX4_CMD_QP_ATTACH
,
1240 .has_outbox
= false,
1241 .out_is_imm
= false,
1242 .encode_slave_id
= false,
1244 .wrapper
= mlx4_QP_ATTACH_wrapper
1247 .opcode
= MLX4_CMD_PROMISC
,
1249 .has_outbox
= false,
1250 .out_is_imm
= false,
1251 .encode_slave_id
= false,
1253 .wrapper
= mlx4_PROMISC_wrapper
1255 /* Ethernet specific commands */
1257 .opcode
= MLX4_CMD_SET_VLAN_FLTR
,
1259 .has_outbox
= false,
1260 .out_is_imm
= false,
1261 .encode_slave_id
= false,
1263 .wrapper
= mlx4_SET_VLAN_FLTR_wrapper
1266 .opcode
= MLX4_CMD_SET_MCAST_FLTR
,
1268 .has_outbox
= false,
1269 .out_is_imm
= false,
1270 .encode_slave_id
= false,
1272 .wrapper
= mlx4_SET_MCAST_FLTR_wrapper
1275 .opcode
= MLX4_CMD_DUMP_ETH_STATS
,
1278 .out_is_imm
= false,
1279 .encode_slave_id
= false,
1281 .wrapper
= mlx4_DUMP_ETH_STATS_wrapper
1284 .opcode
= MLX4_CMD_INFORM_FLR_DONE
,
1286 .has_outbox
= false,
1287 .out_is_imm
= false,
1288 .encode_slave_id
= false,
1292 /* flow steering commands */
1294 .opcode
= MLX4_QP_FLOW_STEERING_ATTACH
,
1296 .has_outbox
= false,
1298 .encode_slave_id
= false,
1300 .wrapper
= mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1303 .opcode
= MLX4_QP_FLOW_STEERING_DETACH
,
1305 .has_outbox
= false,
1306 .out_is_imm
= false,
1307 .encode_slave_id
= false,
1309 .wrapper
= mlx4_QP_FLOW_STEERING_DETACH_wrapper
1313 static int mlx4_master_process_vhcr(struct mlx4_dev
*dev
, int slave
,
1314 struct mlx4_vhcr_cmd
*in_vhcr
)
1316 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1317 struct mlx4_cmd_info
*cmd
= NULL
;
1318 struct mlx4_vhcr_cmd
*vhcr_cmd
= in_vhcr
? in_vhcr
: priv
->mfunc
.vhcr
;
1319 struct mlx4_vhcr
*vhcr
;
1320 struct mlx4_cmd_mailbox
*inbox
= NULL
;
1321 struct mlx4_cmd_mailbox
*outbox
= NULL
;
1328 /* Create sw representation of Virtual HCR */
1329 vhcr
= kzalloc(sizeof(struct mlx4_vhcr
), GFP_KERNEL
);
1333 /* DMA in the vHCR */
1335 ret
= mlx4_ACCESS_MEM(dev
, priv
->mfunc
.vhcr_dma
, slave
,
1336 priv
->mfunc
.master
.slave_state
[slave
].vhcr_dma
,
1337 ALIGN(sizeof(struct mlx4_vhcr_cmd
),
1338 MLX4_ACCESS_MEM_ALIGN
), 1);
1340 mlx4_err(dev
, "%s:Failed reading vhcr"
1341 "ret: 0x%x\n", __func__
, ret
);
1347 /* Fill SW VHCR fields */
1348 vhcr
->in_param
= be64_to_cpu(vhcr_cmd
->in_param
);
1349 vhcr
->out_param
= be64_to_cpu(vhcr_cmd
->out_param
);
1350 vhcr
->in_modifier
= be32_to_cpu(vhcr_cmd
->in_modifier
);
1351 vhcr
->token
= be16_to_cpu(vhcr_cmd
->token
);
1352 vhcr
->op
= be16_to_cpu(vhcr_cmd
->opcode
) & 0xfff;
1353 vhcr
->op_modifier
= (u8
) (be16_to_cpu(vhcr_cmd
->opcode
) >> 12);
1354 vhcr
->e_bit
= vhcr_cmd
->flags
& (1 << 6);
1356 /* Lookup command */
1357 for (i
= 0; i
< ARRAY_SIZE(cmd_info
); ++i
) {
1358 if (vhcr
->op
== cmd_info
[i
].opcode
) {
1364 mlx4_err(dev
, "Unknown command:0x%x accepted from slave:%d\n",
1366 vhcr_cmd
->status
= CMD_STAT_BAD_PARAM
;
1371 if (cmd
->has_inbox
) {
1372 vhcr
->in_param
&= INBOX_MASK
;
1373 inbox
= mlx4_alloc_cmd_mailbox(dev
);
1374 if (IS_ERR(inbox
)) {
1375 vhcr_cmd
->status
= CMD_STAT_BAD_SIZE
;
1380 if (mlx4_ACCESS_MEM(dev
, inbox
->dma
, slave
,
1382 MLX4_MAILBOX_SIZE
, 1)) {
1383 mlx4_err(dev
, "%s: Failed reading inbox (cmd:0x%x)\n",
1384 __func__
, cmd
->opcode
);
1385 vhcr_cmd
->status
= CMD_STAT_INTERNAL_ERR
;
1390 /* Apply permission and bound checks if applicable */
1391 if (cmd
->verify
&& cmd
->verify(dev
, slave
, vhcr
, inbox
)) {
1392 mlx4_warn(dev
, "Command:0x%x from slave: %d failed protection "
1393 "checks for resource_id:%d\n", vhcr
->op
, slave
,
1395 vhcr_cmd
->status
= CMD_STAT_BAD_OP
;
1399 /* Allocate outbox */
1400 if (cmd
->has_outbox
) {
1401 outbox
= mlx4_alloc_cmd_mailbox(dev
);
1402 if (IS_ERR(outbox
)) {
1403 vhcr_cmd
->status
= CMD_STAT_BAD_SIZE
;
1409 /* Execute the command! */
1411 err
= cmd
->wrapper(dev
, slave
, vhcr
, inbox
, outbox
,
1413 if (cmd
->out_is_imm
)
1414 vhcr_cmd
->out_param
= cpu_to_be64(vhcr
->out_param
);
1416 in_param
= cmd
->has_inbox
? (u64
) inbox
->dma
:
1418 out_param
= cmd
->has_outbox
? (u64
) outbox
->dma
:
1420 err
= __mlx4_cmd(dev
, in_param
, &out_param
,
1421 cmd
->out_is_imm
, vhcr
->in_modifier
,
1422 vhcr
->op_modifier
, vhcr
->op
,
1423 MLX4_CMD_TIME_CLASS_A
,
1426 if (cmd
->out_is_imm
) {
1427 vhcr
->out_param
= out_param
;
1428 vhcr_cmd
->out_param
= cpu_to_be64(vhcr
->out_param
);
1433 mlx4_warn(dev
, "vhcr command:0x%x slave:%d failed with"
1434 " error:%d, status %d\n",
1435 vhcr
->op
, slave
, vhcr
->errno
, err
);
1436 vhcr_cmd
->status
= mlx4_errno_to_status(err
);
1441 /* Write outbox if command completed successfully */
1442 if (cmd
->has_outbox
&& !vhcr_cmd
->status
) {
1443 ret
= mlx4_ACCESS_MEM(dev
, outbox
->dma
, slave
,
1445 MLX4_MAILBOX_SIZE
, MLX4_CMD_WRAPPED
);
1447 /* If we failed to write back the outbox after the
1448 *command was successfully executed, we must fail this
1449 * slave, as it is now in undefined state */
1450 mlx4_err(dev
, "%s:Failed writing outbox\n", __func__
);
1456 /* DMA back vhcr result */
1458 ret
= mlx4_ACCESS_MEM(dev
, priv
->mfunc
.vhcr_dma
, slave
,
1459 priv
->mfunc
.master
.slave_state
[slave
].vhcr_dma
,
1460 ALIGN(sizeof(struct mlx4_vhcr
),
1461 MLX4_ACCESS_MEM_ALIGN
),
1464 mlx4_err(dev
, "%s:Failed writing vhcr result\n",
1466 else if (vhcr
->e_bit
&&
1467 mlx4_GEN_EQE(dev
, slave
, &priv
->mfunc
.master
.cmd_eqe
))
1468 mlx4_warn(dev
, "Failed to generate command completion "
1469 "eqe for slave %d\n", slave
);
1474 mlx4_free_cmd_mailbox(dev
, inbox
);
1475 mlx4_free_cmd_mailbox(dev
, outbox
);
1479 static void mlx4_master_do_cmd(struct mlx4_dev
*dev
, int slave
, u8 cmd
,
1480 u16 param
, u8 toggle
)
1482 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1483 struct mlx4_slave_state
*slave_state
= priv
->mfunc
.master
.slave_state
;
1485 u8 is_going_down
= 0;
1488 slave_state
[slave
].comm_toggle
^= 1;
1489 reply
= (u32
) slave_state
[slave
].comm_toggle
<< 31;
1490 if (toggle
!= slave_state
[slave
].comm_toggle
) {
1491 mlx4_warn(dev
, "Incorrect toggle %d from slave %d. *** MASTER"
1492 "STATE COMPROMISIED ***\n", toggle
, slave
);
1495 if (cmd
== MLX4_COMM_CMD_RESET
) {
1496 mlx4_warn(dev
, "Received reset from slave:%d\n", slave
);
1497 slave_state
[slave
].active
= false;
1498 for (i
= 0; i
< MLX4_EVENT_TYPES_NUM
; ++i
) {
1499 slave_state
[slave
].event_eq
[i
].eqn
= -1;
1500 slave_state
[slave
].event_eq
[i
].token
= 0;
1502 /*check if we are in the middle of FLR process,
1503 if so return "retry" status to the slave*/
1504 if (MLX4_COMM_CMD_FLR
== slave_state
[slave
].last_cmd
)
1505 goto inform_slave_state
;
1507 mlx4_dispatch_event(dev
, MLX4_DEV_EVENT_SLAVE_SHUTDOWN
, slave
);
1509 /* write the version in the event field */
1510 reply
|= mlx4_comm_get_version();
1514 /*command from slave in the middle of FLR*/
1515 if (cmd
!= MLX4_COMM_CMD_RESET
&&
1516 MLX4_COMM_CMD_FLR
== slave_state
[slave
].last_cmd
) {
1517 mlx4_warn(dev
, "slave:%d is Trying to run cmd(0x%x) "
1518 "in the middle of FLR\n", slave
, cmd
);
1523 case MLX4_COMM_CMD_VHCR0
:
1524 if (slave_state
[slave
].last_cmd
!= MLX4_COMM_CMD_RESET
)
1526 slave_state
[slave
].vhcr_dma
= ((u64
) param
) << 48;
1527 priv
->mfunc
.master
.slave_state
[slave
].cookie
= 0;
1528 mutex_init(&priv
->mfunc
.master
.gen_eqe_mutex
[slave
]);
1530 case MLX4_COMM_CMD_VHCR1
:
1531 if (slave_state
[slave
].last_cmd
!= MLX4_COMM_CMD_VHCR0
)
1533 slave_state
[slave
].vhcr_dma
|= ((u64
) param
) << 32;
1535 case MLX4_COMM_CMD_VHCR2
:
1536 if (slave_state
[slave
].last_cmd
!= MLX4_COMM_CMD_VHCR1
)
1538 slave_state
[slave
].vhcr_dma
|= ((u64
) param
) << 16;
1540 case MLX4_COMM_CMD_VHCR_EN
:
1541 if (slave_state
[slave
].last_cmd
!= MLX4_COMM_CMD_VHCR2
)
1543 slave_state
[slave
].vhcr_dma
|= param
;
1544 slave_state
[slave
].active
= true;
1545 mlx4_dispatch_event(dev
, MLX4_DEV_EVENT_SLAVE_INIT
, slave
);
1547 case MLX4_COMM_CMD_VHCR_POST
:
1548 if ((slave_state
[slave
].last_cmd
!= MLX4_COMM_CMD_VHCR_EN
) &&
1549 (slave_state
[slave
].last_cmd
!= MLX4_COMM_CMD_VHCR_POST
))
1551 down(&priv
->cmd
.slave_sem
);
1552 if (mlx4_master_process_vhcr(dev
, slave
, NULL
)) {
1553 mlx4_err(dev
, "Failed processing vhcr for slave:%d,"
1554 " resetting slave.\n", slave
);
1555 up(&priv
->cmd
.slave_sem
);
1558 up(&priv
->cmd
.slave_sem
);
1561 mlx4_warn(dev
, "Bad comm cmd:%d from slave:%d\n", cmd
, slave
);
1564 spin_lock(&priv
->mfunc
.master
.slave_state_lock
);
1565 if (!slave_state
[slave
].is_slave_going_down
)
1566 slave_state
[slave
].last_cmd
= cmd
;
1569 spin_unlock(&priv
->mfunc
.master
.slave_state_lock
);
1570 if (is_going_down
) {
1571 mlx4_warn(dev
, "Slave is going down aborting command(%d)"
1572 " executing from slave:%d\n",
1576 __raw_writel((__force u32
) cpu_to_be32(reply
),
1577 &priv
->mfunc
.comm
[slave
].slave_read
);
1583 /* cleanup any slave resources */
1584 mlx4_delete_all_resources_for_slave(dev
, slave
);
1585 spin_lock(&priv
->mfunc
.master
.slave_state_lock
);
1586 if (!slave_state
[slave
].is_slave_going_down
)
1587 slave_state
[slave
].last_cmd
= MLX4_COMM_CMD_RESET
;
1588 spin_unlock(&priv
->mfunc
.master
.slave_state_lock
);
1589 /*with slave in the middle of flr, no need to clean resources again.*/
1591 memset(&slave_state
[slave
].event_eq
, 0,
1592 sizeof(struct mlx4_slave_event_eq_info
));
1593 __raw_writel((__force u32
) cpu_to_be32(reply
),
1594 &priv
->mfunc
.comm
[slave
].slave_read
);
1598 /* master command processing */
1599 void mlx4_master_comm_channel(struct work_struct
*work
)
1601 struct mlx4_mfunc_master_ctx
*master
=
1603 struct mlx4_mfunc_master_ctx
,
1605 struct mlx4_mfunc
*mfunc
=
1606 container_of(master
, struct mlx4_mfunc
, master
);
1607 struct mlx4_priv
*priv
=
1608 container_of(mfunc
, struct mlx4_priv
, mfunc
);
1609 struct mlx4_dev
*dev
= &priv
->dev
;
1619 bit_vec
= master
->comm_arm_bit_vector
;
1620 for (i
= 0; i
< COMM_CHANNEL_BIT_ARRAY_SIZE
; i
++) {
1621 vec
= be32_to_cpu(bit_vec
[i
]);
1622 for (j
= 0; j
< 32; j
++) {
1623 if (!(vec
& (1 << j
)))
1626 slave
= (i
* 32) + j
;
1627 comm_cmd
= swab32(readl(
1628 &mfunc
->comm
[slave
].slave_write
));
1629 slt
= swab32(readl(&mfunc
->comm
[slave
].slave_read
))
1631 toggle
= comm_cmd
>> 31;
1632 if (toggle
!= slt
) {
1633 if (master
->slave_state
[slave
].comm_toggle
1635 printk(KERN_INFO
"slave %d out of sync."
1636 " read toggle %d, state toggle %d. "
1637 "Resynching.\n", slave
, slt
,
1638 master
->slave_state
[slave
].comm_toggle
);
1639 master
->slave_state
[slave
].comm_toggle
=
1642 mlx4_master_do_cmd(dev
, slave
,
1643 comm_cmd
>> 16 & 0xff,
1644 comm_cmd
& 0xffff, toggle
);
1650 if (reported
&& reported
!= served
)
1651 mlx4_warn(dev
, "Got command event with bitmask from %d slaves"
1652 " but %d were served\n",
1655 if (mlx4_ARM_COMM_CHANNEL(dev
))
1656 mlx4_warn(dev
, "Failed to arm comm channel events\n");
1659 static int sync_toggles(struct mlx4_dev
*dev
)
1661 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1666 wr_toggle
= swab32(readl(&priv
->mfunc
.comm
->slave_write
)) >> 31;
1667 end
= jiffies
+ msecs_to_jiffies(5000);
1669 while (time_before(jiffies
, end
)) {
1670 rd_toggle
= swab32(readl(&priv
->mfunc
.comm
->slave_read
)) >> 31;
1671 if (rd_toggle
== wr_toggle
) {
1672 priv
->cmd
.comm_toggle
= rd_toggle
;
1680 * we could reach here if for example the previous VM using this
1681 * function misbehaved and left the channel with unsynced state. We
1682 * should fix this here and give this VM a chance to use a properly
1685 mlx4_warn(dev
, "recovering from previously mis-behaved VM\n");
1686 __raw_writel((__force u32
) 0, &priv
->mfunc
.comm
->slave_read
);
1687 __raw_writel((__force u32
) 0, &priv
->mfunc
.comm
->slave_write
);
1688 priv
->cmd
.comm_toggle
= 0;
1693 int mlx4_multi_func_init(struct mlx4_dev
*dev
)
1695 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1696 struct mlx4_slave_state
*s_state
;
1697 int i
, j
, err
, port
;
1699 priv
->mfunc
.vhcr
= dma_alloc_coherent(&(dev
->pdev
->dev
), PAGE_SIZE
,
1700 &priv
->mfunc
.vhcr_dma
,
1702 if (!priv
->mfunc
.vhcr
) {
1703 mlx4_err(dev
, "Couldn't allocate vhcr.\n");
1707 if (mlx4_is_master(dev
))
1709 ioremap(pci_resource_start(dev
->pdev
, priv
->fw
.comm_bar
) +
1710 priv
->fw
.comm_base
, MLX4_COMM_PAGESIZE
);
1713 ioremap(pci_resource_start(dev
->pdev
, 2) +
1714 MLX4_SLAVE_COMM_BASE
, MLX4_COMM_PAGESIZE
);
1715 if (!priv
->mfunc
.comm
) {
1716 mlx4_err(dev
, "Couldn't map communication vector.\n");
1720 if (mlx4_is_master(dev
)) {
1721 priv
->mfunc
.master
.slave_state
=
1722 kzalloc(dev
->num_slaves
*
1723 sizeof(struct mlx4_slave_state
), GFP_KERNEL
);
1724 if (!priv
->mfunc
.master
.slave_state
)
1727 for (i
= 0; i
< dev
->num_slaves
; ++i
) {
1728 s_state
= &priv
->mfunc
.master
.slave_state
[i
];
1729 s_state
->last_cmd
= MLX4_COMM_CMD_RESET
;
1730 for (j
= 0; j
< MLX4_EVENT_TYPES_NUM
; ++j
)
1731 s_state
->event_eq
[j
].eqn
= -1;
1732 __raw_writel((__force u32
) 0,
1733 &priv
->mfunc
.comm
[i
].slave_write
);
1734 __raw_writel((__force u32
) 0,
1735 &priv
->mfunc
.comm
[i
].slave_read
);
1737 for (port
= 1; port
<= MLX4_MAX_PORTS
; port
++) {
1738 s_state
->vlan_filter
[port
] =
1739 kzalloc(sizeof(struct mlx4_vlan_fltr
),
1741 if (!s_state
->vlan_filter
[port
]) {
1743 kfree(s_state
->vlan_filter
[port
]);
1746 INIT_LIST_HEAD(&s_state
->mcast_filters
[port
]);
1748 spin_lock_init(&s_state
->lock
);
1751 memset(&priv
->mfunc
.master
.cmd_eqe
, 0, sizeof(struct mlx4_eqe
));
1752 priv
->mfunc
.master
.cmd_eqe
.type
= MLX4_EVENT_TYPE_CMD
;
1753 INIT_WORK(&priv
->mfunc
.master
.comm_work
,
1754 mlx4_master_comm_channel
);
1755 INIT_WORK(&priv
->mfunc
.master
.slave_event_work
,
1756 mlx4_gen_slave_eqe
);
1757 INIT_WORK(&priv
->mfunc
.master
.slave_flr_event_work
,
1758 mlx4_master_handle_slave_flr
);
1759 spin_lock_init(&priv
->mfunc
.master
.slave_state_lock
);
1760 priv
->mfunc
.master
.comm_wq
=
1761 create_singlethread_workqueue("mlx4_comm");
1762 if (!priv
->mfunc
.master
.comm_wq
)
1765 if (mlx4_init_resource_tracker(dev
))
1768 sema_init(&priv
->cmd
.slave_sem
, 1);
1769 err
= mlx4_ARM_COMM_CHANNEL(dev
);
1771 mlx4_err(dev
, " Failed to arm comm channel eq: %x\n",
1777 err
= sync_toggles(dev
);
1779 mlx4_err(dev
, "Couldn't sync toggles\n");
1783 sema_init(&priv
->cmd
.slave_sem
, 1);
1788 mlx4_free_resource_tracker(dev
, RES_TR_FREE_ALL
);
1790 flush_workqueue(priv
->mfunc
.master
.comm_wq
);
1791 destroy_workqueue(priv
->mfunc
.master
.comm_wq
);
1794 for (port
= 1; port
<= MLX4_MAX_PORTS
; port
++)
1795 kfree(priv
->mfunc
.master
.slave_state
[i
].vlan_filter
[port
]);
1797 kfree(priv
->mfunc
.master
.slave_state
);
1799 iounmap(priv
->mfunc
.comm
);
1801 dma_free_coherent(&(dev
->pdev
->dev
), PAGE_SIZE
,
1803 priv
->mfunc
.vhcr_dma
);
1804 priv
->mfunc
.vhcr
= NULL
;
1808 int mlx4_cmd_init(struct mlx4_dev
*dev
)
1810 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1812 mutex_init(&priv
->cmd
.hcr_mutex
);
1813 sema_init(&priv
->cmd
.poll_sem
, 1);
1814 priv
->cmd
.use_events
= 0;
1815 priv
->cmd
.toggle
= 1;
1817 priv
->cmd
.hcr
= NULL
;
1818 priv
->mfunc
.vhcr
= NULL
;
1820 if (!mlx4_is_slave(dev
)) {
1821 priv
->cmd
.hcr
= ioremap(pci_resource_start(dev
->pdev
, 0) +
1822 MLX4_HCR_BASE
, MLX4_HCR_SIZE
);
1823 if (!priv
->cmd
.hcr
) {
1824 mlx4_err(dev
, "Couldn't map command register.\n");
1829 priv
->cmd
.pool
= pci_pool_create("mlx4_cmd", dev
->pdev
,
1831 MLX4_MAILBOX_SIZE
, 0);
1832 if (!priv
->cmd
.pool
)
1838 if (!mlx4_is_slave(dev
))
1839 iounmap(priv
->cmd
.hcr
);
1843 void mlx4_multi_func_cleanup(struct mlx4_dev
*dev
)
1845 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1848 if (mlx4_is_master(dev
)) {
1849 flush_workqueue(priv
->mfunc
.master
.comm_wq
);
1850 destroy_workqueue(priv
->mfunc
.master
.comm_wq
);
1851 for (i
= 0; i
< dev
->num_slaves
; i
++) {
1852 for (port
= 1; port
<= MLX4_MAX_PORTS
; port
++)
1853 kfree(priv
->mfunc
.master
.slave_state
[i
].vlan_filter
[port
]);
1855 kfree(priv
->mfunc
.master
.slave_state
);
1858 iounmap(priv
->mfunc
.comm
);
1859 dma_free_coherent(&(dev
->pdev
->dev
), PAGE_SIZE
,
1860 priv
->mfunc
.vhcr
, priv
->mfunc
.vhcr_dma
);
1861 priv
->mfunc
.vhcr
= NULL
;
1864 void mlx4_cmd_cleanup(struct mlx4_dev
*dev
)
1866 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1868 pci_pool_destroy(priv
->cmd
.pool
);
1870 if (!mlx4_is_slave(dev
))
1871 iounmap(priv
->cmd
.hcr
);
1875 * Switch to using events to issue FW commands (can only be called
1876 * after event queue for command events has been initialized).
1878 int mlx4_cmd_use_events(struct mlx4_dev
*dev
)
1880 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1884 priv
->cmd
.context
= kmalloc(priv
->cmd
.max_cmds
*
1885 sizeof (struct mlx4_cmd_context
),
1887 if (!priv
->cmd
.context
)
1890 for (i
= 0; i
< priv
->cmd
.max_cmds
; ++i
) {
1891 priv
->cmd
.context
[i
].token
= i
;
1892 priv
->cmd
.context
[i
].next
= i
+ 1;
1895 priv
->cmd
.context
[priv
->cmd
.max_cmds
- 1].next
= -1;
1896 priv
->cmd
.free_head
= 0;
1898 sema_init(&priv
->cmd
.event_sem
, priv
->cmd
.max_cmds
);
1899 spin_lock_init(&priv
->cmd
.context_lock
);
1901 for (priv
->cmd
.token_mask
= 1;
1902 priv
->cmd
.token_mask
< priv
->cmd
.max_cmds
;
1903 priv
->cmd
.token_mask
<<= 1)
1905 --priv
->cmd
.token_mask
;
1907 down(&priv
->cmd
.poll_sem
);
1908 priv
->cmd
.use_events
= 1;
1914 * Switch back to polling (used when shutting down the device)
1916 void mlx4_cmd_use_polling(struct mlx4_dev
*dev
)
1918 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1921 priv
->cmd
.use_events
= 0;
1923 for (i
= 0; i
< priv
->cmd
.max_cmds
; ++i
)
1924 down(&priv
->cmd
.event_sem
);
1926 kfree(priv
->cmd
.context
);
1928 up(&priv
->cmd
.poll_sem
);
1931 struct mlx4_cmd_mailbox
*mlx4_alloc_cmd_mailbox(struct mlx4_dev
*dev
)
1933 struct mlx4_cmd_mailbox
*mailbox
;
1935 mailbox
= kmalloc(sizeof *mailbox
, GFP_KERNEL
);
1937 return ERR_PTR(-ENOMEM
);
1939 mailbox
->buf
= pci_pool_alloc(mlx4_priv(dev
)->cmd
.pool
, GFP_KERNEL
,
1941 if (!mailbox
->buf
) {
1943 return ERR_PTR(-ENOMEM
);
1948 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox
);
1950 void mlx4_free_cmd_mailbox(struct mlx4_dev
*dev
,
1951 struct mlx4_cmd_mailbox
*mailbox
)
1956 pci_pool_free(mlx4_priv(dev
)->cmd
.pool
, mailbox
->buf
, mailbox
->dma
);
1959 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox
);
1961 u32
mlx4_comm_get_version(void)
1963 return ((u32
) CMD_CHAN_IF_REV
<< 8) | (u32
) CMD_CHAN_VER
;