projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'queue' of git://git.kernel.org/pub/scm/linux/kernel/git/nab/target...
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / cmd.c
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/export.h>
38 #include <linux/pci.h>
39 #include <linux/errno.h>
40
41 #include <linux/mlx4/cmd.h>
42 #include <linux/semaphore.h>
43 #include <rdma/ib_smi.h>
44
45 #include <asm/io.h>
46
47 #include "mlx4.h"
48 #include "fw.h"
49
50 #define CMD_POLL_TOKEN 0xffff
51 #define INBOX_MASK 0xffffffffffffff00ULL
52
53 #define CMD_CHAN_VER 1
54 #define CMD_CHAN_IF_REV 1
55
56 enum {
57 /* command completed successfully: */
58 CMD_STAT_OK = 0x00,
59 /* Internal error (such as a bus error) occurred while processing command: */
60 CMD_STAT_INTERNAL_ERR = 0x01,
61 /* Operation/command not supported or opcode modifier not supported: */
62 CMD_STAT_BAD_OP = 0x02,
63 /* Parameter not supported or parameter out of range: */
64 CMD_STAT_BAD_PARAM = 0x03,
65 /* System not enabled or bad system state: */
66 CMD_STAT_BAD_SYS_STATE = 0x04,
67 /* Attempt to access reserved or unallocaterd resource: */
68 CMD_STAT_BAD_RESOURCE = 0x05,
69 /* Requested resource is currently executing a command, or is otherwise busy: */
70 CMD_STAT_RESOURCE_BUSY = 0x06,
71 /* Required capability exceeds device limits: */
72 CMD_STAT_EXCEED_LIM = 0x08,
73 /* Resource is not in the appropriate state or ownership: */
74 CMD_STAT_BAD_RES_STATE = 0x09,
75 /* Index out of range: */
76 CMD_STAT_BAD_INDEX = 0x0a,
77 /* FW image corrupted: */
78 CMD_STAT_BAD_NVMEM = 0x0b,
79 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
80 CMD_STAT_ICM_ERROR = 0x0c,
81 /* Attempt to modify a QP/EE which is not in the presumed state: */
82 CMD_STAT_BAD_QP_STATE = 0x10,
83 /* Bad segment parameters (Address/Size): */
84 CMD_STAT_BAD_SEG_PARAM = 0x20,
85 /* Memory Region has Memory Windows bound to: */
86 CMD_STAT_REG_BOUND = 0x21,
87 /* HCA local attached memory not present: */
88 CMD_STAT_LAM_NOT_PRE = 0x22,
89 /* Bad management packet (silently discarded): */
90 CMD_STAT_BAD_PKT = 0x30,
91 /* More outstanding CQEs in CQ than new CQ size: */
92 CMD_STAT_BAD_SIZE = 0x40,
93 /* Multi Function device support required: */
94 CMD_STAT_MULTI_FUNC_REQ = 0x50,
95 };
96
97 enum {
98 HCR_IN_PARAM_OFFSET = 0x00,
99 HCR_IN_MODIFIER_OFFSET = 0x08,
100 HCR_OUT_PARAM_OFFSET = 0x0c,
101 HCR_TOKEN_OFFSET = 0x14,
102 HCR_STATUS_OFFSET = 0x18,
103
104 HCR_OPMOD_SHIFT = 12,
105 HCR_T_BIT = 21,
106 HCR_E_BIT = 22,
107 HCR_GO_BIT = 23
108 };
109
110 enum {
111 GO_BIT_TIMEOUT_MSECS = 10000
112 };
113
114 struct mlx4_cmd_context {
115 struct completion done;
116 int result;
117 int next;
118 u64 out_param;
119 u16 token;
120 u8 fw_status;
121 };
122
123 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
124 struct mlx4_vhcr_cmd *in_vhcr);
125
126 static int mlx4_status_to_errno(u8 status)
127 {
128 static const int trans_table[] = {
129 [CMD_STAT_INTERNAL_ERR] = -EIO,
130 [CMD_STAT_BAD_OP] = -EPERM,
131 [CMD_STAT_BAD_PARAM] = -EINVAL,
132 [CMD_STAT_BAD_SYS_STATE] = -ENXIO,
133 [CMD_STAT_BAD_RESOURCE] = -EBADF,
134 [CMD_STAT_RESOURCE_BUSY] = -EBUSY,
135 [CMD_STAT_EXCEED_LIM] = -ENOMEM,
136 [CMD_STAT_BAD_RES_STATE] = -EBADF,
137 [CMD_STAT_BAD_INDEX] = -EBADF,
138 [CMD_STAT_BAD_NVMEM] = -EFAULT,
139 [CMD_STAT_ICM_ERROR] = -ENFILE,
140 [CMD_STAT_BAD_QP_STATE] = -EINVAL,
141 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
142 [CMD_STAT_REG_BOUND] = -EBUSY,
143 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
144 [CMD_STAT_BAD_PKT] = -EINVAL,
145 [CMD_STAT_BAD_SIZE] = -ENOMEM,
146 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
147 };
148
149 if (status >= ARRAY_SIZE(trans_table) ||
150 (status != CMD_STAT_OK && trans_table[status] == 0))
151 return -EIO;
152
153 return trans_table[status];
154 }
155
156 static u8 mlx4_errno_to_status(int errno)
157 {
158 switch (errno) {
159 case -EPERM:
160 return CMD_STAT_BAD_OP;
161 case -EINVAL:
162 return CMD_STAT_BAD_PARAM;
163 case -ENXIO:
164 return CMD_STAT_BAD_SYS_STATE;
165 case -EBUSY:
166 return CMD_STAT_RESOURCE_BUSY;
167 case -ENOMEM:
168 return CMD_STAT_EXCEED_LIM;
169 case -ENFILE:
170 return CMD_STAT_ICM_ERROR;
171 default:
172 return CMD_STAT_INTERNAL_ERR;
173 }
174 }
175
176 static int comm_pending(struct mlx4_dev *dev)
177 {
178 struct mlx4_priv *priv = mlx4_priv(dev);
179 u32 status = readl(&priv->mfunc.comm->slave_read);
180
181 return (swab32(status) >> 31) != priv->cmd.comm_toggle;
182 }
183
184 static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
185 {
186 struct mlx4_priv *priv = mlx4_priv(dev);
187 u32 val;
188
189 priv->cmd.comm_toggle ^= 1;
190 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
191 __raw_writel((__force u32) cpu_to_be32(val),
192 &priv->mfunc.comm->slave_write);
193 mmiowb();
194 }
195
196 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
197 unsigned long timeout)
198 {
199 struct mlx4_priv *priv = mlx4_priv(dev);
200 unsigned long end;
201 int err = 0;
202 int ret_from_pending = 0;
203
204 /* First, verify that the master reports correct status */
205 if (comm_pending(dev)) {
206 mlx4_warn(dev, "Communication channel is not idle."
207 "my toggle is %d (cmd:0x%x)\n",
208 priv->cmd.comm_toggle, cmd);
209 return -EAGAIN;
210 }
211
212 /* Write command */
213 down(&priv->cmd.poll_sem);
214 mlx4_comm_cmd_post(dev, cmd, param);
215
216 end = msecs_to_jiffies(timeout) + jiffies;
217 while (comm_pending(dev) && time_before(jiffies, end))
218 cond_resched();
219 ret_from_pending = comm_pending(dev);
220 if (ret_from_pending) {
221 /* check if the slave is trying to boot in the middle of
222 * FLR process. The only non-zero result in the RESET command
223 * is MLX4_DELAY_RESET_SLAVE*/
224 if ((MLX4_COMM_CMD_RESET == cmd)) {
225 mlx4_warn(dev, "Got slave FLRed from Communication"
226 " channel (ret:0x%x)\n", ret_from_pending);
227 err = MLX4_DELAY_RESET_SLAVE;
228 } else {
229 mlx4_warn(dev, "Communication channel timed out\n");
230 err = -ETIMEDOUT;
231 }
232 }
233
234 up(&priv->cmd.poll_sem);
235 return err;
236 }
237
238 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op,
239 u16 param, unsigned long timeout)
240 {
241 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
242 struct mlx4_cmd_context *context;
243 unsigned long end;
244 int err = 0;
245
246 down(&cmd->event_sem);
247
248 spin_lock(&cmd->context_lock);
249 BUG_ON(cmd->free_head < 0);
250 context = &cmd->context[cmd->free_head];
251 context->token += cmd->token_mask + 1;
252 cmd->free_head = context->next;
253 spin_unlock(&cmd->context_lock);
254
255 init_completion(&context->done);
256
257 mlx4_comm_cmd_post(dev, op, param);
258
259 if (!wait_for_completion_timeout(&context->done,
260 msecs_to_jiffies(timeout))) {
261 err = -EBUSY;
262 goto out;
263 }
264
265 err = context->result;
266 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
267 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
268 op, context->fw_status);
269 goto out;
270 }
271
272 out:
273 /* wait for comm channel ready
274 * this is necessary for prevention the race
275 * when switching between event to polling mode
276 */
277 end = msecs_to_jiffies(timeout) + jiffies;
278 while (comm_pending(dev) && time_before(jiffies, end))
279 cond_resched();
280
281 spin_lock(&cmd->context_lock);
282 context->next = cmd->free_head;
283 cmd->free_head = context - cmd->context;
284 spin_unlock(&cmd->context_lock);
285
286 up(&cmd->event_sem);
287 return err;
288 }
289
290 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
291 unsigned long timeout)
292 {
293 if (mlx4_priv(dev)->cmd.use_events)
294 return mlx4_comm_cmd_wait(dev, cmd, param, timeout);
295 return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
296 }
297
298 static int cmd_pending(struct mlx4_dev *dev)
299 {
300 u32 status;
301
302 if (pci_channel_offline(dev->pdev))
303 return -EIO;
304
305 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
306
307 return (status & swab32(1 << HCR_GO_BIT)) ||
308 (mlx4_priv(dev)->cmd.toggle ==
309 !!(status & swab32(1 << HCR_T_BIT)));
310 }
311
312 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
313 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
314 int event)
315 {
316 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
317 u32 __iomem *hcr = cmd->hcr;
318 int ret = -EAGAIN;
319 unsigned long end;
320
321 mutex_lock(&cmd->hcr_mutex);
322
323 if (pci_channel_offline(dev->pdev)) {
324 /*
325 * Device is going through error recovery
326 * and cannot accept commands.
327 */
328 ret = -EIO;
329 goto out;
330 }
331
332 end = jiffies;
333 if (event)
334 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
335
336 while (cmd_pending(dev)) {
337 if (pci_channel_offline(dev->pdev)) {
338 /*
339 * Device is going through error recovery
340 * and cannot accept commands.
341 */
342 ret = -EIO;
343 goto out;
344 }
345
346 if (time_after_eq(jiffies, end)) {
347 mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
348 goto out;
349 }
350 cond_resched();
351 }
352
353 /*
354 * We use writel (instead of something like memcpy_toio)
355 * because writes of less than 32 bits to the HCR don't work
356 * (and some architectures such as ia64 implement memcpy_toio
357 * in terms of writeb).
358 */
359 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
360 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
361 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
362 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
363 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
364 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
365
366 /* __raw_writel may not order writes. */
367 wmb();
368
369 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
370 (cmd->toggle << HCR_T_BIT) |
371 (event ? (1 << HCR_E_BIT) : 0) |
372 (op_modifier << HCR_OPMOD_SHIFT) |
373 op), hcr + 6);
374
375 /*
376 * Make sure that our HCR writes don't get mixed in with
377 * writes from another CPU starting a FW command.
378 */
379 mmiowb();
380
381 cmd->toggle = cmd->toggle ^ 1;
382
383 ret = 0;
384
385 out:
386 mutex_unlock(&cmd->hcr_mutex);
387 return ret;
388 }
389
390 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
391 int out_is_imm, u32 in_modifier, u8 op_modifier,
392 u16 op, unsigned long timeout)
393 {
394 struct mlx4_priv *priv = mlx4_priv(dev);
395 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
396 int ret;
397
398 mutex_lock(&priv->cmd.slave_cmd_mutex);
399
400 vhcr->in_param = cpu_to_be64(in_param);
401 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
402 vhcr->in_modifier = cpu_to_be32(in_modifier);
403 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
404 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
405 vhcr->status = 0;
406 vhcr->flags = !!(priv->cmd.use_events) << 6;
407
408 if (mlx4_is_master(dev)) {
409 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
410 if (!ret) {
411 if (out_is_imm) {
412 if (out_param)
413 *out_param =
414 be64_to_cpu(vhcr->out_param);
415 else {
416 mlx4_err(dev, "response expected while"
417 "output mailbox is NULL for "
418 "command 0x%x\n", op);
419 vhcr->status = CMD_STAT_BAD_PARAM;
420 }
421 }
422 ret = mlx4_status_to_errno(vhcr->status);
423 }
424 } else {
425 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0,
426 MLX4_COMM_TIME + timeout);
427 if (!ret) {
428 if (out_is_imm) {
429 if (out_param)
430 *out_param =
431 be64_to_cpu(vhcr->out_param);
432 else {
433 mlx4_err(dev, "response expected while"
434 "output mailbox is NULL for "
435 "command 0x%x\n", op);
436 vhcr->status = CMD_STAT_BAD_PARAM;
437 }
438 }
439 ret = mlx4_status_to_errno(vhcr->status);
440 } else
441 mlx4_err(dev, "failed execution of VHCR_POST command"
442 "opcode 0x%x\n", op);
443 }
444
445 mutex_unlock(&priv->cmd.slave_cmd_mutex);
446 return ret;
447 }
448
449 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
450 int out_is_imm, u32 in_modifier, u8 op_modifier,
451 u16 op, unsigned long timeout)
452 {
453 struct mlx4_priv *priv = mlx4_priv(dev);
454 void __iomem *hcr = priv->cmd.hcr;
455 int err = 0;
456 unsigned long end;
457 u32 stat;
458
459 down(&priv->cmd.poll_sem);
460
461 if (pci_channel_offline(dev->pdev)) {
462 /*
463 * Device is going through error recovery
464 * and cannot accept commands.
465 */
466 err = -EIO;
467 goto out;
468 }
469
470 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
471 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
472 if (err)
473 goto out;
474
475 end = msecs_to_jiffies(timeout) + jiffies;
476 while (cmd_pending(dev) && time_before(jiffies, end)) {
477 if (pci_channel_offline(dev->pdev)) {
478 /*
479 * Device is going through error recovery
480 * and cannot accept commands.
481 */
482 err = -EIO;
483 goto out;
484 }
485
486 cond_resched();
487 }
488
489 if (cmd_pending(dev)) {
490 err = -ETIMEDOUT;
491 goto out;
492 }
493
494 if (out_is_imm)
495 *out_param =
496 (u64) be32_to_cpu((__force __be32)
497 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
498 (u64) be32_to_cpu((__force __be32)
499 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
500 stat = be32_to_cpu((__force __be32)
501 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
502 err = mlx4_status_to_errno(stat);
503 if (err)
504 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
505 op, stat);
506
507 out:
508 up(&priv->cmd.poll_sem);
509 return err;
510 }
511
512 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
513 {
514 struct mlx4_priv *priv = mlx4_priv(dev);
515 struct mlx4_cmd_context *context =
516 &priv->cmd.context[token & priv->cmd.token_mask];
517
518 /* previously timed out command completing at long last */
519 if (token != context->token)
520 return;
521
522 context->fw_status = status;
523 context->result = mlx4_status_to_errno(status);
524 context->out_param = out_param;
525
526 complete(&context->done);
527 }
528
529 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
530 int out_is_imm, u32 in_modifier, u8 op_modifier,
531 u16 op, unsigned long timeout)
532 {
533 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
534 struct mlx4_cmd_context *context;
535 int err = 0;
536
537 down(&cmd->event_sem);
538
539 spin_lock(&cmd->context_lock);
540 BUG_ON(cmd->free_head < 0);
541 context = &cmd->context[cmd->free_head];
542 context->token += cmd->token_mask + 1;
543 cmd->free_head = context->next;
544 spin_unlock(&cmd->context_lock);
545
546 init_completion(&context->done);
547
548 mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
549 in_modifier, op_modifier, op, context->token, 1);
550
551 if (!wait_for_completion_timeout(&context->done,
552 msecs_to_jiffies(timeout))) {
553 err = -EBUSY;
554 goto out;
555 }
556
557 err = context->result;
558 if (err) {
559 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
560 op, context->fw_status);
561 goto out;
562 }
563
564 if (out_is_imm)
565 *out_param = context->out_param;
566
567 out:
568 spin_lock(&cmd->context_lock);
569 context->next = cmd->free_head;
570 cmd->free_head = context - cmd->context;
571 spin_unlock(&cmd->context_lock);
572
573 up(&cmd->event_sem);
574 return err;
575 }
576
577 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
578 int out_is_imm, u32 in_modifier, u8 op_modifier,
579 u16 op, unsigned long timeout, int native)
580 {
581 if (pci_channel_offline(dev->pdev))
582 return -EIO;
583
584 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
585 if (mlx4_priv(dev)->cmd.use_events)
586 return mlx4_cmd_wait(dev, in_param, out_param,
587 out_is_imm, in_modifier,
588 op_modifier, op, timeout);
589 else
590 return mlx4_cmd_poll(dev, in_param, out_param,
591 out_is_imm, in_modifier,
592 op_modifier, op, timeout);
593 }
594 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
595 in_modifier, op_modifier, op, timeout);
596 }
597 EXPORT_SYMBOL_GPL(__mlx4_cmd);
598
599
600 static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
601 {
602 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
603 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
604 }
605
606 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
607 int slave, u64 slave_addr,
608 int size, int is_read)
609 {
610 u64 in_param;
611 u64 out_param;
612
613 if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
614 (slave & ~0x7f) | (size & 0xff)) {
615 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx "
616 "master_addr:0x%llx slave_id:%d size:%d\n",
617 slave_addr, master_addr, slave, size);
618 return -EINVAL;
619 }
620
621 if (is_read) {
622 in_param = (u64) slave | slave_addr;
623 out_param = (u64) dev->caps.function | master_addr;
624 } else {
625 in_param = (u64) dev->caps.function | master_addr;
626 out_param = (u64) slave | slave_addr;
627 }
628
629 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
630 MLX4_CMD_ACCESS_MEM,
631 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
632 }
633
634 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
635 struct mlx4_cmd_mailbox *inbox,
636 struct mlx4_cmd_mailbox *outbox)
637 {
638 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
639 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
640 int err;
641 int i;
642
643 if (index & 0x1f)
644 return -EINVAL;
645
646 in_mad->attr_mod = cpu_to_be32(index / 32);
647
648 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
649 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
650 MLX4_CMD_NATIVE);
651 if (err)
652 return err;
653
654 for (i = 0; i < 32; ++i)
655 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
656
657 return err;
658 }
659
660 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
661 struct mlx4_cmd_mailbox *inbox,
662 struct mlx4_cmd_mailbox *outbox)
663 {
664 int i;
665 int err;
666
667 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
668 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
669 if (err)
670 return err;
671 }
672
673 return 0;
674 }
675 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
676 #define PORT_STATE_OFFSET 32
677
678 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
679 {
680 if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
681 return IB_PORT_ACTIVE;
682 else
683 return IB_PORT_DOWN;
684 }
685
686 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
687 struct mlx4_vhcr *vhcr,
688 struct mlx4_cmd_mailbox *inbox,
689 struct mlx4_cmd_mailbox *outbox,
690 struct mlx4_cmd_info *cmd)
691 {
692 struct ib_smp *smp = inbox->buf;
693 u32 index;
694 u8 port;
695 u16 *table;
696 int err;
697 int vidx, pidx;
698 struct mlx4_priv *priv = mlx4_priv(dev);
699 struct ib_smp *outsmp = outbox->buf;
700 __be16 *outtab = (__be16 *)(outsmp->data);
701 __be32 slave_cap_mask;
702 __be64 slave_node_guid;
703 port = vhcr->in_modifier;
704
705 if (smp->base_version == 1 &&
706 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
707 smp->class_version == 1) {
708 if (smp->method == IB_MGMT_METHOD_GET) {
709 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
710 index = be32_to_cpu(smp->attr_mod);
711 if (port < 1 || port > dev->caps.num_ports)
712 return -EINVAL;
713 table = kcalloc(dev->caps.pkey_table_len[port], sizeof *table, GFP_KERNEL);
714 if (!table)
715 return -ENOMEM;
716 /* need to get the full pkey table because the paravirtualized
717 * pkeys may be scattered among several pkey blocks.
718 */
719 err = get_full_pkey_table(dev, port, table, inbox, outbox);
720 if (!err) {
721 for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
722 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
723 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
724 }
725 }
726 kfree(table);
727 return err;
728 }
729 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
730 /*get the slave specific caps:*/
731 /*do the command */
732 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
733 vhcr->in_modifier, vhcr->op_modifier,
734 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
735 /* modify the response for slaves */
736 if (!err && slave != mlx4_master_func_num(dev)) {
737 u8 *state = outsmp->data + PORT_STATE_OFFSET;
738
739 *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
740 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
741 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
742 }
743 return err;
744 }
745 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
746 /* compute slave's gid block */
747 smp->attr_mod = cpu_to_be32(slave / 8);
748 /* execute cmd */
749 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
750 vhcr->in_modifier, vhcr->op_modifier,
751 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
752 if (!err) {
753 /* if needed, move slave gid to index 0 */
754 if (slave % 8)
755 memcpy(outsmp->data,
756 outsmp->data + (slave % 8) * 8, 8);
757 /* delete all other gids */
758 memset(outsmp->data + 8, 0, 56);
759 }
760 return err;
761 }
762 if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
763 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
764 vhcr->in_modifier, vhcr->op_modifier,
765 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
766 if (!err) {
767 slave_node_guid = mlx4_get_slave_node_guid(dev, slave);
768 memcpy(outsmp->data + 12, &slave_node_guid, 8);
769 }
770 return err;
771 }
772 }
773 }
774 if (slave != mlx4_master_func_num(dev) &&
775 ((smp->mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) ||
776 (smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
777 smp->method == IB_MGMT_METHOD_SET))) {
778 mlx4_err(dev, "slave %d is trying to execute a Subnet MGMT MAD, "
779 "class 0x%x, method 0x%x for attr 0x%x. Rejecting\n",
780 slave, smp->method, smp->mgmt_class,
781 be16_to_cpu(smp->attr_id));
782 return -EPERM;
783 }
784 /*default:*/
785 return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
786 vhcr->in_modifier, vhcr->op_modifier,
787 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
788 }
789
790 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
791 struct mlx4_vhcr *vhcr,
792 struct mlx4_cmd_mailbox *inbox,
793 struct mlx4_cmd_mailbox *outbox,
794 struct mlx4_cmd_info *cmd)
795 {
796 u64 in_param;
797 u64 out_param;
798 int err;
799
800 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
801 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
802 if (cmd->encode_slave_id) {
803 in_param &= 0xffffffffffffff00ll;
804 in_param |= slave;
805 }
806
807 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
808 vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
809 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
810
811 if (cmd->out_is_imm)
812 vhcr->out_param = out_param;
813
814 return err;
815 }
816
817 static struct mlx4_cmd_info cmd_info[] = {
818 {
819 .opcode = MLX4_CMD_QUERY_FW,
820 .has_inbox = false,
821 .has_outbox = true,
822 .out_is_imm = false,
823 .encode_slave_id = false,
824 .verify = NULL,
825 .wrapper = mlx4_QUERY_FW_wrapper
826 },
827 {
828 .opcode = MLX4_CMD_QUERY_HCA,
829 .has_inbox = false,
830 .has_outbox = true,
831 .out_is_imm = false,
832 .encode_slave_id = false,
833 .verify = NULL,
834 .wrapper = NULL
835 },
836 {
837 .opcode = MLX4_CMD_QUERY_DEV_CAP,
838 .has_inbox = false,
839 .has_outbox = true,
840 .out_is_imm = false,
841 .encode_slave_id = false,
842 .verify = NULL,
843 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
844 },
845 {
846 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
847 .has_inbox = false,
848 .has_outbox = true,
849 .out_is_imm = false,
850 .encode_slave_id = false,
851 .verify = NULL,
852 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
853 },
854 {
855 .opcode = MLX4_CMD_QUERY_ADAPTER,
856 .has_inbox = false,
857 .has_outbox = true,
858 .out_is_imm = false,
859 .encode_slave_id = false,
860 .verify = NULL,
861 .wrapper = NULL
862 },
863 {
864 .opcode = MLX4_CMD_INIT_PORT,
865 .has_inbox = false,
866 .has_outbox = false,
867 .out_is_imm = false,
868 .encode_slave_id = false,
869 .verify = NULL,
870 .wrapper = mlx4_INIT_PORT_wrapper
871 },
872 {
873 .opcode = MLX4_CMD_CLOSE_PORT,
874 .has_inbox = false,
875 .has_outbox = false,
876 .out_is_imm = false,
877 .encode_slave_id = false,
878 .verify = NULL,
879 .wrapper = mlx4_CLOSE_PORT_wrapper
880 },
881 {
882 .opcode = MLX4_CMD_QUERY_PORT,
883 .has_inbox = false,
884 .has_outbox = true,
885 .out_is_imm = false,
886 .encode_slave_id = false,
887 .verify = NULL,
888 .wrapper = mlx4_QUERY_PORT_wrapper
889 },
890 {
891 .opcode = MLX4_CMD_SET_PORT,
892 .has_inbox = true,
893 .has_outbox = false,
894 .out_is_imm = false,
895 .encode_slave_id = false,
896 .verify = NULL,
897 .wrapper = mlx4_SET_PORT_wrapper
898 },
899 {
900 .opcode = MLX4_CMD_MAP_EQ,
901 .has_inbox = false,
902 .has_outbox = false,
903 .out_is_imm = false,
904 .encode_slave_id = false,
905 .verify = NULL,
906 .wrapper = mlx4_MAP_EQ_wrapper
907 },
908 {
909 .opcode = MLX4_CMD_SW2HW_EQ,
910 .has_inbox = true,
911 .has_outbox = false,
912 .out_is_imm = false,
913 .encode_slave_id = true,
914 .verify = NULL,
915 .wrapper = mlx4_SW2HW_EQ_wrapper
916 },
917 {
918 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
919 .has_inbox = false,
920 .has_outbox = false,
921 .out_is_imm = false,
922 .encode_slave_id = false,
923 .verify = NULL,
924 .wrapper = NULL
925 },
926 {
927 .opcode = MLX4_CMD_NOP,
928 .has_inbox = false,
929 .has_outbox = false,
930 .out_is_imm = false,
931 .encode_slave_id = false,
932 .verify = NULL,
933 .wrapper = NULL
934 },
935 {
936 .opcode = MLX4_CMD_ALLOC_RES,
937 .has_inbox = false,
938 .has_outbox = false,
939 .out_is_imm = true,
940 .encode_slave_id = false,
941 .verify = NULL,
942 .wrapper = mlx4_ALLOC_RES_wrapper
943 },
944 {
945 .opcode = MLX4_CMD_FREE_RES,
946 .has_inbox = false,
947 .has_outbox = false,
948 .out_is_imm = false,
949 .encode_slave_id = false,
950 .verify = NULL,
951 .wrapper = mlx4_FREE_RES_wrapper
952 },
953 {
954 .opcode = MLX4_CMD_SW2HW_MPT,
955 .has_inbox = true,
956 .has_outbox = false,
957 .out_is_imm = false,
958 .encode_slave_id = true,
959 .verify = NULL,
960 .wrapper = mlx4_SW2HW_MPT_wrapper
961 },
962 {
963 .opcode = MLX4_CMD_QUERY_MPT,
964 .has_inbox = false,
965 .has_outbox = true,
966 .out_is_imm = false,
967 .encode_slave_id = false,
968 .verify = NULL,
969 .wrapper = mlx4_QUERY_MPT_wrapper
970 },
971 {
972 .opcode = MLX4_CMD_HW2SW_MPT,
973 .has_inbox = false,
974 .has_outbox = false,
975 .out_is_imm = false,
976 .encode_slave_id = false,
977 .verify = NULL,
978 .wrapper = mlx4_HW2SW_MPT_wrapper
979 },
980 {
981 .opcode = MLX4_CMD_READ_MTT,
982 .has_inbox = false,
983 .has_outbox = true,
984 .out_is_imm = false,
985 .encode_slave_id = false,
986 .verify = NULL,
987 .wrapper = NULL
988 },
989 {
990 .opcode = MLX4_CMD_WRITE_MTT,
991 .has_inbox = true,
992 .has_outbox = false,
993 .out_is_imm = false,
994 .encode_slave_id = false,
995 .verify = NULL,
996 .wrapper = mlx4_WRITE_MTT_wrapper
997 },
998 {
999 .opcode = MLX4_CMD_SYNC_TPT,
1000 .has_inbox = true,
1001 .has_outbox = false,
1002 .out_is_imm = false,
1003 .encode_slave_id = false,
1004 .verify = NULL,
1005 .wrapper = NULL
1006 },
1007 {
1008 .opcode = MLX4_CMD_HW2SW_EQ,
1009 .has_inbox = false,
1010 .has_outbox = true,
1011 .out_is_imm = false,
1012 .encode_slave_id = true,
1013 .verify = NULL,
1014 .wrapper = mlx4_HW2SW_EQ_wrapper
1015 },
1016 {
1017 .opcode = MLX4_CMD_QUERY_EQ,
1018 .has_inbox = false,
1019 .has_outbox = true,
1020 .out_is_imm = false,
1021 .encode_slave_id = true,
1022 .verify = NULL,
1023 .wrapper = mlx4_QUERY_EQ_wrapper
1024 },
1025 {
1026 .opcode = MLX4_CMD_SW2HW_CQ,
1027 .has_inbox = true,
1028 .has_outbox = false,
1029 .out_is_imm = false,
1030 .encode_slave_id = true,
1031 .verify = NULL,
1032 .wrapper = mlx4_SW2HW_CQ_wrapper
1033 },
1034 {
1035 .opcode = MLX4_CMD_HW2SW_CQ,
1036 .has_inbox = false,
1037 .has_outbox = false,
1038 .out_is_imm = false,
1039 .encode_slave_id = false,
1040 .verify = NULL,
1041 .wrapper = mlx4_HW2SW_CQ_wrapper
1042 },
1043 {
1044 .opcode = MLX4_CMD_QUERY_CQ,
1045 .has_inbox = false,
1046 .has_outbox = true,
1047 .out_is_imm = false,
1048 .encode_slave_id = false,
1049 .verify = NULL,
1050 .wrapper = mlx4_QUERY_CQ_wrapper
1051 },
1052 {
1053 .opcode = MLX4_CMD_MODIFY_CQ,
1054 .has_inbox = true,
1055 .has_outbox = false,
1056 .out_is_imm = true,
1057 .encode_slave_id = false,
1058 .verify = NULL,
1059 .wrapper = mlx4_MODIFY_CQ_wrapper
1060 },
1061 {
1062 .opcode = MLX4_CMD_SW2HW_SRQ,
1063 .has_inbox = true,
1064 .has_outbox = false,
1065 .out_is_imm = false,
1066 .encode_slave_id = true,
1067 .verify = NULL,
1068 .wrapper = mlx4_SW2HW_SRQ_wrapper
1069 },
1070 {
1071 .opcode = MLX4_CMD_HW2SW_SRQ,
1072 .has_inbox = false,
1073 .has_outbox = false,
1074 .out_is_imm = false,
1075 .encode_slave_id = false,
1076 .verify = NULL,
1077 .wrapper = mlx4_HW2SW_SRQ_wrapper
1078 },
1079 {
1080 .opcode = MLX4_CMD_QUERY_SRQ,
1081 .has_inbox = false,
1082 .has_outbox = true,
1083 .out_is_imm = false,
1084 .encode_slave_id = false,
1085 .verify = NULL,
1086 .wrapper = mlx4_QUERY_SRQ_wrapper
1087 },
1088 {
1089 .opcode = MLX4_CMD_ARM_SRQ,
1090 .has_inbox = false,
1091 .has_outbox = false,
1092 .out_is_imm = false,
1093 .encode_slave_id = false,
1094 .verify = NULL,
1095 .wrapper = mlx4_ARM_SRQ_wrapper
1096 },
1097 {
1098 .opcode = MLX4_CMD_RST2INIT_QP,
1099 .has_inbox = true,
1100 .has_outbox = false,
1101 .out_is_imm = false,
1102 .encode_slave_id = true,
1103 .verify = NULL,
1104 .wrapper = mlx4_RST2INIT_QP_wrapper
1105 },
1106 {
1107 .opcode = MLX4_CMD_INIT2INIT_QP,
1108 .has_inbox = true,
1109 .has_outbox = false,
1110 .out_is_imm = false,
1111 .encode_slave_id = false,
1112 .verify = NULL,
1113 .wrapper = mlx4_INIT2INIT_QP_wrapper
1114 },
1115 {
1116 .opcode = MLX4_CMD_INIT2RTR_QP,
1117 .has_inbox = true,
1118 .has_outbox = false,
1119 .out_is_imm = false,
1120 .encode_slave_id = false,
1121 .verify = NULL,
1122 .wrapper = mlx4_INIT2RTR_QP_wrapper
1123 },
1124 {
1125 .opcode = MLX4_CMD_RTR2RTS_QP,
1126 .has_inbox = true,
1127 .has_outbox = false,
1128 .out_is_imm = false,
1129 .encode_slave_id = false,
1130 .verify = NULL,
1131 .wrapper = mlx4_RTR2RTS_QP_wrapper
1132 },
1133 {
1134 .opcode = MLX4_CMD_RTS2RTS_QP,
1135 .has_inbox = true,
1136 .has_outbox = false,
1137 .out_is_imm = false,
1138 .encode_slave_id = false,
1139 .verify = NULL,
1140 .wrapper = mlx4_RTS2RTS_QP_wrapper
1141 },
1142 {
1143 .opcode = MLX4_CMD_SQERR2RTS_QP,
1144 .has_inbox = true,
1145 .has_outbox = false,
1146 .out_is_imm = false,
1147 .encode_slave_id = false,
1148 .verify = NULL,
1149 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1150 },
1151 {
1152 .opcode = MLX4_CMD_2ERR_QP,
1153 .has_inbox = false,
1154 .has_outbox = false,
1155 .out_is_imm = false,
1156 .encode_slave_id = false,
1157 .verify = NULL,
1158 .wrapper = mlx4_GEN_QP_wrapper
1159 },
1160 {
1161 .opcode = MLX4_CMD_RTS2SQD_QP,
1162 .has_inbox = false,
1163 .has_outbox = false,
1164 .out_is_imm = false,
1165 .encode_slave_id = false,
1166 .verify = NULL,
1167 .wrapper = mlx4_GEN_QP_wrapper
1168 },
1169 {
1170 .opcode = MLX4_CMD_SQD2SQD_QP,
1171 .has_inbox = true,
1172 .has_outbox = false,
1173 .out_is_imm = false,
1174 .encode_slave_id = false,
1175 .verify = NULL,
1176 .wrapper = mlx4_SQD2SQD_QP_wrapper
1177 },
1178 {
1179 .opcode = MLX4_CMD_SQD2RTS_QP,
1180 .has_inbox = true,
1181 .has_outbox = false,
1182 .out_is_imm = false,
1183 .encode_slave_id = false,
1184 .verify = NULL,
1185 .wrapper = mlx4_SQD2RTS_QP_wrapper
1186 },
1187 {
1188 .opcode = MLX4_CMD_2RST_QP,
1189 .has_inbox = false,
1190 .has_outbox = false,
1191 .out_is_imm = false,
1192 .encode_slave_id = false,
1193 .verify = NULL,
1194 .wrapper = mlx4_2RST_QP_wrapper
1195 },
1196 {
1197 .opcode = MLX4_CMD_QUERY_QP,
1198 .has_inbox = false,
1199 .has_outbox = true,
1200 .out_is_imm = false,
1201 .encode_slave_id = false,
1202 .verify = NULL,
1203 .wrapper = mlx4_GEN_QP_wrapper
1204 },
1205 {
1206 .opcode = MLX4_CMD_SUSPEND_QP,
1207 .has_inbox = false,
1208 .has_outbox = false,
1209 .out_is_imm = false,
1210 .encode_slave_id = false,
1211 .verify = NULL,
1212 .wrapper = mlx4_GEN_QP_wrapper
1213 },
1214 {
1215 .opcode = MLX4_CMD_UNSUSPEND_QP,
1216 .has_inbox = false,
1217 .has_outbox = false,
1218 .out_is_imm = false,
1219 .encode_slave_id = false,
1220 .verify = NULL,
1221 .wrapper = mlx4_GEN_QP_wrapper
1222 },
1223 {
1224 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1225 .has_inbox = false,
1226 .has_outbox = false,
1227 .out_is_imm = false,
1228 .encode_slave_id = false,
1229 .verify = NULL, /* XXX verify: only demux can do this */
1230 .wrapper = NULL
1231 },
1232 {
1233 .opcode = MLX4_CMD_MAD_IFC,
1234 .has_inbox = true,
1235 .has_outbox = true,
1236 .out_is_imm = false,
1237 .encode_slave_id = false,
1238 .verify = NULL,
1239 .wrapper = mlx4_MAD_IFC_wrapper
1240 },
1241 {
1242 .opcode = MLX4_CMD_QUERY_IF_STAT,
1243 .has_inbox = false,
1244 .has_outbox = true,
1245 .out_is_imm = false,
1246 .encode_slave_id = false,
1247 .verify = NULL,
1248 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1249 },
1250 /* Native multicast commands are not available for guests */
1251 {
1252 .opcode = MLX4_CMD_QP_ATTACH,
1253 .has_inbox = true,
1254 .has_outbox = false,
1255 .out_is_imm = false,
1256 .encode_slave_id = false,
1257 .verify = NULL,
1258 .wrapper = mlx4_QP_ATTACH_wrapper
1259 },
1260 {
1261 .opcode = MLX4_CMD_PROMISC,
1262 .has_inbox = false,
1263 .has_outbox = false,
1264 .out_is_imm = false,
1265 .encode_slave_id = false,
1266 .verify = NULL,
1267 .wrapper = mlx4_PROMISC_wrapper
1268 },
1269 /* Ethernet specific commands */
1270 {
1271 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1272 .has_inbox = true,
1273 .has_outbox = false,
1274 .out_is_imm = false,
1275 .encode_slave_id = false,
1276 .verify = NULL,
1277 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1278 },
1279 {
1280 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1281 .has_inbox = false,
1282 .has_outbox = false,
1283 .out_is_imm = false,
1284 .encode_slave_id = false,
1285 .verify = NULL,
1286 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1287 },
1288 {
1289 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1290 .has_inbox = false,
1291 .has_outbox = true,
1292 .out_is_imm = false,
1293 .encode_slave_id = false,
1294 .verify = NULL,
1295 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1296 },
1297 {
1298 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1299 .has_inbox = false,
1300 .has_outbox = false,
1301 .out_is_imm = false,
1302 .encode_slave_id = false,
1303 .verify = NULL,
1304 .wrapper = NULL
1305 },
1306 /* flow steering commands */
1307 {
1308 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1309 .has_inbox = true,
1310 .has_outbox = false,
1311 .out_is_imm = true,
1312 .encode_slave_id = false,
1313 .verify = NULL,
1314 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1315 },
1316 {
1317 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1318 .has_inbox = false,
1319 .has_outbox = false,
1320 .out_is_imm = false,
1321 .encode_slave_id = false,
1322 .verify = NULL,
1323 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1324 },
1325 };
1326
1327 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1328 struct mlx4_vhcr_cmd *in_vhcr)
1329 {
1330 struct mlx4_priv *priv = mlx4_priv(dev);
1331 struct mlx4_cmd_info *cmd = NULL;
1332 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1333 struct mlx4_vhcr *vhcr;
1334 struct mlx4_cmd_mailbox *inbox = NULL;
1335 struct mlx4_cmd_mailbox *outbox = NULL;
1336 u64 in_param;
1337 u64 out_param;
1338 int ret = 0;
1339 int i;
1340 int err = 0;
1341
1342 /* Create sw representation of Virtual HCR */
1343 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1344 if (!vhcr)
1345 return -ENOMEM;
1346
1347 /* DMA in the vHCR */
1348 if (!in_vhcr) {
1349 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1350 priv->mfunc.master.slave_state[slave].vhcr_dma,
1351 ALIGN(sizeof(struct mlx4_vhcr_cmd),
1352 MLX4_ACCESS_MEM_ALIGN), 1);
1353 if (ret) {
1354 mlx4_err(dev, "%s:Failed reading vhcr"
1355 "ret: 0x%x\n", __func__, ret);
1356 kfree(vhcr);
1357 return ret;
1358 }
1359 }
1360
1361 /* Fill SW VHCR fields */
1362 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1363 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1364 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1365 vhcr->token = be16_to_cpu(vhcr_cmd->token);
1366 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1367 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1368 vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1369
1370 /* Lookup command */
1371 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1372 if (vhcr->op == cmd_info[i].opcode) {
1373 cmd = &cmd_info[i];
1374 break;
1375 }
1376 }
1377 if (!cmd) {
1378 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1379 vhcr->op, slave);
1380 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1381 goto out_status;
1382 }
1383
1384 /* Read inbox */
1385 if (cmd->has_inbox) {
1386 vhcr->in_param &= INBOX_MASK;
1387 inbox = mlx4_alloc_cmd_mailbox(dev);
1388 if (IS_ERR(inbox)) {
1389 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1390 inbox = NULL;
1391 goto out_status;
1392 }
1393
1394 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1395 vhcr->in_param,
1396 MLX4_MAILBOX_SIZE, 1)) {
1397 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1398 __func__, cmd->opcode);
1399 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1400 goto out_status;
1401 }
1402 }
1403
1404 /* Apply permission and bound checks if applicable */
1405 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1406 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection "
1407 "checks for resource_id:%d\n", vhcr->op, slave,
1408 vhcr->in_modifier);
1409 vhcr_cmd->status = CMD_STAT_BAD_OP;
1410 goto out_status;
1411 }
1412
1413 /* Allocate outbox */
1414 if (cmd->has_outbox) {
1415 outbox = mlx4_alloc_cmd_mailbox(dev);
1416 if (IS_ERR(outbox)) {
1417 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1418 outbox = NULL;
1419 goto out_status;
1420 }
1421 }
1422
1423 /* Execute the command! */
1424 if (cmd->wrapper) {
1425 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1426 cmd);
1427 if (cmd->out_is_imm)
1428 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1429 } else {
1430 in_param = cmd->has_inbox ? (u64) inbox->dma :
1431 vhcr->in_param;
1432 out_param = cmd->has_outbox ? (u64) outbox->dma :
1433 vhcr->out_param;
1434 err = __mlx4_cmd(dev, in_param, &out_param,
1435 cmd->out_is_imm, vhcr->in_modifier,
1436 vhcr->op_modifier, vhcr->op,
1437 MLX4_CMD_TIME_CLASS_A,
1438 MLX4_CMD_NATIVE);
1439
1440 if (cmd->out_is_imm) {
1441 vhcr->out_param = out_param;
1442 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1443 }
1444 }
1445
1446 if (err) {
1447 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with"
1448 " error:%d, status %d\n",
1449 vhcr->op, slave, vhcr->errno, err);
1450 vhcr_cmd->status = mlx4_errno_to_status(err);
1451 goto out_status;
1452 }
1453
1454
1455 /* Write outbox if command completed successfully */
1456 if (cmd->has_outbox && !vhcr_cmd->status) {
1457 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1458 vhcr->out_param,
1459 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1460 if (ret) {
1461 /* If we failed to write back the outbox after the
1462 *command was successfully executed, we must fail this
1463 * slave, as it is now in undefined state */
1464 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1465 goto out;
1466 }
1467 }
1468
1469 out_status:
1470 /* DMA back vhcr result */
1471 if (!in_vhcr) {
1472 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1473 priv->mfunc.master.slave_state[slave].vhcr_dma,
1474 ALIGN(sizeof(struct mlx4_vhcr),
1475 MLX4_ACCESS_MEM_ALIGN),
1476 MLX4_CMD_WRAPPED);
1477 if (ret)
1478 mlx4_err(dev, "%s:Failed writing vhcr result\n",
1479 __func__);
1480 else if (vhcr->e_bit &&
1481 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1482 mlx4_warn(dev, "Failed to generate command completion "
1483 "eqe for slave %d\n", slave);
1484 }
1485
1486 out:
1487 kfree(vhcr);
1488 mlx4_free_cmd_mailbox(dev, inbox);
1489 mlx4_free_cmd_mailbox(dev, outbox);
1490 return ret;
1491 }
1492
1493 static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1494 {
1495 int port, err;
1496 struct mlx4_vport_state *vp_admin;
1497 struct mlx4_vport_oper_state *vp_oper;
1498
1499 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1500 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1501 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1502 vp_oper->state = *vp_admin;
1503 if (MLX4_VGT != vp_admin->default_vlan) {
1504 err = __mlx4_register_vlan(&priv->dev, port,
1505 vp_admin->default_vlan, &(vp_oper->vlan_idx));
1506 if (err) {
1507 vp_oper->vlan_idx = NO_INDX;
1508 mlx4_warn((&priv->dev),
1509 "No vlan resorces slave %d, port %d\n",
1510 slave, port);
1511 return err;
1512 }
1513 mlx4_dbg((&(priv->dev)), "alloc vlan %d idx %d slave %d port %d\n",
1514 (int)(vp_oper->state.default_vlan),
1515 vp_oper->vlan_idx, slave, port);
1516 }
1517 if (vp_admin->spoofchk) {
1518 vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1519 port,
1520 vp_admin->mac);
1521 if (0 > vp_oper->mac_idx) {
1522 err = vp_oper->mac_idx;
1523 vp_oper->mac_idx = NO_INDX;
1524 mlx4_warn((&priv->dev),
1525 "No mac resorces slave %d, port %d\n",
1526 slave, port);
1527 return err;
1528 }
1529 mlx4_dbg((&(priv->dev)), "alloc mac %llx idx %d slave %d port %d\n",
1530 vp_oper->state.mac, vp_oper->mac_idx, slave, port);
1531 }
1532 }
1533 return 0;
1534 }
1535
1536 static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
1537 {
1538 int port;
1539 struct mlx4_vport_oper_state *vp_oper;
1540
1541 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1542 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1543 if (NO_INDX != vp_oper->vlan_idx) {
1544 __mlx4_unregister_vlan(&priv->dev,
1545 port, vp_oper->vlan_idx);
1546 vp_oper->vlan_idx = NO_INDX;
1547 }
1548 if (NO_INDX != vp_oper->mac_idx) {
1549 __mlx4_unregister_mac(&priv->dev, port, vp_oper->mac_idx);
1550 vp_oper->mac_idx = NO_INDX;
1551 }
1552 }
1553 return;
1554 }
1555
1556 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1557 u16 param, u8 toggle)
1558 {
1559 struct mlx4_priv *priv = mlx4_priv(dev);
1560 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1561 u32 reply;
1562 u8 is_going_down = 0;
1563 int i;
1564 unsigned long flags;
1565
1566 slave_state[slave].comm_toggle ^= 1;
1567 reply = (u32) slave_state[slave].comm_toggle << 31;
1568 if (toggle != slave_state[slave].comm_toggle) {
1569 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER"
1570 "STATE COMPROMISIED ***\n", toggle, slave);
1571 goto reset_slave;
1572 }
1573 if (cmd == MLX4_COMM_CMD_RESET) {
1574 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1575 slave_state[slave].active = false;
1576 mlx4_master_deactivate_admin_state(priv, slave);
1577 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1578 slave_state[slave].event_eq[i].eqn = -1;
1579 slave_state[slave].event_eq[i].token = 0;
1580 }
1581 /*check if we are in the middle of FLR process,
1582 if so return "retry" status to the slave*/
1583 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
1584 goto inform_slave_state;
1585
1586 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
1587
1588 /* write the version in the event field */
1589 reply |= mlx4_comm_get_version();
1590
1591 goto reset_slave;
1592 }
1593 /*command from slave in the middle of FLR*/
1594 if (cmd != MLX4_COMM_CMD_RESET &&
1595 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1596 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) "
1597 "in the middle of FLR\n", slave, cmd);
1598 return;
1599 }
1600
1601 switch (cmd) {
1602 case MLX4_COMM_CMD_VHCR0:
1603 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1604 goto reset_slave;
1605 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1606 priv->mfunc.master.slave_state[slave].cookie = 0;
1607 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1608 break;
1609 case MLX4_COMM_CMD_VHCR1:
1610 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1611 goto reset_slave;
1612 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1613 break;
1614 case MLX4_COMM_CMD_VHCR2:
1615 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1616 goto reset_slave;
1617 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1618 break;
1619 case MLX4_COMM_CMD_VHCR_EN:
1620 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
1621 goto reset_slave;
1622 slave_state[slave].vhcr_dma |= param;
1623 if (mlx4_master_activate_admin_state(priv, slave))
1624 goto reset_slave;
1625 slave_state[slave].active = true;
1626 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
1627 break;
1628 case MLX4_COMM_CMD_VHCR_POST:
1629 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
1630 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST))
1631 goto reset_slave;
1632
1633 mutex_lock(&priv->cmd.slave_cmd_mutex);
1634 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1635 mlx4_err(dev, "Failed processing vhcr for slave:%d,"
1636 " resetting slave.\n", slave);
1637 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1638 goto reset_slave;
1639 }
1640 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1641 break;
1642 default:
1643 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
1644 goto reset_slave;
1645 }
1646 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1647 if (!slave_state[slave].is_slave_going_down)
1648 slave_state[slave].last_cmd = cmd;
1649 else
1650 is_going_down = 1;
1651 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1652 if (is_going_down) {
1653 mlx4_warn(dev, "Slave is going down aborting command(%d)"
1654 " executing from slave:%d\n",
1655 cmd, slave);
1656 return;
1657 }
1658 __raw_writel((__force u32) cpu_to_be32(reply),
1659 &priv->mfunc.comm[slave].slave_read);
1660 mmiowb();
1661
1662 return;
1663
1664 reset_slave:
1665 /* cleanup any slave resources */
1666 mlx4_delete_all_resources_for_slave(dev, slave);
1667 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1668 if (!slave_state[slave].is_slave_going_down)
1669 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
1670 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1671 /*with slave in the middle of flr, no need to clean resources again.*/
1672 inform_slave_state:
1673 memset(&slave_state[slave].event_eq, 0,
1674 sizeof(struct mlx4_slave_event_eq_info));
1675 __raw_writel((__force u32) cpu_to_be32(reply),
1676 &priv->mfunc.comm[slave].slave_read);
1677 wmb();
1678 }
1679
1680 /* master command processing */
1681 void mlx4_master_comm_channel(struct work_struct *work)
1682 {
1683 struct mlx4_mfunc_master_ctx *master =
1684 container_of(work,
1685 struct mlx4_mfunc_master_ctx,
1686 comm_work);
1687 struct mlx4_mfunc *mfunc =
1688 container_of(master, struct mlx4_mfunc, master);
1689 struct mlx4_priv *priv =
1690 container_of(mfunc, struct mlx4_priv, mfunc);
1691 struct mlx4_dev *dev = &priv->dev;
1692 __be32 *bit_vec;
1693 u32 comm_cmd;
1694 u32 vec;
1695 int i, j, slave;
1696 int toggle;
1697 int served = 0;
1698 int reported = 0;
1699 u32 slt;
1700
1701 bit_vec = master->comm_arm_bit_vector;
1702 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
1703 vec = be32_to_cpu(bit_vec[i]);
1704 for (j = 0; j < 32; j++) {
1705 if (!(vec & (1 << j)))
1706 continue;
1707 ++reported;
1708 slave = (i * 32) + j;
1709 comm_cmd = swab32(readl(
1710 &mfunc->comm[slave].slave_write));
1711 slt = swab32(readl(&mfunc->comm[slave].slave_read))
1712 >> 31;
1713 toggle = comm_cmd >> 31;
1714 if (toggle != slt) {
1715 if (master->slave_state[slave].comm_toggle
1716 != slt) {
1717 printk(KERN_INFO "slave %d out of sync."
1718 " read toggle %d, state toggle %d. "
1719 "Resynching.\n", slave, slt,
1720 master->slave_state[slave].comm_toggle);
1721 master->slave_state[slave].comm_toggle =
1722 slt;
1723 }
1724 mlx4_master_do_cmd(dev, slave,
1725 comm_cmd >> 16 & 0xff,
1726 comm_cmd & 0xffff, toggle);
1727 ++served;
1728 }
1729 }
1730 }
1731
1732 if (reported && reported != served)
1733 mlx4_warn(dev, "Got command event with bitmask from %d slaves"
1734 " but %d were served\n",
1735 reported, served);
1736
1737 if (mlx4_ARM_COMM_CHANNEL(dev))
1738 mlx4_warn(dev, "Failed to arm comm channel events\n");
1739 }
1740
1741 static int sync_toggles(struct mlx4_dev *dev)
1742 {
1743 struct mlx4_priv *priv = mlx4_priv(dev);
1744 int wr_toggle;
1745 int rd_toggle;
1746 unsigned long end;
1747
1748 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
1749 end = jiffies + msecs_to_jiffies(5000);
1750
1751 while (time_before(jiffies, end)) {
1752 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
1753 if (rd_toggle == wr_toggle) {
1754 priv->cmd.comm_toggle = rd_toggle;
1755 return 0;
1756 }
1757
1758 cond_resched();
1759 }
1760
1761 /*
1762 * we could reach here if for example the previous VM using this
1763 * function misbehaved and left the channel with unsynced state. We
1764 * should fix this here and give this VM a chance to use a properly
1765 * synced channel
1766 */
1767 mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
1768 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
1769 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
1770 priv->cmd.comm_toggle = 0;
1771
1772 return 0;
1773 }
1774
1775 int mlx4_multi_func_init(struct mlx4_dev *dev)
1776 {
1777 struct mlx4_priv *priv = mlx4_priv(dev);
1778 struct mlx4_slave_state *s_state;
1779 int i, j, err, port;
1780
1781 if (mlx4_is_master(dev))
1782 priv->mfunc.comm =
1783 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) +
1784 priv->fw.comm_base, MLX4_COMM_PAGESIZE);
1785 else
1786 priv->mfunc.comm =
1787 ioremap(pci_resource_start(dev->pdev, 2) +
1788 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
1789 if (!priv->mfunc.comm) {
1790 mlx4_err(dev, "Couldn't map communication vector.\n");
1791 goto err_vhcr;
1792 }
1793
1794 if (mlx4_is_master(dev)) {
1795 priv->mfunc.master.slave_state =
1796 kzalloc(dev->num_slaves *
1797 sizeof(struct mlx4_slave_state), GFP_KERNEL);
1798 if (!priv->mfunc.master.slave_state)
1799 goto err_comm;
1800
1801 priv->mfunc.master.vf_admin =
1802 kzalloc(dev->num_slaves *
1803 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
1804 if (!priv->mfunc.master.vf_admin)
1805 goto err_comm_admin;
1806
1807 priv->mfunc.master.vf_oper =
1808 kzalloc(dev->num_slaves *
1809 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
1810 if (!priv->mfunc.master.vf_oper)
1811 goto err_comm_oper;
1812
1813 for (i = 0; i < dev->num_slaves; ++i) {
1814 s_state = &priv->mfunc.master.slave_state[i];
1815 s_state->last_cmd = MLX4_COMM_CMD_RESET;
1816 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
1817 s_state->event_eq[j].eqn = -1;
1818 __raw_writel((__force u32) 0,
1819 &priv->mfunc.comm[i].slave_write);
1820 __raw_writel((__force u32) 0,
1821 &priv->mfunc.comm[i].slave_read);
1822 mmiowb();
1823 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1824 s_state->vlan_filter[port] =
1825 kzalloc(sizeof(struct mlx4_vlan_fltr),
1826 GFP_KERNEL);
1827 if (!s_state->vlan_filter[port]) {
1828 if (--port)
1829 kfree(s_state->vlan_filter[port]);
1830 goto err_slaves;
1831 }
1832 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
1833 priv->mfunc.master.vf_admin[i].vport[port].default_vlan = MLX4_VGT;
1834 priv->mfunc.master.vf_oper[i].vport[port].state.default_vlan = MLX4_VGT;
1835 priv->mfunc.master.vf_oper[i].vport[port].vlan_idx = NO_INDX;
1836 priv->mfunc.master.vf_oper[i].vport[port].mac_idx = NO_INDX;
1837 }
1838 spin_lock_init(&s_state->lock);
1839 }
1840
1841 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
1842 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
1843 INIT_WORK(&priv->mfunc.master.comm_work,
1844 mlx4_master_comm_channel);
1845 INIT_WORK(&priv->mfunc.master.slave_event_work,
1846 mlx4_gen_slave_eqe);
1847 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
1848 mlx4_master_handle_slave_flr);
1849 spin_lock_init(&priv->mfunc.master.slave_state_lock);
1850 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
1851 priv->mfunc.master.comm_wq =
1852 create_singlethread_workqueue("mlx4_comm");
1853 if (!priv->mfunc.master.comm_wq)
1854 goto err_slaves;
1855
1856 if (mlx4_init_resource_tracker(dev))
1857 goto err_thread;
1858
1859 err = mlx4_ARM_COMM_CHANNEL(dev);
1860 if (err) {
1861 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
1862 err);
1863 goto err_resource;
1864 }
1865
1866 } else {
1867 err = sync_toggles(dev);
1868 if (err) {
1869 mlx4_err(dev, "Couldn't sync toggles\n");
1870 goto err_comm;
1871 }
1872 }
1873 return 0;
1874
1875 err_resource:
1876 mlx4_free_resource_tracker(dev, RES_TR_FREE_ALL);
1877 err_thread:
1878 flush_workqueue(priv->mfunc.master.comm_wq);
1879 destroy_workqueue(priv->mfunc.master.comm_wq);
1880 err_slaves:
1881 while (--i) {
1882 for (port = 1; port <= MLX4_MAX_PORTS; port++)
1883 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1884 }
1885 kfree(priv->mfunc.master.vf_oper);
1886 err_comm_oper:
1887 kfree(priv->mfunc.master.vf_admin);
1888 err_comm_admin:
1889 kfree(priv->mfunc.master.slave_state);
1890 err_comm:
1891 iounmap(priv->mfunc.comm);
1892 err_vhcr:
1893 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1894 priv->mfunc.vhcr,
1895 priv->mfunc.vhcr_dma);
1896 priv->mfunc.vhcr = NULL;
1897 return -ENOMEM;
1898 }
1899
1900 int mlx4_cmd_init(struct mlx4_dev *dev)
1901 {
1902 struct mlx4_priv *priv = mlx4_priv(dev);
1903
1904 mutex_init(&priv->cmd.hcr_mutex);
1905 mutex_init(&priv->cmd.slave_cmd_mutex);
1906 sema_init(&priv->cmd.poll_sem, 1);
1907 priv->cmd.use_events = 0;
1908 priv->cmd.toggle = 1;
1909
1910 priv->cmd.hcr = NULL;
1911 priv->mfunc.vhcr = NULL;
1912
1913 if (!mlx4_is_slave(dev)) {
1914 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) +
1915 MLX4_HCR_BASE, MLX4_HCR_SIZE);
1916 if (!priv->cmd.hcr) {
1917 mlx4_err(dev, "Couldn't map command register.\n");
1918 return -ENOMEM;
1919 }
1920 }
1921
1922 if (mlx4_is_mfunc(dev)) {
1923 priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
1924 &priv->mfunc.vhcr_dma,
1925 GFP_KERNEL);
1926 if (!priv->mfunc.vhcr)
1927 goto err_hcr;
1928 }
1929
1930 priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
1931 MLX4_MAILBOX_SIZE,
1932 MLX4_MAILBOX_SIZE, 0);
1933 if (!priv->cmd.pool)
1934 goto err_vhcr;
1935
1936 return 0;
1937
1938 err_vhcr:
1939 if (mlx4_is_mfunc(dev))
1940 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1941 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
1942 priv->mfunc.vhcr = NULL;
1943
1944 err_hcr:
1945 if (!mlx4_is_slave(dev))
1946 iounmap(priv->cmd.hcr);
1947 return -ENOMEM;
1948 }
1949
1950 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
1951 {
1952 struct mlx4_priv *priv = mlx4_priv(dev);
1953 int i, port;
1954
1955 if (mlx4_is_master(dev)) {
1956 flush_workqueue(priv->mfunc.master.comm_wq);
1957 destroy_workqueue(priv->mfunc.master.comm_wq);
1958 for (i = 0; i < dev->num_slaves; i++) {
1959 for (port = 1; port <= MLX4_MAX_PORTS; port++)
1960 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1961 }
1962 kfree(priv->mfunc.master.slave_state);
1963 kfree(priv->mfunc.master.vf_admin);
1964 kfree(priv->mfunc.master.vf_oper);
1965 }
1966
1967 iounmap(priv->mfunc.comm);
1968 }
1969
1970 void mlx4_cmd_cleanup(struct mlx4_dev *dev)
1971 {
1972 struct mlx4_priv *priv = mlx4_priv(dev);
1973
1974 pci_pool_destroy(priv->cmd.pool);
1975
1976 if (!mlx4_is_slave(dev))
1977 iounmap(priv->cmd.hcr);
1978 if (mlx4_is_mfunc(dev))
1979 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1980 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
1981 priv->mfunc.vhcr = NULL;
1982 }
1983
1984 /*
1985 * Switch to using events to issue FW commands (can only be called
1986 * after event queue for command events has been initialized).
1987 */
1988 int mlx4_cmd_use_events(struct mlx4_dev *dev)
1989 {
1990 struct mlx4_priv *priv = mlx4_priv(dev);
1991 int i;
1992 int err = 0;
1993
1994 priv->cmd.context = kmalloc(priv->cmd.max_cmds *
1995 sizeof (struct mlx4_cmd_context),
1996 GFP_KERNEL);
1997 if (!priv->cmd.context)
1998 return -ENOMEM;
1999
2000 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2001 priv->cmd.context[i].token = i;
2002 priv->cmd.context[i].next = i + 1;
2003 }
2004
2005 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2006 priv->cmd.free_head = 0;
2007
2008 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2009 spin_lock_init(&priv->cmd.context_lock);
2010
2011 for (priv->cmd.token_mask = 1;
2012 priv->cmd.token_mask < priv->cmd.max_cmds;
2013 priv->cmd.token_mask <<= 1)
2014 ; /* nothing */
2015 --priv->cmd.token_mask;
2016
2017 down(&priv->cmd.poll_sem);
2018 priv->cmd.use_events = 1;
2019
2020 return err;
2021 }
2022
2023 /*
2024 * Switch back to polling (used when shutting down the device)
2025 */
2026 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2027 {
2028 struct mlx4_priv *priv = mlx4_priv(dev);
2029 int i;
2030
2031 priv->cmd.use_events = 0;
2032
2033 for (i = 0; i < priv->cmd.max_cmds; ++i)
2034 down(&priv->cmd.event_sem);
2035
2036 kfree(priv->cmd.context);
2037
2038 up(&priv->cmd.poll_sem);
2039 }
2040
2041 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2042 {
2043 struct mlx4_cmd_mailbox *mailbox;
2044
2045 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2046 if (!mailbox)
2047 return ERR_PTR(-ENOMEM);
2048
2049 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2050 &mailbox->dma);
2051 if (!mailbox->buf) {
2052 kfree(mailbox);
2053 return ERR_PTR(-ENOMEM);
2054 }
2055
2056 return mailbox;
2057 }
2058 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2059
2060 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2061 struct mlx4_cmd_mailbox *mailbox)
2062 {
2063 if (!mailbox)
2064 return;
2065
2066 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2067 kfree(mailbox);
2068 }
2069 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
2070
2071 u32 mlx4_comm_get_version(void)
2072 {
2073 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2074 }
2075
2076 static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2077 {
2078 if ((vf < 0) || (vf >= dev->num_vfs)) {
2079 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n", vf, dev->num_vfs);
2080 return -EINVAL;
2081 }
2082
2083 return vf+1;
2084 }
2085
2086 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac)
2087 {
2088 struct mlx4_priv *priv = mlx4_priv(dev);
2089 struct mlx4_vport_state *s_info;
2090 int slave;
2091
2092 if (!mlx4_is_master(dev))
2093 return -EPROTONOSUPPORT;
2094
2095 slave = mlx4_get_slave_indx(dev, vf);
2096 if (slave < 0)
2097 return -EINVAL;
2098
2099 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2100 s_info->mac = mac;
2101 mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2102 vf, port, s_info->mac);
2103 return 0;
2104 }
2105 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
2106
2107 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2108 {
2109 struct mlx4_priv *priv = mlx4_priv(dev);
2110 struct mlx4_vport_state *s_info;
2111 int slave;
2112
2113 if ((!mlx4_is_master(dev)) ||
2114 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
2115 return -EPROTONOSUPPORT;
2116
2117 if ((vlan > 4095) || (qos > 7))
2118 return -EINVAL;
2119
2120 slave = mlx4_get_slave_indx(dev, vf);
2121 if (slave < 0)
2122 return -EINVAL;
2123
2124 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2125 if ((0 == vlan) && (0 == qos))
2126 s_info->default_vlan = MLX4_VGT;
2127 else
2128 s_info->default_vlan = vlan;
2129 s_info->default_qos = qos;
2130 return 0;
2131 }
2132 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
2133
2134 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
2135 {
2136 struct mlx4_priv *priv = mlx4_priv(dev);
2137 struct mlx4_vport_state *s_info;
2138 int slave;
2139
2140 if ((!mlx4_is_master(dev)) ||
2141 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
2142 return -EPROTONOSUPPORT;
2143
2144 slave = mlx4_get_slave_indx(dev, vf);
2145 if (slave < 0)
2146 return -EINVAL;
2147
2148 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2149 s_info->spoofchk = setting;
2150
2151 return 0;
2152 }
2153 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
2154
2155 int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
2156 {
2157 struct mlx4_priv *priv = mlx4_priv(dev);
2158 struct mlx4_vport_state *s_info;
2159 int slave;
2160
2161 if (!mlx4_is_master(dev))
2162 return -EPROTONOSUPPORT;
2163
2164 slave = mlx4_get_slave_indx(dev, vf);
2165 if (slave < 0)
2166 return -EINVAL;
2167
2168 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2169 ivf->vf = vf;
2170
2171 /* need to convert it to a func */
2172 ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
2173 ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
2174 ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
2175 ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
2176 ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
2177 ivf->mac[5] = ((s_info->mac) & 0xff);
2178
2179 ivf->vlan = s_info->default_vlan;
2180 ivf->qos = s_info->default_qos;
2181 ivf->tx_rate = s_info->tx_rate;
2182 ivf->spoofchk = s_info->spoofchk;
2183
2184 return 0;
2185 }
2186 EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
Linux kernel - Deliverables
This page took 0.135438 seconds and 6 git commands to generate.