drivers/net/ethernet/mellanox/mlx4/cq.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
   5  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   6  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   7  *
   8  * This software is available to you under a choice of one of two
   9  * licenses.  You may choose to be licensed under the terms of the GNU
  10  * General Public License (GPL) Version 2, available from the file
  11  * COPYING in the main directory of this source tree, or the
  12  * OpenIB.org BSD license below:
  13  *
  14  *     Redistribution and use in source and binary forms, with or
  15  *     without modification, are permitted provided that the following
  16  *     conditions are met:
  17  *
  18  *      - Redistributions of source code must retain the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer.
  21  *
  22  *      - Redistributions in binary form must reproduce the above
  23  *        copyright notice, this list of conditions and the following
  24  *        disclaimer in the documentation and/or other materials
  25  *        provided with the distribution.
  26  *
  27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  28  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  29  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  30  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  31  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  32  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  33  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  34  * SOFTWARE.
  35  */
  36
  37 #include <linux/init.h>
  38 #include <linux/hardirq.h>
  39 #include <linux/export.h>
  40
  41 #include <linux/mlx4/cmd.h>
  42 #include <linux/mlx4/cq.h>
  43
  44 #include "mlx4.h"
  45 #include "icm.h"
  46
  47 #define MLX4_CQ_STATUS_OK               ( 0 << 28)
  48 #define MLX4_CQ_STATUS_OVERFLOW         ( 9 << 28)
  49 #define MLX4_CQ_STATUS_WRITE_FAIL       (10 << 28)
  50 #define MLX4_CQ_FLAG_CC                 ( 1 << 18)
  51 #define MLX4_CQ_FLAG_OI                 ( 1 << 17)
  52 #define MLX4_CQ_STATE_ARMED             ( 9 <<  8)
  53 #define MLX4_CQ_STATE_ARMED_SOL         ( 6 <<  8)
  54 #define MLX4_EQ_STATE_FIRED             (10 <<  8)
  55
  56 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn)
  57 {
  58         struct mlx4_cq *cq;
  59
  60         cq = radix_tree_lookup(&mlx4_priv(dev)->cq_table.tree,
  61                                cqn & (dev->caps.num_cqs - 1));
  62         if (!cq) {
  63                 mlx4_dbg(dev, "Completion event for bogus CQ %08x\n", cqn);
  64                 return;
  65         }
  66
  67         ++cq->arm_sn;
  68
  69         cq->comp(cq);
  70 }
  71
  72 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type)
  73 {
  74         struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
  75         struct mlx4_cq *cq;
  76
  77         spin_lock(&cq_table->lock);
  78
  79         cq = radix_tree_lookup(&cq_table->tree, cqn & (dev->caps.num_cqs - 1));
  80         if (cq)
  81                 atomic_inc(&cq->refcount);
  82
  83         spin_unlock(&cq_table->lock);
  84
  85         if (!cq) {
  86                 mlx4_warn(dev, "Async event for bogus CQ %08x\n", cqn);
  87                 return;
  88         }
  89
  90         cq->event(cq, event_type);
  91
  92         if (atomic_dec_and_test(&cq->refcount))
  93                 complete(&cq->free);
  94 }
  95
  96 static int mlx4_SW2HW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
  97                          int cq_num)
  98 {
  99         return mlx4_cmd(dev, mailbox->dma, cq_num, 0,
 100                         MLX4_CMD_SW2HW_CQ, MLX4_CMD_TIME_CLASS_A,
 101                         MLX4_CMD_WRAPPED);
 102 }
 103
 104 static int mlx4_MODIFY_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
 105                          int cq_num, u32 opmod)
 106 {
 107         return mlx4_cmd(dev, mailbox->dma, cq_num, opmod, MLX4_CMD_MODIFY_CQ,
 108                         MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
 109 }
 110
 111 static int mlx4_HW2SW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
 112                          int cq_num)
 113 {
 114         return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
 115                             cq_num, mailbox ? 0 : 1, MLX4_CMD_HW2SW_CQ,
 116                             MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
 117 }
 118
 119 int mlx4_cq_modify(struct mlx4_dev *dev, struct mlx4_cq *cq,
 120                    u16 count, u16 period)
 121 {
 122         struct mlx4_cmd_mailbox *mailbox;
 123         struct mlx4_cq_context *cq_context;
 124         int err;
 125
 126         mailbox = mlx4_alloc_cmd_mailbox(dev);
 127         if (IS_ERR(mailbox))
 128                 return PTR_ERR(mailbox);
 129
 130         cq_context = mailbox->buf;
 131         cq_context->cq_max_count = cpu_to_be16(count);
 132         cq_context->cq_period    = cpu_to_be16(period);
 133
 134         err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 1);
 135
 136         mlx4_free_cmd_mailbox(dev, mailbox);
 137         return err;
 138 }
 139 EXPORT_SYMBOL_GPL(mlx4_cq_modify);
 140
 141 int mlx4_cq_resize(struct mlx4_dev *dev, struct mlx4_cq *cq,
 142                    int entries, struct mlx4_mtt *mtt)
 143 {
 144         struct mlx4_cmd_mailbox *mailbox;
 145         struct mlx4_cq_context *cq_context;
 146         u64 mtt_addr;
 147         int err;
 148
 149         mailbox = mlx4_alloc_cmd_mailbox(dev);
 150         if (IS_ERR(mailbox))
 151                 return PTR_ERR(mailbox);
 152
 153         cq_context = mailbox->buf;
 154         cq_context->logsize_usrpage = cpu_to_be32(ilog2(entries) << 24);
 155         cq_context->log_page_size   = mtt->page_shift - 12;
 156         mtt_addr = mlx4_mtt_addr(dev, mtt);
 157         cq_context->mtt_base_addr_h = mtt_addr >> 32;
 158         cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
 159
 160         err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 0);
 161
 162         mlx4_free_cmd_mailbox(dev, mailbox);
 163         return err;
 164 }
 165 EXPORT_SYMBOL_GPL(mlx4_cq_resize);
 166
 167 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn)
 168 {
 169         struct mlx4_priv *priv = mlx4_priv(dev);
 170         struct mlx4_cq_table *cq_table = &priv->cq_table;
 171         int err;
 172
 173         *cqn = mlx4_bitmap_alloc(&cq_table->bitmap);
 174         if (*cqn == -1)
 175                 return -ENOMEM;
 176
 177         err = mlx4_table_get(dev, &cq_table->table, *cqn);
 178         if (err)
 179                 goto err_out;
 180
 181         err = mlx4_table_get(dev, &cq_table->cmpt_table, *cqn);
 182         if (err)
 183                 goto err_put;
 184         return 0;
 185
 186 err_put:
 187         mlx4_table_put(dev, &cq_table->table, *cqn);
 188
 189 err_out:
 190         mlx4_bitmap_free(&cq_table->bitmap, *cqn);
 191         return err;
 192 }
 193
 194 static int mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn)
 195 {
 196         u64 out_param;
 197         int err;
 198
 199         if (mlx4_is_mfunc(dev)) {
 200                 err = mlx4_cmd_imm(dev, 0, &out_param, RES_CQ,
 201                                    RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
 202                                    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
 203                 if (err)
 204                         return err;
 205                 else {
 206                         *cqn = get_param_l(&out_param);
 207                         return 0;
 208                 }
 209         }
 210         return __mlx4_cq_alloc_icm(dev, cqn);
 211 }
 212
 213 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn)
 214 {
 215         struct mlx4_priv *priv = mlx4_priv(dev);
 216         struct mlx4_cq_table *cq_table = &priv->cq_table;
 217
 218         mlx4_table_put(dev, &cq_table->cmpt_table, cqn);
 219         mlx4_table_put(dev, &cq_table->table, cqn);
 220         mlx4_bitmap_free(&cq_table->bitmap, cqn);
 221 }
 222
 223 static void mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn)
 224 {
 225         u64 in_param = 0;
 226         int err;
 227
 228         if (mlx4_is_mfunc(dev)) {
 229                 set_param_l(&in_param, cqn);
 230                 err = mlx4_cmd(dev, in_param, RES_CQ, RES_OP_RESERVE_AND_MAP,
 231                                MLX4_CMD_FREE_RES,
 232                                MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
 233                 if (err)
 234                         mlx4_warn(dev, "Failed freeing cq:%d\n", cqn);
 235         } else
 236                 __mlx4_cq_free_icm(dev, cqn);
 237 }
 238
 239 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent,
 240                   struct mlx4_mtt *mtt, struct mlx4_uar *uar, u64 db_rec,
 241                   struct mlx4_cq *cq, unsigned vector, int collapsed,
 242                   int timestamp_en)
 243 {
 244         struct mlx4_priv *priv = mlx4_priv(dev);
 245         struct mlx4_cq_table *cq_table = &priv->cq_table;
 246         struct mlx4_cmd_mailbox *mailbox;
 247         struct mlx4_cq_context *cq_context;
 248         u64 mtt_addr;
 249         int err;
 250
 251         if (vector > dev->caps.num_comp_vectors + dev->caps.comp_pool)
 252                 return -EINVAL;
 253
 254         cq->vector = vector;
 255
 256         err = mlx4_cq_alloc_icm(dev, &cq->cqn);
 257         if (err)
 258                 return err;
 259
 260         spin_lock_irq(&cq_table->lock);
 261         err = radix_tree_insert(&cq_table->tree, cq->cqn, cq);
 262         spin_unlock_irq(&cq_table->lock);
 263         if (err)
 264                 goto err_icm;
 265
 266         mailbox = mlx4_alloc_cmd_mailbox(dev);
 267         if (IS_ERR(mailbox)) {
 268                 err = PTR_ERR(mailbox);
 269                 goto err_radix;
 270         }
 271
 272         cq_context = mailbox->buf;
 273         cq_context->flags           = cpu_to_be32(!!collapsed << 18);
 274         if (timestamp_en)
 275                 cq_context->flags  |= cpu_to_be32(1 << 19);
 276
 277         cq_context->logsize_usrpage = cpu_to_be32((ilog2(nent) << 24) | uar->index);
 278         cq_context->comp_eqn        = priv->eq_table.eq[vector].eqn;
 279         cq_context->log_page_size   = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
 280
 281         mtt_addr = mlx4_mtt_addr(dev, mtt);
 282         cq_context->mtt_base_addr_h = mtt_addr >> 32;
 283         cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
 284         cq_context->db_rec_addr     = cpu_to_be64(db_rec);
 285
 286         err = mlx4_SW2HW_CQ(dev, mailbox, cq->cqn);
 287         mlx4_free_cmd_mailbox(dev, mailbox);
 288         if (err)
 289                 goto err_radix;
 290
 291         cq->cons_index = 0;
 292         cq->arm_sn     = 1;
 293         cq->uar        = uar;
 294         atomic_set(&cq->refcount, 1);
 295         init_completion(&cq->free);
 296
 297         return 0;
 298
 299 err_radix:
 300         spin_lock_irq(&cq_table->lock);
 301         radix_tree_delete(&cq_table->tree, cq->cqn);
 302         spin_unlock_irq(&cq_table->lock);
 303
 304 err_icm:
 305         mlx4_cq_free_icm(dev, cq->cqn);
 306
 307         return err;
 308 }
 309 EXPORT_SYMBOL_GPL(mlx4_cq_alloc);
 310
 311 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq)
 312 {
 313         struct mlx4_priv *priv = mlx4_priv(dev);
 314         struct mlx4_cq_table *cq_table = &priv->cq_table;
 315         int err;
 316
 317         err = mlx4_HW2SW_CQ(dev, NULL, cq->cqn);
 318         if (err)
 319                 mlx4_warn(dev, "HW2SW_CQ failed (%d) for CQN %06x\n", err, cq->cqn);
 320
 321         synchronize_irq(priv->eq_table.eq[cq->vector].irq);
 322
 323         spin_lock_irq(&cq_table->lock);
 324         radix_tree_delete(&cq_table->tree, cq->cqn);
 325         spin_unlock_irq(&cq_table->lock);
 326
 327         if (atomic_dec_and_test(&cq->refcount))
 328                 complete(&cq->free);
 329         wait_for_completion(&cq->free);
 330
 331         mlx4_cq_free_icm(dev, cq->cqn);
 332 }
 333 EXPORT_SYMBOL_GPL(mlx4_cq_free);
 334
 335 int mlx4_init_cq_table(struct mlx4_dev *dev)
 336 {
 337         struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
 338         int err;
 339
 340         spin_lock_init(&cq_table->lock);
 341         INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC);
 342         if (mlx4_is_slave(dev))
 343                 return 0;
 344
 345         err = mlx4_bitmap_init(&cq_table->bitmap, dev->caps.num_cqs,
 346                                dev->caps.num_cqs - 1, dev->caps.reserved_cqs, 0);
 347         if (err)
 348                 return err;
 349
 350         return 0;
 351 }
 352
 353 void mlx4_cleanup_cq_table(struct mlx4_dev *dev)
 354 {
 355         if (mlx4_is_slave(dev))
 356                 return;
 357         /* Nothing to do to clean up radix_tree */
 358         mlx4_bitmap_cleanup(&mlx4_priv(dev)->cq_table.bitmap);
 359 }