drivers/net/ethernet/mellanox/mlx4/cq.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
   5  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   6  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   7  *
   8  * This software is available to you under a choice of one of two
   9  * licenses.  You may choose to be licensed under the terms of the GNU
  10  * General Public License (GPL) Version 2, available from the file
  11  * COPYING in the main directory of this source tree, or the
  12  * OpenIB.org BSD license below:
  13  *
  14  *     Redistribution and use in source and binary forms, with or
  15  *     without modification, are permitted provided that the following
  16  *     conditions are met:
  17  *
  18  *      - Redistributions of source code must retain the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer.
  21  *
  22  *      - Redistributions in binary form must reproduce the above
  23  *        copyright notice, this list of conditions and the following
  24  *        disclaimer in the documentation and/or other materials
  25  *        provided with the distribution.
  26  *
  27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  28  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  29  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  30  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  31  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  32  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  33  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  34  * SOFTWARE.
  35  */
  36
  37 #include <linux/hardirq.h>
  38 #include <linux/export.h>
  39
  40 #include <linux/mlx4/cmd.h>
  41 #include <linux/mlx4/cq.h>
  42
  43 #include "mlx4.h"
  44 #include "icm.h"
  45
  46 #define MLX4_CQ_STATUS_OK               ( 0 << 28)
  47 #define MLX4_CQ_STATUS_OVERFLOW         ( 9 << 28)
  48 #define MLX4_CQ_STATUS_WRITE_FAIL       (10 << 28)
  49 #define MLX4_CQ_FLAG_CC                 ( 1 << 18)
  50 #define MLX4_CQ_FLAG_OI                 ( 1 << 17)
  51 #define MLX4_CQ_STATE_ARMED             ( 9 <<  8)
  52 #define MLX4_CQ_STATE_ARMED_SOL         ( 6 <<  8)
  53 #define MLX4_EQ_STATE_FIRED             (10 <<  8)
  54
  55 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn)
  56 {
  57         struct mlx4_cq *cq;
  58
  59         cq = radix_tree_lookup(&mlx4_priv(dev)->cq_table.tree,
  60                                cqn & (dev->caps.num_cqs - 1));
  61         if (!cq) {
  62                 mlx4_dbg(dev, "Completion event for bogus CQ %08x\n", cqn);
  63                 return;
  64         }
  65
  66         ++cq->arm_sn;
  67
  68         cq->comp(cq);
  69 }
  70
  71 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type)
  72 {
  73         struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
  74         struct mlx4_cq *cq;
  75
  76         spin_lock(&cq_table->lock);
  77
  78         cq = radix_tree_lookup(&cq_table->tree, cqn & (dev->caps.num_cqs - 1));
  79         if (cq)
  80                 atomic_inc(&cq->refcount);
  81
  82         spin_unlock(&cq_table->lock);
  83
  84         if (!cq) {
  85                 mlx4_warn(dev, "Async event for bogus CQ %08x\n", cqn);
  86                 return;
  87         }
  88
  89         cq->event(cq, event_type);
  90
  91         if (atomic_dec_and_test(&cq->refcount))
  92                 complete(&cq->free);
  93 }
  94
  95 static int mlx4_SW2HW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
  96                          int cq_num)
  97 {
  98         return mlx4_cmd(dev, mailbox->dma, cq_num, 0,
  99                         MLX4_CMD_SW2HW_CQ, MLX4_CMD_TIME_CLASS_A,
 100                         MLX4_CMD_WRAPPED);
 101 }
 102
 103 static int mlx4_MODIFY_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
 104                          int cq_num, u32 opmod)
 105 {
 106         return mlx4_cmd(dev, mailbox->dma, cq_num, opmod, MLX4_CMD_MODIFY_CQ,
 107                         MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
 108 }
 109
 110 static int mlx4_HW2SW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
 111                          int cq_num)
 112 {
 113         return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
 114                             cq_num, mailbox ? 0 : 1, MLX4_CMD_HW2SW_CQ,
 115                             MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
 116 }
 117
 118 int mlx4_cq_modify(struct mlx4_dev *dev, struct mlx4_cq *cq,
 119                    u16 count, u16 period)
 120 {
 121         struct mlx4_cmd_mailbox *mailbox;
 122         struct mlx4_cq_context *cq_context;
 123         int err;
 124
 125         mailbox = mlx4_alloc_cmd_mailbox(dev);
 126         if (IS_ERR(mailbox))
 127                 return PTR_ERR(mailbox);
 128
 129         cq_context = mailbox->buf;
 130         cq_context->cq_max_count = cpu_to_be16(count);
 131         cq_context->cq_period    = cpu_to_be16(period);
 132
 133         err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 1);
 134
 135         mlx4_free_cmd_mailbox(dev, mailbox);
 136         return err;
 137 }
 138 EXPORT_SYMBOL_GPL(mlx4_cq_modify);
 139
 140 int mlx4_cq_resize(struct mlx4_dev *dev, struct mlx4_cq *cq,
 141                    int entries, struct mlx4_mtt *mtt)
 142 {
 143         struct mlx4_cmd_mailbox *mailbox;
 144         struct mlx4_cq_context *cq_context;
 145         u64 mtt_addr;
 146         int err;
 147
 148         mailbox = mlx4_alloc_cmd_mailbox(dev);
 149         if (IS_ERR(mailbox))
 150                 return PTR_ERR(mailbox);
 151
 152         cq_context = mailbox->buf;
 153         cq_context->logsize_usrpage = cpu_to_be32(ilog2(entries) << 24);
 154         cq_context->log_page_size   = mtt->page_shift - 12;
 155         mtt_addr = mlx4_mtt_addr(dev, mtt);
 156         cq_context->mtt_base_addr_h = mtt_addr >> 32;
 157         cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
 158
 159         err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 0);
 160
 161         mlx4_free_cmd_mailbox(dev, mailbox);
 162         return err;
 163 }
 164 EXPORT_SYMBOL_GPL(mlx4_cq_resize);
 165
 166 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn)
 167 {
 168         struct mlx4_priv *priv = mlx4_priv(dev);
 169         struct mlx4_cq_table *cq_table = &priv->cq_table;
 170         int err;
 171
 172         *cqn = mlx4_bitmap_alloc(&cq_table->bitmap);
 173         if (*cqn == -1)
 174                 return -ENOMEM;
 175
 176         err = mlx4_table_get(dev, &cq_table->table, *cqn, GFP_KERNEL);
 177         if (err)
 178                 goto err_out;
 179
 180         err = mlx4_table_get(dev, &cq_table->cmpt_table, *cqn, GFP_KERNEL);
 181         if (err)
 182                 goto err_put;
 183         return 0;
 184
 185 err_put:
 186         mlx4_table_put(dev, &cq_table->table, *cqn);
 187
 188 err_out:
 189         mlx4_bitmap_free(&cq_table->bitmap, *cqn, MLX4_NO_RR);
 190         return err;
 191 }
 192
 193 static int mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn)
 194 {
 195         u64 out_param;
 196         int err;
 197
 198         if (mlx4_is_mfunc(dev)) {
 199                 err = mlx4_cmd_imm(dev, 0, &out_param, RES_CQ,
 200                                    RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
 201                                    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
 202                 if (err)
 203                         return err;
 204                 else {
 205                         *cqn = get_param_l(&out_param);
 206                         return 0;
 207                 }
 208         }
 209         return __mlx4_cq_alloc_icm(dev, cqn);
 210 }
 211
 212 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn)
 213 {
 214         struct mlx4_priv *priv = mlx4_priv(dev);
 215         struct mlx4_cq_table *cq_table = &priv->cq_table;
 216
 217         mlx4_table_put(dev, &cq_table->cmpt_table, cqn);
 218         mlx4_table_put(dev, &cq_table->table, cqn);
 219         mlx4_bitmap_free(&cq_table->bitmap, cqn, MLX4_NO_RR);
 220 }
 221
 222 static void mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn)
 223 {
 224         u64 in_param = 0;
 225         int err;
 226
 227         if (mlx4_is_mfunc(dev)) {
 228                 set_param_l(&in_param, cqn);
 229                 err = mlx4_cmd(dev, in_param, RES_CQ, RES_OP_RESERVE_AND_MAP,
 230                                MLX4_CMD_FREE_RES,
 231                                MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
 232                 if (err)
 233                         mlx4_warn(dev, "Failed freeing cq:%d\n", cqn);
 234         } else
 235                 __mlx4_cq_free_icm(dev, cqn);
 236 }
 237
 238 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent,
 239                   struct mlx4_mtt *mtt, struct mlx4_uar *uar, u64 db_rec,
 240                   struct mlx4_cq *cq, unsigned vector, int collapsed,
 241                   int timestamp_en)
 242 {
 243         struct mlx4_priv *priv = mlx4_priv(dev);
 244         struct mlx4_cq_table *cq_table = &priv->cq_table;
 245         struct mlx4_cmd_mailbox *mailbox;
 246         struct mlx4_cq_context *cq_context;
 247         u64 mtt_addr;
 248         int err;
 249
 250         if (vector > dev->caps.num_comp_vectors + dev->caps.comp_pool)
 251                 return -EINVAL;
 252
 253         cq->vector = vector;
 254
 255         err = mlx4_cq_alloc_icm(dev, &cq->cqn);
 256         if (err)
 257                 return err;
 258
 259         spin_lock_irq(&cq_table->lock);
 260         err = radix_tree_insert(&cq_table->tree, cq->cqn, cq);
 261         spin_unlock_irq(&cq_table->lock);
 262         if (err)
 263                 goto err_icm;
 264
 265         mailbox = mlx4_alloc_cmd_mailbox(dev);
 266         if (IS_ERR(mailbox)) {
 267                 err = PTR_ERR(mailbox);
 268                 goto err_radix;
 269         }
 270
 271         cq_context = mailbox->buf;
 272         cq_context->flags           = cpu_to_be32(!!collapsed << 18);
 273         if (timestamp_en)
 274                 cq_context->flags  |= cpu_to_be32(1 << 19);
 275
 276         cq_context->logsize_usrpage = cpu_to_be32((ilog2(nent) << 24) | uar->index);
 277         cq_context->comp_eqn        = priv->eq_table.eq[vector].eqn;
 278         cq_context->log_page_size   = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
 279
 280         mtt_addr = mlx4_mtt_addr(dev, mtt);
 281         cq_context->mtt_base_addr_h = mtt_addr >> 32;
 282         cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
 283         cq_context->db_rec_addr     = cpu_to_be64(db_rec);
 284
 285         err = mlx4_SW2HW_CQ(dev, mailbox, cq->cqn);
 286         mlx4_free_cmd_mailbox(dev, mailbox);
 287         if (err)
 288                 goto err_radix;
 289
 290         cq->cons_index = 0;
 291         cq->arm_sn     = 1;
 292         cq->uar        = uar;
 293         atomic_set(&cq->refcount, 1);
 294         init_completion(&cq->free);
 295
 296         cq->irq = priv->eq_table.eq[cq->vector].irq;
 297         return 0;
 298
 299 err_radix:
 300         spin_lock_irq(&cq_table->lock);
 301         radix_tree_delete(&cq_table->tree, cq->cqn);
 302         spin_unlock_irq(&cq_table->lock);
 303
 304 err_icm:
 305         mlx4_cq_free_icm(dev, cq->cqn);
 306
 307         return err;
 308 }
 309 EXPORT_SYMBOL_GPL(mlx4_cq_alloc);
 310
 311 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq)
 312 {
 313         struct mlx4_priv *priv = mlx4_priv(dev);
 314         struct mlx4_cq_table *cq_table = &priv->cq_table;
 315         int err;
 316
 317         err = mlx4_HW2SW_CQ(dev, NULL, cq->cqn);
 318         if (err)
 319                 mlx4_warn(dev, "HW2SW_CQ failed (%d) for CQN %06x\n", err, cq->cqn);
 320
 321         synchronize_irq(priv->eq_table.eq[cq->vector].irq);
 322
 323         spin_lock_irq(&cq_table->lock);
 324         radix_tree_delete(&cq_table->tree, cq->cqn);
 325         spin_unlock_irq(&cq_table->lock);
 326
 327         if (atomic_dec_and_test(&cq->refcount))
 328                 complete(&cq->free);
 329         wait_for_completion(&cq->free);
 330
 331         mlx4_cq_free_icm(dev, cq->cqn);
 332 }
 333 EXPORT_SYMBOL_GPL(mlx4_cq_free);
 334
 335 int mlx4_init_cq_table(struct mlx4_dev *dev)
 336 {
 337         struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
 338         int err;
 339
 340         spin_lock_init(&cq_table->lock);
 341         INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC);
 342         if (mlx4_is_slave(dev))
 343                 return 0;
 344
 345         err = mlx4_bitmap_init(&cq_table->bitmap, dev->caps.num_cqs,
 346                                dev->caps.num_cqs - 1, dev->caps.reserved_cqs, 0);
 347         if (err)
 348                 return err;
 349
 350         return 0;
 351 }
 352
 353 void mlx4_cleanup_cq_table(struct mlx4_dev *dev)
 354 {
 355         if (mlx4_is_slave(dev))
 356                 return;
 357         /* Nothing to do to clean up radix_tree */
 358         mlx4_bitmap_cleanup(&mlx4_priv(dev)->cq_table.bitmap);
 359 }