2 * Copyright (c) 2012 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/mlx4/device.h>
35 #include <linux/clocksource.h>
39 /* mlx4_en_read_clock - read raw cycle counter (to be used by time counter)
41 static cycle_t
mlx4_en_read_clock(const struct cyclecounter
*tc
)
43 struct mlx4_en_dev
*mdev
=
44 container_of(tc
, struct mlx4_en_dev
, cycles
);
45 struct mlx4_dev
*dev
= mdev
->dev
;
47 return mlx4_read_clock(dev
) & tc
->mask
;
50 u64
mlx4_en_get_cqe_ts(struct mlx4_cqe
*cqe
)
53 struct mlx4_ts_cqe
*ts_cqe
= (struct mlx4_ts_cqe
*)cqe
;
55 lo
= (u64
)be16_to_cpu(ts_cqe
->timestamp_lo
);
56 hi
= ((u64
)be32_to_cpu(ts_cqe
->timestamp_hi
) + !lo
) << 16;
61 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev
*mdev
,
62 struct skb_shared_hwtstamps
*hwts
,
68 read_lock_irqsave(&mdev
->clock_lock
, flags
);
69 nsec
= timecounter_cyc2time(&mdev
->clock
, timestamp
);
70 read_unlock_irqrestore(&mdev
->clock_lock
, flags
);
72 memset(hwts
, 0, sizeof(struct skb_shared_hwtstamps
));
73 hwts
->hwtstamp
= ns_to_ktime(nsec
);
77 * mlx4_en_remove_timestamp - disable PTP device
78 * @mdev: board private structure
80 * Stop the PTP support.
82 void mlx4_en_remove_timestamp(struct mlx4_en_dev
*mdev
)
84 if (mdev
->ptp_clock
) {
85 ptp_clock_unregister(mdev
->ptp_clock
);
86 mdev
->ptp_clock
= NULL
;
87 mlx4_info(mdev
, "removed PHC\n");
91 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev
*mdev
)
93 bool timeout
= time_is_before_jiffies(mdev
->last_overflow_check
+
94 mdev
->overflow_period
);
98 write_lock_irqsave(&mdev
->clock_lock
, flags
);
99 timecounter_read(&mdev
->clock
);
100 write_unlock_irqrestore(&mdev
->clock_lock
, flags
);
101 mdev
->last_overflow_check
= jiffies
;
106 * mlx4_en_phc_adjfreq - adjust the frequency of the hardware clock
107 * @ptp: ptp clock structure
108 * @delta: Desired frequency change in parts per billion
110 * Adjust the frequency of the PHC cycle counter by the indicated delta from
111 * the base frequency.
113 static int mlx4_en_phc_adjfreq(struct ptp_clock_info
*ptp
, s32 delta
)
119 struct mlx4_en_dev
*mdev
= container_of(ptp
, struct mlx4_en_dev
,
126 mult
= mdev
->nominal_c_mult
;
129 diff
= div_u64(adj
, 1000000000ULL);
131 write_lock_irqsave(&mdev
->clock_lock
, flags
);
132 timecounter_read(&mdev
->clock
);
133 mdev
->cycles
.mult
= neg_adj
? mult
- diff
: mult
+ diff
;
134 write_unlock_irqrestore(&mdev
->clock_lock
, flags
);
140 * mlx4_en_phc_adjtime - Shift the time of the hardware clock
141 * @ptp: ptp clock structure
142 * @delta: Desired change in nanoseconds
144 * Adjust the timer by resetting the timecounter structure.
146 static int mlx4_en_phc_adjtime(struct ptp_clock_info
*ptp
, s64 delta
)
148 struct mlx4_en_dev
*mdev
= container_of(ptp
, struct mlx4_en_dev
,
152 write_lock_irqsave(&mdev
->clock_lock
, flags
);
153 timecounter_adjtime(&mdev
->clock
, delta
);
154 write_unlock_irqrestore(&mdev
->clock_lock
, flags
);
160 * mlx4_en_phc_gettime - Reads the current time from the hardware clock
161 * @ptp: ptp clock structure
162 * @ts: timespec structure to hold the current time value
164 * Read the timecounter and return the correct value in ns after converting
165 * it into a struct timespec.
167 static int mlx4_en_phc_gettime(struct ptp_clock_info
*ptp
, struct timespec
*ts
)
169 struct mlx4_en_dev
*mdev
= container_of(ptp
, struct mlx4_en_dev
,
175 write_lock_irqsave(&mdev
->clock_lock
, flags
);
176 ns
= timecounter_read(&mdev
->clock
);
177 write_unlock_irqrestore(&mdev
->clock_lock
, flags
);
179 ts
->tv_sec
= div_u64_rem(ns
, NSEC_PER_SEC
, &remainder
);
180 ts
->tv_nsec
= remainder
;
186 * mlx4_en_phc_settime - Set the current time on the hardware clock
187 * @ptp: ptp clock structure
188 * @ts: timespec containing the new time for the cycle counter
190 * Reset the timecounter to use a new base value instead of the kernel
193 static int mlx4_en_phc_settime(struct ptp_clock_info
*ptp
,
194 const struct timespec
*ts
)
196 struct mlx4_en_dev
*mdev
= container_of(ptp
, struct mlx4_en_dev
,
198 u64 ns
= timespec_to_ns(ts
);
201 /* reset the timecounter */
202 write_lock_irqsave(&mdev
->clock_lock
, flags
);
203 timecounter_init(&mdev
->clock
, &mdev
->cycles
, ns
);
204 write_unlock_irqrestore(&mdev
->clock_lock
, flags
);
210 * mlx4_en_phc_enable - enable or disable an ancillary feature
211 * @ptp: ptp clock structure
212 * @request: Desired resource to enable or disable
213 * @on: Caller passes one to enable or zero to disable
215 * Enable (or disable) ancillary features of the PHC subsystem.
216 * Currently, no ancillary features are supported.
218 static int mlx4_en_phc_enable(struct ptp_clock_info __always_unused
*ptp
,
219 struct ptp_clock_request __always_unused
*request
,
220 int __always_unused on
)
225 static const struct ptp_clock_info mlx4_en_ptp_clock_info
= {
226 .owner
= THIS_MODULE
,
227 .max_adj
= 100000000,
233 .adjfreq
= mlx4_en_phc_adjfreq
,
234 .adjtime
= mlx4_en_phc_adjtime
,
235 .gettime
= mlx4_en_phc_gettime
,
236 .settime
= mlx4_en_phc_settime
,
237 .enable
= mlx4_en_phc_enable
,
240 void mlx4_en_init_timestamp(struct mlx4_en_dev
*mdev
)
242 struct mlx4_dev
*dev
= mdev
->dev
;
246 rwlock_init(&mdev
->clock_lock
);
248 memset(&mdev
->cycles
, 0, sizeof(mdev
->cycles
));
249 mdev
->cycles
.read
= mlx4_en_read_clock
;
250 mdev
->cycles
.mask
= CLOCKSOURCE_MASK(48);
251 /* Using shift to make calculation more accurate. Since current HW
252 * clock frequency is 427 MHz, and cycles are given using a 48 bits
253 * register, the biggest shift when calculating using u64, is 14
254 * (max_cycles * multiplier < 2^64)
256 mdev
->cycles
.shift
= 14;
258 clocksource_khz2mult(1000 * dev
->caps
.hca_core_clock
, mdev
->cycles
.shift
);
259 mdev
->nominal_c_mult
= mdev
->cycles
.mult
;
261 write_lock_irqsave(&mdev
->clock_lock
, flags
);
262 timecounter_init(&mdev
->clock
, &mdev
->cycles
,
263 ktime_to_ns(ktime_get_real()));
264 write_unlock_irqrestore(&mdev
->clock_lock
, flags
);
266 /* Calculate period in seconds to call the overflow watchdog - to make
267 * sure counter is checked at least once every wrap around.
269 ns
= cyclecounter_cyc2ns(&mdev
->cycles
, mdev
->cycles
.mask
, zero
, &zero
);
270 do_div(ns
, NSEC_PER_SEC
/ 2 / HZ
);
271 mdev
->overflow_period
= ns
;
273 /* Configure the PHC */
274 mdev
->ptp_clock_info
= mlx4_en_ptp_clock_info
;
275 snprintf(mdev
->ptp_clock_info
.name
, 16, "mlx4 ptp");
277 mdev
->ptp_clock
= ptp_clock_register(&mdev
->ptp_clock_info
,
279 if (IS_ERR(mdev
->ptp_clock
)) {
280 mdev
->ptp_clock
= NULL
;
281 mlx4_err(mdev
, "ptp_clock_register failed\n");
283 mlx4_info(mdev
, "registered PHC clock\n");