drivers/net/ethernet/mellanox/mlx4/en_cq.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <linux/mlx4/cq.h>
  35 #include <linux/mlx4/qp.h>
  36 #include <linux/mlx4/cmd.h>
  37
  38 #include "mlx4_en.h"
  39
  40 static void mlx4_en_cq_event(struct mlx4_cq *cq, enum mlx4_event event)
  41 {
  42         return;
  43 }
  44
  45
  46 int mlx4_en_create_cq(struct mlx4_en_priv *priv,
  47                       struct mlx4_en_cq **pcq,
  48                       int entries, int ring, enum cq_type mode,
  49                       int node)
  50 {
  51         struct mlx4_en_dev *mdev = priv->mdev;
  52         struct mlx4_en_cq *cq;
  53         int err;
  54
  55         cq = kzalloc_node(sizeof(*cq), GFP_KERNEL, node);
  56         if (!cq) {
  57                 cq = kzalloc(sizeof(*cq), GFP_KERNEL);
  58                 if (!cq) {
  59                         en_err(priv, "Failed to allocate CQ structure\n");
  60                         return -ENOMEM;
  61                 }
  62         }
  63
  64         cq->size = entries;
  65         cq->buf_size = cq->size * mdev->dev->caps.cqe_size;
  66
  67         cq->ring = ring;
  68         cq->is_tx = mode;
  69         spin_lock_init(&cq->lock);
  70
  71         /* Allocate HW buffers on provided NUMA node.
  72          * dev->numa_node is used in mtt range allocation flow.
  73          */
  74         set_dev_node(&mdev->dev->pdev->dev, node);
  75         err = mlx4_alloc_hwq_res(mdev->dev, &cq->wqres,
  76                                 cq->buf_size, 2 * PAGE_SIZE);
  77         set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node);
  78         if (err)
  79                 goto err_cq;
  80
  81         err = mlx4_en_map_buffer(&cq->wqres.buf);
  82         if (err)
  83                 goto err_res;
  84
  85         cq->buf = (struct mlx4_cqe *)cq->wqres.buf.direct.buf;
  86         *pcq = cq;
  87
  88         return 0;
  89
  90 err_res:
  91         mlx4_free_hwq_res(mdev->dev, &cq->wqres, cq->buf_size);
  92 err_cq:
  93         kfree(cq);
  94         *pcq = NULL;
  95         return err;
  96 }
  97
  98 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
  99                         int cq_idx)
 100 {
 101         struct mlx4_en_dev *mdev = priv->mdev;
 102         int err = 0;
 103         char name[25];
 104         int timestamp_en = 0;
 105         struct cpu_rmap *rmap =
 106 #ifdef CONFIG_RFS_ACCEL
 107                 priv->dev->rx_cpu_rmap;
 108 #else
 109                 NULL;
 110 #endif
 111
 112         cq->dev = mdev->pndev[priv->port];
 113         cq->mcq.set_ci_db  = cq->wqres.db.db;
 114         cq->mcq.arm_db     = cq->wqres.db.db + 1;
 115         *cq->mcq.set_ci_db = 0;
 116         *cq->mcq.arm_db    = 0;
 117         memset(cq->buf, 0, cq->buf_size);
 118
 119         if (cq->is_tx == RX) {
 120                 if (mdev->dev->caps.comp_pool) {
 121                         if (!cq->vector) {
 122                                 sprintf(name, "%s-%d", priv->dev->name,
 123                                         cq->ring);
 124                                 /* Set IRQ for specific name (per ring) */
 125                                 if (mlx4_assign_eq(mdev->dev, name, rmap,
 126                                                    &cq->vector)) {
 127                                         cq->vector = (cq->ring + 1 + priv->port)
 128                                             % mdev->dev->caps.num_comp_vectors;
 129                                         mlx4_warn(mdev, "Failed Assigning an EQ to "
 130                                                   "%s ,Falling back to legacy EQ's\n",
 131                                                   name);
 132                                 }
 133                         }
 134                 } else {
 135                         cq->vector = (cq->ring + 1 + priv->port) %
 136                                 mdev->dev->caps.num_comp_vectors;
 137                 }
 138         } else {
 139                 /* For TX we use the same irq per
 140                 ring we assigned for the RX    */
 141                 struct mlx4_en_cq *rx_cq;
 142
 143                 cq_idx = cq_idx % priv->rx_ring_num;
 144                 rx_cq = priv->rx_cq[cq_idx];
 145                 cq->vector = rx_cq->vector;
 146         }
 147
 148         if (!cq->is_tx)
 149                 cq->size = priv->rx_ring[cq->ring]->actual_size;
 150
 151         if ((cq->is_tx && priv->hwtstamp_config.tx_type) ||
 152             (!cq->is_tx && priv->hwtstamp_config.rx_filter))
 153                 timestamp_en = 1;
 154
 155         err = mlx4_cq_alloc(mdev->dev, cq->size, &cq->wqres.mtt,
 156                             &mdev->priv_uar, cq->wqres.db.dma, &cq->mcq,
 157                             cq->vector, 0, timestamp_en);
 158         if (err)
 159                 return err;
 160
 161         cq->mcq.comp  = cq->is_tx ? mlx4_en_tx_irq : mlx4_en_rx_irq;
 162         cq->mcq.event = mlx4_en_cq_event;
 163
 164         if (!cq->is_tx) {
 165                 netif_napi_add(cq->dev, &cq->napi, mlx4_en_poll_rx_cq, 64);
 166                 napi_hash_add(&cq->napi);
 167                 napi_enable(&cq->napi);
 168         }
 169
 170         return 0;
 171 }
 172
 173 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq)
 174 {
 175         struct mlx4_en_dev *mdev = priv->mdev;
 176         struct mlx4_en_cq *cq = *pcq;
 177
 178         mlx4_en_unmap_buffer(&cq->wqres.buf);
 179         mlx4_free_hwq_res(mdev->dev, &cq->wqres, cq->buf_size);
 180         if (priv->mdev->dev->caps.comp_pool && cq->vector)
 181                 mlx4_release_eq(priv->mdev->dev, cq->vector);
 182         cq->vector = 0;
 183         cq->buf_size = 0;
 184         cq->buf = NULL;
 185         kfree(cq);
 186         *pcq = NULL;
 187 }
 188
 189 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
 190 {
 191         if (!cq->is_tx) {
 192                 napi_disable(&cq->napi);
 193                 napi_hash_del(&cq->napi);
 194                 synchronize_rcu();
 195                 netif_napi_del(&cq->napi);
 196         }
 197
 198         mlx4_cq_free(priv->mdev->dev, &cq->mcq);
 199 }
 200
 201 /* Set rx cq moderation parameters */
 202 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
 203 {
 204         return mlx4_cq_modify(priv->mdev->dev, &cq->mcq,
 205                               cq->moder_cnt, cq->moder_time);
 206 }
 207
 208 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
 209 {
 210         mlx4_cq_arm(&cq->mcq, MLX4_CQ_DB_REQ_NOT, priv->mdev->uar_map,
 211                     &priv->mdev->uar_lock);
 212
 213         return 0;
 214 }
 215
 216