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net: mlx4: use new ETHTOOL_G/SSETTINGS API
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / en_ethtool.c
1 /*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #include <linux/kernel.h>
35 #include <linux/ethtool.h>
36 #include <linux/netdevice.h>
37 #include <linux/mlx4/driver.h>
38 #include <linux/mlx4/device.h>
39 #include <linux/in.h>
40 #include <net/ip.h>
41 #include <linux/bitmap.h>
42
43 #include "mlx4_en.h"
44 #include "en_port.h"
45
46 #define EN_ETHTOOL_QP_ATTACH (1ull << 63)
47 #define EN_ETHTOOL_SHORT_MASK cpu_to_be16(0xffff)
48 #define EN_ETHTOOL_WORD_MASK cpu_to_be32(0xffffffff)
49
50 static int mlx4_en_moderation_update(struct mlx4_en_priv *priv)
51 {
52 int i;
53 int err = 0;
54
55 for (i = 0; i < priv->tx_ring_num; i++) {
56 priv->tx_cq[i]->moder_cnt = priv->tx_frames;
57 priv->tx_cq[i]->moder_time = priv->tx_usecs;
58 if (priv->port_up) {
59 err = mlx4_en_set_cq_moder(priv, priv->tx_cq[i]);
60 if (err)
61 return err;
62 }
63 }
64
65 if (priv->adaptive_rx_coal)
66 return 0;
67
68 for (i = 0; i < priv->rx_ring_num; i++) {
69 priv->rx_cq[i]->moder_cnt = priv->rx_frames;
70 priv->rx_cq[i]->moder_time = priv->rx_usecs;
71 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
72 if (priv->port_up) {
73 err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]);
74 if (err)
75 return err;
76 }
77 }
78
79 return err;
80 }
81
82 static void
83 mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
84 {
85 struct mlx4_en_priv *priv = netdev_priv(dev);
86 struct mlx4_en_dev *mdev = priv->mdev;
87
88 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
89 strlcpy(drvinfo->version, DRV_VERSION " (" DRV_RELDATE ")",
90 sizeof(drvinfo->version));
91 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
92 "%d.%d.%d",
93 (u16) (mdev->dev->caps.fw_ver >> 32),
94 (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff),
95 (u16) (mdev->dev->caps.fw_ver & 0xffff));
96 strlcpy(drvinfo->bus_info, pci_name(mdev->dev->persist->pdev),
97 sizeof(drvinfo->bus_info));
98 }
99
100 static const char mlx4_en_priv_flags[][ETH_GSTRING_LEN] = {
101 "blueflame",
102 "phv-bit"
103 };
104
105 static const char main_strings[][ETH_GSTRING_LEN] = {
106 /* main statistics */
107 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
108 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
109 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
110 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
111 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
112 "tx_heartbeat_errors", "tx_window_errors",
113
114 /* port statistics */
115 "tso_packets",
116 "xmit_more",
117 "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_failed",
118 "rx_csum_good", "rx_csum_none", "rx_csum_complete", "tx_chksum_offload",
119
120 /* pf statistics */
121 "pf_rx_packets",
122 "pf_rx_bytes",
123 "pf_tx_packets",
124 "pf_tx_bytes",
125
126 /* priority flow control statistics rx */
127 "rx_pause_prio_0", "rx_pause_duration_prio_0",
128 "rx_pause_transition_prio_0",
129 "rx_pause_prio_1", "rx_pause_duration_prio_1",
130 "rx_pause_transition_prio_1",
131 "rx_pause_prio_2", "rx_pause_duration_prio_2",
132 "rx_pause_transition_prio_2",
133 "rx_pause_prio_3", "rx_pause_duration_prio_3",
134 "rx_pause_transition_prio_3",
135 "rx_pause_prio_4", "rx_pause_duration_prio_4",
136 "rx_pause_transition_prio_4",
137 "rx_pause_prio_5", "rx_pause_duration_prio_5",
138 "rx_pause_transition_prio_5",
139 "rx_pause_prio_6", "rx_pause_duration_prio_6",
140 "rx_pause_transition_prio_6",
141 "rx_pause_prio_7", "rx_pause_duration_prio_7",
142 "rx_pause_transition_prio_7",
143
144 /* flow control statistics rx */
145 "rx_pause", "rx_pause_duration", "rx_pause_transition",
146
147 /* priority flow control statistics tx */
148 "tx_pause_prio_0", "tx_pause_duration_prio_0",
149 "tx_pause_transition_prio_0",
150 "tx_pause_prio_1", "tx_pause_duration_prio_1",
151 "tx_pause_transition_prio_1",
152 "tx_pause_prio_2", "tx_pause_duration_prio_2",
153 "tx_pause_transition_prio_2",
154 "tx_pause_prio_3", "tx_pause_duration_prio_3",
155 "tx_pause_transition_prio_3",
156 "tx_pause_prio_4", "tx_pause_duration_prio_4",
157 "tx_pause_transition_prio_4",
158 "tx_pause_prio_5", "tx_pause_duration_prio_5",
159 "tx_pause_transition_prio_5",
160 "tx_pause_prio_6", "tx_pause_duration_prio_6",
161 "tx_pause_transition_prio_6",
162 "tx_pause_prio_7", "tx_pause_duration_prio_7",
163 "tx_pause_transition_prio_7",
164
165 /* flow control statistics tx */
166 "tx_pause", "tx_pause_duration", "tx_pause_transition",
167
168 /* packet statistics */
169 "rx_multicast_packets",
170 "rx_broadcast_packets",
171 "rx_jabbers",
172 "rx_in_range_length_error",
173 "rx_out_range_length_error",
174 "tx_multicast_packets",
175 "tx_broadcast_packets",
176 "rx_prio_0_packets", "rx_prio_0_bytes",
177 "rx_prio_1_packets", "rx_prio_1_bytes",
178 "rx_prio_2_packets", "rx_prio_2_bytes",
179 "rx_prio_3_packets", "rx_prio_3_bytes",
180 "rx_prio_4_packets", "rx_prio_4_bytes",
181 "rx_prio_5_packets", "rx_prio_5_bytes",
182 "rx_prio_6_packets", "rx_prio_6_bytes",
183 "rx_prio_7_packets", "rx_prio_7_bytes",
184 "rx_novlan_packets", "rx_novlan_bytes",
185 "tx_prio_0_packets", "tx_prio_0_bytes",
186 "tx_prio_1_packets", "tx_prio_1_bytes",
187 "tx_prio_2_packets", "tx_prio_2_bytes",
188 "tx_prio_3_packets", "tx_prio_3_bytes",
189 "tx_prio_4_packets", "tx_prio_4_bytes",
190 "tx_prio_5_packets", "tx_prio_5_bytes",
191 "tx_prio_6_packets", "tx_prio_6_bytes",
192 "tx_prio_7_packets", "tx_prio_7_bytes",
193 "tx_novlan_packets", "tx_novlan_bytes",
194
195 };
196
197 static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= {
198 "Interrupt Test",
199 "Link Test",
200 "Speed Test",
201 "Register Test",
202 "Loopback Test",
203 };
204
205 static u32 mlx4_en_get_msglevel(struct net_device *dev)
206 {
207 return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable;
208 }
209
210 static void mlx4_en_set_msglevel(struct net_device *dev, u32 val)
211 {
212 ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val;
213 }
214
215 static void mlx4_en_get_wol(struct net_device *netdev,
216 struct ethtool_wolinfo *wol)
217 {
218 struct mlx4_en_priv *priv = netdev_priv(netdev);
219 int err = 0;
220 u64 config = 0;
221 u64 mask;
222
223 if ((priv->port < 1) || (priv->port > 2)) {
224 en_err(priv, "Failed to get WoL information\n");
225 return;
226 }
227
228 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
229 MLX4_DEV_CAP_FLAG_WOL_PORT2;
230
231 if (!(priv->mdev->dev->caps.flags & mask)) {
232 wol->supported = 0;
233 wol->wolopts = 0;
234 return;
235 }
236
237 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
238 if (err) {
239 en_err(priv, "Failed to get WoL information\n");
240 return;
241 }
242
243 if (config & MLX4_EN_WOL_MAGIC)
244 wol->supported = WAKE_MAGIC;
245 else
246 wol->supported = 0;
247
248 if (config & MLX4_EN_WOL_ENABLED)
249 wol->wolopts = WAKE_MAGIC;
250 else
251 wol->wolopts = 0;
252 }
253
254 static int mlx4_en_set_wol(struct net_device *netdev,
255 struct ethtool_wolinfo *wol)
256 {
257 struct mlx4_en_priv *priv = netdev_priv(netdev);
258 u64 config = 0;
259 int err = 0;
260 u64 mask;
261
262 if ((priv->port < 1) || (priv->port > 2))
263 return -EOPNOTSUPP;
264
265 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
266 MLX4_DEV_CAP_FLAG_WOL_PORT2;
267
268 if (!(priv->mdev->dev->caps.flags & mask))
269 return -EOPNOTSUPP;
270
271 if (wol->supported & ~WAKE_MAGIC)
272 return -EINVAL;
273
274 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
275 if (err) {
276 en_err(priv, "Failed to get WoL info, unable to modify\n");
277 return err;
278 }
279
280 if (wol->wolopts & WAKE_MAGIC) {
281 config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED |
282 MLX4_EN_WOL_MAGIC;
283 } else {
284 config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC);
285 config |= MLX4_EN_WOL_DO_MODIFY;
286 }
287
288 err = mlx4_wol_write(priv->mdev->dev, config, priv->port);
289 if (err)
290 en_err(priv, "Failed to set WoL information\n");
291
292 return err;
293 }
294
295 struct bitmap_iterator {
296 unsigned long *stats_bitmap;
297 unsigned int count;
298 unsigned int iterator;
299 bool advance_array; /* if set, force no increments */
300 };
301
302 static inline void bitmap_iterator_init(struct bitmap_iterator *h,
303 unsigned long *stats_bitmap,
304 int count)
305 {
306 h->iterator = 0;
307 h->advance_array = !bitmap_empty(stats_bitmap, count);
308 h->count = h->advance_array ? bitmap_weight(stats_bitmap, count)
309 : count;
310 h->stats_bitmap = stats_bitmap;
311 }
312
313 static inline int bitmap_iterator_test(struct bitmap_iterator *h)
314 {
315 return !h->advance_array ? 1 : test_bit(h->iterator, h->stats_bitmap);
316 }
317
318 static inline int bitmap_iterator_inc(struct bitmap_iterator *h)
319 {
320 return h->iterator++;
321 }
322
323 static inline unsigned int
324 bitmap_iterator_count(struct bitmap_iterator *h)
325 {
326 return h->count;
327 }
328
329 static int mlx4_en_get_sset_count(struct net_device *dev, int sset)
330 {
331 struct mlx4_en_priv *priv = netdev_priv(dev);
332 struct bitmap_iterator it;
333
334 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
335
336 switch (sset) {
337 case ETH_SS_STATS:
338 return bitmap_iterator_count(&it) +
339 (priv->tx_ring_num * 2) +
340 (priv->rx_ring_num * 2);
341 case ETH_SS_TEST:
342 return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags
343 & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2;
344 case ETH_SS_PRIV_FLAGS:
345 return ARRAY_SIZE(mlx4_en_priv_flags);
346 default:
347 return -EOPNOTSUPP;
348 }
349 }
350
351 static void mlx4_en_get_ethtool_stats(struct net_device *dev,
352 struct ethtool_stats *stats, uint64_t *data)
353 {
354 struct mlx4_en_priv *priv = netdev_priv(dev);
355 int index = 0;
356 int i;
357 struct bitmap_iterator it;
358
359 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
360
361 spin_lock_bh(&priv->stats_lock);
362
363 for (i = 0; i < NUM_MAIN_STATS; i++, bitmap_iterator_inc(&it))
364 if (bitmap_iterator_test(&it))
365 data[index++] = ((unsigned long *)&priv->stats)[i];
366
367 for (i = 0; i < NUM_PORT_STATS; i++, bitmap_iterator_inc(&it))
368 if (bitmap_iterator_test(&it))
369 data[index++] = ((unsigned long *)&priv->port_stats)[i];
370
371 for (i = 0; i < NUM_PF_STATS; i++, bitmap_iterator_inc(&it))
372 if (bitmap_iterator_test(&it))
373 data[index++] =
374 ((unsigned long *)&priv->pf_stats)[i];
375
376 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_RX;
377 i++, bitmap_iterator_inc(&it))
378 if (bitmap_iterator_test(&it))
379 data[index++] =
380 ((u64 *)&priv->rx_priority_flowstats)[i];
381
382 for (i = 0; i < NUM_FLOW_STATS_RX; i++, bitmap_iterator_inc(&it))
383 if (bitmap_iterator_test(&it))
384 data[index++] = ((u64 *)&priv->rx_flowstats)[i];
385
386 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_TX;
387 i++, bitmap_iterator_inc(&it))
388 if (bitmap_iterator_test(&it))
389 data[index++] =
390 ((u64 *)&priv->tx_priority_flowstats)[i];
391
392 for (i = 0; i < NUM_FLOW_STATS_TX; i++, bitmap_iterator_inc(&it))
393 if (bitmap_iterator_test(&it))
394 data[index++] = ((u64 *)&priv->tx_flowstats)[i];
395
396 for (i = 0; i < NUM_PKT_STATS; i++, bitmap_iterator_inc(&it))
397 if (bitmap_iterator_test(&it))
398 data[index++] = ((unsigned long *)&priv->pkstats)[i];
399
400 for (i = 0; i < priv->tx_ring_num; i++) {
401 data[index++] = priv->tx_ring[i]->packets;
402 data[index++] = priv->tx_ring[i]->bytes;
403 }
404 for (i = 0; i < priv->rx_ring_num; i++) {
405 data[index++] = priv->rx_ring[i]->packets;
406 data[index++] = priv->rx_ring[i]->bytes;
407 }
408 spin_unlock_bh(&priv->stats_lock);
409
410 }
411
412 static void mlx4_en_self_test(struct net_device *dev,
413 struct ethtool_test *etest, u64 *buf)
414 {
415 mlx4_en_ex_selftest(dev, &etest->flags, buf);
416 }
417
418 static void mlx4_en_get_strings(struct net_device *dev,
419 uint32_t stringset, uint8_t *data)
420 {
421 struct mlx4_en_priv *priv = netdev_priv(dev);
422 int index = 0;
423 int i, strings = 0;
424 struct bitmap_iterator it;
425
426 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
427
428 switch (stringset) {
429 case ETH_SS_TEST:
430 for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++)
431 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
432 if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK)
433 for (; i < MLX4_EN_NUM_SELF_TEST; i++)
434 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
435 break;
436
437 case ETH_SS_STATS:
438 /* Add main counters */
439 for (i = 0; i < NUM_MAIN_STATS; i++, strings++,
440 bitmap_iterator_inc(&it))
441 if (bitmap_iterator_test(&it))
442 strcpy(data + (index++) * ETH_GSTRING_LEN,
443 main_strings[strings]);
444
445 for (i = 0; i < NUM_PORT_STATS; i++, strings++,
446 bitmap_iterator_inc(&it))
447 if (bitmap_iterator_test(&it))
448 strcpy(data + (index++) * ETH_GSTRING_LEN,
449 main_strings[strings]);
450
451 for (i = 0; i < NUM_PF_STATS; i++, strings++,
452 bitmap_iterator_inc(&it))
453 if (bitmap_iterator_test(&it))
454 strcpy(data + (index++) * ETH_GSTRING_LEN,
455 main_strings[strings]);
456
457 for (i = 0; i < NUM_FLOW_STATS; i++, strings++,
458 bitmap_iterator_inc(&it))
459 if (bitmap_iterator_test(&it))
460 strcpy(data + (index++) * ETH_GSTRING_LEN,
461 main_strings[strings]);
462
463 for (i = 0; i < NUM_PKT_STATS; i++, strings++,
464 bitmap_iterator_inc(&it))
465 if (bitmap_iterator_test(&it))
466 strcpy(data + (index++) * ETH_GSTRING_LEN,
467 main_strings[strings]);
468
469 for (i = 0; i < priv->tx_ring_num; i++) {
470 sprintf(data + (index++) * ETH_GSTRING_LEN,
471 "tx%d_packets", i);
472 sprintf(data + (index++) * ETH_GSTRING_LEN,
473 "tx%d_bytes", i);
474 }
475 for (i = 0; i < priv->rx_ring_num; i++) {
476 sprintf(data + (index++) * ETH_GSTRING_LEN,
477 "rx%d_packets", i);
478 sprintf(data + (index++) * ETH_GSTRING_LEN,
479 "rx%d_bytes", i);
480 }
481 break;
482 case ETH_SS_PRIV_FLAGS:
483 for (i = 0; i < ARRAY_SIZE(mlx4_en_priv_flags); i++)
484 strcpy(data + i * ETH_GSTRING_LEN,
485 mlx4_en_priv_flags[i]);
486 break;
487
488 }
489 }
490
491 static u32 mlx4_en_autoneg_get(struct net_device *dev)
492 {
493 struct mlx4_en_priv *priv = netdev_priv(dev);
494 struct mlx4_en_dev *mdev = priv->mdev;
495 u32 autoneg = AUTONEG_DISABLE;
496
497 if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) &&
498 (priv->port_state.flags & MLX4_EN_PORT_ANE))
499 autoneg = AUTONEG_ENABLE;
500
501 return autoneg;
502 }
503
504 static void ptys2ethtool_update_supported_port(unsigned long *mask,
505 struct mlx4_ptys_reg *ptys_reg)
506 {
507 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
508
509 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
510 | MLX4_PROT_MASK(MLX4_1000BASE_T)
511 | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
512 __set_bit(ETHTOOL_LINK_MODE_TP_BIT, mask);
513 } else if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
514 | MLX4_PROT_MASK(MLX4_10GBASE_SR)
515 | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
516 | MLX4_PROT_MASK(MLX4_40GBASE_CR4)
517 | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
518 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
519 __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mask);
520 } else if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
521 | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
522 | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
523 | MLX4_PROT_MASK(MLX4_10GBASE_KR)
524 | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
525 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
526 __set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mask);
527 }
528 }
529
530 static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg)
531 {
532 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper);
533
534 if (!eth_proto) /* link down */
535 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
536
537 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
538 | MLX4_PROT_MASK(MLX4_1000BASE_T)
539 | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
540 return PORT_TP;
541 }
542
543 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR)
544 | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
545 | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
546 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
547 return PORT_FIBRE;
548 }
549
550 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
551 | MLX4_PROT_MASK(MLX4_56GBASE_CR4)
552 | MLX4_PROT_MASK(MLX4_40GBASE_CR4))) {
553 return PORT_DA;
554 }
555
556 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
557 | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
558 | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
559 | MLX4_PROT_MASK(MLX4_10GBASE_KR)
560 | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
561 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
562 return PORT_NONE;
563 }
564 return PORT_OTHER;
565 }
566
567 #define MLX4_LINK_MODES_SZ \
568 (FIELD_SIZEOF(struct mlx4_ptys_reg, eth_proto_cap) * 8)
569
570 enum ethtool_report {
571 SUPPORTED = 0,
572 ADVERTISED = 1,
573 };
574
575 struct ptys2ethtool_config {
576 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
577 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
578 u32 speed;
579 };
580
581 static unsigned long *ptys2ethtool_link_mode(struct ptys2ethtool_config *cfg,
582 enum ethtool_report report)
583 {
584 switch (report) {
585 case SUPPORTED:
586 return cfg->supported;
587 case ADVERTISED:
588 return cfg->advertised;
589 }
590 return NULL;
591 }
592
593 #define MLX4_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \
594 ({ \
595 struct ptys2ethtool_config *cfg; \
596 const unsigned int modes[] = { __VA_ARGS__ }; \
597 unsigned int i; \
598 cfg = &ptys2ethtool_map[reg_]; \
599 cfg->speed = speed_; \
600 bitmap_zero(cfg->supported, \
601 __ETHTOOL_LINK_MODE_MASK_NBITS); \
602 bitmap_zero(cfg->advertised, \
603 __ETHTOOL_LINK_MODE_MASK_NBITS); \
604 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
605 __set_bit(modes[i], cfg->supported); \
606 __set_bit(modes[i], cfg->advertised); \
607 } \
608 })
609
610 /* Translates mlx4 link mode to equivalent ethtool Link modes/speed */
611 static struct ptys2ethtool_config ptys2ethtool_map[MLX4_LINK_MODES_SZ];
612
613 void __init mlx4_en_init_ptys2ethtool_map(void)
614 {
615 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_100BASE_TX, SPEED_100,
616 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
617 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_T, SPEED_1000,
618 ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
619 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_CX_SGMII, SPEED_1000,
620 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
621 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_KX, SPEED_1000,
622 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
623 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_T, SPEED_10000,
624 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
625 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CX4, SPEED_10000,
626 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
627 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KX4, SPEED_10000,
628 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
629 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KR, SPEED_10000,
630 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
631 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CR, SPEED_10000,
632 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
633 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_SR, SPEED_10000,
634 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
635 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_20GBASE_KR2, SPEED_20000,
636 ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT,
637 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
638 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_CR4, SPEED_40000,
639 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
640 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_KR4, SPEED_40000,
641 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
642 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_SR4, SPEED_40000,
643 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
644 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_KR4, SPEED_56000,
645 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
646 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_CR4, SPEED_56000,
647 ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT);
648 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_SR4, SPEED_56000,
649 ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT);
650 };
651
652 static void ptys2ethtool_update_link_modes(unsigned long *link_modes,
653 u32 eth_proto,
654 enum ethtool_report report)
655 {
656 int i;
657 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
658 if (eth_proto & MLX4_PROT_MASK(i))
659 bitmap_or(link_modes, link_modes,
660 ptys2ethtool_link_mode(&ptys2ethtool_map[i],
661 report),
662 __ETHTOOL_LINK_MODE_MASK_NBITS);
663 }
664 }
665
666 static u32 ethtool2ptys_link_modes(const unsigned long *link_modes,
667 enum ethtool_report report)
668 {
669 int i;
670 u32 ptys_modes = 0;
671
672 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
673 if (bitmap_intersects(
674 ptys2ethtool_link_mode(&ptys2ethtool_map[i],
675 report),
676 link_modes,
677 __ETHTOOL_LINK_MODE_MASK_NBITS))
678 ptys_modes |= 1 << i;
679 }
680 return ptys_modes;
681 }
682
683 /* Convert actual speed (SPEED_XXX) to ptys link modes */
684 static u32 speed2ptys_link_modes(u32 speed)
685 {
686 int i;
687 u32 ptys_modes = 0;
688
689 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
690 if (ptys2ethtool_map[i].speed == speed)
691 ptys_modes |= 1 << i;
692 }
693 return ptys_modes;
694 }
695
696 static int
697 ethtool_get_ptys_link_ksettings(struct net_device *dev,
698 struct ethtool_link_ksettings *link_ksettings)
699 {
700 struct mlx4_en_priv *priv = netdev_priv(dev);
701 struct mlx4_ptys_reg ptys_reg;
702 u32 eth_proto;
703 int ret;
704
705 memset(&ptys_reg, 0, sizeof(ptys_reg));
706 ptys_reg.local_port = priv->port;
707 ptys_reg.proto_mask = MLX4_PTYS_EN;
708 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
709 MLX4_ACCESS_REG_QUERY, &ptys_reg);
710 if (ret) {
711 en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)",
712 ret);
713 return ret;
714 }
715 en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n",
716 ptys_reg.proto_mask);
717 en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n",
718 be32_to_cpu(ptys_reg.eth_proto_cap));
719 en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n",
720 be32_to_cpu(ptys_reg.eth_proto_admin));
721 en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n",
722 be32_to_cpu(ptys_reg.eth_proto_oper));
723 en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n",
724 be32_to_cpu(ptys_reg.eth_proto_lp_adv));
725
726 /* reset supported/advertising masks */
727 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
728 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
729
730 ptys2ethtool_update_supported_port(link_ksettings->link_modes.supported,
731 &ptys_reg);
732
733 eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap);
734 ptys2ethtool_update_link_modes(link_ksettings->link_modes.supported,
735 eth_proto, SUPPORTED);
736
737 eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin);
738 ptys2ethtool_update_link_modes(link_ksettings->link_modes.advertising,
739 eth_proto, ADVERTISED);
740
741 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
742 Pause);
743 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
744 Asym_Pause);
745
746 if (priv->prof->tx_pause)
747 ethtool_link_ksettings_add_link_mode(link_ksettings,
748 advertising, Pause);
749 if (priv->prof->tx_pause ^ priv->prof->rx_pause)
750 ethtool_link_ksettings_add_link_mode(link_ksettings,
751 advertising, Asym_Pause);
752
753 link_ksettings->base.port = ptys_get_active_port(&ptys_reg);
754
755 if (mlx4_en_autoneg_get(dev)) {
756 ethtool_link_ksettings_add_link_mode(link_ksettings,
757 supported, Autoneg);
758 ethtool_link_ksettings_add_link_mode(link_ksettings,
759 advertising, Autoneg);
760 }
761
762 link_ksettings->base.autoneg
763 = (priv->port_state.flags & MLX4_EN_PORT_ANC) ?
764 AUTONEG_ENABLE : AUTONEG_DISABLE;
765
766 eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv);
767
768 ethtool_link_ksettings_zero_link_mode(link_ksettings, lp_advertising);
769 ptys2ethtool_update_link_modes(
770 link_ksettings->link_modes.lp_advertising,
771 eth_proto, ADVERTISED);
772 if (priv->port_state.flags & MLX4_EN_PORT_ANC)
773 ethtool_link_ksettings_add_link_mode(link_ksettings,
774 lp_advertising, Autoneg);
775
776 link_ksettings->base.phy_address = 0;
777 link_ksettings->base.mdio_support = 0;
778 link_ksettings->base.eth_tp_mdix = ETH_TP_MDI_INVALID;
779 link_ksettings->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
780
781 return ret;
782 }
783
784 static void
785 ethtool_get_default_link_ksettings(
786 struct net_device *dev, struct ethtool_link_ksettings *link_ksettings)
787 {
788 struct mlx4_en_priv *priv = netdev_priv(dev);
789 int trans_type;
790
791 link_ksettings->base.autoneg = AUTONEG_DISABLE;
792
793 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
794 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
795 10000baseT_Full);
796
797 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
798 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising,
799 10000baseT_Full);
800
801 trans_type = priv->port_state.transceiver;
802 if (trans_type > 0 && trans_type <= 0xC) {
803 link_ksettings->base.port = PORT_FIBRE;
804 ethtool_link_ksettings_add_link_mode(link_ksettings,
805 supported, FIBRE);
806 ethtool_link_ksettings_add_link_mode(link_ksettings,
807 advertising, FIBRE);
808 } else if (trans_type == 0x80 || trans_type == 0) {
809 link_ksettings->base.port = PORT_TP;
810 ethtool_link_ksettings_add_link_mode(link_ksettings,
811 supported, TP);
812 ethtool_link_ksettings_add_link_mode(link_ksettings,
813 advertising, TP);
814 } else {
815 link_ksettings->base.port = -1;
816 }
817 }
818
819 static int
820 mlx4_en_get_link_ksettings(struct net_device *dev,
821 struct ethtool_link_ksettings *link_ksettings)
822 {
823 struct mlx4_en_priv *priv = netdev_priv(dev);
824 int ret = -EINVAL;
825
826 if (mlx4_en_QUERY_PORT(priv->mdev, priv->port))
827 return -ENOMEM;
828
829 en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n",
830 priv->port_state.flags & MLX4_EN_PORT_ANC,
831 priv->port_state.flags & MLX4_EN_PORT_ANE);
832
833 if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL)
834 ret = ethtool_get_ptys_link_ksettings(dev, link_ksettings);
835 if (ret) /* ETH PROT CRTL is not supported or PTYS CMD failed */
836 ethtool_get_default_link_ksettings(dev, link_ksettings);
837
838 if (netif_carrier_ok(dev)) {
839 link_ksettings->base.speed = priv->port_state.link_speed;
840 link_ksettings->base.duplex = DUPLEX_FULL;
841 } else {
842 link_ksettings->base.speed = SPEED_UNKNOWN;
843 link_ksettings->base.duplex = DUPLEX_UNKNOWN;
844 }
845 return 0;
846 }
847
848 /* Calculate PTYS admin according ethtool speed (SPEED_XXX) */
849 static __be32 speed_set_ptys_admin(struct mlx4_en_priv *priv, u32 speed,
850 __be32 proto_cap)
851 {
852 __be32 proto_admin = 0;
853
854 if (!speed) { /* Speed = 0 ==> Reset Link modes */
855 proto_admin = proto_cap;
856 en_info(priv, "Speed was set to 0, Reset advertised Link Modes to default (%x)\n",
857 be32_to_cpu(proto_cap));
858 } else {
859 u32 ptys_link_modes = speed2ptys_link_modes(speed);
860
861 proto_admin = cpu_to_be32(ptys_link_modes) & proto_cap;
862 en_info(priv, "Setting Speed to %d\n", speed);
863 }
864 return proto_admin;
865 }
866
867 static int
868 mlx4_en_set_link_ksettings(struct net_device *dev,
869 const struct ethtool_link_ksettings *link_ksettings)
870 {
871 struct mlx4_en_priv *priv = netdev_priv(dev);
872 struct mlx4_ptys_reg ptys_reg;
873 __be32 proto_admin;
874 int ret;
875
876 u32 ptys_adv = ethtool2ptys_link_modes(
877 link_ksettings->link_modes.advertising, ADVERTISED);
878 const int speed = link_ksettings->base.speed;
879
880 en_dbg(DRV, priv,
881 "Set Speed=%d adv={%*pbl} autoneg=%d duplex=%d\n",
882 speed, __ETHTOOL_LINK_MODE_MASK_NBITS,
883 link_ksettings->link_modes.advertising,
884 link_ksettings->base.autoneg,
885 link_ksettings->base.duplex);
886
887 if (!(priv->mdev->dev->caps.flags2 &
888 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) ||
889 (link_ksettings->base.duplex == DUPLEX_HALF))
890 return -EINVAL;
891
892 memset(&ptys_reg, 0, sizeof(ptys_reg));
893 ptys_reg.local_port = priv->port;
894 ptys_reg.proto_mask = MLX4_PTYS_EN;
895 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
896 MLX4_ACCESS_REG_QUERY, &ptys_reg);
897 if (ret) {
898 en_warn(priv, "Failed to QUERY mlx4_ACCESS_PTYS_REG status(%x)\n",
899 ret);
900 return 0;
901 }
902
903 proto_admin = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
904 cpu_to_be32(ptys_adv) :
905 speed_set_ptys_admin(priv, speed,
906 ptys_reg.eth_proto_cap);
907
908 proto_admin &= ptys_reg.eth_proto_cap;
909 if (!proto_admin) {
910 en_warn(priv, "Not supported link mode(s) requested, check supported link modes.\n");
911 return -EINVAL; /* nothing to change due to bad input */
912 }
913
914 if (proto_admin == ptys_reg.eth_proto_admin)
915 return 0; /* Nothing to change */
916
917 en_dbg(DRV, priv, "mlx4_ACCESS_PTYS_REG SET: ptys_reg.eth_proto_admin = 0x%x\n",
918 be32_to_cpu(proto_admin));
919
920 ptys_reg.eth_proto_admin = proto_admin;
921 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, MLX4_ACCESS_REG_WRITE,
922 &ptys_reg);
923 if (ret) {
924 en_warn(priv, "Failed to write mlx4_ACCESS_PTYS_REG eth_proto_admin(0x%x) status(0x%x)",
925 be32_to_cpu(ptys_reg.eth_proto_admin), ret);
926 return ret;
927 }
928
929 mutex_lock(&priv->mdev->state_lock);
930 if (priv->port_up) {
931 en_warn(priv, "Port link mode changed, restarting port...\n");
932 mlx4_en_stop_port(dev, 1);
933 if (mlx4_en_start_port(dev))
934 en_err(priv, "Failed restarting port %d\n", priv->port);
935 }
936 mutex_unlock(&priv->mdev->state_lock);
937 return 0;
938 }
939
940 static int mlx4_en_get_coalesce(struct net_device *dev,
941 struct ethtool_coalesce *coal)
942 {
943 struct mlx4_en_priv *priv = netdev_priv(dev);
944
945 coal->tx_coalesce_usecs = priv->tx_usecs;
946 coal->tx_max_coalesced_frames = priv->tx_frames;
947 coal->tx_max_coalesced_frames_irq = priv->tx_work_limit;
948
949 coal->rx_coalesce_usecs = priv->rx_usecs;
950 coal->rx_max_coalesced_frames = priv->rx_frames;
951
952 coal->pkt_rate_low = priv->pkt_rate_low;
953 coal->rx_coalesce_usecs_low = priv->rx_usecs_low;
954 coal->pkt_rate_high = priv->pkt_rate_high;
955 coal->rx_coalesce_usecs_high = priv->rx_usecs_high;
956 coal->rate_sample_interval = priv->sample_interval;
957 coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal;
958
959 return 0;
960 }
961
962 static int mlx4_en_set_coalesce(struct net_device *dev,
963 struct ethtool_coalesce *coal)
964 {
965 struct mlx4_en_priv *priv = netdev_priv(dev);
966
967 if (!coal->tx_max_coalesced_frames_irq)
968 return -EINVAL;
969
970 priv->rx_frames = (coal->rx_max_coalesced_frames ==
971 MLX4_EN_AUTO_CONF) ?
972 MLX4_EN_RX_COAL_TARGET :
973 coal->rx_max_coalesced_frames;
974 priv->rx_usecs = (coal->rx_coalesce_usecs ==
975 MLX4_EN_AUTO_CONF) ?
976 MLX4_EN_RX_COAL_TIME :
977 coal->rx_coalesce_usecs;
978
979 /* Setting TX coalescing parameters */
980 if (coal->tx_coalesce_usecs != priv->tx_usecs ||
981 coal->tx_max_coalesced_frames != priv->tx_frames) {
982 priv->tx_usecs = coal->tx_coalesce_usecs;
983 priv->tx_frames = coal->tx_max_coalesced_frames;
984 }
985
986 /* Set adaptive coalescing params */
987 priv->pkt_rate_low = coal->pkt_rate_low;
988 priv->rx_usecs_low = coal->rx_coalesce_usecs_low;
989 priv->pkt_rate_high = coal->pkt_rate_high;
990 priv->rx_usecs_high = coal->rx_coalesce_usecs_high;
991 priv->sample_interval = coal->rate_sample_interval;
992 priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce;
993 priv->tx_work_limit = coal->tx_max_coalesced_frames_irq;
994
995 return mlx4_en_moderation_update(priv);
996 }
997
998 static int mlx4_en_set_pauseparam(struct net_device *dev,
999 struct ethtool_pauseparam *pause)
1000 {
1001 struct mlx4_en_priv *priv = netdev_priv(dev);
1002 struct mlx4_en_dev *mdev = priv->mdev;
1003 int err;
1004
1005 if (pause->autoneg)
1006 return -EINVAL;
1007
1008 priv->prof->tx_pause = pause->tx_pause != 0;
1009 priv->prof->rx_pause = pause->rx_pause != 0;
1010 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1011 priv->rx_skb_size + ETH_FCS_LEN,
1012 priv->prof->tx_pause,
1013 priv->prof->tx_ppp,
1014 priv->prof->rx_pause,
1015 priv->prof->rx_ppp);
1016 if (err)
1017 en_err(priv, "Failed setting pause params\n");
1018 else
1019 mlx4_en_update_pfc_stats_bitmap(mdev->dev, &priv->stats_bitmap,
1020 priv->prof->rx_ppp,
1021 priv->prof->rx_pause,
1022 priv->prof->tx_ppp,
1023 priv->prof->tx_pause);
1024
1025 return err;
1026 }
1027
1028 static void mlx4_en_get_pauseparam(struct net_device *dev,
1029 struct ethtool_pauseparam *pause)
1030 {
1031 struct mlx4_en_priv *priv = netdev_priv(dev);
1032
1033 pause->tx_pause = priv->prof->tx_pause;
1034 pause->rx_pause = priv->prof->rx_pause;
1035 }
1036
1037 static int mlx4_en_set_ringparam(struct net_device *dev,
1038 struct ethtool_ringparam *param)
1039 {
1040 struct mlx4_en_priv *priv = netdev_priv(dev);
1041 struct mlx4_en_dev *mdev = priv->mdev;
1042 u32 rx_size, tx_size;
1043 int port_up = 0;
1044 int err = 0;
1045
1046 if (param->rx_jumbo_pending || param->rx_mini_pending)
1047 return -EINVAL;
1048
1049 rx_size = roundup_pow_of_two(param->rx_pending);
1050 rx_size = max_t(u32, rx_size, MLX4_EN_MIN_RX_SIZE);
1051 rx_size = min_t(u32, rx_size, MLX4_EN_MAX_RX_SIZE);
1052 tx_size = roundup_pow_of_two(param->tx_pending);
1053 tx_size = max_t(u32, tx_size, MLX4_EN_MIN_TX_SIZE);
1054 tx_size = min_t(u32, tx_size, MLX4_EN_MAX_TX_SIZE);
1055
1056 if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size :
1057 priv->rx_ring[0]->size) &&
1058 tx_size == priv->tx_ring[0]->size)
1059 return 0;
1060
1061 mutex_lock(&mdev->state_lock);
1062 if (priv->port_up) {
1063 port_up = 1;
1064 mlx4_en_stop_port(dev, 1);
1065 }
1066
1067 mlx4_en_free_resources(priv);
1068
1069 priv->prof->tx_ring_size = tx_size;
1070 priv->prof->rx_ring_size = rx_size;
1071
1072 err = mlx4_en_alloc_resources(priv);
1073 if (err) {
1074 en_err(priv, "Failed reallocating port resources\n");
1075 goto out;
1076 }
1077 if (port_up) {
1078 err = mlx4_en_start_port(dev);
1079 if (err)
1080 en_err(priv, "Failed starting port\n");
1081 }
1082
1083 err = mlx4_en_moderation_update(priv);
1084
1085 out:
1086 mutex_unlock(&mdev->state_lock);
1087 return err;
1088 }
1089
1090 static void mlx4_en_get_ringparam(struct net_device *dev,
1091 struct ethtool_ringparam *param)
1092 {
1093 struct mlx4_en_priv *priv = netdev_priv(dev);
1094
1095 memset(param, 0, sizeof(*param));
1096 param->rx_max_pending = MLX4_EN_MAX_RX_SIZE;
1097 param->tx_max_pending = MLX4_EN_MAX_TX_SIZE;
1098 param->rx_pending = priv->port_up ?
1099 priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size;
1100 param->tx_pending = priv->tx_ring[0]->size;
1101 }
1102
1103 static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev)
1104 {
1105 struct mlx4_en_priv *priv = netdev_priv(dev);
1106
1107 return priv->rx_ring_num;
1108 }
1109
1110 static u32 mlx4_en_get_rxfh_key_size(struct net_device *netdev)
1111 {
1112 return MLX4_EN_RSS_KEY_SIZE;
1113 }
1114
1115 static int mlx4_en_check_rxfh_func(struct net_device *dev, u8 hfunc)
1116 {
1117 struct mlx4_en_priv *priv = netdev_priv(dev);
1118
1119 /* check if requested function is supported by the device */
1120 if (hfunc == ETH_RSS_HASH_TOP) {
1121 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP))
1122 return -EINVAL;
1123 if (!(dev->features & NETIF_F_RXHASH))
1124 en_warn(priv, "Toeplitz hash function should be used in conjunction with RX hashing for optimal performance\n");
1125 return 0;
1126 } else if (hfunc == ETH_RSS_HASH_XOR) {
1127 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR))
1128 return -EINVAL;
1129 if (dev->features & NETIF_F_RXHASH)
1130 en_warn(priv, "Enabling both XOR Hash function and RX Hashing can limit RPS functionality\n");
1131 return 0;
1132 }
1133
1134 return -EINVAL;
1135 }
1136
1137 static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key,
1138 u8 *hfunc)
1139 {
1140 struct mlx4_en_priv *priv = netdev_priv(dev);
1141 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1142 int rss_rings;
1143 size_t n = priv->rx_ring_num;
1144 int err = 0;
1145
1146 rss_rings = priv->prof->rss_rings ?: priv->rx_ring_num;
1147 rss_rings = 1 << ilog2(rss_rings);
1148
1149 while (n--) {
1150 if (!ring_index)
1151 break;
1152 ring_index[n] = rss_map->qps[n % rss_rings].qpn -
1153 rss_map->base_qpn;
1154 }
1155 if (key)
1156 memcpy(key, priv->rss_key, MLX4_EN_RSS_KEY_SIZE);
1157 if (hfunc)
1158 *hfunc = priv->rss_hash_fn;
1159 return err;
1160 }
1161
1162 static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index,
1163 const u8 *key, const u8 hfunc)
1164 {
1165 struct mlx4_en_priv *priv = netdev_priv(dev);
1166 struct mlx4_en_dev *mdev = priv->mdev;
1167 int port_up = 0;
1168 int err = 0;
1169 int i;
1170 int rss_rings = 0;
1171
1172 /* Calculate RSS table size and make sure flows are spread evenly
1173 * between rings
1174 */
1175 for (i = 0; i < priv->rx_ring_num; i++) {
1176 if (!ring_index)
1177 continue;
1178 if (i > 0 && !ring_index[i] && !rss_rings)
1179 rss_rings = i;
1180
1181 if (ring_index[i] != (i % (rss_rings ?: priv->rx_ring_num)))
1182 return -EINVAL;
1183 }
1184
1185 if (!rss_rings)
1186 rss_rings = priv->rx_ring_num;
1187
1188 /* RSS table size must be an order of 2 */
1189 if (!is_power_of_2(rss_rings))
1190 return -EINVAL;
1191
1192 if (hfunc != ETH_RSS_HASH_NO_CHANGE) {
1193 err = mlx4_en_check_rxfh_func(dev, hfunc);
1194 if (err)
1195 return err;
1196 }
1197
1198 mutex_lock(&mdev->state_lock);
1199 if (priv->port_up) {
1200 port_up = 1;
1201 mlx4_en_stop_port(dev, 1);
1202 }
1203
1204 if (ring_index)
1205 priv->prof->rss_rings = rss_rings;
1206 if (key)
1207 memcpy(priv->rss_key, key, MLX4_EN_RSS_KEY_SIZE);
1208 if (hfunc != ETH_RSS_HASH_NO_CHANGE)
1209 priv->rss_hash_fn = hfunc;
1210
1211 if (port_up) {
1212 err = mlx4_en_start_port(dev);
1213 if (err)
1214 en_err(priv, "Failed starting port\n");
1215 }
1216
1217 mutex_unlock(&mdev->state_lock);
1218 return err;
1219 }
1220
1221 #define all_zeros_or_all_ones(field) \
1222 ((field) == 0 || (field) == (__force typeof(field))-1)
1223
1224 static int mlx4_en_validate_flow(struct net_device *dev,
1225 struct ethtool_rxnfc *cmd)
1226 {
1227 struct ethtool_usrip4_spec *l3_mask;
1228 struct ethtool_tcpip4_spec *l4_mask;
1229 struct ethhdr *eth_mask;
1230
1231 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1232 return -EINVAL;
1233
1234 if (cmd->fs.flow_type & FLOW_MAC_EXT) {
1235 /* dest mac mask must be ff:ff:ff:ff:ff:ff */
1236 if (!is_broadcast_ether_addr(cmd->fs.m_ext.h_dest))
1237 return -EINVAL;
1238 }
1239
1240 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1241 case TCP_V4_FLOW:
1242 case UDP_V4_FLOW:
1243 if (cmd->fs.m_u.tcp_ip4_spec.tos)
1244 return -EINVAL;
1245 l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1246 /* don't allow mask which isn't all 0 or 1 */
1247 if (!all_zeros_or_all_ones(l4_mask->ip4src) ||
1248 !all_zeros_or_all_ones(l4_mask->ip4dst) ||
1249 !all_zeros_or_all_ones(l4_mask->psrc) ||
1250 !all_zeros_or_all_ones(l4_mask->pdst))
1251 return -EINVAL;
1252 break;
1253 case IP_USER_FLOW:
1254 l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1255 if (l3_mask->l4_4_bytes || l3_mask->tos || l3_mask->proto ||
1256 cmd->fs.h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4 ||
1257 (!l3_mask->ip4src && !l3_mask->ip4dst) ||
1258 !all_zeros_or_all_ones(l3_mask->ip4src) ||
1259 !all_zeros_or_all_ones(l3_mask->ip4dst))
1260 return -EINVAL;
1261 break;
1262 case ETHER_FLOW:
1263 eth_mask = &cmd->fs.m_u.ether_spec;
1264 /* source mac mask must not be set */
1265 if (!is_zero_ether_addr(eth_mask->h_source))
1266 return -EINVAL;
1267
1268 /* dest mac mask must be ff:ff:ff:ff:ff:ff */
1269 if (!is_broadcast_ether_addr(eth_mask->h_dest))
1270 return -EINVAL;
1271
1272 if (!all_zeros_or_all_ones(eth_mask->h_proto))
1273 return -EINVAL;
1274 break;
1275 default:
1276 return -EINVAL;
1277 }
1278
1279 if ((cmd->fs.flow_type & FLOW_EXT)) {
1280 if (cmd->fs.m_ext.vlan_etype ||
1281 !((cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1282 0 ||
1283 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1284 cpu_to_be16(VLAN_VID_MASK)))
1285 return -EINVAL;
1286
1287 if (cmd->fs.m_ext.vlan_tci) {
1288 if (be16_to_cpu(cmd->fs.h_ext.vlan_tci) >= VLAN_N_VID)
1289 return -EINVAL;
1290
1291 }
1292 }
1293
1294 return 0;
1295 }
1296
1297 static int mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc *cmd,
1298 struct list_head *rule_list_h,
1299 struct mlx4_spec_list *spec_l2,
1300 unsigned char *mac)
1301 {
1302 int err = 0;
1303 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
1304
1305 spec_l2->id = MLX4_NET_TRANS_RULE_ID_ETH;
1306 memcpy(spec_l2->eth.dst_mac_msk, &mac_msk, ETH_ALEN);
1307 memcpy(spec_l2->eth.dst_mac, mac, ETH_ALEN);
1308
1309 if ((cmd->fs.flow_type & FLOW_EXT) &&
1310 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) {
1311 spec_l2->eth.vlan_id = cmd->fs.h_ext.vlan_tci;
1312 spec_l2->eth.vlan_id_msk = cpu_to_be16(VLAN_VID_MASK);
1313 }
1314
1315 list_add_tail(&spec_l2->list, rule_list_h);
1316
1317 return err;
1318 }
1319
1320 static int mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv *priv,
1321 struct ethtool_rxnfc *cmd,
1322 struct list_head *rule_list_h,
1323 struct mlx4_spec_list *spec_l2,
1324 __be32 ipv4_dst)
1325 {
1326 #ifdef CONFIG_INET
1327 unsigned char mac[ETH_ALEN];
1328
1329 if (!ipv4_is_multicast(ipv4_dst)) {
1330 if (cmd->fs.flow_type & FLOW_MAC_EXT)
1331 memcpy(&mac, cmd->fs.h_ext.h_dest, ETH_ALEN);
1332 else
1333 memcpy(&mac, priv->dev->dev_addr, ETH_ALEN);
1334 } else {
1335 ip_eth_mc_map(ipv4_dst, mac);
1336 }
1337
1338 return mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, &mac[0]);
1339 #else
1340 return -EINVAL;
1341 #endif
1342 }
1343
1344 static int add_ip_rule(struct mlx4_en_priv *priv,
1345 struct ethtool_rxnfc *cmd,
1346 struct list_head *list_h)
1347 {
1348 int err;
1349 struct mlx4_spec_list *spec_l2 = NULL;
1350 struct mlx4_spec_list *spec_l3 = NULL;
1351 struct ethtool_usrip4_spec *l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1352
1353 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1354 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1355 if (!spec_l2 || !spec_l3) {
1356 err = -ENOMEM;
1357 goto free_spec;
1358 }
1359
1360 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, spec_l2,
1361 cmd->fs.h_u.
1362 usr_ip4_spec.ip4dst);
1363 if (err)
1364 goto free_spec;
1365 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1366 spec_l3->ipv4.src_ip = cmd->fs.h_u.usr_ip4_spec.ip4src;
1367 if (l3_mask->ip4src)
1368 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1369 spec_l3->ipv4.dst_ip = cmd->fs.h_u.usr_ip4_spec.ip4dst;
1370 if (l3_mask->ip4dst)
1371 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1372 list_add_tail(&spec_l3->list, list_h);
1373
1374 return 0;
1375
1376 free_spec:
1377 kfree(spec_l2);
1378 kfree(spec_l3);
1379 return err;
1380 }
1381
1382 static int add_tcp_udp_rule(struct mlx4_en_priv *priv,
1383 struct ethtool_rxnfc *cmd,
1384 struct list_head *list_h, int proto)
1385 {
1386 int err;
1387 struct mlx4_spec_list *spec_l2 = NULL;
1388 struct mlx4_spec_list *spec_l3 = NULL;
1389 struct mlx4_spec_list *spec_l4 = NULL;
1390 struct ethtool_tcpip4_spec *l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1391
1392 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1393 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1394 spec_l4 = kzalloc(sizeof(*spec_l4), GFP_KERNEL);
1395 if (!spec_l2 || !spec_l3 || !spec_l4) {
1396 err = -ENOMEM;
1397 goto free_spec;
1398 }
1399
1400 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1401
1402 if (proto == TCP_V4_FLOW) {
1403 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1404 spec_l2,
1405 cmd->fs.h_u.
1406 tcp_ip4_spec.ip4dst);
1407 if (err)
1408 goto free_spec;
1409 spec_l4->id = MLX4_NET_TRANS_RULE_ID_TCP;
1410 spec_l3->ipv4.src_ip = cmd->fs.h_u.tcp_ip4_spec.ip4src;
1411 spec_l3->ipv4.dst_ip = cmd->fs.h_u.tcp_ip4_spec.ip4dst;
1412 spec_l4->tcp_udp.src_port = cmd->fs.h_u.tcp_ip4_spec.psrc;
1413 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.tcp_ip4_spec.pdst;
1414 } else {
1415 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1416 spec_l2,
1417 cmd->fs.h_u.
1418 udp_ip4_spec.ip4dst);
1419 if (err)
1420 goto free_spec;
1421 spec_l4->id = MLX4_NET_TRANS_RULE_ID_UDP;
1422 spec_l3->ipv4.src_ip = cmd->fs.h_u.udp_ip4_spec.ip4src;
1423 spec_l3->ipv4.dst_ip = cmd->fs.h_u.udp_ip4_spec.ip4dst;
1424 spec_l4->tcp_udp.src_port = cmd->fs.h_u.udp_ip4_spec.psrc;
1425 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.udp_ip4_spec.pdst;
1426 }
1427
1428 if (l4_mask->ip4src)
1429 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1430 if (l4_mask->ip4dst)
1431 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1432
1433 if (l4_mask->psrc)
1434 spec_l4->tcp_udp.src_port_msk = EN_ETHTOOL_SHORT_MASK;
1435 if (l4_mask->pdst)
1436 spec_l4->tcp_udp.dst_port_msk = EN_ETHTOOL_SHORT_MASK;
1437
1438 list_add_tail(&spec_l3->list, list_h);
1439 list_add_tail(&spec_l4->list, list_h);
1440
1441 return 0;
1442
1443 free_spec:
1444 kfree(spec_l2);
1445 kfree(spec_l3);
1446 kfree(spec_l4);
1447 return err;
1448 }
1449
1450 static int mlx4_en_ethtool_to_net_trans_rule(struct net_device *dev,
1451 struct ethtool_rxnfc *cmd,
1452 struct list_head *rule_list_h)
1453 {
1454 int err;
1455 struct ethhdr *eth_spec;
1456 struct mlx4_spec_list *spec_l2;
1457 struct mlx4_en_priv *priv = netdev_priv(dev);
1458
1459 err = mlx4_en_validate_flow(dev, cmd);
1460 if (err)
1461 return err;
1462
1463 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1464 case ETHER_FLOW:
1465 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1466 if (!spec_l2)
1467 return -ENOMEM;
1468
1469 eth_spec = &cmd->fs.h_u.ether_spec;
1470 mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2,
1471 &eth_spec->h_dest[0]);
1472 spec_l2->eth.ether_type = eth_spec->h_proto;
1473 if (eth_spec->h_proto)
1474 spec_l2->eth.ether_type_enable = 1;
1475 break;
1476 case IP_USER_FLOW:
1477 err = add_ip_rule(priv, cmd, rule_list_h);
1478 break;
1479 case TCP_V4_FLOW:
1480 err = add_tcp_udp_rule(priv, cmd, rule_list_h, TCP_V4_FLOW);
1481 break;
1482 case UDP_V4_FLOW:
1483 err = add_tcp_udp_rule(priv, cmd, rule_list_h, UDP_V4_FLOW);
1484 break;
1485 }
1486
1487 return err;
1488 }
1489
1490 static int mlx4_en_flow_replace(struct net_device *dev,
1491 struct ethtool_rxnfc *cmd)
1492 {
1493 int err;
1494 struct mlx4_en_priv *priv = netdev_priv(dev);
1495 struct ethtool_flow_id *loc_rule;
1496 struct mlx4_spec_list *spec, *tmp_spec;
1497 u32 qpn;
1498 u64 reg_id;
1499
1500 struct mlx4_net_trans_rule rule = {
1501 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1502 .exclusive = 0,
1503 .allow_loopback = 1,
1504 .promisc_mode = MLX4_FS_REGULAR,
1505 };
1506
1507 rule.port = priv->port;
1508 rule.priority = MLX4_DOMAIN_ETHTOOL | cmd->fs.location;
1509 INIT_LIST_HEAD(&rule.list);
1510
1511 /* Allow direct QP attaches if the EN_ETHTOOL_QP_ATTACH flag is set */
1512 if (cmd->fs.ring_cookie == RX_CLS_FLOW_DISC)
1513 qpn = priv->drop_qp.qpn;
1514 else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) {
1515 qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1);
1516 } else {
1517 if (cmd->fs.ring_cookie >= priv->rx_ring_num) {
1518 en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n",
1519 cmd->fs.ring_cookie);
1520 return -EINVAL;
1521 }
1522 qpn = priv->rss_map.qps[cmd->fs.ring_cookie].qpn;
1523 if (!qpn) {
1524 en_warn(priv, "rxnfc: RX ring (%llu) is inactive\n",
1525 cmd->fs.ring_cookie);
1526 return -EINVAL;
1527 }
1528 }
1529 rule.qpn = qpn;
1530 err = mlx4_en_ethtool_to_net_trans_rule(dev, cmd, &rule.list);
1531 if (err)
1532 goto out_free_list;
1533
1534 loc_rule = &priv->ethtool_rules[cmd->fs.location];
1535 if (loc_rule->id) {
1536 err = mlx4_flow_detach(priv->mdev->dev, loc_rule->id);
1537 if (err) {
1538 en_err(priv, "Fail to detach network rule at location %d. registration id = %llx\n",
1539 cmd->fs.location, loc_rule->id);
1540 goto out_free_list;
1541 }
1542 loc_rule->id = 0;
1543 memset(&loc_rule->flow_spec, 0,
1544 sizeof(struct ethtool_rx_flow_spec));
1545 list_del(&loc_rule->list);
1546 }
1547 err = mlx4_flow_attach(priv->mdev->dev, &rule, &reg_id);
1548 if (err) {
1549 en_err(priv, "Fail to attach network rule at location %d\n",
1550 cmd->fs.location);
1551 goto out_free_list;
1552 }
1553 loc_rule->id = reg_id;
1554 memcpy(&loc_rule->flow_spec, &cmd->fs,
1555 sizeof(struct ethtool_rx_flow_spec));
1556 list_add_tail(&loc_rule->list, &priv->ethtool_list);
1557
1558 out_free_list:
1559 list_for_each_entry_safe(spec, tmp_spec, &rule.list, list) {
1560 list_del(&spec->list);
1561 kfree(spec);
1562 }
1563 return err;
1564 }
1565
1566 static int mlx4_en_flow_detach(struct net_device *dev,
1567 struct ethtool_rxnfc *cmd)
1568 {
1569 int err = 0;
1570 struct ethtool_flow_id *rule;
1571 struct mlx4_en_priv *priv = netdev_priv(dev);
1572
1573 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1574 return -EINVAL;
1575
1576 rule = &priv->ethtool_rules[cmd->fs.location];
1577 if (!rule->id) {
1578 err = -ENOENT;
1579 goto out;
1580 }
1581
1582 err = mlx4_flow_detach(priv->mdev->dev, rule->id);
1583 if (err) {
1584 en_err(priv, "Fail to detach network rule at location %d. registration id = 0x%llx\n",
1585 cmd->fs.location, rule->id);
1586 goto out;
1587 }
1588 rule->id = 0;
1589 memset(&rule->flow_spec, 0, sizeof(struct ethtool_rx_flow_spec));
1590 list_del(&rule->list);
1591 out:
1592 return err;
1593
1594 }
1595
1596 static int mlx4_en_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
1597 int loc)
1598 {
1599 int err = 0;
1600 struct ethtool_flow_id *rule;
1601 struct mlx4_en_priv *priv = netdev_priv(dev);
1602
1603 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
1604 return -EINVAL;
1605
1606 rule = &priv->ethtool_rules[loc];
1607 if (rule->id)
1608 memcpy(&cmd->fs, &rule->flow_spec,
1609 sizeof(struct ethtool_rx_flow_spec));
1610 else
1611 err = -ENOENT;
1612
1613 return err;
1614 }
1615
1616 static int mlx4_en_get_num_flows(struct mlx4_en_priv *priv)
1617 {
1618
1619 int i, res = 0;
1620 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
1621 if (priv->ethtool_rules[i].id)
1622 res++;
1623 }
1624 return res;
1625
1626 }
1627
1628 static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1629 u32 *rule_locs)
1630 {
1631 struct mlx4_en_priv *priv = netdev_priv(dev);
1632 struct mlx4_en_dev *mdev = priv->mdev;
1633 int err = 0;
1634 int i = 0, priority = 0;
1635
1636 if ((cmd->cmd == ETHTOOL_GRXCLSRLCNT ||
1637 cmd->cmd == ETHTOOL_GRXCLSRULE ||
1638 cmd->cmd == ETHTOOL_GRXCLSRLALL) &&
1639 (mdev->dev->caps.steering_mode !=
1640 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up))
1641 return -EINVAL;
1642
1643 switch (cmd->cmd) {
1644 case ETHTOOL_GRXRINGS:
1645 cmd->data = priv->rx_ring_num;
1646 break;
1647 case ETHTOOL_GRXCLSRLCNT:
1648 cmd->rule_cnt = mlx4_en_get_num_flows(priv);
1649 break;
1650 case ETHTOOL_GRXCLSRULE:
1651 err = mlx4_en_get_flow(dev, cmd, cmd->fs.location);
1652 break;
1653 case ETHTOOL_GRXCLSRLALL:
1654 while ((!err || err == -ENOENT) && priority < cmd->rule_cnt) {
1655 err = mlx4_en_get_flow(dev, cmd, i);
1656 if (!err)
1657 rule_locs[priority++] = i;
1658 i++;
1659 }
1660 err = 0;
1661 break;
1662 default:
1663 err = -EOPNOTSUPP;
1664 break;
1665 }
1666
1667 return err;
1668 }
1669
1670 static int mlx4_en_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1671 {
1672 int err = 0;
1673 struct mlx4_en_priv *priv = netdev_priv(dev);
1674 struct mlx4_en_dev *mdev = priv->mdev;
1675
1676 if (mdev->dev->caps.steering_mode !=
1677 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up)
1678 return -EINVAL;
1679
1680 switch (cmd->cmd) {
1681 case ETHTOOL_SRXCLSRLINS:
1682 err = mlx4_en_flow_replace(dev, cmd);
1683 break;
1684 case ETHTOOL_SRXCLSRLDEL:
1685 err = mlx4_en_flow_detach(dev, cmd);
1686 break;
1687 default:
1688 en_warn(priv, "Unsupported ethtool command. (%d)\n", cmd->cmd);
1689 return -EINVAL;
1690 }
1691
1692 return err;
1693 }
1694
1695 static void mlx4_en_get_channels(struct net_device *dev,
1696 struct ethtool_channels *channel)
1697 {
1698 struct mlx4_en_priv *priv = netdev_priv(dev);
1699
1700 memset(channel, 0, sizeof(*channel));
1701
1702 channel->max_rx = MAX_RX_RINGS;
1703 channel->max_tx = MLX4_EN_MAX_TX_RING_P_UP;
1704
1705 channel->rx_count = priv->rx_ring_num;
1706 channel->tx_count = priv->tx_ring_num / MLX4_EN_NUM_UP;
1707 }
1708
1709 static int mlx4_en_set_channels(struct net_device *dev,
1710 struct ethtool_channels *channel)
1711 {
1712 struct mlx4_en_priv *priv = netdev_priv(dev);
1713 struct mlx4_en_dev *mdev = priv->mdev;
1714 int port_up = 0;
1715 int err = 0;
1716
1717 if (channel->other_count || channel->combined_count ||
1718 channel->tx_count > MLX4_EN_MAX_TX_RING_P_UP ||
1719 channel->rx_count > MAX_RX_RINGS ||
1720 !channel->tx_count || !channel->rx_count)
1721 return -EINVAL;
1722
1723 mutex_lock(&mdev->state_lock);
1724 if (priv->port_up) {
1725 port_up = 1;
1726 mlx4_en_stop_port(dev, 1);
1727 }
1728
1729 mlx4_en_free_resources(priv);
1730
1731 priv->num_tx_rings_p_up = channel->tx_count;
1732 priv->tx_ring_num = channel->tx_count * MLX4_EN_NUM_UP;
1733 priv->rx_ring_num = channel->rx_count;
1734
1735 err = mlx4_en_alloc_resources(priv);
1736 if (err) {
1737 en_err(priv, "Failed reallocating port resources\n");
1738 goto out;
1739 }
1740
1741 netif_set_real_num_tx_queues(dev, priv->tx_ring_num);
1742 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
1743
1744 if (dev->num_tc)
1745 mlx4_en_setup_tc(dev, MLX4_EN_NUM_UP);
1746
1747 en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num);
1748 en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num);
1749
1750 if (port_up) {
1751 err = mlx4_en_start_port(dev);
1752 if (err)
1753 en_err(priv, "Failed starting port\n");
1754 }
1755
1756 err = mlx4_en_moderation_update(priv);
1757
1758 out:
1759 mutex_unlock(&mdev->state_lock);
1760 return err;
1761 }
1762
1763 static int mlx4_en_get_ts_info(struct net_device *dev,
1764 struct ethtool_ts_info *info)
1765 {
1766 struct mlx4_en_priv *priv = netdev_priv(dev);
1767 struct mlx4_en_dev *mdev = priv->mdev;
1768 int ret;
1769
1770 ret = ethtool_op_get_ts_info(dev, info);
1771 if (ret)
1772 return ret;
1773
1774 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1775 info->so_timestamping |=
1776 SOF_TIMESTAMPING_TX_HARDWARE |
1777 SOF_TIMESTAMPING_RX_HARDWARE |
1778 SOF_TIMESTAMPING_RAW_HARDWARE;
1779
1780 info->tx_types =
1781 (1 << HWTSTAMP_TX_OFF) |
1782 (1 << HWTSTAMP_TX_ON);
1783
1784 info->rx_filters =
1785 (1 << HWTSTAMP_FILTER_NONE) |
1786 (1 << HWTSTAMP_FILTER_ALL);
1787
1788 if (mdev->ptp_clock)
1789 info->phc_index = ptp_clock_index(mdev->ptp_clock);
1790 }
1791
1792 return ret;
1793 }
1794
1795 static int mlx4_en_set_priv_flags(struct net_device *dev, u32 flags)
1796 {
1797 struct mlx4_en_priv *priv = netdev_priv(dev);
1798 struct mlx4_en_dev *mdev = priv->mdev;
1799 bool bf_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1800 bool bf_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1801 bool phv_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_PHV);
1802 bool phv_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_PHV);
1803 int i;
1804 int ret = 0;
1805
1806 if (bf_enabled_new != bf_enabled_old) {
1807 if (bf_enabled_new) {
1808 bool bf_supported = true;
1809
1810 for (i = 0; i < priv->tx_ring_num; i++)
1811 bf_supported &= priv->tx_ring[i]->bf_alloced;
1812
1813 if (!bf_supported) {
1814 en_err(priv, "BlueFlame is not supported\n");
1815 return -EINVAL;
1816 }
1817
1818 priv->pflags |= MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1819 } else {
1820 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1821 }
1822
1823 for (i = 0; i < priv->tx_ring_num; i++)
1824 priv->tx_ring[i]->bf_enabled = bf_enabled_new;
1825
1826 en_info(priv, "BlueFlame %s\n",
1827 bf_enabled_new ? "Enabled" : "Disabled");
1828 }
1829
1830 if (phv_enabled_new != phv_enabled_old) {
1831 ret = set_phv_bit(mdev->dev, priv->port, (int)phv_enabled_new);
1832 if (ret)
1833 return ret;
1834 else if (phv_enabled_new)
1835 priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV;
1836 else
1837 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_PHV;
1838 en_info(priv, "PHV bit %s\n",
1839 phv_enabled_new ? "Enabled" : "Disabled");
1840 }
1841 return 0;
1842 }
1843
1844 static u32 mlx4_en_get_priv_flags(struct net_device *dev)
1845 {
1846 struct mlx4_en_priv *priv = netdev_priv(dev);
1847
1848 return priv->pflags;
1849 }
1850
1851 static int mlx4_en_get_tunable(struct net_device *dev,
1852 const struct ethtool_tunable *tuna,
1853 void *data)
1854 {
1855 const struct mlx4_en_priv *priv = netdev_priv(dev);
1856 int ret = 0;
1857
1858 switch (tuna->id) {
1859 case ETHTOOL_TX_COPYBREAK:
1860 *(u32 *)data = priv->prof->inline_thold;
1861 break;
1862 default:
1863 ret = -EINVAL;
1864 break;
1865 }
1866
1867 return ret;
1868 }
1869
1870 static int mlx4_en_set_tunable(struct net_device *dev,
1871 const struct ethtool_tunable *tuna,
1872 const void *data)
1873 {
1874 struct mlx4_en_priv *priv = netdev_priv(dev);
1875 int val, ret = 0;
1876
1877 switch (tuna->id) {
1878 case ETHTOOL_TX_COPYBREAK:
1879 val = *(u32 *)data;
1880 if (val < MIN_PKT_LEN || val > MAX_INLINE)
1881 ret = -EINVAL;
1882 else
1883 priv->prof->inline_thold = val;
1884 break;
1885 default:
1886 ret = -EINVAL;
1887 break;
1888 }
1889
1890 return ret;
1891 }
1892
1893 static int mlx4_en_get_module_info(struct net_device *dev,
1894 struct ethtool_modinfo *modinfo)
1895 {
1896 struct mlx4_en_priv *priv = netdev_priv(dev);
1897 struct mlx4_en_dev *mdev = priv->mdev;
1898 int ret;
1899 u8 data[4];
1900
1901 /* Read first 2 bytes to get Module & REV ID */
1902 ret = mlx4_get_module_info(mdev->dev, priv->port,
1903 0/*offset*/, 2/*size*/, data);
1904 if (ret < 2)
1905 return -EIO;
1906
1907 switch (data[0] /* identifier */) {
1908 case MLX4_MODULE_ID_QSFP:
1909 modinfo->type = ETH_MODULE_SFF_8436;
1910 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1911 break;
1912 case MLX4_MODULE_ID_QSFP_PLUS:
1913 if (data[1] >= 0x3) { /* revision id */
1914 modinfo->type = ETH_MODULE_SFF_8636;
1915 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1916 } else {
1917 modinfo->type = ETH_MODULE_SFF_8436;
1918 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1919 }
1920 break;
1921 case MLX4_MODULE_ID_QSFP28:
1922 modinfo->type = ETH_MODULE_SFF_8636;
1923 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1924 break;
1925 case MLX4_MODULE_ID_SFP:
1926 modinfo->type = ETH_MODULE_SFF_8472;
1927 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1928 break;
1929 default:
1930 return -ENOSYS;
1931 }
1932
1933 return 0;
1934 }
1935
1936 static int mlx4_en_get_module_eeprom(struct net_device *dev,
1937 struct ethtool_eeprom *ee,
1938 u8 *data)
1939 {
1940 struct mlx4_en_priv *priv = netdev_priv(dev);
1941 struct mlx4_en_dev *mdev = priv->mdev;
1942 int offset = ee->offset;
1943 int i = 0, ret;
1944
1945 if (ee->len == 0)
1946 return -EINVAL;
1947
1948 memset(data, 0, ee->len);
1949
1950 while (i < ee->len) {
1951 en_dbg(DRV, priv,
1952 "mlx4_get_module_info i(%d) offset(%d) len(%d)\n",
1953 i, offset, ee->len - i);
1954
1955 ret = mlx4_get_module_info(mdev->dev, priv->port,
1956 offset, ee->len - i, data + i);
1957
1958 if (!ret) /* Done reading */
1959 return 0;
1960
1961 if (ret < 0) {
1962 en_err(priv,
1963 "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n",
1964 i, offset, ee->len - i, ret);
1965 return 0;
1966 }
1967
1968 i += ret;
1969 offset += ret;
1970 }
1971 return 0;
1972 }
1973
1974 static int mlx4_en_set_phys_id(struct net_device *dev,
1975 enum ethtool_phys_id_state state)
1976 {
1977 int err;
1978 u16 beacon_duration;
1979 struct mlx4_en_priv *priv = netdev_priv(dev);
1980 struct mlx4_en_dev *mdev = priv->mdev;
1981
1982 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_BEACON))
1983 return -EOPNOTSUPP;
1984
1985 switch (state) {
1986 case ETHTOOL_ID_ACTIVE:
1987 beacon_duration = PORT_BEACON_MAX_LIMIT;
1988 break;
1989 case ETHTOOL_ID_INACTIVE:
1990 beacon_duration = 0;
1991 break;
1992 default:
1993 return -EOPNOTSUPP;
1994 }
1995
1996 err = mlx4_SET_PORT_BEACON(mdev->dev, priv->port, beacon_duration);
1997 return err;
1998 }
1999
2000 const struct ethtool_ops mlx4_en_ethtool_ops = {
2001 .get_drvinfo = mlx4_en_get_drvinfo,
2002 .get_link_ksettings = mlx4_en_get_link_ksettings,
2003 .set_link_ksettings = mlx4_en_set_link_ksettings,
2004 .get_link = ethtool_op_get_link,
2005 .get_strings = mlx4_en_get_strings,
2006 .get_sset_count = mlx4_en_get_sset_count,
2007 .get_ethtool_stats = mlx4_en_get_ethtool_stats,
2008 .self_test = mlx4_en_self_test,
2009 .set_phys_id = mlx4_en_set_phys_id,
2010 .get_wol = mlx4_en_get_wol,
2011 .set_wol = mlx4_en_set_wol,
2012 .get_msglevel = mlx4_en_get_msglevel,
2013 .set_msglevel = mlx4_en_set_msglevel,
2014 .get_coalesce = mlx4_en_get_coalesce,
2015 .set_coalesce = mlx4_en_set_coalesce,
2016 .get_pauseparam = mlx4_en_get_pauseparam,
2017 .set_pauseparam = mlx4_en_set_pauseparam,
2018 .get_ringparam = mlx4_en_get_ringparam,
2019 .set_ringparam = mlx4_en_set_ringparam,
2020 .get_rxnfc = mlx4_en_get_rxnfc,
2021 .set_rxnfc = mlx4_en_set_rxnfc,
2022 .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size,
2023 .get_rxfh_key_size = mlx4_en_get_rxfh_key_size,
2024 .get_rxfh = mlx4_en_get_rxfh,
2025 .set_rxfh = mlx4_en_set_rxfh,
2026 .get_channels = mlx4_en_get_channels,
2027 .set_channels = mlx4_en_set_channels,
2028 .get_ts_info = mlx4_en_get_ts_info,
2029 .set_priv_flags = mlx4_en_set_priv_flags,
2030 .get_priv_flags = mlx4_en_get_priv_flags,
2031 .get_tunable = mlx4_en_get_tunable,
2032 .set_tunable = mlx4_en_set_tunable,
2033 .get_module_info = mlx4_en_get_module_info,
2034 .get_module_eeprom = mlx4_en_get_module_eeprom
2035 };
2036
2037
2038
2039
2040
Linux kernel - Deliverables
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